├── COPYING ├── README.md ├── test ├── Makefile ├── firmware.ld ├── main.c └── oocd.cfg ├── ws2812.c ├── ws2812.h └── ws2812_config.h /COPYING: -------------------------------------------------------------------------------- 1 | GNU AFFERO GENERAL PUBLIC LICENSE 2 | Version 3, 19 November 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU Affero General Public License is a free, copyleft license for 11 | software and other kinds of works, specifically designed to ensure 12 | cooperation with the community in the case of network server software. 13 | 14 | The licenses for most software and other practical works are designed 15 | to take away your freedom to share and change the works. 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It is safest 628 | to attach them to the start of each source file to most effectively 629 | state the exclusion of warranty; and each file should have at least 630 | the "copyright" line and a pointer to where the full notice is found. 631 | 632 | 633 | Copyright (C) 634 | 635 | This program is free software: you can redistribute it and/or modify 636 | it under the terms of the GNU Affero General Public License as published by 637 | the Free Software Foundation, either version 3 of the License, or 638 | (at your option) any later version. 639 | 640 | This program is distributed in the hope that it will be useful, 641 | but WITHOUT ANY WARRANTY; without even the implied warranty of 642 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 643 | GNU Affero General Public License for more details. 644 | 645 | You should have received a copy of the GNU Affero General Public License 646 | along with this program. If not, see . 647 | 648 | Also add information on how to contact you by electronic and paper mail. 649 | 650 | If your software can interact with users remotely through a computer 651 | network, you should also make sure that it provides a way for users to 652 | get its source. For example, if your program is a web application, its 653 | interface could display a "Source" link that leads users to an archive 654 | of the code. There are many ways you could offer source, and different 655 | solutions will be better for different programs; see section 13 for the 656 | specific requirements. 657 | 658 | You should also get your employer (if you work as a programmer) or school, 659 | if any, to sign a "copyright disclaimer" for the program, if necessary. 660 | For more information on this, and how to apply and follow the GNU AGPL, see 661 | . 662 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | A simple library to write data to chains of WS2812 based RGB LEDs from a 2 | STM32F1 series microcontroller. 3 | 4 | Output to any pin through variable methods depending on which pin is desired. 5 | All methods make use of DMA and interrupts to preserve timing while consuming 6 | (relatively) few processor cycles. 7 | 8 | Requirements 9 | ============ 10 | 11 | A working arm-none-eabi gcc. Use https://github.com/esden/summon-arm-toolchain 12 | to make it easy. 13 | 14 | In general there should be no other interrupts run at less than priority 16 15 | while the output is in progress so that the timing requirements are maintained. 16 | All methods require a dedicated (while operating) timer. 17 | 18 | Output Methods 19 | ============= 20 | 21 | There are three available output methods. The first and the lightest on 22 | system resources (both DMA channels and cycle usage) can output to any timer 23 | CC output included the inverted ones. The second can output to any single 24 | GPIO pin. The third can output to a whole or half of a GPIO port controlling 25 | 8 or 16 chains in parallel. 26 | 27 | Timer PWM Mode 28 | -------------- 29 | 30 | This mode can output to any timer CC output. It functions by doing continuous 31 | DMA to the timer's CCR register updating the half buffer at the transfer 32 | complete and half transfer interrupts. This allows it to maintain the timing 33 | with only a single DMA channel, determined by the timer in use. The buffer 34 | space is configurable with more buffer space freeing more processor cycles. 35 | 36 | Single GPIO Mode 37 | ---------------- 38 | 39 | This mode can output to any single pin. In normal mode both the high and low 40 | bytes of the port are controlled but this can be set to only change the desired 41 | pin at the cost of doubling the required buffer space. This mode uses three 42 | DMA channels (to set, lower on 0 bits and lower on 1 bits) determined by the 43 | timer selected. Most timers have multiple options for the DMA channels but 44 | three unique ones must be chosen. Because of the larger DMA requirements this 45 | mode uses more cycles than the PWM mode. The buffer space is configurable 46 | with more buffer space freeing more processor cycles. 47 | 48 | Multiple Parallel GPIO Mode 49 | --------------------------- 50 | 51 | This mode can output to all pins of a GPIO port. In normal mode th high 52 | and low halves of the port are set to the same while in wide mode all 16 are 53 | controlled independently. Each byte or half-word controls one bit of the 54 | output chain. This mode uses three DMA channels (to set, lower on 0 bits 55 | and lower on 1 bits) determined by the timer selected. Most timers have 56 | multiple options for the DMA channels but three unique ones must be chosen. 57 | No buffer space is required. 58 | -------------------------------------------------------------------------------- /test/Makefile: -------------------------------------------------------------------------------- 1 | # Derived from libopencm3 Makefiles 2 | 3 | OBJS = main.o ws2812.o 4 | BINARY = firmware 5 | 6 | DISTCC ?= $(shell which distcc) 7 | PREFIX ?= arm-none-eabi 8 | CC = $(DISTCC) $(PREFIX)-gcc 9 | LD = $(PREFIX)-gcc 10 | OBJCOPY = $(PREFIX)-objcopy 11 | OBJDUMP = $(PREFIX)-objdump 12 | SIZE = $(PREFIX)-size 13 | CFLAGS += --std=gnu99 -Os -g -Wall -Wextra -DSTM32F1 -I.. -I. \ 14 | -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD 15 | LDSCRIPT = $(BINARY).ld 16 | LDFLAGS += -lc -lnosys -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ 17 | -mcpu=cortex-m3 -msoft-float 18 | 19 | OOCD ?= openocd 20 | OOCD_INTERFACE ?= jlink 21 | 22 | # Be silent per default, but 'make V=1' will show all compiler calls. 23 | ifneq ($(V),1) 24 | Q := @ 25 | NULL := 2>/dev/null 26 | else 27 | LDFLAGS += -Wl,--print-gc-sections 28 | endif 29 | 30 | .SUFFIXES: .elf .bin .hex .srec .list .images 31 | .SECONDEXPANSION: 32 | .SECONDARY: 33 | 34 | all: images 35 | 36 | images: $(BINARY).images 37 | flash: $(BINARY).flash 38 | 39 | %.images: %.bin %.hex %.srec %.list 40 | @echo "*** $* images generated ***" 41 | $(Q)$(SIZE) $(*).elf 42 | 43 | %.bin: %.elf 44 | @printf " OBJCOPY $(*).bin\n" 45 | $(Q)$(OBJCOPY) -Obinary $(*).elf $(*).bin 46 | 47 | %.hex: %.elf 48 | @printf " OBJCOPY $(*).hex\n" 49 | $(Q)$(OBJCOPY) -Oihex $(*).elf $(*).hex 50 | 51 | %.srec: %.elf 52 | @printf " OBJCOPY $(*).srec\n" 53 | $(Q)$(OBJCOPY) -Osrec $(*).elf $(*).srec 54 | 55 | %.list: %.elf 56 | @printf " OBJDUMP $(*).list\n" 57 | $(Q)$(OBJDUMP) -S $(*).elf > $(*).list 58 | 59 | %.elf: $(OBJS) $(LDSCRIPT) 60 | @printf " LD $(subst $(shell pwd)/,,$(@))\n" 61 | $(Q)$(LD) -o $(*).elf $(OBJS) -lopencm3_stm32f1 $(LDFLAGS) 62 | 63 | %.o: %.c Makefile 64 | @printf " CC $(subst $(shell pwd)/,,$(@))\n" 65 | $(Q)$(CC) $(CFLAGS) -o $@ -c $< 66 | 67 | %.o: ../%.c Makefile 68 | @printf " CC $(subst $(shell pwd)/,,$(@))\n" 69 | $(Q)$(CC) $(CFLAGS) -o $@ -c $< 70 | 71 | clean: 72 | $(Q)rm -f *.o 73 | $(Q)rm -f *.d 74 | $(Q)rm -f *.elf 75 | $(Q)rm -f *.bin 76 | $(Q)rm -f *.hex 77 | $(Q)rm -f *.srec 78 | $(Q)rm -f *.list 79 | 80 | ifeq ($(OOCD_SERIAL),) 81 | %.flash: %.hex 82 | @printf " FLASH $<\n" 83 | @# IMPORTANT: Don't use "resume", only "reset" will work correctly! 84 | $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ 85 | -f oocd.cfg \ 86 | -c "init" -c "reset init" \ 87 | -c "stm32x mass_erase 0" \ 88 | -c "flash write_image $(*).hex" \ 89 | -c "reset" \ 90 | -c "shutdown" $(NULL) 91 | else 92 | %.flash: %.hex 93 | @printf " FLASH $<\n" 94 | @# IMPORTANT: Don't use "resume", only "reset" will work correctly! 95 | $(Q)$(OOCD) -f interface/$(OOCD_INTERFACE).cfg \ 96 | -f oocd.cfg \ 97 | -c "ft2232_serial $(OOCD_SERIAL)" \ 98 | -c "init" -c "reset init" \ 99 | -c "stm32x mass_erase 0" \ 100 | -c "flash write_image $(*).hex" \ 101 | -c "reset" \ 102 | -c "shutdown" $(NULL) 103 | endif 104 | 105 | .PHONY: images clean daemon 106 | 107 | -include $(OBJS:.o=.d) 108 | 109 | -------------------------------------------------------------------------------- /test/firmware.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2014 Derek Hageman 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program. If not, see . 16 | */ 17 | 18 | /* Derived from the libopencm3 linking scripts 19 | * (C) Uwe Hermann 20 | */ 21 | 22 | 23 | /* Define memory regions. */ 24 | MEMORY 25 | { 26 | rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K 27 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4k 28 | } 29 | 30 | /* Include the common ld script. */ 31 | INCLUDE libopencm3_stm32f1.ld 32 | -------------------------------------------------------------------------------- /test/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2014 Derek Hageman 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program. If not, see . 16 | */ 17 | 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | 25 | #include "ws2812.h" 26 | #include "ws2812_config.h" 27 | 28 | #define N_LEDS 16 29 | 30 | #if 1 31 | static const uint8_t outputColors[8*3] = { 32 | /* G R B */ 33 | 0x00, 0xFF, 0x00, 34 | 0xFF, 0xFF, 0x00, 35 | 0xFF, 0x00, 0x00, 36 | 0xFF, 0x00, 0xFF, 37 | 0x00, 0x00, 0xFF, 38 | 0x00, 0xFF, 0xFF, 39 | 0xFF, 0xFF, 0xFF, 40 | 0x00, 0x00, 0x00, 41 | }; 42 | #else 43 | static const uint8_t outputColors[8*3] = { 44 | /* G R B */ 45 | 0x00, 0x00, 0x00, 46 | 0x00, 0x20, 0x00, 47 | 0x00, 0x40, 0x00, 48 | 0x00, 0x80, 0x00, 49 | 0x00, 0xA0, 0x00, 50 | 0x00, 0xC0, 0x00, 51 | 0x00, 0xE0, 0x00, 52 | 0x00, 0xFF, 0x00, 53 | }; 54 | #endif 55 | 56 | 57 | volatile uint32_t systick; 58 | void sys_tick_handler(void) { 59 | systick++; 60 | } 61 | 62 | static uint32_t wrapU32(uint32_t start, uint32_t now) 63 | { 64 | if (now < start) 65 | return 0xFFFFFFFF - start + now + 1; 66 | return now - start; 67 | } 68 | 69 | static void outputPercent(uint32_t n, int decimals) 70 | { 71 | uint32_t div = 100; 72 | for (int i=0; i 0) { 79 | usart_send_blocking(USART1, '.'); 80 | for (int i=0; i elapsedCycles) 201 | availableCyles = elapsedCycles; 202 | elapsedCycles /= 1000; 203 | availableCyles /= elapsedCycles; 204 | 205 | outputString("Estimated available CPU: "); 206 | outputPercent(availableCyles, 1); 207 | outputString(" %\r\n"); 208 | 209 | 210 | uint32_t begin = systick; 211 | while (wrapU32(begin, systick) < 1000) { } 212 | } 213 | 214 | return 0; 215 | } 216 | -------------------------------------------------------------------------------- /test/oocd.cfg: -------------------------------------------------------------------------------- 1 | set WORKAREASIZE 0x2000 2 | 3 | #source [find target/stm32f1x.cfg] 4 | source [find target/stm32.cfg] 5 | 6 | jtag_khz 100 7 | 8 | #reset_config srst_only 9 | #adapter_nsrst_assert_width 100 10 | #adapter_nsrst_delay 100 11 | -------------------------------------------------------------------------------- /ws2812.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2014 Derek Hageman 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU Affero General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program. If not, see . 16 | */ 17 | 18 | #include 19 | #include 20 | 21 | #include 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | 28 | #include "ws2812.h" 29 | #include "ws2812_config.h" 30 | 31 | /* 32 | * PWM Mode: 33 | * This mode works by transfering a new value to the output compare register 34 | * for the selected output at every update event. The value transferred comes 35 | * from a buffer of outputs that define the duty cycle for the bits it covers. 36 | * So each time the timer completes a cycle the DMA clocks in the next duty 37 | * cycle (the shadow register means this is actually one behind the one that's 38 | * currently being evaluated). 39 | * 40 | * GPIO Modes: 41 | * These modes work by setting up three DMA transfers. The first sets 42 | * the output(s) to high defining the rising edge of the clock. The second 43 | * sets the output(s) low if the bit is zero at T0H. The third sets the 44 | * output(s) low regardless at T1H (no effect if they're already low). A single 45 | * timer is used for all threee DMA transfers. The first DMA (set high) occurs 46 | * at the update event if in use or a CCR set equal to the maximum otherwise. 47 | * The other two CCRs are set to the fractions of the clock cycle to give T0H 48 | * and T1H. For single GPIO mode two intermediate buffers are used that 49 | * contain the values to be sent to the RSR for the GPIO, the other two are 50 | * from static 32-bit locations setting the bits in BSRR. 51 | * 52 | * In PWM mode and single GPIO mode, the DMA buffer is split in half refilled 53 | * by an interrupt once that half completes. The transfer itself is a circular 54 | * one with interrupts at the half and complete for the refilling. For 55 | * GPIO multiple mode, only a single long DMA transfer is needed. 56 | */ 57 | 58 | #ifndef CLOCK 59 | #define CLOCK 800000 60 | #endif 61 | #ifndef T0H 62 | #define T0H 0.32 63 | #endif 64 | #ifndef T1H 65 | #define T1H 0.64 66 | #endif 67 | #ifndef TRESET 68 | #define TRESET 50E-6 69 | #endif 70 | 71 | #if defined(PWM_MODE) 72 | #if defined(GPIO_MODE) || defined(MULTI_MODE) 73 | #error Only one mode can be selected 74 | #endif 75 | #if !defined(BUFFER_SIZE) || BUFFER_SIZE <= 0 || BUFFER_SIZE % 8 != 0 76 | #error Buffer size must be a multiple of 8 77 | #endif 78 | #if !defined(OUTPUT) || OUTPUT < 0 || OUTPUT > 4 79 | #error Invalid timer output 80 | #endif 81 | #elif defined(GPIO_MODE) 82 | #if defined(MULTI_MODE) 83 | #error Only one mode can be selected 84 | #endif 85 | #if !defined(BUFFER_SIZE) || BUFFER_SIZE <= 0 || BUFFER_SIZE % 8 != 0 86 | #error Buffer size must be a multiple of 8 87 | #endif 88 | #elif defined(MULTI_MODE) 89 | 90 | #else 91 | #error Must select an output mode 92 | #endif 93 | 94 | static volatile enum { 95 | Uninitialized = 0, 96 | ResetBlank, 97 | Idle, 98 | SendingData, 99 | } state = Uninitialized; 100 | 101 | extern u32 rcc_ppre1_frequency; 102 | extern u32 rcc_ppre2_frequency; 103 | 104 | static uint8_t timerPeriod(void); 105 | static uint8_t timerZeroHigh(void); 106 | static uint8_t timerOneHigh(void); 107 | static uint16_t timerResetPeriod(void); 108 | static uint32_t timerInputFrequency(void); 109 | static void setOutputsLow(void); 110 | #if (TIMER) == 1 111 | #define USE_TIMER_DIER TIM_DIER(TIM1) 112 | static uint32_t timerInputFrequency(void) 113 | { 114 | return rcc_ppre2_frequency; 115 | } 116 | static void timerInitialize(void) 117 | { 118 | rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); 119 | rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST); 120 | rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST); 121 | TIM_CR1(TIM1) = 0; 122 | TIM_SR(TIM1) = 0; 123 | 124 | nvic_clear_pending_irq(NVIC_TIM1_UP_IRQ); 125 | nvic_enable_irq(NVIC_TIM1_UP_IRQ); 126 | nvic_set_priority(NVIC_TIM1_UP_IRQ, 0); 127 | 128 | TIM_CR2(TIM1) = 0; 129 | TIM_RCR(TIM1) = 0; 130 | TIM_BDTR(TIM1) = TIM_BDTR_MOE; 131 | TIM_PSC(TIM1) = 0; 132 | USE_TIMER_DIER = 0; 133 | } 134 | static void timerStartMain(void) 135 | { 136 | TIM_CR1(TIM1) = 0; 137 | TIM_ARR(TIM1) = (uint16_t)timerPeriod() - 1; 138 | TIM_CNT(TIM1) = 0; 139 | TIM_SR(TIM1) = 0; 140 | TIM_CR1(TIM1) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 141 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 142 | } 143 | static void timerStartReset(void) 144 | { 145 | state = ResetBlank; 146 | TIM_CR1(TIM1) = 0; 147 | TIM_ARR(TIM1) = (uint16_t)timerResetPeriod(); 148 | TIM_CNT(TIM1) = 0; 149 | setOutputsLow(); 150 | TIM_EGR(TIM1) = TIM_EGR_UG; 151 | TIM_SR(TIM1) = 0; 152 | USE_TIMER_DIER = TIM_DIER_UIE; 153 | TIM_CR1(TIM1) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 154 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 155 | } 156 | void tim1_up_isr(void) 157 | { 158 | TIM_CR1(TIM1) = 0; 159 | USE_TIMER_DIER = 0; 160 | TIM_SR(TIM1) = 0; 161 | state = Idle; 162 | } 163 | #elif (TIMER) == 2 164 | #define USE_TIMER_DIER TIM_DIER(TIM2) 165 | static uint32_t timerInputFrequency(void) 166 | { 167 | return rcc_ppre1_frequency; 168 | } 169 | static void timerInitialize(void) 170 | { 171 | rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN); 172 | rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST); 173 | rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST); 174 | TIM_CR1(TIM2) = 0; 175 | TIM_SR(TIM2) = 0; 176 | 177 | nvic_clear_pending_irq(NVIC_TIM2_IRQ); 178 | nvic_enable_irq(NVIC_TIM2_IRQ); 179 | nvic_set_priority(NVIC_TIM2_IRQ, 0); 180 | 181 | TIM_CR2(TIM2) = 0; 182 | TIM_PSC(TIM2) = 0; 183 | } 184 | static void timerStartMain(void) 185 | { 186 | TIM_CR1(TIM2) = 0; 187 | TIM_ARR(TIM2) = (uint16_t)timerPeriod() - 1; 188 | TIM_CNT(TIM2) = 0; 189 | TIM_SR(TIM2) = 0; 190 | TIM_CR1(TIM2) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 191 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 192 | } 193 | static void timerStartReset(void) 194 | { 195 | state = ResetBlank; 196 | TIM_CR1(TIM2) = 0; 197 | TIM_ARR(TIM2) = (uint16_t)timerResetPeriod(); 198 | TIM_CNT(TIM2) = 0; 199 | setOutputsLow(); 200 | TIM_EGR(TIM2) = TIM_EGR_UG; 201 | TIM_SR(TIM2) = 0; 202 | USE_TIMER_DIER = TIM_DIER_UIE; 203 | TIM_CR1(TIM2) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 204 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 205 | } 206 | void tim2_isr(void) 207 | { 208 | TIM_CR1(TIM2) = 0; 209 | USE_TIMER_DIER = 0; 210 | TIM_SR(TIM2) = 0; 211 | state = Idle; 212 | } 213 | #elif (TIMER) == 3 214 | #define USE_TIMER_DIER TIM_DIER(TIM3) 215 | static uint32_t timerInputFrequency(void) 216 | { 217 | return rcc_ppre1_frequency; 218 | } 219 | static void timerInitialize(void) 220 | { 221 | rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN); 222 | rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST); 223 | rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST); 224 | TIM_CR1(TIM3) = 0; 225 | TIM_SR(TIM3) = 0; 226 | 227 | nvic_clear_pending_irq(NVIC_TIM3_IRQ); 228 | nvic_enable_irq(NVIC_TIM3_IRQ); 229 | nvic_set_priority(NVIC_TIM3_IRQ, 0); 230 | 231 | TIM_CR2(TIM3) = 0; 232 | TIM_PSC(TIM3) = 0; 233 | } 234 | static void timerStartMain(void) 235 | { 236 | TIM_CR1(TIM3) = 0; 237 | TIM_ARR(TIM3) = (uint16_t)timerPeriod() - 1; 238 | TIM_CNT(TIM3) = 0; 239 | TIM_SR(TIM3) = 0; 240 | TIM_CR1(TIM3) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 241 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 242 | } 243 | static void timerStartReset(void) 244 | { 245 | state = ResetBlank; 246 | TIM_CR1(TIM3) = 0; 247 | TIM_ARR(TIM3) = (uint16_t)timerResetPeriod(); 248 | TIM_CNT(TIM3) = 0; 249 | setOutputsLow(); 250 | TIM_EGR(TIM3) = TIM_EGR_UG; 251 | TIM_SR(TIM3) = 0; 252 | USE_TIMER_DIER = TIM_DIER_UIE; 253 | TIM_CR1(TIM3) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 254 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 255 | } 256 | void tim3_isr(void) 257 | { 258 | TIM_CR1(TIM3) = 0; 259 | USE_TIMER_DIER = 0; 260 | TIM_SR(TIM3) = 0; 261 | state = Idle; 262 | } 263 | #elif (TIMER) == 4 264 | #define USE_TIMER_DIER TIM_DIER(TIM4) 265 | static uint32_t timerInputFrequency(void) 266 | { 267 | return rcc_ppre1_frequency; 268 | } 269 | static void timerInitialize(void) 270 | { 271 | rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM4EN); 272 | rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST); 273 | rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST); 274 | TIM_CR1(TIM4) = 0; 275 | TIM_SR(TIM4) = 0; 276 | 277 | nvic_clear_pending_irq(NVIC_TIM4_IRQ); 278 | nvic_enable_irq(NVIC_TIM4_IRQ); 279 | nvic_set_priority(NVIC_TIM4_IRQ, 0); 280 | 281 | TIM_CR2(TIM4) = 0; 282 | TIM_PSC(TIM4) = 0; 283 | } 284 | static void timerStartMain(void) 285 | { 286 | TIM_CR1(TIM4) = 0; 287 | TIM_ARR(TIM4) = (uint16_t)timerPeriod() - 1; 288 | TIM_CNT(TIM4) = 0; 289 | TIM_SR(TIM4) = 0; 290 | TIM_CR1(TIM4) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 291 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 292 | } 293 | static void timerStartReset(void) 294 | { 295 | TIM_CR1(TIM4) = 0; 296 | TIM_ARR(TIM4) = (uint16_t)timerResetPeriod(); 297 | TIM_CNT(TIM4) = 0; 298 | setOutputsLow(); 299 | TIM_EGR(TIM4) = TIM_EGR_UG; 300 | TIM_SR(TIM4) = 0; 301 | USE_TIMER_DIER = TIM_DIER_UIE; 302 | TIM_CR1(TIM4) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 303 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 304 | } 305 | void tim4_isr(void) 306 | { 307 | TIM_CR1(TIM4) = 0; 308 | USE_TIMER_DIER = 0; 309 | TIM_SR(TIM4) = 0; 310 | dmaDisable(); 311 | state = Idle; 312 | } 313 | #elif (TIMER) == 5 314 | #define USE_TIMER_DIER TIM_DIER(TIM5) 315 | static uint32_t timerInputFrequency(void) 316 | { 317 | return rcc_ppre1_frequency; 318 | } 319 | static void timerInitialize(void) 320 | { 321 | rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM5EN); 322 | rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST); 323 | rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST); 324 | TIM_CR1(TIM5) = 0; 325 | TIM_SR(TIM5) = 0; 326 | 327 | nvic_clear_pending_irq(NVIC_TIM5_IRQ); 328 | nvic_enable_irq(NVIC_TIM5_IRQ); 329 | nvic_set_priority(NVIC_TIM5_IRQ, 0); 330 | 331 | TIM_CR2(TIM5) = 0; 332 | TIM_PSC(TIM5) = 0; 333 | } 334 | static void timerStartMain(void) 335 | { 336 | TIM_CR1(TIM5) = 0; 337 | TIM_ARR(TIM5) = (uint16_t)timerPeriod() - 1; 338 | TIM_CNT(TIM5) = 0; 339 | TIM_SR(TIM5) = 0; 340 | TIM_CR1(TIM5) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 341 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 342 | } 343 | static void timerStartReset(void) 344 | { 345 | state = ResetBlank; 346 | TIM_CR1(TIM5) = 0; 347 | TIM_ARR(TIM5) = (uint16_t)timerResetPeriod(); 348 | TIM_CNT(TIM5) = 0; 349 | setOutputsLow(); 350 | TIM_EGR(TIM5) = TIM_EGR_UG; 351 | TIM_SR(TIM5) = 0; 352 | USE_TIMER_DIER = TIM_DIER_UIE; 353 | TIM_CR1(TIM5) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 354 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 355 | } 356 | void tim5_isr(void) 357 | { 358 | TIM_CR1(TIM5) = 0; 359 | USE_TIMER_DIER = 0; 360 | TIM_SR(TIM5) = 0; 361 | state = Idle; 362 | } 363 | #elif (TIMER) == 8 364 | #define USE_TIMER_DIER TIM_DIER(TIM8) 365 | static uint32_t timerInputFrequency(void) 366 | { 367 | return rcc_ppre2_frequency; 368 | } 369 | static void timerInitialize(void) 370 | { 371 | rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM8EN); 372 | rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST); 373 | rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST); 374 | TIM_CR1(TIM8) = 0; 375 | TIM_SR(TIM8) = 0; 376 | 377 | nvic_clear_pending_irq(NVIC_TIM8_UP_IRQ); 378 | nvic_enable_irq(NVIC_TIM8_UP_IRQ); 379 | nvic_set_priority(NVIC_TIM8_UP_IRQ, 0); 380 | 381 | TIM_CR2(TIM8) = 0; 382 | TIM_RCR(TIM8) = 0; 383 | TIM_BDTR(TIM8) = TIM_BDTR_MOE; 384 | TIM_PSC(TIM8) = 0; 385 | } 386 | static void timerStartMain(void) 387 | { 388 | TIM_CR1(TIM8) = 0; 389 | TIM_ARR(TIM8) = (uint16_t)timerPeriod() - 1; 390 | TIM_CNT(TIM8) = 0; 391 | TIM_SR(TIM8) = 0; 392 | TIM_CR1(TIM8) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 393 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 394 | } 395 | static void timerStartReset(void) 396 | { 397 | state = ResetBlank; 398 | TIM_CR1(TIM8) = 0; 399 | TIM_ARR(TIM8) = (uint16_t)timerResetPeriod(); 400 | TIM_CNT(TIM8) = 0; 401 | setOutputsLow(); 402 | TIM_EGR(TIM8) = TIM_EGR_UG; 403 | TIM_SR(TIM8) = 0; 404 | USE_TIMER_DIER = TIM_DIER_UIE; 405 | TIM_CR1(TIM8) = TIM_CR1_CKD_CK_INT | TIM_CR1_CMS_EDGE | 406 | TIM_CR1_DIR_UP | TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN; 407 | } 408 | void tim8_up_isr(void) 409 | { 410 | TIM_CR1(TIM8) = 0; 411 | USE_TIMER_DIER = 0; 412 | TIM_SR(TIM8) = 0; 413 | state = Idle; 414 | } 415 | #else 416 | #error Unsupported timer 417 | #endif 418 | static uint8_t timerPeriod(void) 419 | { 420 | return (uint16_t)((timerInputFrequency() + (uint32_t)((CLOCK)/2)) / 421 | (uint32_t)(CLOCK)); 422 | } 423 | static uint8_t timerZeroHigh(void) 424 | { 425 | uint32_t high = (uint32_t)((T0H) * (CLOCK) + 0.5); 426 | return (uint8_t)((high * (uint32_t)timerPeriod() + (uint32_t)((CLOCK)/2)) / 427 | (uint32_t)(CLOCK)); 428 | } 429 | static uint8_t timerOneHigh(void) 430 | { 431 | uint32_t high = (uint32_t)((T1H) * (CLOCK) + 0.5); 432 | return (uint8_t)((high * (uint32_t)timerPeriod() + 433 | (uint32_t)((CLOCK)/2)) / (uint32_t)(CLOCK)); 434 | } 435 | static uint16_t timerResetPeriod(void) 436 | { 437 | return (uint16_t)(timerInputFrequency() / 438 | (uint32_t)(1.0/(TRESET) + 0.5)) + 2; 439 | } 440 | 441 | #if defined(PWM_MODE) || defined(GPIO_MODE) 442 | static bool bufferHalf; 443 | static const uint8_t *sendBegin; 444 | static const uint8_t *sendEnd; 445 | 446 | #if defined(PWM_MODE) || !defined(GPIOANY_STRICT) 447 | static uint8_t dmaBuffer[(BUFFER_SIZE)]; 448 | static void fillNextBuffer(uint8_t high, uint8_t low) 449 | { 450 | uint8_t *target; 451 | if (bufferHalf) { 452 | target = &dmaBuffer[(BUFFER_SIZE)/2]; 453 | } else { 454 | target = &dmaBuffer[0]; 455 | } 456 | bufferHalf = !bufferHalf; 457 | for (int total = 0; total < (BUFFER_SIZE)/(8*2) && 458 | sendBegin != sendEnd; ++sendBegin, ++total) { 459 | uint8_t source = *sendBegin; 460 | for (int bit=0; bit<8; bit++, source <<= 1, ++target) { 461 | if (source & 0x80) { 462 | *target = high; 463 | } else { 464 | *target = low; 465 | } 466 | } 467 | } 468 | } 469 | #else 470 | static uint16_t dmaBuffer[(BUFFER_SIZE)]; 471 | static void fillNextBuffer(void) 472 | { 473 | uint16_t *target; 474 | if (bufferHalf) { 475 | target = &dmaBuffer[(BUFFER_SIZE)/2]; 476 | } else { 477 | target = &dmaBuffer[0]; 478 | } 479 | bufferHalf = !bufferHalf; 480 | for (int total = 0; total < (BUFFER_SIZE)/(8*2) && 481 | sendBegin != sendEnd; ++sendBegin, ++total) { 482 | uint8_t source = *sendBegin; 483 | for (int bit=0; bit<8; bit++, source <<= 1, ++target) { 484 | if (source & 0x80) { 485 | *target = 0; 486 | } else { 487 | *target = 1 << (OUTPUT); 488 | } 489 | } 490 | } 491 | } 492 | #endif 493 | 494 | #if defined(GPIO_MODE) 495 | #if !defined(GPIOANY_STRICT) 496 | static const uint32_t outputHigh = (1 << (OUTPUT)) | 497 | (1 << (((OUTPUT)+8)%16)); 498 | static const uint32_t outputLow = (1 << ((OUTPUT)+16)) | 499 | (1 << (((OUTPUT)+8)%16+16)); 500 | #else 501 | static const uint32_t outputHigh = 1 << (OUTPUT); 502 | static const uint32_t outputLow = 1 << ((OUTPUT) + 16); 503 | #endif 504 | #endif 505 | #endif 506 | 507 | 508 | #if defined(PWM_MODE) 509 | /* This is circular, memory incrementing transfer to peripheral (8->16 bit 510 | * pads the high order bits with zeros, which we want), with interrupts 511 | * at the half and end of the cycle (we refill the half that just 512 | * completed). */ 513 | #define DMA_CCR_WRITE_UP (DMA_CCR_PL_HIGH | DMA_CCR_MSIZE_8BIT | \ 514 | DMA_CCR_PSIZE_16BIT | DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_DIR | \ 515 | DMA_CCR_TCIE | DMA_CCR_HTIE | DMA_CCR_EN) 516 | 517 | #if (OUTPUT) == 1 518 | #define USE_TIMER_CCMRV (TIM_CCMR1_OC1M_PWM1 | TIM_CCMR1_OC1PE) 519 | #if defined(OUTPUT_INVERT) && ((TIMER) == 1 || (TIMER) == 8) 520 | #define USE_TIMER_CCERV (TIM_CCER_CC1NE) 521 | #else 522 | #define USE_TIMER_CCERV (TIM_CCER_CC1E) 523 | #endif 524 | #elif (OUTPUT) == 2 525 | #define USE_TIMER_CCMRV (TIM_CCMR1_OC2M_PWM1 | TIM_CCMR1_OC2PE) 526 | #if defined(OUTPUT_INVERT) && ((TIMER) == 1 || (TIMER) == 8) 527 | #define USE_TIMER_CCERV (TIM_CCER_CC1NE) 528 | #else 529 | #define USE_TIMER_CCERV (TIM_CCER_CC2E) 530 | #endif 531 | #elif (OUTPUT) == 3 532 | #define USE_TIMER_CCMRV (TIM_CCMR2_OC3M_PWM1 | TIM_CCMR2_OC3PE) 533 | #if defined(OUTPUT_INVERT) && ((TIMER) == 1 || (TIMER) == 8) 534 | #define USE_TIMER_CCERV (TIM_CCER_CC3NE) 535 | #else 536 | #define USE_TIMER_CCERV (TIM_CCER_CC3E) 537 | #endif 538 | #elif (OUTPUT) == 4 539 | #define USE_TIMER_CCMRV (TIM_CCMR2_OC4M_PWM1 | TIM_CCMR2_OC4PE) 540 | #if defined(OUTPUT_INVERT) && ((TIMER) == 1 || (TIMER) == 8) 541 | #define USE_TIMER_CCERV (TIM_CCER_CC3NE) 542 | #else 543 | #define USE_TIMER_CCERV (TIM_CCER_CC4E) 544 | #endif 545 | #else 546 | #error Invalid output 547 | #endif 548 | 549 | #if (TIMER) == 1 550 | #define USE_DMA_IFCR DMA_IFCR(DMA1) 551 | #define USE_DMA_CCR DMA_CCR(DMA1, DMA_CHANNEL5) 552 | #define USE_DMA_CGIF DMA_IFCR_CGIF(DMA_CHANNEL5) 553 | #define DMA_IRQ_NAME dma1_channel5_isr 554 | 555 | #if OUTPUT == 1 556 | #define USE_TIMER_CCR TIM_CCR1(TIM1) 557 | #define USE_TIMER_CCMR TIM_CCMR1(TIM1) 558 | #elif OUTPUT == 2 559 | #define USE_TIMER_CCR TIM_CCR2(TIM1) 560 | #define USE_TIMER_CCMR TIM_CCMR1(TIM1) 561 | #elif OUTPUT == 3 562 | #define USE_TIMER_CCR TIM_CCR3(TIM1) 563 | #define USE_TIMER_CCMR TIM_CCMR2(TIM1) 564 | #elif OUTPUT == 4 565 | #define USE_TIMER_CCR TIM_CCR4(TIM1) 566 | #define USE_TIMER_CCMR TIM_CCMR2(TIM1) 567 | #endif 568 | 569 | static void dmaInitialize(void) 570 | { 571 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); 572 | 573 | TIM_CCER(TIM1) = USE_TIMER_CCERV; 574 | USE_TIMER_CCMR = USE_TIMER_CCMRV; 575 | 576 | USE_DMA_CCR = 0; 577 | DMA_CNDTR(DMA1, DMA_CHANNEL5) = BUFFER_SIZE; 578 | DMA_CPAR(DMA1, DMA_CHANNEL5) = (uint32_t)(&USE_TIMER_CCR); 579 | DMA_CMAR(DMA1, DMA_CHANNEL5) = (uint32_t)(&dmaBuffer[0]); 580 | USE_DMA_IFCR = USE_DMA_CGIF; 581 | 582 | nvic_clear_pending_irq(NVIC_DMA1_CHANNEL5_IRQ); 583 | nvic_enable_irq(NVIC_DMA1_CHANNEL5_IRQ); 584 | nvic_set_priority(NVIC_DMA1_CHANNEL5_IRQ, 0); 585 | } 586 | #elif (TIMER) == 2 587 | #define USE_DMA_IFCR DMA_IFCR(DMA1) 588 | #define USE_DMA_CCR DMA_CCR(DMA1, DMA_CHANNEL2) 589 | #define USE_DMA_CGIF DMA_IFCR_CGIF(DMA_CHANNEL2) 590 | #define DMA_IRQ_NAME dma1_channel2_isr 591 | 592 | #if OUTPUT == 1 593 | #define USE_TIMER_CCR TIM_CCR1(TIM2) 594 | #define USE_TIMER_CCMR TIM_CCMR1(TIM2) 595 | #elif OUTPUT == 2 596 | #define USE_TIMER_CCR TIM_CCR2(TIM2) 597 | #define USE_TIMER_CCMR TIM_CCMR1(TIM2) 598 | #elif OUTPUT == 3 599 | #define USE_TIMER_CCR TIM_CCR3(TIM2) 600 | #define USE_TIMER_CCMR TIM_CCMR2(TIM2) 601 | #elif OUTPUT == 4 602 | #define USE_TIMER_CCR TIM_CCR4(TIM2) 603 | #define USE_TIMER_CCMR TIM_CCMR2(TIM2) 604 | #endif 605 | 606 | static void dmaInitialize(void) 607 | { 608 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); 609 | 610 | TIM_CCER(TIM2) = USE_TIMER_CCERV; 611 | USE_TIMER_CCMR = USE_TIMER_CCMRV; 612 | 613 | USE_DMA_CCR = 0; 614 | DMA_CNDTR(DMA1, DMA_CHANNEL2) = BUFFER_SIZE; 615 | DMA_CPAR(DMA1, DMA_CHANNEL2) = (uint32_t)(&USE_TIMER_CCR); 616 | DMA_CMAR(DMA1, DMA_CHANNEL2) = (uint32_t)(&dmaBuffer[0]); 617 | USE_DMA_IFCR = USE_DMA_CGIF; 618 | 619 | nvic_clear_pending_irq(NVIC_DMA1_CHANNEL2_IRQ); 620 | nvic_enable_irq(NVIC_DMA1_CHANNEL2_IRQ); 621 | nvic_set_priority(NVIC_DMA1_CHANNEL2_IRQ, 0); 622 | } 623 | #elif (TIMER) == 3 624 | #define USE_DMA_IFCR DMA_IFCR(DMA1) 625 | #define USE_DMA_CCR DMA_CCR(DMA1, DMA_CHANNEL3) 626 | #define USE_DMA_CGIF DMA_IFCR_CGIF(DMA_CHANNEL3) 627 | #define DMA_IRQ_NAME dma1_channel3_isr 628 | 629 | #if OUTPUT == 1 630 | #define USE_TIMER_CCR TIM_CCR1(TIM3) 631 | #define USE_TIMER_CCMR TIM_CCMR1(TIM3) 632 | #elif OUTPUT == 2 633 | #define USE_TIMER_CCR TIM_CCR2(TIM3) 634 | #define USE_TIMER_CCMR TIM_CCMR1(TIM3) 635 | #elif OUTPUT == 3 636 | #define USE_TIMER_CCR TIM_CCR3(TIM3) 637 | #define USE_TIMER_CCMR TIM_CCMR2(TIM3) 638 | #elif OUTPUT == 4 639 | #define USE_TIMER_CCR TIM_CCR4(TIM3) 640 | #define USE_TIMER_CCMR TIM_CCMR2(TIM3) 641 | #endif 642 | 643 | static void dmaInitialize(void) 644 | { 645 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); 646 | 647 | TIM_CCER(TIM3) = USE_TIMER_CCERV; 648 | USE_TIMER_CCMR = USE_TIMER_CCMRV; 649 | 650 | USE_DMA_CCR = 0; 651 | DMA_CNDTR(DMA1, DMA_CHANNEL3) = BUFFER_SIZE; 652 | DMA_CPAR(DMA1, DMA_CHANNEL3) = (uint32_t)(&USE_TIMER_CCR); 653 | DMA_CMAR(DMA1, DMA_CHANNEL3) = (uint32_t)(&dmaBuffer[0]); 654 | USE_DMA_IFCR = USE_DMA_CGIF; 655 | 656 | nvic_clear_pending_irq(NVIC_DMA1_CHANNEL3_IRQ); 657 | nvic_enable_irq(NVIC_DMA1_CHANNEL3_IRQ); 658 | nvic_set_priority(NVIC_DMA1_CHANNEL3_IRQ, 0); 659 | } 660 | #elif (TIMER) == 4 661 | #define USE_DMA_IFCR DMA_IFCR(DMA1) 662 | #define USE_DMA_CCR DMA_CCR(DMA1, DMA_CHANNEL7) 663 | #define USE_DMA_CGIF DMA_IFCR_CGIF(DMA_CHANNEL7) 664 | #define DMA_IRQ_NAME dma1_channel7_isr 665 | 666 | #if OUTPUT == 1 667 | #define USE_TIMER_CCR TIM_CCR1(TIM4) 668 | #define USE_TIMER_CCMR TIM_CCMR1(TIM4) 669 | #elif OUTPUT == 2 670 | #define USE_TIMER_CCR TIM_CCR2(TIM4) 671 | #define USE_TIMER_CCMR TIM_CCMR1(TIM4) 672 | #elif OUTPUT == 3 673 | #define USE_TIMER_CCR TIM_CCR3(TIM4) 674 | #define USE_TIMER_CCMR TIM_CCMR2(TIM4) 675 | #elif OUTPUT == 4 676 | #define USE_TIMER_CCR TIM_CCR4(TIM4) 677 | #define USE_TIMER_CCMR TIM_CCMR2(TIM4) 678 | #endif 679 | 680 | static void dmaInitialize(void) 681 | { 682 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); 683 | 684 | TIM_CCER(TIM4) = USE_TIMER_CCERV; 685 | USE_TIMER_CCMR = USE_TIMER_CCMRV; 686 | 687 | USE_DMA_CCR = 0; 688 | DMA_CNDTR(DMA1, DMA_CHANNEL7) = BUFFER_SIZE; 689 | DMA_CPAR(DMA1, DMA_CHANNEL7) = (uint32_t)(&USE_TIMER_CCR); 690 | DMA_CMAR(DMA1, DMA_CHANNEL7) = (uint32_t)(&dmaBuffer[0]); 691 | USE_DMA_IFCR = USE_DMA_CGIF; 692 | 693 | nvic_clear_pending_irq(NVIC_DMA1_CHANNEL7_IRQ); 694 | nvic_enable_irq(NVIC_DMA1_CHANNEL7_IRQ); 695 | nvic_set_priority(NVIC_DMA1_CHANNEL7_IRQ, 0); 696 | } 697 | #elif (TIMER) == 5 698 | #define USE_DMA_IFCR DMA_IFCR(DMA2) 699 | #define USE_DMA_CCR DMA_CCR(DMA2, DMA_CHANNEL2) 700 | #define USE_DMA_CGIF DMA_IFCR_CGIF(DMA_CHANNEL2) 701 | #define DMA_IRQ_NAME dma2_channel2_isr 702 | 703 | #if OUTPUT == 1 704 | #define USE_TIMER_CCR TIM_CCR1(TIM5) 705 | #define USE_TIMER_CCMR TIM_CCMR1(TIM5) 706 | #elif OUTPUT == 2 707 | #define USE_TIMER_CCR TIM_CCR2(TIM5) 708 | #define USE_TIMER_CCMR TIM_CCMR1(TIM5) 709 | #elif OUTPUT == 3 710 | #define USE_TIMER_CCR TIM_CCR3(TIM5) 711 | #define USE_TIMER_CCMR TIM_CCMR2(TIM5) 712 | #elif OUTPUT == 4 713 | #define USE_TIMER_CCR TIM_CCR4(TIM5) 714 | #define USE_TIMER_CCMR TIM_CCMR2(TIM5) 715 | #endif 716 | 717 | static void dmaInitialize(void) 718 | { 719 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA2EN); 720 | 721 | TIM_CCER(TIM5) = USE_TIMER_CCERV; 722 | USE_TIMER_CCMR = USE_TIMER_CCMRV; 723 | 724 | USE_DMA_CCR = 0; 725 | DMA_CNDTR(DMA2, DMA_CHANNEL2) = BUFFER_SIZE; 726 | DMA_CPAR(DMA2, DMA_CHANNEL2) = (uint32_t)(&USE_TIMER_CCR); 727 | DMA_CMAR(DMA2, DMA_CHANNEL2) = (uint32_t)(&dmaBuffer[0]); 728 | USE_DMA_IFCR = USE_DMA_CGIF; 729 | 730 | nvic_clear_pending_irq(NVIC_DMA2_CHANNEL2_IRQ); 731 | nvic_enable_irq(NVIC_DMA2_CHANNEL2_IRQ); 732 | nvic_set_priority(NVIC_DMA2_CHANNEL2_IRQ, 0); 733 | } 734 | #elif (TIMER) == 8 735 | #define USE_DMA_IFCR DMA_IFCR(DMA2) 736 | #define USE_DMA_CCR DMA_CCR(DMA2, DMA_CHANNEL1) 737 | #define USE_DMA_CGIF DMA_IFCR_CGIF(DMA_CHANNEL1) 738 | #define DMA_IRQ_NAME dma2_channel1_isr 739 | 740 | #if OUTPUT == 1 741 | #define USE_TIMER_CCR TIM_CCR1(TIM8) 742 | #define USE_TIMER_CCMR TIM_CCMR1(TIM8) 743 | #elif OUTPUT == 2 744 | #define USE_TIMER_CCR TIM_CCR2(TIM8) 745 | #define USE_TIMER_CCMR TIM_CCMR1(TIM8) 746 | #elif OUTPUT == 3 747 | #define USE_TIMER_CCR TIM_CCR3(TIM8) 748 | #define USE_TIMER_CCMR TIM_CCMR2(TIM8) 749 | #elif OUTPUT == 4 750 | #define USE_TIMER_CCR TIM_CCR4(TIM8) 751 | #define USE_TIMER_CCMR TIM_CCMR2(TIM8) 752 | #endif 753 | 754 | static void dmaInitialize(void) 755 | { 756 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA2EN); 757 | 758 | TIM_CCER(TIM8) = USE_TIMER_CCERV; 759 | USE_TIMER_CCMR = USE_TIMER_CCMRV; 760 | 761 | USE_DMA_CCR = 0; 762 | DMA_CNDTR(DMA2, DMA_CHANNEL1) = BUFFER_SIZE; 763 | DMA_CPAR(DMA2, DMA_CHANNEL1) = (uint32_t)(&USE_TIMER_CCR); 764 | DMA_CMAR(DMA2, DMA_CHANNEL1) = (uint32_t)(&dmaBuffer[0]); 765 | USE_DMA_IFCR = USE_DMA_CGIF; 766 | 767 | nvic_clear_pending_irq(NVIC_DMA2_CHANNEL1_IRQ); 768 | nvic_enable_irq(NVIC_DMA2_CHANNEL1_IRQ); 769 | nvic_set_priority(NVIC_DMA2_CHANNEL1_IRQ, 0); 770 | } 771 | #else 772 | #error Unsupported timer 773 | #endif 774 | 775 | static void setOutputsLow(void) 776 | { 777 | USE_TIMER_CCR = 0; 778 | } 779 | static void dmaDisable(void) 780 | { 781 | USE_DMA_CCR = 0; 782 | setOutputsLow(); 783 | } 784 | static void modeInitialize(const void *data, uint16_t length) 785 | { 786 | /* Initialize both buffers and start a send (the request won't 787 | * actually come in until the timer is started). */ 788 | sendBegin = (const uint8_t *)data; 789 | sendEnd = sendBegin + length; 790 | bufferHalf = false; 791 | fillNextBuffer(timerOneHigh(), timerZeroHigh()); 792 | fillNextBuffer(timerOneHigh(), timerZeroHigh()); 793 | 794 | /* Enable the DMA request at the update event */ 795 | USE_DMA_CCR = DMA_CCR_WRITE_UP; 796 | USE_TIMER_DIER = TIM_DIER_UDE; 797 | 798 | /* This means that output won't be updated until the second 799 | * clock cycle (since the DMA request won't come in until the 800 | * update at the end of the first, and the register itself won't 801 | * take the shadow value until the one after that). This is fine, 802 | * however, as we just hold it low and this gives us plenty of 803 | * time to finish up handling. */ 804 | USE_TIMER_CCR = 0; 805 | } 806 | #endif 807 | 808 | #ifdef MULTI_MODE 809 | static const uint32_t outputHigh = 0x000FFFF; 810 | static const uint32_t outputLow = 0xFFFF0000; 811 | #endif 812 | 813 | #if defined(GPIO_MODE) || defined(MULTI_MODE) 814 | /* This is circular in-place contentious transfer to a peripheral with 815 | * the full word write. That is, this just writes the memory word every 816 | * DMA request and does nothing else. */ 817 | #define DMA_CCR_WRITE_FIXED (DMA_CCR_PL_HIGH | DMA_CCR_MSIZE_32BIT | \ 818 | DMA_CCR_PSIZE_32BIT | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_EN) 819 | 820 | /* We rely on the fact that if both set and reset are set in 821 | * BSRR then set takes priority. So the fact that the DMA 822 | * will duplicate the data lines (BSRR is word access only) still 823 | * works. For non-strict DMA mode, the same is true for BRR, we just 824 | * write zeros when we're on a high bit (so no action taken). */ 825 | #if defined(GPIO_MODE) 826 | #if !defined(GPIO_STRICT) 827 | #define DMA_WRITE_TL_MODE (DMA_CCR_MSIZE_8BIT | \ 828 | DMA_CCR_PSIZE_8BIT | DMA_CCR_HTIE) 829 | #else 830 | #define DMA_WRITE_TL_MODE (DMA_CCR_MSIZE_16BIT | \ 831 | DMA_CCR_PSIZE_16BIT | DMA_CCR_HTIE) 832 | #endif 833 | #elif defined(MULTI_MODE) 834 | #if !defined(MUTLI_WIDE) 835 | #define DMA_WRITE_TL_MODE (DMA_CCR_MSIZE_8BIT | \ 836 | DMA_CCR_PSIZE_8BIT) 837 | #else 838 | #define DMA_WRITE_TL_MODE (DMA_CCR_MSIZE_16BIT | \ 839 | DMA_CCR_PSIZE_16BIT) 840 | #endif 841 | #endif 842 | 843 | /* This is circular, memory incrementing transfer to peripheral. For 844 | * GPIO mode there are interrupts at the half and end of the transfer that 845 | * we use to refill the half that just completed. For multiple out mode 846 | * there's only an interrupt at the end, which just starts our reset 847 | * time. */ 848 | #define DMA_CCR_WRITE_TL (DMA_CCR_PL_HIGH | DMA_WRITE_TL_MODE | \ 849 | DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_TCIE | \ 850 | DMA_CCR_EN) 851 | 852 | 853 | #if (TIMER) == 1 854 | #if (DMAC1) == (DMAC2) || (DMAC2) == (DMAC3) || (DMAC3) == (DMAC1) 855 | #error Three different DMA channels must be selected 856 | #endif 857 | #if (DMAC1) != 2 && (DMAC1) != 3 && (DMAC1) != 4 && (DMAC1) != 5 && \ 858 | (DMAC1) != 6 859 | #error DMA selection 1 does not belong to timer 1 860 | #endif 861 | #if (DMAC2) != 2 && (DMAC2) != 3 && (DMAC2) != 4 && (DMAC2) != 5 && \ 862 | (DMAC2) != 6 863 | #error DMA selection 2 does not belong to timer 1 864 | #endif 865 | #if (DMAC3) != 2 && (DMAC3) != 3 && (DMAC3) != 4 && (DMAC3) != 5 && \ 866 | (DMAC3) != 6 867 | #error DMA selection 3 does not belong to timer 1 868 | #endif 869 | 870 | #if (DMAC1) == 5 871 | #define SET_DMA_CHANNEL DMA_CHANNEL5 872 | #define SET_TIMER_DMA TIM_DIER_UDE 873 | #undef SET_TIMER_CCR 874 | #undef DMACSET 875 | #define DMACUSE DMAC2 876 | #define DMACCLR DMAC3 877 | #elif (DMAC2) == 5 878 | #define SET_DMA_CHANNEL DMA_CHANNEL5 879 | #define SET_TIMER_DMA TIM_DIER_UDE 880 | #undef SET_TIMER_CCR 881 | #undef DMACSET 882 | #define DMACUSE DMAC1 883 | #define DMACCLR DMAC3 884 | #elif (DMAC3) == 5 885 | #define SET_DMA_CHANNEL DMA_CHANNEL5 886 | #define SET_TIMER_DMA TIM_DIER_UDE 887 | #undef SET_TIMER_CCR 888 | #undef DMACSET 889 | #define DMACUSE DMAC1 890 | #define DMACCLR DMAC2 891 | #else 892 | #define DMACSET DMAC1 893 | #define DMACUSE DMAC2 894 | #define DMACCLR DMAC3 895 | #endif 896 | 897 | #if defined(DMACSET) 898 | #if (DMACSET) == 2 899 | #define SET_DMA_CHANNEL DMA_CHANNEL2 900 | #define SET_TIMER_CCR TIM_CCR1(TIM1) 901 | #define SET_TIMER_DMA TIM_DIER_CC1DE 902 | #elif (DMACSET) == 3 903 | #define SET_DMA_CHANNEL DMA_CHANNEL3 904 | #define SET_TIMER_CCR TIM_CCR2(TIM1) 905 | #define SET_TIMER_DMA TIM_DIER_CC2DE 906 | #elif (DMACSET) == 4 907 | #define SET_DMA_CHANNEL DMA_CHANNEL4 908 | #define SET_TIMER_CCR TIM_CCR4(TIM1) 909 | #define SET_TIMER_DMA TIM_DIER_CC4DE 910 | #elif (DMACSET) == 6 911 | #define SET_DMA_CHANNEL DMA_CHANNEL6 912 | #define SET_TIMER_CCR TIM_CCR3(TIM1) 913 | #define SET_TIMER_DMA TIM_DIER_CC3DE 914 | #else 915 | #error Invalid set DMA channel 916 | #endif 917 | #endif 918 | #if (DMACCLR) == 2 919 | #define CLR_DMA_CHANNEL DMA_CHANNEL2 920 | #define CLR_TIMER_CCR TIM_CCR1(TIM1) 921 | #define CLR_TIMER_DMA TIM_DIER_CC1DE 922 | #elif (DMACCLR) == 3 923 | #define CLR_DMA_CHANNEL DMA_CHANNEL3 924 | #define CLR_TIMER_CCR TIM_CCR2(TIM1) 925 | #define CLR_TIMER_DMA TIM_DIER_CC2DE 926 | #elif (DMACCLR) == 4 927 | #define CLR_DMA_CHANNEL DMA_CHANNEL4 928 | #define CLR_TIMER_CCR TIM_CCR4(TIM1) 929 | #define CLR_TIMER_DMA TIM_DIER_CC4DE 930 | #elif (DMACCLR) == 6 931 | #define CLR_DMA_CHANNEL DMA_CHANNEL6 932 | #define CLR_TIMER_CCR TIM_CCR3(TIM1) 933 | #define CLR_TIMER_DMA TIM_DIER_CC3DE 934 | #else 935 | #error Invalid clear DMA channel 936 | #endif 937 | #if (DMACUSE) == 2 938 | #define DMA_IRQ_NAME dma1_channel2_isr 939 | #define USE_DMA_CHANNEL DMA_CHANNEL2 940 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL2_IRQ 941 | #define USE_TIMER_CCR TIM_CCR1(TIM1) 942 | #define USE_TIMER_DMA TIM_DIER_CC1DE 943 | #elif (DMACUSE) == 3 944 | #define DMA_IRQ_NAME dma1_channel3_isr 945 | #define USE_DMA_CHANNEL DMA_CHANNEL3 946 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL3_IRQ 947 | #define USE_TIMER_CCR TIM_CCR2(TIM1) 948 | #define USE_TIMER_DMA TIM_DIER_CC2DE 949 | #elif (DMACUSE) == 4 950 | #define DMA_IRQ_NAME dma1_channel4_isr 951 | #define USE_DMA_CHANNEL DMA_CHANNEL4 952 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL4_IRQ 953 | #define USE_TIMER_CCR TIM_CCR4(TIM1) 954 | #define USE_TIMER_DMA TIM_DIER_CC4DE 955 | #elif (DMACUSE) == 6 956 | #define DMA_IRQ_NAME dma1_channel6_isr 957 | #define USE_DMA_CHANNEL DMA_CHANNEL6 958 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL6_IRQ 959 | #define USE_TIMER_CCR TIM_CCR3(TIM1) 960 | #define USE_TIMER_DMA TIM_DIER_CC3DE 961 | #else 962 | #error Invalid use DMA channel 963 | #endif 964 | 965 | #define USE_DMA_IFCR DMA_IFCR(DMA1) 966 | #define USE_DMA_CCR DMA_CCR(DMA1, USE_DMA_CHANNEL) 967 | #define USE_DMA_CNDTR DMA_CNDTR(DMA1, USE_DMA_CHANNEL) 968 | #define USE_DMA_CMAR DMA_CMAR(DMA1, USE_DMA_CHANNEL) 969 | #define USE_DMA_CGIF DMA_IFCR_CGIF(USE_DMA_CHANNEL) 970 | #define SET_DMA_CCR DMA_CCR(DMA1, SET_DMA_CHANNEL) 971 | #define CLR_DMA_CCR DMA_CCR(DMA1, CLR_DMA_CHANNEL) 972 | 973 | static void dmaInitialize(void) 974 | { 975 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); 976 | 977 | USE_DMA_CCR = 0; 978 | #if defined(GPIO_MODE) 979 | USE_DMA_CNDTR = BUFFER_SIZE; 980 | USE_DMA_CMAR = (uint32_t)(&dmaBuffer[0]); 981 | DMA_CPAR(DMA1, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_BRR(PORT)); 982 | #else 983 | DMA_CPAR(DMA1, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_ODR(PORT)); 984 | #endif 985 | USE_DMA_IFCR = USE_DMA_CGIF; 986 | 987 | DMA_CNDTR(DMA1, SET_DMA_CHANNEL) = 1; 988 | DMA_CMAR(DMA1, SET_DMA_CHANNEL) = (uint32_t)(&outputHigh); 989 | DMA_CPAR(DMA1, SET_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 990 | SET_DMA_CCR = DMA_CCR_WRITE_FIXED; 991 | 992 | DMA_CNDTR(DMA1, CLR_DMA_CHANNEL) = 1; 993 | DMA_CMAR(DMA1, CLR_DMA_CHANNEL) = (uint32_t)(&outputLow); 994 | DMA_CPAR(DMA1, CLR_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 995 | CLR_DMA_CCR = DMA_CCR_WRITE_FIXED; 996 | 997 | nvic_clear_pending_irq(USE_DMA_IRQ); 998 | nvic_enable_irq(USE_DMA_IRQ); 999 | nvic_set_priority(USE_DMA_IRQ, 0); 1000 | } 1001 | #elif (TIMER) == 2 1002 | #if (DMAC1) == (DMAC2) || (DMAC2) == (DMAC3) || (DMAC3) == (DMAC1) 1003 | #error Three different DMA channels must be selected 1004 | #endif 1005 | #if (DMAC1) != 1 && (DMAC1) != 2 && (DMAC1) != 5 && (DMAC1) != 7 1006 | #error DMA selection 1 does not belong to timer 2 1007 | #endif 1008 | #if (DMAC2) != 1 && (DMAC2) != 2 && (DMAC2) != 5 && (DMAC2) != 7 1009 | #error DMA selection 2 does not belong to timer 2 1010 | #endif 1011 | #if (DMAC3) != 1 && (DMAC3) != 2 && (DMAC3) != 5 && (DMAC3) != 7 1012 | #error DMA selection 3 does not belong to timer 2 1013 | #endif 1014 | 1015 | #if (DMAC1) == 2 1016 | #define SET_DMA_CHANNEL DMA_CHANNEL2 1017 | #define SET_TIMER_DMA TIM_DIER_UDE 1018 | #undef SET_TIMER_CCR 1019 | #undef DMACSET 1020 | #define DMACUSE DMAC2 1021 | #define DMACCLR DMAC3 1022 | #elif (DMAC2) == 2 1023 | #define SET_DMA_CHANNEL DMA_CHANNEL2 1024 | #define SET_TIMER_DMA TIM_DIER_UDE 1025 | #undef SET_TIMER_CCR 1026 | #undef DMACSET 1027 | #define DMACUSE DMAC1 1028 | #define DMACCLR DMAC3 1029 | #elif (DMAC3) == 2 1030 | #define SET_DMA_CHANNEL DMA_CHANNEL2 1031 | #define SET_TIMER_DMA TIM_DIER_UDE 1032 | #undef SET_TIMER_CCR 1033 | #undef DMACSET 1034 | #define DMACUSE DMAC1 1035 | #define DMACCLR DMAC2 1036 | #else 1037 | #define DMACSET DMAC1 1038 | #define DMACUSE DMAC2 1039 | #define DMACCLR DMAC3 1040 | #endif 1041 | 1042 | #if defined(DMACSET) 1043 | #if (DMACSET) == 1 1044 | #define SET_DMA_CHANNEL DMA_CHANNEL1 1045 | #define SET_TIMER_CCR TIM_CCR3(TIM2) 1046 | #define SET_TIMER_DMA TIM_DIER_CC3DE 1047 | #elif (DMACSET) == 5 1048 | #define SET_DMA_CHANNEL DMA_CHANNEL5 1049 | #define SET_TIMER_CCR TIM_CCR1(TIM2) 1050 | #define SET_TIMER_DMA TIM_DIER_CC1DE 1051 | #elif (DMACSET) == 7 1052 | #define SET_DMA_CHANNEL DMA_CHANNEL7 1053 | #define SET_TIMER_CCR TIM_CCR2(TIM2) 1054 | #define SET_TIMER_DMA TIM_DIER_CC2DE 1055 | #else 1056 | #error Invalid set DMA channel 1057 | #endif 1058 | #endif 1059 | #if (DMACCLR) == 1 1060 | #define CLR_DMA_CHANNEL DMA_CHANNEL1 1061 | #define CLR_TIMER_CCR TIM_CCR3(TIM2) 1062 | #define CLR_TIMER_DMA TIM_DIER_CC3DE 1063 | #elif (DMACCLR) == 5 1064 | #define CLR_DMA_CHANNEL DMA_CHANNEL5 1065 | #define CLR_TIMER_CCR TIM_CCR1(TIM2) 1066 | #define CLR_TIMER_DMA TIM_DIER_CC1DE 1067 | #elif (DMACCLR) == 7 1068 | #define CLR_DMA_CHANNEL DMA_CHANNEL7 1069 | #define CLR_TIMER_CCR TIM_CCR2(TIM2) 1070 | #define CLR_TIMER_DMA TIM_DIER_CC2DE 1071 | #else 1072 | #error Invalid clear DMA channel 1073 | #endif 1074 | #if (DMACUSE) == 1 1075 | #define DMA_IRQ_NAME dma1_channel1_isr 1076 | #define USE_DMA_CHANNEL DMA_CHANNEL1 1077 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL1_IRQ 1078 | #define USE_TIMER_CCR TIM_CCR3(TIM2) 1079 | #define USE_TIMER_DMA TIM_DIER_CC3DE 1080 | #elif (DMACUSE) == 5 1081 | #define DMA_IRQ_NAME dma1_channel5_isr 1082 | #define USE_DMA_CHANNEL DMA_CHANNEL5 1083 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL5_IRQ 1084 | #define USE_TIMER_CCR TIM_CCR1(TIM2) 1085 | #define USE_TIMER_DMA TIM_DIER_CC1DE 1086 | #elif (DMACUSE) == 7 1087 | #define DMA_IRQ_NAME dma1_channel7_isr 1088 | #define USE_DMA_CHANNEL DMA_CHANNEL7 1089 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL7_IRQ 1090 | #define USE_TIMER_CCR TIM_CCR2(TIM2) 1091 | #define USE_TIMER_DMA TIM_DIER_CC2DE 1092 | #else 1093 | #error Invalid use DMA channel 1094 | #endif 1095 | 1096 | #define USE_DMA_IFCR DMA_IFCR(DMA1) 1097 | #define USE_DMA_CCR DMA_CCR(DMA1, USE_DMA_CHANNEL) 1098 | #define USE_DMA_CNDTR DMA_CNDTR(DMA1, USE_DMA_CHANNEL) 1099 | #define USE_DMA_CMAR DMA_CMAR(DMA1, USE_DMA_CHANNEL) 1100 | #define USE_DMA_CGIF DMA_IFCR_CGIF(USE_DMA_CHANNEL) 1101 | #define SET_DMA_CCR DMA_CCR(DMA1, SET_DMA_CHANNEL) 1102 | #define CLR_DMA_CCR DMA_CCR(DMA1, CLR_DMA_CHANNEL) 1103 | 1104 | static void dmaInitialize(void) 1105 | { 1106 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); 1107 | 1108 | USE_DMA_CCR = 0; 1109 | #if defined(GPIO_MODE) 1110 | USE_DMA_CNDTR = BUFFER_SIZE; 1111 | USE_DMA_CMAR = (uint32_t)(&dmaBuffer[0]); 1112 | DMA_CPAR(DMA1, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_BRR(PORT)); 1113 | #else 1114 | DMA_CPAR(DMA1, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_ODR(PORT)); 1115 | #endif 1116 | USE_DMA_IFCR = USE_DMA_CGIF; 1117 | 1118 | DMA_CNDTR(DMA1, SET_DMA_CHANNEL) = 1; 1119 | DMA_CMAR(DMA1, SET_DMA_CHANNEL) = (uint32_t)(&outputHigh); 1120 | DMA_CPAR(DMA1, SET_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1121 | SET_DMA_CCR = DMA_CCR_WRITE_FIXED; 1122 | 1123 | DMA_CNDTR(DMA1, CLR_DMA_CHANNEL) = 1; 1124 | DMA_CMAR(DMA1, CLR_DMA_CHANNEL) = (uint32_t)(&outputLow); 1125 | DMA_CPAR(DMA1, CLR_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1126 | CLR_DMA_CCR = DMA_CCR_WRITE_FIXED; 1127 | 1128 | nvic_clear_pending_irq(USE_DMA_IRQ); 1129 | nvic_enable_irq(USE_DMA_IRQ); 1130 | nvic_set_priority(USE_DMA_IRQ, 0); 1131 | } 1132 | #elif (TIMER) == 3 1133 | #define SET_DMA_CHANNEL DMA_CHANNEL3 1134 | #define SET_TIMER_DMA TIM_DIER_UDE 1135 | #undef SET_TIMER_CCR 1136 | 1137 | #define CLR_DMA_CHANNEL DMA_CHANNEL6 1138 | #define CLR_TIMER_CCR TIM_CCR1(TIM3) 1139 | #define CLR_TIMER_DMA TIM_DIER_CC1DE 1140 | 1141 | #define DMA_IRQ_NAME dma1_channel2_isr 1142 | #define USE_DMA_CHANNEL DMA_CHANNEL2 1143 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL2_IRQ 1144 | #define USE_TIMER_CCR TIM_CCR3(TIM3) 1145 | #define USE_TIMER_DMA TIM_DIER_CC3DE 1146 | 1147 | #define USE_DMA_IFCR DMA_IFCR(DMA1) 1148 | #define USE_DMA_CCR DMA_CCR(DMA1, USE_DMA_CHANNEL) 1149 | #define USE_DMA_CNDTR DMA_CNDTR(DMA1, USE_DMA_CHANNEL) 1150 | #define USE_DMA_CMAR DMA_CMAR(DMA1, USE_DMA_CHANNEL) 1151 | #define USE_DMA_CGIF DMA_IFCR_CGIF(USE_DMA_CHANNEL) 1152 | #define SET_DMA_CCR DMA_CCR(DMA1, SET_DMA_CHANNEL) 1153 | #define CLR_DMA_CCR DMA_CCR(DMA1, CLR_DMA_CHANNEL) 1154 | 1155 | static void dmaInitialize(void) 1156 | { 1157 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); 1158 | 1159 | USE_DMA_CCR = 0; 1160 | #if defined(GPIO_MODE) 1161 | USE_DMA_CNDTR = BUFFER_SIZE; 1162 | USE_DMA_CMAR = (uint32_t)(&dmaBuffer[0]); 1163 | DMA_CPAR(DMA1, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_BRR(PORT)); 1164 | #else 1165 | DMA_CPAR(DMA1, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_ODR(PORT)); 1166 | #endif 1167 | USE_DMA_IFCR = USE_DMA_CGIF; 1168 | 1169 | DMA_CNDTR(DMA1, SET_DMA_CHANNEL) = 1; 1170 | DMA_CMAR(DMA1, SET_DMA_CHANNEL) = (uint32_t)(&outputHigh); 1171 | DMA_CPAR(DMA1, SET_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1172 | SET_DMA_CCR = DMA_CCR_WRITE_FIXED; 1173 | 1174 | DMA_CNDTR(DMA1, CLR_DMA_CHANNEL) = 1; 1175 | DMA_CMAR(DMA1, CLR_DMA_CHANNEL) = (uint32_t)(&outputLow); 1176 | DMA_CPAR(DMA1, CLR_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1177 | CLR_DMA_CCR = DMA_CCR_WRITE_FIXED; 1178 | 1179 | nvic_clear_pending_irq(USE_DMA_IRQ); 1180 | nvic_enable_irq(USE_DMA_IRQ); 1181 | nvic_set_priority(USE_DMA_IRQ, 0); 1182 | } 1183 | #elif (TIMER) == 4 1184 | #if (DMAC1) == (DMAC2) || (DMAC2) == (DMAC3) || (DMAC3) == (DMAC1) 1185 | #error Three different DMA channels must be selected 1186 | #endif 1187 | #if (DMAC1) != 1 && (DMAC1) != 4 && (DMAC1) != 5 && (DMAC1) != 7 1188 | #error DMA selection 1 does not belong to timer 4 1189 | #endif 1190 | #if (DMAC2) != 1 && (DMAC2) != 4 && (DMAC2) != 5 && (DMAC2) != 7 1191 | #error DMA selection 2 does not belong to timer 4 1192 | #endif 1193 | #if (DMAC3) != 1 && (DMAC3) != 4 && (DMAC3) != 5 && (DMAC3) != 7 1194 | #error DMA selection 3 does not belong to timer 4 1195 | #endif 1196 | 1197 | #if (DMAC1) == 7 1198 | #define SET_DMA_CHANNEL DMA_CHANNEL7 1199 | #define SET_TIMER_DMA TIM_DIER_UDE 1200 | #undef SET_TIMER_CCR 1201 | #undef DMACSET 1202 | #define DMACUSE DMAC2 1203 | #define DMACCLR DMAC3 1204 | #elif (DMAC2) == 7 1205 | #define SET_DMA_CHANNEL DMA_CHANNEL7 1206 | #define SET_TIMER_DMA TIM_DIER_UDE 1207 | #undef SET_TIMER_CCR 1208 | #undef DMACSET 1209 | #define DMACUSE DMAC1 1210 | #define DMACCLR DMAC3 1211 | #elif (DMAC3) == 7 1212 | #define SET_DMA_CHANNEL DMA_CHANNEL7 1213 | #define SET_TIMER_DMA TIM_DIER_UDE 1214 | #undef SET_TIMER_CCR 1215 | #undef DMACSET 1216 | #define DMACUSE DMAC1 1217 | #define DMACCLR DMAC2 1218 | #else 1219 | #define DMACSET DMAC1 1220 | #define DMACUSE DMAC2 1221 | #define DMACCLR DMAC3 1222 | #endif 1223 | 1224 | #if defined(DMACSET) 1225 | #if (DMACSET) == 1 1226 | #define SET_DMA_CHANNEL DMA_CHANNEL1 1227 | #define SET_TIMER_CCR TIM_CCR1(TIM4) 1228 | #define SET_TIMER_DMA TIM_DIER_CC1DE 1229 | #elif (DMACSET) == 4 1230 | #define SET_DMA_CHANNEL DMA_CHANNEL4 1231 | #define SET_TIMER_CCR TIM_CCR2(TIM4) 1232 | #define SET_TIMER_DMA TIM_DIER_CC2DE 1233 | #elif (DMACSET) == 5 1234 | #define SET_DMA_CHANNEL DMA_CHANNEL5 1235 | #define SET_TIMER_CCR TIM_CCR3(TIM4) 1236 | #define SET_TIMER_DMA TIM_DIER_CC3DE 1237 | #else 1238 | #error Invalid set DMA channel 1239 | #endif 1240 | #endif 1241 | #if (DMACCLR) == 1 1242 | #define CLR_DMA_CHANNEL DMA_CHANNEL1 1243 | #define CLR_TIMER_CCR TIM_CCR1(TIM4) 1244 | #define CLR_TIMER_DMA TIM_DIER_CC1DE 1245 | #elif (DMACCLR) == 4 1246 | #define CLR_DMA_CHANNEL DMA_CHANNEL4 1247 | #define CLR_TIMER_CCR TIM_CCR2(TIM4) 1248 | #define CLR_TIMER_DMA TIM_DIER_CC2DE 1249 | #elif (DMACCLR) == 5 1250 | #define CLR_DMA_CHANNEL DMA_CHANNEL5 1251 | #define CLR_TIMER_CCR TIM_CCR3(TIM4) 1252 | #define CLR_TIMER_DMA TIM_DIER_CC3DE 1253 | #else 1254 | #error Invalid clear DMA channel 1255 | #endif 1256 | #if (DMACUSE) == 1 1257 | #define DMA_IRQ_NAME dma1_channel1_isr 1258 | #define USE_DMA_CHANNEL DMA_CHANNEL1 1259 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL1_IRQ 1260 | #define USE_TIMER_CCR TIM_CCR1(TIM4) 1261 | #define USE_TIMER_DMA TIM_DIER_CC1DE 1262 | #elif (DMACUSE) == 4 1263 | #define DMA_IRQ_NAME dma1_channel4_isr 1264 | #define USE_DMA_CHANNEL DMA_CHANNEL4 1265 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL4_IRQ 1266 | #define USE_TIMER_CCR TIM_CCR2(TIM4) 1267 | #define USE_TIMER_DMA TIM_DIER_CC2DE 1268 | #elif (DMACUSE) == 5 1269 | #define DMA_IRQ_NAME dma1_channel5_isr 1270 | #define USE_DMA_CHANNEL DMA_CHANNEL5 1271 | #define USE_DMA_IRQ NVIC_DMA1_CHANNEL5_IRQ 1272 | #define USE_TIMER_CCR TIM_CCR3(TIM4) 1273 | #define USE_TIMER_DMA TIM_DIER_CC3DE 1274 | #else 1275 | #error Invalid use DMA channel 1276 | #endif 1277 | 1278 | #define USE_DMA_IFCR DMA_IFCR(DMA1) 1279 | #define USE_DMA_CCR DMA_CCR(DMA1, USE_DMA_CHANNEL) 1280 | #define USE_DMA_CNDTR DMA_CNDTR(DMA1, USE_DMA_CHANNEL) 1281 | #define USE_DMA_CMAR DMA_CMAR(DMA1, USE_DMA_CHANNEL) 1282 | #define USE_DMA_CGIF DMA_IFCR_CGIF(USE_DMA_CHANNEL) 1283 | #define SET_DMA_CCR DMA_CCR(DMA1, SET_DMA_CHANNEL) 1284 | #define CLR_DMA_CCR DMA_CCR(DMA1, CLR_DMA_CHANNEL) 1285 | 1286 | static void dmaInitialize(void) 1287 | { 1288 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN); 1289 | 1290 | USE_DMA_CCR = 0; 1291 | #if defined(GPIO_MODE) 1292 | USE_DMA_CNDTR = BUFFER_SIZE; 1293 | USE_DMA_CMAR = (uint32_t)(&dmaBuffer[0]); 1294 | DMA_CPAR(DMA1, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_BRR(PORT)); 1295 | #else 1296 | DMA_CPAR(DMA1, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_ODR(PORT)); 1297 | #endif 1298 | USE_DMA_IFCR = USE_DMA_CGIF; 1299 | 1300 | DMA_CNDTR(DMA1, SET_DMA_CHANNEL) = 1; 1301 | DMA_CMAR(DMA1, SET_DMA_CHANNEL) = (uint32_t)(&outputHigh); 1302 | DMA_CPAR(DMA1, SET_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1303 | SET_DMA_CCR = DMA_CCR_WRITE_FIXED; 1304 | 1305 | DMA_CNDTR(DMA1, CLR_DMA_CHANNEL) = 1; 1306 | DMA_CMAR(DMA1, CLR_DMA_CHANNEL) = (uint32_t)(&outputLow); 1307 | DMA_CPAR(DMA1, CLR_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1308 | CLR_DMA_CCR = DMA_CCR_WRITE_FIXED; 1309 | 1310 | nvic_clear_pending_irq(USE_DMA_IRQ); 1311 | nvic_enable_irq(USE_DMA_IRQ); 1312 | nvic_set_priority(USE_DMA_IRQ, 0); 1313 | } 1314 | #elif (TIMER) == 5 1315 | #if (DMAC1) == (DMAC2) || (DMAC2) == (DMAC3) || (DMAC3) == (DMAC1) 1316 | #error Three different DMA channels must be selected 1317 | #endif 1318 | #if (DMAC1) != 1 && (DMAC1) != 2 && (DMAC1) != 4 && (DMAC1) != 5 1319 | #error DMA selection 1 does not belong to timer 5 1320 | #endif 1321 | #if (DMAC2) != 1 && (DMAC2) != 2 && (DMAC2) != 4 && (DMAC2) != 5 1322 | #error DMA selection 2 does not belong to timer 5 1323 | #endif 1324 | #if (DMAC3) != 1 && (DMAC3) != 2 && (DMAC3) != 4 && (DMAC3) != 5 1325 | #error DMA selection 3 does not belong to timer 5 1326 | #endif 1327 | 1328 | #if (DMAC1) == 2 1329 | #define SET_DMA_CHANNEL DMA_CHANNEL2 1330 | #define SET_TIMER_DMA TIM_DIER_UDE 1331 | #undef SET_TIMER_CCR 1332 | #undef DMACSET 1333 | #define DMACUSE DMAC2 1334 | #define DMACCLR DMAC3 1335 | #elif (DMAC2) == 2 1336 | #define SET_DMA_CHANNEL DMA_CHANNEL2 1337 | #define SET_TIMER_DMA TIM_DIER_UDE 1338 | #undef SET_TIMER_CCR 1339 | #undef DMACSET 1340 | #define DMACUSE DMAC1 1341 | #define DMACCLR DMAC3 1342 | #elif (DMAC3) == 2 1343 | #define SET_DMA_CHANNEL DMA_CHANNEL2 1344 | #define SET_TIMER_DMA TIM_DIER_UDE 1345 | #undef SET_TIMER_CCR 1346 | #undef DMACSET 1347 | #define DMACUSE DMAC1 1348 | #define DMACCLR DMAC2 1349 | #else 1350 | #define DMACSET DMAC1 1351 | #define DMACUSE DMAC2 1352 | #define DMACCLR DMAC3 1353 | #endif 1354 | 1355 | #if defined(DMACSET) 1356 | #if (DMACSET) == 1 1357 | #define SET_DMA_CHANNEL DMA_CHANNEL1 1358 | #define SET_TIMER_CCR TIM_CCR4(TIM5) 1359 | #define SET_TIMER_DMA TIM_DIER_CC4DE 1360 | #elif (DMACSET) == 4 1361 | #define SET_DMA_CHANNEL DMA_CHANNEL4 1362 | #define SET_TIMER_CCR TIM_CCR2(TIM5) 1363 | #define SET_TIMER_DMA TIM_DIER_CC2DE 1364 | #elif (DMACSET) == 5 1365 | #define SET_DMA_CHANNEL DMA_CHANNEL5 1366 | #define SET_TIMER_CCR TIM_CCR1(TIM5) 1367 | #define SET_TIMER_DMA TIM_DIER_CC1DE 1368 | #else 1369 | #error Invalid set DMA channel 1370 | #endif 1371 | #endif 1372 | #if (DMACCLR) == 1 1373 | #define CLR_DMA_CHANNEL DMA_CHANNEL1 1374 | #define CLR_TIMER_CCR TIM_CCR4(TIM5) 1375 | #define CLR_TIMER_DMA TIM_DIER_CC4DE 1376 | #elif (DMACCLR) == 4 1377 | #define CLR_DMA_CHANNEL DMA_CHANNEL4 1378 | #define CLR_TIMER_CCR TIM_CCR2(TIM5) 1379 | #define CLR_TIMER_DMA TIM_DIER_CC2DE 1380 | #elif (DMACCLR) == 5 1381 | #define CLR_DMA_CHANNEL DMA_CHANNEL5 1382 | #define CLR_TIMER_CCR TIM_CCR1(TIM5) 1383 | #define CLR_TIMER_DMA TIM_DIER_CC1DE 1384 | #else 1385 | #error Invalid clear DMA channel 1386 | #endif 1387 | #if (DMACUSE) == 1 1388 | #define DMA_IRQ_NAME dma1_channel1_isr 1389 | #define USE_DMA_CHANNEL DMA_CHANNEL1 1390 | #define USE_DMA_IRQ NVIC_DMA2_CHANNEL1_IRQ 1391 | #define USE_TIMER_CCR TIM_CCR4(TIM5) 1392 | #define USE_TIMER_DMA TIM_DIER_CC4DE 1393 | #elif (DMACUSE) == 4 1394 | #define DMA_IRQ_NAME dma1_channel4_5_isr 1395 | #define USE_DMA_CHANNEL DMA_CHANNEL4 1396 | #define USE_DMA_IRQ NVIC_DMA2_CHANNEL4_5_IRQ 1397 | #define USE_TIMER_CCR TIM_CCR2(TIM5) 1398 | #define USE_TIMER_DMA TIM_DIER_CC2DE 1399 | #elif (DMACUSE) == 5 1400 | #define DMA_IRQ_NAME dma1_channel4_5_isr 1401 | #define USE_DMA_CHANNEL DMA_CHANNEL5 1402 | #define USE_DMA_IRQ NVIC_DMA2_CHANNEL4_5_IRQ 1403 | #define USE_TIMER_CCR TIM_CCR1(TIM5) 1404 | #define USE_TIMER_DMA TIM_DIER_CC1DE 1405 | #else 1406 | #error Invalid use DMA channel 1407 | #endif 1408 | 1409 | #define USE_DMA_IFCR DMA_IFCR(DMA2) 1410 | #define USE_DMA_CCR DMA_CCR(DMA2, USE_DMA_CHANNEL) 1411 | #define USE_DMA_CNDTR DMA_CNDTR(DMA2, USE_DMA_CHANNEL) 1412 | #define USE_DMA_CMAR DMA_CMAR(DMA2, USE_DMA_CHANNEL) 1413 | #define USE_DMA_CGIF DMA_IFCR_CGIF(USE_DMA_CHANNEL) 1414 | #define SET_DMA_CCR DMA_CCR(DMA2, SET_DMA_CHANNEL) 1415 | #define CLR_DMA_CCR DMA_CCR(DMA2, CLR_DMA_CHANNEL) 1416 | 1417 | static void dmaInitialize(void) 1418 | { 1419 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA2EN); 1420 | 1421 | USE_DMA_CCR = 0; 1422 | #if defined(GPIO_MODE) 1423 | USE_DMA_CNDTR = BUFFER_SIZE; 1424 | USE_DMA_CMAR = (uint32_t)(&dmaBuffer[0]); 1425 | DMA_CPAR(DMA2, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_BRR(PORT)); 1426 | #else 1427 | DMA_CPAR(DMA2, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_ODR(PORT)); 1428 | #endif 1429 | USE_DMA_IFCR = USE_DMA_CGIF; 1430 | 1431 | DMA_CNDTR(DMA2, SET_DMA_CHANNEL) = 1; 1432 | DMA_CMAR(DMA2, SET_DMA_CHANNEL) = (uint32_t)(&outputHigh); 1433 | DMA_CPAR(DMA2, SET_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1434 | SET_DMA_CCR = DMA_CCR_WRITE_FIXED; 1435 | 1436 | DMA_CNDTR(DMA2, CLR_DMA_CHANNEL) = 1; 1437 | DMA_CMAR(DMA2, CLR_DMA_CHANNEL) = (uint32_t)(&outputLow); 1438 | DMA_CPAR(DMA2, CLR_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1439 | CLR_DMA_CCR = DMA_CCR_WRITE_FIXED; 1440 | 1441 | nvic_clear_pending_irq(USE_DMA_IRQ); 1442 | nvic_enable_irq(USE_DMA_IRQ); 1443 | nvic_set_priority(USE_DMA_IRQ, 0); 1444 | } 1445 | #elif (TIMER) == 8 1446 | #if (DMAC1) == (DMAC2) || (DMAC2) == (DMAC3) || (DMAC3) == (DMAC1) 1447 | #error Three different DMA channels must be selected 1448 | #endif 1449 | #if (DMAC1) != 1 && (DMAC1) != 2 && (DMAC1) != 3 && (DMAC1) != 5 1450 | #error DMA selection 1 does not belong to timer 5 1451 | #endif 1452 | #if (DMAC2) != 1 && (DMAC2) != 2 && (DMAC2) != 3 && (DMAC2) != 5 1453 | #error DMA selection 2 does not belong to timer 5 1454 | #endif 1455 | #if (DMAC3) != 1 && (DMAC3) != 2 && (DMAC3) != 3 && (DMAC3) != 5 1456 | #error DMA selection 3 does not belong to timer 5 1457 | #endif 1458 | 1459 | #if (DMAC1) == 1 1460 | #define SET_DMA_CHANNEL DMA_CHANNEL1 1461 | #define SET_TIMER_DMA TIM_DIER_UDE 1462 | #undef SET_TIMER_CCR 1463 | #undef DMACSET 1464 | #define DMACUSE DMAC2 1465 | #define DMACCLR DMAC3 1466 | #elif (DMAC2) == 1 1467 | #define SET_DMA_CHANNEL DMA_CHANNEL1 1468 | #define SET_TIMER_DMA TIM_DIER_UDE 1469 | #undef SET_TIMER_CCR 1470 | #undef DMACSET 1471 | #define DMACUSE DMAC1 1472 | #define DMACCLR DMAC3 1473 | #elif (DMAC3) == 1 1474 | #define SET_DMA_CHANNEL DMA_CHANNEL1 1475 | #define SET_TIMER_DMA TIM_DIER_UDE 1476 | #undef SET_TIMER_CCR 1477 | #undef DMACSET 1478 | #define DMACUSE DMAC1 1479 | #define DMACCLR DMAC2 1480 | #else 1481 | #define DMACSET DMAC1 1482 | #define DMACUSE DMAC2 1483 | #define DMACCLR DMAC3 1484 | #endif 1485 | 1486 | #if defined(DMACSET) 1487 | #if (DMACSET) == 2 1488 | #define SET_DMA_CHANNEL DMA_CHANNEL2 1489 | #define SET_TIMER_CCR TIM_CCR4(TIM8) 1490 | #define SET_TIMER_DMA TIM_DIER_CC4DE 1491 | #elif (DMACSET) == 3 1492 | #define SET_DMA_CHANNEL DMA_CHANNEL3 1493 | #define SET_TIMER_CCR TIM_CCR1(TIM8) 1494 | #define SET_TIMER_DMA TIM_DIER_CC1DE 1495 | #elif (DMACSET) == 5 1496 | #define SET_DMA_CHANNEL DMA_CHANNEL5 1497 | #define SET_TIMER_CCR TIM_CCR2(TIM8) 1498 | #define SET_TIMER_DMA TIM_DIER_CC2DE 1499 | #else 1500 | #error Invalid set DMA channel 1501 | #endif 1502 | #endif 1503 | #if (DMACCLR) == 2 1504 | #define CLR_DMA_CHANNEL DMA_CHANNEL2 1505 | #define CLR_TIMER_CCR TIM_CCR4(TIM8) 1506 | #define CLR_TIMER_DMA TIM_DIER_CC4DE 1507 | #elif (DMACCLR) == 3 1508 | #define CLR_DMA_CHANNEL DMA_CHANNEL3 1509 | #define CLR_TIMER_CCR TIM_CCR1(TIM8) 1510 | #define CLR_TIMER_DMA TIM_DIER_CC1DE 1511 | #elif (DMACCLR) == 5 1512 | #define CLR_DMA_CHANNEL DMA_CHANNEL5 1513 | #define CLR_TIMER_CCR TIM_CCR2(TIM8) 1514 | #define CLR_TIMER_DMA TIM_DIER_CC2DE 1515 | #else 1516 | #error Invalid clear DMA channel 1517 | #endif 1518 | #if (DMACUSE) == 2 1519 | #define DMA_IRQ_NAME dma1_channel2_isr 1520 | #define USE_DMA_CHANNEL DMA_CHANNEL2 1521 | #define USE_DMA_IRQ NVIC_DMA2_CHANNEL2_IRQ 1522 | #define USE_TIMER_CCR TIM_CCR4(TIM8) 1523 | #define USE_TIMER_DMA TIM_DIER_CC4DE 1524 | #elif (DMACUSE) == 3 1525 | #define DMA_IRQ_NAME dma1_channel3_isr 1526 | #define USE_DMA_CHANNEL DMA_CHANNEL3 1527 | #define USE_DMA_IRQ NVIC_DMA2_CHANNEL3_IRQ 1528 | #define USE_TIMER_CCR TIM_CCR1(TIM8) 1529 | #define USE_TIMER_DMA TIM_DIER_CC1DE 1530 | #elif (DMACUSE) == 5 1531 | #define DMA_IRQ_NAME dma1_channel4_5_isr 1532 | #define USE_DMA_CHANNEL DMA_CHANNEL5 1533 | #define USE_DMA_IRQ NVIC_DMA2_CHANNEL5_IRQ 1534 | #define USE_TIMER_CCR TIM_CCR2(TIM8) 1535 | #define USE_TIMER_DMA TIM_DIER_CC2DE 1536 | #else 1537 | #error Invalid use DMA channel 1538 | #endif 1539 | 1540 | #define USE_DMA_IFCR DMA_IFCR(DMA2) 1541 | #define USE_DMA_CCR DMA_CCR(DMA2, USE_DMA_CHANNEL) 1542 | #define USE_DMA_CNDTR DMA_CNDTR(DMA2, USE_DMA_CHANNEL) 1543 | #define USE_DMA_CMAR DMA_CMAR(DMA2, USE_DMA_CHANNEL) 1544 | #define USE_DMA_CGIF DMA_IFCR_CGIF(USE_DMA_CHANNEL) 1545 | #define SET_DMA_CCR DMA_CCR(DMA2, SET_DMA_CHANNEL) 1546 | #define CLR_DMA_CCR DMA_CCR(DMA2, CLR_DMA_CHANNEL) 1547 | 1548 | static void dmaInitialize(void) 1549 | { 1550 | rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA2EN); 1551 | 1552 | USE_DMA_CCR = 0; 1553 | #if defined(GPIO_MODE) 1554 | USE_DMA_CNDTR = BUFFER_SIZE; 1555 | USE_DMA_CMAR = (uint32_t)(&dmaBuffer[0]); 1556 | DMA_CPAR(DMA2, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_BRR(PORT)); 1557 | #else 1558 | DMA_CPAR(DMA2, USE_DMA_CHANNEL) = (uint32_t)(&GPIO_ODR(PORT)); 1559 | #endif 1560 | USE_DMA_IFCR = USE_DMA_CGIF; 1561 | 1562 | DMA_CNDTR(DMA2, SET_DMA_CHANNEL) = 1; 1563 | DMA_CMAR(DMA2, SET_DMA_CHANNEL) = (uint32_t)(&outputHigh); 1564 | DMA_CPAR(DMA2, SET_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1565 | SET_DMA_CCR = DMA_CCR_WRITE_FIXED; 1566 | 1567 | DMA_CNDTR(DMA2, CLR_DMA_CHANNEL) = 1; 1568 | DMA_CMAR(DMA2, CLR_DMA_CHANNEL) = (uint32_t)(&outputLow); 1569 | DMA_CPAR(DMA2, CLR_DMA_CHANNEL) = (uint32_t)(&GPIO_BSRR(PORT)); 1570 | CLR_DMA_CCR = DMA_CCR_WRITE_FIXED; 1571 | 1572 | nvic_clear_pending_irq(USE_DMA_IRQ); 1573 | nvic_enable_irq(USE_DMA_IRQ); 1574 | nvic_set_priority(USE_DMA_IRQ, 0); 1575 | } 1576 | #else 1577 | #error Unsupported timer 1578 | #endif 1579 | 1580 | static void setOutputsLow(void) 1581 | { 1582 | GPIO_BSRR(PORT) = outputLow; 1583 | } 1584 | static void dmaDisable(void) 1585 | { 1586 | USE_DMA_CCR = 0; 1587 | SET_DMA_CCR = 0; 1588 | CLR_DMA_CCR = 0; 1589 | setOutputsLow(); 1590 | } 1591 | static void modeInitialize(const void *data, uint16_t length) 1592 | { 1593 | #if !defined(MULTI_MODE) 1594 | /* Initialize both buffers and start a send (the request won't 1595 | * actually come in until the timer is started). */ 1596 | sendBegin = (const uint8_t *)data; 1597 | sendEnd = sendBegin + length; 1598 | bufferHalf = false; 1599 | #if !defined(GPIOANY_STRICT) 1600 | fillNextBuffer(0, (1 << ((OUTPUT) % 8))); 1601 | fillNextBuffer(0, (1 << ((OUTPUT) % 8))); 1602 | #else 1603 | fillNextBuffer(); 1604 | fillNextBuffer(); 1605 | #endif 1606 | #else 1607 | /* Transfer one extra bit (from a random memory location, basically) 1608 | * so that we don't start the reset too soon. */ 1609 | #if !defined(MULTI_WIDE) 1610 | USE_DMA_CNDTR = length+1; 1611 | #else 1612 | USE_DMA_CNDTR = (length/2)+1; 1613 | #endif 1614 | USE_DMA_CMAR = (uint32_t)(data); 1615 | #endif 1616 | 1617 | #if defined(SET_TIMER_CCR) 1618 | SET_TIMER_CCR = 0; 1619 | #endif 1620 | USE_TIMER_CCR = timerZeroHigh(); 1621 | CLR_TIMER_CCR = timerOneHigh(); 1622 | 1623 | setOutputsLow(); 1624 | USE_DMA_CCR = DMA_CCR_WRITE_TL; 1625 | USE_TIMER_DIER = SET_TIMER_DMA | USE_TIMER_DMA | CLR_TIMER_DMA; 1626 | } 1627 | #endif 1628 | 1629 | #if defined(PWM_MODE) || defined(GPIO_MODE) 1630 | void DMA_IRQ_NAME (void) 1631 | { 1632 | USE_DMA_IFCR = USE_DMA_CGIF; 1633 | 1634 | /* Not done yet, so fill the next buffer and wait for the send to 1635 | * complete. */ 1636 | if (sendBegin != sendEnd) { 1637 | #if defined(PWM_MODE) 1638 | fillNextBuffer(timerOneHigh(), timerZeroHigh()); 1639 | #elif !defined(GPIOANY_STRICT) 1640 | fillNextBuffer(0, (1 << ((OUTPUT) % 8))); 1641 | #else 1642 | fillNextBuffer(); 1643 | #endif 1644 | return; 1645 | } 1646 | 1647 | /* Just clock out one extra buffer to make sure everything is 1648 | * completely out before we start the reset sequence. */ 1649 | if (sendBegin != 0) { 1650 | sendBegin = 0; 1651 | sendEnd = 0; 1652 | return; 1653 | } 1654 | 1655 | /* May already have clocked something out, but we don't care at this 1656 | * point since it's past the end of the chain. */ 1657 | dmaDisable(); 1658 | timerStartReset(); 1659 | } 1660 | #else 1661 | void DMA_IRQ_NAME (void) 1662 | { 1663 | USE_DMA_IFCR = USE_DMA_CGIF; 1664 | dmaDisable(); 1665 | timerStartReset(); 1666 | } 1667 | #endif 1668 | 1669 | void WS2821_initialize(void) 1670 | { 1671 | asm volatile ("CPSID i"); 1672 | timerInitialize(); 1673 | dmaInitialize(); 1674 | timerStartReset(); 1675 | asm volatile ("CPSIE i"); 1676 | } 1677 | 1678 | void WS2821_send(const void *data, uint16_t length) 1679 | { 1680 | if (state == Uninitialized) 1681 | WS2821_initialize(); 1682 | while (WS2812_busy()) { } 1683 | if (length == 0) 1684 | return; 1685 | 1686 | asm volatile ("CPSID i"); 1687 | state = SendingData; 1688 | timerInitialize(); 1689 | dmaInitialize(); 1690 | modeInitialize(data, length); 1691 | timerStartMain(); 1692 | asm volatile ("CPSIE i"); 1693 | } 1694 | 1695 | bool WS2812_busy(void) 1696 | { 1697 | return state != Idle; 1698 | } 1699 | bool WS2812_transmitting(void) 1700 | { 1701 | return state == SendingData; 1702 | } 1703 | -------------------------------------------------------------------------------- /ws2812.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2014 Derek Hageman 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU Affero General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program. If not, see . 16 | */ 17 | 18 | #ifndef WS2812_H 19 | #define WS2812_H 20 | 21 | #include 22 | #include 23 | 24 | /** 25 | * Initialize the WS2812 communications. This starts the initial reset 26 | * blank time. 27 | */ 28 | void WS2821_initialize(void); 29 | 30 | /** 31 | * Send data to the WS2821 chain. This will block if called before the previous 32 | * send is complete. This will also initialize the chain if needed and may 33 | * block for that on the first call. 34 | * 35 | * @param data the data to send (must remain available until the transmission is complete) 36 | * @param length the length in bytes to send 37 | */ 38 | void WS2821_send(const void *data, uint16_t length); 39 | 40 | /** 41 | * Test if the send is still active. This includes the reset period 42 | * after the send. 43 | * 44 | * @return true if the WS2812 send is still in progress 45 | */ 46 | bool WS2812_busy(void); 47 | 48 | /** 49 | * Test if the transmission is still complete. The reset period after 50 | * transmission may still be in progress. The data passed to the the send 51 | * must not become unavailable or change until this returns false. 52 | * 53 | * @return true if the WS2812 transmission is still in progress 54 | */ 55 | bool WS2812_transmitting(void); 56 | 57 | #endif 58 | -------------------------------------------------------------------------------- /ws2812_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2014 Derek Hageman 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU Affero General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program. If not, see . 16 | */ 17 | 18 | #ifndef WS2812CONFIG_H 19 | #define WS2812CONFIG_H 20 | 21 | /* Use a timer as the output. This can output to any of the timer compare 22 | * outputs. It requires a single DMA channel determined by the timer in 23 | * use and some buffer space. */ 24 | #define PWM_MODE 25 | 26 | /* Use general DMA for any pin. This can output to any pin. Unless strict mode 27 | * is enabled then the half-word mirror of the GPIO is also controlled (e.x. 28 | * GPIO1 controls both GPIO1 and GPIO9). It uses a timer, three DMA channels 29 | * determined by the timer selected, and some buffer space. */ 30 | //#define GPIO_MODE 31 | /* Only change the selected output. This causes the buffer size to grow by 32 | * a factor of two */ 33 | //#define GPIO_STRICT 34 | 35 | /* Use general DMA to output to any port. This can output to all channels of 36 | * any port. Unless wide mode is selected then the high and low bytes are 37 | * set equal. In wide mode all channels are set independently. It uses a 38 | * timer and three DMA channels determined by the timer selected. Data is 39 | * output in MSB first, so the first byte/half-word is the MSB of the green 40 | * channel of the first drivers. */ 41 | //#define MULTI_MODE 42 | /* Change all outputs on a port independently. The size given is still the 43 | * size in bytes, but outputs are done in two byte pairs to set the whole 44 | * port. */ 45 | //#define MUTLI_WIDE 46 | 47 | #if defined(PWM_MODE) 48 | /* 49 | * Timer 1: DMA1/5 50 | * Timer 2: DMA1/2 51 | * Timer 3: DMA1/3 52 | * Timer 4: DMA1/7 53 | * Timer 5: DMA2/2 54 | * Timer 8: DMA2/1 55 | */ 56 | #define TIMER 1 57 | 58 | /* Must be configured as an alternate function output */ 59 | #define OUTPUT 1 60 | 61 | /* Use the inverted output (timers 1 or 8) instead of the primary one */ 62 | //#define OUTPUT_INVERT 1 63 | 64 | /* Total space used is this plus 12. Must be a multiple of 8 65 | * and should generally be a multiple of 24 (24 bits per LED). */ 66 | #define BUFFER_SIZE 24*4 67 | #endif 68 | 69 | #if defined(GPIO_MODE) || defined(MULTI_MODE) 70 | /* 71 | * Timer 1: DMA1/2,3,4,5,6 72 | * Timer 2: DMA1/1,2,5,7 73 | * Timer 3: DMA1/2,3,6 74 | * Timer 4: DMA1/1,4,5,7 75 | * Timer 5: DMA2/1,2,4,5 76 | * Timer 8: DMA2/1,2,3,5 77 | * Any three of the above DMAs can be selected 78 | */ 79 | #define TIMER 1 80 | 81 | #if TIMER == 1 82 | #define DMAC1 4 83 | #define DMAC2 5 84 | #define DMAC3 6 85 | #elif TIMER == 2 86 | #define DMAC1 1 87 | #define DMAC2 5 88 | #define DMAC3 7 89 | #elif TIMER == 4 90 | #define DMAC1 1 91 | #define DMAC2 4 92 | #define DMAC3 5 93 | #elif TIMER == 5 94 | #define DMAC1 1 95 | #define DMAC2 2 96 | #define DMAC3 5 97 | #elif TIMER == 8 98 | #define DMAC1 1 99 | #define DMAC2 2 100 | #define DMAC3 5 101 | #endif 102 | 103 | /* Must be configured as a normal output */ 104 | #define PORT GPIOA 105 | #endif 106 | 107 | #if defined(GPIO_MODE) 108 | /* Must be configured as a normal output */ 109 | #define OUTPUT 8 110 | 111 | /* Total space is this (times two if in strict mode) plus 12. Must be a 112 | * multiple of 8 and should generally be a multiple 113 | * of 24 (24 bits per LED). */ 114 | #define BUFFER_SIZE 24*6 115 | #endif 116 | 117 | /* The clock rate in Hz */ 118 | #define CLOCK 800000 119 | /* The 0-bit high duty cycle */ 120 | #define T0H 0.32 121 | /* The 1-bit high duty cycle */ 122 | #define T1H 0.64 123 | /* The reset/latch time */ 124 | #define TRESET 50E-6 125 | 126 | #endif 127 | --------------------------------------------------------------------------------