├── .gitignore ├── LICENSE ├── README.adoc ├── colorize.log ├── .gitignore ├── README.md ├── vivado.tcl └── vivado_colorize.sh ├── fake-nic.adoc ├── fake-nic.sh ├── git-setting.adoc ├── git-setting.sh ├── gitattributes ├── HDL.gitattributes ├── cadence.gitattributes ├── common.gitattributes ├── diamond.gitattributes ├── gnu-tools.gitattributes ├── icecube.gitattributes ├── ise.gitattributes ├── mentor.gitattributes ├── quartus.gitattributes ├── synopsys.gitattributes └── vivado.gitattributes ├── gitignore ├── atmel-avr.gitignore ├── cadence.gitignore ├── common.gitignore ├── diamond.gitignore ├── gnu-tools.gitignore ├── icecube.gitignore ├── ise.gitignore ├── mentor.gitignore ├── quartus.gitignore ├── synopsys.gitignore └── vivado.gitignore ├── image ├── vivado-colorize.png └── xilinx-pll-calc.png ├── scratch.adoc ├── ucf-to-xdc-noslew.sh ├── ucf-to-xdc.adoc ├── ucf-to-xdc.sh ├── vergen-fpga.adoc ├── vergen-fpga.sh ├── vivado-stat-user.sh ├── vivado-stat.adoc ├── vivado-stat.sh ├── xilinx-pll-calc.adoc └── xilinx-pll-calc.php /.gitignore: -------------------------------------------------------------------------------- 1 | # ignore temporary files: 2 | *~ 3 | 4 | # Mac OS X file to store custom attributes of a folder 5 | .DS_Store 6 | 7 | # ignore example output 8 | #example/* 9 | 10 | # joe files: 11 | DEADJOE 12 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2016 Dmitry Murzinov 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.adoc: -------------------------------------------------------------------------------- 1 | = Collect of various scripts for working with EDA-tools (ASIC, FPGA, etc) 2 | Dmitry Murzinov 3 | v1.0, 6.7.2016 4 | :doctype: article 5 | :lang: en 6 | :stem: 7 | :grid: all 8 | :align: center 9 | :imagesdir: image 10 | :homepage: http://idoka.ru 11 | // added 12.07.2023: 12 | :idprefix: 13 | :idseparator: - 14 | ifndef::env-github[:icons: font] 15 | ifdef::env-github[] 16 | :note-caption: :paperclip: 17 | :tip-caption: :bulb: 18 | endif::[] 19 | 20 | image:https://img.shields.io/badge/-Vivado-FF1010.svg?logo=xilinx&logoColor=ffffff[vivado] image:https://img.shields.io/badge/-Quartus-blue.svg?logo=intel&logoColor=ffffff[quartus] 21 | 22 | == Intro 23 | 24 | I hope that helps not only me 25 | 26 | NOTE: Russian description available here: http://idoka.ru/my-fpga-and-asic-scripts/ 27 | 28 | == Script collection 29 | 30 | === UCF2XDC converter 31 | 32 | image:https://img.shields.io/badge/-Vivado-FF1010.svg?logo=xilinx&logoColor=ffffff[vivado] The `ucf-to-xdc.sh` script for Xilinx EDA-tools: that convert ISE-style to Vivado-style constraints (sdc -> xdc) 33 | 34 | Detailed description: 35 | include::ucf-to-xdc.adoc[leveloffset=+2] 36 | 37 | 38 | === Vivado usage runtime statistic 39 | 40 | image:https://img.shields.io/badge/-Vivado-FF1010.svg?logo=xilinx&logoColor=ffffff[vivado] The `vivado-stat.sh` script for Xilinx Vivado-tool: that prints CPU and Memory usage of all instances of Vivado tools 41 | 42 | Detailed description: 43 | include::vivado-stat.adoc[leveloffset=+2] 44 | 45 | 46 | === Fake NIC create 47 | 48 | The `fake-nic.sh` script for creating the (additional) HostID if your laptop don't have any wired Ethernet Adapter or many other cases :) 49 | 50 | Detailed description: 51 | include::fake-nic.adoc[leveloffset=+2] 52 | 53 | TIP: By the way Latest version of FLEXLM and SCL supports multiple HostID at same time, i.e. all eth* (not only eth0) 54 | 55 | 56 | === Build-in revision number into FPGA-image 57 | 58 | The `vergen-fpga.sh` script make imprinting build date and FW-hashsum intro FW-image 59 | 60 | Detailed description: 61 | include::vergen-fpga.adoc[leveloffset=+2] 62 | 63 | 64 | 65 | === Initial git settings of new EDA-related repository 66 | 67 | 68 | The `git-setting.sh` script create empty repo in specifyed location and set up required setting for EDA-related projects (at the first one: the proper `.gitattributes` and `.gitignore` files) 69 | 70 | Detailed description: 71 | include::git-setting.adoc[leveloffset=+2] 72 | 73 | 74 | === Find proper parameters for getting desired Frequency value by PLL/DCM block of Xilinx FPGA 75 | 76 | The `xilinx-pll-calc.php` script print table of proper parameters for desired output frequency (based on known input frequency) 77 | 78 | Detailed description: 79 | include::xilinx-pll-calc.adoc[leveloffset=+2] 80 | 81 | == License 82 | 83 | This project is licensed under the MIT License - see the link:LICENSE[] file for details 84 | 85 | == References 86 | 87 | * link:scratch.adoc[Notes] 88 | 89 | //// 90 | * http://www.redhat.com/[RedHat] 91 | * http://www.centos.org/[CentOS] 92 | * http://www.xilinx.com/[Xilinx] 93 | * http://www.altera.com/[Altera] 94 | //// 95 | 96 | 97 | ---- 98 | 99 | Feel free to send me comments, suggestions and bug reports 100 | 101 | -------------------------------------------------------------------------------- /colorize.log/.gitignore: -------------------------------------------------------------------------------- 1 | *.log 2 | 3 | -------------------------------------------------------------------------------- /colorize.log/README.md: -------------------------------------------------------------------------------- 1 | # EDA log colorizers 2 | 3 | 4 | ## Vivado ![vivado](https://img.shields.io/badge/-Vivado-FF1010.svg?logo=xilinx&logoColor=ffffff) 5 | 6 | ![Vivado log colorizers](/image/vivado-colorize.png?raw=true[]) 7 | 8 | 9 | ### SED syntax explanation 10 | 11 | * `'/\(^#.*\)/d'` - delete all command echo in log 12 | * `"s/\('[\*\/._a-zA-Z0-9]*'\)/\o033[2m\1\o033[22m/g"` - highligth module and signal names inside single quotes 13 | * `"s/\('[\*\/._a-zA-Z0-9]*\[[0-9]*\]'\)/\o033[2m\1\o033[22m/g"` - highligth vectored signal names inside single quotes (xxx[z]) 14 | * Highligting tables: 15 | * `'s/\(^|.*\)/\o033[1m\1\o033[0m/'` 16 | * `'s/\(^----.*\)/\o033[1m\1\o033[0m/'` 17 | * `'s/\(^====.*\)/\o033[1m\1\o033[0m/'` 18 | * `'s/\(^\+.*\)/\o033[1m\1\o033[0m/'` 19 | * Emphasizing build milestones: 20 | * `'s/\(^Phase.*\)/\o033[7m\1\o033[27m/'` 21 | * `'s/\(^Start.*\)/\o033[7m\1\o033[27m/'` 22 | * `'s/\(^WNS.*\)/\o033[36m\1\o033[39m/'` - for highlight custom messages 23 | * Handle standard messages: INFOs, WARNINGs, CRITICAL WARNINGs, ERRORs 24 | * `'s/\(^INFO.*\)/\o033[92m\1\o033[39m/'` - INFOs 25 | * `'s/\(^WARNING.*\)/\o033[34m\1\o033[39m/'` - WARNINGs 26 | * `'s/\(.*CRITICAL.*\)/\o033[35m\1\o033[39m/'` - CRITICAL WARNINGs 27 | * `'s/\(^ERROR.*\)/\o033[31m\1\o033[39m'` - ERRORs 28 | 29 | 30 | #### About echoed-command outputs in log 31 | 32 | 33 | to remove # messages use: 34 | ``` 35 | -e '/\(^#.*\)/d' 36 | ``` 37 | 38 | to hidden # messages use (using non-contrast font for light bg): 39 | ``` 40 | -e 's/\(^#.*\)/\o033[37m\1\o033[39m/' 41 | ``` 42 | 43 | -------------------------------------------------------------------------------- /colorize.log/vivado.tcl: -------------------------------------------------------------------------------- 1 | puts "" 2 | puts "------------------------------------------------------------------------------------" 3 | puts "| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020" 4 | puts "| Date : Sat Aug 15 14:36:25 2020" 5 | puts "| Host : doka running 64-bit CentOS Linux release 7.8.2003 (Core)" 6 | puts "| Command : report_utilization -hierarchical -hierarchical_depth 2" 7 | puts "| Design : xdma_top" 8 | puts "| Device : xcku115flvb2104-2" 9 | puts "| Design State : Routed" 10 | puts "------------------------------------------------------------------------------------" 11 | puts "" 12 | puts "################################################################################" 13 | puts "# STEP#1: define constraints" 14 | puts "################################################################################" 15 | puts "#set_property CONFIG_VOLTAGE 1.8 " 16 | puts "#set_property CFGBVS GND " 17 | puts "#set_property BITSTREAM.GENERAL.COMPRESS TRUE " 18 | puts "#set_property CONFIG_MODE {SPIx8} " 19 | puts "#set_property BITSTREAM.CONFIG.PERSIST SPIx8 " 20 | puts "#set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 " 21 | puts "#set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES " 22 | puts "#set_property BITSTREAM.config.SPI_opcode 0x6B " 23 | puts "#set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown " 24 | puts "#set_property HD.TANDEM_IP_PBLOCK Stage1_Config_IO " 25 | puts "#set_property HD.TANDEM_IP_PBLOCK Stage1_Main " 26 | puts "" 27 | puts "" 28 | puts "WARNING: (Synth 8-7071) port 'pipe_tx0_rcvr_det' of module 'xdma_0_core_top' is unconnected for instance 'inst' " 29 | puts "INFO: \[Synth 8-6155\] done synthesizing module 'user_reg' (9#1) " 30 | puts "INFO: \[Synth 8-6155\] done synthesizing module 'xdma_app' (10#1)" 31 | puts "INFO: \[Synth 8-6155\] done synthesizing module 'xdma_top' (11#1)" 32 | puts "INFO: \[Synth 8-3886\] merging instance 'dma_pcie_rc/pfch_rc_parityerr_reg\[0\]' (FDRE) to 'dma_pcie_rc/pfch_rc_parityerr_reg\[7\]'" 33 | puts "" 34 | 35 | puts "" 36 | puts "CRITICAL WARNING: (Vivado 12-180) No cells matched 'get_cells -hierarchical -filter { NAME =~ *rxlpmen_i_reg\[*\]}'. " 37 | puts "" 38 | puts "Starting Placer Task" 39 | puts "INFO: (Place 30-611) Multithreading enabled for place_design using a maximum of 6 CPUs" 40 | puts "" 41 | puts "Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device" 42 | puts "WARNING: (Place 30-781) Some instances may violate an exclude pblock as they constitute a macro with another instance that belongs to the exclude pblock." 43 | puts "Exclude pblock: xdma_0_i_inst_pcie3_ip_i_inst_Stage1_cfgiob" 44 | puts "" 45 | 46 | puts "Phase 10 Post Router Timing | Checksum: 2a8535c47" 47 | puts "" 48 | puts "INFO: (Common 17-349) Got license for feature 'Implementation' and/or device 'xcku115'" 49 | puts "" 50 | puts "WNS: 1.284 ns (setup)" 51 | puts "WNS: 0.030 ns (hold)" 52 | puts "" 53 | puts "INFO: (DRC 23-27) Running DRC with 6 threads" 54 | puts "WARNING: (DRC RTSTAT-10) No routable loads: 6 net(s) have no routable loads. The problem bus(es) and/or net(s) are xdma_0_i/inst/pcie3_ip_i/inst/cfg_ltssm_state_reg0\[5:0\]." 55 | puts "INFO: (Vivado 12-3199) DRC finished with 0 Errors, 1 Warnings" 56 | puts "INFO: (Vivado 12-3200) Please refer to the DRC report (report_drc) for more information." 57 | puts "INFO: (Designutils 20-2272) Running write_bitstream with 6 threads." 58 | puts "" 59 | puts "Loading data files..." 60 | puts "Loading site data..." 61 | puts "Loading route data..." 62 | puts "Processing options..." 63 | puts "INFO: (Designutils 12-2358) Enabled Tandem boot bitstream." 64 | puts "" 65 | puts "" 66 | puts "ERROR: just for example" 67 | puts "" 68 | -------------------------------------------------------------------------------- /colorize.log/vivado_colorize.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | ####################################################################################### 3 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) 4 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) 5 | ## Link : https://github.com/iDoka/eda-scripts 6 | ## Module : Colorizer for Xilinx Vivado cli log 7 | ## Description: 8 | ## Usage : use sed syntax below to add into your own build scripts and Makefiles 9 | ## Revision : $Rev 10 | ## Date : $LastChangedDate$ 11 | ## License : MIT 12 | ####################################################################################### 13 | 14 | FPGA_LOG=fpga.log 15 | 16 | rm -rf $FPGA_LOG 17 | 18 | vivado -nojournal -mode batch -source vivado.tcl | tee $FPGA_LOG | sed --unbuffered \ 19 | -e '/\(^#.*\)/d' \ 20 | -e "s/\('[\*\/._a-zA-Z0-9]*'\)/\o033[2m\1\o033[22m/g" \ 21 | -e "s/\('[\*\/._a-zA-Z0-9]*\[[0-9]*\]'\)/\o033[2m\1\o033[22m/g" \ 22 | -e 's/\(^|.*\)/\o033[1m\1\o033[0m/' \ 23 | -e 's/\(^----.*\)/\o033[1m\1\o033[0m/' \ 24 | -e 's/\(^====.*\)/\o033[1m\1\o033[0m/' \ 25 | -e 's/\(^\+.*\)/\o033[1m\1\o033[0m/' \ 26 | -e 's/\(^Phase.*\)/\o033[7m\1\o033[27m/' \ 27 | -e 's/\(^Start.*\)/\o033[7m\1\o033[27m/' \ 28 | -e 's/\(^WNS.*\)/\o033[36m\1\o033[39m/' \ 29 | -e 's/\(^INFO.*\)/\o033[92m\1\o033[39m/' \ 30 | -e 's/\(^WARNING.*\)/\o033[34m\1\o033[39m/' \ 31 | -e 's/\(.*CRITICAL.*\)/\o033[35m\1\o033[39m/' \ 32 | -e 's/\(^ERROR.*\)/\o033[31m\1\o033[39m/' 33 | -------------------------------------------------------------------------------- /fake-nic.adoc: -------------------------------------------------------------------------------- 1 | = Fake NIC create 2 | 3 | The `fake-nic.sh` script for creating the (additional) HostID if your laptop don't have any wired Ethernet Adapter or many other cases :) 4 | 5 | Russian description available here: http://idoka.ru/my-fpga-and-asic-scripts/#__ethX_c_MAC 6 | 7 | == Usage 8 | 9 | . Customize variable `$DEV` and `$MAC` in `fake-nic.sh` 10 | . Run it as `root`-user: 11 | + 12 | ``` 13 | ./fake-nic.sh 14 | ``` 15 | + 16 | that install required dependencies on your system and add NIC with proper `$DEV` (name) and `$MAC` (hostid) 17 | 18 | === Run on every bootup 19 | 20 | The quick and dirty way to bring up fake NIC on every bootup is adding to your `/etc/rc.local` strings like this: 21 | ``` 22 | MAC="E4:7D:DE:AD:BE:EF" 23 | DEV="eth1" 24 | ip tuntap add ${DEV} mode tap 25 | ifconfig ${DEV} hw ether ${MAC} 26 | ifconfig ${DEV} up 27 | ``` 28 | 29 | 30 | == Limitation 31 | 32 | This script works only on OS RHEL/CentOS 6.x/7.x as well. OS checker is built-in. 33 | 34 | 35 | == Explanation of working 36 | 37 | see the source code link:fake-nic.sh[] 38 | 39 | == ToDo 40 | 41 | * DEV and MAC pass as argv 42 | * Create a systemd script executing for network activation 43 | 44 | == Known issues 45 | 46 | not yet 47 | -------------------------------------------------------------------------------- /fake-nic.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ####################################################################################### 3 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) 4 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) 5 | ## Link : https://github.com/iDoka/eda-scripts 6 | ## Module : (Additional) NIC-adaptor creator 7 | ## Description: create virtual NIC with manually specifyed HostID 8 | ## (of course, pick any random MAC) 9 | ## Usage : refer to fake-nic.adoc for usage help 10 | ## Revision : $Rev 11 | ## Date : $LastChangedDate$ 12 | ## License : MIT 13 | ####################################################################################### 14 | 15 | # user should be a root 16 | if [ "$(id -u)" != "0" ]; then 17 | echo "This script must be run as root" 18 | exit 1 19 | fi 20 | 21 | # OS version detect 22 | OS_VERSION=`uname -r | sed 's/[0-9.\-]*el\([0-9]*\)[a-zA-Z0-9_.]*/\1/g'` 23 | 24 | # setup HostID and device 25 | MAC="E4:7D:DE:AD:BE:EF" 26 | DEV="eth1" 27 | 28 | case $OS_VERSION in 29 | 6*) # RHEL/CentOS 6 30 | yum install -y tunctl 31 | tunctl -p -u root -t ${DEV} 32 | ifconfig ${DEV} hw ether ${MAC} 33 | ifconfig ${DEV} up 34 | ;; 35 | 7*) # RHEL/CentOS 7 36 | yum install -y bridge-utils 37 | ip tuntap add ${DEV} mode tap 38 | ifconfig ${DEV} hw ether ${MAC} 39 | ifconfig ${DEV} up 40 | ;; 41 | *) # unsupported OS 42 | echo "Your OS is unsupported" 43 | ;; 44 | esac 45 | 46 | -------------------------------------------------------------------------------- /git-setting.adoc: -------------------------------------------------------------------------------- 1 | = Initial git settings of new EDA-related repository 2 | 3 | Russian description available here: http://idoka.ru/my-fpga-and-asic-scripts/#_git__ASICFPGA 4 | 5 | == Synopsis 6 | 7 | The `git-setting.sh` script create empty repo in speciffyed location and set up required setting for EDA-related projects (at the first one: the proper `.gitattributes` and `.gitignore` files) 8 | 9 | == Getting Started 10 | 11 | === Prerequisites 12 | 13 | You need to install the finger client: 14 | 15 | yum install -y finger 16 | 17 | 18 | === Installing 19 | 20 | Not needed to install 21 | 22 | 23 | === Usage 24 | 25 | Just type: 26 | 27 | ``` 28 | ./git-setting.sh /path/to/your/repo 29 | ``` 30 | 31 | that produce required settings and files into `/path/to/your/repo` folder 32 | 33 | 34 | 35 | == Limitation 36 | 37 | This script works only with IO-location and standard constraints 38 | 39 | == Explanation of working 40 | 41 | sed command explanation: 42 | 43 | * `sed '1,8d'` - cut first 8 strings of file 44 | 45 | == ToDo 46 | 47 | * [ ] Checking existence of `$GIT_DIR`, if not exist - create it by `mkdir -p $GIT_DIR` 48 | * [ ] Create typical EDA-project structure tree 49 | 50 | 51 | == Known issues 52 | 53 | Not yet 54 | 55 | == License 56 | 57 | This project is licensed under the MIT License - see the link:LICENSE[] file for details 58 | 59 | == References 60 | 61 | 62 | ---- 63 | 64 | Feel free to send me comments, suggestions and bug reports 65 | -------------------------------------------------------------------------------- /git-setting.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ####################################################################################### 3 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) 4 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) 5 | ## Link : https://github.com/iDoka/eda-scripts 6 | ## Module : git-setting.sh 7 | ## Description: Initial git settings of repository 8 | ## Usage : refer to git-setting.adoc for usage help 9 | ## Revision : $Rev 10 | ## Date : $LastChangedDate$ 11 | ## License : MIT 12 | ####################################################################################### 13 | 14 | 15 | 16 | #### check passing path 17 | if [ -z "$1" ]; then 18 | echo "No path to repository supplied. Exit." 19 | exit 1 20 | fi 21 | 22 | ###### variables 23 | CWD=`pwd` 24 | GIT_DIR=$1 25 | 26 | GIT_USER=`finger $USER | head -1 | cut -d: -f3 | sed 's/^[ ]*//'` 27 | GIT_MAIL=${USER}@${HOSTNAME}.com 28 | 29 | 30 | ########## assembly .gitignore 31 | rm -f ${GIT_DIR}/.gitignore 32 | for f in gitignore/*.gitignore 33 | do 34 | sed '1,8d' $f | cat >> ${GIT_DIR}/.gitignore 35 | done 36 | 37 | ########## assembly .gitattributes 38 | rm -f ${GIT_DIR}/.gitattributes 39 | for f in gitattributes/*.gitattributes 40 | do 41 | sed '1,8d' $f | cat >> ${GIT_DIR}/.gitattributes 42 | done 43 | 44 | ########## git repo setting 45 | cd ${GIT_DIR} 46 | git init 47 | git config user.name "${GIT_USER}" 48 | git config user.email ${GIT_MAIL} 49 | git config color.ui true 50 | git config format.pretty oneline 51 | git add .gitattributes .gitignore 52 | git commit -m "[git] settings was added" 53 | cd ${CWD} 54 | 55 | echo "Done!" 56 | -------------------------------------------------------------------------------- /gitattributes/HDL.gitattributes: -------------------------------------------------------------------------------- 1 | ### verilog 2 | ### See: https://github.com/github-linguist/linguist/blob/v7.30.0/lib/linguist/languages.yml#L7556 3 | *.v linguist-language=Verilog 4 | *.vh linguist-language=Verilog 5 | 6 | ### sv 7 | ### See: https://github.com/github-linguist/linguist/blob/v7.30.0/lib/linguist/languages.yml#L7033 8 | *.sv linguist-language=SystemVerilog 9 | *.svh linguist-language=SystemVerilog 10 | 11 | ### tcl 12 | ### See: https://github.com/github-linguist/linguist/blob/v7.30.0/lib/linguist/languages.yml#L7130 13 | *.tcl linguist-language=TCL 14 | *.sdc linguist-language=TCL 15 | *.xdc linguist-language=TCL 16 | *.qsf linguist-language=TCL 17 | 18 | -------------------------------------------------------------------------------- /gitattributes/cadence.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | -------------------------------------------------------------------------------- /gitattributes/common.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | # Handle line endings automatically for files detected as text and leave all files detected as binary untouched 11 | # Auto detect text files and perform LF normalization 12 | * text=auto 13 | 14 | 15 | ### git 16 | .gitattributes text 17 | .gitignore text 18 | .gitmodules text 19 | .gitkeep text 20 | 21 | 22 | ##### HDL 23 | *.v text 24 | *.vh text 25 | *.sv text 26 | *.svh text 27 | *.opt text 28 | 29 | 30 | ### reports 31 | # *.rpt text 32 | # *.log text 33 | 34 | 35 | ### script 36 | *.tcl text 37 | *.setup text 38 | *.prj text 39 | *.m text 40 | *.py text 41 | *.pl text 42 | *.php text 43 | *.sh text 44 | *.bash text 45 | *.awk text 46 | *.m4 text 47 | Makefile text 48 | *.makefile text 49 | *.mk text 50 | 51 | 52 | ### other extensions 53 | *.c text 54 | *.h text 55 | *.dat text 56 | 57 | 58 | ### Documents 59 | README text 60 | TODO text 61 | BUGS text 62 | *.md text 63 | *.markdown text 64 | *.adoc text 65 | *.textile text 66 | *.asciidoc text 67 | *.docbook text 68 | *.csv text 69 | *.txt text 70 | *.rst text 71 | *.list text 72 | 73 | 74 | ### Graphics 75 | *.png binary diff=exif 76 | *.jpg binary diff=exif 77 | *.jpeg binary diff=exif 78 | *.gif binary 79 | *.ico binary 80 | *.svg text 81 | 82 | 83 | ### meta 84 | *.xml text 85 | *.json text 86 | 87 | 88 | ### These files are binary and should be left untouched 89 | ### (binary is a macro for -text -diff) 90 | *.gz binary 91 | *.tgz binary 92 | *.bz2 binary 93 | *.tar binary 94 | *.zip binary 95 | *.rar binary 96 | *.7z binary 97 | *.ttf binary 98 | -------------------------------------------------------------------------------- /gitattributes/diamond.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | -------------------------------------------------------------------------------- /gitattributes/gnu-tools.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | # gtkwave viever 11 | *.gtkw 12 | 13 | ## CI system 14 | .travis.yml 15 | 16 | -------------------------------------------------------------------------------- /gitattributes/icecube.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | -------------------------------------------------------------------------------- /gitattributes/ise.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | ## constraints 11 | *.ucf text 12 | -------------------------------------------------------------------------------- /gitattributes/mentor.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | *.do text 11 | -------------------------------------------------------------------------------- /gitattributes/quartus.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | *.sof text 11 | *.qsf text 12 | *.qpf text 13 | -------------------------------------------------------------------------------- /gitattributes/synopsys.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | *.sdc text 11 | *.dc text 12 | *.vcs text 13 | *.leda text 14 | -------------------------------------------------------------------------------- /gitattributes/vivado.gitattributes: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitattributes ## 6 | ## Usage : just rename or add contain to .gitattributes ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | ## constraints 11 | *.xdc text 12 | *.xcf text 13 | *.sdc text 14 | 15 | ## 16 | *.xpr text 17 | *.xci text 18 | -------------------------------------------------------------------------------- /gitignore/atmel-avr.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | *.eep 11 | *.elf 12 | *.hex 13 | *.lss 14 | *.lst 15 | *.map 16 | *.o 17 | *.swp 18 | *.sym 19 | .dep 20 | -------------------------------------------------------------------------------- /gitignore/cadence.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | -------------------------------------------------------------------------------- /gitignore/common.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | # ignore temporary files: 11 | *~ 12 | 13 | # Mac OS X file to store custom attributes of a folder 14 | .DS_Store 15 | 16 | 17 | ##### Ignore folder from IP-structure: 18 | sim/log/* 19 | sim/out/* 20 | sim/run/* 21 | syn/log/* 22 | syn/out/* 23 | syn/run/* 24 | 25 | ## Editors: 26 | *.sublime* 27 | *.kate-swp 28 | .directory 29 | *.autosave 30 | DEADJOE 31 | 32 | ## decline machine-builded binary 33 | a.out 34 | *.so 35 | *.a 36 | *.o 37 | *.la 38 | 39 | *.old 40 | *.new 41 | *.bad 42 | *.tmp 43 | 44 | -------------------------------------------------------------------------------- /gitignore/diamond.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | -------------------------------------------------------------------------------- /gitignore/gnu-tools.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | #### dump files 11 | *.vcd 12 | *.lxt 13 | *.lx2 14 | 15 | 16 | #### iverilog compiled binaries 17 | *.vvp 18 | -------------------------------------------------------------------------------- /gitignore/icecube.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | -------------------------------------------------------------------------------- /gitignore/ise.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | -------------------------------------------------------------------------------- /gitignore/mentor.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | ## ModelSim stuff 11 | *.wlf 12 | *.mti 13 | *.mpf 14 | *.swp 15 | *.vpd 16 | *.vcd 17 | command.log 18 | work/ 19 | sim/bin/work/ 20 | modelsim.ini 21 | sim/bin/modelsim.ini 22 | 23 | transcript 24 | -------------------------------------------------------------------------------- /gitignore/quartus.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | -------------------------------------------------------------------------------- /gitignore/synopsys.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | ## decline some garbage from synopsys tools 11 | 12 | ## Design Compiler 13 | *.mr 14 | *.pvl 15 | *.syn 16 | *.svf 17 | 18 | 19 | ## Leda 20 | .leda_work 21 | leda-libs/ 22 | leda-logs/ 23 | leda*.log 24 | leda.inf 25 | leda.pro 26 | .bbox_for_block_check 27 | 28 | 29 | ## 30 | *.swo 31 | *.swm 32 | *.swn 33 | *.swl 34 | 35 | ## vcs garbage 36 | simv* 37 | csrc/ 38 | DVEfiles/ 39 | *.daidir/ 40 | .synopsys_dve_serverport.txt 41 | AN.DB/ 42 | .vlogansetup* 43 | inter.vpd 44 | simv/ 45 | ucli.key 46 | vcs.log 47 | 48 | 49 | -------------------------------------------------------------------------------- /gitignore/vivado.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################### 2 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) ## 3 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) ## 4 | ## Link : https://github.com/iDoka/eda-scripts ## 5 | ## Description: .gitignore ## 6 | ## Usage : just rename or add contain to .gitignore ## 7 | ## License : MIT ## 8 | ######################################################################################### 9 | 10 | ## log files 11 | *.log 12 | *.rpt 13 | 14 | ## bitstream 15 | *.bit 16 | 17 | ## netlist 18 | *.edf 19 | *.edif 20 | *.vn 21 | 22 | ## SDF 23 | *.sdf 24 | 25 | ###### for Xilinx Vivado|ISE 26 | .Xil/ 27 | .hbs/ 28 | .cache/ 29 | xsim.dir/ 30 | 31 | worklib.tb.wdb 32 | fsm_encoding.os 33 | tab_*/ 34 | webtalk.jou 35 | webtalk.log 36 | webtalk_*.jou 37 | webtalk_*.log 38 | vivado.jou 39 | vivado.log 40 | vivado_pid*.str 41 | hs_err_pid* 42 | xelab.* 43 | xsim.* 44 | xvlog.* 45 | *.cache 46 | *.sim 47 | *.runs 48 | *.hw 49 | *.backup.* 50 | *.debug 51 | 52 | 53 | unisims 54 | 55 | -------------------------------------------------------------------------------- /image/vivado-colorize.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iDoka/eda-scripts/f7f479c227797b3cdd6151917872743abcdac0a1/image/vivado-colorize.png -------------------------------------------------------------------------------- /image/xilinx-pll-calc.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iDoka/eda-scripts/f7f479c227797b3cdd6151917872743abcdac0a1/image/xilinx-pll-calc.png -------------------------------------------------------------------------------- /scratch.adoc: -------------------------------------------------------------------------------- 1 | 2 | for `fake-nic.sh`: 3 | ``` 4 | #!/bin/bash 5 | 6 | if [ "$(id -u)" != "0" ]; then 7 | echo "This script must be run as root" 8 | exit 1 9 | fi 10 | 11 | echo -n "Enter new username: "; read user 12 | echo -n "Enter new password: "; read pass 13 | 14 | printf "$user:$(openssl passwd -crypt $pass)\n" >> /etc/nginx/.htpasswd 15 | ``` 16 | 17 | 18 | 19 | $ echo 'NET "ddr3_dq0" LOC = "AY12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST;' | sed '/^$/d;s/[\"=|;]//g;s/[\t]*//g;s/\ \{1,\}/\ /g' | sed 's/NET[ ]*\([_a-zA-Z0-9]*\)[ ]*LOC[ ]*\([A-Z0-9]*\)[ ]*IOSTANDARD[ ]*\([_A-Z0-9]*\)[ ]*VCCAUX_IO[ ]*\([A-Z]*\)[ ]*SLEW[ ]*\([A-Z]*\)/\1 \2 \3 \4 \5/g' 20 | 21 | $ echo 'NET "ddr3_dq[0]" LOC = "AY12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST;' | sed '/^$/d;s/[\"=|;]//g;s/[\t]*//g;s/\ \{1,\}/\ /g' 22 | NET ddr3_dq[0] LOC AY12 IOSTANDARD SSTL15_T_DCI VCCAUX_IO NORMAL SLEW FAST 23 | 24 | replace several whitespace by one: 25 | $ sed 's/\ \{1,\}/\ /g' 26 | 27 | remove blank string from file: 28 | $ sed '/^$/d' input.txt > output.txt 29 | 30 | [ "$x" == "valid" ] && echo "valid" || echo "invalid" 31 | 32 | 33 | sed ':a;N;$!ba;s/\n//g' 34 | 35 | where: 36 | 37 | * :a - create a label 'a' 38 | * N - append the next line to the pattern space 39 | * $! - if not the last line 40 | * ba - branch (go to) label 'a' 41 | * s - substitute 42 | * /\n/ - regex for new line 43 | * // - with text "" 44 | * g - global match (as many times as it can) 45 | 46 | 47 | === how to check if $1 and $2 are null? 48 | 49 | Try using the -z test: 50 | if [ -z "$1" ] && [ -z "$2" ] 51 | 52 | From man bash: 53 | -z string 54 | True if the length of string is zero. 55 | 56 | ---- 57 | 58 | ``` 59 | if [ "$#" -ne 1 ]; then 60 | echo "Illegal number of parameters" 61 | fi 62 | ``` 63 | 64 | Or 65 | 66 | ``` 67 | if test "$#" -ne 1; then 68 | echo "Illegal number of parameters" 69 | fi 70 | ``` 71 | 72 | 73 | --------------- 74 | 75 | * http://askubuntu.com/questions/444082/how-to-check-if-1-and-2-are-null[how to check if $1 and $2 are null?] 76 | * http://stackoverflow.com/questions/18568706/checking-number-of-arguments-bash-script[checking number of arguments bash script] 77 | * http://stackoverflow.com/questions/6482377/check-existence-of-input-argument-in-a-bash-shell-script[Check existence of input argument in a Bash shell script] 78 | 79 | * http://linuxcommand.org/wss0100.php[Writing shell scripts - Lesson 10: Stay Out Of Trouble] 80 | * http://stackoverflow.com/questions/2237080/how-to-compare-strings-in-bash-script 81 | * http://wiki.bash-hackers.org/syntax/ccmd/conditional_expression 82 | * http://tldp.org/LDP/abs/html/comparison-ops.html 83 | * http://tldp.org/LDP/abs/html/loops1.html 84 | * http://ryanstutorials.net/bash-scripting-tutorial/bash-loops.php 85 | * http://www.canbike.org/information-technology/sed-delete-carriage-returns-and-linefeeds-crlf.html 86 | -------------------------------------------------------------------------------- /ucf-to-xdc-noslew.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ####################################################################################### 3 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) 4 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) 5 | ## Link : https://github.com/iDoka/eda-scripts 6 | ## Module : sdc -> xdc converter 7 | ## Description: for Xilinx tools: that convert ISE-style to Vivado-style constraints 8 | ## Usage : refer to ucf-to-xdc.adoc for usage help 9 | ## Revision : $Rev 10 | ## Date : $LastChangedDate$ 11 | ## License : MIT 12 | ####################################################################################### 13 | 14 | 15 | UCFNAME=`basename $1` 16 | DOTCOUNT=`echo ${UCFNAME} | sed 's/[^.]//g' | awk '{ print length }'` 17 | FILE=`basename $1 | cut -d. -f-${DOTCOUNT}` 18 | DIR=`dirname $1` 19 | 20 | ##### obsolete syntax (saved for references): 21 | #sed '/^$/d;s/[\"=|;]//g;s/[\t]*//g;s/\ \{1,\}/\ /g;s/NET[ ]*\(.*\)[ ]*LOC[ ]*\([A-Z0-9]*\)[ ]*IOSTANDARD[ ]*\([_A-Z0-9]*\)[ ]*VCCAUX_IO[ ]*\([A-Z]*\)[ ]*SLEW[ ]*\([A-Z]*\)/set_property PACKAGE_PIN \2 \[get_ports \1\]\nset_property IOSTANDARD \3 \[get_ports \1\]\nset_property VCCAUX_IO \4 \[get_ports \1\]\nset_property SLEW \5 \[get_ports \1\]\n\n/g' \ 22 | # $FILE.ucf > $FILE.xdc 23 | 24 | 25 | sed '/^$/d;s/[\"=|;]//g;s/[\t]*//g;s/\ \{1,\}/\ /g;s/NET[ ]*\(.*\)[ ]*LOC[ ]*\([A-Z0-9]*\)[ ]*IOSTANDARD[ ]*\([_A-Z0-9]*\)[ ]*VCCAUX_IO[ ]*\([A-Z]*\)[ ]/set_property -dict \{PACKAGE_PIN \2 \tIOSTANDARD \3 \tVCCAUX_IO \4\} \[get_ports \1\];/g' \ 26 | $1 > $DIR/$FILE.xdc 27 | 28 | -------------------------------------------------------------------------------- /ucf-to-xdc.adoc: -------------------------------------------------------------------------------- 1 | = UCF2XDC converter 2 | 3 | The `ucf-to-xdc.sh` script for Xilinx EDA-tools: that convert ISE-style to Vivado-style constraints (sdc -> xdc) 4 | 5 | Russian description available here: http://idoka.ru/my-fpga-and-asic-scripts/#_UCF_XDC 6 | 7 | == usage 8 | Just type: 9 | ``` 10 | ./ucf-to-xdc.sh FILENAME.ucf 11 | ``` 12 | that produce the file `FILENAME.xdc` in current dir 13 | 14 | === input file example [ucf] 15 | ``` 16 | NET "DDR_DQ[0]" LOC = "AY12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST; 17 | NET "DDR_DQ[1]" LOC = "AW12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST; 18 | ``` 19 | 20 | === output file example [xdc] 21 | ``` 22 | set_property PACKAGE_PIN AY12 [get_ports DDR_DQ[0]] 23 | set_property IOSTANDARD SSTL15_T_DCI [get_ports DDR_DQ[0]] 24 | set_property VCCAUX_IO NORMAL [get_ports DDR_DQ[0]] 25 | set_property SLEW FAST [get_ports DDR_DQ[0]] 26 | 27 | set_property PACKAGE_PIN AW12 [get_ports DDR_DQ[1]] 28 | set_property IOSTANDARD SSTL15_T_DCI [get_ports DDR_DQ[1]] 29 | set_property VCCAUX_IO NORMAL [get_ports DDR_DQ[1]] 30 | set_property SLEW FAST [get_ports DDR_DQ[1]] 31 | ``` 32 | 33 | == Limitation 34 | 35 | This script works only with IO-location and standard constraints 36 | 37 | == Explanation of working 38 | 39 | sed command explanation: 40 | 41 | * `/^$/d` - remove all empty strings 42 | * `s/[\"=|;]//g` - remove any of these symbols: `"`, `=`, `|`, `;` 43 | * `s/[\t]*//g` - remove all horizontal tabulation symbol 44 | * `s/\ \{1,\}/\ /g` - replace several whitespaces by one (i.e.: `" "` -> `" "`) 45 | * Formatting output string (parted by several string): 46 | ** `s/NET[ ]*\(.*\)[ ]*`.. - extract signal name 47 | ** ..`LOC[ ]*\([A-Z0-9]*\)[ ]*`.. - extract pin name 48 | ** ..`IOSTANDARD[ ]*\([_A-Z0-9]*\)[ ]*`.. - extract IO-standard 49 | ** ..`VCCAUX_IO[ ]*\([A-Z]*\)[ ]*`.. - extract VCCAUX value 50 | ** ..`SLEW[ ]*\([A-Z]*\)/`.. - extract slewrate 51 | ** ..`set_property PACKAGE_PIN \2 \[get_ports \1\]\n`.. - generate location constraint 52 | ** ..`set_property IOSTANDARD \3 \[get_ports \1\]\n`.. - generate IO-standard constraint 53 | ** ..`set_property VCCAUX_IO \4 \[get_ports \1\]\n`.. - generate VCCAUX value constraint 54 | ** ..`set_property SLEW \5 \[get_ports \1\]\n\n/g` - generate slew rate constraint 55 | 56 | 57 | == ToDo 58 | 59 | * a position independent parser of ucf 60 | * move to new one-string format of xdc, like this: 61 | + 62 | ``` 63 | set_property -dict {PACKAGE_PIN AY12 IOSTANDARD SSTL15_T_DCI VCCAUX_IO NORMAL SLEW FAST} [get_ports DDR_DQ[0]]; 64 | ``` 65 | 66 | 67 | == Known issues 68 | 69 | * current version of parser ucf is a position dependent; for some ucf needed changing of order of mention key according input ucf 70 | -------------------------------------------------------------------------------- /ucf-to-xdc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ####################################################################################### 3 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) 4 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) 5 | ## Link : https://github.com/iDoka/eda-scripts 6 | ## Module : sdc -> xdc converter 7 | ## Description: for Xilinx tools: that convert ISE-style to Vivado-style constraints 8 | ## Usage : refer to ucf-to-xdc.adoc for usage help 9 | ## Revision : $Rev 10 | ## Date : $LastChangedDate$ 11 | ## License : MIT 12 | ####################################################################################### 13 | 14 | UCFNAME=`basename $1` 15 | DOTCOUNT=`echo ${UCFNAME} | sed 's/[^.]//g' | awk '{ print length }'` 16 | FILE=`basename $1 | cut -d. -f-${DOTCOUNT}` 17 | DIR=`dirname $1` 18 | # echo "${FILE}" 19 | 20 | ##### obsolete syntax (saved for references): 21 | #sed '/^$/d;s/[\"=|;]//g;s/[\t]*//g;s/\ \{1,\}/\ /g;s/NET[ ]*\(.*\)[ ]*LOC[ ]*\([A-Z0-9]*\)[ ]*IOSTANDARD[ ]*\([_A-Z0-9]*\)[ ]*VCCAUX_IO[ ]*\([A-Z]*\)[ ]*SLEW[ ]*\([A-Z]*\)/set_property PACKAGE_PIN \2 \[get_ports \1\]\nset_property IOSTANDARD \3 \[get_ports \1\]\nset_property VCCAUX_IO \4 \[get_ports \1\]\nset_property SLEW \5 \[get_ports \1\]\n\n/g' \ 22 | # $FILE.ucf > $FILE.xdc 23 | 24 | 25 | sed '/^$/d;s/[\"=|;]//g;s/[\t]*//g;s/\ \{1,\}/\ /g;s/NET[ ]*\(.*\)[ ]*LOC[ ]*\([A-Z0-9]*\)[ ]*IOSTANDARD[ ]*\([_A-Z0-9]*\)[ ]*VCCAUX_IO[ ]*\([A-Z]*\)[ ]*SLEW[ ]*\([A-Z]*\)/set_property -dict \{PACKAGE_PIN \2 \tIOSTANDARD \3 \tVCCAUX_IO \4 \tSLEW \5\} \[get_ports \1\];\n/g' \ 26 | $1 > $DIR/$FILE.xdc 27 | # $FILE.ucf > $FILE.xdc 28 | 29 | -------------------------------------------------------------------------------- /vergen-fpga.adoc: -------------------------------------------------------------------------------- 1 | = Build-in revision number into FPGA-image 2 | 3 | The `vergen-fpga.sh` script make imprinting build date and FW-hashsum intro FW-image 4 | 5 | Russian description available here: http://idoka.ru/my-fpga-and-asic-scripts/#___FPGA 6 | -------------------------------------------------------------------------------- /vergen-fpga.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | ####################################################################################### 3 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) 4 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) 5 | ## Link : https://github.com/iDoka/eda-scripts 6 | ## Module : Build-in revision number into FPGA-image 7 | ## Description: 8 | ## Usage : refer to vergen-fpga.adoc for usage help 9 | ## Revision : $Rev 10 | ## Date : $LastChangedDate$ 11 | ## License : MIT 12 | ####################################################################################### 13 | 14 | 15 | ################################################################ 16 | ##### $1 - filename.mcs FPGA image 17 | ##### Please specify correct Addresses, total length is 20 byte: 18 | ##### 4 byte - data stamp and 19 | ##### 16 byte - MD5 signature 20 | ################################################################ 21 | 22 | 23 | ADDRESS1=0xF800 24 | ADDRESS2=0xF814 25 | 26 | FILENAME=`echo $1 | cut -d. -f1` 27 | 28 | FPGAIMAGE=fpgaimage.hex 29 | 30 | 31 | ######### Setup output format ############# 32 | case $2 in 33 | ### For Intel ihex ### 34 | [iI]*) 35 | FORMAT=intel 36 | FILEEXT=hex 37 | ;; 38 | ### For Motorola s-rec ### 39 | [mM]*) 40 | FORMAT=motorola 41 | FILEEXT=srec 42 | ;; 43 | *) # unsupported options 44 | echo "Incorrect specifyed options!" 45 | echo "Allovable values for specify output format is [I]ntel or [M]otorolla" 46 | ;; 47 | esac 48 | 49 | 50 | ### Converting to Intel ihex ### 51 | promgen -p hex -r $1 -o $FPGAIMAGE 52 | echo Date: `stat $1 --format=%z` 53 | DATEIMAGE=`stat $1 --format=%Z` 54 | CHECKSUM=`md5sum $1 | cut -d' ' -f1` 55 | FWSTRING=`printf "0x%x%s" $DATEIMAGE $CHECKSUM | sed -e :a -e 's/\(.*[0-9a-f]\)\([0-9a-f]\{2\}\)/\1 0x\2/;ta'` 56 | 57 | 58 | srec_cat -generate $ADDRESS1 $ADDRESS2 -repeat-data $FWSTRING $FPGAIMAGE -exclude $ADDRESS1 $ADDRESS2 -output ${FILENAME}.${FILEEXT} -${FORMAT} && echo "...Done!" 59 | -------------------------------------------------------------------------------- /vivado-stat-user.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ####################################################################################### 3 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) 4 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) 5 | ## Link : https://github.com/iDoka/eda-scripts 6 | ## Module : Xilinx Vivado CPU and Memory usage statistic 7 | ## Description: that prints CPU and Memory usage of current user instances of Vivado 8 | ## Usage : refer to vivado-stat.adoc for usage help 9 | ## Revision : $Rev 10 | ## Date : $LastChangedDate$ 11 | ## License : MIT 12 | ####################################################################################### 13 | 14 | 15 | 16 | CMD="vivado" 17 | PERIOD="3s" 18 | 19 | PID=`ps aux | grep $USER | grep ${CMD} | grep lnx64.o | sed 's/\ \{1,\}/\ /g' | cut -d' ' -f2` 20 | 21 | 22 | while true; do 23 | IS_RUN=`ps -C ${CMD} -o comm= | head -1` 24 | #[ -n ${IS_RUN} ] || break 25 | if [ "${IS_RUN}" == "" ]; then 26 | break 27 | fi 28 | #CPU=`ps -C ${CMD} -o user=,pcpu= | grep $USER | sed 's/\ \{1,\}/\ /g' | cut -d' ' -f2 | sed ':a;N;$!ba;s/\n/\+/g' | bc -l | cut -d. -f1 | sed 's/$/%/'` 29 | #CPU=`top -p ${PID} -n1 | awk '{if (NR==8) print $10 }' | cut -d. -f1 | sed 's/$/%/'` 30 | CPU=`top -p ${PIDS} -n1 | awk '{if (NR>=8) print $10 }' | sed '/^$/d' | sed ':a;N;$!ba;s/\n/\+/g' | bc -l | cut -d. -f1 | sed 's/$/%/'` 31 | MEM=`ps -C ${CMD} -o user=,size= | grep $USER | sed 's/\ \{1,\}/\ /g' | cut -d' ' -f2 | sed 's/$/\/1024/g' | sed ':a;N;$!ba;s/\n/\+/g' | bc -l | cut -d. -f1 | sed 's/$/M/'` 32 | echo -e "$CPU\t$MEM" 33 | sleep ${PERIOD} 34 | done 35 | 36 | DATE=`date "+%H:%M %d.%m.%Y"` 37 | echo "*** ${CMD} was finished running at ${DATE} ***" 38 | -------------------------------------------------------------------------------- /vivado-stat.adoc: -------------------------------------------------------------------------------- 1 | = Vivado usage statistic at runtime 2 | 3 | The `vivado-stat.sh` script for Xilinx Vivado-tool: that prints CPU and Memory usage of all instances of Vivado tools 4 | 5 | Russian description available here: http://idoka.ru/my-fpga-and-asic-scripts/#__Xilinx_Vivado 6 | 7 | == Usage 8 | Just type in cli: 9 | ``` 10 | ./vivado-stat.sh 11 | ``` 12 | that run util which periodically prints the resource consumption. 13 | 14 | You can adjust following parameters: 15 | 16 | * `CMD` - the string contain process name for watching 17 | * `PERIOD` - integer value in sec for specify period of watch 18 | 19 | === Example of running 20 | 21 | Sample of output for `PERIOD = "30s"`: 22 | ``` 23 | $ ./vivado-stat.sh 24 | 97% 1265M 25 | 99% 1459M 26 | 98% 1570M 27 | 98% 1822M 28 | 99% 1948M 29 | 99% 2138M 30 | 99% 2531M 31 | 99% 2821M 32 | 103% 2928M 33 | 103% 3098M 34 | 428% 7092M 35 | 477% 8959M 36 | 446% 10335M 37 | 375% 10408M 38 | 435% 11391M 39 | 441% 11633M 40 | 460% 13799M 41 | 420% 13966M 42 | 404% 14006M 43 | 296% 9994M 44 | *** vivado was finished running at 11:11 06.07.2016 *** 45 | $ 46 | ``` 47 | 48 | == Limitation 49 | 50 | .Obsolete: 51 | 52 | This script shows entire `vivado` processes of *all* users. 53 | For prints usage stat for current user should be modifyed script by adding `| grep $USER` filter on pipe 54 | 55 | .Updated: 56 | 57 | Done! Please use the `vivado-stat-user.sh` script for per-user stat of Vivado usage. 58 | 59 | 60 | == Explanation of working 61 | 62 | === CPU 63 | 64 | * `ps -C ${CMD} -o pcpu=` - print all strings that contain of $CMD processes 65 | * `sed ':a;N;$!ba;s/\n/\+/g'` - that converts from multiline to oneline and inserts "+" sign between values; see bellow: 66 | ** `:a` - create a label 'a' 67 | ** `N` - append the next line to the pattern space 68 | ** `$!` - if not the last line 69 | ** `ba` - branch (go to) label 'a' 70 | ** `s` - substitute 71 | ** `/\n/` - regex for new line 72 | ** `/\+/` - with text "+" (\+ - for escaping character) 73 | ** `g` - global match (as many times as it can) 74 | * `bc -l` - pass string to simple calculator 75 | * `cut -d. -f1` - cutting float part of result number 76 | * `sed 's/$/%/'` - added "%" sign for CPU usage on the end of string 77 | 78 | === MEM 79 | 80 | * `ps -C ${CMD} -o size=` - print all strings that contain of $CMD processes 81 | * `sed 's/$/\/1024/g'` - convert kB to MB (by 1k dividing every string) 82 | * `sed ':a;N;$!ba;s/\n/\+/g'` - see the CPU example above 83 | * `bc -l` - pass string to simple calculator 84 | * `cut -d. -f1` - cutting float part of result number 85 | * `sed 's/M/%/'` - added "M" char for RAM usage 86 | 87 | 88 | == ToDo 89 | 90 | [options="readonly"] 91 | * [x] version with separate usage by users 92 | * [ ] start and stop watching between vivado startup without exit 93 | * [x] move from `ps` to `top -p $PID -n1 | awk '{if (NR==8) print $10 }'` 94 | * [x] passing list of PIDs to CPU% usage as follow way: `top -p $PID1,$PID2,..` 95 | 96 | 97 | == Known issues 98 | 99 | * `size` or `vsize` use in `ps` command for RAM consumption? (currently use the `size`) 100 | * FIXED: fake CPU% used on the `ps` cmd. For detail read http://unix.stackexchange.com/questions/58539/top-and-ps-not-showing-the-same-cpu-result[Top and ps not showing the same cpu result] 101 | * FIXED: only one istance of Vivado tools was used for usage statistic 102 | -------------------------------------------------------------------------------- /vivado-stat.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ####################################################################################### 3 | ## Project : Collect of various scripts for working with EDA-tools (ASIC/FPGA/etc) 4 | ## Designer : Dmitry Murzinov (kakstattakim@gmail.com) 5 | ## Link : https://github.com/iDoka/eda-scripts 6 | ## Module : Xilinx Vivado CPU and Memory usage statistic 7 | ## Description: that prints CPU and Memory usage of all instances of Vivado tools 8 | ## Usage : refer to vivado-stat.adoc for usage help 9 | ## Revision : $Rev 10 | ## Date : $LastChangedDate$ 11 | ## License : MIT 12 | ####################################################################################### 13 | 14 | 15 | CMD="vivado" 16 | PERIOD="1s" 17 | 18 | #PID=`ps aux | grep ${CMD} | grep lnx64.o | sed 's/\ \{1,\}/\ /g' | cut -d' ' -f2` 19 | PIDS=`ps aux | grep ${CMD} | grep lnx64.o | sed 's/\ \{1,\}/\ /g' | cut -d' ' -f2 | sed ':a;N;$!ba;s/\n/\,/g'` 20 | 21 | while true; do 22 | IS_RUN=`ps -C ${CMD} -o comm= | head -1` 23 | #[ -n ${IS_RUN} ] || break 24 | if [ "${IS_RUN}" == "" ]; then 25 | break 26 | fi 27 | #CPU=`ps -C ${CMD} -o pcpu= | sed ':a;N;$!ba;s/\n/\+/g' | bc -l | cut -d. -f1 | sed 's/$/%/'` 28 | #CPU=`top -p ${PID} -n1 | awk '{if (NR==8) print $10 }' | cut -d. -f1 | sed 's/$/%/'` 29 | CPU=`top -p ${PIDS} -n1 | awk '{if (NR>=8) print $10 }' | sed '/^$/d' | sed ':a;N;$!ba;s/\n/\+/g' | bc -l | cut -d. -f1 | sed 's/$/%/'` 30 | MEM=`ps -C ${CMD} -o size= | sed 's/$/\/1024/g' | sed ':a;N;$!ba;s/\n/\+/g' | bc -l | cut -d. -f1 | sed 's/$/M/'` 31 | echo -e "$CPU\t$MEM" 32 | sleep ${PERIOD} 33 | done 34 | 35 | DATE=`date "+%H:%M %d.%m.%Y"` 36 | echo "*** ${CMD} was finished running at ${DATE} ***" 37 | 38 | -------------------------------------------------------------------------------- /xilinx-pll-calc.adoc: -------------------------------------------------------------------------------- 1 | = Find proper parameters for getting desired Frequency by PLL/DCM block of Xilinx FPGA 2 | 3 | The `xilinx-pll-calc.php` script print table of proper parameters for desired output frequency (based on known input frequency) 4 | 5 | Russian description available here: http://idoka.ru/my-fpga-and-asic-scripts/#__PLLDCM_Xilinx_FPGA 6 | 7 | == Usage 8 | 9 | . Customize following variables `$F_input` (Hz), `$F_desired` (Hz) and `$precission` (%) in `xilinx-pll-calc.php` 10 | . Choice proper FPGA family, e.g.: `$FPGA = $SPARTAN6;` 11 | . Run it: 12 | + 13 | ``` 14 | php xilinx-pll-calc.php 15 | ``` 16 | + 17 | and looking for bold green string with exactly frequency value: 18 | + 19 | image::/image/xilinx-pll-calc.png?raw=true[] 20 | 21 | == Limitation 22 | 23 | This script supports following family: 24 | 25 | * Xilinx Spartan-6 26 | * Xilinx Virtex-7 27 | * [Add your favourite FPGA. See next chapter] 28 | 29 | 30 | === Adding new FPGA family 31 | 32 | Xilinx, Altera, Lattice?... Everything vendor & family can be supported! 33 | 34 | The quick and dirty way to adding new family is filling associated array like that: 35 | ``` 36 | $VIRTEX7 = array( 37 | "FREQ_INP_MIN" => 19e6, 38 | "FREQ_INP_MAX" => 800e6, 39 | "FREQ_VCO_MIN" => 800e6, 40 | "FREQ_VCO_MAX" => 1600e6, 41 | "FREQ_OUT_MIN" => 6.25e6, 42 | "FREQ_OUT_MAX" => 800e6, 43 | "M_MIN" => 2, 44 | "M_MAX" => 64, 45 | "D_MIN" => 1, 46 | "D_MAX" => 128, 47 | "O_MIN" => 1, 48 | "O_MAX" => 56); 49 | ``` 50 | 51 | Use this equation for explanation key name, like: M, D, O, FREQ_INP, FREQ_VCO, FREQ_OUT. 52 | ``` 53 | ####################### 54 | ######################## # 55 | # # Useful Folmulae # 56 | # M # for PLL Equation # 57 | # Fvco = Fin * - # # 58 | # D ####################### 59 | # # 60 | # Fvco M # 61 | # Fout = ---- or Fout = Fin * ----- # 62 | # O D*O # 63 | # # 64 | ########################################### 65 | ``` 66 | 67 | 68 | == Explanation of working 69 | 70 | see the source code link:xilinx-pll-calc.php[] 71 | 72 | == ToDo 73 | 74 | * Mode of chaining two PLL in serial connection (for solving unresolved with single PLL Freq ratio) 75 | 76 | == Known issues 77 | 78 | not yet known 79 | -------------------------------------------------------------------------------- /xilinx-pll-calc.php: -------------------------------------------------------------------------------- 1 | 1) { 45 | $filename = $argv[1]; 46 | $contents = file_get_contents($filename); 47 | $contents = utf8_encode($contents); 48 | $pinout = json_decode($contents,TRUE); 49 | } 50 | else { 51 | echo "Usage tool in CLI:\n\t$ php xilinx-pll-calc.php\n"; 52 | exit; 53 | } 54 | */ 55 | 56 | ########################################### 57 | ### Store of settings different PLL 58 | 59 | $SPARTAN6 = array( // -3 grade -2 grade -1L grade 60 | "FREQ_INP_MIN" => 19e6, 61 | "FREQ_INP_MAX" => 450e6, // 540 450 300 62 | "FREQ_VCO_MIN" => 400e6, 63 | "FREQ_VCO_MAX" => 1000e6, // 1080 1000 1000 64 | "FREQ_OUT_MIN" => 3.125e6, 65 | "FREQ_OUT_MAX" => 950e6, // 1080 950 500 66 | "M_MIN" => 1, 67 | "M_MAX" => 64, 68 | "D_MIN" => 1, 69 | "D_MAX" => 128, 70 | "O_MIN" => 1, 71 | "O_MAX" => 52); 72 | 73 | $VIRTEX7 = array( // -3 grade -2 grade -1 grade 74 | "FREQ_INP_MIN" => 19e6, 75 | "FREQ_INP_MAX" => 800e6, // 1066 933 800 76 | "FREQ_VCO_MIN" => 800e6, 77 | "FREQ_VCO_MAX" => 1600e6, // 2133 1866 1600 78 | "FREQ_OUT_MIN" => 6.25e6, 79 | "FREQ_OUT_MAX" => 800e6, // 1066 933 800 80 | "M_MIN" => 2, 81 | "M_MAX" => 64, 82 | "D_MIN" => 1, 83 | "D_MAX" => 128, 84 | "O_MIN" => 1, 85 | "O_MAX" => 56); 86 | 87 | ########################################### 88 | 89 | /* 90 | Stages: 91 | 1. Check input range 92 | 2. Check output range 93 | 3. Pick up 3 cycles for proper Fvco and Fout with desired tolerance 94 | 4. If unsuccessful -> goto chain of 2 serial PLL connection 95 | */ 96 | 97 | // Pick up desired FPGA family: 98 | $FPGA = $SPARTAN6; 99 | 100 | 101 | ########## 1. Check input range ########## 102 | if (($FPGA["FREQ_INP_MIN"] > $F_input) | ($FPGA["FREQ_INP_MAX"] < $F_input)) { 103 | echo "CAUTION: Input frequency out of range!".PHP_EOL; 104 | exit; 105 | } 106 | 107 | ########## 2. Check output range ########## 108 | if (($FPGA["FREQ_OUT_MIN"] > $F_desired) or ($FPGA["FREQ_OUT_MAX"] < $F_desired)) { 109 | echo "CAUTION: Output frequency out of range!".PHP_EOL; 110 | exit; 111 | } 112 | 113 | $tolerance = $precission / 100; // parts 114 | echo PHP_EOL."Settings:".PHP_EOL."\tFinput: $F_input Hz".PHP_EOL."\tFoutput: $F_desired Hz (desired)".PHP_EOL.PHP_EOL; 115 | //echo "\e[7m M\tD\tO \tFout (Error)\e[0m".PHP_EOL; 116 | echo "\e[7m M D O Fout (Error)\e[0m".PHP_EOL; 117 | echo "===== ===== ========= =========== =======".PHP_EOL; 118 | 119 | ########## 3. Pick up 3 cycles for proper Fvco and Fout with desired tolerance ########## 120 | for ($M=$FPGA["M_MIN"]; $M<=$FPGA["M_MAX"]; $M++) { 121 | for ($D=$FPGA["D_MIN"]; $D<=$FPGA["D_MAX"]; $D++) { 122 | $F_VCO = $F_input * $M/$D; 123 | if (($FPGA["FREQ_VCO_MIN"] <= $F_VCO) and ($FPGA["FREQ_VCO_MAX"] >= $F_VCO)) { 124 | //echo "M=$M \tD=$D \tVCO=$F_VCO".PHP_EOL; 125 | for ($O=$FPGA["O_MIN"]; $O<=$FPGA["O_MAX"]; $O++) { 126 | $F_output = $F_input * $M/$D/$O; 127 | if ((($F_desired*(1-$tolerance)) <= $F_output) and ($F_output <= ($F_desired*(1+$tolerance)))) { 128 | $deviation = ceil(abs($F_output/$F_desired-1)*100*100)/100; 129 | if ($F_desired == $F_output) { 130 | echo "\e[1m\e[32m $M\t$D\t$O \t$F_output bingo\e[0m".PHP_EOL; 131 | } else { 132 | $F_output = round($F_output); 133 | echo " $M\t$D\t$O \t$F_output ($deviation%)".PHP_EOL; 134 | } 135 | } 136 | } 137 | } 138 | } 139 | } 140 | 141 | 142 | 143 | ########## 4. chain of 2 serial PLL connection ########## 144 | 145 | # To do ... 146 | 147 | 148 | 149 | ########################################################################################################### 150 | ?> 151 | --------------------------------------------------------------------------------