├── Diagram ├── BlockDiagram │ ├── 6TCell.png │ ├── SenseAmp.png │ ├── TriState.png │ ├── PreCharge.png │ ├── WriteDriver.png │ └── Full_BlockDiagram.png └── CircuitDiagram │ ├── cell_6t.png │ ├── full_sram.png │ ├── sense_amp.png │ └── write_driver.png ├── Waveforms └── PreLayout │ └── tb_tran.png ├── Spice ├── PreLayout │ ├── pre_charge.sp │ ├── cell_icon.sp │ ├── sense_amp.sp │ ├── write_driver.sp │ ├── tran_clc.sp │ └── tb_tran.sp └── scmos_bsim4.lib ├── LICENSE └── README.md /Diagram/BlockDiagram/6TCell.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/BlockDiagram/6TCell.png -------------------------------------------------------------------------------- /Waveforms/PreLayout/tb_tran.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Waveforms/PreLayout/tb_tran.png -------------------------------------------------------------------------------- /Diagram/BlockDiagram/SenseAmp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/BlockDiagram/SenseAmp.png -------------------------------------------------------------------------------- /Diagram/BlockDiagram/TriState.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/BlockDiagram/TriState.png -------------------------------------------------------------------------------- /Diagram/BlockDiagram/PreCharge.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/BlockDiagram/PreCharge.png -------------------------------------------------------------------------------- /Diagram/BlockDiagram/WriteDriver.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/BlockDiagram/WriteDriver.png -------------------------------------------------------------------------------- /Diagram/CircuitDiagram/cell_6t.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/CircuitDiagram/cell_6t.png -------------------------------------------------------------------------------- /Diagram/CircuitDiagram/full_sram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/CircuitDiagram/full_sram.png -------------------------------------------------------------------------------- /Diagram/CircuitDiagram/sense_amp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/CircuitDiagram/sense_amp.png -------------------------------------------------------------------------------- /Diagram/CircuitDiagram/write_driver.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/CircuitDiagram/write_driver.png -------------------------------------------------------------------------------- /Diagram/BlockDiagram/Full_BlockDiagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iamkrvikash/OpenSRAM/HEAD/Diagram/BlockDiagram/Full_BlockDiagram.png -------------------------------------------------------------------------------- /Spice/PreLayout/pre_charge.sp: -------------------------------------------------------------------------------- 1 | *Subcircuit for Pre-Charge Ckt 2 | 3 | .subckt pre_charge bl blb pc vdd gnd 4 | 5 | m7 bl pc vdd vdd p w='2u' l='0.4u' 6 | m8 blb pc vdd vdd p w='2u' l='0.4u' 7 | m9 bl pc blb vdd p w='2u' l='0.4u' 8 | 9 | .ends pre_charge 10 | -------------------------------------------------------------------------------- /Spice/PreLayout/cell_icon.sp: -------------------------------------------------------------------------------- 1 | *Subcircuit for SRAM_6T_cell 2 | 3 | .subckt cell_icon bl blb wl vdd gnd 4 | 5 | *Inverter 1 6 | m1 q qbar gnd gnd n w='1.6u' l='0.4u' 7 | m5 q qbar vdd vdd p w='0.6u' l='0.8u' 8 | 9 | *Inverter 2 10 | m2 qbar q gnd gnd n w='1.6u' l='0.4u' 11 | m6 qbar q vdd vdd p w='0.6u' l='0.8u' 12 | 13 | *Access transistor 14 | m3 q wl bl gnd n w='0.8u' l='0.4u' 15 | m4 qbar wl blb gnd n w='0.8u' l='0.4u' 16 | 17 | .ends cell_icon 18 | -------------------------------------------------------------------------------- /Spice/PreLayout/sense_amp.sp: -------------------------------------------------------------------------------- 1 | * Subcircuit for sense amplifier 2 | 3 | .subckt sense_amp bl blb dout en vdd gnd 4 | 5 | m20 gnd en a_56 gnd n w='1.8u' l='0.4u' 6 | 7 | * Inverter 1 8 | m21 a_56 a_48 dout gnd n w='1.8u' l='0.4u' 9 | m22 vdd a_48 dout vdd p w='3.6u' l='0.4u' 10 | 11 | * Inverter 2 12 | m23 a_48 dout a_56 gnd n w='1.8u' l='0.4u' 13 | m24 a_48 dout vdd vdd p w='3.6u' l='0.4u' 14 | 15 | * Bit line Transistor 16 | m25 bl en dout vdd p w='4.8u' l='0.4u' 17 | m26 a_48 en blb vdd p w='4.8u' l='0.4u' 18 | 19 | .ends 20 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 VIKASH KUMAR 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Spice/PreLayout/write_driver.sp: -------------------------------------------------------------------------------- 1 | **** Write_Driver ****** 2 | 3 | .subckt write_driver din bl br en vdd gnd 4 | 5 | **** Inverter to conver Data_in to data_in_bar ****** 6 | * din_bar = inv(din) 7 | M_1 din_bar din gnd gnd n W=0.8u L=0.4u 8 | M_2 din_bar din vdd vdd p W=1.4u L=0.4u 9 | 10 | **** 2input nand gate follwed by inverter to drive BL ****** 11 | * din_bar_gated = nand(en, din) 12 | M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u 13 | M_4 net_7 din gnd gnd n W=1.4u L=0.4u 14 | M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u 15 | M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u 16 | * din_bar_gated_bar = inv(din_bar_gated) 17 | M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u 18 | M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u 19 | 20 | **** 2input nand gate follwed by inverter to drive BLB****** 21 | * din_gated = nand(en, din_bar) 22 | M_9 din_gated en vdd vdd p W=1.4u L=0.4u 23 | M_10 din_gated en net_8 gnd n W=1.4u L=0.4u 24 | M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u 25 | M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u 26 | * din_gated_bar = inv(din_gated) 27 | M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u 28 | M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u 29 | 30 | ************************************************ 31 | * pull down with en enable 32 | M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u 33 | M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u 34 | 35 | 36 | 37 | .ends write_driver 38 | -------------------------------------------------------------------------------- /Spice/PreLayout/tran_clc.sp: -------------------------------------------------------------------------------- 1 | SRAM Design 2 | *Include LIB FILE 3 | .lib scmos_bsim4.lib nom 4 | 5 | *Temperatures 6 | .temp 27 7 | *DC VOltage Sources 8 | vdd vdd 0 5 9 | *Parameters 10 | .global vdd gnd 11 | 12 | *Include 6t-cell subcircuit 13 | xi bl blb wl vdd gnd cell_icon 14 | .include cell_icon.sp 15 | *Include sense_amp subckt 16 | xt bl blb dout en vdd gnd sense_amp 17 | .include sense_amp.sp 18 | *Include write driver subckt 19 | xd din bl blb enw vdd gnd write_driver 20 | .include write_driver.sp 21 | *Include Pre-Charge Transistor 22 | xpre bl blb pc vdd gnd pre_charge 23 | .include pre_charge.sp 24 | 25 | **Clock inverter 26 | mclkp pc clk vdd gnd p w='0.6u' l='0.8u' 27 | mclkn pc clk gnd gnd n w='1.6u' l='0.4u' 28 | 29 | *Routing capacitance 30 | cbl bl gnd 1280f 31 | cblb blb gnd 1280f 32 | cwl wl gnd 2560f 33 | *BitLine overlap capacitance 34 | m10 bl gnd vdd gnd n w='0.8u' l='0.4u' m='127' 35 | m11 blb gnd vdd gnd n w='0.8u' l='0.4u' m='127' 36 | *WordLine parasitic capacitance 37 | m12 vdd wl gnd gnd n w='0.8u' l='0.4u' m='255' 38 | m13 vdd wl vdd gnd n w='0.8u' l='0.4u' m='255' 39 | 40 | *Initial Condition 41 | .nodeset v(xi.q)=0 42 | .nodeset v(xi.qbar)=5 43 | 44 | *Data control (CLock Pulse Line) 45 | vclk clk 0 pulse(5 0 20n 1n 1n 25n 50n) 46 | *Sense Amplifier control Signal 47 | ven en 0 pulse(5 0 40n 1n 1n 5n 100n) 48 | *Access Control 49 | vwl wl 0 pulse(0 5 30n 1n 1n 10n 50n) 50 | *Write Driver Enable & Din 51 | venw enw 0 pulse(0 5 75n 1n 1n 20n 100n) 52 | vdin din 0 pulse(0 5 75n 1n 1n 20n 200n) 53 | 54 | 55 | *Transient Analysis 56 | .tran 5p 300n 57 | .control 58 | run 59 | plot v(dout)-6 v(xi.q) v(xi.qbar) v(bl)+6 v(blb)+6 v(din)+12 v(enw)+18 v(en)+24 v(wl)+30 v(clk)+36 60 | .endc 61 | 62 | .end 63 | 64 | -------------------------------------------------------------------------------- /Spice/PreLayout/tb_tran.sp: -------------------------------------------------------------------------------- 1 | SRAM Design 2 | *Include LIB FILE 3 | .lib ../scmos_bsim4.lib nom 4 | 5 | *Temperatures 6 | .temp 27 7 | *DC VOltage Sources 8 | vdd vdd 0 5 9 | *Parameters 10 | .global vdd gnd 11 | 12 | *Include 6t-cell subcircuit 13 | xi bl blb wl vdd gnd cell_icon 14 | .include cell_icon.sp 15 | *Include sense_amp subckt 16 | xt bl blb dout en vdd gnd sense_amp 17 | .include sense_amp.sp 18 | *Include write driver subckt 19 | xd din bl blb enw vdd gnd write_driver 20 | .include write_driver.sp 21 | *Include Pre-Charge Transistor 22 | xpre bl blb pc vdd gnd pre_charge 23 | .include pre_charge.sp 24 | 25 | **Clock inverter 26 | mclkp pc clk vdd gnd p w='0.6u' l='0.8u' 27 | mclkn pc clk gnd gnd n w='1.6u' l='0.4u' 28 | 29 | *Routing capacitance 30 | cbl bl gnd 1280f 31 | cblb blb gnd 1280f 32 | cwl wl gnd 2560f 33 | *BitLine overlap capacitance 34 | m10 bl gnd vdd gnd n w='0.8u' l='0.4u' m='127' 35 | m11 blb gnd vdd gnd n w='0.8u' l='0.4u' m='127' 36 | *WordLine parasitic capacitance 37 | m12 vdd wl gnd gnd n w='0.8u' l='0.4u' m='255' 38 | m13 vdd wl vdd gnd n w='0.8u' l='0.4u' m='255' 39 | 40 | *Initial Condition 41 | .nodeset v(xi.q)=0 42 | .nodeset v(xi.qbar)=5 43 | 44 | *Data control (CLock Pulse Line) 45 | vclk clk 0 pulse(5 0 20n 1n 1n 25n 50n) 46 | *Sense Amplifier control Signal 47 | ven en 0 pulse(5 0 40n 1n 1n 5n 100n) 48 | *Access Control 49 | vwl wl 0 pulse(0 5 30n 1n 1n 10n 50n) 50 | *Write Driver Enable & Din 51 | venw enw 0 pulse(0 5 75n 1n 1n 20n 100n) 52 | vdin din 0 pulse(0 5 75n 1n 1n 20n 200n) 53 | 54 | 55 | *Transient Analysis 56 | .tran 5p 250n 57 | .control 58 | run 59 | plot v(dout)-6 v(xi.q) v(xi.qbar) v(bl)+6 v(blb)+6 v(din)+12 v(enw)+18 v(en)+24 v(wl)+30 v(clk)+36 60 | .endc 61 | 62 | .end 63 | 64 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | # OpenSRAM 3 | 4 | SRAM Design using OpenSource Applications. 5 | 6 | Table of Contents 7 | ================= 8 | * [SRAM Design](#sram-design) 9 | * [Basic Architectural Block Diagram](#basic-architectural-block-diagram) 10 | * [Pre Layout](#pre-layout) 11 | - [6T Memory cell](#6t-memory-cell) 12 | - [Sense Amplifier](#sense-amplifier) 13 | - [Write Driver](#write-driver) 14 | - [Tri-State Buffer](#tri-state-buffer) 15 | - [Pre-Charge Circuit](#pre-charge-circuit) 16 | - [Simulation of 6T SRAM Cell](#simulation-of-6t-sram-cell-with-write-driver-and-sense-amplifier) 17 | * Pre Layout 18 | * [Installation](#installation) 19 | * [Future Works](#future-works) 20 | * [Contact Information](#contact-information) 21 | 22 | # SRAM Design 23 | The project is focused on the design of 1k*32-bit 6T SRAM memory using opensource memory compiler [OpenRAM](https://openram.soe.ucsc.edu/). For the design of custom memory array, memory compiler takes in SPICE netlists, Layout files of the custom cells designed and few other parameters and generates a SRAM memory array. 24 | 25 | SRAM Specs - Memory Size of **1k x 32-bit,** Operating voltage - **5V**, Technology PDK file - **0.5um SCMOS** Technology from MOSIS. 26 | * For more information on OpenRAM. [Click here](https://github.com/VLSIDA/OpenRAM.git) 27 | 28 | 29 | # Basic Architectural Block Diagram 30 | ![Block Diagram](/Diagram/BlockDiagram/Full_BlockDiagram.png) 31 | 32 | 33 | # Pre Layout 34 | To clone the Repository and download the Netlist files for Simulation, 35 | Enter the following commands in your terminal. 36 | ```sh 37 | $ sudo apt install -y git 38 | $ git clone https://github.com/iamkrvikash/OpenSRAM 39 | $ cd OpenRAM/Spice/PreLayout 40 | ``` 41 | 42 | # 6T Memory Cell 43 | #### Block Diagram 44 | ![6T Cell Block](/Diagram/BlockDiagram/6TCell.png) 45 | 46 | #### Circuit Diagram 47 | ![6T Cell](/Diagram/CircuitDiagram/cell_6t.png) 48 | 49 | ##### DC Analysis of Inverter 50 | ```sh 51 | ngspice tran_dc.sp 52 | ``` 53 | 54 | 55 | 56 | # Sense Amplifier 57 | #### Block Diagram 58 | ![Sense Amp Block](/Diagram/BlockDiagram/SenseAmp.png) 59 | 60 | #### Circuit Diagram 61 | ![Sense Amplifier](/Diagram/CircuitDiagram/sense_amp.png) 62 | 63 | # Write Driver 64 | #### Block Diagram 65 | ![6T Cell Block](/Diagram/BlockDiagram/WriteDriver.png) 66 | 67 | #### Circuit Diagram 68 | ![Write Driver](/Diagram/CircuitDiagram/write_driver.png) 69 | 70 | # Tri-State Buffer 71 | #### Block Diagram 72 | ![Tri-State Block](/Diagram/BlockDiagram/TriState.png) 73 | 74 | #### Circuit Diagram 75 | 76 | 77 | # Pre-Charge Circuit 78 | #### Block Diagram 79 | ![Pre-Charge Block](/Diagram/BlockDiagram/PreCharge.png) 80 | 81 | #### Circuit Diagram 82 | 83 | 84 | 85 | # Simulation of 6T-SRAM Cell with write driver and sense amplifier 86 | ```sh 87 | ngspice tb_tran.sp 88 | ``` 89 | ![SRAM Simulation](/Waveforms/PreLayout/tb_tran.png) 90 | 91 | # Installation 92 | * To download EDA tools (NgSpice, Magic, Netgen) on your System. Follow [Github Page](https://github.com/silicon-vlsi/project2020#Cloning-the-Repository) and Clone the Repo. 93 | * `git clone https://github.com/silicon-vlsi/project2020` 94 | 95 | 96 | # Future Works 97 | * To create the layout using Magic. 98 | * To do Post Layout Simulations. 99 | * Implementing the above designs in OpenRAM Compiler and Compiling the SRAM. 100 | # Contact Information 101 | * Vikash Kumar, Undergraduate Student, SIT BBSR [iamkrvikash@gmail.com](mailto:iamkrvikash@gmail.com) 102 | -------------------------------------------------------------------------------- /Spice/scmos_bsim4.lib: -------------------------------------------------------------------------------- 1 | *****scn4m_subm-model-library****** 2 | * Model files for the MOSIS's Scalable SCMOS Process 3 | * Wmin=0.6um, Lmin = 0.4u 4 | 5 | *simultor: ngspice 6 | *process : scn4m_subm 7 | 8 | 9 | .lib nom 10 | 11 | .MODEL n NMOS ( LEVEL = 49 12 | +VERSION = 3.1 TNOM = 27 TOX = 7.6E-9 13 | +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.4964448 14 | +K1 = 0.5307769 K2 = 0.0199705 K3 = 0.2963637 15 | +K3B = 0.2012165 W0 = 2.836319E-6 NLX = 2.894802E-7 16 | +DVT0W = 0 DVT1W = 5.3E6 DVT2W = -0.032 17 | +DVT0 = 0.112017 DVT1 = 0.2453972 DVT2 = -0.171915 18 | +U0 = 444.9381976 UA = 2.921284E-10 UB = 1.773281E-18 19 | +UC = 7.067896E-11 VSAT = 1.130785E5 A0 = 1.1356246 20 | +AGS = 0.2810374 B0 = 2.844393E-7 B1 = 5E-6 21 | +KETA = -7.8181E-3 A1 = 0 A2 = 1 22 | +RDSW = 925.2701982 PRWG = -1E-3 PRWB = -1E-3 23 | +WR = 1 WINT = 7.186965E-8 LINT = 1.735515E-9 24 | +XL = -2E-8 XW = 0 DWG = -1.712973E-8 25 | +DWB = 5.851691E-9 VOFF = -0.132935 NFACTOR = 0.5710974 26 | +CIT = 0 CDSC = 8.607229E-4 CDSCD = 0 27 | +CDSCB = 0 ETA0 = 2.128321E-3 ETAB = 0 28 | +DSUB = 0.0257957 PCLM = 0.6766314 PDIBLC1 = 1 29 | +PDIBLC2 = 1.787424E-3 PDIBLCB = 0 DROUT = 0.7873539 30 | +PSCBE1 = 6.973485E9 PSCBE2 = 1.46235E-7 PVAG = 0.05 31 | +DELTA = 0.01 MOBMOD = 1 PRT = 0 32 | +UTE = -1.5 KT1 = -0.11 KT1L = 0 33 | +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18 34 | +UC1 = -5.6E-11 AT = 3.3E4 WL = 0 35 | +WLN = 1 WW = 0 WWN = 1 36 | +WWL = 0 LL = 0 LLN = 1 37 | +LW = 0 LWN = 1 LWL = 0 38 | +CAPMOD = 2 CGDO = 1.96E-10 CGSO = 1.96E-10 39 | +CGBO = 0 CJ = 9.276962E-4 PB = 0.8157962 40 | +MJ = 0.3557696 CJSW = 3.181055E-10 PBSW = 0.6869149 41 | +MJSW = 0.1 PVTH0 = -0.0252481 PRDSW = -96.4502805 42 | +PK2 = -4.805372E-3 WKETA = -7.643187E-4 LKETA = -0.0129496 ) 43 | 44 | 45 | .MODEL p PMOS ( LEVEL = 49 46 | +VERSION = 3.1 TNOM = 27 TOX = 7.6E-9 47 | +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.6636594 48 | +K1 = 0.4564781 K2 = -0.019447 K3 = 39.382919 49 | +K3B = -2.8930965 W0 = 2.655585E-6 NLX = 1.51028E-7 50 | +DVT0W = 0 DVT1W = 5.3E6 DVT2W = -0.032 51 | +DVT0 = 1.1744581 DVT1 = 0.7631128 DVT2 = -0.1035171 52 | +U0 = 151.3305606 UA = 2.061211E-10 UB = 1.823477E-18 53 | +UC = -8.97321E-12 VSAT = 9.915604E4 A0 = 1.1210053 54 | +AGS = 0.3961954 B0 = 6.493139E-7 B1 = 4.273215E-6 55 | +KETA = -9.27E-3 A1 = 0 A2 = 1 56 | +RDSW = 2.30725E3 PRWG = -1E-3 PRWB = 0 57 | +WR = 1 WINT = 5.962233E-8 LINT = 4.30928E-9 58 | +XL = -2E-8 XW = 0 DWG = -1.596201E-8 59 | +DWB = 1.378919E-8 VOFF = -0.15 NFACTOR = 2 60 | +CIT = 0 CDSC = 6.593084E-4 CDSCD = 0 61 | +CDSCB = 0 ETA0 = 0.0286461 ETAB = 0 62 | +DSUB = 0.2436027 PCLM = 4.3597508 PDIBLC1 = 7.447024E-4 63 | +PDIBLC2 = 4.256073E-3 PDIBLCB = 0 DROUT = 0.0120292 64 | +PSCBE1 = 1.347622E10 PSCBE2 = 5E-9 PVAG = 3.669793 65 | +DELTA = 0.01 MOBMOD = 1 PRT = 0 66 | +UTE = -1.5 KT1 = -0.11 KT1L = 0 67 | +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18 68 | +UC1 = -5.6E-11 AT = 3.3E4 WL = 0 69 | +WLN = 1 WW = 0 WWN = 1 70 | +WWL = 0 LL = 0 LLN = 1 71 | +LW = 0 LWN = 1 LWL = 0 72 | +CAPMOD = 2 CGDO = 2.307E-10 CGSO = 2.307E-10 73 | +CGBO = 0 CJ = 1.420282E-3 PB = 0.99 74 | +MJ = 0.5490877 CJSW = 4.773605E-10 PBSW = 0.99 75 | +MJSW = 0.1997417 PVTH0 = 6.58707E-3 PRDSW = -93.5582228 76 | +PK2 = 1.011593E-3 WKETA = -0.0101398 LKETA = 6.027967E-3 ) 77 | .endl 78 | 79 | .lib ff 80 | 81 | .MODEL n NMOS ( LEVEL = 49 82 | +VERSION = 3.1 TNOM = 27 TOX = 7.6E-9 83 | +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.4468003 84 | +K1 = 0.5307769 K2 = 0.0199705 K3 = 0.2963637 85 | +K3B = 0.2012165 W0 = 2.836319E-6 NLX = 2.894802E-7 86 | +DVT0W = 0 DVT1W = 5.3E6 DVT2W = -0.032 87 | +DVT0 = 0.112017 DVT1 = 0.2453972 DVT2 = -0.171915 88 | +U0 = 444.9381976 UA = 2.921284E-10 UB = 1.773281E-18 89 | +UC = 7.067896E-11 VSAT = 1.130785E5 A0 = 1.1356246 90 | +AGS = 0.2810374 B0 = 2.844393E-7 B1 = 5E-6 91 | +KETA = -7.8181E-3 A1 = 0 A2 = 1 92 | +RDSW = 925.2701982 PRWG = -1E-3 PRWB = -1E-3 93 | +WR = 1 WINT = 7.186965E-8 LINT = 1.735515E-9 94 | +XL = -2E-8 XW = 0 DWG = -1.712973E-8 95 | +DWB = 5.851691E-9 VOFF = -0.132935 NFACTOR = 0.5710974 96 | +CIT = 0 CDSC = 8.607229E-4 CDSCD = 0 97 | +CDSCB = 0 ETA0 = 2.128321E-3 ETAB = 0 98 | +DSUB = 0.0257957 PCLM = 0.6766314 PDIBLC1 = 1 99 | +PDIBLC2 = 1.787424E-3 PDIBLCB = 0 DROUT = 0.7873539 100 | +PSCBE1 = 6.973485E9 PSCBE2 = 1.46235E-7 PVAG = 0.05 101 | +DELTA = 0.01 MOBMOD = 1 PRT = 0 102 | +UTE = -1.5 KT1 = -0.11 KT1L = 0 103 | +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18 104 | +UC1 = -5.6E-11 AT = 3.3E4 WL = 0 105 | +WLN = 1 WW = 0 WWN = 1 106 | +WWL = 0 LL = 0 LLN = 1 107 | +LW = 0 LWN = 1 LWL = 0 108 | +CAPMOD = 2 CGDO = 1.96E-10 CGSO = 1.96E-10 109 | +CGBO = 0 CJ = 9.276962E-4 PB = 0.8157962 110 | +MJ = 0.3557696 CJSW = 3.181055E-10 PBSW = 0.6869149 111 | +MJSW = 0.1 PVTH0 = -0.0252481 PRDSW = -96.4502805 112 | +PK2 = -4.805372E-3 WKETA = -7.643187E-4 LKETA = -0.0129496 ) 113 | 114 | 115 | .MODEL p PMOS ( LEVEL = 49 116 | +VERSION = 3.1 TNOM = 27 TOX = 7.6E-9 117 | +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.5972935 118 | +K1 = 0.4564781 K2 = -0.019447 K3 = 39.382919 119 | +K3B = -2.8930965 W0 = 2.655585E-6 NLX = 1.51028E-7 120 | +DVT0W = 0 DVT1W = 5.3E6 DVT2W = -0.032 121 | +DVT0 = 1.1744581 DVT1 = 0.7631128 DVT2 = -0.1035171 122 | +U0 = 151.3305606 UA = 2.061211E-10 UB = 1.823477E-18 123 | +UC = -8.97321E-12 VSAT = 9.915604E4 A0 = 1.1210053 124 | +AGS = 0.3961954 B0 = 6.493139E-7 B1 = 4.273215E-6 125 | +KETA = -9.27E-3 A1 = 0 A2 = 1 126 | +RDSW = 2.30725E3 PRWG = -1E-3 PRWB = 0 127 | +WR = 1 WINT = 5.962233E-8 LINT = 4.30928E-9 128 | +XL = -2E-8 XW = 0 DWG = -1.596201E-8 129 | +DWB = 1.378919E-8 VOFF = -0.15 NFACTOR = 2 130 | +CIT = 0 CDSC = 6.593084E-4 CDSCD = 0 131 | +CDSCB = 0 ETA0 = 0.0286461 ETAB = 0 132 | +DSUB = 0.2436027 PCLM = 4.3597508 PDIBLC1 = 7.447024E-4 133 | +PDIBLC2 = 4.256073E-3 PDIBLCB = 0 DROUT = 0.0120292 134 | +PSCBE1 = 1.347622E10 PSCBE2 = 5E-9 PVAG = 3.669793 135 | +DELTA = 0.01 MOBMOD = 1 PRT = 0 136 | +UTE = -1.5 KT1 = -0.11 KT1L = 0 137 | +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18 138 | +UC1 = -5.6E-11 AT = 3.3E4 WL = 0 139 | +WLN = 1 WW = 0 WWN = 1 140 | +WWL = 0 LL = 0 LLN = 1 141 | +LW = 0 LWN = 1 LWL = 0 142 | +CAPMOD = 2 CGDO = 2.307E-10 CGSO = 2.307E-10 143 | +CGBO = 0 CJ = 1.420282E-3 PB = 0.99 144 | +MJ = 0.5490877 CJSW = 4.773605E-10 PBSW = 0.99 145 | +MJSW = 0.1997417 PVTH0 = 6.58707E-3 PRDSW = -93.5582228 146 | +PK2 = 1.011593E-3 WKETA = -0.0101398 LKETA = 6.027967E-3 ) 147 | .endl 148 | 149 | .lib ss 150 | 151 | .MODEL n NMOS ( LEVEL = 49 152 | +VERSION = 3.1 TNOM = 27 TOX = 7.6E-9 153 | +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.5108928 154 | +K1 = 0.5307769 K2 = 0.0199705 K3 = 0.2963637 155 | +K3B = 0.2012165 W0 = 2.836319E-6 NLX = 2.894802E-7 156 | +DVT0W = 0 DVT1W = 5.3E6 DVT2W = -0.032 157 | +DVT0 = 0.112017 DVT1 = 0.2453972 DVT2 = -0.171915 158 | +U0 = 444.9381976 UA = 2.921284E-10 UB = 1.773281E-18 159 | +UC = 7.067896E-11 VSAT = 1.130785E5 A0 = 1.1356246 160 | +AGS = 0.2810374 B0 = 2.844393E-7 B1 = 5E-6 161 | +KETA = -7.8181E-3 A1 = 0 A2 = 1 162 | +RDSW = 925.2701982 PRWG = -1E-3 PRWB = -1E-3 163 | +WR = 1 WINT = 7.186965E-8 LINT = 1.735515E-9 164 | +XL = -2E-8 XW = 0 DWG = -1.712973E-8 165 | +DWB = 5.851691E-9 VOFF = -0.132935 NFACTOR = 0.5710974 166 | +CIT = 0 CDSC = 8.607229E-4 CDSCD = 0 167 | +CDSCB = 0 ETA0 = 2.128321E-3 ETAB = 0 168 | +DSUB = 0.0257957 PCLM = 0.6766314 PDIBLC1 = 1 169 | +PDIBLC2 = 1.787424E-3 PDIBLCB = 0 DROUT = 0.7873539 170 | +PSCBE1 = 6.973485E9 PSCBE2 = 1.46235E-7 PVAG = 0.05 171 | +DELTA = 0.01 MOBMOD = 1 PRT = 0 172 | +UTE = -1.5 KT1 = -0.11 KT1L = 0 173 | +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18 174 | +UC1 = -5.6E-11 AT = 3.3E4 WL = 0 175 | +WLN = 1 WW = 0 WWN = 1 176 | +WWL = 0 LL = 0 LLN = 1 177 | +LW = 0 LWN = 1 LWL = 0 178 | +CAPMOD = 2 CGDO = 1.96E-10 CGSO = 1.96E-10 179 | +CGBO = 0 CJ = 9.276962E-4 PB = 0.8157962 180 | +MJ = 0.3557696 CJSW = 3.181055E-10 PBSW = 0.6869149 181 | +MJSW = 0.1 PVTH0 = -0.0252481 PRDSW = -96.4502805 182 | +PK2 = -4.805372E-3 WKETA = -7.643187E-4 LKETA = -0.0129496 ) 183 | 184 | 185 | .MODEL p PMOS ( LEVEL = 49 186 | +VERSION = 3.1 TNOM = 27 TOX = 7.6E-9 187 | +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.5972935 188 | +K1 = 0.4564781 K2 = -0.019447 K3 = 39.382919 189 | +K3B = -2.8930965 W0 = 2.655585E-6 NLX = 1.51028E-7 190 | +DVT0W = 0 DVT1W = 5.3E6 DVT2W = -0.032 191 | +DVT0 = 1.1744581 DVT1 = 0.7631128 DVT2 = -0.1035171 192 | +U0 = 151.3305606 UA = 2.061211E-10 UB = 1.823477E-18 193 | +UC = -8.97321E-12 VSAT = 9.915604E4 A0 = 1.1210053 194 | +AGS = 0.3961954 B0 = 6.493139E-7 B1 = 4.273215E-6 195 | +KETA = -9.27E-3 A1 = 0 A2 = 1 196 | +RDSW = 2.30725E3 PRWG = -1E-3 PRWB = 0 197 | +WR = 1 WINT = 5.962233E-8 LINT = 4.30928E-9 198 | +XL = -2E-8 XW = 0 DWG = -1.596201E-8 199 | +DWB = 1.378919E-8 VOFF = -0.15 NFACTOR = 2 200 | +CIT = 0 CDSC = 6.593084E-4 CDSCD = 0 201 | +CDSCB = 0 ETA0 = 0.0286461 ETAB = 0 202 | +DSUB = 0.2436027 PCLM = 4.3597508 PDIBLC1 = 7.447024E-4 203 | +PDIBLC2 = 4.256073E-3 PDIBLCB = 0 DROUT = 0.0120292 204 | +PSCBE1 = 1.347622E10 PSCBE2 = 5E-9 PVAG = 3.669793 205 | +DELTA = 0.01 MOBMOD = 1 PRT = 0 206 | +UTE = -1.5 KT1 = -0.11 KT1L = 0 207 | +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18 208 | +UC1 = -5.6E-11 AT = 3.3E4 WL = 0 209 | +WLN = 1 WW = 0 WWN = 1 210 | +WWL = 0 LL = 0 LLN = 1 211 | +LW = 0 LWN = 1 LWL = 0 212 | +CAPMOD = 2 CGDO = 2.307E-10 CGSO = 2.307E-10 213 | +CGBO = 0 CJ = 1.420282E-3 PB = 0.99 214 | +MJ = 0.5490877 CJSW = 4.773605E-10 PBSW = 0.99 215 | +MJSW = 0.1997417 PVTH0 = 6.58707E-3 PRDSW = -93.5582228 216 | +PK2 = 1.011593E-3 WKETA = -0.0101398 LKETA = 6.027967E-3 ) 217 | .endl 218 | 219 | 220 | --------------------------------------------------------------------------------