├── .gitignore ├── 2030.mcs ├── 7seg_LEDs.vhd ├── Buses2030.vhd ├── CLD ├── Regs.rtf ├── qa001.rtf ├── qa011.rtf ├── qa021.rtf ├── qa031.rtf ├── qa041.rtf ├── qa051.rtf ├── qa061.rtf ├── qa071.rtf ├── qa081.rtf ├── qa091.rtf ├── qa161.rtf ├── qa171.rtf ├── qa181.rtf ├── qa191.rtf ├── qa211.rtf ├── qa221.rtf ├── qa311.rtf ├── qa321.rtf ├── qa331.rtf ├── qa341.rtf ├── qa351.rtf ├── qa361.rtf ├── qa371.rtf ├── qa411.rtf ├── qa421.rtf ├── qa431.rtf ├── qa761.rtf ├── qa771.rtf ├── qa781.rtf ├── qa861.rtf ├── qa871.rtf ├── qa879.rtf ├── qa881.rtf ├── qa891.rtf ├── qa901.rtf ├── qa911.rtf ├── qa921.rtf ├── qa931.rtf ├── qa941.rtf ├── qb001.rtf ├── qb011.rtf ├── qb021.rtf ├── qb031.rtf ├── qb041.rtf ├── qb061.rtf ├── qb071.rtf ├── qb081.rtf ├── qb091.rtf ├── qb101.rtf ├── qb111.rtf ├── qb121.rtf ├── qb131.rtf ├── qb151.rtf ├── qb161.rtf ├── qb611.rtf ├── qb621.rtf ├── qb631.rtf ├── qb641.rtf ├── qb651.rtf ├── qb661.rtf ├── qb671.rtf ├── qb681.rtf ├── qb702.rtf ├── qb711.rtf ├── qb712.rtf ├── qb721.rtf ├── qb731.rtf ├── qb741.rtf ├── qb742.rtf ├── qb751.rtf ├── qb752.rtf ├── qb761.rtf ├── qb762.rtf ├── qb771.rtf ├── qb781.rtf ├── qb791.rtf ├── qb801.rtf ├── qb811.rtf ├── qb821.rtf ├── qb831.rtf ├── qb841.rtf ├── qb851.rtf ├── qc001.rtf ├── qc001521.rtf ├── qc011.rtf ├── qc511.rtf ├── qc521.rtf ├── qd011.rtf ├── qd011061.rtf ├── qd021.rtf ├── qd031.rtf ├── qd041.rtf ├── qd051.rtf ├── qd061.rtf ├── qd071.rtf ├── qd071181.rtf ├── qd081.rtf ├── qd091.rtf ├── qd101.rtf ├── qd111.rtf ├── qd121.rtf ├── qd131.rtf ├── qd141.rtf ├── qd161.rtf ├── qd171.rtf ├── qd181.rtf ├── template.rtf └── template2.rtf ├── COPYING ├── FLL.vhd ├── FLVL.vhd ├── FMD2030_5-01A-B.vhd ├── FMD2030_5-01C-D.vhd ├── FMD2030_5-02A-B.vhd ├── FMD2030_5-03A.vhd ├── FMD2030_5-03B.vhd ├── FMD2030_5-03C.vhd ├── FMD2030_5-03D.vhd ├── FMD2030_5-04A-B.vhd ├── FMD2030_5-04C.vhd ├── FMD2030_5-04D.vhd ├── FMD2030_5-05A.vhd ├── FMD2030_5-05B.vhd ├── FMD2030_5-05C.vhd ├── FMD2030_5-05D.vhd ├── FMD2030_5-06A-B.vhd ├── FMD2030_5-06C-D.vhd ├── FMD2030_5-07A1.vhd ├── FMD2030_5-07A2.vhd ├── FMD2030_5-07B1.vhd ├── FMD2030_5-07B2.vhd ├── FMD2030_5-07B_2.vhd ├── FMD2030_5-07C.vhd ├── FMD2030_5-08A.vhd ├── FMD2030_5-08A1.vhd ├── FMD2030_5-08A2.vhd ├── FMD2030_5-08B.vhd ├── FMD2030_5-08C.vhd ├── FMD2030_5-08D.vhd ├── FMD2030_5-09C.vhd ├── FMD2030_5-10A.vhd ├── FMD2030_5-10B.vhd ├── FMD2030_5-10C.vhd ├── FMD2030_5-10D.vhd ├── FMD2030_UDC1.vhd ├── FMD2030_UDC2.vhd ├── FMD2030_UDC3.vhd ├── Gates2030.vhd ├── IBM2030.xise ├── PH.vhd ├── PROM_reader_serial.vhd ├── README ├── README.md ├── README.md~ ├── RS232RefComp.vhd ├── Testbench_panel_LEDs.vhd ├── Testbench_panel_Switches.vhd ├── ccros.c ├── ccros.vhd ├── ccros20100715.txt ├── ccros20120318.txt ├── ccros20210925.txt ├── clock_management.vhd ├── cpu.vhd ├── digilentSP3.ucf ├── ibm1050.vhd ├── ibm2030-cpu.vhd ├── ibm2030-storage.vhd ├── ibm2030-switches.vhd ├── ibm2030-vga.vhd ├── ibm2030.bit ├── ibm2030.vhd ├── panel_LEDs.vhd ├── panel_Switches.vhd ├── shift_compare_serial.vhd └── vga_controller_640_60.vhd /.gitignore: -------------------------------------------------------------------------------- 1 | xst/ 2 | _xmsgs/ 3 | iseconfig/ 4 | isim/ 5 | *.gise 6 | *.xise 7 | *.cmd_log 8 | *.lso 9 | *.prj 10 | *.syr 11 | *.xst 12 | *.xml 13 | *.log 14 | *.xise 15 | *.bgn 16 | *.bld 17 | *.drc 18 | *.ncd 19 | *.ngr 20 | *.ngd 21 | *.ngc 22 | *.pad 23 | *.par 24 | *.pcf 25 | *.ptwx 26 | *.stx 27 | *.twr 28 | *.twx 29 | *.unroutes 30 | *.ut 31 | *.xpi 32 | *.xwbt 33 | *.html 34 | *_map.* 35 | *_ngdbuild. 36 | *_pad.* 37 | *._par. 38 | *.xrpt 39 | *_beh.* 40 | fuse* 41 | *.cmd 42 | xilinxsim.* 43 | _ngo/ 44 | xlnx_auto* -------------------------------------------------------------------------------- /7seg_LEDs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/7seg_LEDs.vhd -------------------------------------------------------------------------------- /Buses2030.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: buses2030.vhd 23 | -- Creation Date: 24 | -- Description: 25 | -- This file defines various system-wide buses 26 | -- 27 | -- Revision History: 28 | -- Revision 1.0 2010-07-09 29 | -- Initial Release 30 | -- Revision 1.1 2012-04-07 31 | -- Add Storage and 1050 interfaces 32 | --------------------------------------------------------------------------- 33 | LIBRARY ieee; 34 | USE ieee.std_logic_1164.all; 35 | use ieee.numeric_std.all; 36 | 37 | 38 | -- This package defines various common buses and structures 39 | package Buses_package is 40 | 41 | -- SALS Bus is the microcode word 42 | type SALS_Bus is record 43 | SALS_PN : STD_LOGIC; 44 | SALS_CN : STD_LOGIC_VECTOR(0 to 5); 45 | SALS_PS : STD_LOGIC; 46 | SALS_PA : STD_LOGIC; 47 | SALS_CH : STD_LOGIC_VECTOR(0 to 3); 48 | SALS_CL : STD_LOGIC_VECTOR(0 to 3); 49 | SALS_CM : STD_LOGIC_VECTOR(0 to 2); 50 | SALS_CU : STD_LOGIC_VECTOR(0 to 1); 51 | SALS_CA : STD_LOGIC_VECTOR(0 to 3); 52 | SALS_CB : STD_LOGIC_VECTOR(0 to 1); 53 | SALS_CK : STD_LOGIC_VECTOR(0 to 3); 54 | SALS_PK : STD_LOGIC; 55 | SALS_PC : STD_LOGIC; 56 | SALS_CD : STD_LOGIC_VECTOR(0 to 3); 57 | SALS_CF : STD_LOGIC_VECTOR(0 to 2); 58 | SALS_CG : STD_LOGIC_VECTOR(0 to 1); 59 | SALS_CV : STD_LOGIC_VECTOR(0 to 1); 60 | SALS_CC : STD_LOGIC_VECTOR(0 to 2); 61 | SALS_CS : STD_LOGIC_VECTOR(0 to 3); 62 | SALS_AA : STD_LOGIC; 63 | SALS_SA : STD_LOGIC; 64 | SALS_AK : STD_LOGIC; 65 | end record SALS_Bus; 66 | 67 | -- The CTRL register is a subset of the SALS which is maintained 68 | -- after the rest of the SALS is cleared as the next word is read 69 | type CTRL_REG is record 70 | CTRL_CD : STD_LOGIC_VECTOR(0 to 3); -- 05C 71 | STRAIGHT : STD_LOGIC; -- Similar to CF(0) inverted 72 | CROSSED : STD_LOGIC; -- Same as CF(0) 73 | CTRL_CC : STD_LOGIC_VECTOR(0 to 2); -- CTRL REG BUS 74 | GT_A_REG_HI : STD_LOGIC; -- Same as CF(1) 75 | GT_A_REG_LO : STD_LOGIC; -- Same as CF(2) 76 | COMPUTE_CY_LCH : STD_LOGIC; -- 06C & CTRL REG BUS 77 | CTRL_CG : STD_LOGIC_VECTOR(0 to 1); -- 03B,06B & CTRL_REG_BUS 78 | GT_B_REG_HI : STD_LOGIC; -- 06B, same as CG(0) 79 | GT_B_REG_LO : STD_LOGIC; -- 06B, same as CG(1) 80 | CTRL_CV : STD_LOGIC_VECTOR(0 to 1); -- CTRL REG BUS 81 | CTRL_CS : STD_LOGIC_VECTOR(0 to 3); -- CTRL REG BUS 82 | end record CTRL_REG; 83 | 84 | -- The Priority bus is used to vector the microcode address when an external 85 | -- interrupt occurs 86 | type PRIORITY_BUS_Type is record 87 | STOP_PULSE : STD_LOGIC; -- X0 88 | PROTECT_PULSE : STD_LOGIC; -- X1 89 | WRAP_PULSE : STD_LOGIC; -- X2 90 | MPX_SHARE_PULSE : STD_LOGIC; -- X3 91 | SX_CHAIN_PULSE : STD_LOGIC; -- X4 92 | MACH_CHK_PULSE : STD_LOGIC; -- X5 93 | IPL_PULSE : STD_LOGIC; -- X6 94 | FORCE_IJ_PULSE : STD_LOGIC; -- X7 95 | PRIORITY_PULSE : STD_LOGIC; -- XP 96 | end record PRIORITY_BUS_Type; 97 | 98 | -- The E Switch bus contains the various signals corresponding to the legends on the 99 | -- selector switch. Only one of these signals will be true. 100 | type E_SW_BUS_Type is record 101 | -- Inner ring 102 | I_SEL,J_SEL,U_SEL,V_SEL,L_SEL,T_SEL,D_SEL,R_SEL,S_SEL,G_SEL,H_SEL,FI_SEL,FT_SEL : STD_LOGIC; 103 | -- Mid ring 104 | MS_SEL, LS_SEL : STD_LOGIC; -- LS marked as AS on dial 105 | -- Outer ring 106 | Q_SEL,C_SEL,F_SEL,TT_SEL,TI_SEL,JI_SEL, 107 | E_SEL_SW_GS,E_SEL_SW_GT,E_SEL_SW_GUV_GCD, 108 | E_SEL_SW_HS,E_SEL_SW_HT,E_SEL_SW_HUV_HCD : STD_LOGIC; 109 | end record E_SW_BUS_Type; 110 | 111 | -- Mpx Tags Out are the tag signals from the CPU to a peripheral 112 | type MPX_TAGS_OUT is record 113 | OPL_OUT, 114 | ADR_OUT, 115 | ADR_OUT2, -- What is this? 116 | CMD_OUT, 117 | STA_OUT, 118 | SRV_OUT, 119 | HLD_OUT, 120 | SEL_OUT, 121 | SUP_OUT, 122 | MTR_OUT, 123 | CLK_OUT : STD_LOGIC; 124 | end record MPX_TAGS_OUT; 125 | 126 | -- Mpx Tags In are the tag signals from a peripheral to the CPU 127 | type MPX_TAGS_IN is record 128 | OPL_IN, 129 | ADR_IN, 130 | STA_IN, 131 | SRV_IN, 132 | SEL_IN, 133 | REQ_IN, 134 | MTR_IN : STD_LOGIC; 135 | end record MPX_TAGS_IN; 136 | 137 | -- List of front panel indicators 138 | subtype IndicatorRange is integer range 0 to 249; -- 218 through 249 are temp debug items 139 | 140 | type STORAGE_IN_INTERFACE is record 141 | ReadData : std_logic_vector(0 to 8); 142 | end record STORAGE_IN_INTERFACE; 143 | 144 | type STORAGE_OUT_INTERFACE is record 145 | MSAR : std_logic_vector(0 to 15); 146 | MainStorage : std_logic; 147 | WritePulse : std_logic; 148 | ReadPulse : std_logic; 149 | WriteData : std_logic_vector(0 to 8); 150 | end record STORAGE_OUT_INTERFACE; 151 | 152 | -- CE connections on 1050 interface 153 | type CE_IN is record 154 | CE_BIT : STD_LOGIC_VECTOR(0 to 7); 155 | CE_MODE : STD_LOGIC; 156 | CE_TI_OR_TE_RUN_MODE : STD_LOGIC; 157 | CE_SEL_OUT : STD_LOGIC; 158 | CE_EXIT_MPLX_SHARE : STD_LOGIC; 159 | CE_DATA_ENTER_NO : STD_LOGIC; 160 | CE_DATA_ENTER_NC : STD_LOGIC; 161 | CE_TI_DECODE : STD_LOGIC; 162 | CE_TE_DECODE : STD_LOGIC; 163 | CE_TA_DECODE : STD_LOGIC; 164 | CE_RESET : STD_LOGIC; 165 | end record CE_IN ; 166 | 167 | type CE_OUT is record 168 | PTT_BITS : STD_LOGIC_VECTOR(0 to 6); 169 | DATA_REG : STD_LOGIC_VECTOR(0 to 7); 170 | RDR_1_CLUTCH : STD_LOGIC; 171 | WRITE_UC : STD_LOGIC; 172 | XLATE_UC : STD_LOGIC; 173 | PUNCH_1_CLUTCH : STD_LOGIC; 174 | NPL : STD_LOGIC_VECTOR(0 to 7); 175 | OUTPUT_SEL_AND_RDY : STD_LOGIC; 176 | TT : STD_LOGIC_VECTOR(0 to 7); 177 | CPU_REQUEST_IN : STD_LOGIC; 178 | n1050_OP_IN : STD_LOGIC; 179 | HOME_RDR_STT_LCH : STD_LOGIC; 180 | RDR_ON_LCH : STD_LOGIC; 181 | MICRO_SHARE_LCH : STD_LOGIC; 182 | PROCEED_LCH : STD_LOGIC; 183 | TA_REG_POS_4 : STD_LOGIC; 184 | CR_LF : STD_LOGIC; 185 | TA_REG_POS_6 : STD_LOGIC; 186 | n1050_RST : STD_LOGIC; 187 | end record CE_OUT; 188 | 189 | type PCH_CONN is record -- serialIn @ 1050 -> CPU signals 190 | -- Input device (keyboard) input connections: 191 | PCH_BITS : STD_LOGIC_VECTOR(0 to 6); 192 | PCH_1_CLUTCH_1050 : STD_LOGIC; 193 | -- Output device (printer) input connections: 194 | RDR_2_READY : STD_LOGIC; 195 | HOME_RDR_STT_LCH : STD_LOGIC; 196 | HOME_OUTPUT_DEV_RDY : STD_LOGIC; 197 | RDR_1_CLUTCH_1050 : STD_LOGIC; 198 | -- Other inputs 199 | CPU_CONNECTED : STD_LOGIC; 200 | REQ_KEY : STD_LOGIC; 201 | end record PCH_CONN; 202 | 203 | type RDR_CONN is record -- serialOut : CPU -> 1050 signals 204 | -- Output device (printer) output connections: 205 | RDR_BITS : STD_LOGIC_VECTOR(0 to 6); 206 | RD_STROBE : STD_LOGIC; 207 | end record RDR_CONN; 208 | 209 | type CONN_1050 is record -- serialControl : CPU -> 1050 signals 210 | n1050_RST_LCH, 211 | n1050_RESET, 212 | HOME_RDR_START, 213 | PROCEED, 214 | RDR_2_HOLD, 215 | CARR_RETURN_AND_LINE_FEED, 216 | RESTORE : STD_LOGIC; 217 | end record CONN_1050; 218 | 219 | type Serial_Output_Lines is record 220 | SerialTx : STD_LOGIC; -- Printer data 221 | RTS : STD_LOGIC; -- Request to send - Keyboard ok to send 222 | DTR : STD_LOGIC; -- Data terminal ready - Printer activated 223 | end record Serial_Output_Lines; 224 | 225 | type Serial_Input_Lines is record 226 | SerialRx : STD_LOGIC; 227 | DCD : STD_LOGIC; -- Carrier Detect - Keyboard ready 228 | DSR : STD_LOGIC; -- Data Set Ready - 1050 Ready 229 | RI : STD_LOGIC; -- Ring Indicator - Unused 230 | CTS : STD_LOGIC; -- Clear to send - Printer ready to accept data 231 | end record Serial_Input_Lines; 232 | 233 | type DEBUG_BUS is record 234 | Selection : integer range 0 to 15; 235 | Probe : STD_LOGIC; 236 | end record DEBUG_BUS; 237 | 238 | end package Buses_package; 239 | -------------------------------------------------------------------------------- /CLD/qa221.rtf: -------------------------------------------------------------------------------- 1 | {\rtf1\fbidis\ansi\ansicpg1252\deff0\deftab709{\fonttbl{\f0\fmodern\fprq1\fcharset0 Courier New;}} 2 | \viewkind4\uc1\pard\ltrpar\lang1033\f0\fs14 0 1 2 3 4 5 6 7 8 9\par 3 | \par 4 | \par 5 | This page causes an invalid op prg int to occur \par 6 | if read or write direct is attempted on a machine \par 7 | A without the direct control feature installed The \par 8 | reamining words in the prg are shown since they \par 9 | are part of the basic ROS, however, they can be \par 10 | entered only if a malfunction occurs. \par 11 | \par 12 | \par 13 | B\par 14 | \par 15 | \par 16 | \par 17 | \par 18 | C \par 19 | \par 20 | \par 21 | \par 22 | \par 23 | \par 24 | D\par 25 | \par 26 | 11 --- XXX\par 27 | | Go to |\par 28 | | QA879.CAE | \par 29 | E ----| | \par 30 | | | | \par 31 | | | |\par 32 | | | |\par 33 | | E9-- 11 --EJ\par 34 | --------------------------------------------------------------------------------------------------------------------------------------- Prg Int\par 35 | F | \par 36 | | \par 37 | 11 --- 03DF | \par 38 | K 0001,0 | | \par 39 | A 0+0+1>L | | \par 40 | G QA911.QDE----------------------------------*S WRITE K>W R*- \par 41 | (11) | | \par 42 | Direct Control | | \par 43 | R 1,1 47R \par 44 | G2-- 11 --GB \par 45 | Invalid op, direct\par 46 | H control is not\par 47 | installed.\par 48 | \par 49 | \par 50 | \par 51 | J \par 52 | \par 53 | \par 54 | \par 55 | \par 56 | \par 57 | K\par 58 | \par 59 | \par 60 | \par 61 | \par 62 | L \par 63 | \par 64 | \par 65 | \par 66 | \par 67 | \par 68 | M\par 69 | \par 70 | \par 71 | \par 72 | \par 73 | N \par 74 | \par 75 | \par 76 | \par 77 | \par 78 | \par 79 | P\par 80 | \par 81 | \par 82 | \par 83 | \par 84 | Q \par 85 | \par 86 | \par 87 | \par 88 | \par 89 | \par 90 | R\par 91 | \par 92 | \par 93 | \par 94 | \par 95 | S\par 96 | \par 97 | Q\par 98 | A\par 99 | 2\par 100 | 2 | 128015 08/24/65 | Mach 2030 | Date 11/17/65 Sheet 1 QA221 |\par 101 | 1 | 128045 11/17/65 | Name | Log 3563 Version |\par 102 | | | Mode Manual | |\par 103 | | | P.N. 837016 | Read and Write Direct |\par 104 | | | IBM Corp. | Invalid op |\par 105 | } 106 | -------------------------------------------------------------------------------- /FLL.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:25:51 06/17/2015 6 | -- Design Name: 7 | -- Module Name: FLL - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- FLL is a level-triggered SR flip-flop 24 | 25 | entity FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end; 26 | 27 | architecture slt of FLL is 28 | begin 29 | process(S,R) 30 | begin 31 | if (S='1') then -- Set takes priority 32 | Q<='1' after 1ns; 33 | elsif (R='1') then 34 | Q<='0' after 1ns; 35 | end if; 36 | end process; 37 | end slt; 38 | 39 | 40 | -------------------------------------------------------------------------------- /FLVL.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:35:52 06/17/2015 6 | -- Design Name: 7 | -- Module Name: FLVL - slt 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | entity FLVL is port( S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR); end; 24 | 25 | architecture slt of FLVL is 26 | alias S1 : STD_LOGIC_VECTOR(Q'range) is S; 27 | alias R1 : STD_LOGIC_VECTOR(Q'range) is R; 28 | begin 29 | process (S1,R1) 30 | begin 31 | for i in Q'range loop 32 | if (S1(i)='1') then -- Set takes priority 33 | Q(i)<='1'; 34 | elsif (R1(i)='1') then 35 | Q(i)<='0'; 36 | end if; 37 | end loop; 38 | end process; 39 | end slt; 40 | 41 | -------------------------------------------------------------------------------- /FMD2030_5-01C-D.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-01C-D.vhd 23 | -- Creation Date: 24 | -- Description: 25 | -- CCROS storage, SALS (Sense Amplifier Latches), CTRL register 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-13 35 | -- Initial Release 36 | -- Revision 1.1 2012-04-07 37 | -- Change CCROS initialisation 38 | --------------------------------------------------------------------------- 39 | LIBRARY ieee; 40 | USE ieee.std_logic_1164.all; 41 | USE ieee.std_logic_arith.all; 42 | USE std.textio.all; 43 | 44 | library work; 45 | use work.Gates_package.all; 46 | use work.Buses_package.all; 47 | library CCROS; 48 | use CCROS.CCROS.all; 49 | 50 | ENTITY CCROS IS 51 | port 52 | ( 53 | -- Inputs 54 | WX : IN STD_LOGIC_VECTOR(0 to 12); -- 01B 55 | MACH_RST_SW : IN STD_LOGIC; -- 03D 56 | MANUAL_STORE : IN STD_LOGIC; -- 03D 57 | ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A 58 | COMPUTE : IN STD_LOGIC; -- 04D 59 | MACH_RST_MPX : IN STD_LOGIC; -- 08C 60 | 61 | CROS_STROBE : IN STD_LOGIC; -- 01B 62 | CROS_GO_PULSE : IN STD_LOGIC; -- 01B 63 | 64 | -- Outputs 65 | SALS: OUT SALS_Bus; 66 | CTRL : OUT CTRL_REG; 67 | CTRL_REG_RST : OUT STD_LOGIC; -- 07B 68 | CK_SAL_P_BIT_TO_MPX : OUT STD_LOGIC; -- ? 69 | 70 | -- Clocks 71 | T1 : IN STD_LOGIC; 72 | P1 : IN STD_LOGIC; 73 | Clk : IN STD_LOGIC -- 50MHz 74 | ); 75 | END CCROS; 76 | 77 | ARCHITECTURE FMD OF CCROS IS 78 | 79 | signal SALS_Word : STD_LOGIC_VECTOR(0 to 54) := (others=>'1'); 80 | 81 | alias SALS_PN : STD_LOGIC is SALS_Word(0); 82 | alias SALS_CN : STD_LOGIC_VECTOR(0 to 5) is SALS_Word(1 to 6); 83 | alias SALS_PS : STD_LOGIC is SALS_Word(7); 84 | alias SALS_PA : STD_LOGIC is SALS_Word(8); 85 | alias SALS_CH : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(9 to 12); 86 | alias SALS_CL : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(13 to 16); 87 | alias SALS_CM : STD_LOGIC_VECTOR(0 to 2) is SALS_Word(17 to 19); 88 | alias SALS_CU : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(20 to 21); 89 | alias SALS_CA : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(22 to 25); 90 | alias SALS_CB : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(26 to 27); 91 | alias SALS_CK : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(28 to 31); 92 | alias SALS_PK : STD_LOGIC is SALS_Word(32); 93 | alias SALS_PC : STD_LOGIC is SALS_Word(33); 94 | alias SALS_CD : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(34 to 37); 95 | alias SALS_CF : STD_LOGIC_VECTOR(0 to 2) is SALS_Word(38 to 40); 96 | alias SALS_CG : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(41 to 42); 97 | alias SALS_CV : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(43 to 44); 98 | alias SALS_CC : STD_LOGIC_VECTOR(0 to 2) is SALS_Word(45 to 47); 99 | alias SALS_CS : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(48 to 51); 100 | alias SALS_AA : STD_LOGIC is SALS_Word(52); 101 | alias SALS_SA : STD_LOGIC is SALS_Word(53); 102 | alias SALS_AK : STD_LOGIC is SALS_Word(54); 103 | 104 | constant CCROS : CCROS_Type := Package_CCROS; 105 | -- constant CCROS : CCROS_Type := readCCROS; 106 | 107 | signal AUX_CTRL_REG_RST : STD_LOGIC; 108 | signal SET_CTRL_REG : STD_LOGIC; 109 | signal sCTRL : CTRL_REG; 110 | signal sCTRL_REG_RST : STD_LOGIC; 111 | 112 | signal CD_LCH_Set,CD_LCH_Reset,CS_LCH_Set,CS_LCH_Reset : STD_LOGIC_VECTOR(0 to 3); 113 | signal STRAIGHT_LCH_Set,CROSSED_LCH_Set,CC2_LCH_Set,CC2_LCH_Reset,GTAHI_LCH_Set,GTAHI_LCH_Reset, 114 | GTALO_LCH_Set,GTALO_LCH_Reset,COMPCY_LCH_Set,COMPCY_LCH_Reset,CG0_Set,CG1_Set,CG_Reset : STD_LOGIC; 115 | signal CV_LCH_Set,CV_LCH_Reset,CC01_LCH_Set,CC01_LCH_Reset : STD_LOGIC_VECTOR(0 to 1); 116 | signal CROS_STROBE_DELAY : STD_LOGIC_VECTOR(1 to 6) := "000000"; 117 | BEGIN 118 | 119 | -- Page 5-01C 120 | sCTRL_REG_RST <= MACH_RST_SW or MANUAL_STORE or ANY_PRIORITY_LCH; 121 | CTRL_REG_RST <= sCTRL_REG_RST; 122 | AUX_CTRL_REG_RST <= T1 or sCTRL_REG_RST; 123 | SET_CTRL_REG <= not ANY_PRIORITY_LCH and P1; 124 | 125 | CD_LCH_Set <= SALS_CD and (0 to 3 => SET_CTRL_REG); 126 | CD_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST); 127 | CD_LCH: FLVL port map(CD_LCH_Set,CD_LCH_Reset,sCTRL.CTRL_CD); -- AA2C6 128 | 129 | STRAIGHT_LCH_Set <= sCTRL_REG_RST or (SET_CTRL_REG and not SALS_CF(0)); 130 | STRAIGHT_LCH: entity work.FLL port map(STRAIGHT_LCH_Set, T1, sCTRL.STRAIGHT); 131 | CROSSED_LCH_Set <= SET_CTRL_REG and SALS_CF(0); 132 | CROSSED_LCH: entity work.FLL port map(CROSSED_LCH_Set, AUX_CTRL_REG_RST, sCTRL.CROSSED); 133 | 134 | CC2_LCH_Set <= SET_CTRL_REG and SALS_CC(2); 135 | CC2_LCH_Reset <= T1 or sCTRL_REG_RST; 136 | CC2_LCH: entity work.FLL port map(CC2_LCH_Set, CC2_LCH_Reset, sCTRL.CTRL_CC(2)); 137 | GTAHI_LCH_Set <= SET_CTRL_REG and SALS_CF(1); 138 | GTAHI_LCH_Reset <= T1 or sCTRL_REG_RST; 139 | GTAHI_LCH: entity work.FLL port map(GTAHI_LCH_Set, GTAHI_LCH_Reset, sCTRL.GT_A_REG_HI); 140 | GTALO_LCH_Set <= SET_CTRL_REG and SALS_CF(2); 141 | GTALO_LCH_Reset <= T1 or sCTRL_REG_RST; 142 | GTALO_LCH: entity work.FLL port map(GTALO_LCH_Set, GTALO_LCH_Reset, sCTRL.GT_A_REG_LO); 143 | COMPCY_LCH_Set <= SET_CTRL_REG and COMPUTE; 144 | COMPCY_LCH_Reset <= T1 or sCTRL_REG_RST; 145 | COMPCY_LCH: entity work.FLL port map(COMPCY_LCH_Set, COMPCY_LCH_Reset, sCTRL.COMPUTE_CY_LCH); 146 | 147 | CG0_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(0)); 148 | CG_Reset <= T1 or (MACH_RST_SW or ANY_PRIORITY_LCH); -- ?? Required to prevent simultaneous Set & Reset of CG by MANUAL_STORE 149 | CG0: entity work.FLL port map(CG0_Set, CG_Reset, sCTRL.CTRL_CG(0)); sCTRL.GT_B_REG_HI <= sCTRL.CTRL_CG(0); 150 | CG1_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(1)); 151 | CG1: entity work.FLL port map(CG1_Set, CG_Reset, sCTRL.CTRL_CG(1)); sCTRL.GT_B_REG_LO <= sCTRL.CTRL_CG(1); 152 | 153 | CV_LCH_Set <= SALS_CV and (0 to 1 => SET_CTRL_REG); 154 | CV_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST); 155 | CV_LCH: entity work.FLVL port map(CV_LCH_Set,CV_LCH_Reset,sCTRL.CTRL_CV); -- AA2D6 156 | CC01_LCH_Set <= SALS_CC(0 to 1) and (0 to 1 => SET_CTRL_REG); 157 | CC01_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST); 158 | CC01_LCH: entity work.FLVL port map(CC01_LCH_Set,CC01_LCH_Reset,sCTRL.CTRL_CC(0 to 1)); -- AA2D6 159 | 160 | CS_LCH_Set <= SALS_CS and (0 to 3 => SET_CTRL_REG); 161 | CS_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST); 162 | CS_LCH: entity work.FLVL port map(CS_LCH_Set,CS_LCH_Reset,sCTRL.CTRL_CS); -- AA2D7 163 | CTRL <= sCTRL; 164 | 165 | CK_SAL_P_BIT_TO_MPX <= SALS_PK and not MACH_RST_MPX; 166 | 167 | -- Page 5-01D 168 | -- CCROS microcode storage 169 | -- Start of read is CROS_GO_PULSE 170 | -- End of read is CCROS_STROBE 171 | -- Should use falling edge of CCROS_STROBE to gate data from CCROS into SALS (actually happens earlier) 172 | CCROS_RESET_SET: process (Clk,CROS_STROBE,CROS_GO_PULSE,WX) 173 | begin 174 | -- Reset SALS when CROS_GO_PULSE goes Low 175 | -- Set SALS 100ns after CROS_STROBE goes High (start of T3) 176 | -- ROAR should have been set during T1 so we have a 1.5 minor cycle (~280ns) access time 177 | if (Clk'Event and Clk='1') then 178 | -- if (CROS_STROBE='1' and CROS_STROBE_DELAY="10000") then 179 | --SALS_Word <= (others => '0'); 180 | -- else 181 | if (CROS_STROBE='1' and CROS_STROBE_DELAY="111100") then 182 | SALS_Word <= CCROS(CCROS_Address_Type(conv_integer(unsigned(WX(1 to 12))))); 183 | -- end if; 184 | end if; 185 | CROS_STROBE_DELAY <= CROS_STROBE & CROS_STROBE_DELAY(1 to 5); 186 | end if; 187 | end process; 188 | 189 | SALS.SALS_PN <= SALS_PN; 190 | SALS.SALS_CN <= SALS_CN; 191 | SALS.SALS_PS <= SALS_PS; 192 | SALS.SALS_PA <= SALS_PA; 193 | SALS.SALS_CH <= SALS_CH; 194 | SALS.SALS_CL <= SALS_CL; 195 | SALS.SALS_CM <= SALS_CM; 196 | SALS.SALS_CU <= SALS_CU; 197 | SALS.SALS_CA <= SALS_CA; 198 | SALS.SALS_CB <= SALS_CB; 199 | SALS.SALS_CK <= SALS_CK; 200 | SALS.SALS_PK <= SALS_PK; 201 | SALS.SALS_PC <= SALS_PC; 202 | SALS.SALS_CD <= SALS_CD; 203 | SALS.SALS_CF <= SALS_CF; 204 | SALS.SALS_CG <= SALS_CG; 205 | SALS.SALS_CV <= SALS_CV; 206 | SALS.SALS_CC <= SALS_CC; 207 | SALS.SALS_CS <= SALS_CS; 208 | SALS.SALS_AA <= SALS_AA; 209 | SALS.SALS_SA <= SALS_SA; 210 | SALS.SALS_AK <= SALS_AK; 211 | 212 | END FMD; 213 | 214 | -------------------------------------------------------------------------------- /FMD2030_5-02A-B.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-02A-B.vhd 23 | -- Creation Date: 24 | -- Description: 25 | -- X6,X7 assembly, ASCII latch, X6,X7 backup (5-02A), WX reg gating (5-02B) 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-09 35 | -- Initial Release 36 | -- Revision 1.1 2012-04-07 37 | -- Enable MPX interruptions 38 | --------------------------------------------------------------------------- 39 | LIBRARY ieee; 40 | USE ieee.std_logic_1164.all; 41 | USE ieee.std_logic_unsigned.all; 42 | 43 | library work; 44 | use work.Gates_package.all; 45 | use work.Buses_package.all; 46 | 47 | ENTITY X6X7 IS 48 | port 49 | ( 50 | SALS : IN SALS_Bus; -- 01C 51 | DECIMAL : IN STD_LOGIC; -- 06B 52 | CONNECT : IN STD_LOGIC; -- 06B 53 | N_CTRL_LM : IN STD_LOGIC; -- 06B 54 | CTRL_N : IN STD_LOGIC; -- 06B 55 | R_REG_0_BIT : IN STD_LOGIC; -- 06C 56 | V67_00_OR_GM_WM : IN STD_LOGIC; -- 05A 57 | STATUS_IN_LCHD : IN STD_LOGIC; -- 06A 58 | OPNL_IN_LCHD : IN STD_LOGIC; -- 06A 59 | CARRY_0_LCHD : IN STD_LOGIC; -- 06A 60 | S_REG_1_OR_R_REG_2 : IN STD_LOGIC; -- 05A 61 | S : IN STD_LOGIC_VECTOR(0 to 7); -- 07B 62 | G : IN STD_LOGIC_VECTOR(0 to 7); -- 05C 63 | TIMER_UPDATE : IN STD_LOGIC; -- 04C 64 | EXTERNAL_INT : IN STD_LOGIC; -- 04C 65 | MPX_INTERRUPT : IN STD_LOGIC; -- 08C 66 | SX1_INTERRUPT : IN STD_LOGIC; -- 12D 67 | SX2_INTERRUPT : IN STD_LOGIC; -- 14D 68 | -- HSMPX : IN STD_LOGIC; -- XXXXX 69 | I_WRAPPED_CPU : IN STD_LOGIC; -- 03B 70 | TIMER_UPDATE_OR_EXT_INT : IN STD_LOGIC; -- 04C 71 | U_WRAPPED_MPX : IN STD_LOGIC; -- 03B 72 | H_REG_6_BIT : IN STD_LOGIC; -- 04C 73 | ADDR_IN_LCHD : IN STD_LOGIC; -- 06A 74 | SERV_IN_LCHD : IN STD_LOGIC; -- 06A 75 | R_REG_VAL_DEC_DIG : IN STD_LOGIC; -- 05A 76 | N1BC_OR_R1 : IN STD_LOGIC; -- 05A 77 | Z_BUS_0 : IN STD_LOGIC; -- 06B 78 | G_REG_1_OR_R_REG_3 : IN STD_LOGIC; -- 05A 79 | GT_BU_ROSAR_TO_WX_REG : IN STD_LOGIC; -- 01B 80 | H_REG_5_PWR : IN STD_LOGIC; -- 04C 81 | MPX_SHARE_PULSE : IN STD_LOGIC; -- 03A 82 | SX_CHAIN_PULSE : IN STD_LOGIC; -- 03A 83 | MACH_RST_SW : IN STD_LOGIC; -- 03D 84 | R_REG_4_BIT : IN STD_LOGIC; -- 06C 85 | ANY_PRIORITY_PULSE : IN STD_LOGIC; -- 03A 86 | 87 | -- Outputs 88 | XOR_OR_OR : OUT STD_LOGIC; -- 03A,04A 89 | INTERRUPT : OUT STD_LOGIC; -- 01B 90 | GT_GWX_TO_WX_REG : OUT STD_LOGIC; -- 01B 91 | GT_FWX_TO_WX_REG : OUT STD_LOGIC; -- 01B 92 | USE_CA_BASIC_DECODER : OUT STD_LOGIC; -- 02B,01A,03C,04C,05C,07A,07C,10C 93 | MPX_ROS_LCH : OUT STD_LOGIC; -- 08C 94 | X6 : OUT STD_LOGIC; 95 | X7 : OUT STD_LOGIC; 96 | USE_ALT_CA_DECODER : OUT STD_LOGIC; -- 07C,04C,10C,07A,11C 97 | GT_CA_TO_W_REG : OUT STD_LOGIC; -- 01B,07A 98 | GT_UV_TO_WX_REG : OUT STD_LOGIC; -- 01B 99 | DIAG_LATCH_RST : OUT STD_LOGIC; -- NEW 100 | -- Debug 101 | DEBUG : OUT STD_LOGIC; 102 | 103 | -- Clocks 104 | T1,T2,T3,T4 : IN STD_LOGIC; 105 | clk : IN STD_LOGIC 106 | ); 107 | END X6X7; 108 | 109 | ARCHITECTURE FMD OF X6X7 IS 110 | 111 | signal TEST_ASCII : STD_LOGIC; 112 | signal TEST_INTRP : STD_LOGIC; 113 | signal TEST_WRAP : STD_LOGIC; 114 | signal GT_ASCII_LCH : STD_LOGIC; 115 | signal GT_MPX_LCH : STD_LOGIC; -- Output of AA3E3 116 | signal GT_SX_LCH : STD_LOGIC; -- Output of AA3L6 117 | signal X6_MUX,X7_MUX : STD_LOGIC; 118 | signal CA_TO_X7_DECO : STD_LOGIC; 119 | signal X6_BRANCH,X7_BRANCH : STD_LOGIC; 120 | signal SX_CH_ROAR_RESTORE : STD_LOGIC; 121 | signal MPX_CH_ROAR_RESTORE : STD_LOGIC; 122 | signal RESTORE_0 : STD_LOGIC; -- Output of AA3K5,FL0 123 | 124 | signal ASCII_LCH : STD_LOGIC; 125 | signal MPX_CH_X6,MPX_CH_X7 : STD_LOGIC; 126 | signal SX_CH_X6,SX_CH_X7 : STD_LOGIC; 127 | signal X6_DATA,X7_DATA : STD_LOGIC; 128 | signal STORED_X6,STORED_X7 : STD_LOGIC; 129 | signal sXOR_OR_OR : STD_LOGIC; 130 | signal sINTERRUPT : STD_LOGIC; 131 | signal sGT_GWX_TO_WX_REG : STD_LOGIC; 132 | signal sGT_FWX_TO_WX_REG : STD_LOGIC; 133 | signal sUSE_CA_BASIC_DECODER : STD_LOGIC; 134 | signal sMPX_ROS_LCH : STD_LOGIC; 135 | 136 | signal REST0_LCH_Set,REST0_LCH_Reset,SXREST_LCH_Set,SXREST_LCH_Reset, 137 | MPXROS_LCH_Reset,MPXROS_LCH_Set,MPXREST_LCH_Set,MPXREST_LCH_Reset : STD_LOGIC; 138 | BEGIN 139 | -- Fig 5-02A 140 | TEST_ASCII <= '1' when SALS.SALS_CK="1001" and SALS.SALS_AK='1' else '0'; -- AB3E7 141 | TEST_INTRP <= '1' when SALS.SALS_CK="1010" and SALS.SALS_AK='1' else '0'; -- AB3E7 142 | TEST_WRAP <= '1' when SALS.SALS_CK="0011" and SALS.SALS_AK='1' else '0'; -- AB3E6 143 | DIAG_LATCH_RST <= '1' when SALS.SALS_CK="0000" and SALS.SALS_AK='1' and T1='1' else '0'; -- NEW! 144 | 145 | sXOR_OR_OR <= DECIMAL and CONNECT and N_CTRL_LM; -- AB3D2 146 | XOR_OR_OR <= sXOR_OR_OR; 147 | GT_ASCII_LCH <= sXOR_OR_OR and CTRL_N and T2; -- AB3D2 148 | DEBUG <= ASCII_LCH; 149 | 150 | -- ?? Debug remove other interrupt sources 151 | -- sINTERRUPT <= TIMER_UPDATE or EXTERNAL_INT or MPX_INTERRUPT or SX1_INTERRUPT or SX2_INTERRUPT; -- AA3K4 152 | sINTERRUPT <= EXTERNAL_INT or MPX_INTERRUPT; 153 | INTERRUPT <= sINTERRUPT; 154 | 155 | 156 | with (SALS.SALS_CH) select X6_MUX <= -- AA3G5 157 | '1' when "0001", 158 | R_REG_0_BIT when "0010", 159 | V67_00_OR_GM_WM when "0011", 160 | STATUS_IN_LCHD when "0100", 161 | OPNL_IN_LCHD when "0101", 162 | CARRY_0_LCHD when "0110", 163 | S(0) when "0111", 164 | S_REG_1_OR_R_REG_2 when "1000", 165 | S(2) when "1001", 166 | S(4) when "1010", 167 | S(6) when "1011", 168 | G(0) when "1100", 169 | G(2) when "1101", 170 | G(4) when "1110", 171 | G(6) when "1111", 172 | '0' when others; -- 0000 173 | 174 | with (SALS.SALS_CL) select X7_MUX <= -- AA3H5 175 | '1' when "0001", 176 | '1' when "0010", -- CL=0010 is CA>W ?? Needed otherwise CA>W always forces X7 to 0 ?? 177 | ADDR_IN_LCHD when "0011", 178 | SERV_IN_LCHD when "0100", 179 | R_REG_VAL_DEC_DIG when "0101", 180 | N1BC_OR_R1 when "0110", 181 | Z_BUS_0 when "0111", 182 | G(7) when "1000", 183 | S(3) when "1001", 184 | S(5) when "1010", 185 | S(7) when "1011", 186 | G_REG_1_OR_R_REG_3 when "1100", 187 | G(3) when "1101", 188 | G(5) when "1110", 189 | sINTERRUPT when "1111", 190 | '0' when others; -- 0000 191 | 192 | 193 | X6_BRANCH <= (not ASCII_LCH or not TEST_ASCII) and -- AA3K3 194 | (not TIMER_UPDATE_OR_EXT_INT or not TEST_INTRP) and -- AA3K3 195 | (not SX2_INTERRUPT or SX1_INTERRUPT or not TEST_INTRP) and -- AA3K4 196 | (not I_WRAPPED_CPU or not TEST_WRAP) and -- AA3K3 197 | X6_MUX; 198 | 199 | X7_BRANCH <= (not TIMER_UPDATE_OR_EXT_INT or not TEST_INTRP) and -- AA3K3 200 | (not SX1_INTERRUPT or not TEST_INTRP) and -- AA3B7 201 | (not TEST_WRAP or not U_WRAPPED_MPX or not H_REG_6_BIT) and -- AA3J5 202 | X7_MUX ; 203 | -- and CA_TO_X7_DECO; ?? Removed as it forced X7 to 0 on CA>W ?? 204 | 205 | sGT_GWX_TO_WX_REG <= GT_BU_ROSAR_TO_WX_REG and H_REG_5_PWR; -- AA3L5 206 | GT_GWX_TO_WX_REG <= sGT_GWX_TO_WX_REG; 207 | sGT_FWX_TO_WX_REG <= GT_BU_ROSAR_TO_WX_REG and not H_REG_5_PWR; -- AA3C2 208 | GT_FWX_TO_WX_REG <= sGT_FWX_TO_WX_REG; 209 | 210 | sUSE_CA_BASIC_DECODER <= not SALS.SALS_AA; 211 | USE_CA_BASIC_DECODER <= sUSE_CA_BASIC_DECODER; 212 | 213 | REST0_LCH_Set <= T2 and sGT_GWX_TO_WX_REG; 214 | REST0_LCH_Reset <= MACH_RST_SW or T1; 215 | REST0_LCH: entity work.FLL port map(REST0_LCH_Set,REST0_LCH_Reset,RESTORE_0); -- AA3K5 Bit 0 216 | SXREST_LCH_Set <= T4 and RESTORE_0; 217 | SXREST_LCH_Reset <= MACH_RST_SW or T3; 218 | SXREST_LCH: entity work.FLL port map(SXREST_LCH_Set,SXREST_LCH_Reset,SX_CH_ROAR_RESTORE); -- AA3K5 Bit 1 219 | MPXROS_LCH_Set <= T2 and sGT_FWX_TO_WX_REG; 220 | MPXROS_LCH_Reset <= MACH_RST_SW or T1; 221 | MPXROS_LCH: entity work.FLL port map(MPXROS_LCH_Set,MPXROS_LCH_Reset,sMPX_ROS_LCH); -- AA3L2 Bit 2 222 | MPX_ROS_LCH <= sMPX_ROS_LCH; 223 | MPXREST_LCH_Set <= T4 and sMPX_ROS_LCH; 224 | MPXREST_LCH_Reset <= MACH_RST_SW or T3; 225 | MPXREST_LCH: entity work.FLL port map(MPXREST_LCH_Set,MPXREST_LCH_Reset,MPX_CH_ROAR_RESTORE); -- AA3L2 Bit 3 226 | 227 | X6_DATA <= X6_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6 228 | X7_DATA <= X7_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6 229 | 230 | GT_MPX_LCH <= (MPX_SHARE_PULSE and T1) or MACH_RST_SW; -- AA3L4,AA3E3 231 | GT_SX_LCH <= (SX_CHAIN_PULSE and T1) or MACH_RST_SW; -- AA3F3,AA3L6 232 | 233 | -- ASCII latch plus X6,X7 storage for 234 | ASC_LCH: entity work.PH port map(R_REG_4_BIT,GT_ASCII_LCH,ASCII_LCH); -- AA3L3 235 | M7_LCH: entity work.PH port map(X7_DATA,GT_MPX_LCH,MPX_CH_X7); -- AA3L3 236 | S7_LCH: entity work.PH port map(X7_DATA,GT_SX_LCH,SX_CH_X7); -- AA3L3 237 | M6_LCH: entity work.PH port map(X6_DATA,GT_MPX_LCH,MPX_CH_X6); -- AA3L3 238 | S6_LCH: entity work.PH port map(X6_DATA,GT_SX_LCH,SX_CH_X6); -- AA3L3 239 | 240 | STORED_X6 <= (SX_CH_ROAR_RESTORE and SX_CH_X6) or (MPX_CH_ROAR_RESTORE and MPX_CH_X6); -- AA3K6 241 | STORED_X7 <= (SX_CH_ROAR_RESTORE and SX_CH_X7) or (MPX_CH_ROAR_RESTORE and MPX_CH_X7); -- AA3K6 242 | 243 | X6 <= X6_DATA or STORED_X6; -- Wire-AND of negated signals 244 | X7 <= X7_DATA or STORED_X7; -- Wire-AND of negated signals 245 | 246 | -- Page 5-02B 247 | USE_ALT_CA_DECODER <= not sUSE_CA_BASIC_DECODER and not ANY_PRIORITY_PULSE; -- AB2F7 ?? 248 | CA_TO_X7_DECO <= '0' when SALS.SALS_CL="0010" else '1'; -- AA3H5 249 | GT_CA_TO_W_REG <= not CA_TO_X7_DECO and not ANY_PRIORITY_PULSE; -- AA3L4,AA3G4 250 | GT_UV_TO_WX_REG <= '1' when SALS.SALS_CK="0001" and SALS.SALS_AK='1' and ANY_PRIORITY_PULSE='0' else '0'; -- AB3E6,AB3B3 251 | 252 | END FMD; 253 | 254 | -------------------------------------------------------------------------------- /FMD2030_5-03A.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-03A.vhd 23 | -- Creation Date: 24 | -- Description: 25 | -- Priority (microcode interruptions) 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-13 35 | -- Initial Release 36 | -- Revision 1.1 2012-04-07 37 | -- Change Priority Reset latch signal name 38 | --------------------------------------------------------------------------- 39 | LIBRARY ieee; 40 | USE ieee.std_logic_1164.all; 41 | USE ieee.std_logic_unsigned.all; 42 | 43 | library work; 44 | use work.Gates_package.all; 45 | use work.Buses_package.all; 46 | 47 | ENTITY Priority IS 48 | port 49 | ( 50 | -- Inputs 51 | RECYCLE_RST : IN STD_LOGIC; -- 04A 52 | S_REG_1_BIT : IN STD_LOGIC; -- 07B 53 | SALS_CDREG : IN STD_LOGIC_VECTOR(0 to 3); -- 01A? 54 | MACH_RST_SW : IN STD_LOGIC; -- 03D 55 | DATA_READY_1 : IN STD_LOGIC; -- 05D 56 | DATA_READY_2 : IN STD_LOGIC; -- ??? 57 | MEM_WRAP_REQ : IN STD_LOGIC; -- 03B 58 | ALLOW_PROTECT : IN STD_LOGIC; -- 06C 59 | PROT_LOC_CPU_OR_MPX : IN STD_LOGIC; -- 08B 60 | READ_CALL : IN STD_LOGIC; -- 05D 61 | XOR_OR_OR : IN STD_LOGIC; -- 02A 62 | CTRL_N : IN STD_LOGIC; -- 06B 63 | STOP_REQ : IN STD_LOGIC; -- 03C 64 | SUPPR_A_REG_CHK : IN STD_LOGIC; -- 07A 65 | H_REG_5_PWR : IN STD_LOGIC; -- 04C 66 | SEL_ROS_REQ : IN STD_LOGIC; -- 12C 67 | FT_3_MPX_SHARE_REQ : IN STD_LOGIC; -- 08D 68 | H_REG_6 : IN STD_LOGIC; -- 04C 69 | P_8F_DETECTED : IN STD_LOGIC; -- 06C 70 | LOAD_IND : IN STD_LOGIC; -- 03C 71 | FORCE_IJ_REQ : IN STD_LOGIC; -- 04A 72 | FIRST_MACH_CHK_REQ : IN STD_LOGIC; -- 07A 73 | MACH_RST_6 : IN STD_LOGIC; -- 03D 74 | ALLOW_WRITE : IN STD_LOGIC; -- 03D 75 | GT_SWS_TO_WX_PWR : IN STD_LOGIC; -- 04A 76 | DIAGNOSTIC_SW : IN STD_LOGIC; -- 04A 77 | MACH_RST_LCH : IN STD_LOGIC; -- 04A 78 | HARD_STOP_LCH : IN STD_LOGIC; -- 03C 79 | R_REG_5 : IN STD_LOGIC; -- 06C 80 | H : IN STD_LOGIC_VECTOR(0 to 7); -- 04C 81 | FORCE_DEAD_CY_LCH : IN STD_LOGIC; -- 04A 82 | 83 | -- Outputs 84 | SUPPR_MACH_CHK_TRAP : OUT STD_LOGIC; -- 03C,04A,07A 85 | ANY_PRIORITY_PULSE_2 : OUT STD_LOGIC; -- 03B,04D 86 | ANY_PRIORITY_LCH : OUT STD_LOGIC; -- 04A,07A 87 | S_REG_1_DLYD : OUT STD_LOGIC; -- 03C 88 | GT_SW_TO_WX_LCH : OUT STD_LOGIC; -- 04A 89 | DATA_READY : OUT STD_LOGIC; -- 06C 90 | MEM_PROTECT_REQ : OUT STD_LOGIC; -- 07A 91 | HZ_DEST_RST : OUT STD_LOGIC; -- 03C,04A 92 | GT_SW_MACH_RST : OUT STD_LOGIC; -- 05A 93 | GT_SWS_TO_WX_LCH : OUT STD_LOGIC; -- 01B 94 | FORCE_IJ_REQ_LCH : OUT STD_LOGIC; -- 03C,04A,04B 95 | SYS_RST_PRIORITY_LCH :OUT STD_LOGIC; -- 06B 96 | MACH_CHK_PULSE : OUT STD_LOGIC; -- 03C,07A 97 | FORCE_IJ_PULSE : OUT STD_LOGIC; -- 04A 98 | SX_CHAIN_PULSE_1 : OUT STD_LOGIC; -- 12C 99 | ANY_PRIORITY_PULSE : OUT STD_LOGIC; -- 01C,01B,02B,04C,11C 100 | ANY_PRIORITY_PULSE_PWR : OUT STD_LOGIC; -- 01B,03C 101 | PRIORITY_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 01B 102 | PRIORITY_BUS_P : OUT STD_LOGIC; 103 | 104 | -- Clocks 105 | T1 : IN STD_LOGIC; 106 | T3 : IN STD_LOGIC; 107 | T4 : IN STD_LOGIC; 108 | P4 : IN STD_LOGIC; 109 | CLK : IN STD_LOGIC 110 | ); 111 | END Priority; 112 | 113 | ARCHITECTURE FMD OF Priority IS 114 | 115 | -- Priority Bus assignments 116 | signal sPRIORITY_BUS : STD_LOGIC_VECTOR(0 to 7); 117 | alias STOP_PULSE : STD_LOGIC is sPRIORITY_BUS(0); 118 | alias PROTECT_PULSE : STD_LOGIC is sPRIORITY_BUS(1); 119 | alias WRAP_PULSE : STD_LOGIC is sPRIORITY_BUS(2); 120 | alias MPX_SHARE_PULSE : STD_LOGIC is sPRIORITY_BUS(3); 121 | alias SX_CHAIN_PULSE : STD_LOGIC is sPRIORITY_BUS(4); 122 | alias PB_MACH_CHK_PULSE : STD_LOGIC is sPRIORITY_BUS(5); 123 | alias IPL_PULSE : STD_LOGIC is sPRIORITY_BUS(6); 124 | alias PB_FORCE_IJ_PULSE : STD_LOGIC is sPRIORITY_BUS(7); 125 | 126 | signal CD0101 : STD_LOGIC; 127 | signal PRIOR_RST_CTRL : STD_LOGIC; 128 | signal PRIORITY_LCH : STD_LOGIC; 129 | signal FIRST_MACH_CHK_LCH : STD_LOGIC; 130 | signal LOAD_REQ_LCH : STD_LOGIC; 131 | signal MEM_WRAP_REQ_LCH : STD_LOGIC; 132 | signal MEM_PROTECT_LCH : STD_LOGIC; 133 | signal STOP_REQ_LCH : STD_LOGIC; 134 | signal SEL_CHAIN_REQ_LCH : STD_LOGIC; 135 | signal MPX_SHARE_REQ_LCH : STD_LOGIC; 136 | signal HI_PRIORITY : STD_LOGIC; 137 | 138 | signal PRIORITY_STACK_IN, PRIORITY_STACK_OUT : STD_LOGIC_VECTOR(0 to 8); 139 | 140 | signal sSUPPR_MACH_CHK_TRAP : STD_LOGIC; 141 | signal sANY_PRIORITY_PULSE_2 : STD_LOGIC; 142 | signal sANY_PRIORITY_LCH : STD_LOGIC; 143 | signal sGT_SW_TO_WX_LCH : STD_LOGIC; 144 | signal sDATA_READY : STD_LOGIC; 145 | signal sMEM_PROTECT_REQ : STD_LOGIC; 146 | signal sHZ_DEST_RST : STD_LOGIC; 147 | signal sGT_SW_MACH_RST : STD_LOGIC; 148 | signal sGT_SWS_TO_WX_LCH : STD_LOGIC; 149 | signal sFORCE_IJ_REQ_LCH : STD_LOGIC; 150 | signal sSYS_RST_PRIORITY_LCH : STD_LOGIC; 151 | signal sMACH_CHK_PULSE : STD_LOGIC; 152 | signal sFORCE_IJ_PULSE : STD_LOGIC; 153 | signal sANY_PRIORITY_PULSE : STD_LOGIC; 154 | signal sMPX_SHARE_PULSE : STD_LOGIC; 155 | signal SUPPR_MACH_TRAP_L,PRIOR_RST_Latch,MEMP_LCH_Set,MEMP_LCH_Reset,PRI_LCH_Set, 156 | PRI_LCH_Reset,PRISTK_LCH_Latch : STD_LOGIC; 157 | 158 | BEGIN 159 | -- Fig 5-03A 160 | SUPPR_MACH_TRAP_L <= XOR_OR_OR and CTRL_N and T3; 161 | SUPPR_MALF_TRAP_LCH: PHR port map(not R_REG_5,SUPPR_MACH_TRAP_L,RECYCLE_RST,sSUPPR_MACH_CHK_TRAP); -- AB3D2,AB3J2 162 | -- ?? SUPPR_MACH_CHK_TRAP is from the output of the PH and not from its reset input ?? 163 | SUPPR_MACH_CHK_TRAP <= sSUPPR_MACH_CHK_TRAP; -- ?? 164 | -- SUPPR_MACH_CHK_TRAP <= not RECYCLE_RST; -- ?? 165 | sANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE; -- AB3D7 166 | ANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE_2; 167 | ANY_PRIORITY: entity work.PH port map(sANY_PRIORITY_PULSE_2,T1,sANY_PRIORITY_LCH); -- AB3D7,AB3J2 168 | ANY_PRIORITY_LCH <= sANY_PRIORITY_LCH; 169 | S1_DLYD: entity work.PH port map(S_REG_1_BIT,T1,S_REG_1_DLYD); -- AB3J2 170 | WX_SABC: entity work.PH port map(sGT_SWS_TO_WX_LCH,T1,sGT_SW_TO_WX_LCH); -- AB3J2 171 | GT_SW_TO_WX_LCH <= sGT_SW_TO_WX_LCH; 172 | CD0101 <= '1' when SALS_CDREG="0101" else '0'; 173 | PRIOR_RST_Latch <= T4 or MACH_RST_SW; 174 | PRIOR_RST_CTRL_PH: entity work.PHR port map(D=>CD0101,L=>PRIOR_RST_Latch,R=>sANY_PRIORITY_PULSE,Q=>PRIOR_RST_CTRL); -- AB3J2 175 | MEMP_LCH_Set <= sDATA_READY and ALLOW_PROTECT and PROT_LOC_CPU_OR_MPX; 176 | MEMP_LCH_Reset <= READ_CALL or RECYCLE_RST; 177 | STG_PROT_REQ: entity work.FLL port map(MEMP_LCH_Set,MEMP_LCH_Reset,sMEM_PROTECT_REQ); -- AA1K7 178 | MEM_PROTECT_REQ <= sMEM_PROTECT_REQ; 179 | 180 | sHZ_DEST_RST <= (P4 and sGT_SW_TO_WX_LCH) or (T3 and PRIOR_RST_CTRL); -- AB3K5,AB3J4 181 | HZ_DEST_RST <= sHZ_DEST_RST; 182 | sGT_SW_MACH_RST <= MACH_RST_6 or GT_SWS_TO_WX_PWR; -- AB3J3 ?? 183 | GT_SW_MACH_RST <= sGT_SW_MACH_RST; 184 | sDATA_READY <= (DATA_READY_1 or DATA_READY_2) and not MEM_WRAP_REQ; -- AA1J6 AA1J4 185 | DATA_READY <= sDATA_READY; 186 | 187 | PRI_LCH_Set <= (T1 and DIAGNOSTIC_SW) or MACH_RST_LCH or (not HARD_STOP_LCH and T3 and sANY_PRIORITY_LCH); 188 | PRI_LCH_Reset <= sHZ_DEST_RST or sGT_SW_MACH_RST; 189 | PRIORITY: entity work.FLL port map(S=>PRI_LCH_Set,R=>PRI_LCH_Reset,Q=>PRIORITY_LCH); -- AB3J4,AB3L4 190 | 191 | -- Priority stack register - all inputs are inverted AB3L2 192 | PRIORITY_STACK_IN(0) <= GT_SWS_TO_WX_PWR; 193 | PRIORITY_STACK_IN(1) <= FIRST_MACH_CHK_REQ; 194 | PRIORITY_STACK_IN(2) <= P_8F_DETECTED or LOAD_IND; 195 | PRIORITY_STACK_IN(3) <= FORCE_IJ_REQ; 196 | PRIORITY_STACK_IN(4) <= MEM_WRAP_REQ; 197 | PRIORITY_STACK_IN(5) <= sMEM_PROTECT_REQ; 198 | PRIORITY_STACK_IN(6) <= STOP_REQ; 199 | PRIORITY_STACK_IN(7) <= SUPPR_A_REG_CHK and not H_REG_5_PWR and SEL_ROS_REQ; 200 | PRIORITY_STACK_IN(8) <= FT_3_MPX_SHARE_REQ and not H_REG_6 and not H_REG_5_PWR; 201 | PRISTK_LCH_Latch <= MACH_RST_6 or (not ALLOW_WRITE and T3) or (P4 and GT_SWS_TO_WX_PWR); 202 | PRISTK_LCH: entity work.PHV9 port map( D => PRIORITY_STACK_IN, 203 | L => PRISTK_LCH_Latch, 204 | Q => PRIORITY_STACK_OUT); 205 | sGT_SWS_TO_WX_LCH <= PRIORITY_STACK_OUT(0); 206 | GT_SWS_TO_WX_LCH <= sGT_SWS_TO_WX_LCH; 207 | FIRST_MACH_CHK_LCH <= PRIORITY_STACK_OUT(1); 208 | LOAD_REQ_LCH <= PRIORITY_STACK_OUT(2); 209 | sFORCE_IJ_REQ_LCH <= PRIORITY_STACK_OUT(3); 210 | FORCE_IJ_REQ_LCH <= sFORCE_IJ_REQ_LCH; 211 | MEM_WRAP_REQ_LCH <= PRIORITY_STACK_OUT(4); 212 | MEM_PROTECT_LCH <= PRIORITY_STACK_OUT(5); 213 | STOP_REQ_LCH <= PRIORITY_STACK_OUT(6); 214 | SEL_CHAIN_REQ_LCH <= PRIORITY_STACK_OUT(7); 215 | MPX_SHARE_REQ_LCH <= PRIORITY_STACK_OUT(8); 216 | 217 | -- HI priorities AB3K3 218 | sMACH_CHK_PULSE <= not sSUPPR_MACH_CHK_TRAP and not PRIORITY_LCH and not sGT_SWS_TO_WX_LCH and FIRST_MACH_CHK_LCH; -- ?? SUPPRESS_MACH_CHECK_TRAP should be inverted ?? 219 | MACH_CHK_PULSE <= sMACH_CHK_PULSE; 220 | PB_MACH_CHK_PULSE <= sMACH_CHK_PULSE; 221 | IPL_PULSE <= not sMACH_CHK_PULSE and not PRIORITY_LCH and not sGT_SWS_TO_WX_LCH and LOAD_REQ_LCH and not H(0); 222 | sFORCE_IJ_PULSE <= not IPL_PULSE and not sMACH_CHK_PULSE and not sGT_SWS_TO_WX_LCH and not PRIORITY_LCH and sFORCE_IJ_REQ_LCH and not H(4); 223 | FORCE_IJ_PULSE <= sFORCE_IJ_PULSE; 224 | PB_FORCE_IJ_PULSE <= sFORCE_IJ_PULSE; 225 | WRAP_PULSE <= not sFORCE_IJ_PULSE and not PRIORITY_LCH and not sGT_SWS_TO_WX_LCH and not IPL_PULSE and not sMACH_CHK_PULSE and MEM_WRAP_REQ_LCH and not H(2); 226 | HI_PRIORITY <= FORCE_DEAD_CY_LCH or sGT_SWS_TO_WX_LCH or sMACH_CHK_PULSE or IPL_PULSE or sFORCE_IJ_PULSE or WRAP_PULSE; -- AB3K3 227 | PRIORITY_BUS <= sPRIORITY_BUS; 228 | 229 | -- LO priorities AB3K4 230 | PROTECT_PULSE <= not HI_PRIORITY and not PRIORITY_LCH and MEM_PROTECT_LCH and not H(3); 231 | STOP_PULSE <= not PROTECT_PULSE and not PRIORITY_LCH and not HI_PRIORITY and STOP_REQ_LCH; 232 | SX_CHAIN_PULSE <= not STOP_PULSE and not PROTECT_PULSE and not HI_PRIORITY and not PRIORITY_LCH and SEL_CHAIN_REQ_LCH and not H(5); 233 | SX_CHAIN_PULSE_1 <= SX_CHAIN_PULSE; 234 | sMPX_SHARE_PULSE <= not SX_CHAIN_PULSE and not STOP_PULSE and not PROTECT_PULSE and not PRIORITY_LCH and not HI_PRIORITY and MPX_SHARE_REQ_LCH and not (H(5) or H(6)); -- ?? 235 | MPX_SHARE_PULSE <= sMPX_SHARE_PULSE; 236 | 237 | SRP_LCH: entity work.FLL port map(MACH_RST_SW,T4,sSYS_RST_PRIORITY_LCH); -- AB3L3 238 | SYS_RST_PRIORITY_LCH <= sSYS_RST_PRIORITY_LCH; 239 | 240 | sANY_PRIORITY_PULSE <= sMPX_SHARE_PULSE or SX_CHAIN_PULSE or STOP_PULSE or PROTECT_PULSE or HI_PRIORITY or sSYS_RST_PRIORITY_LCH; -- AB3K4 ?? 241 | ANY_PRIORITY_PULSE <= sANY_PRIORITY_PULSE; 242 | ANY_PRIORITY_PULSE_PWR <= sANY_PRIORITY_PULSE and not MACH_RST_SW; -- AB3D4 243 | 244 | PRIORITY_BUS_P <= (sSYS_RST_PRIORITY_LCH or FORCE_DEAD_CY_LCH) and not GT_SWS_TO_WX_PWR; -- AB3H5 ?? 245 | 246 | END FMD; 247 | 248 | -------------------------------------------------------------------------------- /FMD2030_5-03B.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-03B.vhd 23 | -- Creation Date: 22:26:31 18/04/05 24 | -- Description: 25 | -- Storage Wrap (references >8k, >16k, >32k or wrapping over 64k) 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-13 35 | -- Initial Release 36 | -- Revision 1.1 2012-04-07 37 | -- Reset UMPX latch on RECYCLE_RST 38 | -- Change to 64k wrap 39 | --------------------------------------------------------------------------- 40 | LIBRARY ieee; 41 | USE ieee.std_logic_1164.all; 42 | USE ieee.std_logic_unsigned.all; 43 | 44 | library work; 45 | use work.Gates_package.all; 46 | use work.Buses_package.all; 47 | 48 | ENTITY StorageWrap IS 49 | port 50 | ( 51 | -- Inputs 52 | SALS : IN SALS_Bus; 53 | CTRL : IN CTRL_REG; 54 | ANY_PRIORITY_PULSE_2 : IN STD_LOGIC; -- 03A 55 | H_REG_5_PWR,H_REG_6 : IN STD_LOGIC; -- 04C 56 | NTRUE : IN STD_LOGIC; -- 06B 57 | CARRY_0 : IN STD_LOGIC; -- 06B 58 | COMPLEMENT : IN STD_LOGIC; -- 06B 59 | GT_J_TO_N_REG,GT_V_TO_N_REG : IN STD_LOGIC; -- 05B 60 | M012 : IN STD_LOGIC_VECTOR(0 to 2); -- 07B 61 | RECYCLE_RST : IN STD_LOGIC; -- 04A 62 | ALLOW_WRITE : IN STD_LOGIC; -- 03D 63 | READ_CALL : IN STD_LOGIC; -- 05D 64 | MAIN_STORAGE : IN STD_LOGIC; -- 04D 65 | DATA_READY_1,DATA_READY_2 : IN STD_LOGIC; -- 05D 66 | 67 | -- Outputs 68 | GT_CK_DECO : OUT STD_LOGIC; -- 03C,04C 69 | SEL_DATA_READY : OUT STD_LOGIC; -- 11C,13C,06C 70 | MEM_WRAP_REQ : OUT STD_LOGIC; -- 03A 71 | MEM_WRAP : OUT STD_LOGIC; -- 06C,11A,13A 72 | I_WRAPPED_CPU,U_WRAPPED_MPX : OUT STD_LOGIC; -- 02A 73 | 74 | -- Clocks 75 | T1,T2,T4 : IN STD_LOGIC; 76 | P1 : IN STD_LOGIC; 77 | CLK : IN STD_LOGIC 78 | ); 79 | END StorageWrap; 80 | 81 | ARCHITECTURE FMD OF StorageWrap IS 82 | 83 | signal RESTORE_WRAP,STORE_WRAP : STD_LOGIC; 84 | signal U_WRAP_CPU,WRAP_BUFF : STD_LOGIC; -- PH outputs 85 | signal NOT_MPX_OR_SEL,ALL_B_GATED,DEST_U,DEST_I_OR_RESTORE,CARRY_OUT_TRUE,CARRY_OUT_COMP,WRAP_TRUE,RESET_WRAP,CHECK_U_WRAP,CHECK_I_WRAP,CHECK_MPX_WRAP,CARRY_OUT : STD_LOGIC; 86 | signal WRAP64 : STD_LOGIC; 87 | signal sGT_CK_DECO : STD_LOGIC; 88 | signal sMEM_WRAP_REQ : STD_LOGIC; 89 | signal sMEM_WRAP : STD_LOGIC; 90 | signal sI_WRAPPED_CPU, sU_WRAPPED_MPX : STD_LOGIC; 91 | signal UWRAP_LCH_Reset,MWR_LCH_Set,MWR_LCH_Reset : STD_LOGIC; 92 | 93 | BEGIN 94 | -- Fig 5-03B 95 | sGT_CK_DECO <= not ANY_PRIORITY_PULSE_2 and SALS.SALS_AK and P1; -- AB3B3,AB3F6 ?? 96 | GT_CK_DECO <= sGT_CK_DECO; 97 | RESTORE_WRAP <= '1' when SALS.SALS_AK='1' and SALS.SALS_CK="0010" else '0'; -- AB3E6 98 | STORE_WRAP <= '1' when not (sGT_CK_DECO='1' and SALS.SALS_CK="1100") else '0'; -- AB3E6,AB3L6 99 | 100 | -- The Wrap latches remember whether a carry was associated with values stored in the U or I registers 101 | -- If so that means we wrapped around from 64k to 0. The Wrap latches are only used if the UV/IJ value is 102 | -- subsequently moved into MN 103 | NOT_MPX_OR_SEL <= not(H_REG_5_PWR or H_REG_6); -- AB2L4 104 | -- "ALL_B_GATED" means reset U wrap ?? 105 | -- "not ALL_B_GATED" means check U wrap ?? 106 | -- The FMD doesn't seem to show this way around, but microcode (e.g. QA781:C3) implies it 107 | ALL_B_GATED <= not (not CTRL.GT_B_REG_HI or not CTRL.GT_B_REG_LO); -- AB2M3 108 | DEST_U <= '1' when CTRL.CTRL_CD="1101" and T4='1' else '0'; -- AB2M3 109 | DEST_I_OR_RESTORE <= '1' when (T4='1' and CTRL.CTRL_CD="1111") or (T1='1' and RESTORE_WRAP='1') else '0'; -- AB2M2 AB2M5 110 | CARRY_OUT_TRUE <= not RESTORE_WRAP and NTRUE and CARRY_0; -- AB2M3 AB2L3 111 | CARRY_OUT_COMP <= COMPLEMENT and not CARRY_0; -- AB2M3 112 | WRAP_TRUE <= CARRY_OUT_TRUE or (RESTORE_WRAP and WRAP_BUFF); -- AB2L3 113 | RESET_WRAP <= NOT_MPX_OR_SEL and ALL_B_GATED and DEST_U; -- AB2M3 114 | CHECK_U_WRAP <= NOT_MPX_OR_SEL and DEST_U and not ALL_B_GATED; -- AB2L4 115 | CHECK_I_WRAP <= NOT_MPX_OR_SEL and DEST_I_OR_RESTORE; -- AB2L4 116 | CHECK_MPX_WRAP <= H_REG_6 and not H_REG_5_PWR; -- AB2L4 117 | CARRY_OUT <= CARRY_OUT_TRUE or CARRY_OUT_COMP; -- AB2L3 118 | 119 | UWRAP_LCH_Reset <= RECYCLE_RST or RESET_WRAP; 120 | UWRAP_LCH: entity work.PHR port map(D=>WRAP_TRUE,L=>CHECK_U_WRAP,R=>UWRAP_LCH_Reset,Q=>U_WRAP_CPU); -- AB2M4 121 | IWRAP_LCH: entity work.PHR port map(D=>WRAP_TRUE,L=>CHECK_I_WRAP,R=>RECYCLE_RST,Q=>sI_WRAPPED_CPU); -- AB2M4 122 | I_WRAPPED_CPU <= sI_WRAPPED_CPU; 123 | UMPX_LCH: entity work.PHR port map(D=>CARRY_OUT,L=>CHECK_MPX_WRAP,R=>RECYCLE_RST,Q=>sU_WRAPPED_MPX); -- AB2M4 ?? Doesn't have reset in FMD - causes Diag failure 124 | U_WRAPPED_MPX <= sU_WRAPPED_MPX; 125 | WBUFF_LCH: entity work.PH port map(D=>sI_WRAPPED_CPU,L=>STORE_WRAP,Q=>WRAP_BUFF); -- AB2M4 ?? *not* sI_WRAPPED_CPU ?? 126 | 127 | WRAP64 <= (not H_REG_6 and GT_V_TO_N_REG and U_WRAP_CPU) or 128 | (GT_J_TO_N_REG and not H_REG_6 and sI_WRAPPED_CPU) or 129 | (GT_V_TO_N_REG and H_REG_6 and sU_WRAPPED_MPX); 130 | 131 | -- Select the appropriate wrap condition based on storage size: 132 | -- sMEM_WRAP <= M012(0) or M012(1) or M012(2); -- 8k 133 | -- sMEM_WRAP <= M012(0) or M012(1); -- 16k 134 | -- sMEM_WRAP <= M012(0); -- 32k 135 | sMEM_WRAP <= WRAP64; -- 64k 136 | MEM_WRAP <= sMEM_WRAP; 137 | 138 | MWR_LCH_Set <= MAIN_STORAGE and T2 and (sMEM_WRAP and not ALLOW_WRITE); -- ?? ALLOW_WRITE use unclear - dot logic 139 | MWR_LCH_Reset <= READ_CALL or RECYCLE_RST; 140 | MWR_LCH: entity work.FLL port map(MWR_LCH_Set,MWR_LCH_Reset,sMEM_WRAP_REQ); 141 | MEM_WRAP_REQ <= sMEM_WRAP_REQ; 142 | SEL_DATA_READY <= (DATA_READY_1 or DATA_READY_2) and not sMEM_WRAP_REQ; 143 | 144 | END FMD; 145 | -------------------------------------------------------------------------------- /FMD2030_5-03D.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-03D.vhd -------------------------------------------------------------------------------- /FMD2030_5-04A-B.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-04A-B.vhd -------------------------------------------------------------------------------- /FMD2030_5-04C.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-04C.vhd 23 | -- Creation Date: 22:26:31 18/04/05 24 | -- Description: 25 | -- Manual Data (E switch) & C,F,H registers 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-13 35 | -- Initial Release 36 | -- Revision 1.01 2012-04-07 37 | -- Fix typo in comment 38 | --------------------------------------------------------------------------- 39 | LIBRARY ieee; 40 | USE ieee.std_logic_1164.all; 41 | USE ieee.std_logic_unsigned.all; 42 | 43 | library work; 44 | use work.Gates_package.all; 45 | use work.Buses_package.all; 46 | 47 | ENTITY ManualDataCFH IS 48 | port 49 | ( 50 | -- Inputs 51 | MACH_RST_PROT : IN STD_LOGIC; -- 07B 52 | USE_MAN_DECO_PWR : IN STD_LOGIC; -- 03D 53 | N60_CY_TIMER_PULSE : IN STD_LOGIC; -- 14A 54 | L_REGISTER : IN STD_LOGIC_VECTOR(0 to 7); -- 05C 55 | MACH_RST_SW : IN STD_LOGIC; -- 03D 56 | EXT_TRAP_MASK_ON : IN STD_LOGIC; -- 08C 57 | USE_MAN_DECODER, USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D 58 | USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B 59 | USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02A 60 | GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C 61 | CK_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C 62 | GT_CK_DECO : IN STD_LOGIC; -- 03B 63 | Z_BUS : IN STD_LOGIC_VECTOR(0 to 7); 64 | Z_BUS_P : IN STD_LOGIC; 65 | MACH_RST_2B : IN STD_LOGIC; -- 06B 66 | MAN_STOR_PWR : IN STD_LOGIC; -- 03D 67 | CD_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 3); -- 01C 68 | RECYCLE_RST : IN STD_LOGIC; -- 04A 69 | 70 | -- Switches 71 | SW_INTRP_TIMER : IN STD_LOGIC; 72 | SW_CONS_INTRP : IN STD_LOGIC; 73 | SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : IN STD_LOGIC_VECTOR(0 to 3); 74 | SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : IN STD_LOGIC; 75 | 76 | -- Outputs 77 | ABCD_SW_BUS,FGHJ_SW_BUS : OUT STD_LOGIC_VECTOR(0 to 15); 78 | AB_SW_P,CD_SW_P,FG_SW_P,HJ_SW_P : OUT STD_LOGIC; 79 | IJ_SEL,UV_SEL : OUT STD_LOGIC; 80 | TIMER_UPDATE : OUT STD_LOGIC; -- 02A 81 | TIMER_UPDATE_OR_EXT_INT : OUT STD_LOGIC; -- 02A 82 | EXT_INTRP : OUT STD_LOGIC; -- 02A 83 | A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P 84 | H_REG_BITS : OUT STD_LOGIC_VECTOR(0 to 7); -- 03B,03A 85 | H_REG_P : OUT STD_LOGIC; -- 03B,03A 86 | H_REG_6 : OUT STD_LOGIC; 87 | H_REG_5_PWR : OUT STD_LOGIC; -- 02A,08B 88 | GT_1050_TAGS : OUT STD_LOGIC; -- 10C 89 | GT_1050_BUS : OUT STD_LOGIC; -- 10C 90 | CD_REG_2 : OUT STD_LOGIC; -- 05C 91 | -- E switch 92 | E_SW : IN E_SW_BUS_Type; 93 | 94 | DEBUG : INOUT DEBUG_BUS; 95 | 96 | -- Clocks 97 | T1,T2,T3,T4 : IN STD_LOGIC; 98 | clk : IN STD_LOGIC 99 | ); 100 | END ManualDataCFH; 101 | 102 | ARCHITECTURE FMD OF ManualDataCFH IS 103 | 104 | signal RST_COUNTER : STD_LOGIC; 105 | signal N10MSPULSE : STD_LOGIC; 106 | signal BIN_DRIVE : STD_LOGIC; 107 | signal CTRL_TRG : STD_LOGIC; 108 | signal CTRL_LCH : STD_LOGIC; 109 | signal CNTR_FULL : STD_LOGIC; 110 | signal C_BINARY_CNTR : STD_LOGIC_VECTOR(4 to 7); 111 | signal EXT_INT : STD_LOGIC; 112 | signal RESET_F_REG : STD_LOGIC; 113 | signal F_REGISTER : STD_LOGIC_VECTOR(0 to 7); 114 | signal F_REGISTER_1A : STD_LOGIC; 115 | signal SET_F_REG_0 : STD_LOGIC; 116 | signal GT_C_TO_A_BUS : STD_LOGIC; 117 | signal GT_F_TO_A : STD_LOGIC; 118 | signal GT_H_TO_A : STD_LOGIC; 119 | signal C_EXT_INT : STD_LOGIC_VECTOR(2 to 7); 120 | signal H_SET : STD_LOGIC; 121 | signal sTIMER_UPDATE : STD_LOGIC; 122 | signal sH_REG_BITS : STD_LOGIC_VECTOR(0 to 7); 123 | signal sH_REG_P : STD_LOGIC; 124 | signal CTL_LCH_Set,CTL_LCH_Reset,CT_FF_Set,BD_FF_Set,EI_LCH_Set,EI_LCH_Reset,F0_LCH_Reset,F1_LCH_Set,F1A_LCH_Reset : STD_LOGIC; 125 | signal F07_LCH_Reset,F07_LCH_Set : STD_LOGIC_VECTOR(0 to 7); 126 | 127 | BEGIN 128 | -- Fig 5-04C 129 | 130 | -- Rotary switches ABCD and FGHJ 131 | ABCD_SW_BUS <= SW_A & SW_B & SW_C & SW_D; 132 | AB_SW_P <= SW_AP xnor SW_BP; -- AC1D2,AC1E3 133 | CD_SW_P <= SW_CP xnor SW_DP; -- AC1D4,AC1E3,AC1D2 134 | 135 | FGHJ_SW_BUS <= SW_F & SW_G & SW_H & SW_J; 136 | FG_SW_P <= SW_FP xnor SW_GP; -- AC1D4,AC1E3,AC1D2 137 | HJ_SW_P <= SW_HP xnor SW_JP; -- AC1D4,AC1E3,AC1D2 138 | 139 | IJ_SEL <= '1' when (E_SW.I_SEL='1' or E_SW.J_SEL='1') and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2 140 | UV_SEL <= '1' when (E_SW.U_SEL='1' or E_SW.V_SEL='1') and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2 141 | 142 | RST_COUNTER <= MACH_RST_PROT; -- BE3G5 143 | 144 | CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (not sTIMER_UPDATE and SW_INTRP_TIMER); 145 | -- CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (sTIMER_UPDATE and SW_INTRP_TIMER); 146 | CTL_LCH_Reset <= CTRL_TRG and T3; 147 | CTL_LCH: entity work.FLL port map(CTL_LCH_Set,CTL_LCH_Reset,CTRL_LCH); -- BE3G6,BE3F5 148 | 149 | N10MSPULSE <= not(N60_CY_TIMER_PULSE and not T3); -- 10ms monostable here 150 | 151 | CT_FF_Set <= CTRL_LCH and T4; 152 | CT_FF: entity work.FLL port map(CT_FF_Set,not CTRL_LCH,CTRL_TRG); -- BE3F6 153 | BD_FF_Set <= not CTRL_LCH and T3 and N10MSPULSE and not CNTR_FULL; -- Not T2 as per MDM (refer FETOM) 154 | BD_FF: entity work.FLL port map(BD_FF_Set,not N10MSPULSE,BIN_DRIVE); -- BE3F6 155 | 156 | process(BIN_DRIVE,RST_COUNTER,CTRL_TRG) -- BE3G7,BE3F7 157 | begin 158 | if RST_COUNTER='1' or CTRL_TRG='1' then 159 | C_BINARY_CNTR <= "0000"; 160 | else if BIN_DRIVE'event and BIN_DRIVE='0' then 161 | C_BINARY_CNTR <= C_BINARY_CNTR + "0001"; 162 | end if; 163 | end if; 164 | end process; 165 | 166 | CNTR_FULL <= C_BINARY_CNTR(4) and C_BINARY_CNTR(5) and C_BINARY_CNTR(6) and C_BINARY_CNTR(7); -- BE3G6 167 | 168 | -- Interrupt generation 169 | sTIMER_UPDATE <= C_BINARY_CNTR(4) or C_BINARY_CNTR(5) or C_BINARY_CNTR(6) or C_BINARY_CNTR(7); -- BE3G6,BE3G5 170 | TIMER_UPDATE <= sTIMER_UPDATE and EXT_TRAP_MASK_ON; -- Modified to include EXT_TRAP_MASK_ON for timer as well 171 | -- TIMER_UPDATE <= sTIMER_UPDATE; 172 | TIMER_UPDATE_OR_EXT_INT <= (sTIMER_UPDATE and EXT_TRAP_MASK_ON) or EXT_INT; -- AC1D5 Modified to include EXT_TRAP_MASK_ON for timer as well 173 | -- TIMER_UPDATE_OR_EXT_INT <= EXT_INT; -- AC1D5 ?? Temporarily prevent Timer 174 | EXT_INT <= (F_REGISTER(0) or F_REGISTER(1) or F_REGISTER(2) or F_REGISTER(3) or 175 | F_REGISTER(4) or F_REGISTER(5) or F_REGISTER(6) or F_REGISTER(7)) and EXT_TRAP_MASK_ON; -- AC1G2 ?? Should this include EXT_TRAP_MASK_ON ? 176 | EI_LCH_Reset <= MACH_RST_SW or RESET_F_REG; 177 | EI_LCH_Set <= EXT_INT and T3; -- ?? Seems to be needed, not as per MDM 178 | EI_LCH: entity work.FLL port map(EI_LCH_Set,EI_LCH_Reset,EXT_INTRP); -- AC1K6,AC1C2 179 | 180 | -- F register - here it is held in True polarity, in the 2030 it is inverted 181 | C_EXT_INT <= "000000"; 182 | SET_F_REG_0 <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and CK_SALS(3) and GT_CK_DECO; -- AB3F7 CK=1111 183 | RESET_F_REG <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and not CK_SALS(3) and GT_CK_DECO; -- AB3F7 CK=1110 184 | 185 | F1A_LCH_Reset <= (L_REGISTER(1) and RESET_F_REG) or RECYCLE_RST; 186 | F1_LCH_Set <= F_REGISTER_1A and SW_CONS_INTRP; 187 | F1A_LCH: entity work.FLL port map(not SW_CONS_INTRP, F1A_LCH_Reset, F_REGISTER_1A); -- AC1L2 188 | 189 | F07_LCH_Set <= SET_F_REG_0 & F1_LCH_Set & C_EXT_INT(2 to 7); 190 | F07_LCH_Reset <= (0 to 7 => RECYCLE_RST) or ((0 to 7 => RESET_F_REG) and ('1' & L_REGISTER(1 to 7))); 191 | F07_LCH: entity work.FLVL port map(F07_LCH_Set, F07_LCH_Reset, F_REGISTER(0 to 7)); -- AC1L2 192 | 193 | -- H register 194 | H_SET <= MACH_RST_2B or (E_SW.H_SEL and MAN_STOR_PWR) or 195 | (T4 and not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3)); -- AB1J2 CD=0101 196 | GT_1050_TAGS <= not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and not CD_CTRL_REG(3); -- AB1B3 CD=0100 197 | GT_1050_BUS <= not CD_CTRL_REG(0) and not CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3); -- AB1B3 CD=0001 198 | CD_REG_2 <= CD_CTRL_REG(2); -- AB1B3 199 | H_LCH: entity work.PHV8 port map(Z_BUS,H_SET,sH_REG_BITS); -- AB1L3 200 | H_REG_BITS <= sH_REG_BITS; 201 | HP_LCH: entity work.PH port map(Z_BUS_P,H_SET,sH_REG_P); -- AB1L3 202 | H_REG_P <= sH_REG_P; 203 | H_REG_6 <= sH_REG_BITS(6); -- AB1C6,AB1G2 204 | H_REG_5_PWR <= sH_REG_BITS(5); -- AB1L2 205 | 206 | -- A bus drive 207 | GT_C_TO_A_BUS <= (E_SW.C_SEL and USE_MAN_DECODER) or 208 | (not GTD_CA_BITS(0) and GTD_CA_BITS(1) and not GTD_CA_BITS(2) and not GTD_CA_BITS(3) and USE_ALT_CA_DECODER); -- AB3C7 CA=0100 209 | GT_F_TO_A <= (E_SW.F_SEL and USE_MAN_DECO_PWR) or 210 | (not GTD_CA_BITS(0) and not GTD_CA_BITS(1) and not GTD_CA_BITS(2) and not GTD_CA_BITS(3) and USE_ALT_CA_DECODER); -- AB3C7 CA=0000 211 | GT_H_TO_A <= (E_SW.H_SEL and USE_MAN_DECODER) or 212 | (not GTD_CA_BITS(0) and GTD_CA_BITS(1) and not GTD_CA_BITS(2) and GTD_CA_BITS(3) and USE_BASIC_CA_DECODER); -- AB3C7 CA=0101 213 | 214 | A_BUS <= not ("0000" & C_BINARY_CNTR & '0') when GT_C_TO_A_BUS='1' 215 | else (F_REGISTER & '0') when GT_F_TO_A='1' -- ?? F_REGISTER should be inverted? 216 | else not (sH_REG_BITS & sH_REG_P) when GT_H_TO_A='1' 217 | else "111111111"; -- AB1F6 218 | 219 | with DEBUG.Selection select 220 | DEBUG.Probe <= 221 | C_BINARY_CNTR(7) when 0, 222 | C_BINARY_CNTR(6) when 1, 223 | C_BINARY_CNTR(5) when 2, 224 | C_BINARY_CNTR(4) when 3, 225 | N10MSPULSE when 4, 226 | CNTR_FULL when 5, 227 | CTRL_LCH when 6, 228 | CTRL_TRG when 7, 229 | BIN_DRIVE when 8, 230 | RST_COUNTER when 9, 231 | N60_CY_TIMER_PULSE when 10, 232 | CTL_LCH_Set when 11, 233 | CTL_LCH_Reset when 12, 234 | BD_FF_Set when 13, 235 | EXT_INT when 14, 236 | sTIMER_UPDATE when 15; 237 | 238 | END FMD; 239 | -------------------------------------------------------------------------------- /FMD2030_5-04D.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-04D.vhd -------------------------------------------------------------------------------- /FMD2030_5-05A.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-05A.vhd -------------------------------------------------------------------------------- /FMD2030_5-05B.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-05B.vhd -------------------------------------------------------------------------------- /FMD2030_5-05C.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-05C.vhd -------------------------------------------------------------------------------- /FMD2030_5-05D.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-05D.vhd 23 | -- Creation Date: 22:26:31 18/04/05 24 | -- Description: 25 | -- Read/Write Storage Clocks for 1st 32k 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-13 35 | -- Initial Release 36 | -- Revision 1.1 2012-04-07 37 | -- Changed for 64k storage: START_1ST_32K triggered for 1st *and* 2nd 32k 38 | --------------------------------------------------------------------------- 39 | LIBRARY ieee; 40 | USE ieee.std_logic_1164.all; 41 | USE ieee.std_logic_unsigned.all; 42 | 43 | library work; 44 | use work.Gates_package.all; 45 | use work.Buses_package.all; 46 | 47 | ENTITY RWStgClk1st32k IS 48 | port 49 | ( 50 | -- Inputs 51 | ALLOW_WRITE : IN STD_LOGIC; -- 03D 52 | CPU_READ_PWR : IN STD_LOGIC; -- 04D 53 | SEL_RD_CALL : IN STD_LOGIC; -- 12C 54 | MAN_RD_CALL : IN STD_LOGIC; -- 03D 55 | ROAR_RESTT_AND_STOR_BYPASS : IN STD_LOGIC; -- 04B 56 | SEL_WR_CALL : IN STD_LOGIC; -- 12C 57 | MAN_WR_CALL : IN STD_LOGIC; -- 03D 58 | CPU_WRITE_PWR : IN STD_LOGIC; -- 04D 59 | EARLY_LOCAL_STG : IN STD_LOGIC; -- 04D 60 | EARLY_M_REG_0 : IN STD_LOGIC; -- 07B 61 | M_REG_0 : IN STD_LOGIC; -- 07B 62 | MACH_RST_SW : IN STD_LOGIC; -- 03D 63 | 64 | 65 | -- Outputs 66 | READ_CALL : OUT STD_LOGIC; -- 03A,03B 67 | USE_LOCAL_MAIN_MEM : OUT STD_LOGIC; -- 06D 68 | USE_MAIN_MEMORY : OUT STD_LOGIC; -- 06D 69 | READ_ECHO_1, READ_ECHO_2 : OUT STD_LOGIC; -- 03D 70 | DATA_READY_1, DATA_READY_2 : OUT STD_LOGIC; -- 03A 03B 71 | WRITE_ECHO_1, WRITE_ECHO_2 : OUT STD_LOGIC; -- 03D 72 | 73 | -- Debug 74 | DEBUG1,DEBUG2,DEBUG3,DEBUG4 : OUT STD_LOGIC; 75 | DEBUG : OUT STD_LOGIC; 76 | DBG_TD1_1, DBG_TD1_2 : OUT STD_LOGIC_VECTOR(1 to 38); 77 | DBG_RD_OR_WR_SET1,DBG_RD_OR_WR_RST1 : OUT STD_LOGIC; 78 | -- Clocks 79 | T1,T2,T3,T4 : IN STD_LOGIC; 80 | CLK : IN STD_LOGIC -- 50MHz / 20ns 81 | ); 82 | END RWStgClk1st32k; 83 | 84 | ARCHITECTURE FMD OF RWStgClk1st32k IS 85 | 86 | signal START_RD,START_WR : STD_LOGIC; 87 | signal START_1ST_32K, START_2ND_32K : STD_LOGIC; 88 | signal READ_CALL_TO_MEM,WRITE_CALL_TO_MEM : STD_LOGIC; 89 | signal sREAD_CALL : STD_LOGIC; 90 | signal sUSE_LOCAL_MAIN_MEM : STD_LOGIC; 91 | signal USE_LOCAL_Set,USE_LOCAL_Reset : STD_LOGIC; 92 | signal TD1 : STD_LOGIC_VECTOR(1 to 38) := (others=>'0'); -- 20ns steps 20 to 740ns 93 | signal RD_OR_WR_RST1, RD_OR_WR_SET1, nRD_OR_WR_SET1, CTRL_R_WIDTH1, TD1IN : STD_LOGIC; 94 | signal TD1_80, TD1_150, TD1_200, TD1_500, TD1_560, TD1_660, TD1_680, TD1_700 : STD_LOGIC; 95 | signal RD_OR_WR_SET1_RESET, dRD_OR_WR_SET1_RESET, CTRL_R_WIDTH1_RESET : STD_LOGIC; 96 | signal READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_2_RESET : STD_LOGIC; 97 | signal WRITE_ECHO_1_SET : STD_LOGIC; 98 | signal WRITE_ECHO_1_RESET : STD_LOGIC; 99 | signal READ_RST_SET1, READ_RST_SET2 : STD_LOGIC; 100 | signal READ_RST_RESET1, READ_RST_RESET2 : STD_LOGIC; 101 | signal RD_RST_CTRL1 : STD_LOGIC; 102 | signal WRITE_RST_SET1 : STD_LOGIC; 103 | signal WRITE_RST_RESET1 : STD_LOGIC; 104 | signal WR_RST_CTRL1 : STD_LOGIC; 105 | signal SET_READ_LCHS1 : STD_LOGIC; 106 | signal DATA_READY1_SET, DATA_READY1_RESET : STD_LOGIC; 107 | signal SET_READ_LCHS1_RESET : STD_LOGIC; 108 | signal dT1 : STD_LOGIC; 109 | signal sDATA_READY_1 : STD_LOGIC; 110 | 111 | BEGIN 112 | -- Fig 5-05D 113 | START_RD <= not ALLOW_WRITE and CPU_READ_PWR and T1; -- AA1K4 114 | START_WR <= ALLOW_WRITE and CPU_WRITE_PWR and T1; -- AA1K4 115 | sREAD_CALL <= START_RD or SEL_RD_CALL or MAN_RD_CALL; -- AA1J2 116 | READ_CALL <= sREAD_CALL; 117 | READ_CALL_TO_MEM <= sREAD_CALL and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J3,AA1C2 118 | WRITE_CALL_TO_MEM <= (MAN_WR_CALL or SEL_WR_CALL or START_WR) and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J2,AA1J3 119 | 120 | USE_LOCAL_Set <= EARLY_LOCAL_STG and READ_CALL_TO_MEM; 121 | USE_LOCAL_Reset <= not EARLY_LOCAL_STG and READ_CALL_TO_MEM; 122 | USE_LOCAL: entity work.FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- CB1E2 123 | USE_LOCAL_MAIN_MEM <= sUSE_LOCAL_MAIN_MEM; 124 | USE_MAIN_MEMORY <= not sUSE_LOCAL_MAIN_MEM; -- CB1H2 125 | 126 | -- START_1ST_32K <= (not EARLY_M_REG_0 and READ_CALL_TO_MEM) or (READ_CALL_TO_MEM and EARLY_LOCAL_STG) or (not M_REG_0 and WRITE_CALL_TO_MEM) or (WRITE_CALL_TO_MEM and sUSE_LOCAL_MAIN_MEM); -- CB1E2 127 | -- START_2ND_32K <= (READ_CALL_TO_MEM and EARLY_M_REG_0 and not sUSE_LOCAL_MAIN_MEM) or (WRITE_CALL_TO_MEM and M_REG_0 and not sUSE_LOCAL_MAIN_MEM); -- CB1E2 128 | START_1ST_32K <= READ_CALL_TO_MEM or WRITE_CALL_TO_MEM; -- CB1E2 combined 1st & 2nd 32k 129 | 130 | -- Generate timing signals relative to START_xxx_32K 131 | -- READ_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW) 132 | -- WRITE_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW) 133 | -- DATA_READY_n ON at 640ns OFF at 700ns (or MACH_RST_SW) 134 | 135 | -- First 32K 136 | TD1_80 <= TD1(4); -- 80ns 137 | TD1_150 <= TD1(8); -- 160ns 138 | TD1_200 <= TD1(10); -- 200ns 139 | TD1_500 <= TD1(25); -- 500ns 140 | TD1_560 <= TD1(28); -- 560ns 141 | TD1_660 <= TD1(33); -- 660ns 142 | TD1_680 <= TD1(34); -- 680ns 143 | TD1_700 <= TD1(35); -- 700ns 144 | 145 | nRD_OR_WR_SET1 <= not RD_OR_WR_SET1; 146 | RD_OR_WR_RST1_FL: entity work.FLL port map(TD1_80, nRD_OR_WR_SET1, RD_OR_WR_RST1); 147 | RD_OR_WR_SET1_RESET <= RD_OR_WR_RST1 or MACH_RST_SW; 148 | -- The delay is to prevent a combinatorial loop: 149 | Delay_RD_OR_WR_SET1_RESET: AR port map (D=>RD_OR_WR_SET1_RESET, clk=>Clk, Q=>dRD_OR_WR_SET1_RESET); 150 | RD_OR_WR_SET1_FL: entity work.FLL port map(START_1ST_32K, dRD_OR_WR_SET1_RESET, RD_OR_WR_SET1); 151 | TD1IN <= not RD_OR_WR_RST1 and RD_OR_WR_SET1; 152 | 153 | -- READ CLOCK 0 154 | READ_ECHO_1_SET <= TD1_150 and SET_READ_LCHS1; 155 | READ_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and RD_RST_CTRL1); 156 | READ_ECHO_1_FL: entity work.FLL port map(READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_1); -- 150 to 680ns 157 | -- READ CLOCK 4 158 | DATA_READY1_SET <= TD1_560 and SET_READ_LCHS1; 159 | DATA_READY1_RESET <= MACH_RST_SW or (TD1_660 and RD_RST_CTRL1); 160 | DATA_READY1_FL: entity work.FLL port map(DATA_READY1_SET, DATA_READY1_RESET, sDATA_READY_1); -- 560 to 660ns 161 | DATA_READY_1 <= sDATA_READY_1; 162 | 163 | -- READ CLOCK 5 164 | READ_RST_SET1 <= TD1_500 and SET_READ_LCHS1; 165 | READ_RST_RESET1 <= MACH_RST_SW or TD1_700; 166 | READ_RST1_FL: entity work.FLL port map(READ_RST_SET1, READ_RST_RESET1, RD_RST_CTRL1); -- 500 to 700ns 167 | -- WRITE CLOCK 0 168 | WRITE_ECHO_1_SET <= TD1_150 and not SET_READ_LCHS1; 169 | WRITE_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and WR_RST_CTRL1); 170 | WRITE_ECHO_1_FL: entity work.FLL port map(WRITE_ECHO_1_SET, WRITE_ECHO_1_RESET, WRITE_ECHO_1); -- 150 to 680ns 171 | -- WRITE CLOCK 4 172 | SET_READ_LCHS1_RESET <= MACH_RST_SW or WRITE_CALL_TO_MEM; -- ?? 173 | SET_READ_LCHS1_FL: entity work.FLL port map(READ_CALL_TO_MEM, SET_READ_LCHS1_RESET, SET_READ_LCHS1); -- RD CALL to WR CALL 174 | -- WRITE CLOCK 5 175 | WRITE_RST_SET1 <= TD1_500 and not SET_READ_LCHS1; 176 | WRITE_RST_RESET1 <= MACH_RST_SW or TD1_150; -- 150ns or 1050ns or 1500ns? 177 | WRITE_RST1_FL: entity work.FLL port map(WRITE_RST_SET1, WRITE_RST_RESET1, WR_RST_CTRL1); -- 500 to 700ns?? 178 | 179 | -- Second 32K 180 | READ_ECHO_2 <= '0'; 181 | DATA_READY_2 <= '0'; 182 | WRITE_ECHO_2 <= '0'; 183 | 184 | -- Debug 185 | DEBUG <= START_RD; 186 | DBG_TD1_1 <= TD1; 187 | DBG_RD_OR_WR_SET1 <= RD_OR_WR_SET1; 188 | DBG_RD_OR_WR_RST1 <= RD_OR_WR_RST1; 189 | 190 | delayLine: process(CLK) 191 | begin 192 | if (rising_edge(CLK)) then 193 | TD1 <= TD1IN & TD1(1 to TD1'right-1); 194 | end if; 195 | end process; 196 | -- Debug latch 197 | 198 | R_DEBUG: process (clk,T1,TD1IN) 199 | begin 200 | if rising_edge(clk) then 201 | if T1='1' and dT1='0' then 202 | DEBUG1 <= '0'; -- Reset on rising edge of T1 203 | else if (sDATA_READY_1 and T1)='1' then 204 | DEBUG1 <= '1'; -- Set on any DATA_READY 205 | end if; 206 | end if; 207 | if T1='1' and dT1='0' then 208 | DEBUG2 <= '0'; -- Reset on rising edge of T1 209 | else if (sDATA_READY_1 and T2)='1' then 210 | DEBUG2 <= '1'; -- Set on any DATA_READY 211 | end if; 212 | end if; 213 | if T1='1' and dT1='0' then 214 | DEBUG3 <= '0'; -- Reset on rising edge of T1 215 | else if (sDATA_READY_1 and T3)='1' then 216 | DEBUG3 <= '1'; -- Set on any DATA_READY 217 | end if; 218 | end if; 219 | if T1='1' and dT1='0' then 220 | DEBUG4 <= '0'; -- Reset on rising edge of T1 221 | else if (sDATA_READY_1 and T4)='1' then 222 | DEBUG4 <= '1'; -- Set on any DATA_READY 223 | end if; 224 | end if; 225 | dT1 <= T1; 226 | end if; 227 | end process; 228 | 229 | 230 | END FMD; 231 | 232 | -------------------------------------------------------------------------------- /FMD2030_5-06A-B.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-06A-B.vhd -------------------------------------------------------------------------------- /FMD2030_5-07A1.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-07A1.vhd -------------------------------------------------------------------------------- /FMD2030_5-07A2.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-07A2.vhd -------------------------------------------------------------------------------- /FMD2030_5-07B1.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-07B1.vhd -------------------------------------------------------------------------------- /FMD2030_5-07B2.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-07B2.vhd 23 | -- Creation Date: 01/11/09 24 | -- Description: 25 | -- S Register 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-13 35 | -- Initial Release 36 | -- Revision 1.1 2012-04-07 37 | -- Change GT_CS_OPT to level-triggered latch 38 | --------------------------------------------------------------------------- 39 | LIBRARY ieee; 40 | USE ieee.std_logic_1164.all; 41 | USE ieee.std_logic_unsigned.all; 42 | 43 | library work; 44 | use work.Gates_package.all; 45 | use work.Buses_package.all; 46 | -- use work.all; 47 | 48 | ENTITY SReg IS 49 | port 50 | ( 51 | SA : IN STD_LOGIC; -- 01C 52 | CS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C 53 | CD : IN STD_LOGIC_VECTOR(0 to 3); -- 01C 54 | N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 7); 55 | Z_BUS0, CARRY_0, Z_BUS_HI_0, Z_BUS_LO_0 : IN STD_LOGIC; -- 06B 56 | GT_CARRY_TO_S3 : IN STD_LOGIC; 57 | S : OUT STD_LOGIC_VECTOR(0 to 7); 58 | GT_Z_BUS_TO_S : OUT STD_LOGIC; 59 | S_REG_RST : OUT STD_LOGIC; 60 | CTRL_REG_RST : IN STD_LOGIC; -- 01C 61 | MAN_STOR_PWR : IN STD_LOGIC; -- 03D 62 | STORE_S_REG_RST : IN STD_LOGIC; -- 03D 63 | E_SW_SEL_S : IN STD_LOGIC; -- 04C 64 | MACH_RST_2C : IN STD_LOGIC; -- 06B 65 | T_REQUEST : IN STD_LOGIC; -- 10BC6 66 | FB_K_T2_PULSE : OUT STD_LOGIC; 67 | CS_DECODE_X001 : OUT STD_LOGIC; -- 03C 68 | BASIC_CS_0 : OUT STD_LOGIC; -- 03C 69 | P1, T1, T2, T3, T4 : IN STD_LOGIC; 70 | clk : IN STD_LOGIC 71 | ); 72 | END SReg; 73 | 74 | ARCHITECTURE FMD OF SReg IS 75 | signal SETS, RESETS : STD_LOGIC_VECTOR(0 to 7); 76 | signal CS_X000,CS_X001,CS_X010,CS_X011,CS_X100,CS_X101,CS_X110,CS_X111,CS_X01X,CS_X0X1,CS_0XXX,CS_1XXX : STD_LOGIC; 77 | signal CD_0110 : STD_LOGIC; 78 | signal GT_CS_OPT_DECODER, GT_CS_BASIC_DECODER : STD_LOGIC; 79 | signal BASIC_NOT_CS_0, sBASIC_CS_0 : STD_LOGIC; 80 | signal sGT_Z_BUS_TO_S : STD_LOGIC; 81 | signal sS_REG_RST : STD_LOGIC; 82 | signal GT_CS_OPT_Set,GT_CS_OPT_Reset : STD_LOGIC; 83 | signal S_REG_Set,S_REG_Reset : STD_LOGIC_VECTOR(0 to 7); 84 | 85 | BEGIN 86 | -- Fig 5-07B 87 | CS_X000 <= '1' when CS(1 to 3)="000" else '0'; 88 | CS_X001 <= '1' when CS(1 to 3)="001" else '0'; 89 | CS_DECODE_X001 <= CS_X001; 90 | CS_X010 <= '1' when CS(1 to 3)="010" else '0'; 91 | CS_X011 <= '1' when CS(1 to 3)="011" else '0'; 92 | CS_X100 <= '1' when CS(1 to 3)="100" else '0'; 93 | CS_X101 <= '1' when CS(1 to 3)="101" else '0'; 94 | CS_X110 <= '1' when CS(1 to 3)="110" else '0'; 95 | CS_X111 <= '1' when CS(1 to 3)="111" else '0'; 96 | CS_X01X <= '1' when CS(1 to 2)="01" else '0'; 97 | CS_X0X1 <= '1' when CS(1)='0' and CS(3)='1' else '0'; 98 | CS_0XXX <= '1' when CS(0)='0' else '0'; 99 | CS_1XXX <= '1' when CS(0)='1' else '0'; 100 | GT_CS_OPT_Set <= SA and P1; 101 | GT_CS_OPT_Reset <= CTRL_REG_RST or T1; 102 | -- GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5 103 | GT_CS_OPT: entity work.FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5 104 | GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5 105 | BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)" 106 | sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)" 107 | BASIC_CS_0 <= sBASIC_CS_0; 108 | FB_K_T2_PULSE <= sBASIC_CS_0 and T2 and CS_X110; -- AA3F7, AA3E3 109 | 110 | CD_0110 <= '1' when CD="0110" else '0'; -- AA3B7, AA3J6 111 | sGT_Z_BUS_TO_S <= (CD_0110 and T4) or (MAN_STOR_PWR and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6 112 | GT_Z_BUS_TO_S <= sGT_Z_BUS_TO_S; 113 | 114 | sS_REG_RST <= (CD_0110 and T3) or (STORE_S_REG_RST and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6 115 | S_REG_RST <= sS_REG_RST; 116 | 117 | 118 | SETS(0) <= CS_X111 and BASIC_NOT_CS_0; -- AA3G7 119 | SETS(1) <= T_REQUEST and CS_X101 and BASIC_NOT_CS_0; -- AA3G7 120 | SETS(2) <= CS_X001 and not Z_BUS0 and sBASIC_CS_0; -- AA3H7 121 | SETS(3) <= GT_CARRY_TO_S3 and CARRY_0; -- AA3H7 122 | SETS(4) <= BASIC_NOT_CS_0 and CS_X01X and Z_BUS_HI_0; -- AA3J7 123 | SETS(5) <= BASIC_NOT_CS_0 and CS_X0X1 and Z_BUS_LO_0; -- AA3J7 124 | SETS(6) <= CS_X011 and sBASIC_CS_0; -- AA3K7 125 | SETS(7) <= CS_X101 and sBASIC_CS_0; -- AA3K7 126 | 127 | RESETS(0) <= CS_X110 and BASIC_NOT_CS_0; -- AA3G7 128 | RESETS(1) <= CS_X101 and not T_REQUEST and BASIC_NOT_CS_0; -- AA3G7 129 | RESETS(2) <= CS_X000 and sBASIC_CS_0; -- AA3H7 130 | RESETS(3) <= not CARRY_0 and GT_CARRY_TO_S3; -- AA3H7 131 | RESETS(4) <= (BASIC_NOT_CS_0 and not Z_BUS_HI_0 and CS_X01X) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7 132 | RESETS(5) <= (BASIC_NOT_CS_0 and not Z_BUS_LO_0 and CS_X0X1) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7 133 | RESETS(6) <= sBASIC_CS_0 and CS_X010; -- AA3K7 134 | RESETS(7) <= sBASIC_CS_0 and CS_X100; -- AA3K7 135 | 136 | S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS); -- ?? "T4 and not T1" to prevent erroneous S4 value 137 | S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS); -- ?? "T4 and not T1" to prevent erroneous S4 value 138 | S_REG: FLVL port map(S_REG_Set, S_REG_Reset, S); -- AA3G7, AA3H7, AA3J7, AA3K7 139 | END FMD; 140 | -------------------------------------------------------------------------------- /FMD2030_5-07B_2.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-07B_2.vhd -------------------------------------------------------------------------------- /FMD2030_5-07C.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-07C.vhd -------------------------------------------------------------------------------- /FMD2030_5-08A.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: LJW 4 | -- 5 | -- Create Date: 22:26:31 04/18/05 6 | -- Design Name: 7 | -- Module Name: Clock+MpxInd - Behavioral 8 | -- Project Name: IBM2030 9 | -- Target Device: XC3S1000 10 | -- Tool versions: ISE V7.1 11 | -- Description: Four-phase clock generation and Multiplexor channel indicators 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | -------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | -- use IEEE.STD_LOGIC_ARITH.ALL; 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 | 25 | entity ClockMpxInd is Port ( 26 | -- Clock stuff 27 | CLOCK_IN : in std_logic; 28 | T1,T2,T3,T4 : out std_logic; 29 | P1,P2,P3,P4 : out std_logic; 30 | OSC_T_LINE : out std_logic; -- 12A 31 | M_CONV_OSC : out std_logic; -- 03C 32 | P_CONV_OSC : out std_logic; -- 03D,03C 33 | M_CONV_OSC_2 : out std_logic; -- 03C 34 | CLOCK_ON : out std_logic; -- 03D,04A,03C,13B,12A,11B 35 | CLOCK_OFF : out std_logic; -- 04B,06C,09B,03D 36 | CLOCK_START : in std_logic; -- 03C 37 | MACH_RST_3 : in std_logic; -- 03D 38 | 39 | -- Mpx Indicator stuff 40 | TEST_LAMP : in std_Logic; -- 04A 41 | OPNL_IN,ADDR_IN,STATUS_IN,SERVICE_IN, 42 | SELECT_OUT,ADDR_OUT,COMMAND_OUT,SERVICE_OUT, 43 | SUPPRESS_OUT : in std_logic; -- 08D 44 | FO_P : in std_logic; -- 08C 45 | FO : in std_logic_vector(0 to 7); -- 08C 46 | IND_OPNL_IN, IND_ADDR_IN,IND_STATUS_IN,IND_SERV_IN, 47 | IND_SEL_OUT,IND_ADDR_OUT,IND_CMMD_OUT,IND_SERV_OUT, 48 | IND_SUPPR_OUT,IND_FO_P : out std_logic; 49 | IND_FO : out std_logic_vector(0 to 7) 50 | ); 51 | end ClockMpxInd; 52 | 53 | architecture slt of ClockMpxInd is 54 | -- subtype DividerSize is STD_LOGIC_VECTOR(5 downto 0); 55 | -- constant RATIO : DividerSize := "001111"; -- 16 gives 3.125MHz 56 | -- subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0); 57 | -- constant RATIO : DividerSize := "00111100000000000000000000"; -- 16M gives 3.125Hz 58 | subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0); 59 | constant RATIO : DividerSize := "00010011000100101101000000"; -- 5M gives 10Hz 60 | constant ZERO : DividerSize := (others=>'0'); 61 | constant ONE : DividerSize := (0=>'1',others=>'0'); 62 | 63 | signal DIVIDER : DividerSize; 64 | signal OSC2,OSC,DLYD_OSC : STD_LOGIC; 65 | -- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4); 66 | signal CLK : STD_LOGIC_VECTOR(1 to 4); 67 | 68 | begin 69 | -- Divide the 50MHz FPGA clock down 70 | -- 1.5us storage cycle means T1-4 takes 750ns, or 3MHz 71 | -- OSC2 is actually double the original oscillator as only one edge is used 72 | process (CLOCK_IN) 73 | begin 74 | if CLOCK_IN'event and CLOCK_IN='1' then 75 | if DIVIDER=RATIO then 76 | DIVIDER <= ZERO; 77 | OSC2 <= not OSC2; 78 | else 79 | DIVIDER <= DIVIDER + ONE; 80 | end if; 81 | end if; 82 | end process; 83 | 84 | -- AC1K6,AC1C6 Probably have to re-do this lot to get it work 85 | --SETS(1) <= not DLYD_OSC and CLOCK_START and not CLK(3) and CLK(4); 86 | --SETS(2) <= DLYD_OSC not CLK(4) and CLK(1); 87 | --SETS(3) <= not DLYD_OSC and not CLK(1) and CLK(2); 88 | --SETS(4) <= (DLYD_OSC and not CLK(2) and CLK(3)) or MACH_RST_3='1'; 89 | --RSTS(1) <= (not DLYD_OSC and CLK(2)) or MACH_RST_3='1'; 90 | --RSTS(2) <= (OSC and CLK(3)) or MACH_RST_3='1'; 91 | --RSTS(3) <= (not DLYD_OSC and CLK(4)) or MACH_RST_3='1'; 92 | --RSTS(4) <= OSC and CLK(1); 93 | --FLV(SETS,RSTS,CLK); -- AC1C6 94 | 95 | -- The following process forms a ring counter 96 | -- MACH_RST_3 forces the counter to 0001 97 | -- If CLOCK_START is false, the counter stays at 0001 98 | -- When CLOCK_START goes true, the counter cycles through 99 | -- 0001 0001 0001 1001 1100 0110 0011 1001 1100 .... 100 | -- When CLOCK_START subsequently goes false, the sequence continues 101 | -- until reaching 0011, after which it stays at 0001 102 | -- ... 1001 1100 0110 0011 0001 0001 0001 ... 103 | 104 | -- The original counter used a level-triggered implementation, driven by 105 | -- both levels of the OSC signal. Here it is easier to make it edge triggered 106 | -- which requires a clock of twice the frequency, hence OSC2 107 | process (OSC2, MACH_RST_3) 108 | begin 109 | if OSC2'event and OSC2='1' then 110 | if OSC='0' then -- Rising edge 111 | OSC <= '1'; 112 | if CLK(2)='1' or MACH_RST_3='1' then 113 | CLK(1) <= '0'; 114 | elsif CLOCK_START='1' and CLK(4)='1' then 115 | CLK(1) <= '1'; 116 | end if; 117 | if CLK(4)='1' or MACH_RST_3='1' then 118 | CLK(3) <= '0'; 119 | elsif CLK(2)='1' then 120 | CLK(3) <= '1'; 121 | end if; 122 | else -- Falling edge 123 | OSC <= '0'; 124 | if CLK(3)='1' or MACH_RST_3='1' then 125 | CLK(2) <= '0'; 126 | elsif CLK(1)='1' then 127 | CLK(2) <= '1'; 128 | end if; 129 | if CLK(3)='1' or MACH_RST_3='1' then 130 | CLK(4) <= '1'; 131 | elsif CLK(1)='1' then 132 | CLK(4) <= '0'; 133 | end if; 134 | end if; 135 | end if; 136 | end process; 137 | 138 | OSC_T_LINE <= not OSC; 139 | M_CONV_OSC <= OSC; 140 | DLYD_OSC <= OSC; -- AC1C6 141 | 142 | P1 <= CLK(1); 143 | P2 <= CLK(2); 144 | P3 <= CLK(3); 145 | P4 <= CLK(4); 146 | 147 | T1 <= CLK(4) and CLK(1); 148 | T2 <= CLK(1) and CLK(2); 149 | T3 <= CLK(2) and CLK(3); 150 | T4 <= CLK(3) and CLK(4); 151 | 152 | CLOCK_ON <= CLK(1) or CLK(2) or CLK(3); 153 | CLOCK_OFF <= not (CLK(1) or CLK(2) or CLK(3)); 154 | P_CONV_OSC <= OSC and not (CLK(1) or CLK(2) or CLK(3)); 155 | M_CONV_OSC_2 <= OSC and not (CLK(1) or CLK(2) or CLK(3)); -- Note: Not inverted, despite the name 156 | 157 | 158 | -- The indicator drivers for the Multiplexor channel are here 159 | IND_OPNL_IN <= OPNL_IN or TEST_LAMP; 160 | IND_ADDR_IN <= ADDR_IN or TEST_LAMP; 161 | IND_STATUS_IN <= STATUS_IN or TEST_LAMP; 162 | IND_SERV_IN <= SERVICE_IN or TEST_LAMP; 163 | IND_SEL_OUT <= SELECT_OUT or TEST_LAMP; 164 | IND_ADDR_OUT <= ADDR_OUT or TEST_LAMP; 165 | IND_CMMD_OUT <= COMMAND_OUT or TEST_LAMP; 166 | IND_SERV_OUT <= SERVICE_OUT or TEST_LAMP; 167 | IND_SUPPR_OUT <= SUPPRESS_OUT or TEST_LAMP; 168 | IND_FO_P <= FO_P or TEST_LAMP; 169 | IND_FO <= FO or (FO'range => TEST_LAMP); 170 | 171 | end slt; 172 | -------------------------------------------------------------------------------- /FMD2030_5-08A1.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-08A1.vhd 23 | -- Creation Date: 22:26:31 18/04/05 24 | -- Description: 25 | -- Clock generator - 4 phase (T1,T2,T3,T4 and P1,P2,P3,P4) 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-13 35 | -- Initial Release 36 | -- Revision 1.1 2012-04-07 37 | -- Add registers to all clock outputs and delay rising edge of Px and Tx clocks 38 | --------------------------------------------------------------------------- 39 | library IEEE; 40 | Library UNISIM; 41 | use UNISIM.vcomponents.all; 42 | use IEEE.STD_LOGIC_1164.ALL; 43 | -- use IEEE.STD_LOGIC_ARITH.ALL; 44 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 45 | use work.Gates_package.all; 46 | use work.all; 47 | 48 | entity Clock is Port ( 49 | -- Clock stuff 50 | CLOCK_IN : in std_logic; 51 | T1,T2,T3,T4 : out std_logic; 52 | P1,P2,P3,P4 : out std_logic; 53 | OSC_T_LINE : out std_logic; -- 12A 54 | M_CONV_OSC : out std_logic; -- 03C 55 | P_CONV_OSC : out std_logic; -- 03D,03C 56 | M_CONV_OSC_2 : out std_logic; -- 03C 57 | CLOCK_ON : out std_logic; -- 03D,04A,03C,13B,12A,11B 58 | CLOCK_OFF : out std_logic; -- 04B,06C,09B,03D 59 | CLOCK_START : in std_logic; -- 03C 60 | MACH_RST_3 : in std_logic; -- 03D 61 | Sw_Slow : in std_logic -- '1' to run slow 62 | ); 63 | end Clock; 64 | 65 | architecture FMD of Clock is 66 | -- Following 2 lines to run clock at 5.33MHz (standard) 67 | -- subtype DividerSize is STD_LOGIC_VECTOR(5 downto 0); 68 | subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0); 69 | constant RATIOFast : DividerSize := "00000000000000000000001000"; -- 5 gives 10MHz => 720ns cycle 70 | -- Following 2 lines to run clock at 5Hz 71 | constant RATIOSlow : DividerSize := "00100010010101010001000000"; -- 5M gives 10Hz => 720ms cycle 72 | constant ZERO : DividerSize := (others=>'0'); 73 | constant ONE : DividerSize := (0=>'1',others=>'0'); 74 | 75 | signal DIVIDER : DividerSize := (others=>'0'); 76 | signal DIVIDER_MAX : DividerSize; 77 | signal OSC2,OSC,M_DLYD_OSC,DLYN_OSC,T1A,T2A,T3A,T4A,OSC2_DLYD : STD_LOGIC := '0'; 78 | -- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4); 79 | signal CLK : STD_LOGIC_VECTOR(1 to 4) := "0001"; 80 | signal P1D,P2D,P3D,P4D : STD_LOGIC; 81 | signal OSC_T_LINEA, CLOCK_ONA, CLOCK_OFFA, P_CONV_OSCA,M_CONV_OSC_2A, N_OSC : STD_LOGIC; 82 | 83 | begin 84 | -- Divide the 50MHz FPGA clock down 85 | -- 1.5us storage cycle means T1-4 takes 750ns, or 1.33MHz 86 | -- The clock to generate the four phases is therefore 2.66MHz 87 | -- OSC2 is actually double the original oscillator (5.33MHz) as only one edge is used 88 | DIVIDER_MAX <= RatioSlow when Sw_Slow='1' else RATIOFast; 89 | OSC2 <= '1' when DIVIDER > '0' & DIVIDER_MAX(DIVIDER_MAX'left downto 1) else '0'; 90 | N_OSC <= not OSC; 91 | 92 | process (CLOCK_IN) 93 | begin 94 | if CLOCK_IN'event and CLOCK_IN='1' then 95 | if DIVIDER>=DIVIDER_MAX then 96 | DIVIDER <= ZERO; 97 | else 98 | DIVIDER <= DIVIDER + ONE; 99 | end if; 100 | end if; 101 | end process; 102 | 103 | -- AC1K6,AC1C6 Probably have to re-do this lot to get it work 104 | --SETS(1) <= not DLYD_OSC and CLOCK_START and not CLK(3) and CLK(4); 105 | --SETS(2) <= DLYD_OSC not CLK(4) and CLK(1); 106 | --SETS(3) <= not DLYD_OSC and not CLK(1) and CLK(2); 107 | --SETS(4) <= (DLYD_OSC and not CLK(2) and CLK(3)) or MACH_RST_3='1'; 108 | --RSTS(1) <= (not DLYD_OSC and CLK(2)) or MACH_RST_3='1'; 109 | --RSTS(2) <= (OSC and CLK(3)) or MACH_RST_3='1'; 110 | --RSTS(3) <= (not DLYD_OSC and CLK(4)) or MACH_RST_3='1'; 111 | --RSTS(4) <= OSC and CLK(1); 112 | --FLV(SETS,RSTS,CLK); -- AC1C6 113 | 114 | -- The following process forms a ring counter 115 | -- MACH_RST_3 forces the counter to 0001 116 | -- If CLOCK_START is false, the counter stays at 0001 117 | -- When CLOCK_START goes true, the counter cycles through 118 | -- 0001 0001 0001 1001 1100 0110 0011 1001 1100 .... 119 | -- When CLOCK_START subsequently goes false, the sequence continues 120 | -- until reaching 0011, after which it stays at 0001 121 | -- ... 1001 1100 0110 0011 0001 0001 0001 ... 122 | 123 | -- The original counter used a level-triggered implementation, driven by 124 | -- both levels of the OSC signal. Here it is easier to make it edge triggered 125 | -- which requires a clock of twice the frequency, hence OSC2 126 | process (OSC2, MACH_RST_3, CLOCK_START) 127 | begin 128 | if OSC2'event and OSC2='1' then 129 | if OSC='0' then -- OSC Rising edge: +P1 (P4=1 & START) -P3 (P4=1) or -P1 +P3 (P2=1) 130 | OSC <= '1'; 131 | if CLK(2)='1' or MACH_RST_3='1' then 132 | CLK(1) <= '0'; 133 | elsif CLOCK_START='1' and CLK(4)='1' then 134 | CLK(1) <= '1'; 135 | end if; 136 | if CLK(4)='1' or MACH_RST_3='1' then 137 | CLK(3) <= '0'; 138 | elsif CLK(2)='1' then 139 | CLK(3) <= '1'; 140 | end if; 141 | else -- OSC Falling edge: +P2 -P4 (P1=1) or -P2 +P4 (P3=1) 142 | OSC <= '0'; 143 | if CLK(3)='1' or MACH_RST_3='1' then 144 | CLK(2) <= '0'; 145 | elsif CLK(1)='1' then 146 | CLK(2) <= '1'; 147 | end if; 148 | if CLK(3)='1' or MACH_RST_3='1' then 149 | CLK(4) <= '1'; 150 | elsif CLK(1)='1' then 151 | CLK(4) <= '0'; 152 | end if; 153 | end if; 154 | end if; 155 | end process; 156 | 157 | OSC_T_LINEA <= OSC; -- AC1B6 158 | OSC_T_LINED : FDCE port map(D=>OSC_T_LINEA,Q=>OSC_T_LINE,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 159 | M_CONV_OSCD : FDCE port map(D=>N_OSC,Q=>M_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0'); -- AC1C6 160 | M_DLYD_OSC <= not OSC; -- AC1C6 161 | DLYN_OSC <= OSC; -- AC1C6 162 | 163 | -- P1 <= CLK(1); 164 | -- P2 <= CLK(2); 165 | -- P3 <= CLK(3); 166 | -- P4 <= CLK(4); 167 | -- Delay the rising edge of each P pulse to ensure that the T pulses never overlap 168 | P1DLY: entity DelayRisingEdgeX port map (D=>CLK(1),CLK=>CLOCK_IN,Q=>P1D); 169 | P2DLY: entity DelayRisingEdgeX port map (D=>CLK(2),CLK=>CLOCK_IN,Q=>P2D); 170 | P3DLY: entity DelayRisingEdgeX port map (D=>CLK(3),CLK=>CLOCK_IN,Q=>P3D); 171 | P4DLY: entity DelayRisingEdgeX port map (D=>CLK(4),CLK=>CLOCK_IN,Q=>P4D); 172 | 173 | T1A <= P4D and P1D; 174 | T2A <= P1D and P2D; 175 | T3A <= P2D and P3D; 176 | T4A <= P3D and P4D; 177 | 178 | T1D : FDCE port map(D=>T1A,Q=>T1,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 179 | T2D : FDCE port map(D=>T2A,Q=>T2,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 180 | T3D : FDCE port map(D=>T3A,Q=>T3,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 181 | T4D : FDCE port map(D=>T4A,Q=>T4,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 182 | P1C : FDCE port map(D=>P1D,Q=>P1,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 183 | P2C : FDCE port map(D=>P2D,Q=>P2,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 184 | P3C : FDCE port map(D=>P3D,Q=>P3,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 185 | P4C : FDCE port map(D=>P4D,Q=>P4,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 186 | 187 | CLOCK_ONA <= CLK(1) or CLK(2) or CLK(3); 188 | CLOCK_OND : FDCE port map(D=>CLOCK_ONA,Q=>CLOCK_ON,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 189 | CLOCK_OFFA <= not CLOCK_ONA; 190 | CLOCK_OFFD : FDCE port map(D=>CLOCK_OFFA,Q=>CLOCK_OFF,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 191 | P_CONV_OSCA <= OSC and CLOCK_OFFA; 192 | P_CONV_OSCD : FDCE port map(D=>P_CONV_OSCA,Q=>P_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 193 | M_CONV_OSC_2A <= not(P_CONV_OSCA); 194 | M_CONV_OSC_2D : FDCE port map(D=>M_CONV_OSC_2A,Q=>M_CONV_OSC_2,CE=>'1',C=>CLOCK_IN,CLR=>'0'); 195 | 196 | end FMD; 197 | -------------------------------------------------------------------------------- /FMD2030_5-08A2.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-08A2.vhd -------------------------------------------------------------------------------- /FMD2030_5-08B.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/FMD2030_5-08B.vhd -------------------------------------------------------------------------------- /FMD2030_5-08C.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-08C.vhd 23 | -- Creation Date: 22:26:31 18/04/05 24 | -- Description: 25 | -- Multiplexor Channel registers FO & FB 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-13 35 | -- Initial Release 36 | -- Revision 1.1 2012-04-07 37 | -- Revise XH & XL BU latches amd MPX_INTRPT signal 38 | --------------------------------------------------------------------------- 39 | library IEEE; 40 | use IEEE.STD_LOGIC_1164.ALL; 41 | use IEEE.STD_LOGIC_ARITH.ALL; 42 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 43 | use work.PH; 44 | use work.FLVL; 45 | 46 | entity MpxFOFB is 47 | Port ( MPX_ROS_LCH : in STD_LOGIC; 48 | S_REG_0 : in STD_LOGIC; 49 | SET_FW : in STD_LOGIC; 50 | S_REG_1 : in STD_LOGIC; 51 | S_REG_2 : in STD_LOGIC; 52 | T3 : in STD_LOGIC; 53 | CK_SALS : in STD_LOGIC_VECTOR (0 to 3); 54 | PK_SALS : in STD_LOGIC; 55 | FBK_T2 : in STD_LOGIC; 56 | MACH_RST_SET_LCH : in STD_LOGIC; 57 | SALS_CS : in STD_LOGIC_VECTOR (0 to 3); 58 | SALS_SA : in STD_LOGIC; 59 | CK_0_PWR : in STD_LOGIC; 60 | R_REG : in STD_LOGIC_VECTOR (0 to 8); 61 | T1,T2 : in STD_LOGIC; 62 | XXH : out STD_LOGIC; 63 | XH : out STD_LOGIC; 64 | XL : out STD_LOGIC; 65 | FT_7_BIT_MPX_CHNL_INTRP : out STD_LOGIC; 66 | FT_2_BIT_MPX_OPN_LCH : out STD_LOGIC; 67 | SUPPR_CTRL_LCH : out STD_LOGIC; 68 | OP_OUT_SIG : out STD_LOGIC; 69 | MPX_OPN_LT_GATE : out STD_LOGIC; 70 | MACH_RST_MPX : out STD_LOGIC; 71 | MPX_INTRPT : out STD_LOGIC; 72 | SX1_MASK : out STD_LOGIC; 73 | EXT_TRAP_MASK_ON : out STD_LOGIC; 74 | SX2_MASK : out STD_LOGIC; 75 | FAK : out STD_LOGIC; 76 | SET_BUS_O_CTRL_LCH : out STD_LOGIC; 77 | MPX_BUS_O_REG : out STD_LOGIC_VECTOR (0 to 8); 78 | clk : in STD_LOGIC); 79 | end MpxFOFB; 80 | 81 | architecture FMD of MpxFOFB is 82 | signal sXXH,sXH,sXL,T3SET,X_SET : STD_LOGIC; 83 | signal XXH_IN,XH_IN,XL_IN : STD_LOGIC; 84 | signal XXHBU,XHBU,XLBU : STD_LOGIC; 85 | signal sMACH_RST_MPX : STD_LOGIC; 86 | signal CK11XX, CKX11X,CKX1X1,CK1X1X,CKXX11 : STD_LOGIC; 87 | signal CHNL_L,OPN_L,SUPPR_L,OUT_L : STD_LOGIC; 88 | signal notOP_OUT_SIG,MpxMask : STD_LOGIC; 89 | alias KP is PK_SALS; 90 | signal sFAK,sSET_BUS_O_CTRL : STD_LOGIC; 91 | signal BusO_Set,BusO_Reset : STD_LOGIC_VECTOR (0 to 8); 92 | signal sFT_7_BIT_MPX_CHNL_INTRP,sFT_2_BIT_MPX_OPN_LCH,sSUPPR_CTRL_LCH : STD_LOGIC; 93 | begin 94 | 95 | -- XL, XH and XXL bits and backup 96 | 97 | XXH_BU: entity PH port map (D=>sXXH, L=>SET_FW, Q=> XXHBU); 98 | XXH_IN <= (XXHBU and MPX_ROS_LCH) or (S_REG_0 and not MPX_ROS_LCH); 99 | X_SET <= T3SET or sMACH_RST_MPX; 100 | XXH_PH: entity PH port map (D=>XXH_IN, L=>X_SET, Q=> sXXH); 101 | XXH <= sXXH; 102 | 103 | XH_BU: entity PH port map (D=>sXH, L=>SET_FW, Q=> XHBU); 104 | -- XH_IN <= (XHBU and MPX_ROS_LCH) or (not S_REG_1 and not MPX_ROS_LCH); 105 | XH_IN <= (XHBU and MPX_ROS_LCH) or (S_REG_1 and not MPX_ROS_LCH); 106 | XH_PH: entity PH port map (D=>XH_IN, L=>X_SET, Q=>sXH); 107 | XH <= sXH; 108 | 109 | XL_BU: entity PH port map (D=>sXL, L=>SET_FW, Q=> XLBU); 110 | -- XL_IN <= (XLBU and MPX_ROS_LCH) or (not S_REG_2 and not MPX_ROS_LCH); 111 | XL_IN <= (XLBU and MPX_ROS_LCH) or (S_REG_2 and not MPX_ROS_LCH); 112 | XL_PH: entity PH port map (D=>XL_IN, L=>X_SET, Q=>sXL); 113 | XL <= sXL; 114 | 115 | -- MPX Flags 116 | 117 | T3SET <= (MPX_ROS_LCH and T3) or (FBK_T2 and CK_SALS(0) and CK_SALS(3)); 118 | sMACH_RST_MPX <= MACH_RST_SET_LCH; 119 | MACH_RST_MPX <= sMACH_RST_MPX; 120 | 121 | CK11XX <= CK_SALS(0) and CK_SALS(1) and FBK_T2; 122 | CHNL_L <= sMACH_RST_MPX or CK11XX; 123 | MPX_CHNL: entity PH port map (D=>KP,L=>CHNL_L,Q=>sFT_7_BIT_MPX_CHNL_INTRP); 124 | FT_7_BIT_MPX_CHNL_INTRP <= sFT_7_BIT_MPX_CHNL_INTRP; 125 | 126 | CKX11X <= CK_SALS(1) and CK_SALS(2) and FBK_T2; 127 | OPN_L <= sMACH_RST_MPX or CKX11X; 128 | MPX_OPN: entity PH port map (D=>KP,L=>OPN_L,Q=>sFT_2_BIT_MPX_OPN_LCH); 129 | FT_2_BIT_MPX_OPN_LCH <= sFT_2_BIT_MPX_OPN_LCH; 130 | 131 | CK1X1X <= CK_SALS(0) and CK_SALS(2) and FBK_T2; 132 | SUPPR_L <= sMACH_RST_MPX or CK1X1X; 133 | SUPPR_CTRL: entity PH port map (D=>KP,L=>SUPPR_L,Q=>sSUPPR_CTRL_LCH); 134 | SUPPR_CTRL_LCH <= sSUPPR_CTRL_LCH; 135 | 136 | CKX1X1 <= CK_SALS(1) and CK_SALS(3) and FBK_T2; 137 | OUT_L <= sMACH_RST_MPX or CKX1X1; 138 | OP_OUT_CTRL: entity PH port map (D=>KP,L=>OUT_L,Q=>notOP_OUT_SIG); 139 | OP_OUT_SIG <= not notOP_OUT_SIG; 140 | 141 | MPX_OPN_LT_GATE <= CKX11X; 142 | 143 | -- External Interrupt Masks 144 | -- ?? Should the R_REG bits be inverted before use? 145 | CKXX11 <= CK_SALS(2) and CK_SALS(3) and FBK_T2; 146 | MPX_MASK: entity PH port map (D=>R_REG(0),L=>CKXX11,Q=>MPXMask); 147 | MPX_INTRPT <= sFT_7_BIT_MPX_CHNL_INTRP and MPXMask; 148 | SX1MASK: entity PH port map (D=>R_REG(1),L=>CKXX11,Q=>SX1_MASK); 149 | EXT_MASK: entity PH port map (D=>R_REG(7),L=>CKXX11,Q=>EXT_TRAP_MASK_ON); 150 | SX2MASK: entity PH port map (D=>R_REG(2),L=>CKXX11,Q=>SX2_MASK); 151 | 152 | -- MPX BUS OUT REGISTER 153 | 154 | sFAK <= SALS_CS(0) and SALS_CS(1) and SALS_CS(2) and SALS_CS(3) and not SALS_SA; 155 | FAK <= sFAK; 156 | 157 | sSET_BUS_O_CTRL <= sFAK and CK_0_PWR; 158 | SET_BUS_O_CTRL_LCH <= sSET_BUS_O_CTRL; 159 | 160 | BusO_Set <= R_REG and (0 to 8=>(sSET_BUS_O_CTRL and T2)); -- ??? "and T2" added to prevent incorrect setting of BUS_O 161 | BusO_Reset <= (0 to 8=>sSET_BUS_O_CTRL and T1); 162 | MPX_BUSO: entity FLVL port map (S=>BusO_Set,R=>BusO_Reset,Q=>MPX_BUS_O_REG); 163 | 164 | end FMD; 165 | 166 | -------------------------------------------------------------------------------- /FMD2030_5-08D.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-08D.vhd 23 | -- Creation Date: 21:39:37 03/22/2010 24 | -- Description: 25 | -- Multiplexor Channel Controls - FA Register - Indicators 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2010-07-13 35 | -- Initial Release 36 | -- Revision 1.1 2012-04-07 37 | -- Revise Mpx and 1050 signals 38 | --------------------------------------------------------------------------- 39 | library IEEE; 40 | use IEEE.STD_LOGIC_1164.ALL; 41 | use IEEE.STD_LOGIC_ARITH.ALL; 42 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 43 | USE work.Gates_package.all; 44 | USE work.Buses_package.all; 45 | USE work.FLL; 46 | 47 | entity MpxFA is 48 | Port ( BUS_O_REG : in STD_LOGIC_VECTOR (0 to 8); 49 | DIAG_SW : in STD_LOGIC; 50 | -- External MPX connections: 51 | MPX_BUS_OUT_BITS : out STD_LOGIC_VECTOR (0 to 8); 52 | MPX_BUS_IN_BITS : in STD_LOGIC_VECTOR (0 to 8); 53 | TAGS_OUT : out MPX_TAGS_OUT; 54 | TAGS_IN : in MPX_TAGS_IN; 55 | -- 56 | FI : out STD_LOGIC_VECTOR(0 to 8); -- Mpx Bus In to CPU 57 | FAK : in STD_LOGIC; 58 | RECYCLE_RST : in STD_LOGIC; 59 | CK_P_BIT : in STD_LOGIC; 60 | ALU_CHK_LCH : in STD_LOGIC; 61 | CHK_SW_PROC_SW : in STD_LOGIC; 62 | N1050_REQ_IN : in STD_LOGIC; 63 | ROS_SCAN : in STD_LOGIC; 64 | FBK_T2 : in STD_LOGIC; 65 | FT5_BIT_SEL_IN : out STD_LOGIC; 66 | SERV_IN_SIGNAL : out STD_LOGIC; 67 | STATUS_IN_SIGNAL : out STD_LOGIC; 68 | FT3_BIT_MPX_SHARE_REQ : out STD_LOGIC; 69 | MPX_SHARE_REQ : out STD_LOGIC; 70 | T1,T2,T3 : in STD_LOGIC; 71 | ANY_PRIORITY_LCH : in STD_LOGIC; 72 | CK_SALS_PWR : in STD_LOGIC_VECTOR (0 to 3); 73 | SET_BUS_O_CTRL_LCH : in STD_LOGIC; 74 | N1401_MODE : in STD_LOGIC; 75 | N1050_OP_IN : in STD_LOGIC; 76 | N1050_CE_MODE : in STD_LOGIC; 77 | MPX_METERING_IN : out STD_LOGIC; 78 | FT7_MPX_CHNL_IN : in STD_LOGIC; 79 | LOAD_IND : in STD_LOGIC; 80 | SUPPR_CTRL_LCH : in STD_LOGIC; 81 | OP_OUT_SIGNAL : in STD_LOGIC; 82 | OP_OUT_SIG : in STD_LOGIC; 83 | SEL_O_FT6 : out STD_LOGIC; 84 | N1050_SEL_IN : out STD_LOGIC; 85 | n1050_SEL_O : in STD_LOGIC; 86 | P_1050_SEL_IN : out STD_LOGIC; 87 | P_1050_SEL_OUT : out STD_LOGIC; 88 | N1050_INSTALLED : in STD_LOGIC; 89 | SUPPR_O : out STD_LOGIC; 90 | DEBUG : inout DEBUG_BUS; 91 | METERING_OUT : in STD_LOGIC; 92 | CLOCK_OUT : in STD_LOGIC; 93 | CLK : in STD_LOGIC; 94 | -- Mpx Indicators 95 | OPNL_IN,ADDR_IN,STATUS_IN,SERVICE_IN, 96 | SELECT_OUT,ADDR_OUT,COMMAND_OUT,SERVICE_OUT, 97 | SUPPRESS_OUT : out std_logic); -- 08A 98 | 99 | end MpxFA; 100 | 101 | architecture FMD of MpxFA is 102 | signal sSERV_IN_SIGNAL, sSTATUS_IN_SIGNAL, sADDR_OUT, sSUPPR_O, sOP_OUT : STD_LOGIC; 103 | signal SIS1,SIS2,SIS3 : STD_LOGIC; 104 | signal OP_INLK_SET, OP_INLK : STD_LOGIC; 105 | signal SERV_OUT, CMD_OUT : STD_LOGIC; 106 | signal sTAGS_OUT : MPX_TAGS_OUT; 107 | signal sTAGS_IN : MPX_TAGS_IN; 108 | signal sFT5_BIT_SEL_IN, Reset_SELO : STD_LOGIC; 109 | signal sn1050_SEL_OUT : STD_LOGIC; 110 | signal sn1050_SEL_IN : STD_LOGIC; 111 | signal CMD_STT_Set, RST_CMD_RSTT_ADDR_OUT, CMD_STT : STD_LOGIC; 112 | signal sFT3_BIT_MPX_SHARE_REQ, sSEL_O_FT6, sSUPPR_O_FT0 : STD_LOGIC; 113 | signal FAK_T2 : STD_LOGIC; 114 | signal SetAdrO2, ADDR_OUT_2, SetAdrOut, SetCmdO, RstCmdO, SetSrvO, RstSrvO : STD_LOGIC; 115 | signal SetCUBusyInlk, ResetCUBusyInlk, CUBusy, RST_STT_SEL_OUT : STD_LOGIC; 116 | signal ResetBusOCtrl, BUSOCtrl : STD_LOGIC; 117 | signal SetStartSelO, ResetStartSelO, StartSelO : STD_LOGIC; 118 | signal NO_1050_SEL_O : STD_LOGIC; 119 | signal SetSelReq, ResetSelReq, SetSelOInlk, SelOInlk : STD_LOGIC; 120 | signal SS_RECYCLE_RST : STD_LOGIC; 121 | signal NOT_OPL_IN : STD_LOGIC; 122 | begin 123 | 124 | STATUS_IN <= sTAGS_IN.STA_IN; 125 | SERVICE_IN <= sTAGS_IN.SRV_IN; 126 | ADDR_IN <= sTAGS_IN.ADR_IN; -- AA3F3 127 | OPNL_IN <= sTAGS_IN.OPL_IN; -- AA3F2 AA3F5 128 | 129 | SIS1 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.SRV_IN) or OP_INLK; -- AA3F2 AA3E2 130 | sSERV_IN_SIGNAL <= SIS1 and (not sTAGS_IN.STA_IN or not sTAGS_IN.SRV_IN); -- Wire-AND, not sure about the OR bit 131 | SERV_IN_SIGNAL <= sSERV_IN_SIGNAL; 132 | 133 | SIS3 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.STA_IN) or (OP_INLK and not sTAGS_OUT.ADR_OUT); -- AA3D7 AA3E2 134 | sSTATUS_IN_SIGNAL <= SIS3 and (not sTAGS_IN.STA_IN or not sTAGS_IN.SRV_IN); -- Wire-AND, not sure about the OR bit 135 | STATUS_IN_SIGNAL <= sSTATUS_IN_SIGNAL; 136 | 137 | OP_INLK_SET <= not sTAGS_IN.OPL_IN and T2; 138 | OP_INLK_FL: entity FLL port map (S=>OP_INLK_SET, R=> T1, Q=>OP_INLK); -- AA3E4 ?? R=> NOT T1 ?? 139 | 140 | sn1050_SEL_IN <= sTAGS_IN.SEL_IN; 141 | n1050_SEL_IN <= sn1050_SEL_IN; 142 | sFT5_BIT_SEL_IN <= (sn1050_SEL_IN and not n1050_INSTALLED) or sn1050_SEL_IN; -- AA3E5 AA3E2 143 | FT5_BIT_SEL_IN <= sFT5_BIT_SEL_IN; 144 | 145 | Reset_SELO <= RECYCLE_RST or FBK_T2 or sFT5_BIT_SEL_IN; -- AA3D7 AA3E7 146 | 147 | CMD_STT_Set <= CK_P_BIT and FAK_T2; -- ?? FMD has FAK not FAK_T2 148 | RST_CMD_RSTT_ADDR_OUT <= (FAK and T1) or RECYCLE_RST; -- AA3E6 AA3E2 149 | CMD_STT_FL: entity FLL port map (S=>CMD_STT_Set, R=>RST_CMD_RSTT_ADDR_OUT, Q=>CMD_STT); -- AA3D7 AA3E7 150 | sFT3_BIT_MPX_SHARE_REQ <= (ROS_SCAN or not CMD_STT) and (N1050_REQ_IN or sTAGS_IN.REQ_IN or (ALU_CHK_LCH and CHK_SW_PROC_SW) or sTAGS_IN.OPL_IN); -- AA3F2 AA3E5 AA3G4 151 | 152 | MPX_SHARE_REQ <= sFT3_BIT_MPX_SHARE_REQ; 153 | FT3_BIT_MPX_SHARE_REQ <= sFT3_BIT_MPX_SHARE_REQ; 154 | 155 | sTAGS_IN.OPL_IN <= TAGS_IN.OPL_IN or (DIAG_SW and BUS_O_REG(7)); -- AA3B4 156 | sTAGS_IN.ADR_IN <= TAGS_IN.ADR_IN or (DIAG_SW and BUS_O_REG(6)); -- AA3B4 157 | sTAGS_IN.STA_IN <= TAGS_IN.STA_IN or (DIAG_SW and BUS_O_REG(4)); -- AA3B4 158 | sTAGS_IN.SRV_IN <= TAGS_IN.SRV_IN or (DIAG_SW and BUS_O_REG(5)); -- AA3B4 159 | sTAGS_IN.SEL_IN <= TAGS_IN.SEL_IN or (DIAG_SW and BUS_O_REG(0)); -- AA3B4 160 | sTAGS_IN.REQ_IN <= TAGS_IN.REQ_IN; 161 | sTAGS_IN.MTR_IN <= TAGS_IN.MTR_IN; 162 | 163 | MPX_BUS_OUT_BITS <= BUS_O_REG; 164 | 165 | FAK_T2 <= FAK and (T2 and not ANY_PRIORITY_LCH); -- AA3B7 AA3F4 AA3E6 166 | 167 | SetAdrO2 <= T3 and sADDR_OUT; 168 | ADDR_OUT_2_FL: entity FLL port map (S=>SetAdrO2, R=>RST_CMD_RSTT_ADDR_OUT, Q=>ADDR_OUT_2); -- AA3E4 169 | 170 | SetAdrOut <= FAK_T2 and CK_SALS_PWR(1); 171 | ADDR_OUT_FL: entity FLL port map (S=>SetAdrOut, R=>RST_CMD_RSTT_ADDR_OUT, Q=>sADDR_OUT); -- AA3D7 AA3E7 172 | ADDR_OUT <= sADDR_OUT; 173 | 174 | SetCmdO <= FAK_T2 and CK_SALS_PWR(2); 175 | RstCmdO <= not sTAGS_IN.ADR_IN and not sTAGS_IN.SRV_IN and not sTAGS_IN.STA_IN; 176 | CMD_O: entity FLL port map (S=>SetCmdO, R=>RstCmdO, Q=>CMD_OUT); -- AA3E4 AA3E5 177 | sTAGS_OUT.CMD_OUT <= CMD_OUT; 178 | 179 | SetSrvO <= FAK_T2 and CK_SALS_PWR(3); 180 | RstSrvO <= not sTAGS_IN.SRV_IN and not sTAGS_IN.STA_IN; 181 | SRV_O: entity FLL port map (S=>SetSrvO, R=>RstSrvO, Q=>SERV_OUT); -- AA3C7 182 | 183 | SetCUBusyInlk <= sTAGS_IN.STA_IN and ADDR_OUT_2 and FBK_T2; 184 | ResetCUBusyInlk <= not sADDR_OUT and T2; 185 | CU_BUSY_INLK: entity FLL port map (S=>SetCUBusyInlk, R=>ResetCUBusyInlk, Q=>CUBusy); -- AA3B5 186 | RST_STT_SEL_OUT <= not OP_OUT_SIG or CUBusy; -- AA3F7 187 | 188 | ResetBusOCtrl <= not sADDR_OUT and not CMD_OUT and not SERV_OUT; -- AA3D7 189 | BUS_O_CTRL: entity FLL port map (S=>SET_BUS_O_CTRL_LCH, R=>ResetBusOCtrl, Q=>BUSOCtrl); -- AA3J5 190 | 191 | SetStartSelO <= ADDR_OUT_2 and T2 and BUSOCtrl; -- AA3E6 192 | ResetStartSelO <= RST_STT_SEL_OUT or (not N1401_MODE and sTAGS_IN.ADR_IN) or (not ADDR_OUT_2 and Reset_SelO); -- AA3F5 AA3K3 193 | START_SEL_O: entity FLL port map (S=>SetStartSelO, R=>ResetStartSelO, Q=>StartSelO); -- AA3L4 AA3E7 194 | sSEL_O_FT6 <= not CUBusy and (StartSelO or NO_1050_SEL_O or sN1050_SEL_OUT); -- AA3E5 195 | SEL_O_FT6 <= sSEL_O_FT6; 196 | NO_1050_SEL_O <= not N1050_INSTALLED and n1050_SEL_O; -- AA3D2 197 | 198 | SetSelReq <= not SelOInlk and T2 and sFT3_BIT_MPX_SHARE_REQ; 199 | ResetSelReq <= SelOInlk or not sFT3_BIT_MPX_SHARE_REQ; 200 | SEL_REQ: entity FLL port map (S=>SetSelReq, R=>ResetSelReq, Q=>sN1050_SEL_OUT); -- AA3F4 201 | -- To Select Out Propagation in 10B 202 | P_1050_SEL_OUT <= sN1050_SEL_OUT; 203 | 204 | SetSelOInlk <= (sTAGS_IN.ADR_IN and sTAGS_IN.OPL_IN) or (N1050_OP_IN and not N1050_CE_MODE); -- AA3B7 205 | NOT_OPL_IN <= not sTAGS_IN.OPL_IN; 206 | SEL_O_INLK: entity FLL port map (S=>SetSelOInlk, R=>NOT_OPL_IN, Q=>SelOInlk); -- AA3C7 207 | -- sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) or not LOAD_IND or SUPPR_CTRL_LCH; -- AA3C7 AA3E5 208 | sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) and not LOAD_IND and SUPPR_CTRL_LCH; -- AA3C7 AA3E5 ?? AA3C7 shown as 'OR' 209 | SUPPR_O <= sSUPPR_O; 210 | 211 | SS_RECYCLE_RST <= RECYCLE_RST; -- AA3G3 Single Shot ?? 212 | sOP_OUT <= OP_OUT_SIGNAL and not SS_RECYCLE_RST; -- AA3D6 213 | 214 | sTAGS_OUT.ADR_OUT2 <= ADDR_OUT_2; 215 | sTAGS_OUT.ADR_OUT <= sADDR_OUT; 216 | -- sTAGS_OUT.CMD_OUT <= CMD_OUT; 217 | sTAGS_OUT.SRV_OUT <= SERV_OUT; 218 | sTAGS_OUT.SEL_OUT <= sSEL_O_FT6; -- ?? 219 | sTAGS_OUT.MTR_OUT <= METERING_OUT; 220 | sTAGS_OUT.CLK_OUT <= CLOCK_OUT; 221 | sTAGS_OUT.SUP_OUT <= sSUPPR_O; 222 | sTAGS_OUT.OPL_OUT <= sOP_OUT; 223 | -- sTAGS_OUT.SEL_OUT <= '0'; -- ?? 224 | sTAGS_OUT.STA_OUT <= '0'; -- ?? 225 | sTAGS_OUT.HLD_OUT <= '0'; -- ?? 226 | 227 | TAGS_OUT <= sTAGS_OUT; 228 | 229 | FI <= MPX_BUS_IN_BITS; 230 | 231 | -- Output tag indicators not really shown 232 | SELECT_OUT <= sSEL_O_FT6; 233 | ADDR_OUT <= sADDR_OUT; 234 | COMMAND_OUT <= CMD_OUT; 235 | SERVICE_OUT <= SERV_OUT; 236 | SUPPRESS_OUT <= sSUPPR_O; 237 | 238 | end FMD; 239 | 240 | -------------------------------------------------------------------------------- /FMD2030_5-09C.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-09C.vhd 23 | -- Creation Date: 24 | -- Description: 25 | -- 1050 Typewriter Console input and output translation circuitry and 26 | -- Control Character detection 27 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 28 | -- for the 360/30 R25-5103-1 29 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 30 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 31 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 32 | -- C is the core storage and X is the CCROS unit 33 | -- 34 | -- Revision History: 35 | -- Revision 1.0 2012-04-07 36 | -- Initial release 37 | --------------------------------------------------------------------------- 38 | LIBRARY ieee; 39 | USE ieee.std_logic_1164.all; 40 | USE ieee.std_logic_unsigned.all; 41 | 42 | library work; 43 | use work.Gates_package.all; 44 | use work.Buses_package.all; 45 | use work.FLL; 46 | 47 | ENTITY n1050_TRANSLATE IS 48 | port 49 | ( 50 | -- Inputs 51 | DATA_REG_BUS : IN STD_LOGIC_VECTOR(0 to 7); -- 10C 52 | RDR_ON_LCH : IN STD_LOGIC; -- 10BD3 53 | PUNCH_1_CLUTCH_1050 : IN STD_LOGIC; -- 10DD5 aka PCH_1_CLUTCH_1050 54 | HOME_RDR_STT_LCH : IN STD_LOGIC; -- 10BB3 55 | CLOCK_STT_RST : IN STD_LOGIC; -- 10AC2 56 | RST_ATTACH : IN STD_LOGIC; -- 10BC2 57 | W_TIME, X_TIME, Y_TIME, Z_TIME : IN STD_LOGIC; -- 10AXX 58 | n1050_RST : IN STD_LOGIC; -- 10BA3 59 | ALLOW_STROBE : IN STD_LOGIC; -- 10CB6 60 | PROCEED_LCH : IN STD_LOGIC; -- 10BC3 61 | SHARE_REQ_RST : IN STD_LOGIC; -- 10BB6 62 | CE_RUN_MODE : IN STD_LOGIC; -- 10DB2 63 | CE_TI_DECODE : IN STD_LOGIC; -- 10DB2 64 | SET_LOWER_CASE : IN STD_LOGIC; -- 10CC5 65 | n1050_RST_LCH : IN STD_LOGIC; -- 10BA3 66 | READY_SHARE : IN STD_LOGIC; -- 10CE6 67 | 68 | -- Outputs 69 | TT2_POS_END : OUT STD_LOGIC; -- 10BD3 70 | XLATE_UC : OUT STD_LOGIC; -- 10C 71 | RD_SHARE_REQ_LCH : OUT STD_LOGIC; -- 10CD4 10BC3 10BD4 72 | READ_SHARE_REQ : OUT STD_LOGIC; -- 10BD3 73 | WRITE_UC : OUT STD_LOGIC; -- 10DD2 74 | SET_SHIFT_LCH : OUT STD_LOGIC; -- 10CC4 75 | PCH_1_HOME : OUT STD_LOGIC; -- 10DC5 76 | RUN : OUT STD_LOGIC; -- 10BB3 10CC3 10BD1 10CE4 10CD2 77 | UNGATED_RUN : OUT STD_LOGIC; -- 10BC4 78 | READ : OUT STD_LOGIC; -- 10CD4 79 | READ_INQ : OUT STD_LOGIC; -- 10CD4 80 | LC_CHARACTER, UC_CHARACTER : OUT STD_LOGIC; -- 10CC5 81 | WRITE_LCH : OUT STD_LOGIC; -- 10BD3 10AC1 10AA2 10BB1 10CA5 10CC3 82 | WRITE_MODE : OUT STD_LOGIC; -- 10CD4 83 | WRITE_STROBE : OUT STD_LOGIC; -- 10DC5 84 | WRITE_LCH_RST : OUT STD_LOGIC; -- 10BA1 85 | RD_OR_RD_INQ : OUT STD_LOGIC; 86 | 87 | DEBUG : INOUT DEBUG_BUS 88 | 89 | -- Clocks 90 | -- T1,T2,T3,T4 : IN STD_LOGIC; 91 | -- P1,P2,P3,P4 : IN STD_LOGIC 92 | 93 | ); 94 | END n1050_TRANSLATE; 95 | 96 | ARCHITECTURE FMD OF n1050_TRANSLATE IS 97 | signal sLC_CHARACTER, sUC_CHARACTER : STD_LOGIC; 98 | signal DataReg4511, DataReg23not00 : STD_LOGIC; 99 | signal EndCode : STD_LOGIC; 100 | signal DataRegSpecial1, DataRegSpecial2, DataRegSpecial3, DataRegSpecial : STD_LOGIC; 101 | signal XLATE_UC_SET, XLATE_UC_RESET : STD_LOGIC; 102 | signal RD_SHARE_REQ_SET, RD_SHARE_REQ_RESET : STD_LOGIC; 103 | signal PREFIX_SET,PREFIX_RESET,PREFIX : STD_LOGIC; 104 | signal BLOCK_SHIFT_SET,BLOCK_SHIFT : STD_LOGIC; 105 | signal sWRITE_LCH : STD_LOGIC; 106 | signal UPPER_CASE_DECODE, LOWER_CASE_DECODE : STD_LOGIC; 107 | signal sRD_SHARE_REQ_LCH : STD_LOGIC; 108 | signal sREAD, sREAD_INQ, sRD_OR_RD_INQ : STD_LOGIC; 109 | signal DataReg01xxxxxx, DataRegLCA, DataRegLCB, DataRegLCC, DataRegLCD, DataRegLCE : STD_LOGIC; 110 | signal DataRegLC, DataRegUC : STD_LOGIC; 111 | signal PRT_IN_UC_SET, PRT_IN_UC_RESET, PRT_IN_UC : STD_LOGIC; 112 | signal WRITE_SET, WRITE_RESET : STD_LOGIC; 113 | signal sUNGATED_RUN : STD_LOGIC; 114 | 115 | BEGIN 116 | -- Fig 5-09C 117 | -- Incoming character handling (keyboard codes AB8421 = 234567) 118 | DataReg4511 <= DATA_REG_BUS(4) and DATA_REG_BUS(5); -- AC3F4 AC3D4 XX11XX 119 | DataReg23not00 <= DATA_REG_BUS(2) or DATA_REG_BUS(3); -- AC3B6 01XXXX 10XXXX 11XXXX 120 | -- EndCode <= DATA_REG_BUS(1) and DataReg4511 and not DATA_REG_BUS(2) and DATA_REG_BUS(6); -- 10x111x = EOB 121 | EndCode <= '1' when DATA_REG_BUS="0000100" else '0'; -- End is 04=Ctrl+D 122 | TT2_POS_END <= (EndCode and sRD_SHARE_REQ_LCH) or READY_SHARE; -- AC3F7 AC3F2 AC3C7 ?? *or* READY_SHARE ?? 123 | -- UPPER_CASE_DECODE <= not DATA_REG_BUS(7) and DATA_REG_BUS(6) and DataReg4511 and not DataReg23not00; -- AC3E2 AB8421=001110=Upshift 124 | UPPER_CASE_DECODE <= '0'; 125 | -- LOWER_CASE_DECODE <= DATA_REG_BUS(6) and not DATA_REG_BUS(7) and DATA_REG_BUS(2) and DATA_REG_BUS(3) and DataReg4511; -- AC3F7 AB8421=111110=Downshift 126 | LOWER_CASE_DECODE <= '0'; 127 | -- The following three lines are probably wrong 128 | DataRegSpecial1 <= DataReg23not00 and DataReg4511 and DATA_REG_BUS(6) and DATA_REG_BUS(7); -- AC3E2 "xx1111" but not "111111" 129 | DataRegSpecial2 <= DataReg4511 and DATA_REG_BUS(7) and not DataReg23not00 and not DATA_REG_BUS(6); -- AC3E2 "101101" = Return 130 | DataRegSpecial3 <= DataReg4511 and not DATA_REG_BUS(6) and not DATA_REG_BUS(7); -- AC3B6 "xx1100" 131 | -- DataRegSpecial <= DataRegSpecial1 or DataRegSpecial2 or DataRegSpecial3; 132 | DataRegSpecial <= '0'; -- Ignore for now 133 | 134 | XLATE_UC_SET <= UPPER_CASE_DECODE and X_TIME; -- AC3F2 135 | XLATE_UC_RESET <= SET_LOWER_CASE or (X_TIME and LOWER_CASE_DECODE); -- AC3F2 136 | XLATE_UC_FL: entity FLL port map (S=>XLATE_UC_SET, R=>XLATE_UC_RESET, Q=>XLATE_UC); -- ????? 137 | 138 | RD_SHARE_REQ_SET <= not DataRegSpecial and not UPPER_CASE_DECODE and not LOWER_CASE_DECODE and sRD_OR_RD_INQ and Y_TIME; 139 | RD_SHARE_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH or (CE_RUN_MODE and CE_TI_DECODE); 140 | RD_SHARE_REQ_FL: entity FLL port map(S=>RD_SHARE_REQ_SET, R=>RD_SHARE_REQ_RESET, Q=>sRD_SHARE_REQ_LCH); -- AC3F5 AC3C7 141 | RD_SHARE_REQ_LCH <= sRD_SHARE_REQ_LCH; 142 | READ_SHARE_REQ <= sRD_SHARE_REQ_LCH and not Y_TIME; -- AC3E3 143 | 144 | sREAD <= HOME_RDR_STT_LCH and RDR_ON_LCH and not sWRITE_LCH; -- AC2G7 145 | READ <= sREAD; 146 | sREAD_INQ <= not sWRITE_LCH and RDR_ON_LCH and PROCEED_LCH; -- AC2G7 147 | READ_INQ <= sREAD_INQ; 148 | sRD_OR_RD_INQ <= sREAD or sREAD_INQ; 149 | RD_OR_RD_INQ <= sRD_OR_RD_INQ; 150 | PCH_1_HOME <= PUNCH_1_CLUTCH_1050 or sREAD or sREAD_INQ; -- AC2G3 151 | 152 | -- Outgoing character handling 153 | -- Prefix is 0x100111 i.e. 27 or 67 154 | PREFIX_SET <= not DATA_REG_BUS(0) and DATA_REG_BUS(2) and not DATA_REG_BUS(3) 155 | and not DATA_REG_BUS(4) and DATA_REG_BUS(5) and DATA_REG_BUS(6) and DATA_REG_BUS(7) and Z_TIME; -- AC3B7 AC3F2 AC3D6 156 | PREFIX_FL: entity FLL port map(S=>PREFIX_SET,R=>Y_TIME,Q=>PREFIX); -- AC3F2 AC3G5 157 | -- Block Shift prevents the shift mechanism from being triggered 158 | BLOCK_SHIFT_SET <= PREFIX and X_TIME; 159 | BLOCK_SHIFT_FL: entity FLL port map(S=>BLOCK_SHIFT_SET,R=>W_TIME,Q=>BLOCK_SHIFT); -- AC3F2 AC3C6 160 | 161 | DataReg01xxxxxx <= not DATA_REG_BUS(0) and DATA_REG_BUS(1); -- AC3D5 AC3B4 162 | DataRegLCA <= not DATA_REG_BUS(5) and DATA_REG_BUS(7) and DataReg01xxxxxx; -- 01xxx0x1 = 01xx0001 "/" 01xx0011 01xx1001 01xx1011 ".$,#" 163 | DataRegLCB <= not DATA_REG_BUS(4) and not DATA_REG_BUS(6) and DataReg01xxxxxx; -- 01xx0x0x = 01xx0000 "-&" 01xx0001 "/" 01xx0100 01xx0101 164 | DataRegLCC <= DATA_REG_BUS(0) and DATA_REG_BUS(1) and DATA_REG_BUS(2) and DATA_REG_BUS(3); -- AC3F5 1111xxxx = 0-9 = LC 165 | DataRegLCD <= DATA_REG_BUS(2) and DATA_REG_BUS(3) and not DATA_REG_BUS(6) and not DATA_REG_BUS(7) 166 | and DataReg01xxxxxx; -- AC3B7 0111xx00 = 01110000 01110100 01111000 01111100 "@" 167 | DataRegLCE <= DATA_REG_BUS(0) and not DATA_REG_BUS(1); -- AC3E5 10xxxxxx = LC 168 | DataRegLC <= DataRegLCA or DataRegLCB or DataRegLCC or DataRegLCD or DataRegLCE; 169 | DataRegUC <= not DataRegLC and DATA_REG_BUS(1); 170 | sLC_CHARACTER <= DataRegLC and not BLOCK_SHIFT; 171 | LC_CHARACTER <= sLC_CHARACTER; 172 | sUC_CHARACTER <= DataRegUC and not BLOCK_SHIFT; 173 | UC_CHARACTER <= sUC_CHARACTER; 174 | 175 | -- PRT_IN_UC remembers whether the printer is already in UC mode 176 | PRT_IN_UC_SET <= sUC_CHARACTER and Z_TIME and ALLOW_STROBE; 177 | PRT_IN_UC_RESET <= (sLC_CHARACTER and Z_TIME and ALLOW_STROBE) or SET_LOWER_CASE; -- AC3F4 178 | PRINT_IN_UC_FL: entity FLL port map(S=>PRT_IN_UC_SET,R=>PRT_IN_UC_RESET,Q=>PRT_IN_UC); -- ????? 179 | WRITE_UC <= PRT_IN_UC; 180 | -- For now the SHIFT function is disabled as it is not required for ASCII output 181 | -- SET_SHIFT_LCH <= not ((PRT_IN_UC and sLC_CHARACTER and sWRITE_LCH) or (sUC_CHARACTER and sWRITE_LCH and not PRT_IN_UC)); -- AC2E5 AC3D4 182 | SET_SHIFT_LCH <= '0'; 183 | 184 | WRITE_SET <= not RDR_ON_LCH and not PUNCH_1_CLUTCH_1050 and HOME_RDR_STT_LCH; -- AC2G7 185 | WRITE_RESET <= CLOCK_STT_RST or RST_ATTACH; 186 | WRITE_FL : entity FLL port map(S=>WRITE_SET,R=>WRITE_RESET,Q=>sWRITE_LCH); -- AC2J5 AC2H6 187 | WRITE_LCH <= sWRITE_LCH; 188 | WRITE_LCH_RST <= sWRITE_LCH; 189 | WRITE_MODE <= WRITE_SET and not n1050_RST; -- AC2D7 190 | WRITE_STROBE <= Z_TIME and ALLOW_STROBE and sWRITE_LCH; -- AC2K6 191 | 192 | -- Stuff common to input and output 193 | sUNGATED_RUN <= sREAD_INQ or sREAD or sWRITE_LCH; -- AC2G3 194 | UNGATED_RUN <= sUNGATED_RUN; 195 | RUN <= sUNGATED_RUN and not n1050_RST_LCH; -- AC2K5 AC2H6 196 | 197 | END FMD; 198 | 199 | -------------------------------------------------------------------------------- /FMD2030_5-10A.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-10A.vhd 23 | -- Creation Date: 24 | -- Description: 25 | -- 1050 Typewriter Console clock control and generation 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2012-04-07 35 | -- Initial release 36 | --------------------------------------------------------------------------- 37 | LIBRARY ieee; 38 | Library UNISIM; 39 | use UNISIM.vcomponents.all; 40 | USE ieee.std_logic_1164.all; 41 | USE ieee.std_logic_unsigned.all; 42 | 43 | library work; 44 | use work.Gates_package.all; 45 | use work.Buses_package.all; 46 | use work.FLL; 47 | 48 | ENTITY n1050_CLOCK IS 49 | port 50 | ( 51 | -- Inputs 52 | WRITE_LCH : IN STD_LOGIC; -- 09CD2 53 | READ_OR_READ_INQ : IN STD_LOGIC; -- 09CC5 54 | RST_ATTACH : IN STD_LOGIC; -- 10BC2 55 | PUNCH_1_CLUTCH : IN STD_LOGIC; -- 10DD5 56 | READ_CLK_INTLK_LCH : IN STD_LOGIC; -- 10BA2 57 | RDR_1_CLUTCH : IN STD_LOGIC; -- 10DD5 58 | CRLF : IN STD_LOGIC; -- ? 59 | 60 | -- Outputs 61 | CLOCK_1 : OUT STD_LOGIC; -- 10CD1 10CA4 62 | W_TIME, X_TIME, Y_TIME, Z_TIME : OUT STD_LOGIC; 63 | CLK_STT_RST : OUT STD_LOGIC; -- 09CE1 64 | 65 | -- Temp 66 | -- POSTRIG, NEGTRIG : OUT STD_LOGIC; 67 | -- OSCOut,C1,C2 : OUT STD_LOGIC; 68 | -- OSCOut,C1,C2 : OUT STD_LOGIC; 69 | 70 | -- Clocks 71 | clk : IN STD_LOGIC -- 50MHz clock 72 | ); 73 | END n1050_CLOCK; 74 | 75 | ARCHITECTURE FMD OF n1050_CLOCK IS 76 | -- Output rate is 9600bps or 960chars/sec or 1.04ms/char. We set the clock to run at 1.2ms/4 or 300us (300 * 50 = 15000 cycles) 77 | -- constant ClockDivider : integer := 15000; 78 | constant ClockDivider : integer := 250; -- Gives 5us OSC rate 79 | 80 | signal OSC : STD_LOGIC; -- Inverted signal 81 | signal CLK_START : STD_LOGIC; 82 | signal TRIGER : STD_LOGIC; 83 | signal nTRIG : STD_LOGIC; 84 | signal BIN_CNTR : STD_LOGIC_VECTOR(1 to 2); 85 | signal Counter : integer; 86 | signal sCLK_STT_RST : STD_LOGIC; 87 | signal CLK_START_SET, CLK_START_RESET : STD_LOGIC; 88 | signal W_SET, X_SET, Y_SET, Z_SET : STD_LOGIC; 89 | signal W_RESET, X_RESET, Y_RESET, Z_RESET : STD_LOGIC; 90 | signal sW_TIME, sX_TIME, sY_TIME, sZ_TIME : STD_LOGIC; 91 | 92 | BEGIN 93 | -- Fig 5-10A 94 | sCLK_STT_RST <= OSC and not BIN_CNTR(1) and sZ_TIME and not sW_TIME; -- AC2H4 95 | CLK_STT_RST <= sCLK_STT_RST; 96 | CLK_START_SET <= (PUNCH_1_CLUTCH and not READ_CLK_INTLK_LCH and READ_OR_READ_INQ) 97 | or (RDR_1_CLUTCH and WRITE_LCH and not CRLF); 98 | CLK_START_RESET <= RST_ATTACH or sCLK_STT_RST; 99 | CLK_START_FL : entity FLL port map(CLK_START_SET,CLK_START_RESET,CLK_START); -- AC2G6 AC2F6 100 | 101 | BIN_CNTR_P: process(OSC,RST_ATTACH) is 102 | begin 103 | if RST_ATTACH='1' then 104 | BIN_CNTR <= "01"; 105 | else if rising_edge(OSC) then 106 | BIN_CNTR <= BIN_CNTR + "01"; 107 | end if; 108 | end if; 109 | end process; 110 | 111 | OSC_P : process(CLK_START,clk) is 112 | begin 113 | if falling_edge(clk) then 114 | if (CLK_START='0') then 115 | OSC <= '1'; 116 | Counter <= 0; 117 | else 118 | Counter <= Counter + 1; 119 | if Counter=ClockDivider then 120 | Counter <= 0; 121 | end if; 122 | if (Counter > (ClockDivider/2)) then 123 | OSC <= '1'; 124 | else 125 | OSC <= '0'; 126 | end if; 127 | end if; 128 | end if; 129 | end process; 130 | 131 | TRIGER <= (not BIN_CNTR(1) and WRITE_LCH) or (READ_OR_READ_INQ and BIN_CNTR(2)); -- AC2G7 132 | nTRIG <= (not BIN_CNTR(2) and not WRITE_LCH) or (BIN_CNTR(1) and WRITE_LCH); -- AC2F7 AC2M2 133 | -- POSTRIG <= TRIGER; 134 | -- NEGTRIG <= nTRIG; 135 | -- OSCOut <= OSC; 136 | -- C1 <= BIN_CNTR(1); 137 | -- C2 <= BIN_CNTR(2); 138 | 139 | W_SET <= not sY_TIME and sZ_TIME and (TRIGER and CLK_START); -- AC2E7 AC2F6 ?? 'not' gate ignored 140 | X_SET <= not sZ_TIME and sW_TIME and nTRIG; 141 | Y_SET <= not sW_TIME and sX_TIME and TRIGER; -- AC2G2 142 | Z_SET <= (not sX_TIME and sY_TIME and nTRIG) or RST_ATTACH or (OSC and not CLK_START); -- AC2E7 ?? RST_ATTACH or (OSC and not CLK_START) ?? 143 | W_RESET <= (sX_TIME and TRIGER) or RST_ATTACH; -- AC2D7 144 | X_RESET <= (sY_TIME and nTRIG) or RST_ATTACH; -- AC2G3 145 | Y_RESET <= (sZ_TIME and TRIGER) or RST_ATTACH or (OSC and not CLK_START); -- AC2F7 146 | Z_RESET <= (sW_TIME and nTRIG); -- AC2G3 147 | 148 | W_JK: FDRSE port map(C=>clk,Q=>sW_TIME,R=>W_RESET,S=>W_SET,CE=>'0',D=>'0'); 149 | -- W_FL : FLL port map(W_SET,W_RESET,sW_TIME); -- AC2G2 150 | W_TIME <= sW_TIME; 151 | X_JK: FDRSE port map(C=>clk,Q=>sX_TIME,R=>X_RESET,S=>X_SET,CE=>'0',D=>'0'); 152 | -- X_FL : FLL port map(X_SET,X_RESET,sX_TIME); -- AC2G2 153 | X_TIME <= sX_TIME; 154 | Y_JK: FDRSE port map(C=>clk,Q=>sY_TIME,R=>Y_RESET,S=>Y_SET,CE=>'0',D=>'0'); 155 | -- Y_FL : FLL port map(Y_SET,Y_RESET,sY_TIME); -- AC2G2 156 | Y_TIME <= sY_TIME; 157 | Z_JK: FDRSE port map(C=>clk,Q=>sZ_TIME,R=>Z_RESET,S=>Z_SET,CE=>'0',D=>'0'); 158 | -- Z_FL : FLL port map(Z_SET,Z_RESET,sZ_TIME); -- AC2F5 159 | Z_TIME <= sZ_TIME; 160 | 161 | CLOCK1_FL : entity FLL port map(W_SET,X_RESET,CLOCK_1); -- ?? CLOCK_1 isn't defined in the diagrams 162 | -- This is a guess at CLOCK_1 being W_TIME OR X_TIME, but can't do that directly without possible glitches 163 | 164 | END FMD; 165 | 166 | -------------------------------------------------------------------------------- /FMD2030_5-10D.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2012 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: FMD2030_5-10D.vhd 23 | -- Creation Date: 24 | -- Description: 25 | -- 1050 Typewriter Console attachment and CE section 26 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 27 | -- for the 360/30 R25-5103-1 28 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 29 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 30 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 31 | -- C is the core storage and X is the CCROS unit 32 | -- 33 | -- Revision History: 34 | -- Revision 1.0 2012-04-07 35 | -- Initial release 36 | --------------------------------------------------------------------------- 37 | LIBRARY ieee; 38 | USE ieee.std_logic_1164.all; 39 | USE ieee.std_logic_unsigned.all; 40 | 41 | library work; 42 | use work.Gates_package.all; 43 | use work.Buses_package.all; 44 | use work.all; 45 | 46 | ENTITY n1050_ATTACH IS 47 | 48 | port 49 | ( 50 | -- Inputs 51 | -- CE Cable 52 | CE_CABLE_IN : IN CE_IN := ("00000000",'0','0','0','0','0','0','0','0','0','0'); 53 | -- CE DATA BUS From 1050 DATA section 54 | PTT_BITS : IN STD_LOGIC_VECTOR(0 to 6); 55 | DATA_REG : IN STD_LOGIC_VECTOR(0 to 7); 56 | NPL_BITS : IN STD_LOGIC_VECTOR(0 to 7); 57 | -- Other stuff 58 | TE_LCH : IN STD_LOGIC; -- 10CB5 59 | WRITE_UC : IN STD_LOGIC; -- 09CD6 60 | XLATE_UC : IN STD_LOGIC; -- 09CB6 61 | CPU_REQUEST_IN : IN STD_LOGIC; -- 10BD6 62 | n1050_OP_IN : IN STD_LOGIC; -- 10BB5 63 | HOME_RDR_STT_LCH : IN STD_LOGIC; -- 10BB3 64 | RDR_ON_LCH : IN STD_LOGIC; -- 10BD3 65 | MICRO_SHARE_LCH : IN STD_LOGIC; -- 10BC3 66 | PROCEED_LCH : IN STD_LOGIC; -- 10BC3 67 | TA_REG_POS_4 : IN STD_LOGIC; -- 10BE3 68 | CR_LF : IN STD_LOGIC; -- 10BE3 69 | TA_REG_POS_6 : IN STD_LOGIC; -- 10BE3 70 | n1050_RST : IN STD_LOGIC; -- 10BE2 71 | GT_WR_REG : IN STD_LOGIC; -- 10CB6 72 | FORCE_LC_SHIFT : IN STD_LOGIC; -- 10CC6 73 | FORCE_SHIFT_CHAR : IN STD_LOGIC; -- 10CC6 74 | WR_STROBE : IN STD_LOGIC; -- 09CD2 75 | PCH_1_HOME : IN STD_LOGIC; -- 09CD6 76 | HOME_RDR_STOP : IN STD_LOGIC; -- 10BB3 77 | TT2_POS_END : IN STD_LOGIC; -- 09CB5 - NOT IN FMD 78 | TT5_POS_INTRV_REQ : IN STD_LOGIC; -- 10CD5 79 | TT6_POS_ATTN : IN STD_LOGIC; -- 10BD6 80 | CPU_LINES_ENTRY : IN CONN_1050; -- 10BE3 81 | 82 | -- Outputs 83 | -- CE Cable 84 | CE_CABLE_OUT : OUT CE_OUT; 85 | -- CE DATA BUS to 10C (1050 DATA) 86 | CE_GT_TA_OR_TE : OUT STD_LOGIC; -- 10C 87 | CE_DATA_ENTER_GT : OUT STD_LOGIC; -- 10BB1 10CA4 10C 88 | CE_TE_DECODE : OUT STD_LOGIC; -- 10CA4 10C 89 | CE_MODE_AND_TE_LCH : OUT STD_LOGIC; 90 | n1050_CE_MODE : OUT STD_LOGIC; -- 10CB3 10BD5 91 | -- Other stuff 92 | CE_SEL_OUT : OUT STD_LOGIC; -- 10BD5 93 | CE_TI_DECODE : OUT STD_LOGIC; -- 09CC5 94 | CE_RUN_MODE : OUT STD_LOGIC; -- 09CC5 95 | CE_TA_DECODE : OUT STD_LOGIC; -- 10BB1 96 | CE_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 10C 97 | EXIT_MPLX_SHARE : OUT STD_LOGIC; -- 10BB5 98 | CE_DATA_ENTER_NC : OUT STD_LOGIC; 99 | -- TT3_POS_1050_OPER : OUT STD_LOGIC; -- 10BE2 10BB2 10BE2 10CE5 Moved to TT_BUS(3) 100 | -- TT4_POS_HOME_STT : OUT STD_LOGIC; -- 10CD2 Moved to TT_BUS(4) 101 | OUTPUT_SEL_AND_RDY : OUT STD_LOGIC; -- 10CD4 102 | n1050_OPER : OUT STD_LOGIC; -- 10CC4 10CE4 103 | PUNCH_BITS : OUT STD_LOGIC_VECTOR(0 to 6); -- 10CE1 104 | READ_INTLK_RST : OUT STD_LOGIC; -- 10BA1 105 | PUNCH_1_CLUTCH : OUT STD_LOGIC; -- 10CE1 10AC1 106 | -- PCH_1_CLUTCH_1050 : OUT STD_LOGIC; -- 09CE1 10BA1 09CD5 107 | REQUEST_KEY : OUT STD_LOGIC; -- 10BE4 108 | RDR_1_CLUTCH : OUT STD_LOGIC; 109 | 110 | -- In/Out TT bus 111 | TT_BUS : INOUT STD_LOGIC_VECTOR(0 to 7); 112 | GTD_TT3 : IN STD_LOGIC; 113 | 114 | -- Hardware Serial Port 115 | serialInput : in Serial_Input_Lines; 116 | serialOutput : out Serial_Output_Lines; 117 | 118 | -- Clocks 119 | T1,T2,T3,T4 : IN STD_LOGIC; 120 | P1,P2,P3,P4 : IN STD_LOGIC; 121 | clk : IN STD_LOGIC 122 | ); 123 | END n1050_ATTACH; 124 | 125 | ARCHITECTURE FMD OF n1050_ATTACH IS 126 | 127 | signal sCE_TA_DECODE, sCE_TE_DECODE : STD_LOGIC; 128 | signal sCE_DATA_ENTER_GT : STD_LOGIC; 129 | signal sn1050_CE_MODE : STD_LOGIC; 130 | signal sPUNCH_1_CLUTCH : STD_LOGIC; 131 | signal sRDR_1_CLUTCH : STD_LOGIC; 132 | signal sOUTPUT_SEL_AND_RDY : STD_LOGIC; 133 | signal TT1_POS_RDR_2_RDY, sTT3_POS_1050_OPER, sTT4_POS_HOME_STT : STD_LOGIC; 134 | signal PCH_CONN_ENTRY : PCH_CONN; 135 | signal RDR_1_CONN_EXIT : RDR_CONN; 136 | signal CPU_LINES_EXIT : CONN_1050; 137 | 138 | BEGIN 139 | -- Fig 5-10D 140 | sCE_TA_DECODE <= CE_CABLE_IN.CE_TA_DECODE; 141 | CE_TA_DECODE <= sCE_TA_DECODE; 142 | CE_GT_TA_OR_TE <= (CE_CABLE_IN.CE_TA_DECODE and sCE_DATA_ENTER_GT) or (sCE_TE_DECODE and sCE_DATA_ENTER_GT); -- AC2G5 143 | sCE_DATA_ENTER_GT <= CE_CABLE_IN.CE_TI_OR_TE_RUN_MODE; 144 | CE_DATA_ENTER_GT <= sCE_DATA_ENTER_GT; 145 | 146 | -- CE cable entry 147 | CE_BUS <= CE_CABLE_IN.CE_BIT; -- AC2M3 148 | sCE_TE_DECODE <= CE_CABLE_IN.CE_TE_DECODE; -- AC2M2 149 | CE_TE_DECODE <= sCE_TE_DECODE; 150 | CE_SEL_OUT <= CE_CABLE_IN.CE_SEL_OUT; -- AC2M2 151 | CE_TI_DECODE <= CE_CABLE_IN.CE_TI_DECODE; -- AC2M2 152 | CE_RUN_MODE <= not CE_CABLE_IN.CE_MODE; -- AC2M2 153 | 154 | CE_MODE_AND_TE_LCH <= (TE_LCH and sn1050_CE_MODE) or CE_CABLE_IN.CE_SEL_OUT; -- AC2E7 155 | sn1050_CE_MODE <= CE_CABLE_IN.CE_MODE; 156 | n1050_CE_MODE <= sn1050_CE_MODE; 157 | EXIT_MPLX_SHARE <= CE_CABLE_IN.CE_EXIT_MPLX_SHARE; 158 | CE_DATA_ENTER_NC <= CE_CABLE_IN.CE_DATA_ENTER_NC; 159 | 160 | -- CE cable exit 161 | CE_CABLE_OUT.PTT_BITS <= PTT_BITS; 162 | CE_CABLE_OUT.DATA_REG <= DATA_REG; 163 | CE_CABLE_OUT.RDR_1_CLUTCH <= sRDR_1_CLUTCH; 164 | CE_CABLE_OUT.WRITE_UC <= WRITE_UC; 165 | CE_CABLE_OUT.XLATE_UC <= XLATE_UC; 166 | CE_CABLE_OUT.PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH; 167 | CE_CABLE_OUT.NPL <= NPL_BITS; 168 | CE_CABLE_OUT.OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY; 169 | CE_CABLE_OUT.TT <= TT_BUS(0 to 2) & GTD_TT3 & TT_BUS(4 to 7); 170 | CE_CABLE_OUT.CPU_REQUEST_IN <= CPU_REQUEST_IN; 171 | CE_CABLE_OUT.n1050_OP_IN <= n1050_OP_IN; 172 | CE_CABLE_OUT.HOME_RDR_STT_LCH <= HOME_RDR_STT_LCH; 173 | CE_CABLE_OUT.RDR_ON_LCH <= RDR_ON_LCH; 174 | CE_CABLE_OUT.MICRO_SHARE_LCH <= MICRO_SHARE_LCH; 175 | CE_CABLE_OUT.PROCEED_LCH <= PROCEED_LCH; 176 | CE_CABLE_OUT.TA_REG_POS_4 <= TA_REG_POS_4; 177 | CE_CABLE_OUT.CR_LF <= CR_LF; 178 | CE_CABLE_OUT.TA_REG_POS_6 <= TA_REG_POS_6; 179 | CE_CABLE_OUT.n1050_RST <= n1050_RST; 180 | 181 | -- RDR connection (output) 182 | -- FORCE_LC_SHIFT and FORCE_SHIFT_CHAR makes 0111110 (downshift) 183 | -- FORCE_SHIFT_CHAR makes 0001110 (upshift) 184 | -- We remove this in favour of simple ASCII on the output 185 | -- RDR_1_CONN_EXIT.RDR_BITS <= (PTT_BITS(0) and GT_WR_REG) -- C 186 | -- & ((PTT_BITS(1) and GT_WR_REG) or FORCE_LC_SHIFT) -- B 187 | -- & ((PTT_BITS(2) and GT_WR_REG) or FORCE_LC_SHIFT) -- A 188 | -- & ((PTT_BITS(3) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 8 189 | -- & ((PTT_BITS(4) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 4 190 | -- & ((PTT_BITS(5) and GT_WR_REG) or FORCE_SHIFT_CHAR) -- 2 191 | -- & (PTT_BITS(6) and GT_WR_REG); -- 1 192 | RDR_1_CONN_EXIT.RDR_BITS <= PTT_BITS; 193 | RDR_1_CONN_EXIT.RD_STROBE <= WR_STROBE; 194 | CPU_LINES_EXIT <= CPU_LINES_ENTRY; 195 | 196 | -- TT Bus 197 | TT_BUS(1) <= TT1_POS_RDR_2_RDY; 198 | TT_BUS(2) <= TT2_POS_END; 199 | TT_BUS(3) <= sTT3_POS_1050_OPER; 200 | -- TT3_POS_1050_OPER <= sTT3_POS_1050_OPER; 201 | TT_BUS(4) <= sTT4_POS_HOME_STT; 202 | -- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT; 203 | TT_BUS(5) <= TT5_POS_INTRV_REQ; 204 | TT_BUS(6) <= TT6_POS_ATTN; 205 | 206 | -- PCH connections (input) 207 | PUNCH_BITS <= PCH_CONN_ENTRY.PCH_BITS; -- AC2L4 208 | READ_INTLK_RST <= '1' when PCH_CONN_ENTRY.PCH_BITS="0000000" else '0'; -- AC2E3 209 | sPUNCH_1_CLUTCH <= PCH_CONN_ENTRY.PCH_1_CLUTCH_1050; -- AC2M2 AC2J7 210 | PUNCH_1_CLUTCH <= sPUNCH_1_CLUTCH; 211 | -- PCH_1_CLUTCH_1050 <= sPUNCH_1_CLUTCH; 212 | TT1_POS_RDR_2_RDY <= PCH_CONN_ENTRY.RDR_2_READY; -- AC2M5 AC2L5 213 | sTT3_POS_1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- AC2J5 214 | sTT4_POS_HOME_STT <= PCH_CONN_ENTRY.HOME_RDR_STT_LCH; -- AC2M5 AC2L5 215 | -- TT4_POS_HOME_STT <= sTT4_POS_HOME_STT; 216 | sOUTPUT_SEL_AND_RDY <= PCH_CONN_ENTRY.HOME_OUTPUT_DEV_RDY; 217 | OUTPUT_SEL_AND_RDY <= sOUTPUT_SEL_AND_RDY; 218 | sRDR_1_CLUTCH <= PCH_CONN_ENTRY.RDR_1_CLUTCH_1050; -- AC2M4 219 | RDR_1_CLUTCH <= sRDR_1_CLUTCH; 220 | n1050_OPER <= PCH_CONN_ENTRY.CPU_CONNECTED; -- FA1D4 221 | REQUEST_KEY <=PCH_CONN_ENTRY.REQ_KEY; -- FA1D4 222 | 223 | console : entity ibm1050 port map( 224 | SerialIn => PCH_CONN_ENTRY, 225 | SerialOut => RDR_1_CONN_EXIT, 226 | SerialControl => CPU_LINES_EXIT, 227 | serialInput => serialInput, 228 | serialOutput => serialOutput, 229 | clk => clk); 230 | 231 | END FMD; 232 | 233 | -------------------------------------------------------------------------------- /PH.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:34:05 06/17/2015 6 | -- Design Name: 7 | -- Module Name: PH - slt 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | -- Simple PH (polarity hold) latch 24 | 25 | entity PH is port( D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end; 26 | 27 | architecture slt of PH is 28 | begin 29 | process(L,D) 30 | begin 31 | if (L='1') then 32 | Q <= D; 33 | end if; 34 | end process; 35 | end slt; 36 | 37 | -------------------------------------------------------------------------------- /PROM_reader_serial.vhd: -------------------------------------------------------------------------------- 1 | --***************************************************************************************** 2 | --** 3 | --** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 4 | --** provided to you "as is". Xilinx and its licensors make and you 5 | --** receive no warranties or conditions, express, implied, statutory 6 | --** or otherwise, and Xilinx specifically disclaims any implied 7 | --** warranties of merchantability, non-infringement, or fitness for a 8 | --** particular purpose. Xilinx does not warrant that the functions 9 | --** contained in these designs will meet your requirements, or that the 10 | --** operation of these designs will be uninterrupted or error free, or 11 | --** that defects in the Designs will be corrected. Furthermore, Xilinx 12 | --** does not warrant or make any representations regarding use or the 13 | --** results of the use of the designs in terms of correctness, accuracy, 14 | --** reliability, or otherwise. 15 | --** 16 | --** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 17 | --** liable for any loss of data, lost profits, cost or procurement of 18 | --** substitute goods or services, or for any special, incidental, 19 | --** consequential, or indirect damages arising from the use or operation 20 | --** of the designs or accompanying documentation, however caused and on 21 | --** any theory of liability. This limitation will apply even if Xilinx 22 | --** has been advised of the possibility of such damage. This limitation 23 | --** shall apply not-withstanding the failure of the essential purpose of 24 | --** any limited remedies herein. 25 | --** 26 | --***************************************************************************************** 27 | -- MODULE : PROM_reader_serial.vhd 28 | -- AUTHOR : Stephan Neuhold 29 | -- VERSION : v1.00 30 | -- 31 | -- 32 | -- REVISION HISTORY: 33 | -- ----------------- 34 | -- No revisions 35 | -- 36 | -- 37 | -- FUNCTION DESCRIPTION: 38 | -- --------------------- 39 | -- This module provides the control state machine 40 | -- for reading data from the PROM. This includes 41 | -- searching for synchronisation patterns, retrieving 42 | -- data, resetting the PROMs address counter. 43 | 44 | 45 | --*************************** 46 | --* Library declarations 47 | --*************************** 48 | library IEEE; 49 | use IEEE.STD_LOGIC_1164.ALL; 50 | use IEEE.STD_LOGIC_ARITH.ALL; 51 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 52 | 53 | library UNISIM; 54 | use UNISIM.VComponents.all; 55 | 56 | 57 | --*********************** 58 | --* Entity declaration 59 | --*********************** 60 | entity PROM_reader_serial is 61 | generic( 62 | length : integer := 5; 63 | frequency : integer := 50 64 | ); 65 | 66 | port( 67 | clock : in std_logic; 68 | reset : in std_logic; --active high 69 | read : in std_logic; --active low 70 | next_sync : in std_logic; --active low 71 | din : in std_logic; 72 | sync_pattern : in std_logic_vector((2**length) - 1 downto 0); 73 | cclk : out std_logic; 74 | sync : out std_logic; --active low 75 | data_ready : out std_logic; --active low 76 | reset_prom : out std_logic; --active high 77 | dout : out std_logic_vector(7 downto 0) 78 | ); 79 | end PROM_reader_serial; 80 | 81 | 82 | architecture Behavioral of PROM_reader_serial is 83 | 84 | 85 | component clock_management 86 | generic( 87 | length : integer := 5; 88 | frequency : integer := 50 89 | ); 90 | port( 91 | clock : in std_logic; 92 | enable : in std_logic; 93 | read_enable : out std_logic; 94 | cclk : out std_logic 95 | ); 96 | end component; 97 | 98 | 99 | component shift_compare_serial 100 | generic( 101 | length : integer := 5 102 | ); 103 | port( 104 | clock : in std_logic; 105 | reset : in std_logic; 106 | enable : in std_logic; 107 | din : in std_logic; 108 | b : in std_logic_vector((2**length) - 1 downto 0); 109 | eq : out std_logic; 110 | din_shifted : out std_logic_vector(7 downto 0) 111 | ); 112 | end component; 113 | 114 | 115 | type state_type is (Look4Sync, Wait4Active, GetData, PresentData); 116 | signal current_state : state_type; 117 | signal count : std_logic_vector(length downto 0); 118 | signal din_read_enable : std_logic; 119 | signal sync_found : std_logic; 120 | signal data : std_logic_vector(7 downto 0); 121 | signal sync_int : std_logic; 122 | signal cclk_on : std_logic; 123 | signal reset_n : std_logic; 124 | 125 | 126 | begin 127 | 128 | 129 | --Clock generation and clock enable generation 130 | Clock_Manager: clock_management 131 | generic map( 132 | length => length, 133 | frequency => frequency 134 | ) 135 | port map( 136 | clock => clock, 137 | enable => cclk_on, 138 | read_enable => din_read_enable, 139 | cclk => cclk 140 | ); 141 | 142 | 143 | --Shift and compare operation 144 | Shift_And_Compare: shift_compare_serial 145 | generic map( 146 | length => length 147 | ) 148 | port map( 149 | clock => clock, 150 | reset => reset, 151 | enable => din_read_enable, 152 | din => din, 153 | b => sync_pattern, 154 | eq => sync_found, 155 | din_shifted => data 156 | ); 157 | 158 | 159 | --State machine 160 | process (clock, reset, current_state, sync_int, read, count, 161 | data, sync_found) 162 | begin 163 | if (reset = '1') then 164 | current_state <= Look4Sync; --this can be changed to Wait4Active so that the FPGA doesnt go looking for data immediately after config 165 | dout <= (others => '0'); 166 | count <= (others => '0'); 167 | sync_int <= '0'; 168 | data_ready <= '1'; 169 | reset_PROM <= '0'; 170 | cclk_on <= '1'; 171 | 172 | elsif rising_edge(clock) then 173 | case current_state is 174 | 175 | --************************************************************* 176 | --* This state clocks in one bit of data at a time from the 177 | --* PROM. With every new bit clocked in a comparison is done 178 | --* to check whether it matches the synchronisation pattern. 179 | --* If the pattern is found then a further bits are read 180 | --* from the PROM to provide the first byte of data appearing 181 | --* after the synchronisation pattern. 182 | --************************************************************* 183 | when Look4Sync => 184 | count <= (others => '0'); 185 | data_ready <= '1'; 186 | sync_int <= '0'; 187 | reset_PROM <= '1'; 188 | if (sync_found = '1') then 189 | current_state <= Wait4Active; 190 | sync_int <= '1'; 191 | cclk_on <= '0'; 192 | end if; 193 | 194 | --********************************************************* 195 | --* At this point the state machine waits for user input. 196 | --* If the user pulses the "read" signal then 8 bits of 197 | --* are retrieved from the PROM. If the user wants to 198 | --* look for another synchronisation pattern and pulses 199 | --* the "next_sync" signal, then the state machine goes 200 | --* into the "Look4Sync" state. 201 | --********************************************************* 202 | when Wait4Active => 203 | count <= (others => '0'); 204 | data_ready <= '1'; 205 | if (read = '0' or sync_int = '1') then 206 | current_state <= GetData; 207 | cclk_on <= '1'; 208 | end if; 209 | if (next_sync = '0') then 210 | current_state <= Look4Sync; 211 | cclk_on <= '1'; 212 | end if; 213 | 214 | --********************************************************* 215 | --* This state gets the data from the PROM. If the 216 | --* synchronisation pattern has just been found then 217 | --* enough data is retrieved to present the first 218 | --* 8 bits after the pattern. This is dependant on the 219 | --* synchronisation pattern length. 220 | --* If the synchronisation pattern has already been found 221 | --* previously then only the next 8 bits of data are 222 | --* retrieved. 223 | --********************************************************* 224 | when GetData => 225 | if (din_read_enable = '1') then 226 | count <= count + 1; 227 | if (sync_int = '1') then 228 | if (count = (2**length) - 1) then 229 | current_state <= PresentData; 230 | sync_int <= '0'; 231 | cclk_on <= '0'; 232 | end if; 233 | else 234 | if (count = 7) then 235 | current_state <= PresentData; 236 | sync_int <= '0'; 237 | cclk_on <= '0'; 238 | end if; 239 | end if; 240 | end if; 241 | 242 | --******************************************************* 243 | --* This state tells the user that 8 bits of data have 244 | --* been retrieved and is presented on the "dout" port. 245 | --* The "Wait4Active" state is then entered to wait for 246 | --* another user request. 247 | --******************************************************* 248 | when PresentData => 249 | dout <= data; 250 | data_ready <= '0'; 251 | current_state <= Wait4Active; 252 | 253 | when others => 254 | null; 255 | 256 | end case; 257 | end if; 258 | sync <= not sync_found; 259 | end process; 260 | 261 | 262 | end Behavioral; 263 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | LJW2030 2 | An IBM System/360 Model 30 in VHDL 3 | 4 | There are two main components to this release: 5 | VHDL for the CPU (with 8k storage) and Multiplexer channel 6 | The microcode image (4k x 55) 7 | 8 | I am not claiming copyright to the microcode image - this is based on IBM manuals from 1964-1965 which may or may not be copyrighted themselves. 9 | 10 | The VHDL is based on the IBM Maintenance Diagram Manual (MDM), which can be found on Bitsavers. 11 | 12 | As supplied, the compiled system is suitable for a Digilent Spartan 3 board with a 1000K device, see http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD 13 | It uses the following I/O: 14 | VGA output (8-colour, 3-bit) 15 | Parallel I/O for switch scanning (10 out, 14 in) 16 | On-board pushbutton inputs (4) 17 | On-board slide switch inputs (8) 18 | On-board LED outputs (8) 19 | If using an alternative board, it may be sufficient to modify the UCF file to reallocate inputs and outputs 20 | 21 | These files can be compiled using the Xilinx ISE Webpack (and presumably other versions of the Xilinx suite). I have not tried compiling them with other VHDL compilers. 22 | 23 | Apologies for the varied quality of the VHDL. This project has taken over 5 years and I have not necessarily re-visited code that was written early on. So there is a variety of styles and conventions. In my defence, it works (or seems to). 24 | 25 | Lawrence Wilkinson 26 | lawrence@ljw.me.uk 27 | 2010/07/16 28 | 29 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | IBM2030 2 | ======= 3 | 4 | An IBM System/360 Model 30 in VHDL 5 | 6 | There are two main components to this release: 7 | * VHDL for the CPU (with 8k storage) and Multiplexer channel 8 | * The microcode image (4k x 55) 9 | 10 | I am not claiming copyright to the microcode image - this is based on IBM manuals from 1964-1965 which may or may not be copyrighted themselves. 11 | 12 | The VHDL is based on the IBM Maintenance Diagram Manual (MDM), which can be found on Bitsavers. 13 | 14 | As supplied, the compiled system is suitable for a Digilent Spartan 3 board with a 1000K device, see http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD 15 | It uses the following I/O: 16 | * VGA output (8-colour, 3-bit) 17 | * Parallel I/O for switch scanning (10 out, 14 in) 18 | * On-board pushbutton inputs (4) 19 | * On-board slide switch inputs (8) 20 | * On-board LED outputs (8) 21 | If using an alternative board, it may be sufficient to modify the UCF file to reallocate inputs and outputs 22 | 23 | These files can be compiled using the Xilinx ISE Webpack (and presumably other versions of the Xilinx suite). I have not tried compiling them with other VHDL compilers. 24 | 25 | Apologies for the varied quality of the VHDL. This project has taken over 5 years and I have not necessarily re-visited code that was written early on. So there is a variety of styles and conventions. In my defence, it works (or seems to). 26 | 27 | Lawrence Wilkinson 28 | lawrence@ljw.me.uk 29 | 2010/07/16 30 | 31 | -------------------------------------------------------------------------------- /README.md~: -------------------------------------------------------------------------------- 1 | IBM2030 2 | ======= 3 | 4 | An IBM System/360 Model 30 in VHDL 5 | 6 | There are two main components to this release: 7 | VHDL for the CPU (with 8k storage) and Multiplexer channel 8 | The microcode image (4k x 55) 9 | 10 | I am not claiming copyright to the microcode image - this is based on IBM manuals from 1964-1965 which may or may not be copyrighted themselves. 11 | 12 | The VHDL is based on the IBM Maintenance Diagram Manual (MDM), which can be found on Bitsavers. 13 | 14 | As supplied, the compiled system is suitable for a Digilent Spartan 3 board with a 1000K device, see http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD 15 | It uses the following I/O: 16 | VGA output (8-colour, 3-bit) 17 | Parallel I/O for switch scanning (10 out, 14 in) 18 | On-board pushbutton inputs (4) 19 | On-board slide switch inputs (8) 20 | On-board LED outputs (8) 21 | If using an alternative board, it may be sufficient to modify the UCF file to reallocate inputs and outputs 22 | 23 | These files can be compiled using the Xilinx ISE Webpack (and presumably other versions of the Xilinx suite). I have not tried compiling them with other VHDL compilers. 24 | 25 | Apologies for the varied quality of the VHDL. This project has taken over 5 years and I have not necessarily re-visited code that was written early on. So there is a variety of styles and conventions. In my defence, it works (or seems to). 26 | 27 | Lawrence Wilkinson 28 | lawrence@ljw.me.uk 29 | 2010/07/16 30 | 31 | -------------------------------------------------------------------------------- /RS232RefComp.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------ 2 | -- RS232RefCom.vhd 3 | ------------------------------------------------------------------------ 4 | -- Author: Dan Pederson 5 | -- Copyright 2004 Digilent, Inc. 6 | ------------------------------------------------------------------------ 7 | -- Description: This file defines a UART which tranfers data from 8 | -- serial form to parallel form and vice versa. 9 | ------------------------------------------------------------------------ 10 | -- Revision History: 11 | -- 07/15/04 (Created) DanP 12 | -- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant 13 | -- in the Clock Dividing Processes 14 | ------------------------------------------------------------------------ 15 | 16 | library IEEE; 17 | use IEEE.STD_LOGIC_1164.ALL; 18 | use IEEE.STD_LOGIC_ARITH.ALL; 19 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 20 | 21 | -- Uncomment the following lines to use the declarations that are 22 | -- provided for instantiating Xilinx primitive components. 23 | --library UNISIM; 24 | --use UNISIM.VComponents.all; 25 | 26 | entity Rs232RefComp is 27 | Port ( 28 | TXD : out std_logic := '1'; 29 | RXD : in std_logic; 30 | CLK : in std_logic; --Master Clock 31 | DBIN : in std_logic_vector (7 downto 0); --Data Bus in 32 | DBOUT : out std_logic_vector (7 downto 0); --Data Bus out 33 | RDA : inout std_logic; --Read Data Available 34 | TBE : inout std_logic := '1'; --Transfer Bus Empty 35 | RD : in std_logic; --Read Strobe 36 | WR : in std_logic; --Write Strobe 37 | PE : out std_logic; --Parity Error Flag 38 | FE : out std_logic; --Frame Error Flag 39 | OE : out std_logic; --Overwrite Error Flag 40 | RST : in std_logic := '0'); --Master Reset 41 | end Rs232RefComp; 42 | 43 | architecture Behavioral of Rs232RefComp is 44 | ------------------------------------------------------------------------ 45 | -- Component Declarations 46 | ------------------------------------------------------------------------ 47 | 48 | ------------------------------------------------------------------------ 49 | -- Local Type Declarations 50 | ------------------------------------------------------------------------ 51 | --Receive state machine 52 | type rstate is ( 53 | strIdle, --Idle state 54 | strEightDelay, --Delays for 8 clock cycles 55 | strGetData, --Shifts in the 8 data bits, and checks parity 56 | strCheckStop --Sets framing error flag if Stop bit is wrong 57 | ); 58 | 59 | type tstate is ( 60 | sttIdle, --Idle state 61 | sttTransfer, --Move data into shift register 62 | sttShift --Shift out data 63 | ); 64 | 65 | type TBEstate is ( 66 | stbeIdle, 67 | stbeSetTBE, 68 | stbeWaitLoad, 69 | stbeWaitWrite 70 | ); 71 | 72 | 73 | ------------------------------------------------------------------------ 74 | -- Signal Declarations 75 | ------------------------------------------------------------------------ 76 | constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600. 77 | --Found by dividing 50MHz by 9600 and 16. 78 | signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register 79 | signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register 80 | signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register 81 | signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register 82 | signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk 83 | signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk 84 | signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times 85 | signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer 86 | signal rClk : std_logic := '0'; --Receiving Clock 87 | signal tClk : std_logic; --Transfering Clock 88 | signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits 89 | signal parError: std_logic; --Parity error bit 90 | signal frameError: std_logic; --Frame error bit 91 | signal CE : std_logic; --Clock enable for the latch 92 | signal ctRst : std_logic := '0'; 93 | signal load : std_logic := '0'; 94 | signal shift : std_logic := '0'; 95 | signal par : std_logic; 96 | signal tClkRST : std_logic := '0'; 97 | signal rShift : std_logic := '0'; 98 | signal dataRST : std_logic := '0'; 99 | signal dataIncr: std_logic := '0'; 100 | 101 | signal strCur : rstate := strIdle; --Current state in the Receive state machine 102 | signal strNext : rstate; --Next state in the Receive state machine 103 | signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine 104 | signal sttNext : tstate; --Next state in the Transfer staet machine 105 | signal stbeCur : TBEstate := stbeIdle; 106 | signal stbeNext: TBEstate; 107 | 108 | ------------------------------------------------------------------------ 109 | -- Module Implementation 110 | ------------------------------------------------------------------------ 111 | 112 | begin 113 | frameError <= not rdSReg(9); 114 | parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) ); 115 | DBOUT <= rdReg; 116 | tfReg <= DBIN; 117 | par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) ); 118 | 119 | --Clock Dividing Functions-- 120 | 121 | process (CLK, clkDiv) --set up clock divide for rClk 122 | begin 123 | if (Clk = '1' and Clk'event) then 124 | if (clkDiv = baudDivide) then 125 | clkDiv <= "000000000"; 126 | else 127 | clkDiv <= clkDiv +1; 128 | end if; 129 | end if; 130 | end process; 131 | 132 | process (clkDiv, rClk, CLK) --Define rClk 133 | begin 134 | if CLK = '1' and CLK'Event then 135 | if clkDiv = baudDivide then 136 | rClk <= not rClk; 137 | else 138 | rClk <= rClk; 139 | end if; 140 | end if; 141 | end process; 142 | 143 | process (rClk) --set up clock divide for tClk 144 | begin 145 | if (rClk = '1' and rClk'event) then 146 | rClkDiv <= rClkDiv +1; 147 | end if; 148 | end process; 149 | 150 | tClk <= rClkDiv(3); --define tClk 151 | 152 | process (rClk, ctRst) --set up a counter based on rClk 153 | begin 154 | if rClk = '1' and rClk'Event then 155 | if ctRst = '1' then 156 | ctr <= "0000"; 157 | else 158 | ctr <= ctr +1; 159 | end if; 160 | end if; 161 | end process; 162 | 163 | process (tClk, tClkRST) --set up a counter based on tClk 164 | begin 165 | if (tClk = '1' and tClk'event) then 166 | if tClkRST = '1' then 167 | tfCtr <= "0000"; 168 | else 169 | tfCtr <= tfCtr +1; 170 | end if; 171 | end if; 172 | end process; 173 | 174 | --This process controls the error flags-- 175 | process (rClk, RST, RD, CE) 176 | begin 177 | if RD = '1' or RST = '1' then 178 | FE <= '0'; 179 | OE <= '0'; 180 | RDA <= '0'; 181 | PE <= '0'; 182 | elsif rClk = '1' and rClk'event then 183 | if CE = '1' then 184 | FE <= frameError; 185 | OE <= RDA; 186 | RDA <= '1'; 187 | PE <= parError; 188 | rdReg(7 downto 0) <= rdSReg (7 downto 0); 189 | end if; 190 | end if; 191 | end process; 192 | 193 | --This process controls the receiving shift register-- 194 | process (rClk, rShift) 195 | begin 196 | if rClk = '1' and rClk'Event then 197 | if rShift = '1' then 198 | rdSReg <= (RXD & rdSReg(9 downto 1)); 199 | end if; 200 | end if; 201 | end process; 202 | 203 | --This process controls the dataCtr to keep track of shifted values-- 204 | process (rClk, dataRST) 205 | begin 206 | if (rClk = '1' and rClk'event) then 207 | if dataRST = '1' then 208 | dataCtr <= "0000"; 209 | elsif dataIncr = '1' then 210 | dataCtr <= dataCtr +1; 211 | end if; 212 | end if; 213 | end process; 214 | 215 | --Receiving State Machine-- 216 | process (rClk, RST) 217 | begin 218 | if rClk = '1' and rClk'Event then 219 | if RST = '1' then 220 | strCur <= strIdle; 221 | else 222 | strCur <= strNext; 223 | end if; 224 | end if; 225 | end process; 226 | 227 | --This process generates the sequence of steps needed receive the data 228 | 229 | process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA) 230 | begin 231 | case strCur is 232 | 233 | when strIdle => 234 | dataIncr <= '0'; 235 | rShift <= '0'; 236 | dataRst <= '0'; 237 | 238 | CE <= '0'; 239 | if RXD = '0' then 240 | ctRst <= '1'; 241 | strNext <= strEightDelay; 242 | else 243 | ctRst <= '0'; 244 | strNext <= strIdle; 245 | end if; 246 | 247 | when strEightDelay => 248 | dataIncr <= '0'; 249 | rShift <= '0'; 250 | CE <= '0'; 251 | 252 | if ctr(2 downto 0) = "111" then 253 | ctRst <= '1'; 254 | dataRST <= '1'; 255 | strNext <= strGetData; 256 | else 257 | ctRst <= '0'; 258 | dataRST <= '0'; 259 | strNext <= strEightDelay; 260 | end if; 261 | 262 | when strGetData => 263 | CE <= '0'; 264 | dataRst <= '0'; 265 | if ctr(3 downto 0) = "1111" then 266 | ctRst <= '1'; 267 | dataIncr <= '1'; 268 | rShift <= '1'; 269 | else 270 | ctRst <= '0'; 271 | dataIncr <= '0'; 272 | rShift <= '0'; 273 | end if; 274 | 275 | if dataCtr = "1010" then 276 | strNext <= strCheckStop; 277 | else 278 | strNext <= strGetData; 279 | end if; 280 | 281 | when strCheckStop => 282 | dataIncr <= '0'; 283 | rShift <= '0'; 284 | dataRst <= '0'; 285 | ctRst <= '0'; 286 | 287 | CE <= '1'; 288 | strNext <= strIdle; 289 | 290 | end case; 291 | 292 | end process; 293 | 294 | --TBE State Machine-- 295 | process (CLK, RST) 296 | begin 297 | if CLK = '1' and CLK'Event then 298 | if RST = '1' then 299 | stbeCur <= stbeIdle; 300 | else 301 | stbeCur <= stbeNext; 302 | end if; 303 | end if; 304 | end process; 305 | 306 | --This process gererates the sequence of events needed to control the TBE flag-- 307 | process (stbeCur, CLK, WR, DBIN, load) 308 | begin 309 | 310 | case stbeCur is 311 | 312 | when stbeIdle => 313 | TBE <= '1'; 314 | if WR = '1' then 315 | stbeNext <= stbeSetTBE; 316 | else 317 | stbeNext <= stbeIdle; 318 | end if; 319 | 320 | when stbeSetTBE => 321 | TBE <= '0'; 322 | if load = '1' then 323 | stbeNext <= stbeWaitLoad; 324 | else 325 | stbeNext <= stbeSetTBE; 326 | end if; 327 | 328 | when stbeWaitLoad => 329 | if load = '0' then 330 | stbeNext <= stbeWaitWrite; 331 | else 332 | stbeNext <= stbeWaitLoad; 333 | end if; 334 | 335 | when stbeWaitWrite => 336 | if WR = '0' then 337 | stbeNext <= stbeIdle; 338 | else 339 | stbeNext <= stbeWaitWrite; 340 | end if; 341 | end case; 342 | end process; 343 | 344 | --This process loads and shifts out the transfer shift register-- 345 | process (load, shift, tClk, tfSReg) 346 | begin 347 | TXD <= tfsReg(0); 348 | if tClk = '1' and tClk'Event then 349 | if load = '1' then 350 | tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0'); 351 | end if; 352 | if shift = '1' then 353 | 354 | tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1)); 355 | end if; 356 | end if; 357 | end process; 358 | 359 | -- Transfer State Machine-- 360 | process (tClk, RST) 361 | begin 362 | if (tClk = '1' and tClk'Event) then 363 | if RST = '1' then 364 | sttCur <= sttIdle; 365 | else 366 | sttCur <= sttNext; 367 | end if; 368 | end if; 369 | end process; 370 | 371 | -- This process generates the sequence of steps needed transfer the data-- 372 | process (sttCur, tfCtr, tfReg, TBE, tclk) 373 | begin 374 | 375 | case sttCur is 376 | 377 | when sttIdle => 378 | tClkRST <= '0'; 379 | shift <= '0'; 380 | load <= '0'; 381 | if TBE = '1' then 382 | sttNext <= sttIdle; 383 | else 384 | sttNext <= sttTransfer; 385 | end if; 386 | 387 | when sttTransfer => 388 | shift <= '0'; 389 | load <= '1'; 390 | tClkRST <= '1'; 391 | sttNext <= sttShift; 392 | 393 | 394 | when sttShift => 395 | shift <= '1'; 396 | load <= '0'; 397 | tClkRST <= '0'; 398 | if tfCtr = "1100" then 399 | sttNext <= sttIdle; 400 | else 401 | sttNext <= sttShift; 402 | end if; 403 | end case; 404 | end process; 405 | 406 | end Behavioral; -------------------------------------------------------------------------------- /Testbench_panel_LEDs.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 13:16:46 06/18/2015 6 | -- Design Name: 7 | -- Module Name: C:/Users/lwilkinson/Documents/Xilinx/IBM2030/Testbench_panel_LEDs.vhd 8 | -- Project Name: IBM2030 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: panel_LEDs 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY Testbench_panel_LEDs IS 36 | END Testbench_panel_LEDs; 37 | 38 | ARCHITECTURE behavior OF Testbench_panel_LEDs IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT panel_LEDs 43 | PORT( 44 | LEDs : IN std_logic_vector(0 to 255); 45 | clk : IN std_logic; 46 | MAX7219_CLK : OUT std_logic; 47 | MAX7219_DIN0 : OUT std_logic; 48 | MAX7219_DIN1 : OUT std_logic; 49 | MAX7219_DIN2 : OUT std_logic; 50 | MAX7219_DIN3 : OUT std_logic; 51 | MAX7219_LOAD : OUT std_logic; 52 | MAX6951_CLK : OUT std_logic; 53 | MAX6951_DIN : OUT std_logic; 54 | MAX6951_CS0 : OUT std_logic; 55 | MAX6951_CS1 : OUT std_logic; 56 | MAX6951_CS2 : OUT std_logic; 57 | MAX6951_CS3 : OUT std_logic 58 | ); 59 | END COMPONENT; 60 | 61 | 62 | --Inputs 63 | signal LEDs : std_logic_vector(0 to 255) := (1 => '1',3 => '1',5 => '1',7 => '1',9 => '1',11 => '1',13 => '1',15 => '1',17 => '1',others => '0'); 64 | signal clk : std_logic := '0'; 65 | 66 | --Outputs 67 | signal MAX7219_CLK : std_logic; 68 | signal MAX7219_DIN0 : std_logic; 69 | signal MAX7219_DIN1 : std_logic; 70 | signal MAX7219_DIN2 : std_logic; 71 | signal MAX7219_DIN3 : std_logic; 72 | signal MAX7219_LOAD : std_logic; 73 | signal MAX6951_CLK : std_logic; 74 | signal MAX6951_DIN : std_logic; 75 | signal MAX6951_CS0 : std_logic; 76 | signal MAX6951_CS1 : std_logic; 77 | signal MAX6951_CS2 : std_logic; 78 | signal MAX6951_CS3 : std_logic; 79 | 80 | -- Clock period definitions 81 | constant clk_period : time := 20 ns; 82 | 83 | BEGIN 84 | 85 | -- Instantiate the Unit Under Test (UUT) 86 | uut: panel_LEDs PORT MAP ( 87 | LEDs => LEDs, 88 | clk => clk, 89 | MAX7219_CLK => MAX7219_CLK, 90 | MAX7219_DIN0 => MAX7219_DIN0, 91 | MAX7219_DIN1 => MAX7219_DIN1, 92 | MAX7219_DIN2 => MAX7219_DIN2, 93 | MAX7219_DIN3 => MAX7219_DIN3, 94 | MAX7219_LOAD => MAX7219_LOAD, 95 | MAX6951_CLK => MAX6951_CLK, 96 | MAX6951_DIN => MAX6951_DIN, 97 | MAX6951_CS0 => MAX6951_CS0, 98 | MAX6951_CS1 => MAX6951_CS1, 99 | MAX6951_CS2 => MAX6951_CS2, 100 | MAX6951_CS3 => MAX6951_CS3 101 | ); 102 | 103 | -- Clock process definitions 104 | clk_process :process 105 | begin 106 | clk <= '0'; 107 | wait for clk_period/2; 108 | clk <= '1'; 109 | wait for clk_period/2; 110 | end process; 111 | 112 | -- Stimulus process 113 | stim_proc: process 114 | begin 115 | -- hold reset state for 100 ns. 116 | wait for 100 ns; 117 | 118 | wait for 1ms; 119 | 120 | -- insert stimulus here 121 | 122 | wait; 123 | end process; 124 | 125 | END; 126 | -------------------------------------------------------------------------------- /Testbench_panel_Switches.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 08:36:53 11/26/2015 6 | -- Design Name: 7 | -- Module Name: C:/Users/lwilkinson/Documents/Xilinx/IBM2030GIT/Testbench_panel_Switches.vhd 8 | -- Project Name: IBM2030 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: panel_Switches 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY Testbench_panel_Switches IS 36 | END Testbench_panel_Switches; 37 | 38 | ARCHITECTURE behavior OF Testbench_panel_Switches IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT panel_Switches 43 | PORT( 44 | LEDs : IN std_logic_vector(0 to 4); 45 | clk : IN std_logic; 46 | Switches : OUT std_logic_vector(0 to 63); 47 | SCL : OUT std_logic; 48 | SDA : INOUT std_logic 49 | ); 50 | END COMPONENT; 51 | 52 | 53 | --Inputs 54 | signal LEDs : std_logic_vector(0 to 4) := (others => '0'); 55 | signal clk : std_logic := '0'; 56 | 57 | --BiDirs 58 | signal MAX7318_SDA : std_logic; 59 | 60 | --Outputs 61 | signal Switches : std_logic_vector(0 to 63); 62 | signal MAX7318_SCL : std_logic; 63 | 64 | -- Clock period definitions 65 | constant clk_period : time := 20 ns; 66 | 67 | BEGIN 68 | 69 | -- Instantiate the Unit Under Test (UUT) 70 | uut: panel_Switches PORT MAP ( 71 | LEDs => LEDs, 72 | clk => clk, 73 | Switches => Switches, 74 | SCL => MAX7318_SCL, 75 | SDA => MAX7318_SDA 76 | ); 77 | 78 | -- Clock process definitions 79 | clk_process :process 80 | begin 81 | clk <= '0'; 82 | wait for clk_period/2; 83 | clk <= '1'; 84 | wait for clk_period/2; 85 | end process; 86 | 87 | 88 | -- Stimulus process 89 | stim_proc: process 90 | begin 91 | -- hold reset state for 100 ns. 92 | wait for 100 ns; 93 | 94 | wait for clk_period*10; 95 | 96 | -- insert stimulus here 97 | wait for 10ms; 98 | 99 | wait; 100 | end process; 101 | 102 | END; 103 | -------------------------------------------------------------------------------- /ccros.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #define ccrosLineSize 100 5 | #define versions " |004|005|006|007|010|014|025|A20" 6 | /* 7 | #AAA CN CH CL CM CU CA CB CK CD CF CG CV CC CS AAASAKPK 8 | 102 F3 0001 0001 110 01 ???? ?? 0010 0110 000 00 00 000 0000 ? 0 0 1 # QA001:C2 9 | */ 10 | struct ccrosLayout { 11 | char space1; 12 | char ADDR[3]; 13 | char space2[2]; 14 | char CN[2]; 15 | char space3; 16 | char CH[4]; 17 | char space4; 18 | char CL[4]; 19 | char space5; 20 | char CM[3]; 21 | char space6; 22 | char CU[2]; 23 | char space7; 24 | char CA[4]; 25 | char space8; 26 | char CB[2]; 27 | char space9; 28 | char CK[4]; 29 | char space10; 30 | char CD[4]; 31 | char space11; 32 | char CF[3]; 33 | char space12; 34 | char CG[2]; 35 | char space13; 36 | char CV[2]; 37 | char space14; 38 | char CC[3]; 39 | char space15; 40 | char CS[4]; 41 | char space16; 42 | char AA; 43 | char space17; 44 | char AS; 45 | char space18; 46 | char AK; 47 | char space19; 48 | char PK; 49 | char space20; 50 | char comment[11]; /* # QANNN:RN- */ 51 | char version[3]; 52 | } ccrosLine; 53 | 54 | typedef struct { 55 | int address; 56 | char ccros[56]; /* Final char is NUL */ 57 | } ccrosEntry; 58 | 59 | ccrosEntry ccros[4096]; 60 | int ccrosEntryCount; 61 | char *flag; 62 | char *ptr; 63 | int i; 64 | char thisVersion[4]; 65 | 66 | int htoi(char *hex, int length) { 67 | int value = 0; 68 | char ch; 69 | 70 | for (;length>0;length--) { 71 | ch = *(hex++); 72 | if (ch >= '0' && ch <= '9') 73 | value = (value << 4) + (ch - '0'); 74 | else if (ch >= 'A' && ch <= 'F') 75 | value = (value << 4) + (ch - 'A' + 10); 76 | else if (ch >= 'a' && ch <= 'f') 77 | value = (value << 4) + (ch - 'a' + 10); 78 | else 79 | return value; 80 | } 81 | } 82 | 83 | char * itob(int value, char *buffer, int length) { 84 | char *ptr; 85 | ptr = buffer + length; 86 | for (;length>0;length--) { 87 | *--ptr = '0' + (value & 1); 88 | value = value >> 1; 89 | } 90 | return buffer; 91 | } 92 | 93 | char parity(char *buffer, int length, char start) { 94 | char result = start; 95 | for (;length>0;length--) { 96 | result^=(*buffer++ & 1); 97 | } 98 | return result; 99 | } 100 | 101 | main (int argc, char *argv[]) { 102 | if ((argc==2) && (strcmp(argv[1],"-v")==0)) { 103 | printf("CCROS file converter 2012-04-07\n"); 104 | exit(0); 105 | } 106 | ccrosEntryCount = 0; 107 | while (1) { 108 | ccrosLine.version[0]=' '; 109 | ccrosLine.version[1]=' '; 110 | ccrosLine.version[2]=' '; 111 | flag = gets((char*)&ccrosLine); 112 | if (flag != NULL) { 113 | thisVersion[0]=ccrosLine.version[0]; 114 | thisVersion[1]=ccrosLine.version[1]; 115 | thisVersion[2]=ccrosLine.version[2]; 116 | thisVersion[3]='\0'; 117 | if (ccrosLine.space1=='#') { 118 | /* Ignore comment line */ 119 | } 120 | else if ( (ccrosLine.space1 !=' ') | (ccrosLine.space2[0] !=' ') | (ccrosLine.space2[1] !=' ') | (ccrosLine.space3 !=' ') | (ccrosLine.space4 !=' ') | (ccrosLine.space5 !=' ') 121 | | (ccrosLine.space6 !=' ') | (ccrosLine.space7 !=' ') | (ccrosLine.space8 !=' ') | (ccrosLine.space9 !=' ') | (ccrosLine.space10!=' ') 122 | | (ccrosLine.space11!=' ') | (ccrosLine.space12!=' ') | (ccrosLine.space13!=' ') | (ccrosLine.space14!=' ') | (ccrosLine.space15!=' ') 123 | | (ccrosLine.space16!=' ') | (ccrosLine.space17!=' ') | (ccrosLine.space18!=' ') | (ccrosLine.space19!=' ') | (ccrosLine.space20!=' ')) { 124 | /* Skip invalid line */ 125 | printf("Line format error\r\n"); 126 | puts((char*)&ccrosLine); 127 | printf("\r\n"); 128 | exit(1); 129 | } 130 | else if (strstr(versions,(char*)&thisVersion[0])==NULL) { 131 | /* Skip it */ 132 | } 133 | else { 134 | char cnBinary[9]; 135 | cnBinary[8]='\0'; 136 | char addrBinary[13]; 137 | addrBinary[12]='\0'; 138 | /* Handle CCROS line - convert to a 56-bit binary string in the same order */ 139 | ccros[ccrosEntryCount].address = htoi(ccrosLine.ADDR,3); 140 | itob(ccros[ccrosEntryCount].address,addrBinary,12); 141 | 142 | ccros[ccrosEntryCount].ccros[55] = '\0'; 143 | /* Generate binary from top 6 bits of CN */ 144 | itob(htoi(ccrosLine.CN,2),cnBinary,8); 145 | 146 | /* 0 (PN) is calculated later */ 147 | ccros[ccrosEntryCount].ccros[0] = '0'; 148 | 149 | ccros[ccrosEntryCount].ccros[1] = cnBinary[0]; 150 | ccros[ccrosEntryCount].ccros[2] = cnBinary[1]; 151 | ccros[ccrosEntryCount].ccros[3] = cnBinary[2]; 152 | ccros[ccrosEntryCount].ccros[4] = cnBinary[3]; 153 | ccros[ccrosEntryCount].ccros[5] = cnBinary[4]; 154 | ccros[ccrosEntryCount].ccros[6] = cnBinary[5]; 155 | 156 | /* 7 (PS) and 8 (PA) are calculated later */ 157 | ccros[ccrosEntryCount].ccros[7] = '0'; 158 | ccros[ccrosEntryCount].ccros[8] = '0'; 159 | 160 | ccros[ccrosEntryCount].ccros[9] = ccrosLine.CH[0]; 161 | ccros[ccrosEntryCount].ccros[10] = ccrosLine.CH[1]; 162 | ccros[ccrosEntryCount].ccros[11] = ccrosLine.CH[2]; 163 | ccros[ccrosEntryCount].ccros[12] = ccrosLine.CH[3]; 164 | 165 | ccros[ccrosEntryCount].ccros[13] = ccrosLine.CL[0]; 166 | ccros[ccrosEntryCount].ccros[14] = ccrosLine.CL[1]; 167 | ccros[ccrosEntryCount].ccros[15] = ccrosLine.CL[2]; 168 | ccros[ccrosEntryCount].ccros[16] = ccrosLine.CL[3]; 169 | 170 | ccros[ccrosEntryCount].ccros[17] = ccrosLine.CM[0]; 171 | ccros[ccrosEntryCount].ccros[18] = ccrosLine.CM[1]; 172 | ccros[ccrosEntryCount].ccros[19] = ccrosLine.CM[2]; 173 | 174 | ccros[ccrosEntryCount].ccros[20] = ccrosLine.CU[0]; 175 | ccros[ccrosEntryCount].ccros[21] = ccrosLine.CU[1]; 176 | 177 | ccros[ccrosEntryCount].ccros[22] = ccrosLine.CA[0]; 178 | ccros[ccrosEntryCount].ccros[23] = ccrosLine.CA[1]; 179 | ccros[ccrosEntryCount].ccros[24] = ccrosLine.CA[2]; 180 | ccros[ccrosEntryCount].ccros[25] = ccrosLine.CA[3]; 181 | 182 | ccros[ccrosEntryCount].ccros[26] = ccrosLine.CB[0]; 183 | ccros[ccrosEntryCount].ccros[27] = ccrosLine.CB[1]; 184 | 185 | ccros[ccrosEntryCount].ccros[28] = ccrosLine.CK[0]; 186 | ccros[ccrosEntryCount].ccros[29] = ccrosLine.CK[1]; 187 | ccros[ccrosEntryCount].ccros[30] = ccrosLine.CK[2]; 188 | ccros[ccrosEntryCount].ccros[31] = ccrosLine.CK[3]; 189 | 190 | ccros[ccrosEntryCount].ccros[32] = ccrosLine.PK; 191 | 192 | /* 32 (PC) is calculated later */ 193 | ccros[ccrosEntryCount].ccros[33] = '0'; 194 | 195 | ccros[ccrosEntryCount].ccros[34] = ccrosLine.CD[0]; 196 | ccros[ccrosEntryCount].ccros[35] = ccrosLine.CD[1]; 197 | ccros[ccrosEntryCount].ccros[36] = ccrosLine.CD[2]; 198 | ccros[ccrosEntryCount].ccros[37] = ccrosLine.CD[3]; 199 | 200 | ccros[ccrosEntryCount].ccros[38] = ccrosLine.CF[0]; 201 | ccros[ccrosEntryCount].ccros[39] = ccrosLine.CF[1]; 202 | ccros[ccrosEntryCount].ccros[40] = ccrosLine.CF[2]; 203 | 204 | ccros[ccrosEntryCount].ccros[41] = ccrosLine.CG[0]; 205 | ccros[ccrosEntryCount].ccros[42] = ccrosLine.CG[1]; 206 | 207 | ccros[ccrosEntryCount].ccros[43] = ccrosLine.CV[0]; 208 | ccros[ccrosEntryCount].ccros[44] = ccrosLine.CV[1]; 209 | 210 | ccros[ccrosEntryCount].ccros[45] = ccrosLine.CC[0]; 211 | ccros[ccrosEntryCount].ccros[46] = ccrosLine.CC[1]; 212 | ccros[ccrosEntryCount].ccros[47] = ccrosLine.CC[2]; 213 | 214 | ccros[ccrosEntryCount].ccros[48] = ccrosLine.CS[0]; 215 | ccros[ccrosEntryCount].ccros[49] = ccrosLine.CS[1]; 216 | ccros[ccrosEntryCount].ccros[50] = ccrosLine.CS[2]; 217 | ccros[ccrosEntryCount].ccros[51] = ccrosLine.CS[3]; 218 | 219 | ccros[ccrosEntryCount].ccros[52] = ccrosLine.AA; 220 | ccros[ccrosEntryCount].ccros[53] = ccrosLine.AS; 221 | ccros[ccrosEntryCount].ccros[54] = ccrosLine.AK; 222 | 223 | /* Now change any ? to 0 */ 224 | for (ptr=&ccros[ccrosEntryCount].ccros[0];ptr<=&ccros[ccrosEntryCount].ccros[54];ptr++) 225 | if (*ptr=='?') *ptr='0'; 226 | 227 | /* PA */ 228 | ccros[ccrosEntryCount].ccros[8] = parity(addrBinary,12,'1'); 229 | 230 | /* PN = CN */ 231 | ccros[ccrosEntryCount].ccros[0] = parity((char*)&ccros[ccrosEntryCount].ccros[1],6,'1'); 232 | 233 | /* PS = PA CH CL CM CU CA CB CK PK AA AK */ 234 | ccros[ccrosEntryCount].ccros[7] = parity((char*)&ccros[ccrosEntryCount].ccros[8],25, 235 | parity((char*)&ccros[ccrosEntryCount].ccros[52],1, 236 | parity((char*)&ccros[ccrosEntryCount].ccros[54],1,'1' 237 | ) 238 | ) 239 | ); 240 | 241 | /* PC = CD CF CG CV CC CS AS */ 242 | ccros[ccrosEntryCount].ccros[33] = parity((char*)&ccros[ccrosEntryCount].ccros[34],18, 243 | parity((char*)&ccros[ccrosEntryCount].ccros[53],1,'1' 244 | ) 245 | ); 246 | 247 | /* BA0 flip PA & PC */ 248 | if (ccros[ccrosEntryCount].address==0xBA0) { 249 | ccros[ccrosEntryCount].ccros[8] = ccros[ccrosEntryCount].ccros[8] ^ 1; 250 | ccros[ccrosEntryCount].ccros[33] = ccros[ccrosEntryCount].ccros[33] ^ 1; 251 | } 252 | /* B60 flip PN, PS, PA & PC */ 253 | if (ccros[ccrosEntryCount].address==0xB60) { 254 | ccros[ccrosEntryCount].ccros[0] = ccros[ccrosEntryCount].ccros[0] ^ 1; 255 | ccros[ccrosEntryCount].ccros[7] = ccros[ccrosEntryCount].ccros[7] ^ 1; 256 | ccros[ccrosEntryCount].ccros[8] = ccros[ccrosEntryCount].ccros[8] ^ 1; 257 | ccros[ccrosEntryCount].ccros[33] = ccros[ccrosEntryCount].ccros[33] ^ 1; 258 | } 259 | ccrosEntryCount++; 260 | } 261 | } 262 | else 263 | break; 264 | } 265 | /* Now output */ 266 | for (i=0;i \"%s\",\r\n",ccros[i].address,(char*)&ccros[i].ccros[0]); 268 | } 269 | } 270 | -------------------------------------------------------------------------------- /clock_management.vhd: -------------------------------------------------------------------------------- 1 | --***************************************************************************************** 2 | --** 3 | --** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 4 | --** provided to you "as is". Xilinx and its licensors make and you 5 | --** receive no warranties or conditions, express, implied, statutory 6 | --** or otherwise, and Xilinx specifically disclaims any implied 7 | --** warranties of merchantability, non-infringement, or fitness for a 8 | --** particular purpose. Xilinx does not warrant that the functions 9 | --** contained in these designs will meet your requirements, or that the 10 | --** operation of these designs will be uninterrupted or error free, or 11 | --** that defects in the Designs will be corrected. Furthermore, Xilinx 12 | --** does not warrant or make any representations regarding use or the 13 | --** results of the use of the designs in terms of correctness, accuracy, 14 | --** reliability, or otherwise. 15 | --** 16 | --** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 17 | --** liable for any loss of data, lost profits, cost or procurement of 18 | --** substitute goods or services, or for any special, incidental, 19 | --** consequential, or indirect damages arising from the use or operation 20 | --** of the designs or accompanying documentation, however caused and on 21 | --** any theory of liability. This limitation will apply even if Xilinx 22 | --** has been advised of the possibility of such damage. This limitation 23 | --** shall apply not-withstanding the failure of the essential purpose of 24 | --** any limited remedies herein. 25 | --** 26 | --***************************************************************************************** 27 | -- MODULE : clock_management.vhd 28 | -- AUTHOR : Stephan Neuhold 29 | -- VERSION : v1.00 30 | -- 31 | -- 32 | -- REVISION HISTORY: 33 | -- ----------------- 34 | -- No revisions 35 | -- 36 | -- 37 | -- FUNCTION DESCRIPTION: 38 | -- --------------------- 39 | -- This module generates an enable signal for 40 | -- the shift register and comparator. It also 41 | -- generates the clock signal that is connected 42 | -- to the PROM. 43 | -- The enable and clock signals are generated 44 | -- based on the "frequency" generic entered for 45 | -- the system clock. 46 | -- The clock signal is only generated at the 47 | -- appropriate times. All other states the clock 48 | -- signal is kept at a logic high. The PROMs 49 | -- address counter only increments on a rising 50 | -- edge of this clock. 51 | 52 | 53 | --*************************** 54 | --* Library declarations 55 | --*************************** 56 | library IEEE; 57 | use IEEE.STD_LOGIC_1164.ALL; 58 | use IEEE.STD_LOGIC_ARITH.ALL; 59 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 60 | 61 | library UNISIM; 62 | use UNISIM.VComponents.all; 63 | 64 | 65 | --*********************** 66 | --* Entity declaration 67 | --*********************** 68 | entity clock_management is 69 | generic( 70 | length : integer := 5; 71 | frequency : integer := 50 72 | ); 73 | port( 74 | clock : in std_logic; 75 | enable : in std_logic; 76 | read_enable : out std_logic; 77 | cclk : out std_logic 78 | ); 79 | end clock_management; 80 | 81 | 82 | architecture Behavioral of clock_management is 83 | 84 | 85 | signal cclk_int : std_logic := '1'; 86 | signal enable_cclk : std_logic; 87 | signal SRL_length : std_logic_vector(3 downto 0); 88 | signal temp : integer := (frequency / 20) - 1; 89 | 90 | 91 | begin 92 | 93 | 94 | --*************************************************** 95 | --* The length of the SRL16 is based on the system 96 | --* clock frequency entered. This frequency is then 97 | --* "divided" down to approximately 10MHz. 98 | --*************************************************** 99 | SRL_length <= conv_std_logic_vector(temp, length - 1); 100 | 101 | Divider0: SRL16 102 | generic map( 103 | init => X"0001" 104 | ) 105 | port map( 106 | clk => clock, 107 | d => enable_cclk, 108 | a0 => SRL_length(0), 109 | a1 => SRL_length(1), 110 | a2 => SRL_length(2), 111 | a3 => SRL_length(3), 112 | q => enable_cclk 113 | ); 114 | 115 | 116 | --*************************************************** 117 | --* This process generates the enable signal for 118 | --* the shift register and the comparator. It also 119 | --* generates the clock signal used to increment 120 | --* the PROMs address counter. 121 | --*************************************************** 122 | process(clock, enable_cclk, enable, cclk_int) 123 | begin 124 | if rising_edge(clock) then 125 | if (enable = '1') then 126 | if (enable_cclk = '1') then 127 | cclk_int <= not cclk_int; 128 | end if; 129 | if (enable_cclk = '1' and cclk_int = '1') then 130 | read_enable <= '1'; 131 | else 132 | read_enable <= '0'; 133 | end if; 134 | else 135 | cclk_int <= '1'; 136 | end if; 137 | end if; 138 | cclk <= cclk_int; 139 | end process; 140 | 141 | 142 | end Behavioral; 143 | -------------------------------------------------------------------------------- /cpu.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/cpu.vhd -------------------------------------------------------------------------------- /digilentSP3.ucf: -------------------------------------------------------------------------------- 1 | # Spartan-3 Starter Board, Digilent 2 | # pin locations 3 | # Original by Pierre Langlois, 2004/07/22 4 | # minimal translation by Capt. LeSauvage 2004/09/23 5 | # LJW2030 V1.0 by Lawrence Wilkinson, 2010/07/16 6 | # V1.1 2012-04-07 7 | # 8 | # Remove the comment symbols (#) in front of the desired lines. 9 | # The names of the ports must match exactly between this file and the design. 10 | 11 | # clock 12 | NET "clk" LOC = "T9"; # 50 MHz 13 | 14 | # LEDs 15 | NET "led<7>" LOC = "P11"; 16 | NET "led<6>" LOC = "P12"; 17 | NET "led<5>" LOC = "N12"; 18 | NET "led<4>" LOC = "P13"; 19 | NET "led<3>" LOC = "N14"; 20 | NET "led<2>" LOC = "L12"; 21 | NET "led<1>" LOC = "P14"; 22 | NET "led<0>" LOC = "K12"; 23 | 24 | # slide switches 25 | NET "sw<7>" LOC = "K13"; 26 | NET "sw<6>" LOC = "K14"; 27 | NET "sw<5>" LOC = "J13"; 28 | NET "sw<4>" LOC = "J14"; 29 | NET "sw<3>" LOC = "H13"; 30 | NET "sw<2>" LOC = "H14"; 31 | NET "sw<1>" LOC = "G12"; 32 | NET "sw<0>" LOC = "F12"; 33 | 34 | # push buttons 35 | NET "pb<3>" LOC = "L14"; 36 | NET "pb<2>" LOC = "L13"; 37 | NET "pb<1>" LOC = "M14"; 38 | NET "pb<0>" LOC = "M13"; 39 | 40 | # seven segment display - shared segments 41 | NET "ssd<7>" LOC = "P16"; 42 | NET "ssd<6>" LOC = "N16"; 43 | NET "ssd<5>" LOC = "F13"; 44 | NET "ssd<4>" LOC = "R16"; 45 | NET "ssd<3>" LOC = "P15"; 46 | NET "ssd<2>" LOC = "N15"; 47 | NET "ssd<1>" LOC = "G13"; 48 | NET "ssd<0>" LOC = "E14"; 49 | 50 | # seven segment display - anodes 51 | NET "ssdan<3>" LOC = "E13"; 52 | NET "ssdan<2>" LOC = "F14"; 53 | NET "ssdan<1>" LOC = "G14"; 54 | NET "ssdan<0>" LOC = "D14"; 55 | 56 | # VGA port 57 | NET "vga_r" LOC = "R12"; 58 | NET "vga_g" LOC = "T12"; 59 | NET "vga_b" LOC = "R11"; 60 | NET "vga_hs" LOC = "R9"; 61 | NET "vga_vs" LOC = "T10"; 62 | 63 | # PS/2 port 64 | #NET "ps2_clk" LOC="M16"; 65 | #NET "ps2_data" LOC="M15"; 66 | 67 | # Expansion ports 68 | #A1 69 | #A2 70 | # 1 Gnd 71 | # 2 VU (+5V) 72 | # 3 Vcco (+3.3V) 73 | NET "pa_io1" LOC="E6"; # HexSw Bit0 74 | NET "pa_io1" PULLDOWN; 75 | NET "pa_io2" LOC="D5"; # HexSw Bit1 76 | NET "pa_io2" PULLDOWN; 77 | NET "pa_io3" LOC="C5"; # HexSw Bit2 78 | NET "pa_io3" PULLDOWN; 79 | NET "pa_io4" LOC="D6"; # HexSw Bit3 80 | NET "pa_io4" PULLDOWN; 81 | NET "pa_io5" LOC="C6"; # HexSwA 82 | NET "pa_io6" LOC="E7"; # HexSwB 83 | # 10: 84 | NET "pa_io7" LOC="C7"; # HexSwC 85 | NET "pa_io8" LOC="D7"; # HexSwD 86 | NET "pa_io9" LOC="C8"; # HexSwE 87 | NET "pa_io10" LOC="D8"; # HexSwF 88 | NET "pa_io11" LOC="C9"; # HexSwG 89 | NET "pa_io12" LOC="D10"; # HexSwH 90 | NET "pa_io13" LOC="A3"; # HexSwJ 91 | NET "pa_io14" LOC="B4"; # HexSwAdrComp 92 | NET "pa_io15" LOC="A4"; # SwE Inner 93 | NET "pa_io15" PULLDOWN; 94 | NET "pa_io16" LOC="B5"; # SwE Outer 95 | NET "pa_io16" PULLDOWN; 96 | # 20: 97 | NET "pa_io17" LOC="A5"; # ROS Ctl INH_CF_STOP 98 | NET "pa_io17" PULLDOWN; 99 | NET "pa_io18" LOC="B6"; # ROS Ctl SCAN 100 | NET "pa_io18" PULLDOWN; 101 | NET "ma2_db0" LOC="B7"; # Rate INST_STEP 102 | NET "ma2_db0" PULLDOWN; 103 | NET "ma2_db1" LOC="A7"; # Rate SINGLE_CYCLE 104 | NET "ma2_db1" PULLDOWN; 105 | NET "ma2_db2" LOC="B8"; # Chk Ctk DIAGNOSTIC 106 | NET "ma2_db2" PULLDOWN; 107 | NET "ma2_db3" LOC="A8"; # Chk Ctl DISABLE 108 | NET "ma2_db3" PULLDOWN; 109 | NET "ma2_db4" LOC="A9"; # Chk Ctl STOP 110 | NET "ma2_db4" PULLDOWN; 111 | NET "ma2_db5" LOC="B10"; # Chk Ctl RESTART 112 | NET "ma2_db5" PULLDOWN; 113 | #NET "ma2_db6" LOC="A10"; # Sys Reset 114 | #NET "ma2_db6" PULLDOWN; 115 | #NET "ma2_db7" LOC="B11"; # ROAR Reset 116 | #NET "ma2_db7" PULLDOWN; 117 | # 30: 118 | #NET "ma2_astb" LOC="B12"; # Start 119 | #NET "ma2_astb" PULLDOWN; 120 | #NET "ma2_dstb" LOC="A12"; # Stop 121 | #NET "ma2_dstb" PULLDOWN; 122 | #NET "ma2_write" LOC="B13"; # Display 123 | #NET "ma2_write" PULLDOWN; 124 | #NET "ma2_wait" LOC="A13"; # Store 125 | #NET "ma2_wait" PULLDOWN; 126 | #NET "ma2_reset" LOC="B14"; # Set IC 127 | #NET "ma2_reset" PULLDOWN; 128 | #NET "ma2_int" LOC="D9"; # Check Reset 129 | #NET "ma2_int" PULLDOWN; 130 | 131 | #A3 132 | 133 | # SRAM 134 | NET "sramaddr<17>" LOC="L3"; 135 | NET "sramaddr<16>" LOC="K5"; 136 | NET "sramaddr<15>" LOC="K3"; 137 | NET "sramaddr<14>" LOC="J3"; 138 | NET "sramaddr<13>" LOC="J4"; 139 | NET "sramaddr<12>" LOC="H4"; 140 | NET "sramaddr<11>" LOC="H3"; 141 | NET "sramaddr<10>" LOC="G5"; 142 | NET "sramaddr<9>" LOC="E4"; 143 | NET "sramaddr<8>" LOC="E3"; 144 | NET "sramaddr<7>" LOC="F4"; 145 | NET "sramaddr<6>" LOC="F3"; 146 | NET "sramaddr<5>" LOC="G4"; 147 | NET "sramaddr<4>" LOC="L4"; 148 | NET "sramaddr<3>" LOC="M3"; 149 | NET "sramaddr<2>" LOC="M4"; 150 | NET "sramaddr<1>" LOC="N3"; 151 | NET "sramaddr<0>" LOC="L5"; 152 | #NET "srama<15>" LOC="R1"; 153 | #NET "srama<15>" PULLDOWN; 154 | #NET "srama<14>" LOC="P1"; 155 | #NET "srama<14>" PULLDOWN; 156 | #NET "srama<13>" LOC="L2"; 157 | #NET "srama<13>" PULLDOWN; 158 | #NET "srama<12>" LOC="J2"; 159 | #NET "srama<12>" PULLDOWN; 160 | #NET "srama<11>" LOC="H1"; 161 | #NET "srama<11>" PULLDOWN; 162 | #NET "srama<10>" LOC="F2"; 163 | #NET "srama<10>" PULLDOWN; 164 | #NET "srama<9>" LOC="P8"; 165 | #NET "srama<9>" PULLDOWN; 166 | NET "srama<8>" LOC="D3"; 167 | NET "srama<7>" LOC="B1"; 168 | NET "srama<6>" LOC="C1"; 169 | NET "srama<5>" LOC="C2"; 170 | NET "srama<4>" LOC="R5"; 171 | NET "srama<3>" LOC="T5"; 172 | NET "srama<2>" LOC="R6"; 173 | NET "srama<1>" LOC="T8"; 174 | NET "srama<0>" LOC="N7"; 175 | NET "sramace" LOC="P7"; 176 | NET "sramaub" LOC="T4"; 177 | NET "sramalb" LOC="P6"; 178 | # NET "sramb<15>" LOC="N1"; 179 | # NET "sramb<14>" LOC="M1"; 180 | # NET "sramb<13>" LOC="K2"; 181 | # NET "sramb<12>" LOC="C3"; 182 | # NET "sramb<11>" LOC="F5"; 183 | # NET "sramb<10>" LOC="G1"; 184 | # NET "sramb<09>" LOC="E2"; 185 | # NET "sramb<08>" LOC="D2"; 186 | # NET "sramb<07>" LOC="D1"; 187 | # NET "sramb<06>" LOC="E1"; 188 | # NET "sramb<05>" LOC="G2"; 189 | # NET "sramb<04>" LOC="J1"; 190 | # NET "sramb<03>" LOC="K1"; 191 | # NET "sramb<02>" LOC="M2"; 192 | # NET "sramb<01>" LOC="N2"; 193 | # NET "sramb<00>" LOC="P2"; 194 | # NET "srambce" LOC="N5"; 195 | # NET "srambub" LOC="R4"; 196 | # NET "sramblb" LOC="P5"; 197 | NET "sramwe" LOC="G3"; 198 | NET "sramoe" LOC="K4"; 199 | 200 | # For the other peripherals and ports listed here, 201 | # consult the Xilinx documentation. 202 | # RS-232 port 203 | NET "serialRx" LOC="T13"; 204 | NET "serialTx" LOC="R13"; 205 | 206 | # expansion connectors 207 | # 208 | # B1 209 | # 1 Gnd 210 | # 2 VU (+5V) 211 | # 3 Vcco (+3.3V) 212 | NET "MAX7219_CLK" LOC="C10"; # B1- 4 213 | NET "MAX7219_LOAD" LOC="T3"; # B1- 5 214 | NET "MAX7219_DIN" LOC="E10"; # B1- 6 215 | NET "MAX7318_SCL" LOC="N11"; # B1- 7 216 | NET "MAX7318_SDA" LOC="C11"; # B1- 8 217 | NET "MAX7318_SDA" PULLUP; 218 | #NET "B1-09" LOC="P10"; # B1- 9 219 | NET "MAX6951_CLK" LOC="D11"; # B1-10 220 | NET "MAX6951_CS0" LOC="R10"; # B1-11 221 | NET "MAX6951_CS1" LOC="C12"; # B1-12 222 | NET "MAX6951_CS2" LOC="T7"; # B1-13 223 | NET "MAX6951_CS3" LOC="D12"; # B1-14 224 | NET "MAX6951_DIN" LOC="R7"; # B1-15 225 | #NET "B1-16" LOC="E11"; 226 | #NET "B1-17" LOC="N6"; 227 | #NET "B1-18" LOC="B16"; 228 | #NET "B1-19" LOC="M6"; 229 | #NET "B1-20" LOC="R3"; 230 | #NET "B1-21" LOC="C15"; 231 | #NET "B1-22" LOC="C16"; 232 | #NET "B1-23" LOC="D15"; 233 | #NET "B1-24" LOC="D16"; 234 | #NET "B1-25" LOC="E15"; 235 | #NET "B1-26" LOC="E16"; 236 | #NET "B1-27" LOC="F15"; 237 | #NET "B1-28" LOC="G15"; 238 | #NET "B1-29" LOC="G16"; 239 | #NET "B1-30" LOC="H15"; 240 | #NET "B1-31" LOC="H16"; 241 | #NET "B1-32" LOC="J16"; 242 | #NET "B1-33" LOC="K16"; 243 | #NET "B1-34" LOC="K15"; 244 | #NET "B1-35" LOC="L15"; 245 | #NET "B1-36" LOC="B3"; 246 | #NET "B1-37" LOC="R14"; 247 | #NET "B1-38" LOC="N9"; 248 | #NET "B1-39" LOC="T15"; 249 | #NET "B1-40" LOC="M11"; 250 | 251 | # 252 | # XCF04S Serial PROM connections 253 | # 254 | NET "din" LOC = "M11"; 255 | NET "reset_prom" LOC = "N9"; 256 | NET "rclk" LOC = "A14"; 257 | #NET "progb" LOC="B3"; 258 | #NET "fpgadone" LOC="R14"; 259 | #NET "fpgacclk" LOC="T15"; 260 | 261 | -------------------------------------------------------------------------------- /ibm1050.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | -- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk 3 | -- 4 | -- This file is part of LJW2030, a VHDL implementation of the IBM 5 | -- System/360 Model 30. 6 | -- 7 | -- LJW2030 is free software: you can redistribute it and/or modify 8 | -- it under the terms of the GNU General Public License as published by 9 | -- the Free Software Foundation, either version 3 of the License, or 10 | -- (at your option) any later version. 11 | -- 12 | -- LJW2030 is distributed in the hope that it will be useful, 13 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | -- GNU General Public License for more details. 16 | -- 17 | -- You should have received a copy of the GNU General Public License 18 | -- along with LJW2030 . If not, see . 19 | -- 20 | --------------------------------------------------------------------------- 21 | -- 22 | -- File: ibm1050.vhd 23 | -- Creation Date: 21:17:39 2005-04-18 24 | -- Description: 25 | -- 1050 (Console Typewriter) attachment 26 | -- 27 | -- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM) 28 | -- for the 360/30 R25-5103-1 29 | -- References like "02AE6" refer to coordinate "E6" on page "5-02A" 30 | -- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A" 31 | -- Gate A is the main logic gate, B is the second (optional) logic gate, 32 | -- C is the core storage and X is the CCROS unit 33 | -- 34 | -- Revision History: 35 | -- Revision 1.0 2012-04-07 36 | -- Initial release - no Tilt/Rotate to ASCII conversion on printing or handling 37 | -- of Shift-Up or Shift-Down, also no ASCII to key-code conversion on input 38 | -- (all this is handled inside the CPU) 39 | --------------------------------------------------------------------------- 40 | library IEEE; 41 | library UNISIM; 42 | use IEEE.STD_LOGIC_1164.ALL; 43 | use IEEE.STD_LOGIC_ARITH.ALL; 44 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 45 | USE work.Buses_package.all; 46 | use UNISIM.vcomponents.all; 47 | use work.all; 48 | 49 | entity ibm1050 is 50 | Port ( 51 | SerialIn : inout PCH_CONN; -- Data lines in to CPU 52 | SerialOut : in RDR_CONN; -- Data lines out of CPU 53 | SerialControl : in CONN_1050; -- Control lines out of CPU 54 | 55 | -- Serial I/O 56 | serialInput : in Serial_Input_Lines; 57 | serialOutput : out Serial_Output_Lines; 58 | 59 | -- 50Mhz clock 60 | clk : in std_logic 61 | ); 62 | end ibm1050; 63 | 64 | architecture FMD of ibm1050 is 65 | 66 | signal SerialBusUngated : STD_LOGIC_VECTOR(7 downto 0); 67 | signal RxDataAvailable : STD_LOGIC; 68 | signal TxBufferEmpty : STD_LOGIC; 69 | signal serialOutputByte : STD_LOGIC_VECTOR(7 downto 0); 70 | signal serialOutputStrobe : STD_LOGIC := '0'; 71 | signal RxAck, PunchGate : STD_LOGIC; 72 | signal resetSerial : STD_LOGIC := '0'; 73 | type printerStateType is (waitForEnable,printerReset,printerEnabled,printCharacter,waitForCharacter,waitFree,printCR,waitForCR,printLF,waitForLF); 74 | signal printerState : printerStateType := waitForEnable; 75 | signal RDR_1_CLUTCH_timer : STD_LOGIC_VECTOR(15 downto 0); 76 | 77 | begin 78 | 79 | Printer: process (clk) 80 | begin 81 | if rising_edge(clk) then 82 | case printerState is 83 | when waitForEnable => 84 | serialIn.HOME_RDR_STT_LCH <= '0'; -- Not running 85 | serialIn.RDR_1_CLUTCH_1050 <= '0'; -- Not ready to receive a character 86 | serialOutputStrobe <= '0'; 87 | if (serialControl.HOME_RDR_START='1') then 88 | resetSerial <= '1'; 89 | printerState <= printerReset; 90 | elsif (serialControl.CARR_RETURN_AND_LINE_FEED='1') then 91 | printerState <= printCR; 92 | end if; 93 | when printerReset => 94 | resetSerial <= '0'; 95 | printerState <= printerEnabled; 96 | when printerEnabled => 97 | serialIn.HOME_RDR_STT_LCH <= '1'; -- Running 98 | serialIn.RDR_1_CLUTCH_1050 <= TxBufferEmpty; -- Ready to receive a character 99 | if (serialControl.HOME_RDR_START='0') then 100 | printerState <= waitForEnable; 101 | elsif (serialOut.RD_STROBE='1') then 102 | printerState <= printCharacter; 103 | elsif (serialControl.CARR_RETURN_AND_LINE_FEED='1') then 104 | printerState <= printCR; 105 | end if; 106 | when printCharacter => 107 | serialIn.RDR_1_CLUTCH_1050 <= '0'; -- Not ready for another character 108 | serialOutputByte <= '0' & SerialOut.RDR_BITS; -- Here we could translate from TILT/ROTATE to ASCII 109 | serialOutputStrobe <= '1'; 110 | printerState <= waitForCharacter; 111 | RDR_1_CLUTCH_TIMER <= x"9C40"; -- 9C40 = 40000 = 800us 112 | when waitForCharacter => 113 | -- Need to wait in this state for long enough to guarantee that 114 | -- RDR_1_CLUTCH is still low at Y_TIME to reset ALLOW_STROBE latch 115 | serialOutputStrobe <= '0'; 116 | if (serialOut.RD_STROBE='0') then 117 | RDR_1_CLUTCH_timer <= RDR_1_CLUTCH_timer - "0000000000000001"; 118 | if (RDR_1_CLUTCH_timer="0000000000000000") then 119 | printerState <= printerEnabled; 120 | end if; 121 | end if; 122 | when printCR => 123 | if (TxBufferEmpty='1') then 124 | serialOutputByte <= "00001101"; -- CR 125 | serialOutputStrobe <= '1'; 126 | printerState <= waitForCR; 127 | end if; 128 | when waitForCR => 129 | serialOutputStrobe <= '0'; 130 | printerState <= printLF; 131 | when printLF => 132 | if (TxBufferEmpty='1') then 133 | serialOutputByte <= "00001010"; -- LF 134 | serialOutputStrobe <= '1'; 135 | printerState <= waitForLF; 136 | end if; 137 | when waitForLF => 138 | serialOutputStrobe <= '0'; 139 | if (serialControl.CARR_RETURN_AND_LINE_FEED='0') then -- Wait for CRLF to drop 140 | if (serialControl.HOME_RDR_START='0') then 141 | printerState <= waitForEnable; 142 | else 143 | printerState <= printerEnabled; 144 | end if; 145 | end if; 146 | when others => 147 | printerState <= waitForEnable; 148 | end case; 149 | end if; 150 | end process Printer; 151 | 152 | serial_port : entity RS232RefComp port map( 153 | RST => '0', --Master Reset 154 | CLK => clk, 155 | -- Rx (PCH) 156 | RXD => SerialInput.serialRx, 157 | RDA => RxDataAvailable, -- Rx data available 158 | PE => open, -- Parity Error Flag 159 | FE => open, -- Frame Error Flag 160 | OE => open, -- Overwrite Error Flag 161 | DBOUT => SerialBusUngated, -- Rx data (needs to be 0 when RDA=0) 162 | RD => RxAck, -- Read strobe 163 | -- Tx (RDR) 164 | TXD => serialOutput.serialTx, 165 | TBE => TxBufferEmpty, -- Tx buffer empty 166 | DBIN => serialOutputByte, -- Tx data 167 | WR => serialOutputStrobe -- Write Strobe 168 | ); 169 | -- Make incoming data 0 when nothing is available 170 | SerialIn.PCH_BITS <= SerialBusUngated(6 downto 0) when PunchGate='1' else "0000000"; 171 | PunchStrobeSS : entity SS port map (clk=>clk, count=>2500, D=>RxDataAvailable, Q=>RxAck); -- 50us or so 172 | SerialIn.PCH_1_CLUTCH_1050 <= RxAck; 173 | PunchGateSS : entity SS port map (clk=>clk, count=>3000, D=>RxDataAvailable, Q=>PunchGate); -- A bit more than 50us so Read Interlock is reset after PCH_1_CLUTCH drops 174 | 175 | SerialIn.CPU_CONNECTED <= '1'; -- 1050 always on-line 176 | SerialIn.HOME_OUTPUT_DEV_RDY <= '1'; -- Printer always ready 177 | SerialIn.RDR_2_READY <= '0'; 178 | -- SerialIn.HOME_RDR_STT_LCH <= SerialControl.HOME_RDR_START; 179 | SerialIn.REQ_KEY <= '0'; 180 | 181 | SerialOutput.RTS <= '1'; 182 | SerialOutput.DTR <= '1'; 183 | 184 | end FMD; 185 | -------------------------------------------------------------------------------- /ibm2030-switches.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/ibm2030-switches.vhd -------------------------------------------------------------------------------- /ibm2030.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/ibm2030.bit -------------------------------------------------------------------------------- /panel_LEDs.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/panel_LEDs.vhd -------------------------------------------------------------------------------- /panel_Switches.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/panel_Switches.vhd -------------------------------------------------------------------------------- /shift_compare_serial.vhd: -------------------------------------------------------------------------------- 1 | --***************************************************************************************** 2 | --** 3 | --** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 4 | --** provided to you "as is". Xilinx and its licensors make and you 5 | --** receive no warranties or conditions, express, implied, statutory 6 | --** or otherwise, and Xilinx specifically disclaims any implied 7 | --** warranties of merchantability, non-infringement, or fitness for a 8 | --** particular purpose. Xilinx does not warrant that the functions 9 | --** contained in these designs will meet your requirements, or that the 10 | --** operation of these designs will be uninterrupted or error free, or 11 | --** that defects in the Designs will be corrected. Furthermore, Xilinx 12 | --** does not warrant or make any representations regarding use or the 13 | --** results of the use of the designs in terms of correctness, accuracy, 14 | --** reliability, or otherwise. 15 | --** 16 | --** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be 17 | --** liable for any loss of data, lost profits, cost or procurement of 18 | --** substitute goods or services, or for any special, incidental, 19 | --** consequential, or indirect damages arising from the use or operation 20 | --** of the designs or accompanying documentation, however caused and on 21 | --** any theory of liability. This limitation will apply even if Xilinx 22 | --** has been advised of the possibility of such damage. This limitation 23 | --** shall apply not-withstanding the failure of the essential purpose of 24 | --** any limited remedies herein. 25 | --** 26 | --***************************************************************************************** 27 | -- MODULE : shift_compare_serial.vhd 28 | -- AUTHOR : Stephan Neuhold 29 | -- VERSION : v1.00 30 | -- 31 | -- 32 | -- REVISION HISTORY: 33 | -- ----------------- 34 | -- No revisions 35 | -- 36 | -- 37 | -- FUNCTION DESCRIPTION: 38 | -- --------------------- 39 | -- This module provides the shifting in of data 40 | -- and comparing that data to the synchronisation 41 | -- pattern. Once the synchronisation pattern has 42 | -- been found, the last eight bits of data 43 | -- shifted in are presented. 44 | -- 45 | -- The shift register and comparator are 46 | -- automatically scaled to the correct length 47 | -- using the "length" generic. 48 | 49 | 50 | --*************************** 51 | --* Library declarations 52 | --*************************** 53 | library IEEE; 54 | use IEEE.STD_LOGIC_1164.ALL; 55 | use IEEE.STD_LOGIC_ARITH.ALL; 56 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 57 | 58 | library UNISIM; 59 | use UNISIM.VComponents.all; 60 | 61 | 62 | --*********************** 63 | --* Entity declaration 64 | --*********************** 65 | entity shift_compare_serial is 66 | generic( 67 | length : integer := 5 68 | ); 69 | port( 70 | clock : in std_logic; 71 | reset : in std_logic; 72 | enable : in std_logic; 73 | din : in std_logic; 74 | b : in std_logic_vector((2**length) - 1 downto 0); 75 | eq : out std_logic; 76 | din_shifted : out std_logic_vector(7 downto 0) 77 | ); 78 | end shift_compare_serial; 79 | 80 | 81 | architecture Behavioral of shift_compare_serial is 82 | 83 | 84 | signal q : std_logic_vector((2**length) - 1 downto 0); 85 | signal r : std_logic_vector((2**length) downto 0); 86 | signal a : std_logic_vector((2**length) - 1 downto 0); 87 | signal b_swapped : std_logic_vector((2**length) - 1 downto 0); 88 | signal GND : std_logic; 89 | 90 | 91 | begin 92 | 93 | 94 | --*************************************************** 95 | --* This process swaps the bits in the data byte. 96 | --* This is done to present the data in the format 97 | --* that it is entered in the PROM file. 98 | --*************************************************** 99 | process (clock, a) 100 | begin 101 | for i in 0 to 7 loop 102 | din_shifted(i) <= a(((2**length) - 1) - i); 103 | end loop; 104 | end process; 105 | 106 | 107 | --******************************************************* 108 | --* This process swaps the bits of every byte of the 109 | --* synchronisation pattern. This is done so that 110 | --* data read in from the PROM can be directly 111 | --* compared. Data from the PROM is read with all 112 | --* bits of every byte swapped. 113 | --* e.g. 114 | --* If the data in the PROM is 28h then this is read in 115 | --* the following way: 116 | --* 00010100 117 | --******************************************************* 118 | process (clock, b) 119 | begin 120 | for i in 0 to (((2**length) / 8) - 1) loop 121 | for j in 0 to 7 loop 122 | b_swapped((8 * i) + j) <= b(7 + (8 * i) - j); 123 | end loop; 124 | end loop; 125 | end process; 126 | 127 | 128 | --*********************************************** 129 | --* This is the first FF of the shift register. 130 | --* It needs to be seperated from the rest 131 | --* since it has a different input. 132 | --*********************************************** 133 | GND <= '0'; 134 | r(0) <= '1'; 135 | 136 | Data_Shifter_0_Serial: FDRE 137 | port map( 138 | C => clock, 139 | D => din, 140 | CE => enable, 141 | R => reset, 142 | Q => a(0) 143 | ); 144 | 145 | 146 | --*************************************************** 147 | --* This loop generates as many registers needed 148 | --* based on the length of the synchronisation 149 | --* word. 150 | --*************************************************** 151 | Shifter_Serial: 152 | for i in 1 to (2**length) - 1 generate 153 | Data_Shifter_Serial: FDRE 154 | port map( 155 | C => clock, 156 | D => a(i - 1), 157 | CE => enable, 158 | R => reset, 159 | Q => a(i) 160 | ); 161 | end generate; 162 | 163 | 164 | --*********************************************** 165 | --* This loop generates as many LUTs and MUXCYs 166 | --* as needed based on the length of the 167 | --* synchronisation word. 168 | --*********************************************** 169 | Comparator_Serial: 170 | for i in 0 to (2**length) - 1 generate 171 | Comparator_LUTs_Serial: LUT2 172 | generic map( 173 | INIT => X"9" 174 | ) 175 | port map( 176 | I0 => a(i), 177 | I1 => b_swapped(i), 178 | O => q(i) 179 | ); 180 | 181 | Comparator_MUXs_Serial: MUXCY 182 | port map( 183 | DI => GND, 184 | CI => r(i), 185 | S => q(i), 186 | O => r(i + 1) 187 | ); 188 | end generate; 189 | 190 | eq <= r(2**length); 191 | 192 | 193 | end Behavioral; 194 | -------------------------------------------------------------------------------- /vga_controller_640_60.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ibm2030/IBM2030/60ebdf7263b77bfbcbd33a4f63bbe072f3c17cb1/vga_controller_640_60.vhd --------------------------------------------------------------------------------