├── LICENSE ├── README.md ├── images └── core_ppln.png ├── rtl ├── README.md ├── shared │ ├── and_or_mux.sv │ ├── arbiter.sv │ ├── data_cache.sv │ ├── data_operation.sv │ ├── eb_buff_generic.sv │ ├── eb_one_slot.sv │ ├── eb_two_slot.sv │ ├── fifo_dual_ported.sv │ ├── fifo_duth.sv │ ├── fifo_flush.sv │ ├── fifo_initialized.sv │ ├── fifo_overflow.sv │ ├── ld_st_buffer.sv │ ├── lru.sv │ ├── lru_more.sv │ ├── lru_two.sv │ ├── main_memory.sv │ ├── onehot_detect.sv │ ├── params.sv │ ├── rr_arbiter.sv │ ├── sram.sv │ ├── structs.sv │ └── wait_buffer.sv └── vector │ ├── v_fp_alu.sv │ ├── v_int_alu.sv │ ├── vdata_operation.sv │ ├── vector_top.sv │ ├── vex.sv │ ├── vex_pipe.sv │ ├── vis.sv │ ├── vld_st_buffer.sv │ ├── vmacros.sv │ ├── vmu.sv │ ├── vmu_ld_eng.sv │ ├── vmu_st_eng.sv │ ├── vmu_tp_eng.sv │ ├── vrat.sv │ ├── vrf.sv │ ├── vrrm.sv │ └── vstructs.sv ├── sva ├── README.md ├── vector_top_sva.sv ├── vex_pipe_sva.sv ├── vex_sva.sv ├── vis_sva.sv ├── vmu_ld_eng_sva.sv ├── vmu_st_eng_sva.sv ├── vmu_sva.sv ├── vmu_tp_eng_sva.sv └── vrrm_sva.sv └── vector_simulator ├── README.md ├── compile_vector_simulator.do ├── decoder_results ├── autogenerated_params.sv ├── init_main_memory.txt └── instrs │ ├── data1_output.txt │ ├── data2_output.txt │ ├── decoded_output.txt │ ├── destination_output.txt │ ├── fu_output.txt │ ├── immediate_output.txt │ ├── maxvl_output.txt │ ├── microop_output.txt │ ├── operand_a_output.txt │ ├── operand_b_output.txt │ ├── operand_c_output.txt │ ├── reconfigure_output.txt │ └── vl_output.txt ├── examples ├── dot_product │ ├── decoder_results │ │ ├── autogenerated_params.sv │ │ ├── instrs │ │ │ ├── data1_output.txt │ │ │ ├── data2_output.txt │ │ │ ├── decoded_output.txt │ │ │ ├── destination_output.txt │ │ │ ├── fu_output.txt │ │ │ ├── immediate_output.txt │ │ │ ├── maxvl_output.txt │ │ │ ├── microop_output.txt │ │ │ ├── operand_a_output.txt │ │ │ ├── operand_b_output.txt │ │ │ ├── operand_c_output.txt │ │ │ ├── reconfigure_output.txt │ │ │ └── vl_output.txt │ │ ├── test_mem_1byte.txt │ │ ├── test_mem_2byte.txt │ │ └── test_mem_4byte.txt │ └── instrs.csv ├── fir │ ├── decoder_results │ │ ├── autogenerated_params.sv │ │ ├── instrs │ │ │ ├── data1_output.txt │ │ │ ├── data2_output.txt │ │ │ ├── decoded_output.txt │ │ │ ├── destination_output.txt │ │ │ ├── fu_output.txt │ │ │ ├── immediate_output.txt │ │ │ ├── maxvl_output.txt │ │ │ ├── microop_output.txt │ │ │ ├── operand_a_output.txt │ │ │ ├── operand_b_output.txt │ │ │ ├── operand_c_output.txt │ │ │ ├── reconfigure_output.txt │ │ │ └── vl_output.txt │ │ ├── test_mem_1byte.txt │ │ ├── test_mem_2byte.txt │ │ └── test_mem_4byte.txt │ └── instrs.csv ├── saxpy │ ├── decoder_results │ │ ├── autogenerated_params.sv │ │ ├── instrs │ │ │ ├── data1_output.txt │ │ │ ├── data2_output.txt │ │ │ ├── decoded_output.txt │ │ │ ├── destination_output.txt │ │ │ ├── fu_output.txt │ │ │ ├── immediate_output.txt │ │ │ ├── maxvl_output.txt │ │ │ ├── microop_output.txt │ │ │ ├── operand_a_output.txt │ │ │ ├── operand_b_output.txt │ │ │ ├── operand_c_output.txt │ │ │ ├── reconfigure_output.txt │ │ │ └── vl_output.txt │ │ ├── test_mem_1byte.txt │ │ ├── test_mem_2byte.txt │ │ └── test_mem_4byte.txt │ └── instrs.csv └── vvadd │ ├── decoder_results │ ├── autogenerated_params.sv │ ├── instrs │ │ ├── data1_output.txt │ │ ├── data2_output.txt │ │ ├── decoded_output.txt │ │ ├── destination_output.txt │ │ ├── fu_output.txt │ │ ├── immediate_output.txt │ │ ├── maxvl_output.txt │ │ ├── microop_output.txt │ │ ├── operand_a_output.txt │ │ ├── operand_b_output.txt │ │ ├── operand_c_output.txt │ │ ├── reconfigure_output.txt │ │ └── vl_output.txt │ ├── test_mem_1byte.txt │ ├── test_mem_2byte.txt │ └── test_mem_4byte.txt │ └── instrs.csv ├── files_rtl.f ├── files_sim.f ├── instrs.csv ├── sim_generator.py ├── vector_driver.sv ├── vector_sim_top.sv └── wave_simulator.do /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/README.md -------------------------------------------------------------------------------- /images/core_ppln.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/images/core_ppln.png -------------------------------------------------------------------------------- /rtl/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/README.md -------------------------------------------------------------------------------- /rtl/shared/and_or_mux.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/and_or_mux.sv -------------------------------------------------------------------------------- /rtl/shared/arbiter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/arbiter.sv -------------------------------------------------------------------------------- /rtl/shared/data_cache.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/data_cache.sv -------------------------------------------------------------------------------- /rtl/shared/data_operation.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/data_operation.sv -------------------------------------------------------------------------------- /rtl/shared/eb_buff_generic.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/eb_buff_generic.sv -------------------------------------------------------------------------------- /rtl/shared/eb_one_slot.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/eb_one_slot.sv -------------------------------------------------------------------------------- /rtl/shared/eb_two_slot.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/eb_two_slot.sv -------------------------------------------------------------------------------- /rtl/shared/fifo_dual_ported.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/fifo_dual_ported.sv -------------------------------------------------------------------------------- /rtl/shared/fifo_duth.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/fifo_duth.sv -------------------------------------------------------------------------------- /rtl/shared/fifo_flush.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/fifo_flush.sv -------------------------------------------------------------------------------- /rtl/shared/fifo_initialized.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/fifo_initialized.sv -------------------------------------------------------------------------------- /rtl/shared/fifo_overflow.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/fifo_overflow.sv -------------------------------------------------------------------------------- /rtl/shared/ld_st_buffer.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/ld_st_buffer.sv -------------------------------------------------------------------------------- /rtl/shared/lru.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/lru.sv -------------------------------------------------------------------------------- /rtl/shared/lru_more.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/lru_more.sv -------------------------------------------------------------------------------- /rtl/shared/lru_two.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/lru_two.sv -------------------------------------------------------------------------------- /rtl/shared/main_memory.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/main_memory.sv -------------------------------------------------------------------------------- /rtl/shared/onehot_detect.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/onehot_detect.sv -------------------------------------------------------------------------------- /rtl/shared/params.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/params.sv -------------------------------------------------------------------------------- /rtl/shared/rr_arbiter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/rr_arbiter.sv -------------------------------------------------------------------------------- /rtl/shared/sram.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/sram.sv -------------------------------------------------------------------------------- /rtl/shared/structs.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/structs.sv -------------------------------------------------------------------------------- /rtl/shared/wait_buffer.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/shared/wait_buffer.sv -------------------------------------------------------------------------------- /rtl/vector/v_fp_alu.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/v_fp_alu.sv -------------------------------------------------------------------------------- /rtl/vector/v_int_alu.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/v_int_alu.sv -------------------------------------------------------------------------------- /rtl/vector/vdata_operation.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vdata_operation.sv -------------------------------------------------------------------------------- /rtl/vector/vector_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vector_top.sv -------------------------------------------------------------------------------- /rtl/vector/vex.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vex.sv -------------------------------------------------------------------------------- /rtl/vector/vex_pipe.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vex_pipe.sv -------------------------------------------------------------------------------- /rtl/vector/vis.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vis.sv -------------------------------------------------------------------------------- /rtl/vector/vld_st_buffer.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vld_st_buffer.sv -------------------------------------------------------------------------------- /rtl/vector/vmacros.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vmacros.sv -------------------------------------------------------------------------------- /rtl/vector/vmu.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vmu.sv -------------------------------------------------------------------------------- /rtl/vector/vmu_ld_eng.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vmu_ld_eng.sv -------------------------------------------------------------------------------- /rtl/vector/vmu_st_eng.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vmu_st_eng.sv -------------------------------------------------------------------------------- /rtl/vector/vmu_tp_eng.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vmu_tp_eng.sv -------------------------------------------------------------------------------- /rtl/vector/vrat.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vrat.sv -------------------------------------------------------------------------------- /rtl/vector/vrf.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vrf.sv -------------------------------------------------------------------------------- /rtl/vector/vrrm.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vrrm.sv -------------------------------------------------------------------------------- /rtl/vector/vstructs.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/rtl/vector/vstructs.sv -------------------------------------------------------------------------------- /sva/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/README.md -------------------------------------------------------------------------------- /sva/vector_top_sva.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/vector_top_sva.sv -------------------------------------------------------------------------------- /sva/vex_pipe_sva.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/vex_pipe_sva.sv -------------------------------------------------------------------------------- /sva/vex_sva.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/vex_sva.sv -------------------------------------------------------------------------------- /sva/vis_sva.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/vis_sva.sv -------------------------------------------------------------------------------- /sva/vmu_ld_eng_sva.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/vmu_ld_eng_sva.sv -------------------------------------------------------------------------------- /sva/vmu_st_eng_sva.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/vmu_st_eng_sva.sv -------------------------------------------------------------------------------- /sva/vmu_sva.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/vmu_sva.sv -------------------------------------------------------------------------------- /sva/vmu_tp_eng_sva.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/vmu_tp_eng_sva.sv -------------------------------------------------------------------------------- /sva/vrrm_sva.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/sva/vrrm_sva.sv -------------------------------------------------------------------------------- /vector_simulator/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/README.md -------------------------------------------------------------------------------- /vector_simulator/compile_vector_simulator.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/compile_vector_simulator.do -------------------------------------------------------------------------------- /vector_simulator/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 442; -------------------------------------------------------------------------------- /vector_simulator/decoder_results/init_main_memory.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/init_main_memory.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/data1_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/data1_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/data2_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/data2_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/decoded_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/decoded_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/destination_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/destination_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/fu_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/fu_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/immediate_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/immediate_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/maxvl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/maxvl_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/microop_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/microop_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/operand_a_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/operand_a_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/operand_b_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/operand_b_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/operand_c_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/operand_c_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/reconfigure_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/reconfigure_output.txt -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/vl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/decoder_results/instrs/vl_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 1051; -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/data1_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/data1_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/data2_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/data2_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/decoded_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/decoded_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/destination_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/destination_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/fu_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/fu_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/immediate_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/immediate_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/maxvl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/maxvl_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/microop_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/microop_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/operand_a_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/operand_a_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/operand_b_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/operand_b_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/operand_c_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/operand_c_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/reconfigure_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/reconfigure_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/vl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/instrs/vl_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/test_mem_1byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/test_mem_1byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/test_mem_2byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/test_mem_2byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/test_mem_4byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/decoder_results/test_mem_4byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/instrs.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/dot_product/instrs.csv -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 2513; -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/data1_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/data1_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/data2_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/data2_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/decoded_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/decoded_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/destination_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/destination_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/fu_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/fu_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/immediate_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/immediate_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/maxvl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/maxvl_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/microop_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/microop_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/operand_a_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/operand_a_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/operand_b_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/operand_b_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/operand_c_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/operand_c_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/reconfigure_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/reconfigure_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/instrs/vl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/instrs/vl_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/test_mem_1byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/test_mem_1byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/test_mem_2byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/test_mem_2byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/test_mem_4byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/decoder_results/test_mem_4byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/fir/instrs.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/fir/instrs.csv -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 870; -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/data1_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/data1_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/data2_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/data2_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/decoded_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/decoded_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/destination_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/destination_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/fu_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/fu_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/immediate_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/immediate_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/maxvl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/maxvl_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/microop_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/microop_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/operand_a_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/operand_a_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/operand_b_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/operand_b_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/operand_c_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/operand_c_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/reconfigure_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/reconfigure_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/vl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/instrs/vl_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/test_mem_1byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/test_mem_1byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/test_mem_2byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/test_mem_2byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/test_mem_4byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/decoder_results/test_mem_4byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/instrs.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/saxpy/instrs.csv -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 442; -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/data1_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/data1_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/data2_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/data2_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/decoded_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/decoded_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/destination_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/destination_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/fu_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/fu_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/immediate_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/immediate_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/maxvl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/maxvl_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/microop_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/microop_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/operand_a_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/operand_a_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/operand_b_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/operand_b_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/operand_c_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/operand_c_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/reconfigure_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/reconfigure_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/vl_output.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/instrs/vl_output.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/test_mem_1byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/test_mem_1byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/test_mem_2byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/test_mem_2byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/test_mem_4byte.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/decoder_results/test_mem_4byte.txt -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/instrs.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/examples/vvadd/instrs.csv -------------------------------------------------------------------------------- /vector_simulator/files_rtl.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/files_rtl.f -------------------------------------------------------------------------------- /vector_simulator/files_sim.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/files_sim.f -------------------------------------------------------------------------------- /vector_simulator/instrs.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/instrs.csv -------------------------------------------------------------------------------- /vector_simulator/sim_generator.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/sim_generator.py -------------------------------------------------------------------------------- /vector_simulator/vector_driver.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/vector_driver.sv -------------------------------------------------------------------------------- /vector_simulator/vector_sim_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/vector_sim_top.sv -------------------------------------------------------------------------------- /vector_simulator/wave_simulator.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/vector_simulator/wave_simulator.do --------------------------------------------------------------------------------