├── vector_simulator ├── decoder_results │ ├── autogenerated_params.sv │ └── instrs │ │ ├── reconfigure_output.txt │ │ ├── fu_output.txt │ │ ├── destination_output.txt │ │ ├── operand_a_output.txt │ │ ├── operand_b_output.txt │ │ ├── operand_c_output.txt │ │ └── microop_output.txt ├── examples │ ├── fir │ │ ├── decoder_results │ │ │ └── autogenerated_params.sv │ │ └── instrs.csv │ ├── saxpy │ │ ├── decoder_results │ │ │ ├── autogenerated_params.sv │ │ │ └── instrs │ │ │ │ ├── reconfigure_output.txt │ │ │ │ └── fu_output.txt │ │ └── instrs.csv │ ├── vvadd │ │ ├── decoder_results │ │ │ ├── autogenerated_params.sv │ │ │ └── instrs │ │ │ │ ├── reconfigure_output.txt │ │ │ │ ├── fu_output.txt │ │ │ │ ├── destination_output.txt │ │ │ │ ├── operand_a_output.txt │ │ │ │ ├── operand_b_output.txt │ │ │ │ ├── operand_c_output.txt │ │ │ │ └── microop_output.txt │ │ └── instrs.csv │ └── dot_product │ │ ├── decoder_results │ │ ├── autogenerated_params.sv │ │ └── instrs │ │ │ └── reconfigure_output.txt │ │ └── instrs.csv ├── files_sim.f ├── instrs.csv ├── compile_vector_simulator.do ├── files_rtl.f ├── README.md └── vector_driver.sv ├── images └── core_ppln.png ├── sva ├── README.md ├── vmu_st_eng_sva.sv ├── vex_pipe_sva.sv ├── vex_sva.sv ├── vrrm_sva.sv ├── vmu_ld_eng_sva.sv ├── vmu_tp_eng_sva.sv ├── vmu_sva.sv ├── vis_sva.sv └── vector_top_sva.sv ├── rtl ├── vector │ ├── vmacros.sv │ ├── vrat.sv │ ├── vrf.sv │ ├── vdata_operation.sv │ ├── v_fp_alu.sv │ └── vstructs.sv ├── shared │ ├── lru_two.sv │ ├── and_or_mux.sv │ ├── lru.sv │ ├── onehot_detect.sv │ ├── arbiter.sv │ ├── sram.sv │ ├── eb_one_slot.sv │ ├── eb_buff_generic.sv │ ├── fifo_duth.sv │ ├── fifo_flush.sv │ ├── fifo_initialized.sv │ ├── fifo_overflow.sv │ ├── rr_arbiter.sv │ ├── lru_more.sv │ ├── eb_two_slot.sv │ ├── params.sv │ ├── fifo_dual_ported.sv │ ├── structs.sv │ └── data_operation.sv └── README.md ├── LICENSE └── README.md /vector_simulator/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 442; -------------------------------------------------------------------------------- /images/core_ppln.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ic-lab-duth/RISC-V-Vector/HEAD/images/core_ppln.png -------------------------------------------------------------------------------- /vector_simulator/examples/fir/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 2513; -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 870; -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 442; -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/autogenerated_params.sv: -------------------------------------------------------------------------------- 1 | localparam int SIM_VECTOR_INSTRS = 1051; -------------------------------------------------------------------------------- /sva/README.md: -------------------------------------------------------------------------------- 1 | # Overview 2 | This directory contains various x-checks and assertions for the vector datapath units. These have, so far, been only used in simulation and not in any formal verification flow. 3 | -------------------------------------------------------------------------------- /vector_simulator/files_sim.f: -------------------------------------------------------------------------------- 1 | -sv 2 | 3 | ../rtl/shared/main_memory.sv 4 | 5 | ../vector_simulator/decoder_results/autogenerated_params.sv 6 | ../vector_simulator/vector_driver.sv 7 | ../vector_simulator/vector_sim_top.sv -------------------------------------------------------------------------------- /vector_simulator/instrs.csv: -------------------------------------------------------------------------------- 1 | //========================== 2 | // vvadd for 5000 elements 3 | // after copying the instr.csv, run with: 4 | // > python .\sim_generator.py .\instrs.csv 5000 VECTOR_LANES 5 | // where VECTOR_LANES the number of the RTLs vector lanes 6 | //========================== 7 | //load the first array 8 | vld, v0, #0 9 | //load the second array 10 | vld, v1, #2048 11 | //add the result 12 | vadd, v2, v0, v1 -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/instrs.csv: -------------------------------------------------------------------------------- 1 | //========================== 2 | // vvadd for 5000 elements 3 | // after copying the instr.csv, run with: 4 | // > python .\sim_generator.py .\instrs.csv 5000 VECTOR_LANES 5 | // where VECTOR_LANES the number of the RTLs vector lanes 6 | //========================== 7 | //load the first array 8 | vld, v0, #0 9 | //load the second array 10 | vld, v1, #2048 11 | //add the result 12 | vadd, v2, v0, v1 -------------------------------------------------------------------------------- /vector_simulator/compile_vector_simulator.do: -------------------------------------------------------------------------------- 1 | quit -sim 2 | file delete -force work 3 | 4 | vlib work 5 | 6 | #compile the dut code 7 | #set cmd "vlog -F ../dut/files.f +incdir+.../dut/ -lint" 8 | #set cmd "vlog -F files.f +incdir+../rtl/" 9 | #eval $cmd 10 | 11 | vlog -f files_rtl.f -f files_sim.f +incdir+../rtl/shared/ +incdir+../rtl/vector/ +incdir+../sva/ 12 | 13 | vsim -novopt work.vector_sim_top -onfinish "stop" 14 | log -r /* 15 | do wave_simulator.do 16 | onbreak {wave zoom full} 17 | run -all 18 | wave zoom full -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/instrs.csv: -------------------------------------------------------------------------------- 1 | //========================== 2 | // saxpy for 5000 elements 3 | // after copying the instr.csv, run with: 4 | // > python .\sim_generator.py .\instrs.csv 5000 VECTOR_LANES 5 | // where VECTOR_LANES the number of the RTLs vector lanes 6 | //========================== 7 | //load conditions 8 | vld, v1, #0 9 | //load x 10 | vld, v2, #640 11 | //load y 12 | vld, v3, #1280 13 | // compare cond 14 | vseq, v1, v1, v1 15 | // mul a*x 16 | vmul, v4, v3, v3 17 | // add a*x+y 18 | vadd, v4, v4, v2 19 | // store result 20 | vsw, v4, #2560 -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/instrs.csv: -------------------------------------------------------------------------------- 1 | //========================== 2 | // Dot product of 2 arrays with 5000 el 3 | // after copying the instr.csv, run with: 4 | // > python .\sim_generator.py .\instrs.csv 5000 VECTOR_LANES 5 | // where VECTOR_LANES the number of the RTLs vector lanes 6 | //========================== 7 | //v0 holds the total sum -> zero it 8 | vandi, v0, v0, #0 9 | //load the first array 10 | vld, v1, #0 11 | //load the second array 12 | vld, v2, #2048 13 | //calculate their product 14 | vmul, v3, v1, v2 15 | //reduce the result 16 | vradd, v4, v3 17 | //add it to sum 18 | vadd, v4, v0 -------------------------------------------------------------------------------- /vector_simulator/examples/fir/instrs.csv: -------------------------------------------------------------------------------- 1 | //========================== 2 | // FIR filter for 5000 el 3 | // after copying the instr.csv, run with: 4 | // > python .\sim_generator.py .\instrs.csv 5000 VECTOR_LANES 5 | // where VECTOR_LANES the number of the RTLs vector lanes 6 | //========================== 7 | //load third tap (-2) & mul 8 | vld, v2, #8 9 | vslli, v2, v2, #2 10 | //load second tap (-1) & mul 11 | vld, v3, #12 12 | vmul, v3, v3, #3 13 | //------------------------- 14 | //add the first two 15 | vadd, v5, v3, v2 16 | //------------------------- 17 | //load first tap & mul 18 | vld, v4, #16 19 | vmul, v4, v4, #3 20 | //load first tap (-4) 21 | vld, v0, #0 22 | //------------------------- 23 | //add two more 24 | vadd, v6, v4, v0 25 | //------------------------- 26 | //load second tap (-3) 27 | vld, v1, #4 28 | //------------------------- 29 | // add first sum and new vector 30 | vadd, v5, v5, v1 31 | // final addition 32 | vadd, v5, v5, v6 -------------------------------------------------------------------------------- /rtl/vector/vmacros.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * @author VLSI Lab, EE dept., Democritus University of Thrace 4 | * 5 | */ 6 | // FU code definitions 7 | `define MEM_FU 2'b00 8 | `define FP_FU 2'b01 9 | `define INT_FU 2'b10 10 | `define FXP_FU 2'b11 11 | 12 | // Memory Unit definitions 13 | `define LD_BIT 6 14 | 15 | `define MEM_OP_RANGE_HI 5 16 | `define MEM_OP_RANGE_LO 4 17 | 18 | `define MEM_SZ_RANGE_HI 3 19 | `define MEM_SZ_RANGE_LO 2 20 | 21 | `define OP_UNIT_STRIDED 2'b00 22 | `define OP_STRIDED 2'b10 23 | `define OP_INDEXED 2'b11 24 | 25 | `define SZ_8 1 26 | `define SZ_16 2 27 | `define SZ_32 0 28 | 29 | `define RDC_OP_W 2 30 | `define RDC_ADD 2'b00 31 | `define RDC_AND 2'b10 32 | `define RDC_OR 2'b11 33 | `define RDC_XOR 2'b11 34 | 35 | // Forwarding Point definitions 36 | // _F stands for flopped 37 | // non-flopped hurt freq 38 | `define EX1 1 39 | `define EX2 2 40 | `define EX2_F 20 41 | `define EX3 3 42 | `define EX3_F 30 43 | `define EX4 4 44 | `define EX4_F 40 -------------------------------------------------------------------------------- /rtl/shared/lru_two.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info LRU Sub Module 3 | * @info Top-Module: lru.sv 4 | * 5 | * @author VLSI Lab, EE dept., Democritus University of Thrace 6 | * 7 | * @param ENTRIES : The total addressable entries. 8 | * @param INDEX_BITS : The address width 9 | */ 10 | module lru_two #(ENTRIES=256,INDEX_BITS=8) ( 11 | input logic clk , 12 | input logic rst_n , 13 | //Read Port 14 | input logic [INDEX_BITS-1:0] line_selector , 15 | output logic lru_way , 16 | //Update Port 17 | input logic lru_update , 18 | input logic referenced_set 19 | ); 20 | // #Internal Signals# 21 | logic [ENTRIES-1 : 0] Stored_Stats; 22 | 23 | // Push the Output 24 | assign lru_way = Stored_Stats[line_selector]; 25 | 26 | //Update the bookkeeping 27 | always_ff @(posedge clk or negedge rst_n) begin : Update 28 | if(!rst_n) begin 29 | Stored_Stats <= 'b0; 30 | end else begin 31 | if(lru_update) begin 32 | Stored_Stats[line_selector] <= ~referenced_set; 33 | end 34 | end 35 | end 36 | 37 | endmodule -------------------------------------------------------------------------------- /sva/vmu_st_eng_sva.sv: -------------------------------------------------------------------------------- 1 | //======================================================= 2 | // X Checks 3 | //======================================================= 4 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_in)) 5 | else $error("x-check:vmu_st_eng: valid_in"); 6 | 7 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(unlock_en_o)) 8 | else $error("x-check:vmu_st_eng: unlock_en_o"); 9 | 10 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(grant_i)) 11 | else $error("x-check:vmu_st_eng: grant_i"); 12 | //======================================================= 13 | // Properties 14 | //======================================================= 15 | assert property (@(posedge clk) disable iff(!rst_n) DATA_WIDTH == 32) 16 | else $error("vmu_st_eng: Designed only for 32bit data width"); 17 | 18 | assert property (@(posedge clk) disable iff(!rst_n) valid_in |-> nxt_memory_op inside {0, 2, 3}) 19 | else $error("vmu_st_eng: Illegal memory op"); 20 | 21 | assert property (@(posedge clk) disable iff(!rst_n) valid_in |-> nxt_size inside {0, 1, 2}) 22 | else $error("vmu_st_eng: Illegal memory size"); -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | RISC-V^2 Vector processor LICENSE 2 | 3 | Copyright (c) 2019-2020 Integrated Circuits Lab, Democritus University of Thrace, Greece. 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /sva/vex_pipe_sva.sv: -------------------------------------------------------------------------------- 1 | //======================================================= 2 | // X Checks 3 | //======================================================= 4 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_i)) 5 | else $error("x-check:vex_pipe: valid_i"); 6 | assert property (@(posedge clk) disable iff(!rst_n) valid_i |-> ~$isunknown(mask_i)) 7 | else $error("x-check:vex_pipe: mask_i"); 8 | assert property (@(posedge clk) disable iff(!rst_n) valid_i |-> ~$isunknown(microop_i)) 9 | else $error("x-check:vex_pipe: microop_i"); 10 | assert property (@(posedge clk) disable iff(!rst_n) valid_i |-> ~$isunknown(fu_i)) 11 | else $error("x-check:vex_pipe: fu_i"); 12 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(frw_a_en_o)) 13 | else $error("x-check:vex_pipe: frw_a_en_o"); 14 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(frw_b_en_o)) 15 | else $error("x-check:vex_pipe: frw_b_en_o"); 16 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(wr_en_o)) 17 | else $error("x-check:vex_pipe: wr_en_o"); 18 | //======================================================= 19 | // Properties 20 | //======================================================= 21 | -------------------------------------------------------------------------------- /vector_simulator/files_rtl.f: -------------------------------------------------------------------------------- 1 | -sv 2 | 3 | 4 | 5 | ../rtl/shared/params.sv 6 | ../rtl/shared/structs.sv 7 | ../rtl/vector/vmacros.sv 8 | ../rtl/vector/vstructs.sv 9 | 10 | ../rtl/shared/and_or_mux.sv 11 | ../rtl/shared/arbiter.sv 12 | ../rtl/shared/eb_buff_generic.sv 13 | ../rtl/shared/eb_one_slot.sv 14 | ../rtl/shared/eb_two_slot.sv 15 | ../rtl/shared/fifo_dual_ported.sv 16 | ../rtl/shared/fifo_duth.sv 17 | ../rtl/shared/fifo_flush.sv 18 | ../rtl/shared/fifo_overflow.sv 19 | ../rtl/shared/fifo_initialized.sv 20 | ../rtl/shared/lru.sv 21 | ../rtl/shared/lru_two.sv 22 | ../rtl/shared/lru_more.sv 23 | ../rtl/shared/onehot_detect.sv 24 | ../rtl/shared/rr_arbiter.sv 25 | ../rtl/shared/sram.sv 26 | 27 | ../rtl/shared/data_cache.sv 28 | ../rtl/shared/ld_st_buffer.sv 29 | ../rtl/shared/wait_buffer.sv 30 | ../rtl/shared/data_operation.sv 31 | ../rtl/vector/vdata_operation.sv 32 | ../rtl/vector/vld_st_buffer.sv 33 | 34 | ../rtl/vector/vector_top.sv 35 | 36 | ../rtl/vector/vrrm.sv 37 | ../rtl/vector/vrat.sv 38 | 39 | ../rtl/vector/vmu.sv 40 | ../rtl/vector/vmu_st_eng.sv 41 | ../rtl/vector/vmu_ld_eng.sv 42 | ../rtl/vector/vmu_tp_eng.sv 43 | 44 | ../rtl/vector/vis.sv 45 | ../rtl/vector/vrf.sv 46 | 47 | ../rtl/vector/vex.sv 48 | ../rtl/vector/vex_pipe.sv 49 | ../rtl/vector/v_int_alu.sv 50 | ../rtl/vector/v_fp_alu.sv -------------------------------------------------------------------------------- /rtl/shared/and_or_mux.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @info and-or-multiplexer 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | * @brief Multiplexer implemented by an AND-OR tree, selected by at-most-one-hot signal ('sel'). 7 | * All inputs and the output have a width of 'DW'. 8 | * Input data ('data_in') are in bit-blasted form, i.e. input i should be placed in bits [(i+1)*DW-1 : i*DW] 9 | * 10 | * @param INPUTS number of inputs 11 | * @param DW common data width for each input and the output 12 | */ 13 | 14 | module and_or_mux 15 | #( 16 | parameter int INPUTS = 4, 17 | parameter int DW = 16 18 | ) 19 | ( 20 | input logic[INPUTS-1:0][DW-1:0] data_in, 21 | input logic[INPUTS-1:0] sel, 22 | output logic[DW-1:0] data_out 23 | ); 24 | 25 | // version 2, and using variable like operation. 26 | // using 1-bit logic temp exactly as in VHDL. 27 | // When assignments are = (and not <=) in always blocks 28 | // temp signal behaves exactly as a variable in VHDL 29 | logic tmp; 30 | 31 | always_comb begin: mux 32 | for(int w=0; w < DW; w=w+1) begin 33 | tmp = 0; 34 | for(int i=0; i < INPUTS; i=i+1) begin 35 | tmp = tmp | ( sel[i] & data_in[i][w] ); 36 | end 37 | data_out[w] = tmp; 38 | end 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /rtl/shared/lru.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info LRU Top Module 3 | * @info Top-Module: lru_two.sv, lru_more.sv 4 | * 5 | * @author VLSI Lab, EE dept., Democritus University of Thrace 6 | * 7 | * @param ASSOCIATIVITY: The cache assosiativity 8 | * @param ENTRIES : The total addressable entries. 9 | * @param INDEX_BITS : The address width 10 | * @param OUTPUT_BITS : The Output width 11 | */ 12 | module lru #(ASSOCIATIVITY=2,ENTRIES=256,INDEX_BITS=8,OUTPUT_BITS=2) ( 13 | input logic clk , 14 | input logic rst_n , 15 | input logic [ INDEX_BITS-1:0] line_selector , 16 | input logic [OUTPUT_BITS-1:0] referenced_set, 17 | input logic lru_update , 18 | output logic [OUTPUT_BITS-1:0] lru_way 19 | ); 20 | generate 21 | if(ASSOCIATIVITY==2) begin 22 | //instantiate the 2-way LRU module 23 | lru_two #(ENTRIES,INDEX_BITS) 24 | lru_two(.clk (clk), 25 | .rst_n (rst_n), 26 | .line_selector (line_selector), 27 | .referenced_set (referenced_set), 28 | .lru_update (lru_update), 29 | .lru_way (lru_way)); 30 | end else if(ASSOCIATIVITY>2) begin 31 | //instantiate the >2-way LRU module 32 | lru_more #(ASSOCIATIVITY,ENTRIES,INDEX_BITS,OUTPUT_BITS) 33 | lru_more(.clk (clk), 34 | .rst_n (rst_n), 35 | .line_selector (line_selector), 36 | .referenced_set (referenced_set), 37 | .lru_update (lru_update), 38 | .lru_way (lru_way)); 39 | end 40 | endgenerate 41 | 42 | endmodule -------------------------------------------------------------------------------- /rtl/shared/onehot_detect.sv: -------------------------------------------------------------------------------- 1 | 2 | module onehot_detect #(parameter int N = 4) ( 3 | input logic [N-1:0] vec_in , 4 | output logic exactly_one , 5 | output logic more_than_one 6 | ); 7 | 8 | 9 | localparam int NODES = 2**$clog2(N)-1; 10 | localparam int EDGES = 2*NODES + 1 ; //+1: zero'th is output 11 | 12 | logic[EDGES-1:0] h, z, f; 13 | logic[2**$clog2(N)-1:0] vec_in_ext; 14 | 15 | genvar i; 16 | generate 17 | for (i=0; i<2**$clog2(N); i++) begin: for_i 18 | if (i < N) begin 19 | assign vec_in_ext[i] = vec_in[i]; 20 | end else begin 21 | assign vec_in_ext[i] = 1'b0; 22 | end 23 | end 24 | endgenerate 25 | 26 | genvar l; 27 | generate 28 | for (l=0; l= NODES) begin: if_leaf 30 | // Initialize H, Z, F 31 | assign h[l] = vec_in_ext[l-NODES]; 32 | assign z[l] = ~vec_in_ext[l-NODES]; 33 | assign f[l] = 1'b0; 34 | end else begin: if_rest 35 | // check node: 36 | // H = (H_L & Z_R) | (H_R & Z_L) 37 | assign h[l] = ( h[2*l+1] & z[2*l+2] ) | ( h[2*l+2] & z[2*l+1] ); 38 | // Z = Z_L & Z_R 39 | assign z[l] = z[2*l+1] & z[2*l+2]; 40 | // F = F_L | F_R | (H_L & H_R) 41 | assign f[l] = f[2*l+1] | f[2*l+2] | ( h[2*l+1] & h[2*l+2] ); 42 | end 43 | end 44 | endgenerate 45 | assign exactly_one = h[0]; 46 | assign more_than_one = f[0]; 47 | 48 | endmodule -------------------------------------------------------------------------------- /sva/vex_sva.sv: -------------------------------------------------------------------------------- 1 | //======================================================= 2 | // X Checks 3 | //======================================================= 4 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_i)) 5 | else $error("x-check:vex: valid_i"); 6 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|frw_a_en)) 7 | else $error("x-check:vex: frw_a_en"); 8 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|frw_b_en)) 9 | else $error("x-check:vex: frw_b_en"); 10 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|wr_en)) 11 | else $error("x-check:vex: wr_en"); 12 | 13 | generate 14 | for (genvar k = 0; k < VECTOR_LANES; k++) begin 15 | assert property (@(posedge clk) disable iff(!rst_n) frw_a_en[k] |-> ~$isunknown(|frw_a_addr)) 16 | else $error("x-check:vex: frw_a_addr"); 17 | assert property (@(posedge clk) disable iff(!rst_n) frw_a_en[k] |-> ~$isunknown(|frw_a_ticket)) 18 | else $error("x-check:vex: frw_a_ticket"); 19 | assert property (@(posedge clk) disable iff(!rst_n) frw_b_en[k] |-> ~$isunknown(|frw_b_addr)) 20 | else $error("x-check:vex: frw_b_addr"); 21 | assert property (@(posedge clk) disable iff(!rst_n) frw_b_en[k] |-> ~$isunknown(|frw_b_ticket)) 22 | else $error("x-check:vex: frw_b_ticket"); 23 | assert property (@(posedge clk) disable iff(!rst_n) wr_en[k] |-> ~$isunknown(|wr_addr)) 24 | else $error("x-check:vex: wr_addr"); 25 | assert property (@(posedge clk) disable iff(!rst_n) wr_en[k] |-> ~$isunknown(|wr_ticket)) 26 | else $error("x-check:vex: wr_ticket"); 27 | end 28 | endgenerate 29 | //======================================================= 30 | // Properties 31 | //======================================================= 32 | -------------------------------------------------------------------------------- /sva/vrrm_sva.sv: -------------------------------------------------------------------------------- 1 | //======================================================= 2 | // X Checks 3 | //======================================================= 4 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_in)) 5 | else $error("x-check:vrrm: valid_in"); 6 | 7 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(pop_instr)) 8 | else $error("x-check:vrrm: pop_instr"); 9 | 10 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_o)) 11 | else $error("x-check:vrrm: valid_o"); 12 | 13 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(ready_i)) 14 | else $error("x-check:vrrm: ready_i"); 15 | 16 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(m_valid_o)) 17 | else $error("x-check:vrrm: m_valid_o"); 18 | 19 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(m_ready_i)) 20 | else $error("x-check:vrrm: m_ready_i"); 21 | 22 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(do_remap)) 23 | else $error("x-check:vrrm: do_remap"); 24 | 25 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(do_operation)) 26 | else $error("x-check:vrrm: do_operation"); 27 | 28 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(do_reconfigure)) 29 | else $error("x-check:vrrm: do_reconfigure"); 30 | 31 | assert property (@(posedge clk) disable iff(!rst_n | ~valid_in) ~$isunknown(memory_instr)) 32 | else $error("x-check:vrrm: memory_instr"); 33 | //======================================================= 34 | // Properties 35 | //======================================================= 36 | //In the future, an exception could be used to capture this violation. For now assume illegal 37 | assert property (@(posedge clk) disable iff(~rst_n) do_remap |-> (current_remaps < max_remaps)) 38 | else $fatal("Did more remaps than the Max allowed. Use less rdsts or reconfigure"); -------------------------------------------------------------------------------- /sva/vmu_ld_eng_sva.sv: -------------------------------------------------------------------------------- 1 | //======================================================= 2 | // X Checks 3 | //======================================================= 4 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_in)) 5 | else $error("x-check:vmu_ld_eng: valid_in"); 6 | 7 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(wrtbck_en_o)) 8 | else $error("x-check:vmu_ld_eng: wrtbck_en_o"); 9 | 10 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(grant_i)) 11 | else $error("x-check:vmu_ld_eng: grant_i"); 12 | 13 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(wrtbck_req_o)) 14 | else $error("x-check:vmu_ld_eng: wrtbck_req_o"); 15 | 16 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(wrtbck_grant_i)) 17 | else $error("x-check:vmu_ld_eng: wrtbck_grant_i"); 18 | 19 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(resp_valid_i)) 20 | else $error("x-check:vmu_ld_eng: resp_valid_i"); 21 | 22 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(unlock_en_o)) 23 | else $error("x-check:vmu_ld_eng: unlock_en_o"); 24 | 25 | //======================================================= 26 | // Properties 27 | //======================================================= 28 | logic flag_illegal; 29 | always_comb begin 30 | flag_illegal = 0; 31 | for (int i = 0; i < VECTOR_LANES; i++) begin 32 | if(pending_elem[0][i] && !active_elem[0][i]) flag_illegal = 1; 33 | if(pending_elem[1][i] && !active_elem[1][i]) flag_illegal = 1; 34 | end 35 | end 36 | 37 | assert property (@(posedge clk) disable iff(!rst_n) DATA_WIDTH == 32) 38 | else $error("vmu_ld_eng: Designed only for 32bit data width"); 39 | 40 | assert property (@(posedge clk) disable iff(!rst_n) valid_in |-> nxt_memory_op inside {0, 2, 3}) 41 | else $error("vmu_ld_eng: Illegal memory op"); 42 | 43 | assert property (@(posedge clk) disable iff(!rst_n) valid_in |-> nxt_size inside {0, 1, 2}) 44 | else $error("vmu_ld_eng: Illegal memory size"); 45 | 46 | assert property (@(posedge clk) disable iff(!rst_n) !flag_illegal) 47 | else $error("vmu_ld_eng: Illegal state in the tracking"); -------------------------------------------------------------------------------- /sva/vmu_tp_eng_sva.sv: -------------------------------------------------------------------------------- 1 | //======================================================= 2 | // X Checks 3 | //======================================================= 4 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_in)) 5 | else $fatal("x-check:vmu_tp_eng: valid_in"); 6 | 7 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(wrtbck_en_o)) 8 | else $fatal("x-check:vmu_tp_eng: wrtbck_en_o"); 9 | 10 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(grant_i)) 11 | else $fatal("x-check:vmu_tp_eng: grant_i"); 12 | 13 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(wrtbck_req_o)) 14 | else $fatal("x-check:vmu_tp_eng: wrtbck_req_o"); 15 | 16 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(wrtbck_grant_i)) 17 | else $fatal("x-check:vmu_tp_eng: wrtbck_grant_i"); 18 | 19 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(req_en_o)) 20 | else $fatal("x-check:vmu_tp_eng: req_en_o"); 21 | 22 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(resp_valid_i)) 23 | else $fatal("x-check:vmu_tp_eng: resp_valid_i"); 24 | 25 | //======================================================= 26 | // Properties 27 | //======================================================= 28 | 29 | logic flag_illegal; 30 | always_comb begin 31 | flag_illegal = 0; 32 | for (int i = 0; i < VECTOR_LANES; i++) begin 33 | if(pending_elem[0][i] && !active_elem[0][i]) flag_illegal = 1; 34 | if(pending_elem[1][i] && !active_elem[1][i]) flag_illegal = 1; 35 | end 36 | end 37 | 38 | assert property (@(posedge clk) disable iff(!rst_n) !flag_illegal) 39 | else $fatal("vmu_tp_eng: Illegal state in the tracking"); 40 | 41 | assert property (@(posedge clk) disable iff(!rst_n) DATA_WIDTH == 32) 42 | else $fatal("vmu_tp_eng: Designed only for 32bit data width"); 43 | 44 | assert property (@(posedge clk) disable iff(!rst_n) valid_in |-> nxt_size inside {0, 1, 2}) 45 | else $fatal("vmu_tp_eng: Illegal memory size"); 46 | 47 | assert property (@(posedge clk) disable iff(!rst_n) new_transaction_en |-> (nxt_win_col_num <= kernel_size_r)) 48 | else $fatal("vmu_tp_eng: Illegal Scenario"); -------------------------------------------------------------------------------- /rtl/shared/arbiter.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @info Arbiter 3 | * 4 | * Prioritized Arbiter. If the inputted priority points to input i, then the request vector ('request_i') 5 | * is checked in the following order: i->...->N-1->0->...->i-1 6 | * 7 | * 'grant_o' is at-most-one-hot - 'anygnt_o' is the OR-reduced request vector 8 | * 9 | * @param N number of input requestors 10 | */ 11 | 12 | module arbiter 13 | #(parameter int N = 4) 14 | ( 15 | //Inputs 16 | input logic[N-1:0] request_i, 17 | input logic[N-1:0] priority_i, 18 | //Outputs 19 | output logic[N-1:0] grant_o, 20 | output logic anygnt_o); 21 | 22 | localparam int S = $clog2(N); 23 | 24 | // Priority propagate and ganerate signals 25 | logic [N-1:0] g [S:0]; 26 | logic [N-1:0] p [S-1:0]; 27 | 28 | logic [N-1:0] grant_s; 29 | logic valid; 30 | 31 | assign grant_o = grant_s; 32 | 33 | // Parallel prefix round-robin arbitration 34 | 35 | int i,j; 36 | always_comb 37 | begin 38 | // initialize priority propagate 39 | // and generate vectors 40 | p[0][0] = ~request_i[N-1]; 41 | g[0][0] = priority_i[0]; 42 | for(j=1; j < N; j=j+1) 43 | begin 44 | p[0][j] = ~request_i[j-1]; 45 | g[0][j] = priority_i[j]; 46 | end 47 | 48 | // implement first log2n-1 prefix levels 49 | for(i=1; i < S; i=i+1) 50 | for(j=0; j < N; j=j+1) 51 | begin 52 | if ((j-2**(i-1)) < 0) 53 | begin 54 | g[i][j] = g[i-1][j] | ( p[i-1][j] & g[i-1][N+j-2**(i-1)]); 55 | p[i][j] = p[i-1][j] & p[i-1][N+j-2**(i-1)]; 56 | end 57 | else 58 | begin 59 | g[i][j] = g[i-1][j] | ( p[i-1][j] & g[i-1][ j-2**(i-1)]); 60 | p[i][j] = p[i-1][j] & p[i-1][ j-2**(i-1)]; 61 | end 62 | end 63 | 64 | // last prefix level 65 | for(j=0; j < N; j=j+1) 66 | begin 67 | if ((j-2**(S-1)) < 0) 68 | g[S][j] = g[S-1][j] | ( p[S-1][j] & g[S-1][ N+j-2**(S-1)]); 69 | else 70 | g[S][j] = g[S-1][j] | ( p[S-1][j] & g[S-1][ j-2**(S-1)]); 71 | end 72 | 73 | // grant signal generation 74 | for(j=0; j < N; j=j+1) 75 | grant_s[j] = request_i[j] & g[S][j]; 76 | 77 | end 78 | 79 | // Any grant generation at last prefix level 80 | assign valid = ~( p[S-1][N-1] & p[S-1][N/2-1]); 81 | assign anygnt_o = valid; 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /rtl/shared/sram.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info SRAM Module 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | * @brief An SRAM module with parameterized Read and Write Ports. 7 | * Can also be configured to be resetable with initial value==0 8 | * 9 | * @param SIZE : # of addressable entries (lines) in the array 10 | * @param DATA_WIDTH : # of Data Bits 11 | * @param RD_PORTS : # of Read Ports 12 | * @param WR_PORTS : # of Write Ports 13 | * @param RESETABLE : Indicates if the entries will be resetable 14 | */ 15 | module sram 16 | #(SIZE=1024,DATA_WIDTH=8, RD_PORTS=1, WR_PORTS=1, RESETABLE=0) ( 17 | input logic clk , 18 | input logic rst_n , 19 | //Write Port 20 | input logic [WR_PORTS-1:0] Wr_En , 21 | input logic [WR_PORTS-1:0][$clog2(SIZE)-1:0] write_address, 22 | input logic [WR_PORTS-1:0][ DATA_WIDTH-1:0] new_data , 23 | //Read Port 24 | input logic [RD_PORTS-1:0][$clog2(SIZE)-1:0] read_address , 25 | output logic [RD_PORTS-1:0][ DATA_WIDTH-1:0] data_out 26 | ); 27 | 28 | localparam SEL_BITS = $clog2(SIZE); 29 | // #Internal Signals# 30 | logic [SIZE-1:0][DATA_WIDTH-1:0] Memory_Array; 31 | 32 | //Push the Data out 33 | always_comb begin : DataOUT 34 | for (int i = 0; i < RD_PORTS; i++) begin 35 | data_out[i] = Memory_Array[read_address[i]]; 36 | end 37 | end 38 | 39 | generate 40 | if(RESETABLE) begin 41 | //Create Resetable SRAM 42 | always_ff @(posedge clk or negedge rst_n) begin : Update 43 | if(!rst_n) begin 44 | for (int i = 0; i <= SIZE-1; i++) begin 45 | Memory_Array[i]<='d0; 46 | end 47 | end else begin 48 | for (int i = 0; i < WR_PORTS; i++) begin 49 | if (Wr_En[i]) Memory_Array[write_address[i]] <= new_data[i]; 50 | end 51 | end 52 | end 53 | end else begin 54 | //Create Non-Resetable SRAM 55 | always_ff @(posedge clk) begin : Update 56 | for (int i = 0; i < WR_PORTS; i++) begin 57 | if (Wr_En[i]) Memory_Array[write_address[i]] <= new_data[i]; 58 | end 59 | end 60 | end 61 | endgenerate 62 | 63 | 64 | endmodule -------------------------------------------------------------------------------- /rtl/shared/eb_one_slot.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @info eb_one_slot 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | * @brief 1-slot Elastic Buffer (EB) with parameter that determines the implementation in terms of throughput 7 | * and propagation of back-notification path ('ready_out'). 8 | * 9 | * @param FULL_THROUGHPUT Determines the implementation. 10 | * - If set to 0, a Half-Bandwidth EB (HBEB) is generated, where back notification ('ready_out') is deasserted whenever the buffer is full, 11 | * which cannot offer more than 50% throughput 12 | * - If set to 1, a Pipelined EB (PEB) is generated, which supports 100% throughput, but the notification signal is 13 | * send backwards combinationally 14 | * @param DATA_WIDTH data width 15 | * @param GATING_FRIENDLY determines if data are always registered (==0) or only when 'valid_in' is asserted (==1). 16 | */ 17 | 18 | module eb_one_slot 19 | #( 20 | parameter logic FULL_THROUGHPUT = 1'b0, 21 | parameter int DATA_WIDTH = 16, 22 | parameter logic GATING_FRIENDLY = 1'b1 23 | ) 24 | ( 25 | input logic clk, 26 | input logic rst, 27 | // input side 28 | input logic valid_in, 29 | output logic ready_out, 30 | input logic[DATA_WIDTH-1:0] data_in, 31 | 32 | //output side 33 | output logic valid_out, 34 | input logic ready_in, 35 | output logic[DATA_WIDTH-1:0] data_out 36 | ); 37 | // ------------------------------------------------------------------------------------------------ // 38 | logic[DATA_WIDTH-1:0] data_r; 39 | logic full_r; 40 | logic write_en; 41 | // ------------------------------------------------------------------------------------------------ // 42 | assign valid_out = full_r; 43 | assign ready_out = write_en; 44 | assign data_out = data_r; 45 | 46 | // write_en depends on impl. 47 | generate 48 | if (FULL_THROUGHPUT) begin: gen_if_ft 49 | assign write_en = ready_in | ~full_r; 50 | end else begin: gen_if_ht 51 | assign write_en = ~full_r; 52 | end 53 | endgenerate 54 | 55 | // Full reg 56 | always_ff @(posedge clk, posedge rst) begin: ff_full_r 57 | if (rst) begin 58 | full_r <= 0; 59 | end else begin 60 | if (write_en) begin 61 | full_r <= valid_in; 62 | end 63 | end 64 | end 65 | 66 | // data reg 67 | always_ff @(posedge clk) begin: ff_data_r 68 | if (write_en) begin 69 | if (!GATING_FRIENDLY | valid_in) begin 70 | data_r <= data_in; 71 | end 72 | end 73 | end 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /rtl/vector/vrat.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info Vector Register Aliasing Table 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | */ 7 | module vrat #( 8 | parameter int TOTAL_ENTRIES = 32, 9 | parameter int DATA_WIDTH = 4 10 | ) ( 11 | input logic clk , 12 | input logic rst_n , 13 | input logic reconfigure, 14 | //Write Port 15 | input logic [$clog2(TOTAL_ENTRIES)-1:0] write_addr , 16 | input logic [ DATA_WIDTH-1:0] write_data , 17 | input logic write_en , 18 | //Read Port #1 19 | input logic [$clog2(TOTAL_ENTRIES)-1:0] read_addr_1, 20 | output logic [ DATA_WIDTH-1:0] read_data_1, 21 | output logic remapped_1 , 22 | //Read Port #2 23 | input logic [$clog2(TOTAL_ENTRIES)-1:0] read_addr_2, 24 | output logic [ DATA_WIDTH-1:0] read_data_2, 25 | output logic remapped_2 , 26 | //Read Port #3 27 | input logic [$clog2(TOTAL_ENTRIES)-1:0] read_addr_3, 28 | output logic [ DATA_WIDTH-1:0] read_data_3, 29 | output logic remapped_3 , 30 | //Mask Port 31 | output logic [ DATA_WIDTH-1:0] mask_src 32 | ); 33 | localparam ADDR_WIDTH = $clog2(TOTAL_ENTRIES); 34 | 35 | logic [TOTAL_ENTRIES-1:0][DATA_WIDTH-1 : 0] ratMem; 36 | logic [TOTAL_ENTRIES-1:0] remapped; 37 | 38 | //RAT memory storage 39 | always_ff @(posedge clk or negedge rst_n) begin : mem 40 | if(~rst_n) begin 41 | for (int i = 0; i < TOTAL_ENTRIES; i++) begin 42 | ratMem[i] <= i; 43 | end 44 | end else begin 45 | if (reconfigure) begin 46 | ratMem <= 'b0; 47 | end else if(write_en) begin 48 | ratMem[write_addr] <= write_data; 49 | end 50 | end 51 | end 52 | //Register Status Storage (remapped y/n) 53 | always_ff @(posedge clk or negedge rst_n) begin : remap 54 | if(~rst_n) begin 55 | remapped <= 'b1; 56 | end else begin 57 | if (reconfigure) begin 58 | remapped <= 'b0; 59 | end else if(write_en) begin 60 | remapped[write_addr] <= 1'b1; 61 | end 62 | end 63 | end 64 | //Push Data Out 65 | assign read_data_1 = ratMem[read_addr_1]; 66 | assign remapped_1 = remapped[read_addr_1]; 67 | assign read_data_2 = ratMem[read_addr_2]; 68 | assign remapped_2 = remapped[read_addr_2]; 69 | assign read_data_3 = ratMem[read_addr_3]; 70 | assign remapped_3 = remapped[read_addr_3]; 71 | 72 | assign mask_src = ratMem['d1]; 73 | 74 | 75 | endmodule -------------------------------------------------------------------------------- /rtl/shared/eb_buff_generic.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @info fifo_duth 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | * @brief 7 | * 8 | * @param 9 | * @param 10 | */ 11 | 12 | // Set BUFF_TYPE as follows: 13 | // 0: One-slot Half-Bandwidth EB (50% throughput) 14 | // 1: One-slot Full-Bandwidth EB (100% throughput - comb backpressure paths) 15 | // 2: Two-slot Full-Bandwidth EB (100% throughput) 16 | // 3: FIFO (use param DEPTH to set the depth) 17 | module eb_buff_generic 18 | #( 19 | parameter int DW = 32, 20 | parameter int BUFF_TYPE = 2, 21 | parameter int DEPTH = 4 22 | ) 23 | ( 24 | input logic clk, 25 | input logic rst, 26 | // input channel 27 | input logic[DW-1:0] data_i, 28 | input logic valid_i, 29 | output logic ready_o, 30 | // output channel 31 | output logic[DW-1:0] data_o, 32 | output logic valid_o, 33 | input logic ready_i 34 | ); 35 | 36 | generate 37 | if ( (BUFF_TYPE == 0) | (BUFF_TYPE == 1) ) begin: gen_one_slot_eb 38 | eb_one_slot #( 39 | .FULL_THROUGHPUT(BUFF_TYPE == 1), 40 | .DATA_WIDTH (DW ), 41 | .GATING_FRIENDLY(1'b1 ) 42 | ) eb ( 43 | .clk (clk ), 44 | .rst (rst ), 45 | 46 | .valid_in (valid_i), 47 | .ready_out(ready_o), 48 | .data_in (data_i ), 49 | 50 | .valid_out(valid_o), 51 | .ready_in (ready_i), 52 | .data_out (data_o ) 53 | ); 54 | 55 | end else if (BUFF_TYPE == 2) begin: gen_two_slot_eb 56 | eb_two_slot #( 57 | .DATA_WIDTH (DW ), 58 | .GATING_FRIENDLY(1'b1) 59 | ) eb ( 60 | .clk (clk ), 61 | .rst (rst ), 62 | 63 | .valid_in (valid_i), 64 | .ready_out(ready_o), 65 | .data_in (data_i ), 66 | 67 | .valid_out(valid_o), 68 | .ready_in (ready_i), 69 | .data_out (data_o ) 70 | ); 71 | end else begin: gen_fifo 72 | // FIFO has a different interface that is NOT flow-controlled 73 | logic fifo_push; 74 | logic fifo_pop; 75 | 76 | assign fifo_push = valid_i & ready_o; 77 | assign fifo_pop = valid_o & ready_i; 78 | 79 | fifo_duth #( 80 | .DW (DW ), 81 | .DEPTH(DEPTH) 82 | ) fifo ( 83 | .clk (clk ), 84 | .rst (rst ), 85 | 86 | .push_data(data_i ), 87 | .push (fifo_push), 88 | .ready (ready_o ), 89 | 90 | .pop_data (data_o ), 91 | .valid (valid_o ), 92 | .pop (fifo_pop ) 93 | ); 94 | end 95 | endgenerate 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /rtl/shared/fifo_duth.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @info fifo_duth 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | * @brief FIFO circular buffer. Uses an input decoder to store to the proper place and an output MUX to select the proper output data. 7 | * 8 | * @param DW data width 9 | * @param DEPTH number of buffer slots. Note: If 1, leads to 50% throughput, so use @see eb_one_slot with FULL_THROUGHPUT asserted. 10 | */ 11 | 12 | module fifo_duth 13 | #( 14 | parameter int DW = 16, 15 | parameter int DEPTH = 4 16 | ) 17 | ( 18 | input logic clk, 19 | input logic rst, 20 | // input channel 21 | input logic[DW-1:0] push_data, 22 | input logic push, 23 | output logic ready, 24 | // output channel 25 | output logic[DW-1:0] pop_data, 26 | output logic valid, 27 | input logic pop 28 | ); 29 | 30 | logic[DEPTH-1:0][DW-1:0] mem; 31 | logic[DEPTH-1:0] push_pnt; 32 | logic[DEPTH-1:0] pop_pnt; 33 | logic[DEPTH :0] status_cnt; 34 | 35 | assign valid = ~status_cnt[0]; 36 | assign ready = ~status_cnt[DEPTH]; 37 | 38 | //Pointer update (one-hot shifting pointers) 39 | always_ff @ (posedge clk, posedge rst) begin: ff_push_pnt 40 | if (rst) begin 41 | push_pnt <= 1; 42 | end else begin 43 | // push pointer 44 | if (push) begin 45 | push_pnt <= {push_pnt[DEPTH-2:0], push_pnt[DEPTH-1]}; 46 | end 47 | end 48 | end 49 | always_ff @ (posedge clk, posedge rst) begin: ff_pop_pnt 50 | if (rst) begin 51 | pop_pnt <= 1; 52 | end else begin 53 | // pop pointer 54 | if (pop) begin 55 | pop_pnt <= {pop_pnt[DEPTH-2:0], pop_pnt[DEPTH-1]}; 56 | end 57 | end 58 | end 59 | 60 | // Status (occupied slots) Counter 61 | always_ff @ (posedge clk, posedge rst) begin: ff_status_cnt 62 | if (rst) begin 63 | status_cnt <= 1; // status counter onehot coded 64 | end else begin 65 | if (push & ~pop) begin 66 | // shift left status counter (increment) 67 | status_cnt <= { status_cnt[DEPTH-1:0],1'b0 } ; 68 | end else if (~push & pop) begin 69 | // shift right status counter (decrement) 70 | status_cnt <= {1'b0, status_cnt[DEPTH:1] }; 71 | end 72 | end 73 | end 74 | 75 | // data write (push) 76 | // address decoding needed for onehot push pointer 77 | always_ff @ (posedge clk) begin: ff_reg_dec 78 | for (int i=0; i < DEPTH; i++) begin 79 | if ( push & push_pnt[i] ) begin 80 | mem[i] <= push_data; 81 | end 82 | end 83 | end 84 | 85 | and_or_mux 86 | #( 87 | .INPUTS (DEPTH), 88 | .DW (DW) 89 | ) 90 | mux_out 91 | ( 92 | .data_in (mem), 93 | .sel (pop_pnt), 94 | .data_out (pop_data) 95 | ); 96 | 97 | assert property (@(posedge clk) disable iff(rst) push |-> ready) else $fatal(1, "Pushing on full!"); 98 | assert property (@(posedge clk) disable iff(rst) pop |-> valid) else $fatal(1, "Popping on empty!"); 99 | endmodule 100 | -------------------------------------------------------------------------------- /vector_simulator/README.md: -------------------------------------------------------------------------------- 1 | # Overview 2 | This directory contains the testing framework for the vector core. A generation script parses the vector instructions and generates the decoded information that a scalar core would produce. Then, the vector driver compiles this information and drives it to the vector datapath. 3 | 4 | The top file of the testbench is the `vector_sim_top.sv`. It instantiates the full vector core with the vector driver connected to it. It also includes some extra functionality, such as deadlock detection and performance printing on the test completion. 5 | 6 | The top file of the tb driver is the `vector_driver.sv`. Internally it stores the instructions in program order by maintaining their decoded information in fifos. Each fifo has a different control information, that would have been generated by the decoders in the scalar pipeline. All this information is pieced together and pushed to the vector core via a ready/valid protocol. On top of that, the fifos can contain special encodings to trigger extra functionality. The main usage of this is to insert bubble cycles, where the scalar core would not push any vector instructions. This can happen on the end of vector loops, where the scalar core would execute some scalar code to determine if the computation has finished, and if not, update pointers and branch. During that time no vector instructions would/are pushed in the vector core. The fifos are populated reading memory files generated by an emulation script. 7 | 8 | The emulation script is the `sim_generator.py`. It reads the vector instructions in a pseudo-assembly notation from a *.csv*, takes as a parameter the pipeline size and the application vector length (_AVL_) and computes the scalar decoder's outputs. For example, for a 1-lane pipeline, with application vector length == 10, and no hardware loop unrolling, the script would generate 10 loops, each containing the decoded information from the vector instructions, with bubble cycles between each loop emualating the control cycles of the scalar core. The output is stored in the `/decoder_results` directory, from where the testbench will read them. 9 | 10 | _**Script Parameters:**_ 11 | - *parameter 1*: csv file path/name 12 | - *parameter 2*: total elements to be processed (AVL) 13 | - *parameter 3*: available vector lanes 14 | 15 | ``` 16 | python .\sim_generator.py .\instrs.csv AVL VECTOR_LANES 17 | ``` 18 | 19 | The number of the bubble cycles added for each loop iteration can be configured using the `TOTAL_BUBBLE_CYCLES` parameter inside the script. To extract meaningful performance metrics, the number of bubble cycles has to match the number of scalar instructions that the vector loop would normally use. 20 | 21 | For example, to run the **vvadd** test from the provided examples: 22 | - copy the `/vector_simulator/examples/vvadd/instrs.csv` file into the `/vector_simulator` directory 23 | - run the generator: `python .\sim_generator.py .\instrs.csv 5000 8` 24 | - open Questasim and navigate into the `/vector_simulator` directory 25 | - execute `do compile_vector_simulator.do` in Questasim. The RTL will be built, the simulation will run and a pre-loaded waveform will be loaded at the end of the simulation. Some performance metrics will be saved in `/vector_simulator/perf_results/results.log` 26 | -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/reconfigure_output.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 0 3 | 0 4 | 0 5 | 1 6 | 1 7 | 1 8 | 1 9 | 0 10 | 0 11 | 0 12 | 1 13 | 1 14 | 1 15 | 1 16 | 0 17 | 0 18 | 0 19 | 1 20 | 1 21 | 1 22 | 1 23 | 0 24 | 0 25 | 0 26 | 1 27 | 1 28 | 1 29 | 1 30 | 0 31 | 0 32 | 0 33 | 1 34 | 1 35 | 1 36 | 1 37 | 0 38 | 0 39 | 0 40 | 1 41 | 1 42 | 1 43 | 1 44 | 0 45 | 0 46 | 0 47 | 1 48 | 1 49 | 1 50 | 1 51 | 0 52 | 0 53 | 0 54 | 1 55 | 1 56 | 1 57 | 1 58 | 0 59 | 0 60 | 0 61 | 1 62 | 1 63 | 1 64 | 1 65 | 0 66 | 0 67 | 0 68 | 1 69 | 1 70 | 1 71 | 1 72 | 0 73 | 0 74 | 0 75 | 1 76 | 1 77 | 1 78 | 1 79 | 0 80 | 0 81 | 0 82 | 1 83 | 1 84 | 1 85 | 1 86 | 0 87 | 0 88 | 0 89 | 1 90 | 1 91 | 1 92 | 1 93 | 0 94 | 0 95 | 0 96 | 1 97 | 1 98 | 1 99 | 1 100 | 0 101 | 0 102 | 0 103 | 1 104 | 1 105 | 1 106 | 1 107 | 0 108 | 0 109 | 0 110 | 1 111 | 1 112 | 1 113 | 1 114 | 0 115 | 0 116 | 0 117 | 1 118 | 1 119 | 1 120 | 1 121 | 0 122 | 0 123 | 0 124 | 1 125 | 1 126 | 1 127 | 1 128 | 0 129 | 0 130 | 0 131 | 1 132 | 1 133 | 1 134 | 1 135 | 0 136 | 0 137 | 0 138 | 1 139 | 1 140 | 1 141 | 1 142 | 0 143 | 0 144 | 0 145 | 1 146 | 1 147 | 1 148 | 1 149 | 0 150 | 0 151 | 0 152 | 1 153 | 1 154 | 1 155 | 1 156 | 0 157 | 0 158 | 0 159 | 1 160 | 1 161 | 1 162 | 1 163 | 0 164 | 0 165 | 0 166 | 1 167 | 1 168 | 1 169 | 1 170 | 0 171 | 0 172 | 0 173 | 1 174 | 1 175 | 1 176 | 1 177 | 0 178 | 0 179 | 0 180 | 1 181 | 1 182 | 1 183 | 1 184 | 0 185 | 0 186 | 0 187 | 1 188 | 1 189 | 1 190 | 1 191 | 0 192 | 0 193 | 0 194 | 1 195 | 1 196 | 1 197 | 1 198 | 0 199 | 0 200 | 0 201 | 1 202 | 1 203 | 1 204 | 1 205 | 0 206 | 0 207 | 0 208 | 1 209 | 1 210 | 1 211 | 1 212 | 0 213 | 0 214 | 0 215 | 1 216 | 1 217 | 1 218 | 1 219 | 0 220 | 0 221 | 0 222 | 1 223 | 1 224 | 1 225 | 1 226 | 0 227 | 0 228 | 0 229 | 1 230 | 1 231 | 1 232 | 1 233 | 0 234 | 0 235 | 0 236 | 1 237 | 1 238 | 1 239 | 1 240 | 0 241 | 0 242 | 0 243 | 1 244 | 1 245 | 1 246 | 1 247 | 0 248 | 0 249 | 0 250 | 1 251 | 1 252 | 1 253 | 1 254 | 0 255 | 0 256 | 0 257 | 1 258 | 1 259 | 1 260 | 1 261 | 0 262 | 0 263 | 0 264 | 1 265 | 1 266 | 1 267 | 1 268 | 0 269 | 0 270 | 0 271 | 1 272 | 1 273 | 1 274 | 1 275 | 0 276 | 0 277 | 0 278 | 1 279 | 1 280 | 1 281 | 1 282 | 0 283 | 0 284 | 0 285 | 1 286 | 1 287 | 1 288 | 1 289 | 0 290 | 0 291 | 0 292 | 1 293 | 1 294 | 1 295 | 1 296 | 0 297 | 0 298 | 0 299 | 1 300 | 1 301 | 1 302 | 1 303 | 0 304 | 0 305 | 0 306 | 1 307 | 1 308 | 1 309 | 1 310 | 0 311 | 0 312 | 0 313 | 1 314 | 1 315 | 1 316 | 1 317 | 0 318 | 0 319 | 0 320 | 1 321 | 1 322 | 1 323 | 1 324 | 0 325 | 0 326 | 0 327 | 1 328 | 1 329 | 1 330 | 1 331 | 0 332 | 0 333 | 0 334 | 1 335 | 1 336 | 1 337 | 1 338 | 0 339 | 0 340 | 0 341 | 1 342 | 1 343 | 1 344 | 1 345 | 0 346 | 0 347 | 0 348 | 1 349 | 1 350 | 1 351 | 1 352 | 0 353 | 0 354 | 0 355 | 1 356 | 1 357 | 1 358 | 1 359 | 0 360 | 0 361 | 0 362 | 1 363 | 1 364 | 1 365 | 1 366 | 0 367 | 0 368 | 0 369 | 1 370 | 1 371 | 1 372 | 1 373 | 0 374 | 0 375 | 0 376 | 1 377 | 1 378 | 1 379 | 1 380 | 0 381 | 0 382 | 0 383 | 1 384 | 1 385 | 1 386 | 1 387 | 0 388 | 0 389 | 0 390 | 1 391 | 1 392 | 1 393 | 1 394 | 0 395 | 0 396 | 0 397 | 1 398 | 1 399 | 1 400 | 1 401 | 0 402 | 0 403 | 0 404 | 1 405 | 1 406 | 1 407 | 1 408 | 0 409 | 0 410 | 0 411 | 1 412 | 1 413 | 1 414 | 1 415 | 0 416 | 0 417 | 0 418 | 1 419 | 1 420 | 1 421 | 1 422 | 0 423 | 0 424 | 0 425 | 1 426 | 1 427 | 1 428 | 1 429 | 0 430 | 0 431 | 0 432 | 1 433 | 1 434 | 1 435 | 1 436 | 0 437 | 0 438 | 0 439 | 1 440 | 1 441 | 1 442 | 1 443 | -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/reconfigure_output.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 0 3 | 0 4 | 0 5 | 1 6 | 1 7 | 1 8 | 1 9 | 0 10 | 0 11 | 0 12 | 1 13 | 1 14 | 1 15 | 1 16 | 0 17 | 0 18 | 0 19 | 1 20 | 1 21 | 1 22 | 1 23 | 0 24 | 0 25 | 0 26 | 1 27 | 1 28 | 1 29 | 1 30 | 0 31 | 0 32 | 0 33 | 1 34 | 1 35 | 1 36 | 1 37 | 0 38 | 0 39 | 0 40 | 1 41 | 1 42 | 1 43 | 1 44 | 0 45 | 0 46 | 0 47 | 1 48 | 1 49 | 1 50 | 1 51 | 0 52 | 0 53 | 0 54 | 1 55 | 1 56 | 1 57 | 1 58 | 0 59 | 0 60 | 0 61 | 1 62 | 1 63 | 1 64 | 1 65 | 0 66 | 0 67 | 0 68 | 1 69 | 1 70 | 1 71 | 1 72 | 0 73 | 0 74 | 0 75 | 1 76 | 1 77 | 1 78 | 1 79 | 0 80 | 0 81 | 0 82 | 1 83 | 1 84 | 1 85 | 1 86 | 0 87 | 0 88 | 0 89 | 1 90 | 1 91 | 1 92 | 1 93 | 0 94 | 0 95 | 0 96 | 1 97 | 1 98 | 1 99 | 1 100 | 0 101 | 0 102 | 0 103 | 1 104 | 1 105 | 1 106 | 1 107 | 0 108 | 0 109 | 0 110 | 1 111 | 1 112 | 1 113 | 1 114 | 0 115 | 0 116 | 0 117 | 1 118 | 1 119 | 1 120 | 1 121 | 0 122 | 0 123 | 0 124 | 1 125 | 1 126 | 1 127 | 1 128 | 0 129 | 0 130 | 0 131 | 1 132 | 1 133 | 1 134 | 1 135 | 0 136 | 0 137 | 0 138 | 1 139 | 1 140 | 1 141 | 1 142 | 0 143 | 0 144 | 0 145 | 1 146 | 1 147 | 1 148 | 1 149 | 0 150 | 0 151 | 0 152 | 1 153 | 1 154 | 1 155 | 1 156 | 0 157 | 0 158 | 0 159 | 1 160 | 1 161 | 1 162 | 1 163 | 0 164 | 0 165 | 0 166 | 1 167 | 1 168 | 1 169 | 1 170 | 0 171 | 0 172 | 0 173 | 1 174 | 1 175 | 1 176 | 1 177 | 0 178 | 0 179 | 0 180 | 1 181 | 1 182 | 1 183 | 1 184 | 0 185 | 0 186 | 0 187 | 1 188 | 1 189 | 1 190 | 1 191 | 0 192 | 0 193 | 0 194 | 1 195 | 1 196 | 1 197 | 1 198 | 0 199 | 0 200 | 0 201 | 1 202 | 1 203 | 1 204 | 1 205 | 0 206 | 0 207 | 0 208 | 1 209 | 1 210 | 1 211 | 1 212 | 0 213 | 0 214 | 0 215 | 1 216 | 1 217 | 1 218 | 1 219 | 0 220 | 0 221 | 0 222 | 1 223 | 1 224 | 1 225 | 1 226 | 0 227 | 0 228 | 0 229 | 1 230 | 1 231 | 1 232 | 1 233 | 0 234 | 0 235 | 0 236 | 1 237 | 1 238 | 1 239 | 1 240 | 0 241 | 0 242 | 0 243 | 1 244 | 1 245 | 1 246 | 1 247 | 0 248 | 0 249 | 0 250 | 1 251 | 1 252 | 1 253 | 1 254 | 0 255 | 0 256 | 0 257 | 1 258 | 1 259 | 1 260 | 1 261 | 0 262 | 0 263 | 0 264 | 1 265 | 1 266 | 1 267 | 1 268 | 0 269 | 0 270 | 0 271 | 1 272 | 1 273 | 1 274 | 1 275 | 0 276 | 0 277 | 0 278 | 1 279 | 1 280 | 1 281 | 1 282 | 0 283 | 0 284 | 0 285 | 1 286 | 1 287 | 1 288 | 1 289 | 0 290 | 0 291 | 0 292 | 1 293 | 1 294 | 1 295 | 1 296 | 0 297 | 0 298 | 0 299 | 1 300 | 1 301 | 1 302 | 1 303 | 0 304 | 0 305 | 0 306 | 1 307 | 1 308 | 1 309 | 1 310 | 0 311 | 0 312 | 0 313 | 1 314 | 1 315 | 1 316 | 1 317 | 0 318 | 0 319 | 0 320 | 1 321 | 1 322 | 1 323 | 1 324 | 0 325 | 0 326 | 0 327 | 1 328 | 1 329 | 1 330 | 1 331 | 0 332 | 0 333 | 0 334 | 1 335 | 1 336 | 1 337 | 1 338 | 0 339 | 0 340 | 0 341 | 1 342 | 1 343 | 1 344 | 1 345 | 0 346 | 0 347 | 0 348 | 1 349 | 1 350 | 1 351 | 1 352 | 0 353 | 0 354 | 0 355 | 1 356 | 1 357 | 1 358 | 1 359 | 0 360 | 0 361 | 0 362 | 1 363 | 1 364 | 1 365 | 1 366 | 0 367 | 0 368 | 0 369 | 1 370 | 1 371 | 1 372 | 1 373 | 0 374 | 0 375 | 0 376 | 1 377 | 1 378 | 1 379 | 1 380 | 0 381 | 0 382 | 0 383 | 1 384 | 1 385 | 1 386 | 1 387 | 0 388 | 0 389 | 0 390 | 1 391 | 1 392 | 1 393 | 1 394 | 0 395 | 0 396 | 0 397 | 1 398 | 1 399 | 1 400 | 1 401 | 0 402 | 0 403 | 0 404 | 1 405 | 1 406 | 1 407 | 1 408 | 0 409 | 0 410 | 0 411 | 1 412 | 1 413 | 1 414 | 1 415 | 0 416 | 0 417 | 0 418 | 1 419 | 1 420 | 1 421 | 1 422 | 0 423 | 0 424 | 0 425 | 1 426 | 1 427 | 1 428 | 1 429 | 0 430 | 0 431 | 0 432 | 1 433 | 1 434 | 1 435 | 1 436 | 0 437 | 0 438 | 0 439 | 1 440 | 1 441 | 1 442 | 1 443 | -------------------------------------------------------------------------------- /rtl/shared/fifo_flush.sv: -------------------------------------------------------------------------------- 1 | /** 2 | *@info fifo_flush 3 | *@info Sub-Modules: and_or_mux.sv 4 | * 5 | * 6 | * @brief FIFO circular buffer. Uses an input decoder to store to the proper place and an output MUX to select the proper output data. 7 | * Accepts a flush signal, to empty the whole fifo 8 | * 9 | * @param DW data width 10 | * @param DEPTH number of buffer slots. Note: If 1, leads to 50% throughput, so use @see eb_one_slot with FULL_THROUGHPUT asserted. 11 | */ 12 | 13 | module fifo_flush #( 14 | parameter int DW = 16, 15 | parameter int DEPTH = 4 16 | ) ( 17 | input logic clk , 18 | input logic rst , 19 | //flush channel 20 | input logic flush , 21 | //input channel 22 | input logic [DW-1:0] push_data, 23 | input logic push , 24 | output logic ready , 25 | //output channel 26 | output logic [DW-1:0] pop_data , 27 | output logic valid , 28 | input logic pop 29 | ); 30 | 31 | logic[DEPTH-1:0][DW-1:0] mem; 32 | logic[DEPTH-1:0] push_pnt; 33 | logic[DEPTH-1:0] pop_pnt; 34 | logic[DEPTH :0] status_cnt; 35 | 36 | assign valid = ~status_cnt[0]; 37 | assign ready = ~status_cnt[DEPTH]; 38 | 39 | //Pointer update (one-hot shifting pointers) 40 | always_ff @ (posedge clk, posedge rst) begin: ff_push_pnt 41 | if (rst) begin 42 | push_pnt <= 1; 43 | end else begin 44 | // push pointer 45 | if (flush) begin 46 | push_pnt <= 1; 47 | end else if (push) begin 48 | push_pnt <= {push_pnt[DEPTH-2:0], push_pnt[DEPTH-1]}; 49 | end 50 | end 51 | end 52 | always_ff @ (posedge clk, posedge rst) begin: ff_pop_pnt 53 | if (rst) begin 54 | pop_pnt <= 1; 55 | end else begin 56 | // pop pointer 57 | if (flush) begin 58 | pop_pnt <= 1; 59 | end else if (pop) begin 60 | pop_pnt <= {pop_pnt[DEPTH-2:0], pop_pnt[DEPTH-1]}; 61 | end 62 | end 63 | end 64 | 65 | // Status (occupied slots) Counter 66 | always_ff @ (posedge clk, posedge rst) begin: ff_status_cnt 67 | if (rst) begin 68 | status_cnt <= 1; // status counter onehot coded 69 | end else begin 70 | if (flush) begin 71 | status_cnt <= 1; 72 | end else if (push & ~pop) begin 73 | // shift left status counter (increment) 74 | status_cnt <= { status_cnt[DEPTH-1:0],1'b0 } ; 75 | end else if (~push & pop) begin 76 | // shift right status counter (decrement) 77 | status_cnt <= {1'b0, status_cnt[DEPTH:1] }; 78 | end 79 | end 80 | end 81 | 82 | // data write (push) 83 | // address decoding needed for onehot push pointer 84 | always_ff @ (posedge clk) begin: ff_reg_dec 85 | for (int i=0; i < DEPTH; i++) begin 86 | if ( push & push_pnt[i] ) begin 87 | mem[i] <= push_data; 88 | end 89 | end 90 | end 91 | 92 | and_or_mux 93 | #( 94 | .INPUTS (DEPTH), 95 | .DW (DW) 96 | ) 97 | mux_out 98 | ( 99 | .data_in (mem), 100 | .sel (pop_pnt), 101 | .data_out (pop_data) 102 | ); 103 | 104 | assert property (@(posedge clk) disable iff(rst) push |-> ready) else $fatal(1, "Pushing on full!"); 105 | assert property (@(posedge clk) disable iff(rst) pop |-> valid) else $fatal(1, "Popping on empty!"); 106 | endmodule 107 | -------------------------------------------------------------------------------- /rtl/shared/fifo_initialized.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @info fifo_duth 3 | * @info Sub-Modules: and_or_mux.sv 4 | * 5 | * @author VLSI Lab, EE dept., Democritus University of Thrace 6 | * 7 | * @brief FIFO circular buffer. Uses an input decoder to store to the proper place and an output MUX to select the proper output data. 8 | * Each Entry is initialized with a value equal to its id 9 | * 10 | * @param DW data width 11 | * @param DEPTH number of buffer slots. Note: If 1, leads to 50% throughput, so use @see eb_one_slot with FULL_THROUGHPUT asserted. 12 | */ 13 | 14 | module fifo_initialized 15 | #( 16 | parameter int DW = 16, 17 | parameter int DEPTH = 4 18 | ) 19 | ( 20 | input logic clk, 21 | input logic rst, 22 | // input channel 23 | input logic[DW-1:0] push_data, 24 | input logic push, 25 | output logic ready, 26 | // output channel 27 | output logic[DW-1:0] pop_data, 28 | output logic valid, 29 | input logic pop 30 | ); 31 | 32 | logic[DEPTH-1:0][DW-1:0] mem; 33 | logic[DEPTH-1:0] push_pnt; 34 | logic[DEPTH-1:0] pop_pnt; 35 | logic[DEPTH :0] status_cnt; 36 | 37 | assign valid = ~status_cnt[0]; 38 | assign ready = ~status_cnt[DEPTH]; 39 | 40 | //Pointer update (one-hot shifting pointers) 41 | always_ff @ (posedge clk, posedge rst) begin: ff_push_pnt 42 | if (rst) begin 43 | push_pnt <= 1 << DEPTH; 44 | end else begin 45 | // push pointer 46 | if (push) begin 47 | push_pnt <= {push_pnt[DEPTH-2:0], push_pnt[DEPTH-1]}; 48 | end 49 | end 50 | end 51 | always_ff @ (posedge clk, posedge rst) begin: ff_pop_pnt 52 | if (rst) begin 53 | pop_pnt <= 1; 54 | end else begin 55 | // pop pointer 56 | if (pop) begin 57 | pop_pnt <= {pop_pnt[DEPTH-2:0], pop_pnt[DEPTH-1]}; 58 | end 59 | end 60 | end 61 | 62 | // Status (occupied slots) Counter 63 | always_ff @ (posedge clk, posedge rst) begin: ff_status_cnt 64 | if (rst) begin 65 | status_cnt <= 1 << DEPTH; // status counter onehot coded 66 | end else begin 67 | if (push & ~pop) begin 68 | // shift left status counter (increment) 69 | status_cnt <= { status_cnt[DEPTH-1:0],1'b0 } ; 70 | end else if (~push & pop) begin 71 | // shift right status counter (decrement) 72 | status_cnt <= {1'b0, status_cnt[DEPTH:1] }; 73 | end 74 | end 75 | end 76 | 77 | // data write (push) 78 | // address decoding needed for onehot push pointer 79 | always_ff @ (posedge clk or posedge rst) begin: ff_reg_dec 80 | if (rst) begin 81 | for (int i = 0; i < DEPTH; i++) begin 82 | mem[i] <= i; 83 | end 84 | end else begin 85 | for (int i=0; i < DEPTH; i++) begin 86 | if ( push & push_pnt[i] ) begin 87 | mem[i] <= push_data; 88 | end 89 | end 90 | end 91 | end 92 | 93 | and_or_mux 94 | #( 95 | .INPUTS (DEPTH), 96 | .DW (DW) 97 | ) 98 | mux_out 99 | ( 100 | .data_in (mem), 101 | .sel (pop_pnt), 102 | .data_out (pop_data) 103 | ); 104 | 105 | assert property (@(posedge clk) disable iff(rst) push |-> ready) else $fatal(1, "Pushing on full!"); 106 | assert property (@(posedge clk) disable iff(rst) pop |-> valid) else $fatal(1, "Popping on empty!"); 107 | endmodule 108 | -------------------------------------------------------------------------------- /rtl/shared/fifo_overflow.sv: -------------------------------------------------------------------------------- 1 | /** 2 | *@info fifo_overflow 3 | *@info Sub-Modules: and_or_mux.sv 4 | * 5 | * 6 | * @brief FIFO circular buffer. Uses an input decoder to store to the proper place and an output MUX to select the proper output data. 7 | * Accepts a flush signal, to empty the whole fifo 8 | * 9 | * @param DW data width 10 | * @param DEPTH number of buffer slots. Note: If 1, leads to 50% throughput, so use @see eb_one_slot with FULL_THROUGHPUT asserted. 11 | */ 12 | 13 | module fifo_overflow 14 | #( 15 | parameter int DW = 16, 16 | parameter int DEPTH = 4 17 | ) 18 | ( 19 | input logic clk, 20 | input logic rst, 21 | //flush channel 22 | input logic flush , 23 | // input channel 24 | input logic[DW-1:0] push_data, 25 | input logic push, 26 | // output channel 27 | output logic[DW-1:0] pop_data, 28 | output logic valid, 29 | input logic pop 30 | ); 31 | 32 | logic[DEPTH-1:0][DW-1:0] mem; 33 | logic[DEPTH-1:0] push_pnt; 34 | logic[DEPTH-1:0] pop_pnt; 35 | logic[DEPTH :0] status_cnt; 36 | 37 | assign valid = ~status_cnt[0]; 38 | 39 | //Pointer update (one-hot shifting pointers) 40 | always_ff @ (posedge clk, posedge rst) begin: ff_push_pnt 41 | if (rst) begin 42 | push_pnt <= 1; 43 | end else begin 44 | // push pointer 45 | if(flush) begin 46 | push_pnt <= 1; 47 | end else if (push) begin 48 | push_pnt <= {push_pnt[DEPTH-2:0], push_pnt[DEPTH-1]}; 49 | end 50 | end 51 | end 52 | always_ff @ (posedge clk, posedge rst) begin: ff_pop_pnt 53 | if (rst) begin 54 | pop_pnt <= 1; 55 | end else begin 56 | // pop pointer 57 | if(flush) begin 58 | pop_pnt <= 1; 59 | end else if(push & status_cnt[DEPTH-1]) begin 60 | pop_pnt <= {pop_pnt[DEPTH-2:0], pop_pnt[DEPTH-1]}; 61 | end else if (pop) begin 62 | pop_pnt <= {pop_pnt[DEPTH-2:0], pop_pnt[DEPTH-1]}; 63 | end 64 | end 65 | end 66 | 67 | // Status (occupied slots) Counter 68 | always_ff @ (posedge clk, posedge rst) begin: ff_status_cnt 69 | if (rst) begin 70 | status_cnt <= 1; // status counter onehot coded 71 | end else begin 72 | if(flush) begin 73 | status_cnt <= 1; 74 | end else if (push & ~pop) begin 75 | // shift left status counter (increment) 76 | if(!status_cnt[DEPTH-1]) begin 77 | status_cnt <= { status_cnt[DEPTH-1:0],1'b0 } ; 78 | end 79 | end else if (~push & pop) begin 80 | // shift right status counter (decrement) 81 | status_cnt <= {1'b0, status_cnt[DEPTH:1] }; 82 | end 83 | end 84 | end 85 | 86 | // data write (push) 87 | // address decoding needed for onehot push pointer 88 | always_ff @ (posedge clk) begin: ff_reg_dec 89 | for (int i=0; i < DEPTH; i++) begin 90 | if ( push & push_pnt[i] ) begin 91 | mem[i] <= push_data; 92 | end 93 | end 94 | end 95 | 96 | and_or_mux 97 | #( 98 | .INPUTS (DEPTH), 99 | .DW (DW) 100 | ) 101 | mux_out 102 | ( 103 | .data_in (mem), 104 | .sel (pop_pnt), 105 | .data_out (pop_data) 106 | ); 107 | 108 | assert property (@(posedge clk) disable iff(rst) pop |-> valid) else $fatal(1, "Popping on empty!"); 109 | endmodule 110 | -------------------------------------------------------------------------------- /rtl/vector/vrf.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info Vector Register File 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | */ 7 | module vrf #( 8 | parameter int VREGS = 32, 9 | parameter int ELEMENTS = 4 , 10 | parameter int DATA_WIDTH = 32 11 | ) ( 12 | input logic clk , 13 | input logic reset , 14 | //Element Read Ports 15 | input logic [ $clog2(VREGS)-1:0] rd_addr_1 , 16 | output logic [ ELEMENTS-1:0][DATA_WIDTH-1:0] data_out_1 , 17 | input logic [ $clog2(VREGS)-1:0] rd_addr_2 , 18 | output logic [ ELEMENTS-1:0][DATA_WIDTH-1:0] data_out_2 , 19 | input logic [ $clog2(VREGS)-1:0] mask_src , 20 | output logic [ ELEMENTS-1:0] mask , 21 | //Element Write Ports 22 | input logic [ ELEMENTS-1:0] el_wr_en , 23 | input logic [ $clog2(VREGS)-1:0] el_wr_addr , 24 | input logic [ ELEMENTS-1:0][DATA_WIDTH-1:0] el_wr_data , 25 | //Register Read Port 26 | input logic [ $clog2(VREGS)-1:0] v_rd_addr_0 , 27 | output logic [ELEMENTS*DATA_WIDTH-1:0] v_data_out_0, 28 | input logic [ $clog2(VREGS)-1:0] v_rd_addr_1 , 29 | output logic [ELEMENTS*DATA_WIDTH-1:0] v_data_out_1, 30 | input logic [ $clog2(VREGS)-1:0] v_rd_addr_2 , 31 | output logic [ELEMENTS*DATA_WIDTH-1:0] v_data_out_2, 32 | //Register Write Port 33 | input logic [ ELEMENTS-1:0] v_wr_en , 34 | input logic [ $clog2(VREGS)-1:0] v_wr_addr , 35 | input logic [ELEMENTS*DATA_WIDTH-1:0] v_wr_data 36 | ); 37 | 38 | //Internal Signals 39 | logic [VREGS-1:0][ELEMENTS-1:0][DATA_WIDTH-1:0] memory ; 40 | logic [VREGS-1:0] wr_addr_oh ; 41 | logic [VREGS-1:0] v_wr_addr_oh; 42 | // Convert to one-hot 43 | assign v_wr_addr_oh = (1 << v_wr_addr); 44 | assign wr_addr_oh = (1 << el_wr_addr); 45 | //Store new Data 46 | always_ff @(posedge clk) begin : memManage 47 | if(reset) begin 48 | for (int k = 0; k < ELEMENTS; k++) begin 49 | for (int i = 0; i < VREGS; i++) begin 50 | memory[i][k] <= 'h0; 51 | end 52 | end 53 | end else begin 54 | for (int k = 0; k < ELEMENTS; k++) begin 55 | for (int i = 0; i < VREGS; i++) begin 56 | if(v_wr_addr_oh[i] && v_wr_en[k]) begin 57 | memory[i][k] <= v_wr_data[k*DATA_WIDTH +: DATA_WIDTH]; 58 | end else if(wr_addr_oh[i] && el_wr_en[k]) begin 59 | memory[i][k] <= el_wr_data[k]; 60 | end 61 | end 62 | end 63 | end 64 | end 65 | // Pick the Data and push them to the Output 66 | assign v_data_out_0 = memory[v_rd_addr_0]; 67 | assign v_data_out_1 = memory[v_rd_addr_1]; 68 | assign v_data_out_2 = memory[v_rd_addr_2]; 69 | always_comb begin : DataOut 70 | for (int i = 0; i < ELEMENTS; i++) begin 71 | data_out_1[i] = memory[rd_addr_1][i]; 72 | data_out_2[i] = memory[rd_addr_2][i]; 73 | mask[i] = memory[mask_src][i][0]; 74 | end 75 | end 76 | 77 | endmodule -------------------------------------------------------------------------------- /rtl/vector/vdata_operation.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info Data Operation Sub-Module 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | * @brief Used in the Data Cache, a provided microop picks the operation that will be used 7 | * 8 | * @param ADDR_W : # of Address Bits 9 | * @param DATA_W : # of Data Bits 10 | * @param MICROOP_W : # of Microoperation Bits 11 | * @param BLOCK_W : # of Cache Block Bits 12 | * @param LOAD_ONLY : Instatiates the block only with the load operations 13 | */ 14 | module vdata_operation #( 15 | parameter ADDR_W = 5 , 16 | parameter DATA_W = 256, 17 | parameter MICROOP_W = 7 , 18 | parameter SIZE_W = 6 , 19 | parameter BLOCK_W = 256 20 | ) ( 21 | input logic clk , 22 | input logic valid_i , 23 | //Inputs 24 | input logic [ ADDR_W-1:0] input_address, 25 | input logic [2*BLOCK_W-1:0] input_block , 26 | input logic [ DATA_W-1:0] input_data , 27 | input logic [MICROOP_W-1:0] microop , 28 | input logic [ SIZE_W-1:0] size , 29 | //Outputs 30 | output logic valid_exc , 31 | output logic [ 3:0] exception , 32 | output logic [2*BLOCK_W-1:0] output_block , 33 | output logic [ DATA_W-1:0] output_vector 34 | ); 35 | 36 | // #Internal Signals# 37 | logic [ ADDR_W+3:0] offset_ammount ; 38 | logic [ SIZE_W+2:0] size_in_bits ; 39 | logic [2*BLOCK_W-1:0] shifted_data ; 40 | logic [ DATA_W-1:0] load_output_mask; 41 | logic [2*BLOCK_W-1:0] lower_mask ; 42 | logic [2*BLOCK_W-1:0] upper_mask ; 43 | logic [2*BLOCK_W-1:0] store_mask ; 44 | logic [2*BLOCK_W-1:0] new_data ; 45 | logic [2*BLOCK_W-1:0] new_block ; 46 | 47 | assign valid_exc = 1'b0; 48 | assign exception = '0; 49 | //======================================================= 50 | // Mask for output data (LOADS) 51 | //======================================================= 52 | // Shift the input block to align the data to position 0 53 | assign offset_ammount = input_address << 3; 54 | assign shifted_data = input_block >> offset_ammount; 55 | 56 | // Convert the size to number of bits 57 | assign size_in_bits = size << 3; //convert bytes to bits 58 | 59 | // Mask for output data (LOADS) 60 | assign load_output_mask = ~('1 << size_in_bits); 61 | assign output_vector = load_output_mask & shifted_data[DATA_W-1:0]; 62 | 63 | 64 | //======================================================= 65 | // Mask for new memory block (STORES) 66 | //======================================================= 67 | assign lower_mask = ~('1 << offset_ammount); 68 | assign upper_mask = lower_mask << size_in_bits; 69 | assign store_mask = upper_mask & lower_mask; 70 | // shift the data to the correct position inside the block 71 | assign new_data = (input_data << offset_ammount) & store_mask; 72 | // zero-out the old data inside the input block 73 | assign new_block = input_block & (~store_mask); 74 | // merge the old block with the new data 75 | assign output_block = new_block | new_data; 76 | 77 | 78 | //======================================================= 79 | // Maximum supported transaction size is equal/smaller than the configured cache line 80 | assert property (@(posedge clk) valid_i |-> (size_in_bits <= BLOCK_W)) else $warning("FATAL:vdata_operation: unsupported configuration"); 81 | assert property (@(posedge clk) valid_i |-> ~$isunknown(|output_vector)) else $error("x-check:vdata_operation: output_vector"); 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /rtl/shared/rr_arbiter.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @info Round Robin (RR) Arbiter 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | * @brief Round Robin (RR) Arbiter. If current priority points to input i, then the request vector ('request') 7 | * is checked in the following order: i->...->N-1->0->...->i-1 8 | * Priority is updated using 'update_pri', under the following policy: 9 | * When input i is currently being granted ('grant[i]' asserted) and update_pri[i] is asserted, 10 | * priority will be updated to point to input i+1 in the next cycle. 11 | * 'grant' is at-most-one-hot - 'anygrant' is the OR-reduced request vector 12 | * 13 | * @param N number of input requestors 14 | * @param PRI_RST starting priority after reset (points to that position, i.e. can have a value 0...N-1) 15 | */ 16 | 17 | //import noc_global::*; 18 | 19 | module rr_arbiter 20 | #(parameter int N = 2, 21 | parameter int PRI_RST = 0) 22 | (input logic clk, 23 | input logic rst, 24 | input logic[N-1:0] request, 25 | output logic[N-1:0] grant, 26 | output logic anygnt, 27 | input logic update_pri); 28 | 29 | localparam int S = $clog2(N); 30 | 31 | // Internal priority register 32 | logic[N-1:0] priority2; 33 | 34 | // Priority propagate and ganerate signals 35 | logic [N-1:0] g [S:0]; 36 | logic [N-1:0] p [S-1:0]; 37 | 38 | logic [N-1:0] grant_s; 39 | logic valid; 40 | 41 | assign grant = grant_s; 42 | 43 | // Parallel prefix round-robin arbitration 44 | 45 | int i,j; 46 | always_comb 47 | begin 48 | // initialize priority propagate 49 | // and generate vectors 50 | p[0][0] = ~request[N-1]; 51 | g[0][0] = priority2[0]; 52 | for(j=1; j < N; j=j+1) 53 | begin 54 | p[0][j] = ~request[j-1]; 55 | g[0][j] = priority2[j]; 56 | end 57 | 58 | // implement first log2n-1 prefix levels 59 | for(i=1; i < S; i=i+1) 60 | for(j=0; j < N; j=j+1) 61 | begin 62 | if ((j-2**(i-1)) < 0) 63 | begin 64 | g[i][j] = g[i-1][j] | ( p[i-1][j] & g[i-1][N+j-2**(i-1)]); 65 | p[i][j] = p[i-1][j] & p[i-1][N+j-2**(i-1)]; 66 | end 67 | else 68 | begin 69 | g[i][j] = g[i-1][j] | ( p[i-1][j] & g[i-1][ j-2**(i-1)]); 70 | p[i][j] = p[i-1][j] & p[i-1][ j-2**(i-1)]; 71 | end 72 | end 73 | 74 | // last prefix level 75 | for(j=0; j < N; j=j+1) 76 | begin 77 | if ((j-2**(S-1)) < 0) 78 | g[S][j] = g[S-1][j] | ( p[S-1][j] & g[S-1][ N+j-2**(S-1)]); 79 | else 80 | g[S][j] = g[S-1][j] | ( p[S-1][j] & g[S-1][ j-2**(S-1)]); 81 | end 82 | 83 | // grant signal generation 84 | for(j=0; j < N; j=j+1) 85 | grant_s[j] = request[j] & g[S][j]; 86 | 87 | end 88 | 89 | // Any grant generation at last prefix level 90 | assign valid = ~( p[S-1][N-1] & p[S-1][N/2-1]); 91 | assign anygnt = valid; 92 | 93 | //////////////////////// 94 | // Priority update logic 95 | //////////////////////// 96 | // int k; 97 | always_ff @ (posedge clk, posedge rst) 98 | begin 99 | if (rst) 100 | priority2 <= (1'b1 << PRI_RST); 101 | else 102 | if (valid) // At least one input was granted 103 | begin 104 | priority2 <= 0; 105 | for (int k=0; k < N; k=k+1) 106 | if (grant_s[k]) 107 | if (update_pri) 108 | begin 109 | if (k == (N-1)) 110 | priority2[0] <= 1'b1; 111 | else 112 | priority2[k+1] <= 1'b1; 113 | end 114 | else 115 | // if connection kept, current winner has the highest priority2 116 | priority2[k] <= 1'b1; 117 | 118 | end 119 | end 120 | 121 | endmodule 122 | -------------------------------------------------------------------------------- /sva/vmu_sva.sv: -------------------------------------------------------------------------------- 1 | //======================================================= 2 | // X Checks 3 | //======================================================= 4 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_in)) 5 | else $fatal("x-check:vmu: valid_in"); 6 | 7 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(cache_ready_i)) 8 | else $fatal("x-check:vmu: cache_ready_i"); 9 | 10 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(mem_resp_valid_i)) 11 | else $fatal("x-check:vmu: mem_resp_valid_i"); 12 | 13 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(wrtbck_en_o)) 14 | else $fatal("x-check:vmu: wrtbck_en_o"); 15 | 16 | assert property (@(posedge clk) disable iff(!rst_n) wrtbck_en_o |-> ~$isunknown(wrtbck_reg_o)) 17 | else $fatal("x-check:vmu: wrtbck_reg_o"); 18 | 19 | assert property (@(posedge clk) disable iff(!rst_n) wrtbck_en_o |-> ~$isunknown(wrtbck_data_o)) 20 | else $fatal("x-check:vmu: wrtbck_data_o"); 21 | 22 | assert property (@(posedge clk) disable iff(!rst_n) wrtbck_en_o |-> ~$isunknown(wrtbck_ticket_o)) 23 | else $fatal("x-check:vmu: wrtbck_ticket_o"); 24 | 25 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(unlock_en_o)) 26 | else $fatal("x-check:vmu: unlock_en_o"); 27 | 28 | assert property (@(posedge clk) disable iff(!rst_n) unlock_en_o |-> ~$isunknown(unlock_reg_a_o)) 29 | else $fatal("x-check:vmu: unlock_reg_a_o"); 30 | 31 | assert property (@(posedge clk) disable iff(!rst_n) unlock_en_o |-> ~$isunknown(unlock_reg_b_o)) 32 | else $fatal("x-check:vmu: unlock_reg_b_o"); 33 | 34 | assert property (@(posedge clk) disable iff(!rst_n) unlock_en_o |-> ~$isunknown(unlock_ticket_o)) 35 | else $fatal("x-check:vmu: unlock_ticket_o"); 36 | 37 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(push_load)) 38 | else $fatal("x-check:vmu: push_load"); 39 | 40 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(push_store)) 41 | else $fatal("x-check:vmu: push_store"); 42 | 43 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(push_toepl)) 44 | else $fatal("x-check:vmu: push_store"); 45 | 46 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(any_grant)) 47 | else $fatal("x-check:vmu: any_grant"); 48 | 49 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(ready_o)) 50 | else $fatal("x-check:vmu: ready_o"); 51 | 52 | 53 | // generate if (ADVANCED_ARBITR) begin 54 | // assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|active)) 55 | // else $fatal("x-check:vmu: active"); 56 | 57 | // assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|tail)) 58 | // else $fatal("x-check:vmu: tail"); 59 | 60 | // assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|activity_array)) 61 | // else $fatal("x-check:vmu: activity_array"); 62 | // end endgenerate 63 | //======================================================= 64 | // Properties 65 | //======================================================= 66 | assert property (@(posedge clk) disable iff(!rst_n) !(load_unlock_en & store_unlock_en)) 67 | else $fatal("vmu: unsupported scenario yet"); 68 | 69 | // assert property (@(posedge clk) disable iff(!rst_n) any_request & cache_ready_i |-> any_grant) 70 | // else $fatal("vmu: no memory grant was given"); 71 | 72 | assert property (@(posedge clk) disable iff(!rst_n) |wb_request |-> |wb_grant) 73 | else $fatal("vmu: no writeback grant was given"); 74 | 75 | assert property (@(posedge clk) disable iff(!rst_n) !fifo_ready |-> !ready_o) 76 | else $fatal("vmu: no new instr can be processed when activity matrix is full"); 77 | 78 | // generate if (ADVANCED_ARBITR) begin 79 | // assert property (@(posedge clk) disable iff(!rst_n) tail == 0 |=> ~&tail) 80 | // else $fatal("vmu: tail can not underflow"); 81 | // end endgenerate -------------------------------------------------------------------------------- /sva/vis_sva.sv: -------------------------------------------------------------------------------- 1 | //======================================================= 2 | // X Checks 3 | //======================================================= 4 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_in)) 5 | else $error("x-check:vis: valid_in"); 6 | 7 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(ready_o)) 8 | else $error("x-check:vis: ready_o"); 9 | 10 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_o)) 11 | else $error("x-check:vis: valid_o"); 12 | 13 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(ready_i)) 14 | else $error("x-check:vis: ready_i"); 15 | 16 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|mem_wr_en)) 17 | else $error("x-check:vis: mem_wr_en"); 18 | 19 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(unlock_en)) 20 | else $error("x-check:vis: unlock_en"); 21 | 22 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|frw_a_en)) 23 | else $error("x-check:vis: frw_a_en"); 24 | 25 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|frw_b_en)) 26 | else $error("x-check:vis: frw_b_en"); 27 | 28 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|wr_en)) 29 | else $error("x-check:vis: wr_en"); 30 | 31 | assert property (@(posedge clk) disable iff(!rst_n) valid_in |-> ~$isunknown(memory_instr)) 32 | else $error("x-check:vis: memory_instr"); 33 | 34 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(do_reconfigure)) 35 | else $error("x-check:vis: do_reconfigure"); 36 | 37 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(pop)) 38 | else $error("x-check:vis: pop"); 39 | 40 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(do_issue)) 41 | else $error("x-check:vis: do_issue"); 42 | 43 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|wr_en_masked)) 44 | else $error("x-check:vis: wr_en_masked"); 45 | 46 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|mem_wr_en)) 47 | else $error("x-check:vis: mem_wr_en"); 48 | 49 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|pending)) 50 | else $error("x-check:vis: pending"); 51 | 52 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(|locked)) 53 | else $error("x-check:vis: locked"); 54 | 55 | assert property (@(posedge clk) disable iff(!rst_n) |wr_en |-> ~$isunknown(|wr_addr)) 56 | else $error("x-check:vis: Address must not be X when a valid writeback is indicated"); 57 | 58 | assert property (@(posedge clk) disable iff(!rst_n) |wr_en |-> ~$isunknown(|wr_ticket)) 59 | else $error("x-check:vis: Ticket must not be X when a valid writeback is indicated"); 60 | 61 | generate for (genvar k = 0; k < VECTOR_LANES; k++) begin: g_vis_sva_writeback 62 | assert property (@(posedge clk) disable iff(!rst_n) wr_en[k] |-> ~$isunknown(|wr_data[k])) 63 | else $error("x-check:vis: writeback data must not be X for active pipes"); 64 | end endgenerate 65 | 66 | assert property (@(posedge clk) disable iff(!rst_n) |mem_wr_en |-> ~$isunknown(|mem_wr_addr)) 67 | else $error("x-check:vis: Address must not be X when a valid memory writeback is indicated"); 68 | 69 | assert property (@(posedge clk) disable iff(!rst_n) |mem_wr_en |-> ~$isunknown(|mem_wr_ticket)) 70 | else $error("x-check:vis: Ticket must not be X when a valid memory writeback is indicated"); 71 | //======================================================= 72 | // Properties 73 | //======================================================= 74 | assert property (@(posedge clk) disable iff(!rst_n) valid_in & !ready_o |=> valid_in) 75 | else $error("Assertion:vis: valid_in must stay stable"); 76 | 77 | assert property (@(posedge clk) disable iff(!rst_n) valid_in & !ready_o |=> $stable(instr_in)) 78 | else $error("Assertion:vis: input data must remain stable"); 79 | 80 | -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/fu_output.txt: -------------------------------------------------------------------------------- 1 | 00 2 | 00 3 | 00 4 | 10 5 | 11 6 | 11 7 | 11 8 | 11 9 | 00 10 | 00 11 | 10 12 | 11 13 | 11 14 | 11 15 | 11 16 | 00 17 | 00 18 | 10 19 | 11 20 | 11 21 | 11 22 | 11 23 | 00 24 | 00 25 | 10 26 | 11 27 | 11 28 | 11 29 | 11 30 | 00 31 | 00 32 | 10 33 | 11 34 | 11 35 | 11 36 | 11 37 | 00 38 | 00 39 | 10 40 | 11 41 | 11 42 | 11 43 | 11 44 | 00 45 | 00 46 | 10 47 | 11 48 | 11 49 | 11 50 | 11 51 | 00 52 | 00 53 | 10 54 | 11 55 | 11 56 | 11 57 | 11 58 | 00 59 | 00 60 | 10 61 | 11 62 | 11 63 | 11 64 | 11 65 | 00 66 | 00 67 | 10 68 | 11 69 | 11 70 | 11 71 | 11 72 | 00 73 | 00 74 | 10 75 | 11 76 | 11 77 | 11 78 | 11 79 | 00 80 | 00 81 | 10 82 | 11 83 | 11 84 | 11 85 | 11 86 | 00 87 | 00 88 | 10 89 | 11 90 | 11 91 | 11 92 | 11 93 | 00 94 | 00 95 | 10 96 | 11 97 | 11 98 | 11 99 | 11 100 | 00 101 | 00 102 | 10 103 | 11 104 | 11 105 | 11 106 | 11 107 | 00 108 | 00 109 | 10 110 | 11 111 | 11 112 | 11 113 | 11 114 | 00 115 | 00 116 | 10 117 | 11 118 | 11 119 | 11 120 | 11 121 | 00 122 | 00 123 | 10 124 | 11 125 | 11 126 | 11 127 | 11 128 | 00 129 | 00 130 | 10 131 | 11 132 | 11 133 | 11 134 | 11 135 | 00 136 | 00 137 | 10 138 | 11 139 | 11 140 | 11 141 | 11 142 | 00 143 | 00 144 | 10 145 | 11 146 | 11 147 | 11 148 | 11 149 | 00 150 | 00 151 | 10 152 | 11 153 | 11 154 | 11 155 | 11 156 | 00 157 | 00 158 | 10 159 | 11 160 | 11 161 | 11 162 | 11 163 | 00 164 | 00 165 | 10 166 | 11 167 | 11 168 | 11 169 | 11 170 | 00 171 | 00 172 | 10 173 | 11 174 | 11 175 | 11 176 | 11 177 | 00 178 | 00 179 | 10 180 | 11 181 | 11 182 | 11 183 | 11 184 | 00 185 | 00 186 | 10 187 | 11 188 | 11 189 | 11 190 | 11 191 | 00 192 | 00 193 | 10 194 | 11 195 | 11 196 | 11 197 | 11 198 | 00 199 | 00 200 | 10 201 | 11 202 | 11 203 | 11 204 | 11 205 | 00 206 | 00 207 | 10 208 | 11 209 | 11 210 | 11 211 | 11 212 | 00 213 | 00 214 | 10 215 | 11 216 | 11 217 | 11 218 | 11 219 | 00 220 | 00 221 | 10 222 | 11 223 | 11 224 | 11 225 | 11 226 | 00 227 | 00 228 | 10 229 | 11 230 | 11 231 | 11 232 | 11 233 | 00 234 | 00 235 | 10 236 | 11 237 | 11 238 | 11 239 | 11 240 | 00 241 | 00 242 | 10 243 | 11 244 | 11 245 | 11 246 | 11 247 | 00 248 | 00 249 | 10 250 | 11 251 | 11 252 | 11 253 | 11 254 | 00 255 | 00 256 | 10 257 | 11 258 | 11 259 | 11 260 | 11 261 | 00 262 | 00 263 | 10 264 | 11 265 | 11 266 | 11 267 | 11 268 | 00 269 | 00 270 | 10 271 | 11 272 | 11 273 | 11 274 | 11 275 | 00 276 | 00 277 | 10 278 | 11 279 | 11 280 | 11 281 | 11 282 | 00 283 | 00 284 | 10 285 | 11 286 | 11 287 | 11 288 | 11 289 | 00 290 | 00 291 | 10 292 | 11 293 | 11 294 | 11 295 | 11 296 | 00 297 | 00 298 | 10 299 | 11 300 | 11 301 | 11 302 | 11 303 | 00 304 | 00 305 | 10 306 | 11 307 | 11 308 | 11 309 | 11 310 | 00 311 | 00 312 | 10 313 | 11 314 | 11 315 | 11 316 | 11 317 | 00 318 | 00 319 | 10 320 | 11 321 | 11 322 | 11 323 | 11 324 | 00 325 | 00 326 | 10 327 | 11 328 | 11 329 | 11 330 | 11 331 | 00 332 | 00 333 | 10 334 | 11 335 | 11 336 | 11 337 | 11 338 | 00 339 | 00 340 | 10 341 | 11 342 | 11 343 | 11 344 | 11 345 | 00 346 | 00 347 | 10 348 | 11 349 | 11 350 | 11 351 | 11 352 | 00 353 | 00 354 | 10 355 | 11 356 | 11 357 | 11 358 | 11 359 | 00 360 | 00 361 | 10 362 | 11 363 | 11 364 | 11 365 | 11 366 | 00 367 | 00 368 | 10 369 | 11 370 | 11 371 | 11 372 | 11 373 | 00 374 | 00 375 | 10 376 | 11 377 | 11 378 | 11 379 | 11 380 | 00 381 | 00 382 | 10 383 | 11 384 | 11 385 | 11 386 | 11 387 | 00 388 | 00 389 | 10 390 | 11 391 | 11 392 | 11 393 | 11 394 | 00 395 | 00 396 | 10 397 | 11 398 | 11 399 | 11 400 | 11 401 | 00 402 | 00 403 | 10 404 | 11 405 | 11 406 | 11 407 | 11 408 | 00 409 | 00 410 | 10 411 | 11 412 | 11 413 | 11 414 | 11 415 | 00 416 | 00 417 | 10 418 | 11 419 | 11 420 | 11 421 | 11 422 | 00 423 | 00 424 | 10 425 | 11 426 | 11 427 | 11 428 | 11 429 | 00 430 | 00 431 | 10 432 | 11 433 | 11 434 | 11 435 | 11 436 | 00 437 | 00 438 | 10 439 | 11 440 | 11 441 | 11 442 | 11 443 | -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/fu_output.txt: -------------------------------------------------------------------------------- 1 | 00 2 | 00 3 | 00 4 | 10 5 | 11 6 | 11 7 | 11 8 | 11 9 | 00 10 | 00 11 | 10 12 | 11 13 | 11 14 | 11 15 | 11 16 | 00 17 | 00 18 | 10 19 | 11 20 | 11 21 | 11 22 | 11 23 | 00 24 | 00 25 | 10 26 | 11 27 | 11 28 | 11 29 | 11 30 | 00 31 | 00 32 | 10 33 | 11 34 | 11 35 | 11 36 | 11 37 | 00 38 | 00 39 | 10 40 | 11 41 | 11 42 | 11 43 | 11 44 | 00 45 | 00 46 | 10 47 | 11 48 | 11 49 | 11 50 | 11 51 | 00 52 | 00 53 | 10 54 | 11 55 | 11 56 | 11 57 | 11 58 | 00 59 | 00 60 | 10 61 | 11 62 | 11 63 | 11 64 | 11 65 | 00 66 | 00 67 | 10 68 | 11 69 | 11 70 | 11 71 | 11 72 | 00 73 | 00 74 | 10 75 | 11 76 | 11 77 | 11 78 | 11 79 | 00 80 | 00 81 | 10 82 | 11 83 | 11 84 | 11 85 | 11 86 | 00 87 | 00 88 | 10 89 | 11 90 | 11 91 | 11 92 | 11 93 | 00 94 | 00 95 | 10 96 | 11 97 | 11 98 | 11 99 | 11 100 | 00 101 | 00 102 | 10 103 | 11 104 | 11 105 | 11 106 | 11 107 | 00 108 | 00 109 | 10 110 | 11 111 | 11 112 | 11 113 | 11 114 | 00 115 | 00 116 | 10 117 | 11 118 | 11 119 | 11 120 | 11 121 | 00 122 | 00 123 | 10 124 | 11 125 | 11 126 | 11 127 | 11 128 | 00 129 | 00 130 | 10 131 | 11 132 | 11 133 | 11 134 | 11 135 | 00 136 | 00 137 | 10 138 | 11 139 | 11 140 | 11 141 | 11 142 | 00 143 | 00 144 | 10 145 | 11 146 | 11 147 | 11 148 | 11 149 | 00 150 | 00 151 | 10 152 | 11 153 | 11 154 | 11 155 | 11 156 | 00 157 | 00 158 | 10 159 | 11 160 | 11 161 | 11 162 | 11 163 | 00 164 | 00 165 | 10 166 | 11 167 | 11 168 | 11 169 | 11 170 | 00 171 | 00 172 | 10 173 | 11 174 | 11 175 | 11 176 | 11 177 | 00 178 | 00 179 | 10 180 | 11 181 | 11 182 | 11 183 | 11 184 | 00 185 | 00 186 | 10 187 | 11 188 | 11 189 | 11 190 | 11 191 | 00 192 | 00 193 | 10 194 | 11 195 | 11 196 | 11 197 | 11 198 | 00 199 | 00 200 | 10 201 | 11 202 | 11 203 | 11 204 | 11 205 | 00 206 | 00 207 | 10 208 | 11 209 | 11 210 | 11 211 | 11 212 | 00 213 | 00 214 | 10 215 | 11 216 | 11 217 | 11 218 | 11 219 | 00 220 | 00 221 | 10 222 | 11 223 | 11 224 | 11 225 | 11 226 | 00 227 | 00 228 | 10 229 | 11 230 | 11 231 | 11 232 | 11 233 | 00 234 | 00 235 | 10 236 | 11 237 | 11 238 | 11 239 | 11 240 | 00 241 | 00 242 | 10 243 | 11 244 | 11 245 | 11 246 | 11 247 | 00 248 | 00 249 | 10 250 | 11 251 | 11 252 | 11 253 | 11 254 | 00 255 | 00 256 | 10 257 | 11 258 | 11 259 | 11 260 | 11 261 | 00 262 | 00 263 | 10 264 | 11 265 | 11 266 | 11 267 | 11 268 | 00 269 | 00 270 | 10 271 | 11 272 | 11 273 | 11 274 | 11 275 | 00 276 | 00 277 | 10 278 | 11 279 | 11 280 | 11 281 | 11 282 | 00 283 | 00 284 | 10 285 | 11 286 | 11 287 | 11 288 | 11 289 | 00 290 | 00 291 | 10 292 | 11 293 | 11 294 | 11 295 | 11 296 | 00 297 | 00 298 | 10 299 | 11 300 | 11 301 | 11 302 | 11 303 | 00 304 | 00 305 | 10 306 | 11 307 | 11 308 | 11 309 | 11 310 | 00 311 | 00 312 | 10 313 | 11 314 | 11 315 | 11 316 | 11 317 | 00 318 | 00 319 | 10 320 | 11 321 | 11 322 | 11 323 | 11 324 | 00 325 | 00 326 | 10 327 | 11 328 | 11 329 | 11 330 | 11 331 | 00 332 | 00 333 | 10 334 | 11 335 | 11 336 | 11 337 | 11 338 | 00 339 | 00 340 | 10 341 | 11 342 | 11 343 | 11 344 | 11 345 | 00 346 | 00 347 | 10 348 | 11 349 | 11 350 | 11 351 | 11 352 | 00 353 | 00 354 | 10 355 | 11 356 | 11 357 | 11 358 | 11 359 | 00 360 | 00 361 | 10 362 | 11 363 | 11 364 | 11 365 | 11 366 | 00 367 | 00 368 | 10 369 | 11 370 | 11 371 | 11 372 | 11 373 | 00 374 | 00 375 | 10 376 | 11 377 | 11 378 | 11 379 | 11 380 | 00 381 | 00 382 | 10 383 | 11 384 | 11 385 | 11 386 | 11 387 | 00 388 | 00 389 | 10 390 | 11 391 | 11 392 | 11 393 | 11 394 | 00 395 | 00 396 | 10 397 | 11 398 | 11 399 | 11 400 | 11 401 | 00 402 | 00 403 | 10 404 | 11 405 | 11 406 | 11 407 | 11 408 | 00 409 | 00 410 | 10 411 | 11 412 | 11 413 | 11 414 | 11 415 | 00 416 | 00 417 | 10 418 | 11 419 | 11 420 | 11 421 | 11 422 | 00 423 | 00 424 | 10 425 | 11 426 | 11 427 | 11 428 | 11 429 | 00 430 | 00 431 | 10 432 | 11 433 | 11 434 | 11 435 | 11 436 | 00 437 | 00 438 | 10 439 | 11 440 | 11 441 | 11 442 | 11 443 | -------------------------------------------------------------------------------- /rtl/shared/lru_more.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info LRU Sub Module 3 | * @info Top Module: lru.sv 4 | * 5 | * @author VLSI Lab, EE dept., Democritus University of Thrace 6 | * 7 | * @param ASSOCIATIVITY: The cache's associavity for which the LRU is intented. 8 | * @param ENTRIES : The total addressable entries. 9 | * @param INDEX_BITS : The address width 10 | * @param OUTPUT_BITS : The output width 11 | */ 12 | module lru_more #(ASSOCIATIVITY=4,ENTRIES=256,INDEX_BITS=8,OUTPUT_BITS=2) ( 13 | input logic clk , 14 | input logic rst_n , 15 | //Read Port 16 | input logic [ INDEX_BITS-1:0] line_selector , 17 | output logic [OUTPUT_BITS-1:0] lru_way , 18 | //Update Port 19 | input logic lru_update , 20 | input logic [OUTPUT_BITS-1:0] referenced_set 21 | ); 22 | // #Internal Signals 23 | logic [ENTRIES-1 : 0] Stored_Stats; 24 | logic lru_update1,lru_update2,selected_bank,lru_way1,lru_way2; 25 | 26 | generate 27 | // ASSOCIATIVITY==4 28 | if(ASSOCIATIVITY==4) begin 29 | //Drive the Wr_En signals (Top Bit from reference indicates the bank) 30 | assign lru_update1 = ~referenced_set[1] & lru_update; 31 | assign lru_update2 = referenced_set[1] & lru_update; 32 | 33 | lru_two #(ENTRIES,INDEX_BITS) 34 | lru_1(.clk (clk), 35 | .rst_n (rst_n), 36 | .line_selector (line_selector), 37 | .referenced_set (referenced_set[0]), 38 | .lru_update (lru_update1), 39 | .lru_way (lru_way1)); 40 | 41 | lru_two #(ENTRIES,INDEX_BITS) 42 | lru_2(.clk (clk), 43 | .rst_n (rst_n), 44 | .line_selector (line_selector), 45 | .referenced_set (referenced_set[0]), 46 | .lru_update (lru_update2), 47 | .lru_way (lru_way2)); 48 | 49 | //Retrieve Stored Data 50 | assign selected_bank = Stored_Stats[line_selector]; 51 | //Choose one bank based on the stored data 52 | assign lru_way = selected_bank ? {1'b1,lru_way2} : {1'b0,lru_way1}; 53 | //Save the data (which of the 2 banks were used) 54 | always_ff @(posedge clk or negedge rst_n) begin : Update 55 | if(!rst_n) begin 56 | Stored_Stats <= 'b0; 57 | end else begin 58 | if(lru_update) begin 59 | //Top Bit from reference indicates the bank 60 | Stored_Stats[line_selector] <= ~referenced_set[1]; 61 | end 62 | end 63 | end 64 | // ASSOCIATIVITY>4 (e.g. 8/16) 65 | end else if(ASSOCIATIVITY>4) begin 66 | 67 | assign lru_update1 = ~referenced_set[ASSOCIATIVITY -2] & lru_update; 68 | assign lru_update2 = referenced_set[ASSOCIATIVITY -2] & lru_update; 69 | 70 | lru_more #(ASSOCIATIVITY/2,ENTRIES,INDEX_BITS,OUTPUT_BITS-1) 71 | lru_more1(.clk (clk), 72 | .rst_n (rst_n), 73 | .line_selector (line_selector), 74 | .referenced_set (referenced_set[OUTPUT_BITS-2 : 0]), 75 | .lru_update (lru_update1), 76 | .lru_way (lru_way1)); 77 | 78 | lru_more #(ASSOCIATIVITY/2,ENTRIES,INDEX_BITS,OUTPUT_BITS-1) 79 | lru_more2(.clk (clk), 80 | .rst_n (rst_n), 81 | .line_selector (line_selector), 82 | .referenced_set (referenced_set[OUTPUT_BITS-2 : 0]), 83 | .lru_update (lru_update2), 84 | .lru_way (lru_way2)); 85 | 86 | //Retrieve Stored Data 87 | assign selected_bank = Stored_Stats[line_selector]; 88 | //Choose one bank based on the stored data 89 | assign lru_way = selected_bank ? {0,lru_way1} : {1,lru_way2}; 90 | //Save the data (which of the 2 banks were used) 91 | always_ff @(posedge clk or negedge rst_n) begin : Update 92 | if(!rst_n) begin 93 | Stored_Stats <= 'b0; 94 | end else begin 95 | if(lru_update) begin 96 | //Top Bit from reference indicates one of the banks 97 | Stored_Stats[line_selector] <= ~referenced_set[ASSOCIATIVITY -2]; 98 | end 99 | end 100 | end 101 | end 102 | endgenerate 103 | 104 | endmodule -------------------------------------------------------------------------------- /rtl/shared/eb_two_slot.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * @info eb_two_slot 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | * @brief 2-slot Elastic Buffer (EB) that achieves 100% throughput without combinational back-notification propagation. 7 | * Combines the benefits of HBEB and PEB (@see eb_one_slot) but requires 2 buffer slots. 8 | * Note: It is not mandatory that the sender checks the EB's ready_out to assert its valid. 9 | * Design Concerns: 10 | * + Completely cuts off the forward path. Output Data do not go through any MUX (as would happen in a 11 | * circular buffer FIFO). This comes at the cost of the following: 12 | * - The Input Data path sees a 2:1 MUX. 13 | * - It is not a really power friendly design (the input buffer slot makes redundant writes) & in case 14 | * of a stall, it SHIFTS data 15 | * It may be preferred in cases where Output paths are slower and the FIFO MUX must be removed. 16 | * (can be used combined with circular buffer FIFO, @see fifo_duth) 17 | * 18 | * @param DATA_WIDTH data width 19 | * @param GATING_FRIENDLY determines if data are always registered (==0) or only when 'valid_in' is asserted (==1). 20 | */ 21 | 22 | module eb_two_slot 23 | #( 24 | parameter int DATA_WIDTH = 16, 25 | parameter logic GATING_FRIENDLY = 1'b1 26 | ) 27 | ( 28 | input logic clk, 29 | input logic rst, 30 | // input side 31 | input logic valid_in, 32 | output logic ready_out, 33 | input logic[DATA_WIDTH-1:0] data_in, 34 | 35 | //output side 36 | output logic valid_out, 37 | input logic ready_in, 38 | output logic[DATA_WIDTH-1:0] data_out 39 | ); 40 | // ------------------------------------------------------------------------------------------------ // 41 | // Main 42 | logic valid_to_main_eb; 43 | logic ready_from_main_eb; 44 | logic[DATA_WIDTH-1:0] data_to_main_eb; 45 | // Buffered ready 46 | logic ready_main_buf; 47 | //Aux 48 | logic ready_from_aux_eb; 49 | logic valid_from_aux_eb; 50 | logic ready_to_aux_eb; 51 | logic[DATA_WIDTH-1:0] data_from_aux_eb; 52 | // ------------------------------------------------------------------------------------------------ // 53 | 54 | // Back 55 | assign ready_out = ready_from_aux_eb; 56 | 57 | // Aux reg 58 | eb_one_slot 59 | #( 60 | .FULL_THROUGHPUT (1'b1), 61 | .DATA_WIDTH (DATA_WIDTH), 62 | .GATING_FRIENDLY (GATING_FRIENDLY) 63 | ) 64 | eb_aux 65 | ( 66 | .clk (clk), 67 | .rst (rst), 68 | .valid_in (valid_in), 69 | .ready_out (ready_from_aux_eb), 70 | .data_in (data_in), 71 | .valid_out (valid_from_aux_eb), 72 | .ready_in (ready_to_aux_eb), 73 | .data_out (data_from_aux_eb) 74 | ); 75 | 76 | assign ready_to_aux_eb = ready_main_buf; 77 | 78 | // buffer ready from main reg 79 | always_ff @ (posedge clk, posedge rst) begin: ff_ready_main_buf 80 | if (rst) begin 81 | ready_main_buf <= 1; 82 | end else begin 83 | ready_main_buf <= ready_from_main_eb; 84 | end 85 | end 86 | 87 | // Main reg 88 | assign valid_to_main_eb = ready_from_aux_eb ? valid_in : valid_from_aux_eb; 89 | assign data_to_main_eb = ready_from_aux_eb ? data_in : data_from_aux_eb; 90 | 91 | eb_one_slot 92 | #( 93 | .FULL_THROUGHPUT (1'b1), 94 | .DATA_WIDTH (DATA_WIDTH), 95 | .GATING_FRIENDLY (GATING_FRIENDLY) 96 | ) 97 | eb_main 98 | ( 99 | .clk (clk), 100 | .rst (rst), 101 | .valid_in (valid_to_main_eb), 102 | .ready_out (ready_from_main_eb), 103 | .data_in (data_to_main_eb), 104 | .valid_out (valid_out), 105 | .ready_in (ready_in), 106 | .data_out (data_out) 107 | ); 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /rtl/shared/params.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * @author VLSI Lab, EE dept., Democritus University of Thrace 4 | * 5 | */ 6 | `ifdef MODEL_TECH 7 | `include "vmacros.sv" 8 | `endif 9 | //============================================// 10 | // Scalar Pipe Parameters // 11 | //============================================// 12 | 13 | //=============================== 14 | // TUNABLE PARAMETERS 15 | //=============================== 16 | 17 | //Dual Issue Enabler 18 | localparam int DUAL_ISSUE = 1; 19 | //Logging Enabler 20 | localparam int ENABLE_LOGGING = 0; 21 | 22 | //------------------------- 23 | //Memory System Parameters 24 | //------------------------- 25 | // instruction cache entries 26 | localparam int IC_ENTRIES = 32; 27 | // instruction cache line size 28 | localparam int IC_DW = 256; 29 | // instruction cache associativity 30 | localparam int IC_ASC = 2; 31 | // data cache entries 32 | localparam int DC_ENTRIES = 32; 33 | // data cache line size 34 | localparam int DC_DW = 512; 35 | // data cache associativity 36 | localparam int DC_ASC = 4; 37 | // L2 cache entries 38 | localparam int L2_ENTRIES = 2048; 39 | // L2 line size 40 | localparam int L2_DW = 1024; 41 | // Immitate a realistic memory system 42 | localparam int REALISTIC = 1; 43 | // Response Cycles for L2 (when realistic enabled) 44 | localparam int DELAY_CYCLES = 10; 45 | 46 | //--------------------------- 47 | //Branch Predictor Parameters 48 | //--------------------------- 49 | localparam int RAS_DEPTH = 8 ; 50 | localparam int GSH_HISTORY_BITS = 2 ; 51 | localparam int GSH_SIZE = 256; 52 | localparam int BTB_SIZE = 256; 53 | 54 | //=============================== 55 | // NOT !! TUNABLE PARAMETERS 56 | //=============================== 57 | 58 | //--------------------------- 59 | //ROB Parameters 60 | //--------------------------- 61 | localparam int ROB_ENTRIES = 8 ; //default: 8 62 | localparam int ROB_TICKET_W = $clog2(ROB_ENTRIES); //default: DO NOT MODIFY 63 | 64 | //--------------------------- 65 | //Other Parameters (DO NOT MODIFY) 66 | //--------------------------- 67 | localparam int ISTR_DW = 32 ; //default: 32 68 | localparam int ADDR_BITS = 32 ; //default: 32 69 | localparam int DATA_WIDTH = 32 ; //default: 32 70 | localparam int FETCH_WIDTH = 64 ; //default: 64 71 | localparam int R_WIDTH = 6 ; //default: 6 72 | localparam int MICROOP_W = 5 ; //default: 5 73 | 74 | //--------------------------- 75 | //CSR Parameters (DO NOT MODIFY) 76 | localparam int CSR_DEPTH = 64; 77 | 78 | //============================================// 79 | // Vector Pipe Parameters // 80 | //============================================// 81 | //=============================== 82 | // TUNABLE PARAMETERS 83 | //=============================== 84 | // Enables the vector pipeline 85 | localparam int VECTOR_ENABLED = 1; 86 | // number of vector lanes/elements (currently max 16) 87 | localparam int VECTOR_LANES = 8; //must also change dummy param in vstructs 88 | // execution stage the forwardwing point will be connected to : 89 | // EX1 1 90 | // EX2 2 91 | // EX2_F 20 (flopped) 92 | // EX3 3 93 | // EX3_F 30 (flopped) 94 | // EX4 4 95 | // EX4_F 40 (flopped) 96 | localparam int VECTOR_FWD_POINT_A = `EX1; 97 | localparam int VECTOR_FWD_POINT_B = `EX4_F; 98 | // Enable dynamic RF allocation and hw loop unrolling 99 | localparam USE_HW_UNROLL = 1; 100 | //=============================== 101 | // NOT !! TUNABLE PARAMETERS 102 | //=============================== 103 | //Floating Point ALU present 104 | localparam VECTOR_FP_ALU = 1; 105 | //Fixed Point ALU not present yet 106 | localparam VECTOR_FXP_ALU = 0; 107 | localparam int VECTOR_REGISTERS = 32 ; //default: 32 108 | localparam int VECTOR_MEM_MICROOP_WIDTH = 7 ; //default: 7 109 | localparam int VECTOR_MICROOP_WIDTH = 7 ; //default: 7 110 | localparam int VECTOR_TICKET_BITS = 5 ; //default: 5 111 | localparam int VECTOR_MAX_REQ_WIDTH = 512; //default: 256 -------------------------------------------------------------------------------- /vector_simulator/vector_driver.sv: -------------------------------------------------------------------------------- 1 | `include "vstructs.sv" 2 | module vector_driver #( 3 | parameter int DEPTH = 4 , 4 | parameter int DATA_WIDTH = 32, 5 | parameter int VECTOR_REGISTERS = 32, 6 | parameter int VECTOR_LANES = 8 , 7 | parameter int MICROOP_WIDTH = 32 8 | ) ( 9 | input logic clk , 10 | input logic rst_n , 11 | // input side 12 | output logic valid_o, 13 | output to_vector instr_o, 14 | input logic pop_i 15 | ); 16 | 17 | logic [$clog2(DEPTH+1)-1:0] head; 18 | // Memory Initialized with the generator outputs 19 | logic reconfiguration_list[DEPTH-1:0]; 20 | logic [ DATA_WIDTH-1:0] data1_list [DEPTH-1:0]; 21 | logic [ DATA_WIDTH-1:0] data2_list [DEPTH-1:0]; 22 | logic [ DATA_WIDTH-1:0] immediate_list [DEPTH-1:0]; 23 | logic [$clog2(VECTOR_REGISTERS)-1:0] destination_list [DEPTH-1:0]; 24 | logic [$clog2(VECTOR_REGISTERS)-1:0] operand_a_list [DEPTH-1:0]; 25 | logic [$clog2(VECTOR_REGISTERS)-1:0] operand_b_list [DEPTH-1:0]; 26 | logic [$clog2(VECTOR_REGISTERS)-1:0] operand_c_list [DEPTH-1:0]; 27 | logic [ MICROOP_WIDTH-1:0] microop_list [DEPTH-1:0]; 28 | logic [ 1:0] fu_list [DEPTH-1:0]; 29 | logic [ 32-1:0] maxvl_list [DEPTH-1:0]; 30 | logic [ 32-1:0] vl_list [DEPTH-1:0]; 31 | 32 | // Load the Memories 33 | initial begin 34 | $readmemb("../vector_simulator/decoder_results/instrs/data1_output.txt",data1_list); 35 | $readmemb("../vector_simulator/decoder_results/instrs/data2_output.txt",data2_list); 36 | $readmemb("../vector_simulator/decoder_results/instrs/immediate_output.txt",immediate_list); 37 | $readmemb("../vector_simulator/decoder_results/instrs/destination_output.txt",destination_list); 38 | $readmemb("../vector_simulator/decoder_results/instrs/operand_a_output.txt",operand_a_list); 39 | $readmemb("../vector_simulator/decoder_results/instrs/operand_b_output.txt",operand_b_list); 40 | $readmemb("../vector_simulator/decoder_results/instrs/operand_c_output.txt",operand_c_list); 41 | $readmemb("../vector_simulator/decoder_results/instrs/microop_output.txt",microop_list); 42 | $readmemb("../vector_simulator/decoder_results/instrs/fu_output.txt",fu_list); 43 | $readmemb("../vector_simulator/decoder_results/instrs/reconfigure_output.txt",reconfiguration_list); 44 | $readmemb("../vector_simulator/decoder_results/instrs/maxvl_output.txt",maxvl_list); 45 | $readmemb("../vector_simulator/decoder_results/instrs/vl_output.txt",vl_list); 46 | end 47 | 48 | logic instr_is_dummy; 49 | // A dummy instruction is a NOP that will be poped from the list but not issued 50 | // Used to emulate cycles where the scalar core decodes scalar instructions (e.g. control instrs) 51 | assign instr_is_dummy = reconfiguration_list[head] & &fu_list[head] & microop_list[head] & ~|vl_list[head] & ~|maxvl_list[head]; 52 | 53 | // Manage the list head pointer 54 | always_ff @(posedge clk or negedge rst_n) begin 55 | if(~rst_n) begin 56 | head <= 0; 57 | end else begin 58 | if (pop_i | instr_is_dummy) head <= head +1; 59 | end 60 | end 61 | 62 | // Create the Outputs 63 | assign valid_o = (head < DEPTH) & rst_n & ~instr_is_dummy; 64 | 65 | assign instr_o.valid = valid_o; 66 | assign instr_o.dst = destination_list[head]; 67 | assign instr_o.src1 = operand_a_list[head]; 68 | assign instr_o.src2 = operand_b_list[head]; 69 | assign instr_o.data1 = data1_list[head]; 70 | assign instr_o.data2 = data2_list[head]; 71 | assign instr_o.reconfigure = reconfiguration_list[head]; 72 | assign instr_o.immediate = immediate_list[head]; 73 | assign instr_o.fu = fu_list[head]; 74 | assign instr_o.microop = microop_list[head]; 75 | assign instr_o.maxvl = maxvl_list[head][$clog2(VECTOR_REGISTERS*VECTOR_LANES):0]; 76 | assign instr_o.vl = vl_list[head][$clog2(VECTOR_REGISTERS*VECTOR_LANES):0]; 77 | assign instr_o.use_mask = '0; 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## RISC-V2: A vector processor core for the RISC-V Vector ISA extension 2 | Vector architectures are almost unique in their ability to effectively combine high programmability attributes, high computational throughput, and high energy efficiency. This work builds an efficient vector processor that implements the upcoming RISC-V vector ISA extension. The proposed architecture is founded on the traditional tenets of vector processing, and it introduces novel techniques that reap high performance benefits in a cost-effective implementation: 3 | 4 | - A new register remapping technique that together with a dynamically allocated register file enable dynamic hardware-based loop unrolling 5 | and optimized instruction scheduling at run-time. 6 | - The design’s decoupled execution scheme employs resource acquire-and-release semantics to disambiguate between parallel computation and memory-access 7 | instruction streams, thereby allowing for independent execution/memory flow rates. 8 | - A dynamically generated hardware reduction tree enables significant acceleration of reduction intstructions. 9 | - Variable execution latency based on instruction type 10 | 11 | RISC-V2 is integrated in a two-way superscalar OoO core. 12 | 13 | 14 | 15 | The scalar core acts as the main control processor, with all the instructions being fetched and decoded in the scalar pipeline. 16 | During the superscalar issue stage, the instructions are diverted to the correct path (i.e., scalar, or vector), based on their type. 17 | A vector instruction queue decouples the execution rates of the two datapaths. 18 | 19 | At the moment, the RTL of the scalar core is not publicly shared. We will fix this soon. 20 | 21 | ## Directory Hierarchy 22 | 23 | The folder hierarchy is organised as follows: 24 | - `images`: schematics and instruction mappings to microops 25 | - `rtl` : contains all the synthesisable RTL files 26 | - `sva` : contains related x-checks and assertions for the design 27 | - `vector_simulator` : contains the TB to run a simulation with the Vector datapath, as well as some example stimulus. 28 | 29 | ## Repo State 30 | 31 | - Support for Integer Arithmetic, Memory operations & Reduction operations 32 | - Support for register grouping and dynamic register file allocation 33 | - Decoupled execution between computational and memory instructions 34 | - Current maximum vector lanes supported is 16. 35 | - SVAs have been used in simulation only. No formal verification runs at the moment. 36 | 37 | ## Future Work 38 | - Align to the newer versions of the RISC-V ISA 39 | - Replace MUL/DIV units with optimised hardware, to reduce execution latency and improve timing closure 40 | - Decouple the vis<>vmu paths, which are currently very pressed for timing. Trials made in that area resulted in a much smaller footprint, due to the decompressed hardware 41 | - Add back-pressure on the execution pipes, to allow for `vector_lanes > 16` configurations (Needed by the reduction tree to support more lanes) 42 | - Add Floating point execution lanes 43 | 44 | ## The provided simulator 45 | The repo at it's current stage contains the vector datapath, as well as a testbench that can be used to simulate payloads on it. The superscalar core is not provided yet, but will be released in the future. The hierarchy can be seen below: 46 | 47 | _**TB Level Hierarchy:**_ 48 | ->`vector_sim_top.sv` -> `vector_driver` & `vector_top` 49 | 50 | | Hierarchy Name | Details | 51 | |:----------------:|-----------------------------------------------------------------------------------------------------| 52 | | vector_sim_top | top level of the TB, instantiating the vector datapath and the scalar simulator. | 53 | | vector_driver | The TB driver that feeds the vector datapath with decoded vector instructions. | 54 | | vector_top | The top level of the vector datapath, as shown in figure 2. | 55 | 56 | ## Reference 57 | RISC-V2 architecture and performance is presented in 58 | IEEE International Symposium on Circuits and Systems, Oct. 2020. You can find the paper 59 | [paper](https://ieeexplore.ieee.org/document/9181071) here. 60 | To cite this work please use 61 | ``` 62 | @INPROCEEDINGS{risc-v-squared, 63 | author={K. {Patsidis} and C. {Nicopoulos} and G. C. {Sirakoulis} and G. {Dimitrakopoulos}}, 64 | booktitle={2020 IEEE International Symposium on Circuits and Systems (ISCAS)}, 65 | title={RISC-V^$2$: A Scalable RISC-V Vector Processor}, 66 | year={2020}, 67 | volume={}, 68 | number={}, 69 | pages={1-5},} 70 | ``` 71 | 72 | 73 | ## License 74 | RISC-V2 is licensed under the [MIT License](./LICENSE). 75 | -------------------------------------------------------------------------------- /rtl/README.md: -------------------------------------------------------------------------------- 1 | # Overview 2 | This directory contains all the synthesisable RTL files. 3 | 4 | All the parameters regarding the design can be found inside the `params.sv` file. Note that only a subset of them are tunable, as mentioned in the comments inside the file. Also, within the file there are some scalar parameters, which are not actively used by this repo, until the superscalar core is also released. 5 | 6 | Any structs and macros used in the vector datapath can be found inside the `vmacros.sv` and `vstructs.sv` files respectively. 7 | 8 | ### Vector Datapath 9 | 10 | The following table lists the major units in the vector datapath and their operation 11 | 12 | | Vector Unit Name | Details | 13 | |:----------------:|-----------------------------------------------------------------------------------------------------| 14 | | vrrm | The Register Remap stage, responsible for the register grouping and allocation. | 15 | | vis | The Issue stage, responsible for hazard tracking and operand selection. It is based around a scoreboard.| 16 | | vex | The execution stage, containing the vector lanes and surround logic and connection. | 17 | | vex_pipe | The main execution lane, containing the different execution units. | 18 | | vmu | The vector memory unit, containing sub-engines handling different memory accesses and arbitration logic for those engines. | 19 | | vmu_ld_eng | The load engine of the memory unit. | 20 | | vmu_st_eng | The store engine of the memory unit. | 21 | | vmu_tp_eng | The region prefetch engine of the memory unit, used in tangem with custom instructions to accelerate image loading from memory. | 22 | 23 | The list of the curently supported operations (custom instructions are denoted with italic fonts): 24 | 25 | | Memory Operations | Integer Operations | 26 | |:-------------------:|:-------------------:| 27 | | vfld |vadd | 28 | | vflh |vaddi | 29 | | vflsd |vaddw | 30 | | vflsh |vaddiw | 31 | | vflsw |vsub | 32 | | vflw |vsubw | 33 | | vflxd |vmul | 34 | | vflxh |vmulh | 35 | | vflxw |vmulhsu | 36 | | vlb |vmulhu | 37 | | vlbu |vmulwdn | 38 | | vld |vdiv | 39 | | vlh |vdivu | 40 | | vlhu |vrem | 41 | | vlsb |vremu | 42 | | vlsbu |vsll | 43 | | vlsd |vslli | 44 | | vlsw |vsra | 45 | | vlswu |vsrai | 46 | | vlw |vsrl | 47 | | vlwu |vsrli | 48 | | vlxb |vand | 49 | | vlxbu |vandi | 50 | | vlxd |vor | 51 | | vlxh |vori | 52 | | vlxh |vxor | 53 | | vlxhu |vxori | 54 | | vlxhu |vseq | 55 | | vlxw |vslt | 56 | | vlxwu |vsltu | 57 | | vsb |vrelu | 58 | | vsd |vstep | 59 | | vsh |vbrelu | 60 | | vssb |vprelu | 61 | | vssd |vradd | 62 | | vssh |vrand | 63 | | vssw |vror | 64 | | vsw |vrxor | 65 | | vsxb | | 66 | | vsxd | | 67 | | vsxh | | 68 | | vsxub | | 69 | | vsxud | | 70 | | vsxuh | | 71 | | vsxuw | | 72 | | vsxw | | 73 | | *vtplcfg* | | 74 | | *vtpl* | | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/destination_output.txt: -------------------------------------------------------------------------------- 1 | 00000 2 | 00000 3 | 00001 4 | 00010 5 | 00000 6 | 00000 7 | 00000 8 | 00000 9 | 00000 10 | 00001 11 | 00010 12 | 00000 13 | 00000 14 | 00000 15 | 00000 16 | 00000 17 | 00001 18 | 00010 19 | 00000 20 | 00000 21 | 00000 22 | 00000 23 | 00000 24 | 00001 25 | 00010 26 | 00000 27 | 00000 28 | 00000 29 | 00000 30 | 00000 31 | 00001 32 | 00010 33 | 00000 34 | 00000 35 | 00000 36 | 00000 37 | 00000 38 | 00001 39 | 00010 40 | 00000 41 | 00000 42 | 00000 43 | 00000 44 | 00000 45 | 00001 46 | 00010 47 | 00000 48 | 00000 49 | 00000 50 | 00000 51 | 00000 52 | 00001 53 | 00010 54 | 00000 55 | 00000 56 | 00000 57 | 00000 58 | 00000 59 | 00001 60 | 00010 61 | 00000 62 | 00000 63 | 00000 64 | 00000 65 | 00000 66 | 00001 67 | 00010 68 | 00000 69 | 00000 70 | 00000 71 | 00000 72 | 00000 73 | 00001 74 | 00010 75 | 00000 76 | 00000 77 | 00000 78 | 00000 79 | 00000 80 | 00001 81 | 00010 82 | 00000 83 | 00000 84 | 00000 85 | 00000 86 | 00000 87 | 00001 88 | 00010 89 | 00000 90 | 00000 91 | 00000 92 | 00000 93 | 00000 94 | 00001 95 | 00010 96 | 00000 97 | 00000 98 | 00000 99 | 00000 100 | 00000 101 | 00001 102 | 00010 103 | 00000 104 | 00000 105 | 00000 106 | 00000 107 | 00000 108 | 00001 109 | 00010 110 | 00000 111 | 00000 112 | 00000 113 | 00000 114 | 00000 115 | 00001 116 | 00010 117 | 00000 118 | 00000 119 | 00000 120 | 00000 121 | 00000 122 | 00001 123 | 00010 124 | 00000 125 | 00000 126 | 00000 127 | 00000 128 | 00000 129 | 00001 130 | 00010 131 | 00000 132 | 00000 133 | 00000 134 | 00000 135 | 00000 136 | 00001 137 | 00010 138 | 00000 139 | 00000 140 | 00000 141 | 00000 142 | 00000 143 | 00001 144 | 00010 145 | 00000 146 | 00000 147 | 00000 148 | 00000 149 | 00000 150 | 00001 151 | 00010 152 | 00000 153 | 00000 154 | 00000 155 | 00000 156 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00000 427 | 00000 428 | 00000 429 | 00000 430 | 00000 431 | 00001 432 | 00000 433 | 00000 434 | 00000 435 | 00000 436 | 00000 437 | 00000 438 | 00001 439 | 00000 440 | 00000 441 | 00000 442 | 00000 443 | -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/operand_c_output.txt: -------------------------------------------------------------------------------- 1 | 00000 2 | 00000 3 | 00000 4 | 00000 5 | 00000 6 | 00000 7 | 00000 8 | 00000 9 | 00000 10 | 00000 11 | 00000 12 | 00000 13 | 00000 14 | 00000 15 | 00000 16 | 00000 17 | 00000 18 | 00000 19 | 00000 20 | 00000 21 | 00000 22 | 00000 23 | 00000 24 | 00000 25 | 00000 26 | 00000 27 | 00000 28 | 00000 29 | 00000 30 | 00000 31 | 00000 32 | 00000 33 | 00000 34 | 00000 35 | 00000 36 | 00000 37 | 00000 38 | 00000 39 | 00000 40 | 00000 41 | 00000 42 | 00000 43 | 00000 44 | 00000 45 | 00000 46 | 00000 47 | 00000 48 | 00000 49 | 00000 50 | 00000 51 | 00000 52 | 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00000 223 | 00000 224 | 00000 225 | 00000 226 | 00000 227 | 00000 228 | 00000 229 | 00000 230 | 00000 231 | 00000 232 | 00000 233 | 00000 234 | 00000 235 | 00000 236 | 00000 237 | 00000 238 | 00000 239 | 00000 240 | 00000 241 | 00000 242 | 00000 243 | 00000 244 | 00000 245 | 00000 246 | 00000 247 | 00000 248 | 00000 249 | 00000 250 | 00000 251 | 00000 252 | 00000 253 | 00000 254 | 00000 255 | 00000 256 | 00000 257 | 00000 258 | 00000 259 | 00000 260 | 00000 261 | 00000 262 | 00000 263 | 00000 264 | 00000 265 | 00000 266 | 00000 267 | 00000 268 | 00000 269 | 00000 270 | 00000 271 | 00000 272 | 00000 273 | 00000 274 | 00000 275 | 00000 276 | 00000 277 | 00000 278 | 00000 279 | 00000 280 | 00000 281 | 00000 282 | 00000 283 | 00000 284 | 00000 285 | 00000 286 | 00000 287 | 00000 288 | 00000 289 | 00000 290 | 00000 291 | 00000 292 | 00000 293 | 00000 294 | 00000 295 | 00000 296 | 00000 297 | 00000 298 | 00000 299 | 00000 300 | 00000 301 | 00000 302 | 00000 303 | 00000 304 | 00000 305 | 00000 306 | 00000 307 | 00000 308 | 00000 309 | 00000 310 | 00000 311 | 00000 312 | 00000 313 | 00000 314 | 00000 315 | 00000 316 | 00000 317 | 00000 318 | 00000 319 | 00000 320 | 00000 321 | 00000 322 | 00000 323 | 00000 324 | 00000 325 | 00000 326 | 00000 327 | 00000 328 | 00000 329 | 00000 330 | 00000 331 | 00000 332 | 00000 333 | 00000 334 | 00000 335 | 00000 336 | 00000 337 | 00000 338 | 00000 339 | 00000 340 | 00000 341 | 00000 342 | 00000 343 | 00000 344 | 00000 345 | 00000 346 | 00000 347 | 00000 348 | 00000 349 | 00000 350 | 00000 351 | 00000 352 | 00000 353 | 00000 354 | 00000 355 | 00000 356 | 00000 357 | 00000 358 | 00000 359 | 00000 360 | 00000 361 | 00000 362 | 00000 363 | 00000 364 | 00000 365 | 00000 366 | 00000 367 | 00000 368 | 00000 369 | 00000 370 | 00000 371 | 00000 372 | 00000 373 | 00000 374 | 00000 375 | 00000 376 | 00000 377 | 00000 378 | 00000 379 | 00000 380 | 00000 381 | 00000 382 | 00000 383 | 00000 384 | 00000 385 | 00000 386 | 00000 387 | 00000 388 | 00000 389 | 00000 390 | 00000 391 | 00000 392 | 00000 393 | 00000 394 | 00000 395 | 00000 396 | 00000 397 | 00000 398 | 00000 399 | 00000 400 | 00000 401 | 00000 402 | 00000 403 | 00000 404 | 00000 405 | 00000 406 | 00000 407 | 00000 408 | 00000 409 | 00000 410 | 00000 411 | 00000 412 | 00000 413 | 00000 414 | 00000 415 | 00000 416 | 00000 417 | 00000 418 | 00000 419 | 00000 420 | 00000 421 | 00000 422 | 00000 423 | 00000 424 | 00000 425 | 00000 426 | 00000 427 | 00000 428 | 00000 429 | 00000 430 | 00000 431 | 00000 432 | 00000 433 | 00000 434 | 00000 435 | 00000 436 | 00000 437 | 00000 438 | 00000 439 | 00000 440 | 00000 441 | 00000 442 | 00000 443 | -------------------------------------------------------------------------------- /sva/vector_top_sva.sv: -------------------------------------------------------------------------------- 1 | //======================================================= 2 | // X Checks 3 | //======================================================= 4 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(valid_in)) 5 | else $error("x-check:TOP: valid_in"); 6 | 7 | assert property (@(posedge clk) disable iff(!rst_n) valid_in |-> ~$isunknown(|instr_in)) 8 | else $error("x-check:TOP: instr_in"); 9 | 10 | assert property (@(posedge clk) disable iff(!rst_n) ~$isunknown(pop)) 11 | else $error("x-check:TOP: pop"); 12 | //======================================================= 13 | // Properties 14 | //======================================================= 15 | assert property (@(posedge clk) disable iff(!rst_n) (valid_in & ~instr_in.reconfigure & instr_in.fu == `MEM_FU) |-> 16 | instr_in.microop inside { 17 | 7'b0000000, 18 | 7'b0000000, 19 | 7'b0000100, 20 | 7'b0001000, 21 | 7'b0100000, 22 | 7'b0100000, 23 | 7'b0100100, 24 | 7'b0101000, 25 | 7'b0110000, 26 | 7'b0110000, 27 | 7'b0110000, 28 | 7'b0110000, 29 | 7'b0110100, 30 | 7'b0110100, 31 | 7'b0111000, 32 | 7'b0111000, 33 | 7'b1000000, 34 | 7'b1000000, 35 | 7'b1000001, 36 | 7'b1000001, 37 | 7'b1000010, 38 | 7'b1000100, 39 | 7'b1000110, 40 | 7'b1001000, 41 | 7'b1001001, 42 | 7'b1001010, 43 | 7'b1010011, 44 | 7'b1100000, 45 | 7'b1100000, 46 | 7'b1100001, 47 | 7'b1100001, 48 | 7'b1100010, 49 | 7'b1100100, 50 | 7'b1100110, 51 | 7'b1101000, 52 | 7'b1101001, 53 | 7'b1101010, 54 | 7'b1110000, 55 | 7'b1110000, 56 | 7'b1110001, 57 | 7'b1110001, 58 | 7'b1110010, 59 | 7'b1110011, 60 | 7'b1110100, 61 | 7'b1110110, 62 | 7'b1111000, 63 | 7'b1111001, 64 | 7'b1111010 65 | } 66 | ) else $error("Assertion:TOP: invalid microop for MEM_FU"); 67 | 68 | // Only a sample of pseudo FPU instructions are present, mainly used for performance evaluations 69 | assert property (@(posedge clk) disable iff(!rst_n) (valid_in & ~instr_in.reconfigure & instr_in.fu == `FP_FU) |-> 70 | instr_in.microop inside {7'b0000001, 7'b0000010, 7'b0000011} 71 | ) else $error("Assertion:TOP: invalid microop for FP_FU"); 72 | 73 | assert property (@(posedge clk) disable iff(!rst_n) (valid_in & ~instr_in.reconfigure & instr_in.fu == `INT_FU) |-> 74 | instr_in.microop inside { 75 | 7'b0000001, 76 | 7'b0000010, 77 | 7'b0000011, 78 | 7'b0000100, 79 | 7'b0000101, 80 | 7'b0000110, 81 | 7'b0000111, 82 | 7'b0001000, 83 | 7'b0001001, 84 | 7'b0001010, 85 | 7'b0001011, 86 | 7'b0001100, 87 | 7'b0001101, 88 | 7'b0001110, 89 | 7'b0001111, 90 | 7'b0010000, 91 | 7'b0010001, 92 | 7'b0010010, 93 | 7'b0010011, 94 | 7'b0010100, 95 | 7'b0010101, 96 | 7'b0010110, 97 | 7'b0010111, 98 | 7'b0011000, 99 | 7'b0011001, 100 | 7'b0011010, 101 | 7'b0011011, 102 | 7'b0011100, 103 | 7'b0011101, 104 | 7'b0011110, 105 | 7'b0100000, 106 | 7'b0100001, 107 | 7'b0100010, 108 | 7'b0100011, 109 | 7'b1000000, 110 | 7'b1000001, 111 | 7'b1000010, 112 | 7'b1000011 113 | } 114 | ) else $error("Assertion:TOP: invalid microop for INT_FU"); 115 | 116 | assert property (@(posedge clk) disable iff(!rst_n) valid_in |-> (instr_in.fu != `FXP_FU) 117 | ) else $error("Assertion:TOP: Fixed Point is current not supported"); 118 | 119 | assert property (@(posedge clk) disable iff(!rst_n) (valid_in & (instr_in.fu == `FXP_FU)) |-> (instr_in.microop != 7'b1111111) 120 | ) else $error("Assertion:TOP: Illegal encoding: This is used to denote a bubble cycle in the simulator, should not have reached the datapath"); -------------------------------------------------------------------------------- /rtl/vector/v_fp_alu.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info Vector Floating Point Unit 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | */ 7 | `ifdef MODEL_TECH 8 | `include "vstructs.sv" 9 | `endif 10 | module v_fp_alu #( 11 | parameter int DATA_WIDTH = 32 , 12 | parameter int MICROOP_WIDTH = 5 , 13 | parameter int VECTOR_TICKET_BITS = 5 , 14 | parameter int VECTOR_LANE_NUM = 1 , 15 | parameter int EX1_W = 160, 16 | parameter int EX2_W = 96 , 17 | parameter int EX3_W = 96 , 18 | parameter int EX4_W = 32 19 | ) ( 20 | input logic clk , 21 | input logic rst_n , 22 | input logic valid_i , 23 | input logic [ DATA_WIDTH-1:0] data_a_ex1_i , 24 | input logic [ DATA_WIDTH-1:0] data_b_ex1_i , 25 | input logic [ DATA_WIDTH-1:0] imm_ex1_i , 26 | input logic [MICROOP_WIDTH-1:0] microop_i , 27 | input logic mask_i , 28 | // Result Ex1 Out 29 | output logic ready_res_ex1_o, 30 | output logic [ EX1_W-1:0] result_ex1_o , 31 | // EX2 Data In 32 | input logic [ EX1_W-1:0] data_ex2_i , 33 | input logic mask_ex2_i , 34 | // Result EX2 Out 35 | output logic ready_res_ex2_o, 36 | output logic [ EX2_W-1:0] result_ex2_o , 37 | // EX3 Data In 38 | input logic [ EX2_W-1:0] data_ex3_i , 39 | input logic mask_ex3_i , 40 | // Result EX3 Out 41 | output logic ready_res_ex3_o, 42 | output logic [ EX3_W-1:0] result_ex3_o , 43 | // EX4 Data In 44 | input logic [ EX3_W-1:0] data_ex4_i , 45 | input logic mask_ex4_i , 46 | // Result EX4 Out 47 | output logic ready_res_ex4_o, 48 | output logic [ EX4_W-1:0] result_ex4_o 49 | ); 50 | logic [MICROOP_WIDTH-1:0] microop_fp_ex2; 51 | logic [ DATA_WIDTH-1:0] lut_res_tan ; 52 | logic [ DATA_WIDTH-1:0] lut_res_sig ; 53 | logic [ DATA_WIDTH-1:0] lut_res_cos ; 54 | logic [ EX1_W-1:0] result_fp_ex1 ; 55 | logic [ EX2_W-1:0] result_fp_ex2 ; 56 | logic [ EX3_W-1:0] result_fp_ex3 ; 57 | logic [ EX4_W-1:0] result_fp_ex4 ; 58 | logic valid_fp_ex1 ; 59 | logic valid_fp_ex2 ; 60 | logic valid_fp_ex3 ; 61 | logic valid_fp_ex4 ; 62 | 63 | assign lut_res_tan = '0; 64 | assign lut_res_sig = '0; 65 | assign lut_res_cos = '0; 66 | always_comb begin 67 | case (microop_i) 68 | 7'b0100000 : begin 69 | // VTAN 70 | result_fp_ex1 = lut_res_tan; 71 | valid_fp_ex1 = valid_i; 72 | end 73 | 7'b0100001 : begin 74 | // VSIN 75 | result_fp_ex1 = lut_res_sig; 76 | valid_fp_ex1 = valid_i; 77 | end 78 | 7'b0100010 : begin 79 | // VCOS 80 | result_fp_ex1 = lut_res_cos; 81 | valid_fp_ex1 = valid_i; 82 | end 83 | default : begin 84 | result_fp_ex1 = 'x; 85 | valid_fp_ex1 = 1'b0; 86 | end 87 | endcase 88 | end 89 | always_ff @(posedge clk) begin 90 | if (valid_fp_ex1) begin 91 | microop_fp_ex2 <= microop_i; 92 | end 93 | end 94 | always_ff @(posedge clk or negedge rst_n) begin 95 | if(~rst_n) begin 96 | valid_fp_ex2 <= 0; 97 | end else begin 98 | valid_fp_ex2 <= valid_fp_ex1; 99 | end 100 | end 101 | //----------------------------------------------- 102 | //EX2 103 | //----------------------------------------------- 104 | always_comb begin 105 | case (microop_fp_ex2) 106 | 7'b0100000 : begin 107 | // VTAN 108 | result_fp_ex2 = data_ex2_i + data_ex2_i; 109 | end 110 | 7'b0100001 : begin 111 | // VSIN 112 | result_fp_ex2 = data_ex2_i - data_ex2_i; 113 | end 114 | 7'b0100010 : begin 115 | // VCOS 116 | result_fp_ex2 = data_ex2_i + data_ex2_i; 117 | end 118 | default : begin 119 | result_fp_ex2 = 'x; 120 | end 121 | endcase 122 | end 123 | 124 | assign valid_fp_ex3 = 1'b0; 125 | assign valid_fp_ex4 = 1'b0; 126 | //================================================ 127 | // Outputs 128 | //================================================ 129 | // EX1 Out 130 | assign ready_res_ex1_o = 1'b0; //no fp finishes in 1 cycle 131 | assign result_ex1_o = {EX1_W{mask_i}} & result_fp_ex1; 132 | // EX2 Out 133 | assign ready_res_ex2_o = valid_fp_ex2; //indicate ready data 134 | assign result_ex2_o = {EX2_W{mask_ex2_i}} & result_fp_ex2; 135 | // EX3 Out 136 | assign ready_res_ex3_o = valid_fp_ex3; //indicate ready data 137 | assign result_ex3_o = {EX3_W{mask_ex3_i}} & result_fp_ex3; 138 | // EX4 Out 139 | assign ready_res_ex4_o = valid_fp_ex4; //indicate ready data 140 | assign result_ex4_o = {EX4_W{mask_ex4_i}} & result_fp_ex4; 141 | 142 | endmodule // v_fp_alu -------------------------------------------------------------------------------- /rtl/shared/fifo_dual_ported.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info Dual Ported FIFO 3 | * @info Sub-Modules: and_or_mux.sv 4 | * 5 | * @author VLSI Lab, EE dept., Democritus University of Thrace 6 | * 7 | * @brief Instructions assigned: Branches, Shifts, Compares 8 | * 9 | * @note Priority is given to the input interface 1 : If 2 pushes simultaneously, push_data_1 will get the first available slot 10 | * @note Output Interfaces are linked. Can not pop_2 without pop_1 11 | * 12 | * @param DW : # of Data Bits (default 16 bits) 13 | * @param DEPTH : # of Entries (default 4 entries) (if DEPTH==1, then 50% throughput) 14 | */ 15 | module fifo_dual_ported #( 16 | parameter int DW = 16, 17 | parameter int DEPTH = 4 18 | ) ( 19 | input logic clk , 20 | input logic rst , 21 | //Flush Interface 22 | input logic valid_flush, 23 | //input interface 1 24 | input logic push_1 , 25 | output logic ready_1 , 26 | input logic [DW-1:0] push_data_1, 27 | //input interface 2 28 | input logic push_2 , 29 | output logic ready_2 , 30 | input logic [DW-1:0] push_data_2, 31 | //output interface 1 32 | output logic [DW-1:0] pop_data_1 , 33 | output logic valid_1 , 34 | input logic pop_1 , 35 | //output interface 2 36 | output logic [DW-1:0] pop_data_2 , 37 | output logic valid_2 , 38 | input logic pop_2 39 | ); 40 | 41 | // #Internal Signals# 42 | logic[DEPTH-1:0][DW-1:0] memory; 43 | logic[DEPTH-1:0] tail, tail_plus; 44 | logic[DEPTH-1:0] head, head_plus; 45 | logic[DEPTH :0] status_cnt; 46 | logic[3 :0] shift_vector; 47 | logic double_push, single_push, double_pop, single_pop; 48 | logic shift_left_double, shift_left_single; 49 | logic shift_right_double, shift_right_single; 50 | 51 | assign valid_1 = ~status_cnt[0]; 52 | assign valid_2 = ~status_cnt[1] & ~status_cnt[0]; 53 | assign ready_1 = ~status_cnt[DEPTH]; 54 | assign ready_2 = ~status_cnt[DEPTH] & ~status_cnt[DEPTH-1]; 55 | //intermidiate logic 56 | assign single_push = push_1 | push_2; 57 | assign double_push = push_1 & push_2; 58 | assign single_pop = pop_1 | pop_2; 59 | assign double_pop = pop_1 & pop_2; 60 | 61 | assign shift_left_double = double_push & ~single_pop; 62 | assign shift_left_single = ((double_push & single_pop) | (single_push & ~single_pop)) & ~shift_left_double; 63 | assign shift_right_double = double_pop & ~single_push; 64 | assign shift_right_single = ((double_pop & single_push) | (single_pop & ~single_push)) & ~shift_right_double; 65 | assign shift_vector = {shift_left_double,shift_left_single,shift_right_double,shift_right_single}; 66 | // Tail Pointer update (one-hot shifting pointers) 67 | always_ff @ (posedge clk, posedge rst) begin: TailManagement 68 | if (rst) begin 69 | tail <= 1; 70 | end else if (valid_flush) begin 71 | tail <= 1; 72 | end else begin 73 | // push pointer 74 | if (double_push) begin 75 | tail <= {tail[DEPTH-3:0], tail[DEPTH-1:DEPTH-2]}; 76 | end else if(single_push) begin 77 | tail <= {tail[DEPTH-2:0], tail[DEPTH-1]}; 78 | end 79 | end 80 | end 81 | assign tail_plus = {tail[DEPTH-2:0], tail[DEPTH-1]}; 82 | // Head Pointer update (one-hot shifting pointers) 83 | always_ff @ (posedge clk, posedge rst) begin: HeadManagement 84 | if (rst) begin 85 | head <= 1; 86 | end else if (valid_flush) begin 87 | head <= 1; 88 | end else begin 89 | // pop pointer 90 | if (double_pop) begin 91 | head <= {head[DEPTH-3:0], head[DEPTH-1:DEPTH-2]}; 92 | end else if(single_pop) begin 93 | head <= {head[DEPTH-2:0], head[DEPTH-1]}; 94 | end 95 | end 96 | end 97 | assign head_plus = {head[DEPTH-2:0], head[DEPTH-1]}; 98 | // Status Counter (onehot coded) 99 | always_ff @ (posedge clk, posedge rst) begin: ff_status_cnt 100 | if (rst) begin 101 | status_cnt <= 1; 102 | end else if (valid_flush) begin 103 | status_cnt <= 1; 104 | end else begin 105 | case (shift_vector) 106 | 4'b1000 : status_cnt <= {status_cnt[DEPTH-2:0], 2'b0}; 107 | 4'b0100 : status_cnt <= {status_cnt[DEPTH-1:0], 1'b0}; 108 | 4'b0010 : status_cnt <= {2'b0, status_cnt[DEPTH:2]}; 109 | 4'b0001 : status_cnt <= {1'b0, status_cnt[DEPTH:1]}; 110 | default : status_cnt <= status_cnt; 111 | endcase 112 | end 113 | end 114 | // Data write (push) 115 | // address decoding needed for onehot push pointer 116 | always_ff @ (posedge clk) begin: ff_reg_dec 117 | for (int i=0; i < DEPTH; i++) begin 118 | if(double_push) begin 119 | if(push_1 && tail[i]) begin 120 | memory[i] <= push_data_1; 121 | end else if(push_2 && tail_plus[i]) begin 122 | memory[i] <= push_data_2; 123 | end 124 | end else begin 125 | if(push_1 && tail[i]) begin 126 | memory[i] <= push_data_1; 127 | end else if(push_2 && tail[i]) begin 128 | memory[i] <= push_data_2; 129 | end 130 | end 131 | end 132 | end 133 | 134 | and_or_mux #( 135 | .INPUTS (DEPTH), 136 | .DW (DW) 137 | ) 138 | mux_out_1 ( 139 | .data_in (memory), 140 | .sel (head), 141 | .data_out (pop_data_1) 142 | ); 143 | 144 | and_or_mux #( 145 | .INPUTS (DEPTH), 146 | .DW (DW) 147 | ) 148 | mux_out_2 ( 149 | .data_in (memory), 150 | .sel (head_plus), 151 | .data_out (pop_data_2) 152 | ); 153 | 154 | assert property (@(posedge clk) disable iff(rst) pop_2 |-> pop_1) else $error(1, "DP FIFO:Illegal Scenario"); 155 | endmodule 156 | -------------------------------------------------------------------------------- /vector_simulator/decoder_results/instrs/microop_output.txt: -------------------------------------------------------------------------------- 1 | 0000000 2 | 1000000 3 | 1000000 4 | 0000001 5 | 1111111 6 | 1111111 7 | 1111111 8 | 1111111 9 | 1000000 10 | 1000000 11 | 0000001 12 | 1111111 13 | 1111111 14 | 1111111 15 | 1111111 16 | 1000000 17 | 1000000 18 | 0000001 19 | 1111111 20 | 1111111 21 | 1111111 22 | 1111111 23 | 1000000 24 | 1000000 25 | 0000001 26 | 1111111 27 | 1111111 28 | 1111111 29 | 1111111 30 | 1000000 31 | 1000000 32 | 0000001 33 | 1111111 34 | 1111111 35 | 1111111 36 | 1111111 37 | 1000000 38 | 1000000 39 | 0000001 40 | 1111111 41 | 1111111 42 | 1111111 43 | 1111111 44 | 1000000 45 | 1000000 46 | 0000001 47 | 1111111 48 | 1111111 49 | 1111111 50 | 1111111 51 | 1000000 52 | 1000000 53 | 0000001 54 | 1111111 55 | 1111111 56 | 1111111 57 | 1111111 58 | 1000000 59 | 1000000 60 | 0000001 61 | 1111111 62 | 1111111 63 | 1111111 64 | 1111111 65 | 1000000 66 | 1000000 67 | 0000001 68 | 1111111 69 | 1111111 70 | 1111111 71 | 1111111 72 | 1000000 73 | 1000000 74 | 0000001 75 | 1111111 76 | 1111111 77 | 1111111 78 | 1111111 79 | 1000000 80 | 1000000 81 | 0000001 82 | 1111111 83 | 1111111 84 | 1111111 85 | 1111111 86 | 1000000 87 | 1000000 88 | 0000001 89 | 1111111 90 | 1111111 91 | 1111111 92 | 1111111 93 | 1000000 94 | 1000000 95 | 0000001 96 | 1111111 97 | 1111111 98 | 1111111 99 | 1111111 100 | 1000000 101 | 1000000 102 | 0000001 103 | 1111111 104 | 1111111 105 | 1111111 106 | 1111111 107 | 1000000 108 | 1000000 109 | 0000001 110 | 1111111 111 | 1111111 112 | 1111111 113 | 1111111 114 | 1000000 115 | 1000000 116 | 0000001 117 | 1111111 118 | 1111111 119 | 1111111 120 | 1111111 121 | 1000000 122 | 1000000 123 | 0000001 124 | 1111111 125 | 1111111 126 | 1111111 127 | 1111111 128 | 1000000 129 | 1000000 130 | 0000001 131 | 1111111 132 | 1111111 133 | 1111111 134 | 1111111 135 | 1000000 136 | 1000000 137 | 0000001 138 | 1111111 139 | 1111111 140 | 1111111 141 | 1111111 142 | 1000000 143 | 1000000 144 | 0000001 145 | 1111111 146 | 1111111 147 | 1111111 148 | 1111111 149 | 1000000 150 | 1000000 151 | 0000001 152 | 1111111 153 | 1111111 154 | 1111111 155 | 1111111 156 | 1000000 157 | 1000000 158 | 0000001 159 | 1111111 160 | 1111111 161 | 1111111 162 | 1111111 163 | 1000000 164 | 1000000 165 | 0000001 166 | 1111111 167 | 1111111 168 | 1111111 169 | 1111111 170 | 1000000 171 | 1000000 172 | 0000001 173 | 1111111 174 | 1111111 175 | 1111111 176 | 1111111 177 | 1000000 178 | 1000000 179 | 0000001 180 | 1111111 181 | 1111111 182 | 1111111 183 | 1111111 184 | 1000000 185 | 1000000 186 | 0000001 187 | 1111111 188 | 1111111 189 | 1111111 190 | 1111111 191 | 1000000 192 | 1000000 193 | 0000001 194 | 1111111 195 | 1111111 196 | 1111111 197 | 1111111 198 | 1000000 199 | 1000000 200 | 0000001 201 | 1111111 202 | 1111111 203 | 1111111 204 | 1111111 205 | 1000000 206 | 1000000 207 | 0000001 208 | 1111111 209 | 1111111 210 | 1111111 211 | 1111111 212 | 1000000 213 | 1000000 214 | 0000001 215 | 1111111 216 | 1111111 217 | 1111111 218 | 1111111 219 | 1000000 220 | 1000000 221 | 0000001 222 | 1111111 223 | 1111111 224 | 1111111 225 | 1111111 226 | 1000000 227 | 1000000 228 | 0000001 229 | 1111111 230 | 1111111 231 | 1111111 232 | 1111111 233 | 1000000 234 | 1000000 235 | 0000001 236 | 1111111 237 | 1111111 238 | 1111111 239 | 1111111 240 | 1000000 241 | 1000000 242 | 0000001 243 | 1111111 244 | 1111111 245 | 1111111 246 | 1111111 247 | 1000000 248 | 1000000 249 | 0000001 250 | 1111111 251 | 1111111 252 | 1111111 253 | 1111111 254 | 1000000 255 | 1000000 256 | 0000001 257 | 1111111 258 | 1111111 259 | 1111111 260 | 1111111 261 | 1000000 262 | 1000000 263 | 0000001 264 | 1111111 265 | 1111111 266 | 1111111 267 | 1111111 268 | 1000000 269 | 1000000 270 | 0000001 271 | 1111111 272 | 1111111 273 | 1111111 274 | 1111111 275 | 1000000 276 | 1000000 277 | 0000001 278 | 1111111 279 | 1111111 280 | 1111111 281 | 1111111 282 | 1000000 283 | 1000000 284 | 0000001 285 | 1111111 286 | 1111111 287 | 1111111 288 | 1111111 289 | 1000000 290 | 1000000 291 | 0000001 292 | 1111111 293 | 1111111 294 | 1111111 295 | 1111111 296 | 1000000 297 | 1000000 298 | 0000001 299 | 1111111 300 | 1111111 301 | 1111111 302 | 1111111 303 | 1000000 304 | 1000000 305 | 0000001 306 | 1111111 307 | 1111111 308 | 1111111 309 | 1111111 310 | 1000000 311 | 1000000 312 | 0000001 313 | 1111111 314 | 1111111 315 | 1111111 316 | 1111111 317 | 1000000 318 | 1000000 319 | 0000001 320 | 1111111 321 | 1111111 322 | 1111111 323 | 1111111 324 | 1000000 325 | 1000000 326 | 0000001 327 | 1111111 328 | 1111111 329 | 1111111 330 | 1111111 331 | 1000000 332 | 1000000 333 | 0000001 334 | 1111111 335 | 1111111 336 | 1111111 337 | 1111111 338 | 1000000 339 | 1000000 340 | 0000001 341 | 1111111 342 | 1111111 343 | 1111111 344 | 1111111 345 | 1000000 346 | 1000000 347 | 0000001 348 | 1111111 349 | 1111111 350 | 1111111 351 | 1111111 352 | 1000000 353 | 1000000 354 | 0000001 355 | 1111111 356 | 1111111 357 | 1111111 358 | 1111111 359 | 1000000 360 | 1000000 361 | 0000001 362 | 1111111 363 | 1111111 364 | 1111111 365 | 1111111 366 | 1000000 367 | 1000000 368 | 0000001 369 | 1111111 370 | 1111111 371 | 1111111 372 | 1111111 373 | 1000000 374 | 1000000 375 | 0000001 376 | 1111111 377 | 1111111 378 | 1111111 379 | 1111111 380 | 1000000 381 | 1000000 382 | 0000001 383 | 1111111 384 | 1111111 385 | 1111111 386 | 1111111 387 | 1000000 388 | 1000000 389 | 0000001 390 | 1111111 391 | 1111111 392 | 1111111 393 | 1111111 394 | 1000000 395 | 1000000 396 | 0000001 397 | 1111111 398 | 1111111 399 | 1111111 400 | 1111111 401 | 1000000 402 | 1000000 403 | 0000001 404 | 1111111 405 | 1111111 406 | 1111111 407 | 1111111 408 | 1000000 409 | 1000000 410 | 0000001 411 | 1111111 412 | 1111111 413 | 1111111 414 | 1111111 415 | 1000000 416 | 1000000 417 | 0000001 418 | 1111111 419 | 1111111 420 | 1111111 421 | 1111111 422 | 1000000 423 | 1000000 424 | 0000001 425 | 1111111 426 | 1111111 427 | 1111111 428 | 1111111 429 | 1000000 430 | 1000000 431 | 0000001 432 | 1111111 433 | 1111111 434 | 1111111 435 | 1111111 436 | 1000000 437 | 1000000 438 | 0000001 439 | 1111111 440 | 1111111 441 | 1111111 442 | 1111111 443 | -------------------------------------------------------------------------------- /vector_simulator/examples/vvadd/decoder_results/instrs/microop_output.txt: -------------------------------------------------------------------------------- 1 | 0000000 2 | 1000000 3 | 1000000 4 | 0000001 5 | 1111111 6 | 1111111 7 | 1111111 8 | 1111111 9 | 1000000 10 | 1000000 11 | 0000001 12 | 1111111 13 | 1111111 14 | 1111111 15 | 1111111 16 | 1000000 17 | 1000000 18 | 0000001 19 | 1111111 20 | 1111111 21 | 1111111 22 | 1111111 23 | 1000000 24 | 1000000 25 | 0000001 26 | 1111111 27 | 1111111 28 | 1111111 29 | 1111111 30 | 1000000 31 | 1000000 32 | 0000001 33 | 1111111 34 | 1111111 35 | 1111111 36 | 1111111 37 | 1000000 38 | 1000000 39 | 0000001 40 | 1111111 41 | 1111111 42 | 1111111 43 | 1111111 44 | 1000000 45 | 1000000 46 | 0000001 47 | 1111111 48 | 1111111 49 | 1111111 50 | 1111111 51 | 1000000 52 | 1000000 53 | 0000001 54 | 1111111 55 | 1111111 56 | 1111111 57 | 1111111 58 | 1000000 59 | 1000000 60 | 0000001 61 | 1111111 62 | 1111111 63 | 1111111 64 | 1111111 65 | 1000000 66 | 1000000 67 | 0000001 68 | 1111111 69 | 1111111 70 | 1111111 71 | 1111111 72 | 1000000 73 | 1000000 74 | 0000001 75 | 1111111 76 | 1111111 77 | 1111111 78 | 1111111 79 | 1000000 80 | 1000000 81 | 0000001 82 | 1111111 83 | 1111111 84 | 1111111 85 | 1111111 86 | 1000000 87 | 1000000 88 | 0000001 89 | 1111111 90 | 1111111 91 | 1111111 92 | 1111111 93 | 1000000 94 | 1000000 95 | 0000001 96 | 1111111 97 | 1111111 98 | 1111111 99 | 1111111 100 | 1000000 101 | 1000000 102 | 0000001 103 | 1111111 104 | 1111111 105 | 1111111 106 | 1111111 107 | 1000000 108 | 1000000 109 | 0000001 110 | 1111111 111 | 1111111 112 | 1111111 113 | 1111111 114 | 1000000 115 | 1000000 116 | 0000001 117 | 1111111 118 | 1111111 119 | 1111111 120 | 1111111 121 | 1000000 122 | 1000000 123 | 0000001 124 | 1111111 125 | 1111111 126 | 1111111 127 | 1111111 128 | 1000000 129 | 1000000 130 | 0000001 131 | 1111111 132 | 1111111 133 | 1111111 134 | 1111111 135 | 1000000 136 | 1000000 137 | 0000001 138 | 1111111 139 | 1111111 140 | 1111111 141 | 1111111 142 | 1000000 143 | 1000000 144 | 0000001 145 | 1111111 146 | 1111111 147 | 1111111 148 | 1111111 149 | 1000000 150 | 1000000 151 | 0000001 152 | 1111111 153 | 1111111 154 | 1111111 155 | 1111111 156 | 1000000 157 | 1000000 158 | 0000001 159 | 1111111 160 | 1111111 161 | 1111111 162 | 1111111 163 | 1000000 164 | 1000000 165 | 0000001 166 | 1111111 167 | 1111111 168 | 1111111 169 | 1111111 170 | 1000000 171 | 1000000 172 | 0000001 173 | 1111111 174 | 1111111 175 | 1111111 176 | 1111111 177 | 1000000 178 | 1000000 179 | 0000001 180 | 1111111 181 | 1111111 182 | 1111111 183 | 1111111 184 | 1000000 185 | 1000000 186 | 0000001 187 | 1111111 188 | 1111111 189 | 1111111 190 | 1111111 191 | 1000000 192 | 1000000 193 | 0000001 194 | 1111111 195 | 1111111 196 | 1111111 197 | 1111111 198 | 1000000 199 | 1000000 200 | 0000001 201 | 1111111 202 | 1111111 203 | 1111111 204 | 1111111 205 | 1000000 206 | 1000000 207 | 0000001 208 | 1111111 209 | 1111111 210 | 1111111 211 | 1111111 212 | 1000000 213 | 1000000 214 | 0000001 215 | 1111111 216 | 1111111 217 | 1111111 218 | 1111111 219 | 1000000 220 | 1000000 221 | 0000001 222 | 1111111 223 | 1111111 224 | 1111111 225 | 1111111 226 | 1000000 227 | 1000000 228 | 0000001 229 | 1111111 230 | 1111111 231 | 1111111 232 | 1111111 233 | 1000000 234 | 1000000 235 | 0000001 236 | 1111111 237 | 1111111 238 | 1111111 239 | 1111111 240 | 1000000 241 | 1000000 242 | 0000001 243 | 1111111 244 | 1111111 245 | 1111111 246 | 1111111 247 | 1000000 248 | 1000000 249 | 0000001 250 | 1111111 251 | 1111111 252 | 1111111 253 | 1111111 254 | 1000000 255 | 1000000 256 | 0000001 257 | 1111111 258 | 1111111 259 | 1111111 260 | 1111111 261 | 1000000 262 | 1000000 263 | 0000001 264 | 1111111 265 | 1111111 266 | 1111111 267 | 1111111 268 | 1000000 269 | 1000000 270 | 0000001 271 | 1111111 272 | 1111111 273 | 1111111 274 | 1111111 275 | 1000000 276 | 1000000 277 | 0000001 278 | 1111111 279 | 1111111 280 | 1111111 281 | 1111111 282 | 1000000 283 | 1000000 284 | 0000001 285 | 1111111 286 | 1111111 287 | 1111111 288 | 1111111 289 | 1000000 290 | 1000000 291 | 0000001 292 | 1111111 293 | 1111111 294 | 1111111 295 | 1111111 296 | 1000000 297 | 1000000 298 | 0000001 299 | 1111111 300 | 1111111 301 | 1111111 302 | 1111111 303 | 1000000 304 | 1000000 305 | 0000001 306 | 1111111 307 | 1111111 308 | 1111111 309 | 1111111 310 | 1000000 311 | 1000000 312 | 0000001 313 | 1111111 314 | 1111111 315 | 1111111 316 | 1111111 317 | 1000000 318 | 1000000 319 | 0000001 320 | 1111111 321 | 1111111 322 | 1111111 323 | 1111111 324 | 1000000 325 | 1000000 326 | 0000001 327 | 1111111 328 | 1111111 329 | 1111111 330 | 1111111 331 | 1000000 332 | 1000000 333 | 0000001 334 | 1111111 335 | 1111111 336 | 1111111 337 | 1111111 338 | 1000000 339 | 1000000 340 | 0000001 341 | 1111111 342 | 1111111 343 | 1111111 344 | 1111111 345 | 1000000 346 | 1000000 347 | 0000001 348 | 1111111 349 | 1111111 350 | 1111111 351 | 1111111 352 | 1000000 353 | 1000000 354 | 0000001 355 | 1111111 356 | 1111111 357 | 1111111 358 | 1111111 359 | 1000000 360 | 1000000 361 | 0000001 362 | 1111111 363 | 1111111 364 | 1111111 365 | 1111111 366 | 1000000 367 | 1000000 368 | 0000001 369 | 1111111 370 | 1111111 371 | 1111111 372 | 1111111 373 | 1000000 374 | 1000000 375 | 0000001 376 | 1111111 377 | 1111111 378 | 1111111 379 | 1111111 380 | 1000000 381 | 1000000 382 | 0000001 383 | 1111111 384 | 1111111 385 | 1111111 386 | 1111111 387 | 1000000 388 | 1000000 389 | 0000001 390 | 1111111 391 | 1111111 392 | 1111111 393 | 1111111 394 | 1000000 395 | 1000000 396 | 0000001 397 | 1111111 398 | 1111111 399 | 1111111 400 | 1111111 401 | 1000000 402 | 1000000 403 | 0000001 404 | 1111111 405 | 1111111 406 | 1111111 407 | 1111111 408 | 1000000 409 | 1000000 410 | 0000001 411 | 1111111 412 | 1111111 413 | 1111111 414 | 1111111 415 | 1000000 416 | 1000000 417 | 0000001 418 | 1111111 419 | 1111111 420 | 1111111 421 | 1111111 422 | 1000000 423 | 1000000 424 | 0000001 425 | 1111111 426 | 1111111 427 | 1111111 428 | 1111111 429 | 1000000 430 | 1000000 431 | 0000001 432 | 1111111 433 | 1111111 434 | 1111111 435 | 1111111 436 | 1000000 437 | 1000000 438 | 0000001 439 | 1111111 440 | 1111111 441 | 1111111 442 | 1111111 443 | -------------------------------------------------------------------------------- /rtl/shared/structs.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * @author VLSI Lab, EE dept., Democritus University of Thrace 4 | * 5 | */ 6 | //Packet Fetched from IF 7 | typedef struct packed { 8 | logic [31 : 0] pc ; 9 | logic [31 : 0] data ; 10 | logic taken_branch; 11 | } fetched_packet; 12 | //Internal ROB configuration (per entry) 13 | typedef struct packed { 14 | logic valid ; 15 | logic pending ; 16 | logic flushed ; 17 | logic valid_dest ; 18 | logic [ 5 : 0] lreg ; 19 | logic [ 5 : 0] preg ; 20 | logic [ 5 : 0] ppreg ; 21 | logic [ 4 : 0] microoperation ; 22 | logic valid_exception; //Clear reorder buffer on exception 23 | logic [ 3 : 0] cause ; //redirect depending on cause 24 | logic is_store ; 25 | logic [31 : 0] address ; 26 | logic [31 : 0] pc ; 27 | } rob_entry; 28 | //--------------------------------------------------------------------------------------- 29 | //Struct from IS stage to request new entries(2x max per cycle) 30 | typedef struct packed { 31 | logic valid_request_1 ; 32 | logic valid_dest_1 ; 33 | logic [5 : 0] lreg_1 ; 34 | logic [5 : 0] preg_1 ; 35 | logic [5 : 0] ppreg_1 ; 36 | logic [4 : 0] microoperation_1; 37 | logic [31: 0] pc_1 ; 38 | 39 | logic valid_request_2 ; 40 | logic valid_dest_2 ; 41 | logic [5 : 0] lreg_2 ; 42 | logic [5 : 0] preg_2 ; 43 | logic [5 : 0] ppreg_2 ; 44 | logic [4 : 0] microoperation_2; 45 | logic [31: 0] pc_2 ; 46 | } new_entries; 47 | //--------------------------------------------------------------------------------------- 48 | //Struct to Update the Architectural Register File 49 | typedef struct packed { 50 | logic valid_commit; 51 | logic valid_write ; 52 | logic flushed ; 53 | logic [ 5 : 0] ldst ; 54 | logic [ 5 : 0] pdst ; 55 | logic [ 5 : 0] ppdst ; 56 | logic [31 : 0] data ; 57 | logic [ 2 : 0] ticket ; 58 | logic [31 : 0] pc ; 59 | } writeback_toARF; 60 | //--------------------------------------------------------------------------------------- 61 | //Struct from EX stage to update internal ROB status 62 | typedef struct packed { 63 | logic valid ; 64 | logic [ 5 : 0] destination ; 65 | logic [ 2 : 0] ticket ; 66 | logic [31 : 0] data ; 67 | logic valid_exception; 68 | logic [ 3 : 0] cause ; 69 | } ex_update; 70 | //--------------------------------------------------------------------------------------- 71 | //Struct towards Issue stage 72 | typedef struct packed { 73 | logic is_full ; 74 | logic two_empty; 75 | logic [2 : 0] ticket ; 76 | } to_issue; 77 | //--------------------------------------------------------------------------------------- 78 | //Struct Carrying a decoded Instruction 79 | typedef struct packed { 80 | logic [31 : 0] pc ; 81 | logic [ 5 : 0] source1 ; 82 | logic source1_pc ; 83 | logic [ 5 : 0] source2 ; 84 | logic source2_immediate; 85 | logic [31 : 0] immediate ; 86 | logic [ 5 : 0] source3 ; 87 | logic [ 5 : 0] destination ; 88 | logic [ 1 : 0] functional_unit ; 89 | logic [ 4 : 0] microoperation ; 90 | logic [ 2 : 0] rm ; 91 | logic is_branch ; 92 | logic is_vector ; 93 | logic is_valid ; 94 | } decoded_instr; 95 | //--------------------------------------------------------------------------------------- 96 | //Struct Carrying a decoded and Renamed Instruction 97 | typedef struct packed { 98 | logic [31 : 0] pc ; 99 | logic [ 5 : 0] source1 ; 100 | logic source1_pc ; 101 | logic [ 5 : 0] source2 ; 102 | logic source2_immediate; 103 | logic [31 : 0] immediate ; 104 | logic [ 5 : 0] source3 ; 105 | logic [ 5 : 0] destination ; 106 | logic [ 1 : 0] functional_unit ; 107 | logic [ 4 : 0] microoperation ; 108 | logic [ 3 : 0] ticket ; 109 | logic [ 2 : 0] rm ; 110 | logic [ 1 : 0] rat_id ; 111 | logic is_branch ; 112 | logic is_vector ; 113 | logic is_valid ; 114 | } renamed_instr; 115 | //--------------------------------------------------------------------------------------- 116 | //Scoreboard Bookkeeping (per entry) 117 | typedef struct packed { 118 | logic pending; 119 | logic [1 : 0] fu ; 120 | logic [2 : 0] ticket ; 121 | logic in_rob ; 122 | }scoreboard_entry; 123 | //--------------------------------------------------------------------------------------- 124 | //FU Busy Configuration(per Entry) 125 | typedef struct packed { 126 | logic busy; 127 | }fu_entry; 128 | //-------------------------- 129 | //to_Execution Stage 130 | typedef struct packed { 131 | logic valid ; 132 | logic [31 : 0] pc ; 133 | logic [ 5 : 0] destination ; 134 | 135 | logic [31 : 0] data1 ; 136 | 137 | logic [31 : 0] data2 ; 138 | 139 | logic [31 : 0] immediate ; 140 | logic [ 1 : 0] functional_unit; 141 | logic [ 4 : 0] microoperation ; 142 | logic [ 2 : 0] rm ; 143 | logic [ 1 : 0] rat_id ; 144 | logic [ 2 : 0] ticket ; 145 | }to_execution; 146 | //--------------------------------------------------------------------------------------- 147 | typedef struct packed { 148 | logic valid_jump ; 149 | logic jump_taken ; 150 | logic is_comp ; 151 | logic [ 1 : 0] rat_id ; 152 | logic [31 : 0] orig_pc ; 153 | logic [31 : 0] jump_address; 154 | logic [ 2 : 0] ticket ; 155 | } predictor_update; 156 | //--------------------------------------------------------------------------------------- -------------------------------------------------------------------------------- /rtl/vector/vstructs.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * @author VLSI Lab, EE dept., Democritus University of Thrace 4 | * 5 | */ 6 | `ifdef MODEL_TECH 7 | `include "vmacros.sv" 8 | `endif 9 | localparam DUMMY_VECTOR_LANES = 8; 10 | localparam DUMMY_REQ_DATA_WIDTH = 512; 11 | //--------------------------------------------------------------------------------------- 12 | //to Vector Pipeline 13 | typedef struct packed { 14 | logic valid ; 15 | 16 | logic [ 4:0] dst ; 17 | logic [ 4:0] src1 ; 18 | logic [ 4:0] src2 ; 19 | 20 | logic [ 31:0] data1 ; 21 | logic [ 31:0] data2 ; 22 | 23 | logic reconfigure; 24 | logic [ 31:0] immediate ; 25 | logic [ 1:0] fu ; 26 | logic [ 6:0] microop ; 27 | logic [ 1:0] use_mask ; 28 | 29 | // [$clog2(VECTOR_REGISTERS*VECTOR_LANES):0] 30 | logic [$clog2(32*DUMMY_VECTOR_LANES):0] maxvl ; 31 | logic [$clog2(32*DUMMY_VECTOR_LANES):0] vl ; 32 | } to_vector; 33 | //-------------------------------------- 34 | //Remapped Vector Instruction 35 | typedef struct packed { 36 | logic valid ; 37 | 38 | logic [ 4:0] dst ; 39 | logic dst_iszero ; 40 | logic [ 4:0] src1 ; 41 | logic src1_iszero; 42 | logic [ 4:0] src2 ; 43 | logic src2_iszero; 44 | logic [ 4:0] mask_src ; 45 | 46 | logic [ 31:0] data1 ; 47 | logic [ 31:0] data2 ; 48 | 49 | logic reconfigure; 50 | logic [ 4:0] ticket ; 51 | logic [ 31:0] immediate ; 52 | logic [ 1:0] fu ; 53 | logic [ 6:0] microop ; 54 | logic use_mask ; 55 | logic [ 1:0] lock ; 56 | 57 | // [$clog2(VECTOR_REGISTERS*VECTOR_LANES):0] 58 | logic [$clog2(32*DUMMY_VECTOR_LANES):0] maxvl ; 59 | logic [$clog2(32*DUMMY_VECTOR_LANES):0] vl ; 60 | } remapped_v_instr; 61 | //-------------------------------------- 62 | //Remapped Memory Vector Instruction 63 | typedef struct packed { 64 | logic valid ; 65 | 66 | logic [ 4:0] dst ; 67 | // logic dst_iszero ; 68 | logic [ 4:0] src1 ; 69 | // logic src1_iszero; 70 | logic [ 4:0] src2 ; 71 | // logic src2_iszero; 72 | 73 | logic [ 31:0] data1 ; 74 | logic [ 31:0] data2 ; 75 | 76 | logic [ 4:0] ticket ; 77 | logic [ 4:0] last_ticket_src1; 78 | logic [ 4:0] last_ticket_src2; 79 | logic [ 31:0] immediate ; 80 | logic [ 6:0] microop ; 81 | logic reconfigure ; 82 | 83 | // [$clog2(VECTOR_REGISTERS*VECTOR_LANES):0] 84 | logic [$clog2(32*DUMMY_VECTOR_LANES):0] maxvl ; 85 | logic [$clog2(32*DUMMY_VECTOR_LANES):0] vl ; 86 | } memory_remapped_v_instr; 87 | //-------------------------------------- 88 | //to_Execution Stage 89 | typedef struct packed { 90 | logic valid ; 91 | logic mask ; 92 | 93 | logic [31:0] data1 ; 94 | logic [31:0] data2 ; 95 | logic [31:0] immediate; 96 | }to_vector_exec; 97 | typedef struct packed { 98 | logic [ 4:0] dst ; 99 | logic [ 4:0] ticket ; 100 | logic [ 1:0] fu ; 101 | logic [ 6:0] microop ; 102 | logic [$clog2(32*DUMMY_VECTOR_LANES):0] vl ; 103 | logic head_uop; 104 | logic end_uop ; 105 | }to_vector_exec_info; 106 | //-------------------------------------- 107 | //Vector memory Request 108 | typedef struct packed { 109 | logic [ 31:0] address; 110 | logic [ 6:0] microop; 111 | logic [$clog2(DUMMY_REQ_DATA_WIDTH/8):0] size ; 112 | logic [ DUMMY_REQ_DATA_WIDTH-1:0] data ; 113 | logic [ $clog2(DUMMY_VECTOR_LANES):0] ticket ; //$clog2(VECTOR_LANES) 114 | }vector_mem_req; 115 | //-------------------------------------- 116 | //Vector memory response 117 | typedef struct packed { 118 | logic [ $clog2(DUMMY_VECTOR_LANES):0] ticket; //$clog2(VECTOR_LANES) 119 | logic [$clog2(DUMMY_REQ_DATA_WIDTH/8):0] size ; //$clog2(REQ_DATA_WIDTH/8) 120 | logic [ DUMMY_REQ_DATA_WIDTH-1:0] data ; //REQ_DATA_WIDTH 121 | }vector_mem_resp; 122 | //-------------------------------------- 123 | //Int Operation Enumaration 124 | typedef enum logic [7-1:0] { 125 | VADD = 7'b0000001, 126 | VADDI = 7'b0000010, 127 | VADDW = 7'b0000011, 128 | VADDIW = 7'b0000100, 129 | VSUB = 7'b0000101, 130 | VSUBW = 7'b0000110, 131 | VMUL = 7'b0000111, 132 | VMULH = 7'b0001000, 133 | VMULHSU = 7'b0001001, 134 | VMULHU = 7'b0001010, 135 | VMULWDN = 7'b0001011, 136 | VDIV = 7'b0001100, 137 | VDIVU = 7'b0001101, 138 | VREM = 7'b0001110, 139 | VREMU = 7'b0001111, 140 | VSLL = 7'b0010000, 141 | VSLLI = 7'b0010001, 142 | VSRA = 7'b0010010, 143 | VSRAI = 7'b0010011, 144 | VSRL = 7'b0010100, 145 | VSRLI = 7'b0010101, 146 | VAND = 7'b0010110, 147 | VANDI = 7'b0010111, 148 | VOR = 7'b0011000, 149 | VORI = 7'b0011001, 150 | VXOR = 7'b0011010, 151 | VXORI = 7'b0011011, 152 | VSEQ = 7'b0011100, 153 | VSLT = 7'b0011101, 154 | VSLTU = 7'b0011110 155 | } v_int_op_t; -------------------------------------------------------------------------------- /vector_simulator/examples/saxpy/decoder_results/instrs/reconfigure_output.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 0 3 | 0 4 | 0 5 | 0 6 | 0 7 | 0 8 | 0 9 | 1 10 | 1 11 | 1 12 | 1 13 | 0 14 | 0 15 | 0 16 | 0 17 | 0 18 | 0 19 | 0 20 | 1 21 | 1 22 | 1 23 | 1 24 | 0 25 | 0 26 | 0 27 | 0 28 | 0 29 | 0 30 | 0 31 | 1 32 | 1 33 | 1 34 | 1 35 | 0 36 | 0 37 | 0 38 | 0 39 | 0 40 | 0 41 | 0 42 | 1 43 | 1 44 | 1 45 | 1 46 | 0 47 | 0 48 | 0 49 | 0 50 | 0 51 | 0 52 | 0 53 | 1 54 | 1 55 | 1 56 | 1 57 | 0 58 | 0 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| 10 41 | 00 42 | 11 43 | 11 44 | 11 45 | 11 46 | 00 47 | 00 48 | 00 49 | 10 50 | 10 51 | 10 52 | 00 53 | 11 54 | 11 55 | 11 56 | 11 57 | 00 58 | 00 59 | 00 60 | 10 61 | 10 62 | 10 63 | 00 64 | 11 65 | 11 66 | 11 67 | 11 68 | 00 69 | 00 70 | 00 71 | 10 72 | 10 73 | 10 74 | 00 75 | 11 76 | 11 77 | 11 78 | 11 79 | 00 80 | 00 81 | 00 82 | 10 83 | 10 84 | 10 85 | 00 86 | 11 87 | 11 88 | 11 89 | 11 90 | 00 91 | 00 92 | 00 93 | 10 94 | 10 95 | 10 96 | 00 97 | 11 98 | 11 99 | 11 100 | 11 101 | 00 102 | 00 103 | 00 104 | 10 105 | 10 106 | 10 107 | 00 108 | 11 109 | 11 110 | 11 111 | 11 112 | 00 113 | 00 114 | 00 115 | 10 116 | 10 117 | 10 118 | 00 119 | 11 120 | 11 121 | 11 122 | 11 123 | 00 124 | 00 125 | 00 126 | 10 127 | 10 128 | 10 129 | 00 130 | 11 131 | 11 132 | 11 133 | 11 134 | 00 135 | 00 136 | 00 137 | 10 138 | 10 139 | 10 140 | 00 141 | 11 142 | 11 143 | 11 144 | 11 145 | 00 146 | 00 147 | 00 148 | 10 149 | 10 150 | 10 151 | 00 152 | 11 153 | 11 154 | 11 155 | 11 156 | 00 157 | 00 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491 | 10 492 | 00 493 | 11 494 | 11 495 | 11 496 | 11 497 | 00 498 | 00 499 | 00 500 | 10 501 | 10 502 | 10 503 | 00 504 | 11 505 | 11 506 | 11 507 | 11 508 | 00 509 | 00 510 | 00 511 | 10 512 | 10 513 | 10 514 | 00 515 | 11 516 | 11 517 | 11 518 | 11 519 | 00 520 | 00 521 | 00 522 | 10 523 | 10 524 | 10 525 | 00 526 | 11 527 | 11 528 | 11 529 | 11 530 | 00 531 | 00 532 | 00 533 | 10 534 | 10 535 | 10 536 | 00 537 | 11 538 | 11 539 | 11 540 | 11 541 | 00 542 | 00 543 | 00 544 | 10 545 | 10 546 | 10 547 | 00 548 | 11 549 | 11 550 | 11 551 | 11 552 | 00 553 | 00 554 | 00 555 | 10 556 | 10 557 | 10 558 | 00 559 | 11 560 | 11 561 | 11 562 | 11 563 | 00 564 | 00 565 | 00 566 | 10 567 | 10 568 | 10 569 | 00 570 | 11 571 | 11 572 | 11 573 | 11 574 | 00 575 | 00 576 | 00 577 | 10 578 | 10 579 | 10 580 | 00 581 | 11 582 | 11 583 | 11 584 | 11 585 | 00 586 | 00 587 | 00 588 | 10 589 | 10 590 | 10 591 | 00 592 | 11 593 | 11 594 | 11 595 | 11 596 | 00 597 | 00 598 | 00 599 | 10 600 | 10 601 | 10 602 | 00 603 | 11 604 | 11 605 | 11 606 | 11 607 | 00 608 | 00 609 | 00 610 | 10 611 | 10 612 | 10 613 | 00 614 | 11 615 | 11 616 | 11 617 | 11 618 | 00 619 | 00 620 | 00 621 | 10 622 | 10 623 | 10 624 | 00 625 | 11 626 | 11 627 | 11 628 | 11 629 | 00 630 | 00 631 | 00 632 | 10 633 | 10 634 | 10 635 | 00 636 | 11 637 | 11 638 | 11 639 | 11 640 | 00 641 | 00 642 | 00 643 | 10 644 | 10 645 | 10 646 | 00 647 | 11 648 | 11 649 | 11 650 | 11 651 | 00 652 | 00 653 | 00 654 | 10 655 | 10 656 | 10 657 | 00 658 | 11 659 | 11 660 | 11 661 | 11 662 | 00 663 | 00 664 | 00 665 | 10 666 | 10 667 | 10 668 | 00 669 | 11 670 | 11 671 | 11 672 | 11 673 | 00 674 | 00 675 | 00 676 | 10 677 | 10 678 | 10 679 | 00 680 | 11 681 | 11 682 | 11 683 | 11 684 | 00 685 | 00 686 | 00 687 | 10 688 | 10 689 | 10 690 | 00 691 | 11 692 | 11 693 | 11 694 | 11 695 | 00 696 | 00 697 | 00 698 | 10 699 | 10 700 | 10 701 | 00 702 | 11 703 | 11 704 | 11 705 | 11 706 | 00 707 | 00 708 | 00 709 | 10 710 | 10 711 | 10 712 | 00 713 | 11 714 | 11 715 | 11 716 | 11 717 | 00 718 | 00 719 | 00 720 | 10 721 | 10 722 | 10 723 | 00 724 | 11 725 | 11 726 | 11 727 | 11 728 | 00 729 | 00 730 | 00 731 | 10 732 | 10 733 | 10 734 | 00 735 | 11 736 | 11 737 | 11 738 | 11 739 | 00 740 | 00 741 | 00 742 | 10 743 | 10 744 | 10 745 | 00 746 | 11 747 | 11 748 | 11 749 | 11 750 | 00 751 | 00 752 | 00 753 | 10 754 | 10 755 | 10 756 | 00 757 | 11 758 | 11 759 | 11 760 | 11 761 | 00 762 | 00 763 | 00 764 | 10 765 | 10 766 | 10 767 | 00 768 | 11 769 | 11 770 | 11 771 | 11 772 | 00 773 | 00 774 | 00 775 | 10 776 | 10 777 | 10 778 | 00 779 | 11 780 | 11 781 | 11 782 | 11 783 | 00 784 | 00 785 | 00 786 | 10 787 | 10 788 | 10 789 | 00 790 | 11 791 | 11 792 | 11 793 | 11 794 | 00 795 | 00 796 | 00 797 | 10 798 | 10 799 | 10 800 | 00 801 | 11 802 | 11 803 | 11 804 | 11 805 | 00 806 | 00 807 | 00 808 | 10 809 | 10 810 | 10 811 | 00 812 | 11 813 | 11 814 | 11 815 | 11 816 | 00 817 | 00 818 | 00 819 | 10 820 | 10 821 | 10 822 | 00 823 | 11 824 | 11 825 | 11 826 | 11 827 | 00 828 | 00 829 | 00 830 | 10 831 | 10 832 | 10 833 | 00 834 | 11 835 | 11 836 | 11 837 | 11 838 | 00 839 | 00 840 | 00 841 | 10 842 | 10 843 | 10 844 | 00 845 | 11 846 | 11 847 | 11 848 | 11 849 | 00 850 | 00 851 | 00 852 | 10 853 | 10 854 | 10 855 | 00 856 | 11 857 | 11 858 | 11 859 | 11 860 | 00 861 | 00 862 | 00 863 | 10 864 | 10 865 | 10 866 | 00 867 | 11 868 | 11 869 | 11 870 | 11 871 | -------------------------------------------------------------------------------- /rtl/shared/data_operation.sv: -------------------------------------------------------------------------------- 1 | /* 2 | * @info Data Operation Sub-Module 3 | * 4 | * @author VLSI Lab, EE dept., Democritus University of Thrace 5 | * 6 | * @brief Used in the Data Cache, a provided microop picks the operation that will be used 7 | * 8 | * @param ADDR_W : # of Address Bits 9 | * @param DATA_W : # of Data Bits 10 | * @param MICROOP : # of Microoperation Bits 11 | * @param BLOCK_W : # of Cache Block Bits 12 | * @param LOAD_ONLY : Instatiates the block only with the load operations 13 | */ 14 | module data_operation #( 15 | parameter ADDR_W = 5 , 16 | parameter DATA_W = 32 , 17 | parameter MICROOP = 5 , 18 | parameter BLOCK_W = 256, 19 | parameter LOAD_ONLY = 0 20 | ) ( 21 | //Inputs 22 | input logic [ ADDR_W-1:0] input_address, 23 | input logic [BLOCK_W-1:0] input_block , 24 | input logic [ DATA_W-1:0] input_data , 25 | input logic [MICROOP-1:0] microop , 26 | //Outputs 27 | output logic valid_exc , 28 | output logic [ 3:0] exception , 29 | output logic [BLOCK_W-1:0] output_block , 30 | output logic [ DATA_W-1:0] output_vector 31 | ); 32 | 33 | // #Internal Signals# 34 | logic [ DATA_W-1:0] data_loaded_32; 35 | logic [DATA_W/2-1:0] data_loaded_16; 36 | logic [DATA_W/4-1:0] data_loaded_8 ; 37 | logic [ ADDR_W+3:0] selector ; 38 | 39 | generate 40 | //Used for Load Instructions Only 41 | if(LOAD_ONLY) begin 42 | assign selector = 0; 43 | assign data_loaded_32 = input_block[selector +: DATA_W]; 44 | assign data_loaded_16 = input_block[selector +: DATA_W/2]; 45 | assign data_loaded_8 = input_block[selector +: DATA_W/4]; 46 | always_comb begin : OutputVector 47 | case (microop) 48 | 5'b00001: begin 49 | //LW/FLW/C.LWSP/C.FLWSP/C.LW/C.FLW 50 | valid_exc = 0; 51 | exception = 0; 52 | output_vector = data_loaded_32; 53 | end 54 | 5'b00010: begin 55 | //LH 56 | valid_exc = 0; 57 | exception = 0; 58 | output_vector = {{16{data_loaded_16[15]}},data_loaded_16}; 59 | end 60 | 5'b00011: begin 61 | //LHU 62 | valid_exc = 0; 63 | exception = 0; 64 | output_vector = {16'b0,data_loaded_16}; 65 | end 66 | 5'b00100: begin 67 | //LB 68 | valid_exc = 0; 69 | exception = 0; 70 | output_vector = {{24{data_loaded_8[7]}},data_loaded_8}; 71 | end 72 | 5'b00101: begin 73 | //LBU 74 | valid_exc = 0; 75 | exception = 0; 76 | output_vector = {24'b0,data_loaded_8}; 77 | end 78 | default : begin 79 | valid_exc = 1; 80 | exception = 2; 81 | output_vector = input_data; 82 | end 83 | endcase 84 | end 85 | assign output_block = input_block; 86 | end else begin 87 | //Used for both Load/Store Instructions 88 | assign selector = input_address << 3; 89 | assign data_loaded_32 = input_block[selector +: DATA_W]; 90 | assign data_loaded_16 = input_block[selector +: DATA_W/2]; 91 | assign data_loaded_8 = input_block[selector +: DATA_W/4]; 92 | //Create the new load/store vector with the modified data 93 | always_comb begin : OutputVector 94 | case (microop) 95 | 5'b00001: begin 96 | //LW/FLW/C.LWSP/C.FLWSP/C.LW/C.FLW 97 | valid_exc = 0; 98 | exception = 0; 99 | output_vector = data_loaded_32; 100 | end 101 | 5'b00010: begin 102 | //LH 103 | valid_exc = 0; 104 | exception = 0; 105 | output_vector = {{16{data_loaded_16[15]}},data_loaded_16}; 106 | end 107 | 5'b00011: begin 108 | //LHU 109 | valid_exc = 0; 110 | exception = 0; 111 | output_vector = {16'b0,data_loaded_16}; 112 | end 113 | 5'b00100: begin 114 | //LB 115 | valid_exc = 0; 116 | exception = 0; 117 | output_vector = {{24{data_loaded_8[7]}},data_loaded_8}; 118 | end 119 | 5'b00101: begin 120 | //LBU 121 | valid_exc = 0; 122 | exception = 0; 123 | output_vector = {24'b0,data_loaded_8}; 124 | end 125 | 5'b00110: begin 126 | //SW/FSW/C.SWSP/C.FSWSP/C.SW/C.FSW 127 | valid_exc = 0; 128 | exception = 0; 129 | output_vector = input_data; 130 | end 131 | 5'b00111: begin 132 | //SH 133 | valid_exc = 0; 134 | exception = 0; 135 | output_vector = {data_loaded_32[DATA_W-1:16],input_data[15:0]}; 136 | end 137 | 5'b01000: begin 138 | //SB 139 | valid_exc = 0; 140 | exception = 0; 141 | output_vector = {data_loaded_32[DATA_W-1:8],input_data[7:0]}; 142 | end 143 | //FLOATING POINT CURRENTLY DISABLED 144 | /* 145 | 5'b01001: begin 146 | //FCVT.S.W 147 | valid_exc = 0; 148 | exception = 0; 149 | end 150 | 5'b01010: begin 151 | //FCVT.S.WU 152 | valid_exc = 0; 153 | exception = 0; 154 | end 155 | 5'b01011: begin 156 | //FCVT.W.S 157 | valid_exc = 0; 158 | exception = 0; 159 | end 160 | 5'b01100: begin 161 | //FCVT.WU.S 162 | valid_exc = 0; 163 | exception = 0; 164 | end 165 | */ 166 | default : begin 167 | valid_exc = 1; 168 | exception = 2; 169 | output_vector = input_data; 170 | end 171 | endcase 172 | end 173 | 174 | //Create the new modified Block to be stored 175 | always_comb begin : OutputBlock 176 | output_block = input_block; 177 | output_block[selector +: DATA_W] = output_vector; 178 | end 179 | end 180 | endgenerate 181 | 182 | endmodule 183 | -------------------------------------------------------------------------------- /vector_simulator/examples/dot_product/decoder_results/instrs/reconfigure_output.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 0 3 | 0 4 | 0 5 | 0 6 | 0 7 | 0 8 | 1 9 | 1 10 | 1 11 | 1 12 | 0 13 | 0 14 | 0 15 | 0 16 | 0 17 | 0 18 | 1 19 | 1 20 | 1 21 | 1 22 | 0 23 | 0 24 | 0 25 | 0 26 | 0 27 | 0 28 | 1 29 | 1 30 | 1 31 | 1 32 | 0 33 | 0 34 | 0 35 | 0 36 | 0 37 | 0 38 | 1 39 | 1 40 | 1 41 | 1 42 | 0 43 | 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1045 | 0 1046 | 0 1047 | 0 1048 | 1 1049 | 1 1050 | 1 1051 | 1 1052 | --------------------------------------------------------------------------------