├── .gitignore ├── Makefile ├── README.md ├── common ├── configure │ ├── au50 │ │ └── configure.xml │ ├── configure.xml │ ├── ultra96 │ │ └── configure.xml │ └── zcu102 │ │ └── configure.xml ├── constraints │ ├── au50_100M │ │ ├── scripts │ │ │ ├── _full_init_post.tcl │ │ │ ├── _full_init_pre.tcl │ │ │ ├── _full_opt_post.tcl │ │ │ ├── _full_opt_pre.tcl │ │ │ ├── _full_place_post.tcl │ │ │ ├── _full_place_pre.tcl │ │ │ ├── _full_route_post.tcl │ │ │ ├── _vpl_post_init.tcl │ │ │ ├── _vpl_post_opt.tcl │ │ │ ├── _vpl_post_place.tcl │ │ │ ├── _vpl_post_route.tcl │ │ │ ├── _vpl_pre_init.tcl │ │ │ ├── _vpl_pre_opt.tcl │ │ │ ├── _vpl_pre_place.tcl │ │ │ ├── debug_profile_hooks.tcl │ │ │ ├── ocl_util.tcl │ │ │ ├── platform.tcl │ │ │ ├── postopt.tcl │ │ │ ├── postroute.tcl │ │ │ ├── preopt.tcl │ │ │ └── vpl_init.tcl │ │ └── xdc │ │ │ ├── dont_partition.xdc │ │ │ ├── impl.xdc │ │ │ └── ulp_ooc_copy.xdc │ ├── au50_150M │ │ ├── scripts │ │ │ ├── _full_init_post.tcl │ │ │ ├── _full_init_pre.tcl │ │ │ ├── _full_opt_post.tcl │ │ │ ├── _full_opt_pre.tcl │ │ │ ├── _full_place_post.tcl │ │ │ ├── _full_place_pre.tcl │ │ │ ├── _full_route_post.tcl │ │ │ ├── _vpl_post_init.tcl │ │ │ ├── _vpl_post_opt.tcl │ │ │ ├── _vpl_post_place.tcl │ │ │ ├── _vpl_post_route.tcl │ │ │ ├── _vpl_pre_init.tcl │ │ │ ├── _vpl_pre_opt.tcl │ │ │ ├── _vpl_pre_place.tcl │ │ │ ├── debug_profile_hooks.tcl │ │ │ ├── ocl_util.tcl │ │ │ ├── platform.tcl │ │ │ ├── postopt.tcl │ │ │ ├── postroute.tcl │ │ │ ├── preopt.tcl │ │ │ └── vpl_init.tcl │ │ └── xdc │ │ │ ├── dont_partition.xdc │ │ │ ├── impl.xdc │ │ │ └── ulp_ooc_copy.xdc │ ├── au50_200M │ │ ├── scripts │ │ │ ├── _full_init_post.tcl │ │ │ ├── _full_init_pre.tcl │ │ │ ├── _full_opt_post.tcl │ │ │ ├── _full_opt_pre.tcl │ │ │ ├── _full_place_post.tcl │ │ │ ├── _full_place_pre.tcl │ │ │ ├── _full_route_post.tcl │ │ │ ├── _vpl_post_init.tcl │ │ │ ├── _vpl_post_opt.tcl │ │ │ ├── _vpl_post_place.tcl │ │ │ ├── _vpl_post_route.tcl │ │ │ ├── _vpl_pre_init.tcl │ │ │ ├── _vpl_pre_opt.tcl │ │ │ ├── _vpl_pre_place.tcl │ │ │ ├── debug_profile_hooks.tcl │ │ │ ├── ocl_util.tcl │ │ │ ├── platform.tcl │ │ │ ├── postopt.tcl │ │ │ ├── postroute.tcl │ │ │ ├── preopt.tcl │ │ │ └── vpl_init.tcl │ │ └── xdc │ │ │ ├── dont_partition.xdc │ │ │ ├── impl.xdc │ │ │ └── ulp_ooc_copy.xdc │ ├── au50_250M │ │ ├── scripts │ │ │ ├── _full_init_post.tcl │ │ │ ├── _full_init_pre.tcl │ │ │ ├── _full_opt_post.tcl │ │ │ ├── _full_opt_pre.tcl │ │ │ ├── _full_place_post.tcl │ │ │ ├── _full_place_pre.tcl │ │ │ ├── _full_route_post.tcl │ │ │ ├── _vpl_post_init.tcl │ │ │ ├── _vpl_post_opt.tcl │ │ │ ├── _vpl_post_place.tcl │ │ │ ├── _vpl_post_route.tcl │ │ │ ├── _vpl_pre_init.tcl │ │ │ ├── _vpl_pre_opt.tcl │ │ │ ├── _vpl_pre_place.tcl │ │ │ ├── debug_profile_hooks.tcl │ │ │ ├── ocl_util.tcl │ │ │ ├── platform.tcl │ │ │ ├── postopt.tcl │ │ │ ├── postroute.tcl │ │ │ ├── preopt.tcl │ │ │ └── vpl_init.tcl │ │ └── xdc │ │ │ ├── dont_partition.xdc │ │ │ ├── impl.xdc │ │ │ └── ulp_ooc_copy.xdc │ ├── au50_300M │ │ ├── scripts │ │ │ ├── _full_init_post.tcl │ │ │ ├── _full_init_pre.tcl │ │ │ ├── _full_opt_post.tcl │ │ │ ├── _full_opt_pre.tcl │ │ │ ├── _full_place_post.tcl │ │ │ ├── _full_place_pre.tcl │ │ │ ├── _full_route_post.tcl │ │ │ ├── _vpl_post_init.tcl │ │ │ ├── _vpl_post_opt.tcl │ │ │ ├── _vpl_post_place.tcl │ │ │ ├── _vpl_post_route.tcl │ │ │ ├── _vpl_pre_init.tcl │ │ │ ├── _vpl_pre_opt.tcl │ │ │ ├── _vpl_pre_place.tcl │ │ │ ├── debug_profile_hooks.tcl │ │ │ ├── ocl_util.tcl │ │ │ ├── platform.tcl │ │ │ ├── postopt.tcl │ │ │ ├── postroute.tcl │ │ │ ├── preopt.tcl │ │ │ └── vpl_init.tcl │ │ └── xdc │ │ │ ├── dont_partition.xdc │ │ │ ├── impl.xdc │ │ │ └── ulp_ooc_copy.xdc │ ├── ultra96 │ │ ├── scripts │ │ │ ├── _full_init_post.tcl │ │ │ ├── _full_init_pre.tcl │ │ │ ├── _full_opt_post.tcl │ │ │ ├── _full_opt_pre.tcl │ │ │ ├── _full_place_post.tcl │ │ │ ├── _full_place_pre.tcl │ │ │ ├── _full_route_post.tcl │ │ │ ├── _vpl_post_init.tcl │ │ │ ├── _vpl_post_opt.tcl │ │ │ ├── _vpl_post_place.tcl │ │ │ ├── _vpl_post_route.tcl │ │ │ ├── _vpl_pre_init.tcl │ │ │ ├── _vpl_pre_opt.tcl │ │ │ ├── _vpl_pre_place.tcl │ │ │ ├── debug_profile_hooks.tcl │ │ │ ├── dynamic_postopt.tcl │ │ │ ├── ocl_util.tcl │ │ │ ├── platform.tcl │ │ │ └── vpl_init.tcl │ │ └── xdc │ │ │ ├── _post_sys_link_gen_constrs.xdc │ │ │ ├── dont_partition.xdc │ │ │ ├── dynamic_impl.xdc │ │ │ └── pfm_dynamic_ooc_copy.xdc │ └── zcu102 │ │ ├── scripts │ │ ├── _full_init_post.tcl │ │ ├── _full_init_pre.tcl │ │ ├── _full_opt_post.tcl │ │ ├── _full_opt_pre.tcl │ │ ├── _full_place_post.tcl │ │ ├── _full_place_pre.tcl │ │ ├── _full_post_route_phys_opt_post.tcl │ │ ├── _full_route_post.tcl │ │ ├── _full_write_bitstream_post.tcl │ │ ├── _full_write_bitstream_pre.tcl │ │ ├── _vivado_impl_props.tcl │ │ ├── _vivado_params.tcl │ │ ├── _vivado_report_commands.tcl │ │ ├── _vivado_synth_props.tcl │ │ ├── _vpl_post_init.tcl │ │ ├── _vpl_post_opt.tcl │ │ ├── _vpl_post_place.tcl │ │ ├── _vpl_post_post_route_phys_opt.tcl │ │ ├── _vpl_post_route.tcl │ │ ├── _vpl_post_write_bit_pdi.tcl │ │ ├── _vpl_pre_init.tcl │ │ ├── _vpl_pre_opt.tcl │ │ ├── _vpl_pre_place.tcl │ │ ├── _vpl_pre_write_bit_pdi.tcl │ │ ├── debug_profile_hooks.tcl │ │ ├── dynamic_postopt.tcl │ │ ├── ocl_util.tcl │ │ ├── platform.tcl │ │ ├── profile.tcl │ │ └── vpl_init.tcl │ │ └── xdc │ │ ├── _post_sys_link_gen_constrs.xdc │ │ ├── dont_partition.xdc │ │ ├── dynamic_impl.xdc │ │ └── pfm_dynamic_ooc_copy.xdc ├── driver_src │ ├── config.cpp │ └── config.h ├── hipr │ └── au50_dfx_hipr │ │ ├── Makefile │ │ ├── checkpoint │ │ └── dummy │ │ ├── cpp │ │ ├── Makefile │ │ ├── host │ │ ├── out.log │ │ ├── run.sh │ │ ├── runtime_.log │ │ └── src │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── arch │ │ │ ├── au50.txt │ │ │ ├── au50_invalid.txt │ │ │ ├── au51.txt │ │ │ ├── au51_invalid.txt │ │ │ ├── yboard.txt │ │ │ ├── yboard_invalid.txt │ │ │ ├── zcu102.txt │ │ │ ├── zcu102_invalid.txt │ │ │ ├── zcu103.txt │ │ │ └── zcu103_invalid.txt │ │ │ ├── cmdParser.cpp │ │ │ ├── cmdParser.hpp │ │ │ ├── gen.py │ │ │ ├── hipr.cpp │ │ │ ├── hipr.hpp │ │ │ ├── main.cpp │ │ │ ├── my_cmd.py │ │ │ ├── my_plot.py │ │ │ ├── plot.py │ │ │ ├── rec.py │ │ │ ├── run.py │ │ │ ├── sweep.py │ │ │ └── typedefs.hpp │ │ ├── python │ │ ├── mk_abs_tcl.py │ │ ├── mk_gen_pfm_tcl.py │ │ ├── mk_overlay_tcl.py │ │ └── report.py │ │ ├── shell │ │ ├── run_gen_pfm_dymanic.sh │ │ ├── run_python.sh │ │ └── run_tcl.sh │ │ ├── src4level2 │ │ ├── page │ │ │ └── page.v │ │ └── ydma_bb │ │ │ ├── RelayStation.v │ │ │ ├── stream_shell.v │ │ │ ├── ydma.v │ │ │ ├── ydma_Loop_VITIS_LOOP_31_1_proc1.v │ │ │ ├── ydma_Loop_VITIS_LOOP_31_1_proc1_Pipeline_VITIS_LOOP_31_1.v │ │ │ ├── ydma_Loop_VITIS_LOOP_32_2_proc2.v │ │ │ ├── ydma_Loop_VITIS_LOOP_32_2_proc2_Pipeline_VITIS_LOOP_32_2.v │ │ │ ├── ydma_Loop_VITIS_LOOP_35_3_proc3.v │ │ │ ├── ydma_Loop_VITIS_LOOP_36_4_proc4.v │ │ │ ├── ydma_aximm1_m_axi.v │ │ │ ├── ydma_aximm2_m_axi.v │ │ │ ├── ydma_control_s_axi.v │ │ │ ├── ydma_entry_proc.v │ │ │ ├── ydma_fifo_w32_d2_S.v │ │ │ ├── ydma_fifo_w512_d1024_A.v │ │ │ ├── ydma_fifo_w64_d256_A.v │ │ │ ├── ydma_fifo_w64_d2_S.v │ │ │ ├── ydma_hls_deadlock_detection_unit.v │ │ │ ├── ydma_hls_deadlock_detector.vh │ │ │ └── ydma_hls_deadlock_report_unit.vh │ │ ├── tcl │ │ ├── empty_pfm_dynamic.tcl │ │ ├── out_of_context_syn_page.tcl │ │ ├── out_of_context_syn_ydma_bb.tcl │ │ ├── replace_sub_module_level1.tcl │ │ └── sub_divided.tcl │ │ └── xdc │ │ └── dummy ├── metadata │ ├── au50_100M │ │ ├── appendSection.rtd │ │ ├── debug_ip_layout.rtd │ │ ├── systemDiagramModelSlrBaseAddress.json │ │ ├── ydma.rtd │ │ ├── ydma.xml │ │ ├── ydma_build.rtd │ │ └── ydma_xml.rtd │ ├── au50_150M │ │ ├── appendSection.rtd │ │ ├── debug_ip_layout.rtd │ │ ├── systemDiagramModelSlrBaseAddress.json │ │ ├── ydma.rtd │ │ ├── ydma.xml │ │ ├── ydma_build.rtd │ │ └── ydma_xml.rtd │ ├── au50_200M │ │ ├── appendSection.rtd │ │ ├── debug_ip_layout.rtd │ │ ├── systemDiagramModelSlrBaseAddress.json │ │ ├── ydma.rtd │ │ ├── ydma.xml │ │ ├── ydma_build.rtd │ │ └── ydma_xml.rtd │ ├── au50_300M │ │ ├── appendSection.rtd │ │ ├── debug_ip_layout.rtd │ │ ├── systemDiagramModelSlrBaseAddress.json │ │ ├── ydma.xml │ │ ├── ydma_build.rtd │ │ └── ydma_xml.rtd │ ├── ultra96 │ │ └── ydma.xml │ └── zcu102 │ │ └── ydma.xml ├── overlay │ ├── dcp_lib │ │ └── dummy.dcp │ ├── main.bit │ ├── riscv_bit_lib │ │ ├── ._page10_32bramI1O2.bit │ │ ├── ._page10_32bramI2O3.bit │ │ ├── ._page10_32bramI3O4.bit │ │ ├── ._page11_32bramI2O4.bit │ │ ├── ._page11_32bramI2O5.bit │ │ ├── ._page11_riscv_32bramI5O5.bit │ │ ├── ._page16_32bramI1O2.bit │ │ ├── ._page16_32bramI2O3.bit │ │ ├── ._page16_32bramI3O5.bit │ │ ├── ._page16_riscv_32bramI5O5.bit │ │ ├── ._page17_16bramI3O2.bit │ │ ├── ._page17_32bramI0O2.bit │ │ ├── ._page17_32bramI1O2.bit │ │ ├── ._page17_32bramI2O3.bit │ │ ├── ._page17_32bramI3O4.bit │ │ ├── ._page17_riscv_32bramI5O5.bit │ │ ├── ._page18_16bramI3O2.bit │ │ ├── ._page18_32bramI1O2.bit │ │ ├── ._page18_32bramI2O3.bit │ │ ├── ._page18_32bramI3O3.bit │ │ ├── ._page18_riscv_32bramI5O5.bit │ │ ├── ._page19_32bramI1O2.bit │ │ ├── ._page19_32bramI2O4.bit │ │ ├── ._page19_64bramI3O2.bit │ │ ├── ._page19_riscv_64bramI5O5.bit │ │ ├── ._page20_32bramI1O2.bit │ │ ├── ._page20_32bramI2O3.bit │ │ ├── ._page20_32bramI5O3.bit │ │ ├── ._page20_64bramI1O2.bit │ │ ├── ._page20_64bramI2O2.bit │ │ ├── ._page20_riscv_64bramI5O5.bit │ │ ├── ._page24_16bramI1O3.bit │ │ ├── ._page24_16bramI5O5.bit │ │ ├── ._page24_32bramI1O2.bit │ │ ├── ._page24_64bramI1O2.bit │ │ ├── ._page24_64bramI1O4.bit │ │ ├── ._page24_64bramI2O2.bit │ │ ├── ._page24_riscv_16bramI5O5.bit │ │ ├── ._page26_16bramI1O3.bit │ │ ├── ._page26_16bramI5O5.bit │ │ ├── ._page26_32bramI1O2.bit │ │ ├── ._page26_32bramI2O2.bit │ │ ├── ._page26_riscv_16bramI5O5.bit │ │ ├── ._page27_16bramI1O3.bit │ │ ├── ._page27_16bramI5O5.bit │ │ ├── ._page27_32bramI2O2.bit │ │ ├── ._page27_riscv_16bramI5O5.bit │ │ ├── ._page28_16bramI2O2.bit │ │ ├── ._page28_32bramI1O3.bit │ │ ├── ._page28_32bramI2O3.bit │ │ ├── ._page28_riscv_16bramI5O5.bit │ │ ├── ._page29_16bramI1O3.bit │ │ ├── ._page29_32bramI2O2.bit │ │ ├── ._page29_riscv_16bramI5O5.bit │ │ ├── ._page30_16bramI1O2.bit │ │ ├── ._page30_32bramI1O2.bit │ │ ├── ._page30_32bramI2O3.bit │ │ ├── ._page30_32bramI2O4.bit │ │ ├── ._page30_riscv_16bramI5O5.bit │ │ ├── ._page31_32bramI0O2.bit │ │ ├── ._page31_32bramI1O2.bit │ │ ├── ._page31_riscv_16bramI5O5.bit │ │ ├── ._page3_16bramI5O5.bit │ │ ├── ._page3_32bramI1O3.bit │ │ ├── ._page3_32bramI2O2.bit │ │ ├── ._page3_riscv_16bramI5O5.bit │ │ ├── ._page4_32bramI1O2.bit │ │ ├── ._page4_32bramI1O3.bit │ │ ├── ._page4_riscv_16bramI5O5.bit │ │ ├── ._page5_16bramI1O3.bit │ │ ├── ._page5_32bramI1O2.bit │ │ ├── ._page5_32bramI1O3.bit │ │ ├── ._page5_riscv_16bramI5O5.bit │ │ ├── ._page6_32bramI1O2.bit │ │ ├── ._page6_32bramI2O2.bit │ │ ├── ._page6_32bramI2O4.bit │ │ ├── ._page6_riscv_16bramI5O5.bit │ │ ├── ._page8_16bramI2O2.bit │ │ ├── ._page8_32bramI1O2.bit │ │ ├── ._page8_64bramI1O5.bit │ │ ├── ._page8_64bramI2O2.bit │ │ ├── ._page8_64bramI2O3.bit │ │ ├── ._page8_96bramI1O2.bit │ │ ├── ._page8_riscv_64bramI5O5.bit │ │ ├── ._page9_16bramI5O2.bit │ │ ├── ._page9_32bramI1O2.bit │ │ ├── ._page9_32bramI1O3.bit │ │ ├── ._page9_32bramI2O3.bit │ │ └── ._page9_riscv_32bramI5O5.bit │ └── size_table │ │ ├── utilization2.rpt │ │ └── utilization3.rpt ├── riscv_bram │ ├── dummy.tcl │ ├── run.sh │ ├── src │ │ ├── Config_Controls.v │ │ ├── ExtractCtrl.v │ │ ├── Input_Port.v │ │ ├── Input_Port_Cluster.v │ │ ├── Output_Port.v │ │ ├── Output_Port_Cluster.v │ │ ├── Stream_Flow_Control.v │ │ ├── converge_ctrl.v │ │ ├── instr_config.v │ │ ├── leaf.v │ │ ├── leaf_interface.v │ │ ├── picorv32.v │ │ ├── picorv32_wrapper.v │ │ ├── picorv_mem.v │ │ ├── ram0.v │ │ ├── ram2.v │ │ ├── read_b_in.v │ │ ├── riscv2consumer.v │ │ ├── rise_detect.v │ │ ├── write_b_in.v │ │ ├── write_b_out.v │ │ ├── xram2.v │ │ └── xram_triple.v │ └── utilization.rpt ├── riscv_src │ ├── riscv │ │ ├── Makefile │ │ ├── ap_fixed.h │ │ ├── ap_int.h │ │ ├── firmware.h │ │ ├── firmware.map │ │ ├── hls_stream.h │ │ ├── hls_video.h │ │ ├── main.cpp │ │ ├── makehex.py │ │ ├── print.cpp │ │ ├── run.sh │ │ ├── sections.lds │ │ ├── start.S │ │ ├── start.h │ │ └── stream.cpp │ └── src │ │ ├── picorv32.v │ │ ├── picorv32_wrapper.v │ │ ├── picorv_mem.v │ │ ├── ram0.v │ │ ├── riscv2consumer.v │ │ ├── rise_detect.v │ │ ├── xram2.v │ │ └── xram_triple.v ├── script_src │ ├── Makefile_riscv │ ├── cvd.tcl │ ├── gen.sh │ ├── gen_resource.py │ ├── gen_runtime.sh │ ├── gen_runtime_au50.sh │ ├── gen_runtime_ultra96.sh │ ├── gen_runtime_zcu102.sh │ ├── gen_xclbin.sh │ ├── gen_xclbin_au50.sh │ ├── gen_xclbin_ultra96.sh │ ├── gen_xclbin_zcu102.sh │ ├── get_partion_pins.tcl │ ├── get_pblocks.tcl │ ├── impl_page.tcl │ ├── impl_page_au50.tcl │ ├── impl_page_bk.tcl │ ├── impl_page_ultra96.tcl │ ├── impl_page_zcu102.tcl │ ├── impl_static_32_48_OpticalFlow.tcl │ ├── project_syn2gen_counter_debug.tcl │ ├── project_syn_gen_mono.tcl │ ├── project_syn_gen_u96.tcl │ ├── project_syn_gen_u96_100_20.tcl │ ├── project_syn_gen_zcu102.tcl │ ├── project_syn_gen_zcu102_16_leaves.tcl │ ├── project_syn_gen_zcu102_30_leaves.tcl │ ├── project_xsdk_core.tcl │ ├── project_xsdk_core0.tcl │ ├── qsub_main.sh │ ├── qsub_run.sh │ ├── run100_150.sh │ ├── run160_200.sh │ ├── run210_250.sh │ ├── run260_300.sh │ ├── run310_350.sh │ ├── run360_400.sh │ ├── run_bnn512.sh │ ├── run_digit_reg512.sh │ ├── run_face_detection512.sh │ ├── run_optical_flow512.sh │ ├── run_rendering512.sh │ ├── run_spam_filter512.sh │ ├── sim.tcl │ └── test.tcl ├── sim_src │ ├── counter1.v │ └── test.v ├── verilog_src │ ├── AxiLite2Bft_v2_0.v │ ├── Config_Controls.v │ ├── ExtractCtrl.v │ ├── Input_Port.v │ ├── Input_Port_Cluster.v │ ├── InterfaceWapper.v │ ├── InterfaceWapper1.v │ ├── InterfaceWapper4.v │ ├── InterfaceWapper6.v │ ├── InterfaceWapper7.v │ ├── Output_Port.v │ ├── Output_Port_Cluster.v │ ├── README.md │ ├── Stream_Flow_Control.v │ ├── SynFIFO.v │ ├── axi2stream_v1_0.v │ ├── bft.v │ ├── bft_level_0.v │ ├── bft_level_1.v │ ├── clock_100M_100M.xdc │ ├── clock_constraints.xdc │ ├── converge_ctrl.v │ ├── converter.v │ ├── counter1.v │ ├── direction_determiner_0.v │ ├── direction_params.vh │ ├── fifo_stream_in.v │ ├── fifo_stream_out.v │ ├── floorplan_static_wrapper.v │ ├── gen_nw.v │ ├── gen_nw32.v │ ├── gen_nw8.v │ ├── instr_config.v │ ├── interface.v │ ├── leaf.v │ ├── leaf_empty.v │ ├── leaf_interface.v │ ├── leaf_riscv.v │ ├── pblocks_32.xdc │ ├── pi_arbiter.v │ ├── pi_arbiter_0.v │ ├── pi_cluster.v │ ├── pi_cluster_0.v │ ├── pi_switch.v │ ├── pi_switch_0.v │ ├── picorv32.v │ ├── picorv32_wrapper.v │ ├── picorv_mem.v │ ├── pipe_ff.v │ ├── pipe_ff_0.v │ ├── pipe_ff_1.v │ ├── ram0.v │ ├── ram2.v │ ├── read_b_in.v │ ├── read_queue.v │ ├── riscv2consumer.v │ ├── rise_detect.v │ ├── sel_vld.v │ ├── single_ram.v │ ├── stream_shell.v │ ├── subtree_212_wrapper.v │ ├── t_arbiter.v │ ├── t_arbiter_0.v │ ├── t_cluster.v │ ├── t_cluster_0.v │ ├── t_switch.v │ ├── t_switch_0.v │ ├── test.v │ ├── user_kernel.v │ ├── write_b_in.v │ ├── write_b_out.v │ ├── write_queue.v │ ├── xram2.v │ └── xram_triple.v └── ydma │ ├── au50 │ ├── Makefile │ ├── build.sh │ ├── replace.py │ └── xrt.ini │ ├── hw │ ├── Makefile │ ├── build.sh │ ├── gen.sh │ └── xrt.ini │ ├── hw_u250 │ ├── .Xil │ │ └── configutil-1989-ylxiao-OptiPlex-7050 │ │ │ └── hw │ │ │ ├── ext_metadata.json │ │ │ ├── hw_emu │ │ │ ├── ext_metadata.json │ │ │ └── hw_emu.json │ │ │ └── xsa.xml │ ├── Makefile │ ├── build.sh │ ├── emconfig.json │ └── xrt.ini │ ├── src │ ├── au50_dfx.cfg │ ├── host.cpp │ ├── host_bk.cpp │ ├── input_data.h │ ├── load.cpp │ ├── multi_load.cpp │ ├── typedefs.h │ ├── ultra96_dfx.cfg │ ├── ydma.cpp │ └── zcu102_dfx.cfg │ ├── sw_emu │ ├── Makefile │ ├── build_and_run.sh │ └── xrt.ini │ ├── ultra96 │ ├── Makefile │ ├── build.sh │ ├── gen.sh │ ├── run_app.sh │ └── ultra96_dfx_manual │ │ ├── Makefile │ │ ├── python │ │ ├── mk_abs_tcl.py │ │ ├── mk_gen_pfm_tcl.py │ │ └── mk_overlay_tcl.py │ │ ├── shell │ │ ├── run_gen_pfm_dymanic.sh │ │ ├── run_python.sh │ │ └── run_tcl.sh │ │ ├── src4level2 │ │ ├── page │ │ │ └── page.v │ │ ├── page_bk │ │ │ ├── Config_Controls.v │ │ │ ├── ExtractCtrl.v │ │ │ ├── Input_Port.v │ │ │ ├── Input_Port_Cluster.v │ │ │ ├── Output_Port.v │ │ │ ├── Output_Port_Cluster.v │ │ │ ├── Stream_Flow_Control.v │ │ │ ├── SynFIFO.v │ │ │ ├── converge_ctrl.v │ │ │ ├── leaf_interface.v │ │ │ ├── page.v │ │ │ ├── ram0.v │ │ │ ├── read_b_in.v │ │ │ ├── single_ram.v │ │ │ ├── user_kernel.v │ │ │ ├── write_b_in.v │ │ │ └── write_b_out.v │ │ └── ydma_bb │ │ │ ├── Config_Controls.v │ │ │ ├── ExtractCtrl.v │ │ │ ├── Input_Port.v │ │ │ ├── Input_Port_Cluster.v │ │ │ ├── Output_Port.v │ │ │ ├── Output_Port_Cluster.v │ │ │ ├── Stream_Flow_Control.v │ │ │ ├── SynFIFO.v │ │ │ ├── bft.v │ │ │ ├── config_parser.v │ │ │ ├── config_parser_config_parser_Pipeline_VITIS_LOOP_207_1.v │ │ │ ├── config_parser_config_parser_Pipeline_VITIS_LOOP_213_2.v │ │ │ ├── config_parser_config_parser_Pipeline_VITIS_LOOP_221_3.v │ │ │ ├── config_parser_config_parser_Pipeline_VITIS_LOOP_230_5.v │ │ │ ├── config_parser_flow_control_loop_pipe_sequential_init.v │ │ │ ├── config_parser_regslice_both.v │ │ │ ├── config_parser_v1_buffer_V.v │ │ │ ├── converge_ctrl.v │ │ │ ├── data32to512.v │ │ │ ├── data32to512_data32to512_Pipeline_VITIS_LOOP_158_1.v │ │ │ ├── data32to512_flow_control_loop_pipe_sequential_init.v │ │ │ ├── data32to512_regslice_both.v │ │ │ ├── gen_nw_vivado.v │ │ │ ├── leaf_bb.v │ │ │ ├── leaf_interface.v │ │ │ ├── leaf_interface_wrapper1.v │ │ │ ├── page.v │ │ │ ├── ram0.v │ │ │ ├── read_b_in.v │ │ │ ├── single_ram.v │ │ │ ├── ulp_ydma_1_0.v │ │ │ ├── user_kernel.v │ │ │ ├── write_b_in.v │ │ │ ├── write_b_out.v │ │ │ ├── ydma_Loop_VITIS_LOOP_31_1_proc1.v │ │ │ ├── ydma_Loop_VITIS_LOOP_31_1_proc1_Pipeline_VITIS_LOOP_31_1.v │ │ │ ├── ydma_Loop_VITIS_LOOP_32_2_proc2.v │ │ │ ├── ydma_Loop_VITIS_LOOP_32_2_proc2_Pipeline_VITIS_LOOP_32_2.v │ │ │ ├── ydma_Loop_VITIS_LOOP_35_3_proc3.v │ │ │ ├── ydma_Loop_VITIS_LOOP_36_4_proc4.v │ │ │ ├── ydma_aximm1_m_axi.v │ │ │ ├── ydma_aximm2_m_axi.v │ │ │ ├── ydma_bb.v │ │ │ ├── ydma_control_s_axi.v │ │ │ ├── ydma_entry_proc.v │ │ │ ├── ydma_fifo_w32_d2_S.v │ │ │ ├── ydma_fifo_w512_d2014_A.v │ │ │ ├── ydma_fifo_w64_d256_A.v │ │ │ └── ydma_fifo_w64_d2_S.v │ │ ├── tcl │ │ ├── empty_pfm_dynamic.tcl │ │ ├── out_of_context_syn_page.tcl │ │ ├── out_of_context_syn_ydma_bb.tcl │ │ ├── replace_sub_module_level1.tcl │ │ └── sub_divided.tcl │ │ └── xdc │ │ ├── sub.xdc │ │ ├── sub_hw1.xdc │ │ ├── sub_s1.xdc │ │ └── sub_s2.xdc │ └── zcu102 │ ├── Makefile │ ├── build.sh │ ├── gen.sh │ ├── replace.py │ ├── run_app.sh │ ├── xrt.ini │ ├── zcu102_dfx_hipr │ ├── Makefile │ ├── cpp │ │ ├── run.sh │ │ └── src │ │ │ ├── app │ │ │ └── connect.txt │ │ │ ├── arch │ │ │ ├── au50.txt │ │ │ ├── zcu102.txt │ │ │ └── zcu102_invalid.txt │ │ │ ├── hipr.cpp │ │ │ ├── hipr.hpp │ │ │ ├── host.cpp │ │ │ └── typedefs.hpp │ ├── python │ │ ├── mk_abs_tcl.py │ │ ├── mk_gen_pfm_tcl.py │ │ ├── mk_overlay_tcl.py │ │ └── report.py │ ├── shell │ │ ├── run_gen_pfm_dymanic.sh │ │ ├── run_python.sh │ │ └── run_tcl.sh │ ├── src4level2 │ │ ├── page │ │ │ └── page.v │ │ └── ydma_bb │ │ │ ├── RelayStation.v │ │ │ ├── stream_shell.v │ │ │ ├── ydma.v │ │ │ ├── ydma_Loop_VITIS_LOOP_31_1_proc1.v │ │ │ ├── ydma_Loop_VITIS_LOOP_31_1_proc1_Pipeline_VITIS_LOOP_31_1.v │ │ │ ├── ydma_Loop_VITIS_LOOP_32_2_proc2.v │ │ │ ├── ydma_Loop_VITIS_LOOP_32_2_proc2_Pipeline_VITIS_LOOP_32_2.v │ │ │ ├── ydma_Loop_VITIS_LOOP_35_3_proc3.v │ │ │ ├── ydma_Loop_VITIS_LOOP_36_4_proc4.v │ │ │ ├── ydma_aximm1_m_axi.v │ │ │ ├── ydma_aximm2_m_axi.v │ │ │ ├── ydma_control_s_axi.v │ │ │ ├── ydma_entry_proc.v │ │ │ ├── ydma_fifo_w32_d2_S.v │ │ │ ├── ydma_fifo_w512_d1024_A.v │ │ │ ├── ydma_fifo_w64_d256_A.v │ │ │ └── ydma_fifo_w64_d2_S.v │ └── tcl │ │ ├── empty_pfm_dynamic.tcl │ │ ├── out_of_context_syn_page.tcl │ │ ├── out_of_context_syn_ydma_bb.tcl │ │ ├── replace_sub_module_level1.tcl │ │ └── sub_divided.tcl │ └── zcu102_dfx_manual │ ├── Makefile │ ├── python │ ├── mk_abs_tcl.py │ ├── mk_gen_pfm_tcl.py │ └── mk_overlay_tcl.py │ ├── shell │ ├── run_gen_pfm_dymanic.sh │ ├── run_python.sh │ └── run_tcl.sh │ ├── src4level2 │ ├── page │ │ └── page.v │ └── ydma_bb │ │ ├── Config_Controls.v │ │ ├── ExtractCtrl.v │ │ ├── Input_Port.v │ │ ├── Input_Port_Cluster.v │ │ ├── Output_Port.v │ │ ├── Output_Port_Cluster.v │ │ ├── Stream_Flow_Control.v │ │ ├── SynFIFO.v │ │ ├── bft.v │ │ ├── config_parser.v │ │ ├── config_parser_config_parser_Pipeline_VITIS_LOOP_102_3.v │ │ ├── config_parser_config_parser_Pipeline_VITIS_LOOP_89_1.v │ │ ├── config_parser_flow_control_loop_pipe_sequential_init.v │ │ ├── config_parser_regslice_both.v │ │ ├── converge_ctrl.v │ │ ├── data32to512.v │ │ ├── data32to512_data32to512_Pipeline_VITIS_LOOP_175_1.v │ │ ├── data32to512_flow_control_loop_pipe_sequential_init.v │ │ ├── data32to512_regslice_both.v │ │ ├── leaf_interface.v │ │ ├── leaf_interface_wrapper1.v │ │ ├── page_bb.v │ │ ├── ram0.v │ │ ├── read_b_in.v │ │ ├── single_ram.v │ │ ├── stream_shell.v │ │ ├── write_b_in.v │ │ ├── write_b_out.v │ │ ├── ydma_Loop_VITIS_LOOP_31_1_proc1.v │ │ ├── ydma_Loop_VITIS_LOOP_31_1_proc1_Pipeline_VITIS_LOOP_31_1.v │ │ ├── ydma_Loop_VITIS_LOOP_32_2_proc2.v │ │ ├── ydma_Loop_VITIS_LOOP_32_2_proc2_Pipeline_VITIS_LOOP_32_2.v │ │ ├── ydma_Loop_VITIS_LOOP_35_3_proc3.v │ │ ├── ydma_Loop_VITIS_LOOP_36_4_proc4.v │ │ ├── ydma_aximm1_m_axi.v │ │ ├── ydma_aximm2_m_axi.v │ │ ├── ydma_bb.v │ │ ├── ydma_control_s_axi.v │ │ ├── ydma_entry_proc.v │ │ ├── ydma_fifo_w32_d2_S.v │ │ ├── ydma_fifo_w512_d16384_A.v │ │ ├── ydma_fifo_w64_d256_A.v │ │ └── ydma_fifo_w64_d2_S.v │ ├── tcl │ ├── empty_pfm_dynamic.tcl │ ├── out_of_context_syn_page.tcl │ ├── out_of_context_syn_ydma_bb.tcl │ ├── replace_sub_module_level1.tcl │ └── sub_divided.tcl │ └── xdc │ └── sub.xdc ├── images ├── bunny.png ├── csimu.png ├── error.png ├── report_all.png ├── report_one.png ├── runtime_all.png └── runtime_one.png ├── input_src ├── datamover │ ├── Makefile │ ├── cfg │ │ ├── u50.cfg │ │ ├── zcu102.cfg │ │ └── zcu102_dfx.cfg │ ├── data_proc2.cpp │ ├── data_proc2.h │ ├── host │ │ ├── host.cpp │ │ ├── main.cpp │ │ ├── top.cpp │ │ ├── top.h │ │ └── typedefs.h │ ├── operators │ │ ├── data_proc1.cpp │ │ ├── data_proc1.h │ │ ├── data_proc2.cpp │ │ └── data_proc2.h │ └── sw_emu │ │ ├── Makefile │ │ ├── build_and_run.sh │ │ └── xrt.ini ├── rendering512 │ ├── Makefile │ ├── cfg │ │ ├── u50_dfx.cfg │ │ ├── zcu102.cfg │ │ └── zcu102_dfx.cfg │ ├── host │ │ ├── host.cpp │ │ ├── input_data.h │ │ ├── main.cpp │ │ ├── top.cpp │ │ ├── top.h │ │ └── typedefs.h │ ├── operators │ │ ├── coloringFB_bot_m.cpp │ │ ├── coloringFB_bot_m.h │ │ ├── coloringFB_top_m.cpp │ │ ├── coloringFB_top_m.h │ │ ├── data_redir_m.cpp │ │ ├── data_redir_m.h │ │ ├── data_transfer.cpp │ │ ├── data_transfer.h │ │ ├── rasterization2_m.cpp │ │ ├── rasterization2_m.h │ │ ├── zculling_bot.cpp │ │ ├── zculling_bot.h │ │ ├── zculling_top.cpp │ │ └── zculling_top.h │ ├── sw_emu │ │ ├── Makefile │ │ ├── build_and_run.sh │ │ └── xrt.ini │ └── zcu102 │ │ ├── Makefile │ │ ├── app.exe │ │ └── build.sh └── rendering512_all │ ├── Makefile │ ├── cfg │ ├── u50_dfx.cfg │ ├── zcu102.cfg │ └── zcu102_dfx.cfg │ ├── host │ ├── host.cpp │ ├── input_data.h │ ├── main.cpp │ ├── top.cpp │ ├── top.h │ └── typedefs.h │ ├── operators │ ├── coloringFB_bot_m.cpp │ ├── coloringFB_bot_m.h │ ├── coloringFB_top_m.cpp │ ├── coloringFB_top_m.h │ ├── data_redir_m.cpp │ ├── data_redir_m.h │ ├── data_transfer.cpp │ ├── data_transfer.h │ ├── rasterization2_m.cpp │ ├── rasterization2_m.h │ ├── zculling_bot.cpp │ ├── zculling_bot.h │ ├── zculling_top.cpp │ └── zculling_top.h │ ├── sw_emu │ ├── Makefile │ ├── build_and_run.sh │ └── xrt.ini │ └── zcu102 │ ├── Makefile │ ├── app.exe │ └── build.sh ├── pr_flow.py └── pr_flow ├── HW2riscv.py ├── __init__.py ├── bit.py ├── config.py ├── gen_basic.py ├── gen_bft.py ├── gen_sdk.py ├── hls.py ├── impl.py ├── ip_repo.py ├── mbft.py ├── monolithic.py ├── overlay.py ├── overlay_hipr.py ├── report.py ├── riscv2HW.py ├── runtime.py ├── syn.py ├── utils.py ├── xclbin.py └── ydma.py /.gitignore: -------------------------------------------------------------------------------- 1 | workspace/ 2 | *.pyc 3 | -------------------------------------------------------------------------------- /common/configure/au50/configure.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_full_init_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_full_init_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_full_opt_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_opt.tcl 3 | source ./scripts/postopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_full_opt_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_opt.tcl 3 | source ./scripts/preopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_full_place_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_full_place_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_full_route_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_route.tcl 3 | source ./scripts/postroute.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_vpl_post_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | write_user_impl_clock_constraint "level0_i/ulp" "clk_kernel2_in {is_user_set false instance _bd_top port clk_kernel2_in clk_id 1 freq 500.000000} clk_kernel_in {is_user_set true instance _bd_top port clk_kernel_in clk_id 0 freq 100}" "" "output" 3 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_vpl_post_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_vpl_post_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | # utilization reports 3 | report_utilization_impl true "ydma" "placed" "level0_i/ulp" $input_dir $vivado_output_dir 4 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_vpl_post_route.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | 14 | # generate cookie file for messaging 15 | write_cookie_file_impl "ydma" 16 | 17 | # utilization reports 18 | report_utilization_impl true "ydma" "routed" "level0_i/ulp" $input_dir $vivado_output_dir 19 | 20 | # kernel service update 21 | update_kernel_info $steps_log $vpl_output_dir "level0_i/ulp" 22 | 23 | # update noc node information 24 | update_profile_metadata_postroute $vpl_output_dir 25 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_vpl_pre_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_vpl_pre_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | ocl_util::report_utilization_drc "luts -1 brams -1 registers -1 dsps -1" "level0_i/ulp" 0.8 $steps_log $vivado_output_dir 14 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/_vpl_pre_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | set xocc_optimize_level 0 14 | set_property SEVERITY {Warning} [get_drc_checks HDPR-5] 15 | set_param logicopt.enableBUFGinsertHFN 0 16 | 17 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/postroute.tcl: -------------------------------------------------------------------------------- 1 | report_power -------------------------------------------------------------------------------- /common/constraints/au50_100M/scripts/vpl_init.tcl: -------------------------------------------------------------------------------- 1 | # This file automatically generated by vpl 2 | # please do not modify 3 | set vpp_link_root [file normalize [file join [file dirname [info script]] .. .. ..]] 4 | set vpl_root "$vpp_link_root/vivado/vpl" 5 | set local_dir "$vpl_root/.local" 6 | 7 | set vivado_error_file "vivado_error.txt" 8 | set vivado_warn_file "vivado_warning.txt" 9 | set vivado_output_dir "$vpl_root/output" 10 | set output_dir "$vpl_root/output" 11 | set vpl_output_dir "$vpp_link_root/int" 12 | set input_dir "$vpl_root/input" 13 | set steps_log "$vpp_link_root/link.steps.log" 14 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/xdc/dont_partition.xdc: -------------------------------------------------------------------------------- 1 | set_property DONT_PARTITION TRUE [get_cells -hier -filter {SDX_KERNEL==true}] 2 | -------------------------------------------------------------------------------- /common/constraints/au50_100M/xdc/ulp_ooc_copy.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name blp_s_aclk_ctrl_00 -period 20 [get_ports blp_s_aclk_ctrl_00] 10 | create_clock -name blp_s_aclk_freerun_ref_00 -period 10 [get_ports blp_s_aclk_freerun_ref_00] 11 | create_clock -name blp_s_aclk_pcie_00 -period 4 [get_ports blp_s_aclk_pcie_00] 12 | create_clock -name clk_kernel_in -period 3.333 [get_ports clk_kernel_in] 13 | create_clock -name clk_kernel2_in -period 2 [get_ports clk_kernel2_in] 14 | create_clock -name hbm_aclk_in -period 2.222 [get_ports hbm_aclk_in] 15 | 16 | ################################################################################ 17 | # Kernel clock overridden by user 18 | create_clock -name USER_clk_kernel_in -period 10.0 [get_ports clk_kernel_in] 19 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_full_init_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_full_init_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_full_opt_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_opt.tcl 3 | source ./scripts/postopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_full_opt_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_opt.tcl 3 | source ./scripts/preopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_full_place_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_full_place_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_full_route_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_route.tcl 3 | source ./scripts/postroute.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_vpl_post_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | write_user_impl_clock_constraint "level0_i/ulp" "clk_kernel2_in {is_user_set false instance _bd_top port clk_kernel2_in clk_id 1 freq 500.000000} clk_kernel_in {is_user_set true instance _bd_top port clk_kernel_in clk_id 0 freq 150}" "" "output" 3 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_vpl_post_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_vpl_post_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | # utilization reports 3 | report_utilization_impl true "ydma" "placed" "level0_i/ulp" $input_dir $vivado_output_dir 4 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_vpl_post_route.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | 14 | # generate cookie file for messaging 15 | write_cookie_file_impl "ydma" 16 | 17 | # utilization reports 18 | report_utilization_impl true "ydma" "routed" "level0_i/ulp" $input_dir $vivado_output_dir 19 | 20 | # kernel service update 21 | update_kernel_info $steps_log $vpl_output_dir "level0_i/ulp" 22 | 23 | # update noc node information 24 | update_profile_metadata_postroute $vpl_output_dir 25 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_vpl_pre_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_vpl_pre_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | ocl_util::report_utilization_drc "luts -1 brams -1 registers -1 dsps -1" "level0_i/ulp" 0.8 $steps_log $vivado_output_dir 14 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/_vpl_pre_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | set xocc_optimize_level 0 14 | set_property SEVERITY {Warning} [get_drc_checks HDPR-5] 15 | set_param logicopt.enableBUFGinsertHFN 0 16 | 17 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/postroute.tcl: -------------------------------------------------------------------------------- 1 | report_power -------------------------------------------------------------------------------- /common/constraints/au50_150M/scripts/vpl_init.tcl: -------------------------------------------------------------------------------- 1 | # This file automatically generated by vpl 2 | # please do not modify 3 | set vpp_link_root [file normalize [file join [file dirname [info script]] .. .. ..]] 4 | set vpl_root "$vpp_link_root/vivado/vpl" 5 | set local_dir "$vpl_root/.local" 6 | 7 | set vivado_error_file "vivado_error.txt" 8 | set vivado_warn_file "vivado_warning.txt" 9 | set vivado_output_dir "$vpl_root/output" 10 | set output_dir "$vpl_root/output" 11 | set vpl_output_dir "$vpp_link_root/int" 12 | set input_dir "$vpl_root/input" 13 | set steps_log "$vpp_link_root/link.steps.log" 14 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/xdc/dont_partition.xdc: -------------------------------------------------------------------------------- 1 | set_property DONT_PARTITION TRUE [get_cells -hier -filter {SDX_KERNEL==true}] 2 | -------------------------------------------------------------------------------- /common/constraints/au50_150M/xdc/ulp_ooc_copy.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name blp_s_aclk_ctrl_00 -period 20 [get_ports blp_s_aclk_ctrl_00] 10 | create_clock -name blp_s_aclk_freerun_ref_00 -period 10 [get_ports blp_s_aclk_freerun_ref_00] 11 | create_clock -name blp_s_aclk_pcie_00 -period 4 [get_ports blp_s_aclk_pcie_00] 12 | create_clock -name clk_kernel_in -period 3.333 [get_ports clk_kernel_in] 13 | create_clock -name clk_kernel2_in -period 2 [get_ports clk_kernel2_in] 14 | create_clock -name hbm_aclk_in -period 2.222 [get_ports hbm_aclk_in] 15 | 16 | ################################################################################ 17 | # Kernel clock overridden by user 18 | create_clock -name USER_clk_kernel_in -period 6.666666666666667 [get_ports clk_kernel_in] 19 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_full_init_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_full_init_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_full_opt_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_opt.tcl 3 | source ./scripts/postopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_full_opt_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_opt.tcl 3 | source ./scripts/preopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_full_place_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_full_place_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_full_route_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_route.tcl 3 | source ./scripts/postroute.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_vpl_post_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | write_user_impl_clock_constraint "level0_i/ulp" "clk_kernel2_in {is_user_set false instance _bd_top port clk_kernel2_in clk_id 1 freq 500.000000} clk_kernel_in {is_user_set true instance _bd_top port clk_kernel_in clk_id 0 freq 200}" "" "output" 3 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_vpl_post_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_vpl_post_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | # utilization reports 3 | report_utilization_impl true "ydma" "placed" "level0_i/ulp" $input_dir $vivado_output_dir 4 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_vpl_post_route.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | 14 | # generate cookie file for messaging 15 | write_cookie_file_impl "ydma" 16 | 17 | # utilization reports 18 | report_utilization_impl true "ydma" "routed" "level0_i/ulp" $input_dir $vivado_output_dir 19 | 20 | # kernel service update 21 | update_kernel_info $steps_log $vpl_output_dir "level0_i/ulp" 22 | 23 | # update noc node information 24 | update_profile_metadata_postroute $vpl_output_dir 25 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_vpl_pre_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_vpl_pre_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | ocl_util::report_utilization_drc "luts -1 brams -1 registers -1 dsps -1" "level0_i/ulp" 0.8 $steps_log $vivado_output_dir 14 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/_vpl_pre_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | set xocc_optimize_level 0 14 | set_property SEVERITY {Warning} [get_drc_checks HDPR-5] 15 | set_param logicopt.enableBUFGinsertHFN 0 16 | 17 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/postroute.tcl: -------------------------------------------------------------------------------- 1 | report_power -------------------------------------------------------------------------------- /common/constraints/au50_200M/scripts/vpl_init.tcl: -------------------------------------------------------------------------------- 1 | # This file automatically generated by vpl 2 | # please do not modify 3 | set vpp_link_root [file normalize [file join [file dirname [info script]] .. .. ..]] 4 | set vpl_root "$vpp_link_root/vivado/vpl" 5 | set local_dir "$vpl_root/.local" 6 | 7 | set vivado_error_file "vivado_error.txt" 8 | set vivado_warn_file "vivado_warning.txt" 9 | set vivado_output_dir "$vpl_root/output" 10 | set output_dir "$vpl_root/output" 11 | set vpl_output_dir "$vpp_link_root/int" 12 | set input_dir "$vpl_root/input" 13 | set steps_log "$vpp_link_root/link.steps.log" 14 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/xdc/dont_partition.xdc: -------------------------------------------------------------------------------- 1 | set_property DONT_PARTITION TRUE [get_cells -hier -filter {SDX_KERNEL==true}] 2 | -------------------------------------------------------------------------------- /common/constraints/au50_200M/xdc/ulp_ooc_copy.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name blp_s_aclk_ctrl_00 -period 20 [get_ports blp_s_aclk_ctrl_00] 10 | create_clock -name blp_s_aclk_freerun_ref_00 -period 10 [get_ports blp_s_aclk_freerun_ref_00] 11 | create_clock -name blp_s_aclk_pcie_00 -period 4 [get_ports blp_s_aclk_pcie_00] 12 | create_clock -name clk_kernel_in -period 3.333 [get_ports clk_kernel_in] 13 | create_clock -name clk_kernel2_in -period 2 [get_ports clk_kernel2_in] 14 | create_clock -name hbm_aclk_in -period 2.222 [get_ports hbm_aclk_in] 15 | 16 | ################################################################################ 17 | # Kernel clock overridden by user 18 | create_clock -name USER_clk_kernel_in -period 5.0 [get_ports clk_kernel_in] 19 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_full_init_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_full_init_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_full_opt_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_opt.tcl 3 | source ./scripts/postopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_full_opt_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_opt.tcl 3 | source ./scripts/preopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_full_place_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_full_place_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_full_route_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_route.tcl 3 | source ./scripts/postroute.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_vpl_post_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | write_user_impl_clock_constraint "level0_i/ulp" "clk_kernel2_in {is_user_set false instance _bd_top port clk_kernel2_in clk_id 1 freq 500.000000} clk_kernel_in {is_user_set true instance _bd_top port clk_kernel_in clk_id 0 freq 250}" "" "output" 3 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_vpl_post_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_vpl_post_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | # utilization reports 3 | report_utilization_impl true "ydma" "placed" "level0_i/ulp" $input_dir $vivado_output_dir 4 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_vpl_post_route.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | 14 | # generate cookie file for messaging 15 | write_cookie_file_impl "ydma" 16 | 17 | # utilization reports 18 | report_utilization_impl true "ydma" "routed" "level0_i/ulp" $input_dir $vivado_output_dir 19 | 20 | # kernel service update 21 | update_kernel_info $steps_log $vpl_output_dir "level0_i/ulp" 22 | 23 | # update noc node information 24 | update_profile_metadata_postroute $vpl_output_dir 25 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_vpl_pre_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_vpl_pre_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | ocl_util::report_utilization_drc "luts -1 brams -1 registers -1 dsps -1" "level0_i/ulp" 0.8 $steps_log $vivado_output_dir 14 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/_vpl_pre_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | set xocc_optimize_level 0 14 | set_property SEVERITY {Warning} [get_drc_checks HDPR-5] 15 | set_param logicopt.enableBUFGinsertHFN 0 16 | 17 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/postroute.tcl: -------------------------------------------------------------------------------- 1 | report_power -------------------------------------------------------------------------------- /common/constraints/au50_250M/scripts/vpl_init.tcl: -------------------------------------------------------------------------------- 1 | # This file automatically generated by vpl 2 | # please do not modify 3 | set vpp_link_root [file normalize [file join [file dirname [info script]] .. .. ..]] 4 | set vpl_root "$vpp_link_root/vivado/vpl" 5 | set local_dir "$vpl_root/.local" 6 | 7 | set vivado_error_file "vivado_error.txt" 8 | set vivado_warn_file "vivado_warning.txt" 9 | set vivado_output_dir "$vpl_root/output" 10 | set output_dir "$vpl_root/output" 11 | set vpl_output_dir "$vpp_link_root/int" 12 | set input_dir "$vpl_root/input" 13 | set steps_log "$vpp_link_root/link.steps.log" 14 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/xdc/dont_partition.xdc: -------------------------------------------------------------------------------- 1 | set_property DONT_PARTITION TRUE [get_cells -hier -filter {SDX_KERNEL==true}] 2 | -------------------------------------------------------------------------------- /common/constraints/au50_250M/xdc/ulp_ooc_copy.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name blp_s_aclk_ctrl_00 -period 20 [get_ports blp_s_aclk_ctrl_00] 10 | create_clock -name blp_s_aclk_freerun_ref_00 -period 10 [get_ports blp_s_aclk_freerun_ref_00] 11 | create_clock -name blp_s_aclk_pcie_00 -period 4 [get_ports blp_s_aclk_pcie_00] 12 | create_clock -name clk_kernel_in -period 3.333 [get_ports clk_kernel_in] 13 | create_clock -name clk_kernel2_in -period 2 [get_ports clk_kernel2_in] 14 | create_clock -name hbm_aclk_in -period 2.222 [get_ports hbm_aclk_in] 15 | 16 | ################################################################################ 17 | # Kernel clock overridden by user 18 | create_clock -name USER_clk_kernel_in -period 4.0 [get_ports clk_kernel_in] 19 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_full_init_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_full_init_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_full_opt_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_opt.tcl 3 | source ./scripts/postopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_full_opt_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_opt.tcl 3 | source ./scripts/preopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_full_place_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_full_place_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_full_route_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_route.tcl 3 | source ./scripts/postroute.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_vpl_post_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | write_user_impl_clock_constraint "level0_i/ulp" "clk_kernel2_in {is_user_set false instance _bd_top port clk_kernel2_in clk_id 1 freq 500.000000} clk_kernel_in {is_user_set false instance _bd_top port clk_kernel_in clk_id 0 freq 300.000000}" "" "output" 3 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_vpl_post_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_vpl_post_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | # utilization reports 3 | report_utilization_impl true "ydma" "placed" "level0_i/ulp" $input_dir $vivado_output_dir 4 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_vpl_post_route.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | 14 | # generate cookie file for messaging 15 | write_cookie_file_impl "ydma" 16 | 17 | # utilization reports 18 | report_utilization_impl true "ydma" "routed" "level0_i/ulp" $input_dir $vivado_output_dir 19 | 20 | # kernel service update 21 | update_kernel_info $steps_log $vpl_output_dir "level0_i/ulp" 22 | 23 | # update noc node information 24 | update_profile_metadata_postroute $vpl_output_dir 25 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_vpl_pre_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_vpl_pre_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | ocl_util::report_utilization_drc "luts -1 brams -1 registers -1 dsps -1" "level0_i/ulp" 0.8 $steps_log $vivado_output_dir 14 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/_vpl_pre_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | set xocc_optimize_level 0 14 | set_property SEVERITY {Warning} [get_drc_checks HDPR-5] 15 | set_param logicopt.enableBUFGinsertHFN 0 16 | 17 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/postroute.tcl: -------------------------------------------------------------------------------- 1 | report_power -------------------------------------------------------------------------------- /common/constraints/au50_300M/scripts/vpl_init.tcl: -------------------------------------------------------------------------------- 1 | # This file automatically generated by vpl 2 | # please do not modify 3 | set vpp_link_root [file normalize [file join [file dirname [info script]] .. .. ..]] 4 | set vpl_root "$vpp_link_root/vivado/vpl" 5 | set local_dir "$vpl_root/.local" 6 | 7 | set vivado_error_file "vivado_error.txt" 8 | set vivado_warn_file "vivado_warning.txt" 9 | set vivado_output_dir "$vpl_root/output" 10 | set output_dir "$vpl_root/output" 11 | set vpl_output_dir "$vpp_link_root/int" 12 | set input_dir "$vpl_root/input" 13 | set steps_log "$vpp_link_root/link.steps.log" 14 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/xdc/dont_partition.xdc: -------------------------------------------------------------------------------- 1 | set_property DONT_PARTITION TRUE [get_cells -hier -filter {SDX_KERNEL==true}] 2 | -------------------------------------------------------------------------------- /common/constraints/au50_300M/xdc/ulp_ooc_copy.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name blp_s_aclk_ctrl_00 -period 20 [get_ports blp_s_aclk_ctrl_00] 10 | create_clock -name blp_s_aclk_freerun_ref_00 -period 10 [get_ports blp_s_aclk_freerun_ref_00] 11 | create_clock -name blp_s_aclk_pcie_00 -period 4 [get_ports blp_s_aclk_pcie_00] 12 | create_clock -name clk_kernel_in -period 3.333 [get_ports clk_kernel_in] 13 | create_clock -name clk_kernel2_in -period 2 [get_ports clk_kernel2_in] 14 | create_clock -name hbm_aclk_in -period 2.222 [get_ports hbm_aclk_in] 15 | 16 | ################################################################################ -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_full_init_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_full_init_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_full_opt_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_opt.tcl 3 | source ./scripts/dynamic_postopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_full_opt_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_opt.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_full_place_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_full_place_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_full_route_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_route.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_vpl_post_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | write_user_impl_clock_constraint "pfm_top_i/dynamic_region" "" "" "./output" 3 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_vpl_post_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_vpl_post_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | # utilization reports 3 | report_utilization_impl true "ydma" "placed" "pfm_top_i/dynamic_region" $input_dir $vivado_output_dir 4 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_vpl_post_route.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | 14 | # generate cookie file for messaging 15 | write_cookie_file_impl "ydma" 16 | 17 | # utilization reports 18 | report_utilization_impl true "ydma" "routed" "pfm_top_i/dynamic_region" $input_dir $vivado_output_dir 19 | 20 | # kernel service update 21 | update_kernel_info $steps_log $vpl_output_dir "pfm_top_i/dynamic_region" 22 | 23 | # update noc node information 24 | update_profile_metadata_postroute $vpl_output_dir 25 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_vpl_pre_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_vpl_pre_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | ocl_util::report_utilization_drc "luts 68074 brams 216 registers 135419 dsps 360" "pfm_top_i/dynamic_region" 0.8 $steps_log $vivado_output_dir 14 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/_vpl_pre_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | set xocc_optimize_level 0 14 | set_property SEVERITY {Warning} [get_drc_checks HDPR-5] 15 | set_param logicopt.enableBUFGinsertHFN 0 16 | 17 | -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/dynamic_postopt.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/common/constraints/ultra96/scripts/dynamic_postopt.tcl -------------------------------------------------------------------------------- /common/constraints/ultra96/scripts/vpl_init.tcl: -------------------------------------------------------------------------------- 1 | # This file automatically generated by vpl 2 | # please do not modify 3 | set vpp_link_root [file normalize [file join [file dirname [info script]] .. .. ..]] 4 | set vpl_root "$vpp_link_root/vivado/vpl" 5 | set local_dir "$vpl_root/.local" 6 | 7 | set vivado_error_file "vivado_error.txt" 8 | set vivado_warn_file "vivado_warning.txt" 9 | set vivado_output_dir "$vpl_root/output" 10 | set output_dir "$vpl_root/output" 11 | set vpl_output_dir "$vpp_link_root/int" 12 | set input_dir "$vpl_root/input" 13 | set steps_log "$vpp_link_root/link.steps.log" 14 | -------------------------------------------------------------------------------- /common/constraints/ultra96/xdc/_post_sys_link_gen_constrs.xdc: -------------------------------------------------------------------------------- 1 | # No content 2 | -------------------------------------------------------------------------------- /common/constraints/ultra96/xdc/dont_partition.xdc: -------------------------------------------------------------------------------- 1 | set_property DONT_PARTITION TRUE [get_cells -hier -filter {SDX_KERNEL==true}] 2 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_init_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_init_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_init.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_opt_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_opt.tcl 3 | source ./scripts/dynamic_postopt.tcl 4 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_opt_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_opt.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_place_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_place_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_place.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_post_route_phys_opt_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_post_route_phys_opt.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_route_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_route.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_write_bitstream_post.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_post_write_bit_pdi.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_full_write_bitstream_pre.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | source ./scripts/_vpl_pre_write_bit_pdi.tcl 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vivado_params.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by vpl 2 | set_param project.loadTopLevelOOCConstrs 1 3 | set_param compiler.enablePerformanceTrace true 4 | set_param project.writeIntermediateCheckpoints 0 5 | set_param bd.ForceAppCoreUpgrade 1 6 | set_param board.repoPaths .local/hw_platform/board 7 | set_param hd.Visual 0 8 | set_param project.enablePRFlowIPI 1 9 | set_param project.gatelevelSubdesign 1 10 | set_param place.ultrathreadsUsed 0 11 | 12 | # Params added by user 13 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_post_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | write_user_impl_clock_constraint "pfm_top_i/dynamic_region" "" "" ./output 3 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_post_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_post_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | # utilization reports 3 | report_utilization_impl true "ydma" "placed" "pfm_top_i/dynamic_region" $input_dir $vivado_output_dir 4 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_post_post_route_phys_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_post_route.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ../../../.local/vpl_init.tcl 4 | source $local_dir/ocl_util.tcl 5 | source $local_dir/platform.tcl 6 | source $local_dir/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | 14 | # generate cookie file for messaging 15 | write_cookie_file_impl "ydma" 16 | 17 | # utilization reports 18 | report_utilization_impl true "ydma" "routed" "pfm_top_i/dynamic_region" $input_dir $vivado_output_dir 19 | 20 | # kernel service update 21 | update_kernel_info $steps_log $vpl_output_dir "pfm_top_i/dynamic_region" 22 | 23 | # update noc node information 24 | update_profile_metadata_postroute $vpl_output_dir 25 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_post_write_bit_pdi.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_pre_init.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_pre_opt.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | ocl_util::report_utilization_drc "luts 269074 brams 912 registers 537219 dsps 2520" "pfm_top_i/dynamic_region" 0.8 $steps_log $vivado_output_dir 14 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_pre_place.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | set xocc_optimize_level 0 14 | set_property SEVERITY {Warning} [get_drc_checks HDPR-5] 15 | set_param logicopt.enableBUFGinsertHFN 0 16 | 17 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/_vpl_pre_write_bit_pdi.tcl: -------------------------------------------------------------------------------- 1 | # This file was automatically generated by Vpl 2 | if { ![info exists _is_init_cmds] } { 3 | source ./scripts/vpl_init.tcl 4 | source ./scripts/ocl_util.tcl 5 | source ./scripts/platform.tcl 6 | source ./scripts/debug_profile_hooks.tcl 7 | namespace import ocl_util::* 8 | 9 | set _is_init_cmds true 10 | } 11 | 12 | 13 | 14 | # run timing analysis and frequency scaling 15 | if { ![report_timing_and_scale_freq "pfm_top_i/dynamic_region" "dr" $vivado_output_dir $vpl_output_dir "kernel_clock_freqs {} system_clock_freqs {} worst_negative_slack 0 max_frequency 650 min_frequency 10 error_on_hold_violation true skip_timing_and_scaling false enable_auto_freq_scale false" "ydma"] } { 16 | return false 17 | } 18 | -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/dynamic_postopt.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/common/constraints/zcu102/scripts/dynamic_postopt.tcl -------------------------------------------------------------------------------- /common/constraints/zcu102/scripts/vpl_init.tcl: -------------------------------------------------------------------------------- 1 | # This file automatically generated by vpl 2 | # please do not modify 3 | set vpp_link_root [file normalize [file join [file dirname [info script]] .. .. ..]] 4 | set vpl_root "$vpp_link_root/vivado/vpl" 5 | set local_dir "$vpl_root/.local" 6 | 7 | set vivado_error_file "vivado_error.txt" 8 | set vivado_warn_file "vivado_warning.txt" 9 | set vivado_output_dir "$vpl_root/output" 10 | set output_dir "$vpl_root/output" 11 | set vpl_output_dir "$vpp_link_root/int" 12 | set input_dir "$vpl_root/input" 13 | set steps_log "$vpp_link_root/link.steps.log" 14 | -------------------------------------------------------------------------------- /common/constraints/zcu102/xdc/_post_sys_link_gen_constrs.xdc: -------------------------------------------------------------------------------- 1 | # No content 2 | -------------------------------------------------------------------------------- /common/constraints/zcu102/xdc/dont_partition.xdc: -------------------------------------------------------------------------------- 1 | set_property DONT_PARTITION TRUE [get_cells -hier -filter {SDX_KERNEL==true}] 2 | -------------------------------------------------------------------------------- /common/constraints/zcu102/xdc/dynamic_impl.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/common/constraints/zcu102/xdc/dynamic_impl.xdc -------------------------------------------------------------------------------- /common/driver_src/config.h: -------------------------------------------------------------------------------- 1 | class config{ 2 | public: 3 | unsigned int ctrl_reg; 4 | unsigned int reg0; 5 | unsigned int reg1; 6 | unsigned int reg2; 7 | unsigned int reg3; 8 | unsigned int reg4; 9 | unsigned int reg5; 10 | unsigned int reg6; 11 | unsigned int reg7; 12 | 13 | 14 | config(unsigned int BASE_ADDR, unsigned int CTRL_REG); 15 | 16 | void read_from_fifo(); 17 | 18 | void write_to_fifo(int high_32_bits, int low_32_bits); 19 | 20 | void init_regs(); 21 | 22 | void ap_start(); 23 | 24 | void instr_config(unsigned int bft_addr,const unsigned int *instr_data, unsigned int len); 25 | 26 | void app(); 27 | 28 | 29 | }; 30 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/checkpoint/dummy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/common/hipr/au50_dfx_hipr/checkpoint/dummy -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/host: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/common/hipr/au50_dfx_hipr/cpp/host -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | CXX=g++ 4 | CFLAG='-m64 -g -O3' 5 | GUROBI_DIR=/opt/gurobi951/linux64 6 | INC=-I${GUROBI_DIR}/include/ 7 | LIB=-L${GUROBI_DIR}/lib/' -lgurobi_c++ -lgurobi95 -lm' 8 | src=./src 9 | m= 10 | 11 | # g++ ./src/host.cpp ./src/hipr.cpp -o host 12 | ${CXX} ${CFLAG} ${INC} -o host ./${src}/*.cpp ./${src}/*.hpp #${LIB} 13 | 14 | 15 | start=$(date +%s.%N) 16 | 17 | ./host -P ./src/app/$1 18 | 19 | # dur=$(echo "$(date +%s.%N) - $start" | bc) 20 | dur=0 21 | printf "run: %.3f seconds" $dur > runtime_${1}.log 22 | printf "" 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/runtime_.log: -------------------------------------------------------------------------------- 1 | run: 0.454 seconds -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/README.md: -------------------------------------------------------------------------------- 1 | # hipr_milp 2 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/arch/au50_invalid.txt: -------------------------------------------------------------------------------- 1 | OFFSET_CLB_BRAM36_BRAM18_DSP2_URAM288 0 0 0 -6 0 2 | MAX_ROW 8 3 | INVALID_TILE_x_y_w_h 68 1 3 1 4 | INVALID_TILE_x_y_w_h 68 4 3 1 5 | INVALID_TILE_x_y_w_h 108 3 19 2 6 | INVALID_TILE_x_y_w_h 0 0 90 1 7 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/arch/au51_invalid.txt: -------------------------------------------------------------------------------- 1 | OFFSET_CLB_BRAM36_BRAM18_DSP2 0 0 0 -6 2 | INVALID_TILE_X1_X2_Y1_Y2 125 126 0 0 -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/arch/yboard.txt: -------------------------------------------------------------------------------- 1 | CLB 0 CLB 1 2 | BRAM18 0 CLB 2 3 | CLB 3 DSP2 0 4 | CLB 4 CLB 5 5 | BRAM18 1 CLB 6 6 | CLB 7 CLB 8 -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/arch/yboard_invalid.txt: -------------------------------------------------------------------------------- 1 | OFFSET_CLB_BRAM36_BRAM18_DSP2 0 0 0 0 2 | INVALID_TILE_X1_X2_Y1_Y2 3 4 2 2 3 | INVALID_TILE_X1_X2_Y1_Y2 6 7 2 2 -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/arch/zcu102.txt: -------------------------------------------------------------------------------- 1 | CLB 1 CLB 2 2 | BRAM18 0 CLB 3 3 | CLB 4 DSP2 0 4 | CLB 5 CLB 6 5 | CLB 7 CLB 8 6 | BRAM18 1 CLB 9 7 | CLB 10 DSP2 1 8 | CLB 11 CLB 12 9 | CLB 13 DSP2 2 10 | CLB 14 CLB 15 11 | CLB 16 CLB 17 12 | BRAM18 2 CLB 18 13 | CLB 19 DSP2 3 14 | CLB 20 CLB 21 15 | CLB 22 CLB 23 16 | BRAM18 3 CLB 24 17 | CLB 25 DSP2 4 18 | CLB 26 CLB 27 19 | CLB 28 DSP2 5 20 | CLB 29 CLB 30 21 | CLB 31 CLB 32 22 | BRAM18 4 CLB 33 23 | CLB 34 DSP2 6 24 | CLB 35 CLB 36 25 | CLB 37 CLB 38 26 | BRAM18 5 CLB 39 27 | CLB 40 DSP2 7 28 | CLB 41 CLB 42 29 | CLB 43 DSP2 8 30 | CLB 44 CLB 45 31 | CLB 46 CLB 47 32 | BRAM18 6 CLB 48 33 | CLB 49 DSP2 9 34 | CLB 50 CLB 51 35 | CLB 52 DSP2 10 36 | CLB 53 CLB 54 37 | CLB 55 DSP2 11 38 | CLB 56 CLB 57 39 | CLB 58 CLB 59 40 | BRAM18 7 CLB 60 41 | CLB 61 DSP2 12 42 | CLB 62 CLB 63 43 | CLB 64 CLB 65 44 | BRAM18 8 CLB 66 45 | CLB 67 DSP2 13 46 | CLB 68 CLB 69 47 | CLB 70 CLB 71 48 | BRAM18 9 CLB 72 49 | CLB 73 DSP2 14 50 | CLB 74 CLB 75 51 | CLB 76 DSP2 15 52 | CLB 77 CLB 78 53 | CLB 79 CLB 80 54 | BRAM18 10 CLB 81 55 | CLB 82 CLB 83 56 | BRAM18 11 CLB 84 57 | CLB 85 PCIE 0 58 | PCIE 1 CLB 86 59 | CLB 87 DSP2 16 60 | CLB 88 CLB 89 61 | CLB 90 DSP2 17 62 | CLB 91 CLB 92 63 | CLB 93 CLB 94 64 | BRAM18 12 CLB 95 65 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/arch/zcu102_invalid.txt: -------------------------------------------------------------------------------- 1 | OFFSET_CLB_BRAM36_BRAM18_DSP2 5 1 2 2 2 | MAX_ROW 7 3 | INVALID_TILE_x_y_w_h 0 0 37 3 4 | INVALID_TILE_x_y_w_h 55 1 2 1 5 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/arch/zcu103.txt: -------------------------------------------------------------------------------- 1 | CLB 1 CLB 2 2 | BRAM18 0 CLB 3 3 | CLB 4 DSP2 0 4 | CLB 5 CLB 6 5 | CLB 7 CLB 8 6 | BRAM18 1 CLB 9 7 | CLB 10 DSP2 1 8 | CLB 11 CLB 12 9 | CLB 13 DSP2 2 10 | CLB 14 CLB 15 11 | CLB 16 CLB 17 12 | BRAM18 2 CLB 18 13 | CLB 19 DSP2 3 14 | CLB 20 CLB 21 15 | CLB 22 CLB 23 16 | BRAM18 3 CLB 24 17 | CLB 25 DSP2 4 18 | CLB 26 CLB 27 19 | CLB 28 DSP2 5 20 | CLB 29 CLB 30 21 | CLB 31 CLB 32 22 | BRAM18 4 CLB 33 23 | CLB 34 DSP2 6 24 | CLB 35 CLB 36 25 | CLB 37 CLB 38 26 | BRAM18 5 CLB 39 27 | CLB 40 DSP2 7 28 | CLB 41 CLB 42 29 | CLB 43 DSP2 8 30 | CLB 44 CLB 45 31 | CLB 46 CLB 47 32 | BRAM18 6 CLB 48 33 | CLB 49 DSP2 9 34 | CLB 50 CLB 51 35 | CLB 52 DSP2 10 36 | CLB 53 CLB 54 37 | CLB 55 DSP2 11 38 | CLB 56 CLB 57 39 | CLB 58 CLB 59 40 | BRAM18 7 CLB 60 41 | CLB 61 DSP2 12 42 | CLB 62 CLB 63 43 | CLB 64 CLB 65 44 | BRAM18 8 CLB 66 45 | CLB 67 DSP2 13 46 | CLB 68 CLB 69 47 | CLB 70 CLB 71 48 | BRAM18 9 CLB 72 49 | CLB 73 DSP2 14 50 | CLB 74 CLB 75 51 | CLB 76 DSP2 15 52 | CLB 77 CLB 78 53 | CLB 79 CLB 80 54 | BRAM18 10 CLB 81 55 | CLB 82 CLB 83 56 | BRAM18 11 CLB 84 57 | CLB 85 PCIE 0 58 | PCIE 1 CLB 86 59 | CLB 87 DSP2 16 60 | CLB 88 CLB 89 61 | CLB 90 DSP2 17 62 | CLB 91 CLB 92 63 | CLB 93 CLB 94 64 | BRAM18 12 CLB 95 65 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/arch/zcu103_invalid.txt: -------------------------------------------------------------------------------- 1 | OFFSET_CLB_BRAM36_BRAM18_DSP2 5 1 2 2 2 | INVALID_TILE_X1_X2_Y1_Y2 65 66 1 1 3 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/cmdParser.hpp: -------------------------------------------------------------------------------- 1 | #include "typedefs.hpp" 2 | #ifndef __CMDPARSER_H__ 3 | #define __CMDPARSER_H__ 4 | 5 | class cmdParser{ 6 | public: 7 | string opt_solver; 8 | bool _opt_solver=false; 9 | string path_prefix; 10 | bool _path_prefix=false; 11 | string device; 12 | bool _device=false; 13 | double t_init = 0; 14 | bool _t_init = false; 15 | int my_seed = 0; 16 | bool _my_seed = false; 17 | int trial_num = 0; 18 | bool _trial_num = false; 19 | double t_min = 0; 20 | bool _t_min = false; 21 | string out_file; 22 | bool _out_file = false; 23 | string inst_name; 24 | bool _inst_name = false; 25 | string out_log_file; 26 | bool _out_log_file = false; 27 | 28 | 29 | cmdParser(int argc, char **argv); 30 | string isSet(bool in); 31 | void print_par(void); 32 | 33 | }; 34 | 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/cpp/src/gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import matplotlib 3 | import matplotlib.pyplot as plt 4 | 5 | a = [2, 1, 3] 6 | 7 | a.remove(2) 8 | 9 | print (a) 10 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/python/mk_abs_tcl.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import argparse 3 | import os 4 | 5 | 6 | parser = argparse.ArgumentParser() 7 | parser.add_argument('workspace') 8 | parser.add_argument('-t', '--top', type=str, default="no_func", help="set top function name for out of context synthesis") 9 | parser.add_argument('-f', '--file_name', type=str, default="no_func", help="set output file name prefix") 10 | parser.add_argument('-a', '--app_name', type=str, default="no_func", help="set output file name prefix") 11 | 12 | args = parser.parse_args() 13 | workspace = args.workspace 14 | top_name = args.top 15 | file_name = args.file_name 16 | 17 | 18 | 19 | 20 | for i in range(100): 21 | file_out = open(workspace+'/_x/link/vivado/vpl/prj/prj.runs/impl_1/abs_gen'+str(i)+'.tcl', 'w') 22 | file_out.write('open_checkpoint design_route.dcp\n') 23 | file_out.write('update_design -cell level0_i/ulp/ydma_1/page'+str(i)+'_inst -black_box\n') 24 | file_out.write('lock_design -level routing\n') 25 | file_out.write('write_abstract_shell -force -cell level0_i/ulp/ydma_1/page'+str(i)+'_inst p_'+str(i)+'\n') 26 | file_out.close() 27 | 28 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/shell/run_gen_pfm_dymanic.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | workspace=$1 3 | 4 | 5 | cd ${workspace}/_x/link/vivado/vpl/prj/prj.runs/impl_1/ 6 | vivado -mode batch -source gen_pfm_dynamic.tcl 7 | cd - 8 | cp ${workspace}/_x/link/vivado/vpl/prj/prj.runs/impl_1/pfm_dynamic.dcp ./checkpoint 9 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/shell/run_python.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | python_name=$1 4 | python_arg1=$2 5 | python_arg2=$3 6 | python_arg3=$4 7 | python_arg4=$5 8 | 9 | python3 ${python_name} ${python_arg1} -t ${python_arg2} -f ${python_arg3} -a ${python_arg4} 10 | 11 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/shell/run_tcl.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | tcl_name=$1 4 | tcl_argv=$2 5 | 6 | vivado -mode batch -source ${tcl_name} -tclargs $2 7 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/src4level2/page/page.v: -------------------------------------------------------------------------------- 1 | module page( 2 | input wire clk, 3 | input wire [48 : 0] din_leaf_bft2interface, 4 | output reg [48 : 0] dout_leaf_interface2bft, 5 | input wire resend, 6 | input wire reset 7 | ); 8 | 9 | always@(posedge clk)begin 10 | if(reset) begin 11 | dout_leaf_interface2bft <= 0; 12 | end else if(resend) begin 13 | dout_leaf_interface2bft <= din_leaf_bft2interface; 14 | end else begin 15 | dout_leaf_interface2bft <= dout_leaf_interface2bft; 16 | end 17 | end 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/tcl/empty_pfm_dynamic.tcl: -------------------------------------------------------------------------------- 1 | set cell_name ydma 2 | open_checkpoint ./checkpoint/pfm_dynamic.dcp 3 | update_design -black_box -cells ${cell_name}_1 4 | write_checkpoint -force ./checkpoint/pfm_dynamic_bb.dcp 5 | 6 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/tcl/out_of_context_syn_page.tcl: -------------------------------------------------------------------------------- 1 | set top_name page 2 | 3 | set dir "./src4level2/page" 4 | set contents [glob -nocomplain -directory $dir *] 5 | foreach item $contents { 6 | if { [regexp {.*\.tcl} $item] } { 7 | source $item 8 | } else { 9 | add_files -norecurse $item 10 | } 11 | } 12 | 13 | set_param general.maxThreads 8 14 | set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY XPM_FIFO} [current_project] 15 | set logFileId [open ./runOOC.log "w"] 16 | set start_time [clock seconds] 17 | set_param general.maxThreads 8 18 | synth_design -top $top_name -part xcu50-fsvh2104-2-e -mode out_of_context 19 | write_checkpoint -force ./checkpoint/$top_name.dcp 20 | set end_time [clock seconds] 21 | set total_seconds [expr $end_time - $start_time] 22 | puts $logFileId "syn: $total_seconds seconds" 23 | report_utilization -hierarchical > utilization.rpt 24 | 25 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/tcl/out_of_context_syn_ydma_bb.tcl: -------------------------------------------------------------------------------- 1 | set top_name ydma_bb 2 | 3 | set dir "./src4level2/ydma_bb" 4 | set contents [glob -nocomplain -directory $dir *] 5 | foreach item $contents { 6 | if { [regexp {.*\.tcl} $item] } { 7 | source $item 8 | } else { 9 | add_files -norecurse $item 10 | } 11 | } 12 | 13 | set_param general.maxThreads 8 14 | set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY XPM_FIFO} [current_project] 15 | set logFileId [open ./runOOC.log "w"] 16 | set start_time [clock seconds] 17 | set_param general.maxThreads 8 18 | synth_design -top $top_name -part xcu50-fsvh2104-2-e -mode out_of_context 19 | write_checkpoint -force ./checkpoint/$top_name.dcp 20 | set end_time [clock seconds] 21 | set total_seconds [expr $end_time - $start_time] 22 | puts $logFileId "syn: $total_seconds seconds" 23 | report_utilization -hierarchical > utilization.rpt 24 | 25 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/tcl/replace_sub_module_level1.tcl: -------------------------------------------------------------------------------- 1 | set kl_name ydma_bb 2 | 3 | add_files ./checkpoint/pfm_dynamic_bb.dcp 4 | add_files ./checkpoint/${kl_name}.dcp 5 | set_property SCOPED_TO_CELLS { ydma_1 } [get_files ./checkpoint/${kl_name}.dcp] 6 | link_design -mode default -part xcu50-fsvh2104-2-e -top ulp 7 | write_checkpoint -force ./checkpoint/pfm_dynamic_new_bb.dcp 8 | 9 | 10 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/tcl/sub_divided.tcl: -------------------------------------------------------------------------------- 1 | 2 | open_checkpoint ./checkpoint/hw_bb_locked.dcp 3 | pr_subdivide -cell level0_i/ulp -subcells {level0_i/ulp/ydma_1/page2_inst level0_i/ulp/ydma_1/page3_inst level0_i/ulp/ydma_1/page4_inst level0_i/ulp/ydma_1/page5_inst level0_i/ulp/ydma_1/page6_inst level0_i/ulp/ydma_1/page7_inst level0_i/ulp/ydma_1/page8_inst level0_i/ulp/ydma_1/page9_inst level0_i/ulp/ydma_1/page10_inst level0_i/ulp/ydma_1/page11_inst level0_i/ulp/ydma_1/page12_inst level0_i/ulp/ydma_1/page13_inst level0_i/ulp/ydma_1/page14_inst level0_i/ulp/ydma_1/page15_inst level0_i/ulp/ydma_1/page16_inst level0_i/ulp/ydma_1/page17_inst level0_i/ulp/ydma_1/page18_inst level0_i/ulp/ydma_1/page19_inst level0_i/ulp/ydma_1/page20_inst level0_i/ulp/ydma_1/page21_inst level0_i/ulp/ydma_1/page22_inst level0_i/ulp/ydma_1/page23_inst } ./checkpoint/pfm_dynamic_new_bb.dcp 4 | write_checkpoint -force ./checkpoint/hw_bb_divided.dcp 5 | 6 | -------------------------------------------------------------------------------- /common/hipr/au50_dfx_hipr/xdc/dummy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/common/hipr/au50_dfx_hipr/xdc/dummy -------------------------------------------------------------------------------- /common/metadata/au50_100M/ydma_xml.rtd: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": { 3 | "major": "1", 4 | "minor": "0", 5 | "patch": "0" 6 | }, 7 | "clock_freq_topology": { 8 | "m_count": "3", 9 | "m_clock_freq": { 10 | "clock_freq": { 11 | "m_freq_Mhz": "450", 12 | "m_type": "SYSTEM", 13 | "m_name": "hbm_aclk", 14 | "m_original_name": "hbm_aclk" 15 | }, 16 | "": { 17 | "m_freq_Mhz": "500", 18 | "m_type": "KERNEL", 19 | "m_name": "KERNEL_CLK", 20 | "m_original_name": "clk_kernel2_in" 21 | }, 22 | "": { 23 | "m_freq_Mhz": "100", 24 | "m_type": "DATA", 25 | "m_name": "DATA_CLK", 26 | "m_original_name": "clk_kernel_in" 27 | } 28 | } 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /common/metadata/au50_150M/ydma_xml.rtd: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": { 3 | "major": "1", 4 | "minor": "0", 5 | "patch": "0" 6 | }, 7 | "clock_freq_topology": { 8 | "m_count": "3", 9 | "m_clock_freq": { 10 | "clock_freq": { 11 | "m_freq_Mhz": "450", 12 | "m_type": "SYSTEM", 13 | "m_name": "hbm_aclk", 14 | "m_original_name": "hbm_aclk" 15 | }, 16 | "": { 17 | "m_freq_Mhz": "500", 18 | "m_type": "KERNEL", 19 | "m_name": "KERNEL_CLK", 20 | "m_original_name": "clk_kernel2_in" 21 | }, 22 | "": { 23 | "m_freq_Mhz": "150", 24 | "m_type": "DATA", 25 | "m_name": "DATA_CLK", 26 | "m_original_name": "clk_kernel_in" 27 | } 28 | } 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /common/metadata/au50_200M/ydma_xml.rtd: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": { 3 | "major": "1", 4 | "minor": "0", 5 | "patch": "0" 6 | }, 7 | "clock_freq_topology": { 8 | "m_count": "3", 9 | "m_clock_freq": { 10 | "clock_freq": { 11 | "m_freq_Mhz": "450", 12 | "m_type": "SYSTEM", 13 | "m_name": "hbm_aclk", 14 | "m_original_name": "hbm_aclk" 15 | }, 16 | "": { 17 | "m_freq_Mhz": "500", 18 | "m_type": "KERNEL", 19 | "m_name": "KERNEL_CLK", 20 | "m_original_name": "clk_kernel2_in" 21 | }, 22 | "": { 23 | "m_freq_Mhz": "100", 24 | "m_type": "DATA", 25 | "m_name": "DATA_CLK", 26 | "m_original_name": "clk_kernel_in" 27 | } 28 | } 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /common/metadata/au50_300M/ydma_xml.rtd: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": { 3 | "major": "1", 4 | "minor": "0", 5 | "patch": "0" 6 | }, 7 | "clock_freq_topology": { 8 | "m_count": "3", 9 | "m_clock_freq": { 10 | "clock_freq": { 11 | "m_freq_Mhz": "450", 12 | "m_type": "SYSTEM", 13 | "m_name": "hbm_aclk", 14 | "m_original_name": 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} else { 16 | add_files -norecurse $item 17 | } 18 | } 19 | set_param general.maxThreads 8 20 | set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY XPM_FIFO} [current_project] 21 | set logFileId [open ./runLog_user_kernel.log "w"] 22 | set start_time [clock seconds] 23 | set_param general.maxThreads 8 24 | synth_design -top leaf -part xczu9eg-ffvb1156-2-e -mode out_of_context 25 | write_checkpoint -force page_netlist.dcp 26 | set end_time [clock seconds] 27 | set total_seconds [expr $end_time - $start_time] 28 | puts $logFileId "syn: $total_seconds seconds" 29 | report_utilization -hierarchical > utilization.rpt 30 | 31 | -------------------------------------------------------------------------------- /common/riscv_bram/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | source /opt/Xilinx/SDx/2018.2/settings64.sh 3 | vivado -mode batch -source dummy.tcl 4 | 5 | -------------------------------------------------------------------------------- /common/riscv_bram/src/rise_detect.v: -------------------------------------------------------------------------------- 1 | module rise_detect #( 2 | parameter integer data_width = 8 3 | ) 4 | ( 5 | output reg [data_width-1:0]data_out, 6 | input [data_width-1:0] data_in, 7 | input clk, 8 | input reset 9 | ); 10 | 11 | reg [data_width-1:0] data_in_1; 12 | reg [data_width-1:0] data_in_2; 13 | 14 | always@(posedge clk) begin 15 | if(reset) begin 16 | {data_in_2, data_in_1} <= 0; 17 | end else begin 18 | {data_in_2, data_in_1} <= {data_in_1, data_in}; 19 | end 20 | end 21 | 22 | wire [data_width-1:0] data_out_comb; 23 | assign data_out_comb = (~data_in_2) & (data_in_1); 24 | 25 | always@(posedge clk) begin 26 | if(reset) begin 27 | data_out <= 0; 28 | end else begin 29 | data_out <= data_out_comb; 30 | end 31 | end 32 | 33 | 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /common/riscv_bram/src/write_b_in.v: -------------------------------------------------------------------------------- 1 | /** port == 2,3,4 2 | * bft to bram_in_2,bram_in_3,bram_in_4 3 | */ 4 | 5 | module write_b_in#( 6 | parameter NUM_PORT_BITS = 4, 7 | parameter PAYLOAD_BITS = 64, 8 | parameter NUM_ADDR_BITS = 7, 9 | parameter PORT_No = 2 10 | )( 11 | output reg wea, 12 | output reg [NUM_ADDR_BITS-1:0] addra, 13 | output reg [PAYLOAD_BITS:0] dina, 14 | input clk, 15 | input reset, 16 | input [NUM_PORT_BITS-1:0] port, 17 | input [NUM_ADDR_BITS-1:0] addr, 18 | input vldBit, 19 | input [PAYLOAD_BITS-1:0] payload); 20 | 21 | always@(posedge clk) begin 22 | if(reset) begin 23 | wea <= 0; 24 | addra <= 0; 25 | dina <= 0; 26 | end 27 | else begin 28 | if(port==PORT_No && vldBit) begin // need to be changed! 29 | wea <= 1; 30 | addra <= addr; 31 | dina <= {vldBit,payload}; 32 | end 33 | else begin 34 | wea <= 0; 35 | addra <= 0; // random 36 | dina <= 0; // random 37 | end 38 | end 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /common/riscv_bram/src/write_b_out.v: -------------------------------------------------------------------------------- 1 | module write_b_out#( 2 | parameter PAYLOAD_BITS = 64 3 | )( 4 | input vld_user2b_out, 5 | input [PAYLOAD_BITS-1:0] din_leaf_user2interface, 6 | input full, 7 | 8 | output reg wr_en, 9 | output reg [PAYLOAD_BITS-1:0] din); 10 | 11 | // assign wr_en = (full) ? 0 : (vld_user2b_out) ? 1 : 0; 12 | // assign din = (full) ? 42 : (vld_user2b_out) ? din_leaf_user2interface : 42; 13 | 14 | always@(*) begin 15 | if(full) begin // can't push in to fifo 16 | wr_en = 0; 17 | din = 42; // random, because this data won't be written anyway 18 | end 19 | else begin 20 | if(vld_user2b_out) begin 21 | wr_en = 1; 22 | din = din_leaf_user2interface; 23 | end 24 | else begin 25 | wr_en = 0; 26 | din = 42; // random, because this data won't be written anyway 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /common/riscv_src/riscv/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: 3 | ./qsub_run.sh 4 | /opt/riscv32i/bin/riscv32-unknown-elf-objdump -S firmware.elf > out.S 5 | 6 | clean: 7 | rm -rf ./*.o ./*.elf ./*.hex ./*.bin 8 | -------------------------------------------------------------------------------- /common/riscv_src/riscv/firmware.h: -------------------------------------------------------------------------------- 1 | // This is free and unencumbered software released into the public domain. 2 | // 3 | // Anyone is free to copy, modify, publish, use, compile, sell, or 4 | // distribute this software, either in source code form or as a compiled 5 | // binary, for any purpose, commercial or non-commercial, and by any 6 | // means. 7 | 8 | #ifndef FIRMWARE_H 9 | #define FIRMWARE_H 10 | 11 | #include 12 | #include 13 | #include "typedefs.h" 14 | 15 | // irq.c 16 | uint32_t *irq(uint32_t *regs, uint32_t irqs); 17 | 18 | // print.c 19 | void print_chr(char ch); 20 | void print_str(const char *p); 21 | void print_dec(unsigned int val); 22 | void print_hex(unsigned int val, int digits); 23 | void print_float(float din); 24 | uint32_t read_word1(void); 25 | void write_word1(uint32_t out_value); 26 | uint32_t read_word2(void); 27 | void write_word2(uint32_t out_value); 28 | uint32_t read_word3(void); 29 | void write_word3(uint32_t out_value); 30 | uint32_t read_word4(void); 31 | void write_word4(uint32_t out_value); 32 | 33 | 34 | // stream.c 35 | void stream(void); 36 | 37 | // stats.c 38 | void stats(void); 39 | 40 | // operator 41 | #endif 42 | -------------------------------------------------------------------------------- /common/riscv_src/riscv/main.cpp: -------------------------------------------------------------------------------- 1 | // This is free and unencumbered software released into the public domain. 2 | // 3 | // Anyone is free to copy, modify, publish, use, compile, sell, or 4 | // distribute this software, either in source code form or as a compiled 5 | // binary, for any purpose, commercial or non-commercial, and by any 6 | // means. 7 | 8 | // A simple Sieve of Eratosthenes 9 | 10 | #include "firmware.h" 11 | 12 | #define STREAMOUT1 0x10000008 13 | #define STREAMOUT2 0x10000010 14 | #define STREAMOUT3 0x10000018 15 | #define STREAMOUT4 0x10000020 16 | #define STREAMOUT5 0x10000028 17 | #define STREAMIN1 0x10000004 18 | #define STREAMIN2 0x1000000c 19 | #define STREAMIN3 0x10000014 20 | #define STREAMIN4 0x1000001c 21 | #define STREAMIN5 0x10000024 22 | 23 | int main(void) 24 | { 25 | char const *s = "Hello world!\n"; 26 | print_str(s); 27 | int i = 0; 28 | //stream operator instance; 29 | return 0; 30 | 31 | } 32 | -------------------------------------------------------------------------------- /common/riscv_src/riscv/sections.lds: -------------------------------------------------------------------------------- 1 | /* 2 | This is free and unencumbered software released into the public domain. 3 | 4 | Anyone is free to copy, modify, publish, use, compile, sell, or 5 | distribute this software, either in source code form or as a compiled 6 | binary, for any purpose, commercial or non-commercial, and by any 7 | means. 8 | */ 9 | 10 | MEMORY { 11 | /* the memory in the testbench is 128k in size; 12 | * set LENGTH=96k and leave at least 32k for stack */ 13 | mem : ORIGIN = 0x00000000, LENGTH = 0x00004000 14 | } 15 | 16 | SECTIONS { 17 | .memory : { 18 | . = 0x000000; 19 | _start*(.text); 20 | *(.text); 21 | *(*); 22 | end = .; 23 | PROVIDE ( __global_pointer$ = . + 0x800 ); 24 | . = ALIGN(4); 25 | _edata = ABSOLUTE ( . ); 26 | _end = .; 27 | } > mem 28 | } 29 | -------------------------------------------------------------------------------- /common/riscv_src/riscv/stream.cpp: -------------------------------------------------------------------------------- 1 | // This is free and unencumbered software released into the public domain. 2 | // 3 | // Anyone is free to copy, modify, publish, use, compile, sell, or 4 | // distribute this software, either in source code form or as a compiled 5 | // binary, for any purpose, commercial or non-commercial, and by any 6 | // means. 7 | 8 | // A simple Sieve of Eratosthenes 9 | #include "firmware.h" 10 | //#include "ap_int.h" 11 | static void stats_print_dec(unsigned int val, int digits, bool zero_pad) 12 | { 13 | char buffer[32]; 14 | char *p = buffer; 15 | while (val || digits > 0) { 16 | if (val) 17 | *(p++) = '0' + val % 10; 18 | else 19 | *(p++) = zero_pad ? '0' : ' '; 20 | val = val / 10; 21 | digits--; 22 | } 23 | while (p != buffer) { 24 | if (p[-1] == ' ' && p[-2] == ' ') p[-1] = '.'; 25 | print_chr(*(--p)); 26 | } 27 | print_chr('\n'); 28 | } 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /common/riscv_src/src/rise_detect.v: -------------------------------------------------------------------------------- 1 | module rise_detect #( 2 | parameter integer data_width = 8 3 | ) 4 | ( 5 | output reg [data_width-1:0]data_out, 6 | input [data_width-1:0] data_in, 7 | input clk, 8 | input reset 9 | ); 10 | 11 | reg [data_width-1:0] data_in_1; 12 | reg [data_width-1:0] data_in_2; 13 | 14 | always@(posedge clk) begin 15 | if(reset) begin 16 | {data_in_2, data_in_1} <= 0; 17 | end else begin 18 | {data_in_2, data_in_1} <= {data_in_1, data_in}; 19 | end 20 | end 21 | 22 | wire [data_width-1:0] data_out_comb; 23 | assign data_out_comb = (~data_in_2) & (data_in_1); 24 | 25 | always@(posedge clk) begin 26 | if(reset) begin 27 | data_out <= 0; 28 | end else begin 29 | data_out <= data_out_comb; 30 | end 31 | end 32 | 33 | 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /common/script_src/gen.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | # source /opt/Xilinx/Vivado/2018.2/Settings64.sh 3 | bitstream=$1 4 | xmlfile=$2 5 | xclbin=$3 6 | 7 | 8 | xclbinutil --add-section DEBUG_IP_LAYOUT:JSON:../F001_overlay/ydma/au50/_x/link/int/debug_ip_layout.rtd \ 9 | --add-section BITSTREAM:RAW:${bitstream} \ 10 | --force --target hw --key-value SYS:dfx_enable:true \ 11 | --add-section :JSON:../F001_overlay/ydma/au50/_x/link/int/ydma.rtd \ 12 | --append-section :JSON:../F001_overlay/ydma/au50/_x/link/int/appendSection.rtd \ 13 | --add-section EMBEDDED_METADATA:RAW:${xmlfile} \ 14 | --add-section CLOCK_FREQ_TOPOLOGY:JSON:../F001_overlay/ydma/au50/_x/link/int/ydma_xml.rtd \ 15 | --add-section BUILD_METADATA:JSON:../F001_overlay/ydma/au50/_x/link/int/ydma_build.rtd \ 16 | --add-section SYSTEM_METADATA:RAW:../F001_overlay/ydma/au50/_x/link/int/systemDiagramModelSlrBaseAddress.json \ 17 | --key-value SYS:PlatformVBNV:xilinx_u50_gen3x16_xdma_201920_3 \ 18 | --output ./${xclbin} 19 | -------------------------------------------------------------------------------- /common/script_src/gen_resource.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | # -*- coding: utf-8 -*- 3 | import re 4 | 5 | 6 | if __name__ == '__main__': 7 | 8 | clb_list = [] 9 | ff_list = [] 10 | bram_list = [] 11 | dsp_list = [] 12 | 13 | resource_dist = open("resource.csv", 'w') 14 | for i in range(2, 32): 15 | file_in = open('./p_'+str(i)+'.rpt', 'r') 16 | out_str = 'p_'+str(i) 17 | for line in file_in: 18 | if line.startswith('| CLB LUTs'): 19 | clb = re.findall(r"\d+", line) 20 | clb_list.append(clb[2]) 21 | out_str+=','+clb[2] 22 | 23 | if line.startswith('| CLB Registers'): 24 | ff = re.findall(r"\d+", line) 25 | ff_list.append(ff[2]) 26 | out_str+=','+ff[2] 27 | 28 | if line.startswith('| Block'): 29 | bram = re.findall(r"\d+", line) 30 | bram_list.append(bram[2]) 31 | out_str+=','+bram[2] 32 | 33 | if line.startswith('| DSPs'): 34 | dsp = re.findall(r"\d+", line) 35 | dsp_list.append(dsp[2]) 36 | out_str+=','+dsp[2] 37 | print out_str 38 | resource_dist.write(out_str+'\n') 39 | file_in.close() 40 | 41 | resource_dist.close() 42 | 43 | 44 | 45 | -------------------------------------------------------------------------------- /common/script_src/gen_runtime.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | Xilinx_dir 3 | xrt_dir 4 | g++ -Wall -g -std=c++11 host.cpp -o app.exe -I${XILINX_XRT}/include/ -I${XILINX_VIVADO}/include/ -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ 5 | -------------------------------------------------------------------------------- /common/script_src/gen_runtime_au50.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | source Xilinx_dir 3 | source xrt_dir 4 | g++ -Wall -g -std=c++11 host.cpp -o ../../app.exe -I${XILINX_XRT}/include/ -I${XILINX_VIVADO}/include/ -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ 5 | -------------------------------------------------------------------------------- /common/script_src/gen_runtime_ultra96.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | Xilinx_dir 3 | export PLATFORM_REPO_PATHS= 4 | export ROOTFS= 5 | export MaxJobNum=$(nproc) 6 | #export MaxJobNum=10 7 | 8 | unset LD_LIBRARY_PATH 9 | 10 | sdk_dir 11 | 12 | ${CXX} -Wall -g -std=c++11 host.cpp -o ./sd_card/app.exe \ 13 | -I/usr/include/xrt \ 14 | -I${XILINX_VIVADO}/include \ 15 | -lOpenCL \ 16 | -lpthread \ 17 | -lrt \ 18 | -lstdc++ 19 | 20 | 21 | -------------------------------------------------------------------------------- /common/script_src/gen_runtime_zcu102.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | # Xilinx_dir 3 | export PLATFORM_REPO_PATHS= 4 | export ROOTFS= 5 | export MaxJobNum=$(nproc) 6 | #export MaxJobNum=10 7 | 8 | # xrt_dir 9 | unset LD_LIBRARY_PATH 10 | util_src=$(ls ./util/*.cpp) | true 11 | # sdk_dir 12 | 13 | ${CXX} -Wall -g -std=c++11 host.cpp ${util_src} -o ./app.exe \ 14 | -I/usr/include/xrt \ 15 | -I${XILINX_VIVADO}/include \ 16 | -lOpenCL \ 17 | -lpthread \ 18 | -lrt \ 19 | -lstdc++ 20 | 21 | # cp_cmd 22 | 23 | 24 | -------------------------------------------------------------------------------- /common/script_src/gen_xclbin_au50.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | # source /opt/Xilinx/Vivado/2018.2/Settings64.sh 3 | bitstream=$1 4 | xmlfile=$2 5 | xclbin=$3 6 | workspace=$4 7 | 8 | xclbinutil --add-section DEBUG_IP_LAYOUT:JSON:${workspace}/ydma/au50/_x/link/int/debug_ip_layout.rtd \ 9 | --add-section BITSTREAM:RAW:${bitstream} \ 10 | --force --target hw --key-value SYS:dfx_enable:true \ 11 | --add-section :JSON:${workspace}/ydma/au50/_x/link/int/ydma.rtd \ 12 | --append-section :JSON:${workspace}/ydma/au50/_x/link/int/appendSection.rtd \ 13 | --add-section EMBEDDED_METADATA:RAW:${xmlfile} \ 14 | --add-section CLOCK_FREQ_TOPOLOGY:JSON:${workspace}/ydma/au50/_x/link/int/ydma_xml.rtd \ 15 | --add-section BUILD_METADATA:JSON:${workspace}/ydma/au50/_x/link/int/ydma_build.rtd \ 16 | --add-section SYSTEM_METADATA:RAW:${workspace}/ydma/au50/_x/link/int/systemDiagramModelSlrBaseAddress.json \ 17 | --key-value SYS:PlatformVBNV:xilinx_u50_gen3x16_xdma_201920_3 \ 18 | --output ./${xclbin} 19 | -------------------------------------------------------------------------------- /common/script_src/gen_xclbin_ultra96.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | # source /opt/Xilinx/Vivado/2018.2/Settings64.sh 3 | bitstream=$1 4 | xmlfile=$2 5 | xclbin=$3 6 | 7 | xclbinutil --add-section DEBUG_IP_LAYOUT:JSON:../F001_overlay/ydma/ultra96/_x/link/int/debug_ip_layout.rtd \ 8 | --add-section BITSTREAM:RAW:${bitstream} \ 9 | --force --target hw --key-value SYS:dfx_enable:true \ 10 | --add-section :JSON:../F001_overlay/ydma/ultra96/_x/link/int/ydma.rtd \ 11 | --add-section CLOCK_FREQ_TOPOLOGY:JSON:../F001_overlay/ydma/ultra96/_x/link/int/ydma_xml.rtd \ 12 | --add-section BUILD_METADATA:JSON:../F001_overlay/ydma/ultra96/_x/link/int/ydma_build.rtd \ 13 | --add-section EMBEDDED_METADATA:RAW:${xmlfile} \ 14 | --add-section SYSTEM_METADATA:RAW:../F001_overlay/ydma/ultra96/_x/link/int/systemDiagramModelSlrBaseAddress.json \ 15 | --key-value SYS:PlatformVBNV:xilinx_ultra96_dynamic_0_0 \ 16 | --output ./${xclbin} 17 | 18 | -------------------------------------------------------------------------------- /common/script_src/gen_xclbin_zcu102.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | # source /opt/Xilinx/Vivado/2018.2/Settings64.sh 3 | bitstream=$1 4 | xmlfile=$2 5 | xclbin=$3 6 | 7 | 8 | xclbinutil --add-section DEBUG_IP_LAYOUT:JSON:./ydma/zcu102/_x/link/int/debug_ip_layout.rtd \ 9 | --add-section BITSTREAM:RAW:${bitstream} \ 10 | --force --target hw --key-value SYS:dfx_enable:true --add-section :JSON:./ydma/zcu102/_x/link/int/ydma.rtd \ 11 | --add-section CLOCK_FREQ_TOPOLOGY:JSON:./ydma/zcu102/_x/link/int/ydma_xml.rtd \ 12 | --add-section BUILD_METADATA:JSON:./ydma/zcu102/_x/link/int/ydma_build.rtd \ 13 | --add-section EMBEDDED_METADATA:RAW:${xmlfile} \ 14 | --add-section SYSTEM_METADATA:RAW:./ydma/zcu102/_x/link/int/systemDiagramModelSlrBaseAddress.json \ 15 | --key-value SYS:PlatformVBNV:xilinx_zcu102_dynamic_1_0 \ 16 | --output ./${xclbin} 17 | -------------------------------------------------------------------------------- /common/script_src/project_xsdk_core.tcl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/tclsh 2 | set core_num "0" 3 | set Benchmark_name optical_flow 4 | set vivado_prj "." 5 | set project_name ${Benchmark_name} 6 | set example_prj "Empty Application" 7 | set language "C++" 8 | set hdf_name "floorplan_static_wrapper" 9 | set core_name "psu_cortexa53_" 10 | set_workspace ./${vivado_prj} 11 | 12 | 13 | 14 | create_project -type hw -name ${hdf_name}_hw_platform_0 -hwspec ./${vivado_prj}/${hdf_name}.hdf 15 | create_project -type bsp -name ${project_name}${core_num}_bsp -hwproject ${hdf_name}_hw_platform_0 -proc ${core_name}${core_num} -os standalone 16 | create_project -type app -name ${project_name}${core_num} -hwproject floorplan_static_wrapper_hw_platform_0 -proc ${core_name}${core_num} -os standalone -lang ${language} -app {Empty Application} -bsp ${project_name}${core_num}_bsp 17 | file delete -force ./${vivado_prj}/${project_name}${core_num}/src/main.cc 18 | importsources -name ${project_name}${core_num} -path ./cpp_src 19 | 20 | 21 | 22 | #build -type bsp -name ${project_name}${core_num}_bsp 23 | #build -type app -name ${project_name}${core_num} 24 | #clean -type bsp -name ${project_name}${core_num}_bsp 25 | #clean -type all 26 | #build -type all 27 | -------------------------------------------------------------------------------- /common/script_src/qsub_main.sh: -------------------------------------------------------------------------------- 1 | lAddr="(youemail)@seas.upenn.edu" 2 | 3 | qsub -N rendering_test -q 70s@icgrid43 -hold_jid spam_mono -l mem=8G -pe onenode 1 -cwd ./qsub_run.sh 4 | -------------------------------------------------------------------------------- /common/script_src/qsub_run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | source /scratch/safe/SDSoC/SDx/2018.2/settings64.sh 3 | vivado -mode batch -source test.tcl 4 | -------------------------------------------------------------------------------- /common/script_src/run100_150.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | #my_dir= 4 | # 5 | #make prj_name= freq=300M overlay || true 6 | #sqsub(){ 7 | # mkdir -p workspace/qsub 8 | # qsub -N $1 -q 70s -hold_jid NONE -m abe -M qsub@qsub.com -l mem=100G -pe onenode 1 -o workspace/qsub -e workspace/qsub -cwd ./common/script_src/run_$1.sh 9 | #} 10 | # 11 | #sqsub rendering512 12 | #sqsub digit_reg512 13 | #sqsub spam_filter512 14 | #sqsub optical_flow512 15 | #sqsub face_detection512 16 | #sqsub bnn512 17 | 18 | 19 | make freq_start=100 freq_end=150 freq_diff=10 install 20 | 21 | 22 | -------------------------------------------------------------------------------- /common/script_src/run160_200.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | #my_dir= 4 | # 5 | #make prj_name= freq=300M overlay || true 6 | #sqsub(){ 7 | # mkdir -p workspace/qsub 8 | # qsub -N $1 -q 70s -hold_jid NONE -m abe -M qsub@qsub.com -l mem=100G -pe onenode 1 -o workspace/qsub -e workspace/qsub -cwd ./common/script_src/run_$1.sh 9 | #} 10 | # 11 | #sqsub rendering512 12 | #sqsub digit_reg512 13 | #sqsub spam_filter512 14 | #sqsub optical_flow512 15 | #sqsub face_detection512 16 | #sqsub bnn512 17 | 18 | 19 | make freq_start=160 freq_end=200 freq_diff=10 install 20 | 21 | 22 | -------------------------------------------------------------------------------- /common/script_src/run210_250.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | #my_dir= 4 | # 5 | #make prj_name= freq=300M overlay || true 6 | #sqsub(){ 7 | # mkdir -p workspace/qsub 8 | # qsub -N $1 -q 70s -hold_jid NONE -m abe -M qsub@qsub.com -l mem=100G -pe onenode 1 -o workspace/qsub -e workspace/qsub -cwd ./common/script_src/run_$1.sh 9 | #} 10 | # 11 | #sqsub rendering512 12 | #sqsub digit_reg512 13 | #sqsub spam_filter512 14 | #sqsub optical_flow512 15 | #sqsub face_detection512 16 | #sqsub bnn512 17 | 18 | 19 | make freq_start=210 freq_end=250 freq_diff=10 install 20 | 21 | 22 | -------------------------------------------------------------------------------- /common/script_src/run260_300.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | #my_dir= 4 | # 5 | #make prj_name= freq=300M overlay || true 6 | #sqsub(){ 7 | # mkdir -p workspace/qsub 8 | # qsub -N $1 -q 70s -hold_jid NONE -m abe -M qsub@qsub.com -l mem=100G -pe onenode 1 -o workspace/qsub -e workspace/qsub -cwd ./common/script_src/run_$1.sh 9 | #} 10 | # 11 | #sqsub rendering512 12 | #sqsub digit_reg512 13 | #sqsub spam_filter512 14 | #sqsub optical_flow512 15 | #sqsub face_detection512 16 | #sqsub bnn512 17 | 18 | 19 | make freq_start=260 freq_end=300 freq_diff=10 install 20 | 21 | 22 | -------------------------------------------------------------------------------- /common/script_src/run310_350.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | #my_dir= 4 | # 5 | #make prj_name= freq=300M overlay || true 6 | #sqsub(){ 7 | # mkdir -p workspace/qsub 8 | # qsub -N $1 -q 70s -hold_jid NONE -m abe -M qsub@qsub.com -l mem=100G -pe onenode 1 -o workspace/qsub -e workspace/qsub -cwd ./common/script_src/run_$1.sh 9 | #} 10 | # 11 | #sqsub rendering512 12 | #sqsub digit_reg512 13 | #sqsub spam_filter512 14 | #sqsub optical_flow512 15 | #sqsub face_detection512 16 | #sqsub bnn512 17 | 18 | 19 | make freq_start=310 freq_end=350 freq_diff=10 install 20 | 21 | 22 | -------------------------------------------------------------------------------- /common/script_src/run360_400.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | #my_dir= 4 | # 5 | #make prj_name= freq=300M overlay || true 6 | #sqsub(){ 7 | # mkdir -p workspace/qsub 8 | # qsub -N $1 -q 70s -hold_jid NONE -m abe -M qsub@qsub.com -l mem=100G -pe onenode 1 -o workspace/qsub -e workspace/qsub -cwd ./common/script_src/run_$1.sh 9 | #} 10 | # 11 | #sqsub rendering512 12 | #sqsub digit_reg512 13 | #sqsub spam_filter512 14 | #sqsub optical_flow512 15 | #sqsub face_detection512 16 | #sqsub bnn512 17 | 18 | 19 | make freq_start=360 freq_end=400 freq_diff=10 install 20 | 21 | 22 | -------------------------------------------------------------------------------- /common/script_src/run_bnn512.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | make prj_name=bnn512 freq=150M overlay 3 | make prj_name=bnn512 freq=150M -j12 4 | 5 | -------------------------------------------------------------------------------- /common/script_src/run_digit_reg512.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | 4 | make prj_name=digit_reg512 freq=200M overlay 5 | make prj_name=digit_reg512 freq=200M -j12 6 | -------------------------------------------------------------------------------- /common/script_src/run_face_detection512.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | make prj_name=face_detection512 freq=200M overlay 4 | make prj_name=face_detection512 freq=200M -j12 5 | -------------------------------------------------------------------------------- /common/script_src/run_optical_flow512.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | make prj_name=optical_flow512 freq=200M overlay 4 | make prj_name=optical_flow512 freq=200M -j12 5 | -------------------------------------------------------------------------------- /common/script_src/run_rendering512.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | make prj_name=rendering512 freq=200M overlay 4 | make prj_name=rendering512 freq=200M -j12 5 | -------------------------------------------------------------------------------- /common/script_src/run_spam_filter512.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | make prj_name=spam_filter512 freq=200M overlay 4 | make prj_name=spam_filter512 freq=200M -j12 5 | -------------------------------------------------------------------------------- /common/sim_src/counter1.v: -------------------------------------------------------------------------------- 1 | module counter1 #( 2 | parameter CNT_WIDTH = 32 3 | )( 4 | input clk, 5 | input reset, 6 | input valid, 7 | input ready, 8 | output reg [CNT_WIDTH-1:0] cnt1 9 | ); 10 | 11 | 12 | 13 | always@(posedge clk) begin 14 | if (reset) 15 | cnt1 <= 0; 16 | else if(valid && ready) 17 | cnt1 <= cnt1 + 1; 18 | else 19 | cnt1 <= cnt1; 20 | end 21 | 22 | 23 | endmodule 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /common/verilog_src/README.md: -------------------------------------------------------------------------------- 1 | high speed interface 2 | -------------------------------------------------------------------------------- /common/verilog_src/bft_level_0.v: -------------------------------------------------------------------------------- 1 | module bft_level_0( 2 | input clk, 3 | input [195:0] din0, 4 | input [195:0] din1, 5 | input [195:0] din2, 6 | input [195:0] din3, 7 | input reset, 8 | output [195:0] l_bus_o, 9 | output [195:0] l_but_o1, 10 | output [195:0] r_but_o, 11 | output [195:0] r_but_o1); 12 | 13 | 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /common/verilog_src/bft_level_1.v: -------------------------------------------------------------------------------- 1 | module bft_level_1( 2 | input clk, 3 | input [195:0] din, 4 | input [48:0] leaf_0_in, 5 | input [48:0] leaf_1_in, 6 | input [48:0] leaf_2_in, 7 | input [48:0] leaf_3_in, 8 | input [48:0] leaf_4_in, 9 | input [48:0] leaf_5_in, 10 | input [48:0] leaf_6_in, 11 | input [48:0] leaf_7_in, 12 | input reset, 13 | 14 | output [195:0] bus_o, 15 | output [48:0] leaf_0_out, 16 | output [48:0] leaf_1_out, 17 | output [48:0] leaf_2_out, 18 | output [48:0] leaf_3_out, 19 | output [48:0] leaf_4_out, 20 | output [48:0] leaf_5_out, 21 | output [48:0] leaf_6_out, 22 | output [48:0] leaf_7_out, 23 | output resend_0, 24 | output resend_1, 25 | output resend_2, 26 | output resend_3, 27 | output resend_4, 28 | output resend_5, 29 | output resend_6, 30 | output resend_7); 31 | 32 | 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /common/verilog_src/clock_100M_100M.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.000 -name clk_bft [get_ports clk_bft] 2 | create_clock -period 10.000 -name clk_user [get_ports clk_user] 3 | -------------------------------------------------------------------------------- /common/verilog_src/clock_constraints.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 3.3 -name clk_bft [get_ports clk_bft] 2 | create_clock -period 4 -name clk_user [get_ports clk_user] 3 | -------------------------------------------------------------------------------- /common/verilog_src/counter1.v: -------------------------------------------------------------------------------- 1 | module counter1 #( 2 | parameter CNT_WIDTH = 32 3 | )( 4 | input clk, 5 | input reset, 6 | input valid, 7 | input ready, 8 | output reg [CNT_WIDTH-1:0] cnt1 9 | ); 10 | 11 | 12 | 13 | always@(posedge clk) begin 14 | if (reset) 15 | cnt1 <= 0; 16 | else if(valid && ready) 17 | cnt1 <= cnt1 + 1; 18 | else 19 | cnt1 <= cnt1; 20 | end 21 | 22 | 23 | endmodule 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /common/verilog_src/direction_determiner_0.v: -------------------------------------------------------------------------------- 1 | `include "direction_params.vh" 2 | module direction_determiner_0 ( 3 | input valid_i, 4 | input [$clog2(num_leaves)-1:0] addr_i, 5 | output reg [1:0] d 6 | ); 7 | 8 | // override these values in top modules 9 | parameter num_leaves= 0; 10 | parameter addr= 0; 11 | parameter level= 0; //level = $bits(addr) 12 | 13 | generate 14 | if (level == 0) begin 15 | always @* 16 | if (valid_i) begin 17 | if (addr_i[$clog2(num_leaves)-1]) 18 | d= `RIGHT; 19 | else 20 | d= `LEFT; 21 | end 22 | else 23 | d= `VOID; 24 | end 25 | else begin 26 | wire [level-1:0] addr_xnor_addr_i= 27 | ~(addr ^ addr_i[$clog2(num_leaves)-1:$clog2(num_leaves) - level]); 28 | 29 | always @* 30 | if (valid_i == 1'b0) 31 | d= `VOID; 32 | else if (&addr_xnor_addr_i == 1'b1) begin 33 | if (addr_i[$clog2(num_leaves)-1 - level] == 1'b0) 34 | d= `LEFT; 35 | else 36 | d= `RIGHT; 37 | end 38 | else if (&addr_xnor_addr_i == 1'b0) 39 | d= `UP; 40 | else 41 | d= `VOID; 42 | end 43 | endgenerate 44 | endmodule 45 | -------------------------------------------------------------------------------- /common/verilog_src/direction_params.vh: -------------------------------------------------------------------------------- 1 | `ifndef DIRECTION_PARAMS_H 2 | `define DIRECTION_PARAMS_H 3 | `define VOID 2'b00 4 | `define LEFT 2'b01 5 | `define RIGHT 2'b10 6 | `define UP 2'b11 7 | // Used for pi switch 8 | `define UPL 2'b11 9 | `define UPR 2'b00 // replaces VOID in t_switch 10 | `endif 11 | -------------------------------------------------------------------------------- /common/verilog_src/floorplan_static_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018 4 | //Date : Wed May 27 16:48:11 2020 5 | //Host : ylxiao-OptiPlex-7050 running 64-bit Ubuntu 18.04.4 LTS 6 | //Command : generate_target floorplan_static_wrapper.bd 7 | //Design : floorplan_static_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module floorplan_static_wrapper 13 | (); 14 | 15 | 16 | floorplan_static floorplan_static_i 17 | (); 18 | endmodule 19 | -------------------------------------------------------------------------------- /common/verilog_src/pipe_ff.v: -------------------------------------------------------------------------------- 1 | module pipe_ff ( 2 | input clk, 3 | input reset, 4 | input [data_width-1:0] din, 5 | output reg [data_width-1:0] dout 6 | ); 7 | 8 | parameter data_width= 2; 9 | 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | dout <= 0; 14 | else 15 | dout <=din; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /common/verilog_src/pipe_ff_0.v: -------------------------------------------------------------------------------- 1 | module pipe_ff_0 ( 2 | input clk, 3 | input reset, 4 | input [data_width-1:0] din, 5 | output reg [data_width-1:0] dout 6 | ); 7 | 8 | parameter data_width= 2; 9 | 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | dout <= 0; 14 | else 15 | dout <=din; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /common/verilog_src/pipe_ff_1.v: -------------------------------------------------------------------------------- 1 | module pipe_ff_1 ( 2 | input clk, 3 | input reset, 4 | input [data_width-1:0] din, 5 | output reg [data_width-1:0] dout 6 | ); 7 | 8 | parameter data_width= 2; 9 | 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | dout <= 0; 14 | else 15 | dout <=din; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /common/verilog_src/sel_vld.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 07/19/2020 04:06:19 PM 7 | // Design Name: 8 | // Module Name: sel_vld 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module sel_vld( 24 | input [48:0] in_port, 25 | output vld_out 26 | 27 | ); 28 | 29 | assign vld_out = in_port[48]; 30 | endmodule 31 | -------------------------------------------------------------------------------- /common/verilog_src/write_b_in.v: -------------------------------------------------------------------------------- 1 | /** port == 2,3,4 2 | * bft to bram_in_2,bram_in_3,bram_in_4 3 | */ 4 | 5 | module write_b_in#( 6 | parameter NUM_PORT_BITS = 4, 7 | parameter PAYLOAD_BITS = 64, 8 | parameter NUM_ADDR_BITS = 7, 9 | parameter PORT_No = 2 10 | )( 11 | output reg wea, 12 | output reg [NUM_ADDR_BITS-1:0] addra, 13 | output reg [PAYLOAD_BITS:0] dina, 14 | input clk, 15 | input reset, 16 | input [NUM_PORT_BITS-1:0] port, 17 | input [NUM_ADDR_BITS-1:0] addr, 18 | input vldBit, 19 | input [PAYLOAD_BITS-1:0] payload); 20 | 21 | always@(posedge clk) begin 22 | if(reset) begin 23 | wea <= 0; 24 | addra <= 0; 25 | dina <= 0; 26 | end 27 | else begin 28 | if(port==PORT_No && vldBit) begin // need to be changed! 29 | wea <= 1; 30 | addra <= addr; 31 | dina <= {vldBit,payload}; 32 | end 33 | else begin 34 | wea <= 0; 35 | addra <= 0; // random 36 | dina <= 0; // random 37 | end 38 | end 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /common/verilog_src/write_b_out.v: -------------------------------------------------------------------------------- 1 | module write_b_out#( 2 | parameter PAYLOAD_BITS = 64 3 | )( 4 | input vld_user2b_out, 5 | input [PAYLOAD_BITS-1:0] din_leaf_user2interface, 6 | input full, 7 | 8 | output reg wr_en, 9 | output reg [PAYLOAD_BITS-1:0] din); 10 | 11 | // assign wr_en = (full) ? 0 : (vld_user2b_out) ? 1 : 0; 12 | // assign din = (full) ? 42 : (vld_user2b_out) ? din_leaf_user2interface : 42; 13 | 14 | always@(*) begin 15 | if(full) begin // can't push in to fifo 16 | wr_en = 0; 17 | din = 42; // random, because this data won't be written anyway 18 | end 19 | else begin 20 | if(vld_user2b_out) begin 21 | wr_en = 1; 22 | din = din_leaf_user2interface; 23 | end 24 | else begin 25 | wr_en = 0; 26 | din = 42; // random, because this data won't be written anyway 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /common/ydma/au50/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | Xilinx_dir 4 | xrt_dir 5 | export PLATFORM_REPO_PATHS= 6 | export kl_name=ydma 7 | export MaxJobNum=$(nproc) 8 | export PLATFORM= 9 | 10 | # Make sure everything is up to date 11 | make all 12 | -------------------------------------------------------------------------------- /common/ydma/au50/xrt.ini: -------------------------------------------------------------------------------- 1 | [Debug] 2 | opencl_summary=true 3 | opencl_device_counter=true 4 | opencl_trace=true 5 | stall_trace=all 6 | -------------------------------------------------------------------------------- /common/ydma/hw/Makefile: -------------------------------------------------------------------------------- 1 | PRJ_NAME=ydma 2 | SRC_DIR=../src 3 | 4 | all: app.exe emconfig.json $(PRJ_NAME).xclbin 5 | 6 | app.exe: $(SRC_DIR)/host.cpp 7 | g++ -Wall -g -std=c++11 $(SRC_DIR)/host.cpp -o app.exe \ 8 | -I${XILINX_XRT}/include/ \ 9 | -I${XILINX_VIVADO}/include/ \ 10 | -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ 11 | 12 | $(PRJ_NAME).xo: $(SRC_DIR)/$(PRJ_NAME).cpp 13 | v++ -c -t ${TARGET} --config $(SRC_DIR)/u50.cfg -k $(PRJ_NAME) \ 14 | -I${XILINX_VIVADO}/include/ \ 15 | -I$(SRC_DIR)/ \ 16 | $(SRC_DIR)/$(PRJ_NAME).cpp -o $(PRJ_NAME).xo 17 | 18 | $(PRJ_NAME).xclbin: ./$(PRJ_NAME).xo 19 | v++ -l -t ${TARGET} --config $(SRC_DIR)/u50.cfg ./$(PRJ_NAME).xo -o $(PRJ_NAME).xclbin 20 | 21 | emconfig.json: 22 | emconfigutil --platform xilinx_u50_gen3x16_xdma_201920_3 --nd 1 23 | 24 | clean: 25 | rm -rf $(PRJ_NAME)* app.exe *json *csv *log *summary _x xilinx* .run .Xil .ipcache *.jou 26 | 27 | # Unless specified, use the current directory name as the v++ build target 28 | TARGET ?= $(notdir $(CURDIR)) 29 | -------------------------------------------------------------------------------- /common/ydma/hw/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Exit when any command fails 4 | set -e 5 | source /opt/Xilinx/Vitis/2021.1/settings64.sh 6 | source /opt/xilinx/xrt/setup.sh 7 | export PLATFORM_REPO_PATHS=/opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3 8 | # Make sure everything is up to date 9 | make all 10 | 11 | -------------------------------------------------------------------------------- /common/ydma/hw/gen.sh: -------------------------------------------------------------------------------- 1 | 2 | xclbinutil --add-section DEBUG_IP_LAYOUT:JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/debug_ip_layout.rtd \ 3 | --add-section BITSTREAM:RAW:$1\ 4 | --force --target hw --key-value SYS:dfx_enable:true \ 5 | --add-section :JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/ydma.rtd \ 6 | --append-section :JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/appendSection.rtd \ 7 | --add-section CLOCK_FREQ_TOPOLOGY:JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/ydma_xml.rtd \ 8 | --add-section BUILD_METADATA:JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/ydma_build.rtd \ 9 | --add-section EMBEDDED_METADATA:RAW:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/ydma.xml \ 10 | --add-section SYSTEM_METADATA:RAW:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/systemDiagramModelSlrBaseAddress.json \ 11 | --key-value SYS:PlatformVBNV:xilinx_u50_gen3x16_xdma_201920_3 \ 12 | --output $2 13 | #--add-section BITSTREAM:RAW:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/partial.bit \ 14 | #--output /home/ylxiao/ws_211/rosetta_vitis/ydma/hw/ydma.xclbin 15 | -------------------------------------------------------------------------------- /common/ydma/hw/xrt.ini: -------------------------------------------------------------------------------- 1 | [Debug] 2 | profile=true 3 | timeline_trace=true 4 | data_transfer_trace=fine 5 | stall_trace=all -------------------------------------------------------------------------------- /common/ydma/hw_u250/.Xil/configutil-1989-ylxiao-OptiPlex-7050/hw/hw_emu/ext_metadata.json: -------------------------------------------------------------------------------- 1 | { 2 | "platformData":{ 3 | "plp": 4 | { 5 | "ert" : "enabled", 6 | "ertVersion" : "30", 7 | "peerToPeer" : "enabled", 8 | "dma" : "xdma", 9 | "m2m" : "enabled", 10 | "slaveBridge" : "enabled", 11 | "numCdma" : "0", 12 | "ertCmdqBaseAddr" : "0x008000000000", 13 | "ertBaseAddr" : "0x0", 14 | "cdmaBaseAddress0" : "0x0", 15 | "cdmaBaseAddress1" : "0x0", 16 | "cdmaBaseAddress2" : "0x0", 17 | "cdmaBaseAddress3" : "0x0" 18 | }, 19 | "ulp": 20 | { 21 | } 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /common/ydma/hw_u250/Makefile: -------------------------------------------------------------------------------- 1 | PRJ_NAME=ydma 2 | SRC_DIR=../src 3 | 4 | all: app.exe emconfig.json $(PRJ_NAME).xclbin 5 | 6 | app.exe: $(SRC_DIR)/host.cpp 7 | g++ -Wall -g -std=c++11 $(SRC_DIR)/host.cpp -o app.exe \ 8 | -I${XILINX_XRT}/include/ \ 9 | -I${XILINX_VIVADO}/include/ \ 10 | -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ 11 | 12 | $(PRJ_NAME).xo: $(SRC_DIR)/$(PRJ_NAME).cpp 13 | v++ -c -t ${TARGET} --config $(SRC_DIR)/u250.cfg -k $(PRJ_NAME) \ 14 | -I${XILINX_VIVADO}/include/ \ 15 | -I$(SRC_DIR)/ \ 16 | $(SRC_DIR)/$(PRJ_NAME).cpp -o $(PRJ_NAME).xo 17 | 18 | $(PRJ_NAME).xclbin: ./$(PRJ_NAME).xo 19 | v++ -l -t ${TARGET} --config $(SRC_DIR)/u250.cfg ./$(PRJ_NAME).xo -o $(PRJ_NAME).xclbin 20 | 21 | emconfig.json: 22 | emconfigutil --platform xilinx_u250_gen3x16_xdma_3_1_202020_1 --nd 1 23 | 24 | clean: 25 | rm -rf $(PRJ_NAME)* app.exe *json *csv *log *summary _x xilinx* .run .Xil .ipcache *.jou 26 | 27 | # Unless specified, use the current directory name as the v++ build target 28 | TARGET ?= $(notdir $(CURDIR)) 29 | -------------------------------------------------------------------------------- /common/ydma/hw_u250/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Exit when any command fails 4 | set -e 5 | source /opt/Xilinx/Vitis/2021.1/settings64.sh 6 | source /opt/xilinx/xrt/setup.sh 7 | export PLATFORM_REPO_PATHS=xilinx_u250_gen3x16_xdma_3_1_202020_1 8 | # Make sure everything is up to date 9 | make all 10 | 11 | -------------------------------------------------------------------------------- /common/ydma/hw_u250/xrt.ini: -------------------------------------------------------------------------------- 1 | [Debug] 2 | profile=true 3 | timeline_trace=true 4 | data_transfer_trace=fine 5 | stall_trace=all -------------------------------------------------------------------------------- /common/ydma/src/au50_dfx.cfg: -------------------------------------------------------------------------------- 1 | platform= 2 | debug=1 3 | save-temps=1 4 | 5 | [connectivity] 6 | nk=ydma:1:ydma_1 7 | sp=ydma_1.input1:HBM[0] 8 | sp=ydma_1.input2:HBM[1] 9 | sp=ydma_1.output1:HBM[0] 10 | sp=ydma_1.output2:HBM[1] 11 | 12 | [profile] 13 | data=all:all:all 14 | -------------------------------------------------------------------------------- /common/ydma/src/ultra96_dfx.cfg: -------------------------------------------------------------------------------- 1 | platform=xilinx_ultra96_base_dfx_202110_1 2 | debug=1 3 | save-temps=1 4 | 5 | [profile] 6 | data=all:all:all 7 | 8 | 9 | -------------------------------------------------------------------------------- /common/ydma/src/zcu102_dfx.cfg: -------------------------------------------------------------------------------- 1 | platform=xilinx_zcu102_base_dfx_202110_1 2 | debug=1 3 | save-temps=1 4 | 5 | [profile] 6 | data=all:all:all 7 | 8 | 9 | -------------------------------------------------------------------------------- /common/ydma/sw_emu/Makefile: -------------------------------------------------------------------------------- 1 | PRJ_NAME=ydma 2 | SRC_DIR=../src 3 | 4 | all: app.exe emconfig.json $(PRJ_NAME).xclbin 5 | 6 | app.exe: $(SRC_DIR)/host.cpp 7 | g++ -Wall -g -std=c++11 $(SRC_DIR)/host.cpp -o app.exe \ 8 | -I${XILINX_XRT}/include/ \ 9 | -I${XILINX_VIVADO}/include/ \ 10 | -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ 11 | 12 | $(PRJ_NAME).xo: $(SRC_DIR)/$(PRJ_NAME).cpp 13 | v++ -c -t ${TARGET} --config $(SRC_DIR)/u50.cfg -k $(PRJ_NAME) \ 14 | -I${XILINX_VIVADO}/include/ \ 15 | -I$(SRC_DIR)/ \ 16 | $(SRC_DIR)/$(PRJ_NAME).cpp -o $(PRJ_NAME).xo 17 | 18 | $(PRJ_NAME).xclbin: ./$(PRJ_NAME).xo 19 | v++ -l -t ${TARGET} --config $(SRC_DIR)/u50.cfg ./$(PRJ_NAME).xo -o $(PRJ_NAME).xclbin 20 | 21 | emconfig.json: 22 | emconfigutil --platform xilinx_u50_gen3x16_xdma_201920_3 --nd 1 23 | 24 | clean: 25 | rm -rf $(PRJ_NAME)* app.exe *json *csv *log *summary _x xilinx* .run .Xil .ipcache *.jou 26 | 27 | # Unless specified, use the current directory name as the v++ build target 28 | TARGET ?= $(notdir $(CURDIR)) 29 | -------------------------------------------------------------------------------- /common/ydma/sw_emu/build_and_run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | 4 | # Exit when any command fails 5 | set -e 6 | source /opt/Xilinx/Vitis/2021.1/settings64.sh 7 | source /opt/xilinx/xrt/setup.sh 8 | export PLATFORM_REPO_PATHS=/opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_201920_3 9 | kenerl_name=ydma 10 | # Make sure everything is up to date 11 | make all 12 | 13 | # Run the application in HW emulation mode 14 | XCL_EMULATION_MODE=sw_emu ./app.exe ${kenerl_name}.xclbin 15 | 16 | -------------------------------------------------------------------------------- /common/ydma/sw_emu/xrt.ini: -------------------------------------------------------------------------------- 1 | [Debug] 2 | profile=true 3 | timeline_trace=true 4 | -------------------------------------------------------------------------------- /common/ydma/ultra96/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | cd ../../ 3 | root_dir=$(pwd) 4 | cd - 5 | 6 | 7 | export PLATFORM_REPO_PATHS= 8 | export ROOTFS= 9 | export kl_name=ydma 10 | export MaxJobNum=$(nproc) 11 | export PLATFORM= 12 | #export MaxJobNum=10 13 | 14 | Xilinx_dir 15 | unset LD_LIBRARY_PATH 16 | 17 | sdk_dir 18 | 19 | # Make sure everything is up to date 20 | # make app.exe 21 | # make clean 22 | make all 23 | # make $1 24 | # make ${kl_name}.xo 25 | 26 | 27 | 28 | # Exit when any command fails 29 | #set -e 30 | #if [[ -z "$ROOTFS" ]]; then 31 | # echo "Error: make sure to set the ROOTFS environment variable" 32 | # exit 33 | #fi 34 | #if [[ -z "$SYSROOT" ]]; then 35 | # echo "Error: make sure to set the SYSROOT environment variable" 36 | # exit 37 | #fi 38 | #if [[ -z "$PLATFORM_REPO_PATHS" ]]; then 39 | # echo "Error: make sure to set the PLATFORM_REPO_PATHS environment variable" 40 | # exit 41 | #fi 42 | 43 | 44 | -------------------------------------------------------------------------------- /common/ydma/ultra96/gen.sh: -------------------------------------------------------------------------------- 1 | 2 | xclbinutil --add-section DEBUG_IP_LAYOUT:JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/debug_ip_layout.rtd \ 3 | --add-section BITSTREAM:RAW:$1\ 4 | --force --target hw --key-value SYS:dfx_enable:true \ 5 | --add-section :JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/ydma.rtd \ 6 | --append-section :JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/appendSection.rtd \ 7 | --add-section CLOCK_FREQ_TOPOLOGY:JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/ydma_xml.rtd \ 8 | --add-section BUILD_METADATA:JSON:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/ydma_build.rtd \ 9 | --add-section EMBEDDED_METADATA:RAW:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/ydma.xml \ 10 | --add-section SYSTEM_METADATA:RAW:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/systemDiagramModelSlrBaseAddress.json \ 11 | --key-value SYS:PlatformVBNV:xilinx_u50_gen3x16_xdma_201920_3 \ 12 | --output $2 13 | #--add-section BITSTREAM:RAW:/home/ylxiao/ws_211/rosetta_vitis/ydma/hw/_x/link/int/partial.bit \ 14 | #--output /home/ylxiao/ws_211/rosetta_vitis/ydma/hw/ydma.xclbin 15 | -------------------------------------------------------------------------------- /common/ydma/ultra96/run_app.sh: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # To run on the ZCU102 board, copy the packagge/sd_card directory onto the SD card, plug it into the board and power it up. 4 | # When the Linux prompt appears, run this script by entering the following command: 5 | # source /mnt/sd-mmcblk0p1/run_app.sh 6 | # 7 | 8 | mount /dev/mmcblk0p1 /mnt 9 | cd /mnt 10 | 11 | cp platform_desc.txt /etc/xocl.txt 12 | 13 | export XILINX_XRT=/usr 14 | export XILINX_VITIS=/mnt 15 | 16 | ./app.exe ydma.xclbin 17 | 18 | echo "INFO: press Ctrl+a x to exit qemu" 19 | 20 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/python/mk_abs_tcl.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import argparse 3 | import os 4 | 5 | 6 | parser = argparse.ArgumentParser() 7 | parser.add_argument('workspace') 8 | parser.add_argument('-t', '--top', type=str, default="no_func", help="set top function name for out of context synthesis") 9 | parser.add_argument('-f', '--file_name', type=str, default="no_func", help="set output file name prefix") 10 | 11 | args = parser.parse_args() 12 | workspace = args.workspace 13 | top_name = args.top 14 | file_name = args.file_name 15 | 16 | 17 | 18 | 19 | for i in range(100): 20 | file_out = open(workspace+'/_x/link/vivado/vpl/prj/prj.runs/impl_1/abs_gen'+str(i)+'.tcl', 'w') 21 | file_out.write('open_checkpoint design_route.dcp\n') 22 | file_out.write('update_design -cell pfm_top_i/dynamic_region/ydma_1/page'+str(i)+'_inst -black_box\n') 23 | file_out.write('lock_design -level routing\n') 24 | file_out.write('write_abstract_shell -force -cell pfm_top_i/dynamic_region/ydma_1/page'+str(i)+'_inst p_'+str(i)+'\n') 25 | file_out.close() 26 | 27 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/shell/run_gen_pfm_dymanic.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | workspace=$1 3 | 4 | 5 | cd ${workspace}/_x/link/vivado/vpl/prj/prj.runs/impl_1/ 6 | vivado -mode batch -source gen_pfm_dynamic.tcl 7 | cd - 8 | cp ${workspace}/_x/link/vivado/vpl/prj/prj.runs/impl_1/pfm_dynamic.dcp ./checkpoint 9 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/shell/run_python.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | python_name=$1 4 | python_arg1=$2 5 | python_arg2=$3 6 | python_arg3=$4 7 | 8 | 9 | python ${python_name} ${python_arg1} -t ${python_arg2} -f ${python_arg3} 10 | 11 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/shell/run_tcl.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | tcl_name=$1 4 | tcl_argv=$2 5 | 6 | vivado -mode batch -source ${tcl_name} -tclargs $2 7 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/src4level2/page/page.v: -------------------------------------------------------------------------------- 1 | module page( 2 | input wire clk, 3 | input wire [48 : 0] din_leaf_bft2interface, 4 | output reg [48 : 0] dout_leaf_interface2bft, 5 | input wire resend, 6 | input wire reset 7 | ); 8 | 9 | always@(posedge clk)begin 10 | if(reset) begin 11 | dout_leaf_interface2bft <= 0; 12 | end else if(resend) begin 13 | dout_leaf_interface2bft <= din_leaf_bft2interface; 14 | end else begin 15 | dout_leaf_interface2bft <= dout_leaf_interface2bft; 16 | end 17 | end 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/src4level2/page_bk/page.v: -------------------------------------------------------------------------------- 1 | module page( 2 | input wire clk, 3 | input wire [48 : 0] din_leaf_bft2interface, 4 | output reg [48 : 0] dout_leaf_interface2bft, 5 | input wire resend, 6 | input wire reset 7 | ); 8 | 9 | always@(posedge clk)begin 10 | if(reset) begin 11 | dout_leaf_interface2bft <= 0; 12 | end else if(resend) begin 13 | dout_leaf_interface2bft <= din_leaf_bft2interface; 14 | end else begin 15 | dout_leaf_interface2bft <= dout_leaf_interface2bft; 16 | end 17 | end 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/src4level2/page_bk/write_b_out.v: -------------------------------------------------------------------------------- 1 | module write_b_out#( 2 | parameter PAYLOAD_BITS = 64 3 | )( 4 | input vld_user2b_out, 5 | input [PAYLOAD_BITS-1:0] din_leaf_user2interface, 6 | input full, 7 | 8 | output reg wr_en, 9 | output reg [PAYLOAD_BITS-1:0] din); 10 | 11 | // assign wr_en = (full) ? 0 : (vld_user2b_out) ? 1 : 0; 12 | // assign din = (full) ? 42 : (vld_user2b_out) ? din_leaf_user2interface : 42; 13 | 14 | always@(*) begin 15 | if(full) begin // can't push in to fifo 16 | wr_en = 0; 17 | din = 42; // random, because this data won't be written anyway 18 | end 19 | else begin 20 | if(vld_user2b_out) begin 21 | wr_en = 1; 22 | din = din_leaf_user2interface; 23 | end 24 | else begin 25 | wr_en = 0; 26 | din = 42; // random, because this data won't be written anyway 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/src4level2/ydma_bb/config_parser_v1_buffer_V.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2021.1 (64-bit) 3 | // Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. 4 | // ============================================================== 5 | `timescale 1 ns / 1 ps 6 | module config_parser_v1_buffer_V (address0, ce0, d0, we0, q0, reset,clk); 7 | 8 | parameter DataWidth = 64; 9 | parameter AddressWidth = 8; 10 | parameter AddressRange = 256; 11 | 12 | input[AddressWidth-1:0] address0; 13 | input ce0; 14 | input[DataWidth-1:0] d0; 15 | input we0; 16 | output reg[DataWidth-1:0] q0; 17 | input reset; 18 | input clk; 19 | 20 | reg [DataWidth-1:0] ram[0:AddressRange-1]; 21 | 22 | 23 | 24 | 25 | always @(posedge clk) 26 | begin 27 | if (ce0) begin 28 | if (we0) 29 | ram[address0] <= d0; 30 | q0 <= ram[address0]; 31 | end 32 | end 33 | 34 | 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/src4level2/ydma_bb/leaf_bb.v: -------------------------------------------------------------------------------- 1 | module page_bb( 2 | input wire clk, 3 | input wire [48 : 0] din_leaf_bft2interface, 4 | output wire [48 : 0] dout_leaf_interface2bft, 5 | input wire resend, 6 | input wire reset 7 | ); 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/src4level2/ydma_bb/write_b_out.v: -------------------------------------------------------------------------------- 1 | module write_b_out#( 2 | parameter PAYLOAD_BITS = 64 3 | )( 4 | input vld_user2b_out, 5 | input [PAYLOAD_BITS-1:0] din_leaf_user2interface, 6 | input full, 7 | 8 | output reg wr_en, 9 | output reg [PAYLOAD_BITS-1:0] din); 10 | 11 | // assign wr_en = (full) ? 0 : (vld_user2b_out) ? 1 : 0; 12 | // assign din = (full) ? 42 : (vld_user2b_out) ? din_leaf_user2interface : 42; 13 | 14 | always@(*) begin 15 | if(full) begin // can't push in to fifo 16 | wr_en = 0; 17 | din = 42; // random, because this data won't be written anyway 18 | end 19 | else begin 20 | if(vld_user2b_out) begin 21 | wr_en = 1; 22 | din = din_leaf_user2interface; 23 | end 24 | else begin 25 | wr_en = 0; 26 | din = 42; // random, because this data won't be written anyway 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/tcl/empty_pfm_dynamic.tcl: -------------------------------------------------------------------------------- 1 | set cell_name ydma 2 | open_checkpoint ./checkpoint/pfm_dynamic.dcp 3 | update_design -black_box -cells ${cell_name}_1 4 | write_checkpoint -force ./checkpoint/pfm_dynamic_bb.dcp 5 | 6 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/tcl/out_of_context_syn_page.tcl: -------------------------------------------------------------------------------- 1 | set top_name page 2 | 3 | set dir "./src4level2/page" 4 | set contents [glob -nocomplain -directory $dir *] 5 | foreach item $contents { 6 | if { [regexp {.*\.tcl} $item] } { 7 | source $item 8 | } else { 9 | add_files -norecurse $item 10 | } 11 | } 12 | 13 | set_param general.maxThreads 8 14 | set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY XPM_FIFO} [current_project] 15 | set logFileId [open ./runOOC.log "w"] 16 | set start_time [clock seconds] 17 | set_param general.maxThreads 8 18 | synth_design -top $top_name -part xczu3eg-sbva484-1-i -mode out_of_context 19 | write_checkpoint -force ./checkpoint/$top_name.dcp 20 | set end_time [clock seconds] 21 | set total_seconds [expr $end_time - $start_time] 22 | puts $logFileId "syn: $total_seconds seconds" 23 | report_utilization -hierarchical > utilization.rpt 24 | 25 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/tcl/out_of_context_syn_ydma_bb.tcl: -------------------------------------------------------------------------------- 1 | set top_name ydma_bb 2 | 3 | set dir "./src4level2/ydma_bb" 4 | set contents [glob -nocomplain -directory $dir *] 5 | foreach item $contents { 6 | if { [regexp {.*\.tcl} $item] } { 7 | source $item 8 | } else { 9 | add_files -norecurse $item 10 | } 11 | } 12 | 13 | set_param general.maxThreads 8 14 | set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY XPM_FIFO} [current_project] 15 | set logFileId [open ./runOOC.log "w"] 16 | set start_time [clock seconds] 17 | set_param general.maxThreads 8 18 | synth_design -top $top_name -part xczu3eg-sbva484-1-i -mode out_of_context 19 | write_checkpoint -force ./checkpoint/$top_name.dcp 20 | set end_time [clock seconds] 21 | set total_seconds [expr $end_time - $start_time] 22 | puts $logFileId "syn: $total_seconds seconds" 23 | report_utilization -hierarchical > utilization.rpt 24 | 25 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/tcl/replace_sub_module_level1.tcl: -------------------------------------------------------------------------------- 1 | set kl_name ydma_bb 2 | 3 | add_files ./checkpoint/pfm_dynamic_bb.dcp 4 | add_files ./checkpoint/${kl_name}.dcp 5 | set_property SCOPED_TO_CELLS { ydma_1 } [get_files ./checkpoint/${kl_name}.dcp] 6 | link_design -mode default -part xczu3eg-sbva484-1-i -top pfm_dynamic 7 | write_checkpoint -force ./checkpoint/pfm_dynamic_new_bb.dcp 8 | 9 | 10 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/tcl/sub_divided.tcl: -------------------------------------------------------------------------------- 1 | 2 | open_checkpoint ./checkpoint/hw_bb_locked.dcp 3 | pr_subdivide -cell pfm_top_i/dynamic_region -subcells {pfm_top_i/dynamic_region/ydma_1/page2_inst pfm_top_i/dynamic_region/ydma_1/page3_inst } ./checkpoint/pfm_dynamic_new_bb.dcp 4 | write_checkpoint -force ./checkpoint/hw_bb_divided.dcp 5 | 6 | -------------------------------------------------------------------------------- /common/ydma/ultra96/ultra96_dfx_manual/xdc/sub.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_pblock p_2 3 | resize_pblock [get_pblocks p_2] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} 4 | 5 | 6 | create_pblock p_3 7 | resize_pblock [get_pblocks p_3] -add {SLICE_X14Y120:SLICE_X47Y179} 8 | resize_pblock [get_pblocks p_3] -add {DSP48E2_X1Y48:DSP48E2_X4Y71} 9 | resize_pblock [get_pblocks p_3] -add {RAMB18_X2Y48:RAMB18_X5Y71} 10 | resize_pblock [get_pblocks p_3] -add {RAMB36_X2Y24:RAMB36_X5Y35} 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | set_property IS_SOFT TRUE [get_pblocks p_2] 41 | set_property IS_SOFT TRUE [get_pblocks p_3] 42 | 43 | set_property SNAPPING_MODE ON [get_pblocks p_2] 44 | set_property SNAPPING_MODE ON [get_pblocks p_3] 45 | 46 | add_cells_to_pblock [get_pblocks p_2] [get_cells -quiet [list pfm_top_i/dynamic_region/ydma_1/page2_inst]] 47 | add_cells_to_pblock [get_pblocks p_3] [get_cells -quiet [list pfm_top_i/dynamic_region/ydma_1/page3_inst]] 48 | 49 | 50 | -------------------------------------------------------------------------------- /common/ydma/zcu102/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | cd ../../ 3 | root_dir=$(pwd) 4 | cd - 5 | 6 | 7 | export PLATFORM_REPO_PATHS= 8 | export ROOTFS= 9 | export kl_name=ydma 10 | export MaxJobNum=$(nproc) 11 | export PLATFORM= 12 | #export MaxJobNum=10 13 | 14 | Xilinx_dir 15 | xrt_dir 16 | unset LD_LIBRARY_PATH 17 | 18 | sdk_dir 19 | 20 | # Make sure everything is up to date 21 | # make app.exe 22 | # make clean 23 | make all 24 | # make $1 25 | # make ${kl_name}.xo 26 | 27 | 28 | 29 | # Exit when any command fails 30 | #set -e 31 | #if [[ -z "$ROOTFS" ]]; then 32 | # echo "Error: make sure to set the ROOTFS environment variable" 33 | # exit 34 | #fi 35 | #if [[ -z "$SYSROOT" ]]; then 36 | # echo "Error: make sure to set the SYSROOT environment variable" 37 | # exit 38 | #fi 39 | #if [[ -z "$PLATFORM_REPO_PATHS" ]]; then 40 | # echo "Error: make sure to set the PLATFORM_REPO_PATHS environment variable" 41 | # exit 42 | #fi 43 | 44 | 45 | -------------------------------------------------------------------------------- /common/ydma/zcu102/run_app.sh: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # To run on the ZCU102 board, copy the packagge/sd_card directory onto the SD card, plug it into the board and power it up. 4 | # When the Linux prompt appears, run this script by entering the following command: 5 | # source /mnt/sd-mmcblk0p1/run_app.sh 6 | # 7 | 8 | mount /dev/mmcblk0p1 /mnt 9 | cd /mnt 10 | 11 | cp platform_desc.txt /etc/xocl.txt 12 | 13 | export XILINX_XRT=/usr 14 | export XILINX_VITIS=/mnt 15 | 16 | ./app.exe ydma.xclbin 17 | 18 | echo "INFO: press Ctrl+a x to exit qemu" 19 | 20 | -------------------------------------------------------------------------------- /common/ydma/zcu102/xrt.ini: -------------------------------------------------------------------------------- 1 | [Debug] 2 | opencl_summary=true 3 | opencl_device_counter=true 4 | opencl_trace=true 5 | stall_trace=all 6 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/cpp/run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | g++ -std=c++11 ./src/host.cpp ./src/hipr.cpp -o host 4 | 5 | start=$(date +%s.%N) 6 | 7 | ./host $1 8 | 9 | dur=$(echo "$(date +%s.%N) - $start" | bc) 10 | printf "run: %.3f seconds" $dur > runtime_${1}.log 11 | printf "" 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/cpp/src/app/connect.txt: -------------------------------------------------------------------------------- 1 | data_transfer data_redir_m 2 | DMA data_transfer 3 | data_redir_m rasterization2_m 4 | zculling_top coloringFB_top_m 5 | data_redir_m rasterization2_m 6 | rasterization2_m zculling_top 7 | coloringFB_top_m DMA 8 | rasterization2_m zculling_top 9 | coloringFB_bot_m coloringFB_top_m 10 | zculling_bot coloringFB_bot_m 11 | rasterization2_m zculling_bot 12 | rasterization2_m zculling_bot 13 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/cpp/src/arch/zcu102_invalid.txt: -------------------------------------------------------------------------------- 1 | OFFSET_CLB_BRAM36_BRAM18_DSP2 5 1 2 2 2 | INVALID_TILE 0 36 0 2 3 | INVALID_TILE 56 57 1 1 -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/cpp/src/host.cpp: -------------------------------------------------------------------------------- 1 | #include "typedefs.hpp" 2 | #include "hipr.hpp" 3 | 4 | 5 | int main(int argc, char **argv){ 6 | 7 | // Define the input data path; 8 | string path_prefix, device, inst_name; 9 | if(argc>1){\ 10 | path_prefix = argv[1]; 11 | device = argv[2]; 12 | } 13 | else{ 14 | path_prefix = "./src/app"; 15 | device = "zcu102"; 16 | inst_name = "pfm_top_i/dynamic_region"; 17 | } 18 | 19 | // Instantiate a pr class; 20 | hipr pr_inst(path_prefix, device, inst_name); 21 | 22 | pr_inst.SimulatedAnnealing(); 23 | 24 | // pr_inst.print_invalid(); 25 | // pr_inst.print_connect(); 26 | // pr_inst.print_pragma(); 27 | // pr_inst.print_tile(); 28 | pr_inst.print_dfx(); 29 | // pr_inst.print_utilization(); 30 | pr_inst.gen_xdc(); 31 | 32 | 33 | 34 | cout << "Done!" << endl; 35 | return SUCCESS; 36 | } 37 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/python/mk_abs_tcl.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import argparse 3 | import os 4 | 5 | 6 | parser = argparse.ArgumentParser() 7 | parser.add_argument('workspace') 8 | parser.add_argument('-t', '--top', type=str, default="no_func", help="set top function name for out of context synthesis") 9 | parser.add_argument('-f', '--file_name', type=str, default="no_func", help="set output file name prefix") 10 | 11 | args = parser.parse_args() 12 | workspace = args.workspace 13 | top_name = args.top 14 | file_name = args.file_name 15 | 16 | 17 | 18 | 19 | for i in range(100): 20 | file_out = open(workspace+'/_x/link/vivado/vpl/prj/prj.runs/impl_1/abs_gen'+str(i)+'.tcl', 'w') 21 | file_out.write('open_checkpoint design_route.dcp\n') 22 | file_out.write('update_design -cell level0_i/ulp/ydma_1/page'+str(i)+'_inst -black_box\n') 23 | file_out.write('lock_design -level routing\n') 24 | file_out.write('write_abstract_shell -force -cell level0_i/ulp/ydma_1/page'+str(i)+'_inst p_'+str(i)+'\n') 25 | file_out.close() 26 | 27 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/shell/run_gen_pfm_dymanic.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | workspace=$1 3 | 4 | 5 | cd ${workspace}/_x/link/vivado/vpl/prj/prj.runs/impl_1/ 6 | vivado -mode batch -source gen_pfm_dynamic.tcl 7 | cd - 8 | cp ${workspace}/_x/link/vivado/vpl/prj/prj.runs/impl_1/pfm_dynamic.dcp ./checkpoint 9 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/shell/run_python.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | python_name=$1 4 | python_arg1=$2 5 | python_arg2=$3 6 | python_arg3=$4 7 | 8 | 9 | python ${python_name} ${python_arg1} -t ${python_arg2} -f ${python_arg3} 10 | 11 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/shell/run_tcl.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | tcl_name=$1 4 | tcl_argv=$2 5 | 6 | vivado -mode batch -source ${tcl_name} -tclargs $2 7 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/src4level2/page/page.v: -------------------------------------------------------------------------------- 1 | module page( 2 | input wire clk, 3 | input wire [48 : 0] din_leaf_bft2interface, 4 | output reg [48 : 0] dout_leaf_interface2bft, 5 | input wire resend, 6 | input wire reset 7 | ); 8 | 9 | always@(posedge clk)begin 10 | if(reset) begin 11 | dout_leaf_interface2bft <= 0; 12 | end else if(resend) begin 13 | dout_leaf_interface2bft <= din_leaf_bft2interface; 14 | end else begin 15 | dout_leaf_interface2bft <= dout_leaf_interface2bft; 16 | end 17 | end 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/tcl/empty_pfm_dynamic.tcl: -------------------------------------------------------------------------------- 1 | set cell_name ydma 2 | open_checkpoint ./checkpoint/pfm_dynamic.dcp 3 | update_design -black_box -cells ${cell_name}_1 4 | write_checkpoint -force ./checkpoint/pfm_dynamic_bb.dcp 5 | 6 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/tcl/out_of_context_syn_page.tcl: -------------------------------------------------------------------------------- 1 | set top_name page 2 | 3 | set dir "./src4level2/page" 4 | set contents [glob -nocomplain -directory $dir *] 5 | foreach item $contents { 6 | if { [regexp {.*\.tcl} $item] } { 7 | source $item 8 | } else { 9 | add_files -norecurse $item 10 | } 11 | } 12 | 13 | set_param general.maxThreads 8 14 | set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY XPM_FIFO} [current_project] 15 | set logFileId [open ./runOOC.log "w"] 16 | set start_time [clock seconds] 17 | set_param general.maxThreads 8 18 | synth_design -top $top_name -part xcu50-fsvh2104-2-e -mode out_of_context 19 | write_checkpoint -force ./checkpoint/$top_name.dcp 20 | set end_time [clock seconds] 21 | set total_seconds [expr $end_time - $start_time] 22 | puts $logFileId "syn: $total_seconds seconds" 23 | report_utilization -hierarchical > utilization.rpt 24 | 25 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/tcl/out_of_context_syn_ydma_bb.tcl: -------------------------------------------------------------------------------- 1 | set top_name ydma_bb 2 | 3 | set dir "./src4level2/ydma_bb" 4 | set contents [glob -nocomplain -directory $dir *] 5 | foreach item $contents { 6 | if { [regexp {.*\.tcl} $item] } { 7 | source $item 8 | } else { 9 | add_files -norecurse $item 10 | } 11 | } 12 | 13 | set_param general.maxThreads 8 14 | set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY XPM_FIFO} [current_project] 15 | set logFileId [open ./runOOC.log "w"] 16 | set start_time [clock seconds] 17 | set_param general.maxThreads 8 18 | synth_design -top $top_name -part xcu50-fsvh2104-2-e -mode out_of_context 19 | write_checkpoint -force ./checkpoint/$top_name.dcp 20 | set end_time [clock seconds] 21 | set total_seconds [expr $end_time - $start_time] 22 | puts $logFileId "syn: $total_seconds seconds" 23 | report_utilization -hierarchical > utilization.rpt 24 | 25 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/tcl/replace_sub_module_level1.tcl: -------------------------------------------------------------------------------- 1 | set kl_name ydma_bb 2 | 3 | add_files ./checkpoint/pfm_dynamic_bb.dcp 4 | add_files ./checkpoint/${kl_name}.dcp 5 | set_property SCOPED_TO_CELLS { ydma_1 } [get_files ./checkpoint/${kl_name}.dcp] 6 | link_design -mode default -part xczu9eg-ffvb1156-2-e -top pfm_dynamic 7 | write_checkpoint -force ./checkpoint/pfm_dynamic_new_bb.dcp 8 | 9 | 10 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_hipr/tcl/sub_divided.tcl: -------------------------------------------------------------------------------- 1 | 2 | open_checkpoint ./checkpoint/hw_bb_locked.dcp 3 | pr_subdivide -cell level0_i/ulp -subcells {level0_i/ulp/ydma_1/page2_inst level0_i/ulp/ydma_1/page3_inst level0_i/ulp/ydma_1/page4_inst level0_i/ulp/ydma_1/page5_inst level0_i/ulp/ydma_1/page6_inst level0_i/ulp/ydma_1/page7_inst level0_i/ulp/ydma_1/page8_inst level0_i/ulp/ydma_1/page9_inst level0_i/ulp/ydma_1/page10_inst level0_i/ulp/ydma_1/page11_inst level0_i/ulp/ydma_1/page12_inst level0_i/ulp/ydma_1/page13_inst level0_i/ulp/ydma_1/page14_inst level0_i/ulp/ydma_1/page15_inst level0_i/ulp/ydma_1/page16_inst level0_i/ulp/ydma_1/page17_inst level0_i/ulp/ydma_1/page18_inst level0_i/ulp/ydma_1/page19_inst level0_i/ulp/ydma_1/page20_inst level0_i/ulp/ydma_1/page21_inst level0_i/ulp/ydma_1/page22_inst level0_i/ulp/ydma_1/page23_inst } ./checkpoint/pfm_dynamic_new_bb.dcp 4 | write_checkpoint -force ./checkpoint/hw_bb_divided.dcp 5 | 6 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/python/mk_abs_tcl.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import argparse 3 | import os 4 | 5 | 6 | parser = argparse.ArgumentParser() 7 | parser.add_argument('workspace') 8 | parser.add_argument('-t', '--top', type=str, default="no_func", help="set top function name for out of context synthesis") 9 | parser.add_argument('-f', '--file_name', type=str, default="no_func", help="set output file name prefix") 10 | 11 | args = parser.parse_args() 12 | workspace = args.workspace 13 | top_name = args.top 14 | file_name = args.file_name 15 | 16 | 17 | 18 | 19 | for i in range(100): 20 | file_out = open(workspace+'/_x/link/vivado/vpl/prj/prj.runs/impl_1/abs_gen'+str(i)+'.tcl', 'w') 21 | file_out.write('open_checkpoint design_route.dcp\n') 22 | file_out.write('update_design -cell pfm_top_i/dynamic_region/ydma_1/page'+str(i)+'_inst -black_box\n') 23 | file_out.write('lock_design -level routing\n') 24 | file_out.write('write_abstract_shell -force -cell pfm_top_i/dynamic_region/ydma_1/page'+str(i)+'_inst p_'+str(i)+'\n') 25 | file_out.close() 26 | 27 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/shell/run_gen_pfm_dymanic.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | workspace=$1 3 | 4 | 5 | cd ${workspace}/_x/link/vivado/vpl/prj/prj.runs/impl_1/ 6 | vivado -mode batch -source gen_pfm_dynamic.tcl 7 | cd - 8 | cp ${workspace}/_x/link/vivado/vpl/prj/prj.runs/impl_1/pfm_dynamic.dcp ./checkpoint 9 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/shell/run_python.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | python_name=$1 4 | python_arg1=$2 5 | python_arg2=$3 6 | python_arg3=$4 7 | 8 | 9 | python ${python_name} ${python_arg1} -t ${python_arg2} -f ${python_arg3} 10 | 11 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/shell/run_tcl.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -e 2 | 3 | tcl_name=$1 4 | tcl_argv=$2 5 | 6 | vivado -mode batch -source ${tcl_name} -tclargs $2 7 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/src4level2/page/page.v: -------------------------------------------------------------------------------- 1 | module page( 2 | input wire clk, 3 | input wire [48 : 0] din_leaf_bft2interface, 4 | output reg [48 : 0] dout_leaf_interface2bft, 5 | input wire resend, 6 | input wire reset 7 | ); 8 | 9 | always@(posedge clk)begin 10 | if(reset) begin 11 | dout_leaf_interface2bft <= 0; 12 | end else if(resend) begin 13 | dout_leaf_interface2bft <= din_leaf_bft2interface; 14 | end else begin 15 | dout_leaf_interface2bft <= dout_leaf_interface2bft; 16 | end 17 | end 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/src4level2/ydma_bb/page_bb.v: -------------------------------------------------------------------------------- 1 | module page_bb( 2 | input wire clk, 3 | input wire [48 : 0] din_leaf_bft2interface, 4 | output wire [48 : 0] dout_leaf_interface2bft, 5 | input wire resend, 6 | input wire reset 7 | ); 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/src4level2/ydma_bb/write_b_out.v: -------------------------------------------------------------------------------- 1 | module write_b_out#( 2 | parameter PAYLOAD_BITS = 64 3 | )( 4 | input vld_user2b_out, 5 | input [PAYLOAD_BITS-1:0] din_leaf_user2interface, 6 | input full, 7 | 8 | output reg wr_en, 9 | output reg [PAYLOAD_BITS-1:0] din); 10 | 11 | // assign wr_en = (full) ? 0 : (vld_user2b_out) ? 1 : 0; 12 | // assign din = (full) ? 42 : (vld_user2b_out) ? din_leaf_user2interface : 42; 13 | 14 | always@(*) begin 15 | if(full) begin // can't push in to fifo 16 | wr_en = 0; 17 | din = 42; // random, because this data won't be written anyway 18 | end 19 | else begin 20 | if(vld_user2b_out) begin 21 | wr_en = 1; 22 | din = din_leaf_user2interface; 23 | end 24 | else begin 25 | wr_en = 0; 26 | din = 42; // random, because this data won't be written anyway 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/tcl/empty_pfm_dynamic.tcl: -------------------------------------------------------------------------------- 1 | set cell_name ydma 2 | open_checkpoint ./checkpoint/pfm_dynamic.dcp 3 | update_design -black_box -cells ${cell_name}_1 4 | write_checkpoint -force ./checkpoint/pfm_dynamic_bb.dcp 5 | 6 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/tcl/out_of_context_syn_page.tcl: -------------------------------------------------------------------------------- 1 | set top_name page 2 | 3 | set dir "./src4level2/page" 4 | set contents [glob -nocomplain -directory $dir *] 5 | foreach item $contents { 6 | if { [regexp {.*\.tcl} $item] } { 7 | source $item 8 | } else { 9 | add_files -norecurse $item 10 | } 11 | } 12 | 13 | set_param general.maxThreads 8 14 | set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY XPM_FIFO} [current_project] 15 | set logFileId [open ./runOOC.log "w"] 16 | set start_time [clock seconds] 17 | set_param general.maxThreads 8 18 | synth_design -top $top_name -part xczu9eg-ffvb1156-2-e -mode out_of_context 19 | write_checkpoint -force ./checkpoint/$top_name.dcp 20 | set end_time [clock seconds] 21 | set total_seconds [expr $end_time - $start_time] 22 | puts $logFileId "syn: $total_seconds seconds" 23 | report_utilization -hierarchical > utilization.rpt 24 | 25 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/tcl/out_of_context_syn_ydma_bb.tcl: -------------------------------------------------------------------------------- 1 | set top_name ydma_bb 2 | 3 | set dir "./src4level2/ydma_bb" 4 | set contents [glob -nocomplain -directory $dir *] 5 | foreach item $contents { 6 | if { [regexp {.*\.tcl} $item] } { 7 | source $item 8 | } else { 9 | add_files -norecurse $item 10 | } 11 | } 12 | 13 | set_param general.maxThreads 8 14 | set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY XPM_FIFO} [current_project] 15 | set logFileId [open ./runOOC.log "w"] 16 | set start_time [clock seconds] 17 | set_param general.maxThreads 8 18 | synth_design -top $top_name -part xczu9eg-ffvb1156-2-e -mode out_of_context 19 | write_checkpoint -force ./checkpoint/$top_name.dcp 20 | set end_time [clock seconds] 21 | set total_seconds [expr $end_time - $start_time] 22 | puts $logFileId "syn: $total_seconds seconds" 23 | report_utilization -hierarchical > utilization.rpt 24 | 25 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/tcl/replace_sub_module_level1.tcl: -------------------------------------------------------------------------------- 1 | set kl_name ydma_bb 2 | 3 | add_files ./checkpoint/pfm_dynamic_bb.dcp 4 | add_files ./checkpoint/${kl_name}.dcp 5 | set_property SCOPED_TO_CELLS { ydma_1 } [get_files ./checkpoint/${kl_name}.dcp] 6 | link_design -mode default -part xczu9eg-ffvb1156-2-e -top pfm_dynamic 7 | write_checkpoint -force ./checkpoint/pfm_dynamic_new_bb.dcp 8 | 9 | 10 | -------------------------------------------------------------------------------- /common/ydma/zcu102/zcu102_dfx_manual/tcl/sub_divided.tcl: -------------------------------------------------------------------------------- 1 | 2 | open_checkpoint ./checkpoint/hw_bb_locked.dcp 3 | pr_subdivide -cell pfm_top_i/dynamic_region -subcells {pfm_top_i/dynamic_region/ydma_1/page2_inst pfm_top_i/dynamic_region/ydma_1/page3_inst pfm_top_i/dynamic_region/ydma_1/page4_inst pfm_top_i/dynamic_region/ydma_1/page5_inst pfm_top_i/dynamic_region/ydma_1/page6_inst pfm_top_i/dynamic_region/ydma_1/page7_inst pfm_top_i/dynamic_region/ydma_1/page8_inst pfm_top_i/dynamic_region/ydma_1/page9_inst pfm_top_i/dynamic_region/ydma_1/page10_inst pfm_top_i/dynamic_region/ydma_1/page11_inst pfm_top_i/dynamic_region/ydma_1/page12_inst pfm_top_i/dynamic_region/ydma_1/page13_inst pfm_top_i/dynamic_region/ydma_1/page14_inst pfm_top_i/dynamic_region/ydma_1/page15_inst pfm_top_i/dynamic_region/ydma_1/page16_inst pfm_top_i/dynamic_region/ydma_1/page17_inst} ./checkpoint/pfm_dynamic_new_bb.dcp 4 | write_checkpoint -force ./checkpoint/hw_bb_divided.dcp 5 | 6 | -------------------------------------------------------------------------------- /images/bunny.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/images/bunny.png -------------------------------------------------------------------------------- /images/csimu.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/images/csimu.png -------------------------------------------------------------------------------- /images/error.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/images/error.png -------------------------------------------------------------------------------- /images/report_all.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/images/report_all.png -------------------------------------------------------------------------------- /images/report_one.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/images/report_one.png -------------------------------------------------------------------------------- /images/runtime_all.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/images/runtime_all.png -------------------------------------------------------------------------------- /images/runtime_one.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/images/runtime_one.png -------------------------------------------------------------------------------- /input_src/datamover/cfg/u50.cfg: -------------------------------------------------------------------------------- 1 | platform=xilinx_u50_gen3x16_xdma_201920_3 2 | debug=1 3 | save-temps=1 4 | 5 | [connectivity] 6 | nk=ydma:1:ydma_1 7 | sp=ydma_1.input1:HBM[0] 8 | sp=ydma_1.input2:HBM[1] 9 | sp=ydma_1.output1:HBM[0] 10 | sp=ydma_1.output2:HBM[1] 11 | 12 | [profile] 13 | data=all:all:all 14 | -------------------------------------------------------------------------------- /input_src/datamover/cfg/zcu102.cfg: -------------------------------------------------------------------------------- 1 | platform=zcu102_custom 2 | debug=1 3 | save-temps=1 4 | 5 | [profile] 6 | data=all:all:all 7 | 8 | 9 | -------------------------------------------------------------------------------- /input_src/datamover/cfg/zcu102_dfx.cfg: -------------------------------------------------------------------------------- 1 | platform=xilinx_zcu102_base_dfx_202020_1 2 | debug=1 3 | save-temps=1 4 | 5 | [profile] 6 | data=all:all:all 7 | 8 | 9 | -------------------------------------------------------------------------------- /input_src/datamover/data_proc2.cpp: -------------------------------------------------------------------------------- 1 | #include "../host/typedefs.h" 2 | 3 | void data_proc2 ( 4 | hls::stream > & Input_1, 5 | hls::stream > & Output_1 6 | ) 7 | { 8 | #pragma HLS INTERFACE axis register both port=Input_1 9 | #pragma HLS INTERFACE axis register both port=Output_1 10 | 11 | ap_uint<512> tmp; 12 | 13 | for(int i=0; i > & Input_1, 4 | hls::stream > & Output_1); 5 | #pragma map_target = HIPR 6 | #pragma clb =8 ff = 1 bram =10 dsp =1.2 7 | -------------------------------------------------------------------------------- /input_src/datamover/host/top.h: -------------------------------------------------------------------------------- 1 | /*===============================================================*/ 2 | /* */ 3 | /* rendering.h */ 4 | /* */ 5 | /* C++ kernel for 3D Rendering */ 6 | /* */ 7 | /*===============================================================*/ 8 | 9 | #ifndef __RENDERING_H__ 10 | #define __RENDERING_H__ 11 | 12 | #include "../host/typedefs.h" 13 | 14 | //#pragma SDS data access_pattern(input:SEQUENTIAL, output:SEQUENTIAL) 15 | 16 | void top ( 17 | hls::stream > & Input_1, 18 | hls::stream > & Output_1 19 | ); 20 | 21 | 22 | #endif 23 | 24 | -------------------------------------------------------------------------------- /input_src/datamover/host/typedefs.h: -------------------------------------------------------------------------------- 1 | /*===============================================================*/ 2 | /* */ 3 | /* typedefs.h */ 4 | /* */ 5 | /* Typedefs for the host */ 6 | /* */ 7 | /*===============================================================*/ 8 | 9 | #ifndef __TYPEDEFS_H__ 10 | #define __TYPEDEFS_H__ 11 | 12 | 13 | 14 | // hls header 15 | #include "ap_int.h" 16 | #include "hls_stream.h" 17 | // specialized datatypes 18 | typedef ap_uint<1> bit1; 19 | typedef ap_uint<2> bit2; 20 | typedef ap_uint<8> bit8; 21 | typedef ap_uint<16> bit16; 22 | typedef ap_uint<32> bit32; 23 | typedef ap_uint<64> bit64; 24 | typedef ap_uint<512> bit512; 25 | 26 | #define MAX_X 1024 27 | #endif 28 | -------------------------------------------------------------------------------- /input_src/datamover/operators/data_proc1.cpp: -------------------------------------------------------------------------------- 1 | #include "../host/typedefs.h" 2 | 3 | 4 | 5 | void data_proc1 ( 6 | hls::stream > & Input_1, 7 | hls::stream > & Output_1 8 | ) 9 | { 10 | #pragma HLS INTERFACE axis register both port=Input_1 11 | #pragma HLS INTERFACE axis register both port=Output_1 12 | 13 | ap_uint<512> tmp; 14 | 15 | for(int i=0; i > & Input_1, 5 | hls::stream > & Output_1); 6 | #pragma map_target = HIPR 7 | #pragma clb =8 ff = 1 bram =10 dsp =1.2 8 | -------------------------------------------------------------------------------- /input_src/datamover/operators/data_proc2.cpp: -------------------------------------------------------------------------------- 1 | #include "../host/typedefs.h" 2 | 3 | void data_proc2 ( 4 | hls::stream > & Input_1, 5 | hls::stream > & Output_1 6 | ) 7 | { 8 | #pragma HLS INTERFACE axis register both port=Input_1 9 | #pragma HLS INTERFACE axis register both port=Output_1 10 | 11 | ap_uint<512> tmp; 12 | 13 | for(int i=0; i > & Input_1, 4 | hls::stream > & Output_1); 5 | #pragma map_target = HIPR 6 | #pragma clb =8 ff = 1 bram =10 dsp =1.2 7 | -------------------------------------------------------------------------------- /input_src/datamover/sw_emu/Makefile: -------------------------------------------------------------------------------- 1 | PRJ_NAME=ydma 2 | SRC_DIR=.. 3 | operators_dir=./input_src/$(prj_name)/operators 4 | operators_src=$(wildcard $(SRC_DIR)/operators/*.cpp) 5 | 6 | all: app.exe emconfig.json $(PRJ_NAME).xclbin 7 | 8 | app.exe: $(SRC_DIR)/host/host.cpp 9 | g++ -Wall -g -std=c++11 $^ -o app.exe \ 10 | -I${XILINX_XRT}/include/ \ 11 | -I${XILINX_VIVADO}/include/ \ 12 | -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ 13 | 14 | $(PRJ_NAME).xo: $(SRC_DIR)/host/top.cpp $(SRC_DIR)/host/typedefs.h $(operators_src) 15 | v++ -c -t ${TARGET} --config $(SRC_DIR)/cfg/u50.cfg -k $(PRJ_NAME) \ 16 | -I${XILINX_VIVADO}/include/ \ 17 | -I$(SRC_DIR)/ \ 18 | -I$(SRC_DIR)/host \ 19 | $^ -o $(PRJ_NAME).xo 20 | 21 | $(PRJ_NAME).xclbin: ./$(PRJ_NAME).xo 22 | v++ -l -t ${TARGET} --config $(SRC_DIR)/cfg/u50.cfg -I$(SRC_DIR)/ $^ -o $(PRJ_NAME).xclbin 23 | 24 | emconfig.json: 25 | emconfigutil --platform xilinx_u50_gen3x16_xdma_201920_3 --nd 1 26 | 27 | clean: 28 | rm -rf $(PRJ_NAME)* app.exe *json *csv *log *summary _x xilinx* .run .Xil .ipcache *.jou 29 | 30 | echo: 31 | echo $(operators_src) 32 | 33 | # Unless specified, use the current directory name as the v++ build target 34 | TARGET ?= $(notdir $(CURDIR)) 35 | -------------------------------------------------------------------------------- /input_src/datamover/sw_emu/build_and_run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Exit when any command fails 4 | set -e 5 | source /scratch/unsafe/Xilinx/Vitis/2021.1/settings64.sh 6 | source /opt/xilinx/xrt/setup.sh 7 | 8 | # Make sure everything is up to date 9 | make all 10 | 11 | # Run the application in HW emulation mode 12 | XCL_EMULATION_MODE=sw_emu ./app.exe ydma.xclbin 13 | 14 | -------------------------------------------------------------------------------- /input_src/datamover/sw_emu/xrt.ini: -------------------------------------------------------------------------------- 1 | [Debug] 2 | profile=true 3 | timeline_trace=true 4 | -------------------------------------------------------------------------------- /input_src/rendering512/cfg/u50_dfx.cfg: -------------------------------------------------------------------------------- 1 | platform=xilinx_u50_gen3x16_xdma_201920_3 2 | debug=1 3 | save-temps=1 4 | 5 | [connectivity] 6 | nk=ydma:1:ydma_1 7 | sp=ydma_1.input1:HBM[0] 8 | sp=ydma_1.input2:HBM[1] 9 | sp=ydma_1.output1:HBM[0] 10 | sp=ydma_1.output2:HBM[1] 11 | 12 | [profile] 13 | data=all:all:all 14 | -------------------------------------------------------------------------------- /input_src/rendering512/cfg/zcu102.cfg: -------------------------------------------------------------------------------- 1 | platform=zcu102_custom 2 | debug=1 3 | save-temps=1 4 | 5 | [profile] 6 | data=all:all:all 7 | 8 | 9 | -------------------------------------------------------------------------------- /input_src/rendering512/cfg/zcu102_dfx.cfg: -------------------------------------------------------------------------------- 1 | platform=xilinx_zcu102_base_dfx_202020_1 2 | debug=1 3 | save-temps=1 4 | 5 | [profile] 6 | data=all:all:all 7 | 8 | 9 | -------------------------------------------------------------------------------- /input_src/rendering512/host/top.h: -------------------------------------------------------------------------------- 1 | /*===============================================================*/ 2 | /* */ 3 | /* rendering.h */ 4 | /* */ 5 | /* C++ kernel for 3D Rendering */ 6 | /* */ 7 | /*===============================================================*/ 8 | 9 | #ifndef __RENDERING_H__ 10 | #define __RENDERING_H__ 11 | 12 | #include "../host/typedefs.h" 13 | 14 | //#pragma SDS data access_pattern(input:SEQUENTIAL, output:SEQUENTIAL) 15 | 16 | void top ( 17 | hls::stream > & Input_1, 18 | hls::stream > & Output_1 19 | ); 20 | 21 | void data_gen( 22 | hls::stream > & Output_1 23 | ); 24 | 25 | void config_parser( 26 | hls::stream< bit64 > & input1, 27 | hls::stream< bit64 > & output1, 28 | hls::stream< bit64 > & output2 29 | ); 30 | #endif 31 | 32 | -------------------------------------------------------------------------------- /input_src/rendering512/operators/coloringFB_bot_m.h: -------------------------------------------------------------------------------- 1 | // color the frame buffer 2 | void coloringFB_bot_m( 3 | hls::stream > & Input_1, 4 | hls::stream > & Output_1); 5 | 6 | #pragma clb =4 ff=1 bram =2.4 dsp =1.2 7 | -------------------------------------------------------------------------------- /input_src/rendering512/operators/coloringFB_top_m.h: -------------------------------------------------------------------------------- 1 | // color the frame buffer 2 | void coloringFB_top_m( 3 | hls::stream > & Input_1, 4 | hls::stream > & Input_2, 5 | hls::stream > & Output_1); 6 | #pragma clb =4 ff= 1 bram =2.4 dsp =1.2 7 | -------------------------------------------------------------------------------- /input_src/rendering512/operators/data_redir_m.h: -------------------------------------------------------------------------------- 1 | void data_redir_m ( 2 | hls::stream > & Input_1, 3 | hls::stream > & Output_1, 4 | hls::stream > & Output_2 5 | ); 6 | 7 | #pragma map_target = HIPR 8 | #pragma clb =8 ff = 1 bram =2.4 dsp =1.2 9 | 10 | 11 | -------------------------------------------------------------------------------- /input_src/rendering512/operators/data_transfer.cpp: -------------------------------------------------------------------------------- 1 | #include "../host/typedefs.h" 2 | 3 | 4 | void data_transfer ( 5 | hls::stream > & Input_1, 6 | hls::stream > & Output_1 7 | ) 8 | { 9 | #pragma HLS INTERFACE axis register port=Input_1 10 | #pragma HLS INTERFACE axis register port=Output_1 11 | bit512 in_tmp; 12 | bit128 out_tmp; 13 | 14 | for ( int i = 0; i < NUM_3D_TRI/4; i++) 15 | { 16 | in_tmp = Input_1.read(); 17 | 18 | for (int j=0; j<4; j++){ 19 | #pragma HLS PIPELINE II=1 20 | for(int jj=0; jj<4; jj++){ 21 | out_tmp(jj*32+31, jj*32) = in_tmp(j*128+jj*32+31, j*128+jj*32); 22 | } 23 | Output_1.write(out_tmp); 24 | } 25 | } 26 | 27 | } 28 | 29 | -------------------------------------------------------------------------------- /input_src/rendering512/operators/data_transfer.h: -------------------------------------------------------------------------------- 1 | void data_transfer ( 2 | hls::stream > & Input_1, 3 | hls::stream > & Output_1 4 | ); 5 | 6 | #pragma clb =8 ff = 1 bram =2.4 dsp =1.2 7 | 8 | -------------------------------------------------------------------------------- /input_src/rendering512/operators/rasterization2_m.h: -------------------------------------------------------------------------------- 1 | 2 | void rasterization2_m ( 3 | hls::stream > & Input_1, 4 | hls::stream > & Output_1, 5 | hls::stream > & Output_2, 6 | 7 | hls::stream > & Input_2, 8 | hls::stream > & Output_3, 9 | hls::stream > & Output_4 10 | ); 11 | #pragma clb =4 ff = 1 bram =2.4 dsp =1.2 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /input_src/rendering512/operators/zculling_bot.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | // filter hidden pixels 5 | void zculling_bot ( 6 | hls::stream > & Input_1, 7 | hls::stream > & Input_2, 8 | hls::stream > & Output_1 9 | ); 10 | #pragma clb =4 ff = 1 bram =2.4 dsp =1.2 11 | -------------------------------------------------------------------------------- /input_src/rendering512/operators/zculling_top.h: -------------------------------------------------------------------------------- 1 | 2 | // filter hidden pixels 3 | void zculling_top ( 4 | hls::stream > & Input_1, 5 | hls::stream > & Input_2, 6 | hls::stream > & Output_1 7 | ); 8 | #pragma clb =4 ff=1 bram =2.4 dsp =1.2 9 | 10 | -------------------------------------------------------------------------------- /input_src/rendering512/sw_emu/Makefile: -------------------------------------------------------------------------------- 1 | PRJ_NAME=ydma 2 | SRC_DIR=.. 3 | operators_dir=./input_src/$(prj_name)/operators 4 | operators_src=$(wildcard $(SRC_DIR)/operators/*.cpp) 5 | 6 | all: app.exe emconfig.json $(PRJ_NAME).xclbin 7 | 8 | app.exe: $(SRC_DIR)/host/host.cpp 9 | g++ -Wall -g -std=c++11 $^ -o app.exe \ 10 | -I${XILINX_XRT}/include/ \ 11 | -I${XILINX_VIVADO}/include/ \ 12 | -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ 13 | 14 | $(PRJ_NAME).xo: $(SRC_DIR)/host/top.cpp $(SRC_DIR)/host/typedefs.h $(operators_src) 15 | v++ -c -t ${TARGET} --config $(SRC_DIR)/cfg/u50_dfx.cfg -k $(PRJ_NAME) \ 16 | -I${XILINX_VIVADO}/include/ \ 17 | -I$(SRC_DIR)/ \ 18 | -I$(SRC_DIR)/host \ 19 | $^ -o $(PRJ_NAME).xo 20 | 21 | $(PRJ_NAME).xclbin: ./$(PRJ_NAME).xo 22 | v++ -l -t ${TARGET} --config $(SRC_DIR)/cfg/u50_dfx.cfg -I$(SRC_DIR)/ $^ -o $(PRJ_NAME).xclbin 23 | 24 | emconfig.json: 25 | emconfigutil --platform xilinx_u50_gen3x16_xdma_201920_3 --nd 1 26 | 27 | clean: 28 | rm -rf $(PRJ_NAME)* app.exe *json *csv *log *summary _x xilinx* .run .Xil .ipcache *.jou 29 | 30 | echo: 31 | echo $(operators_src) 32 | 33 | # Unless specified, use the current directory name as the v++ build target 34 | TARGET ?= $(notdir $(CURDIR)) 35 | -------------------------------------------------------------------------------- /input_src/rendering512/sw_emu/build_and_run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Exit when any command fails 4 | set -e 5 | source /opt/Xilinx/Vitis/2021.1/settings64.sh 6 | source /opt/xilinx/xrt/setup.sh 7 | 8 | # Make sure everything is up to date 9 | make all 10 | 11 | # Run the application in HW emulation mode 12 | XCL_EMULATION_MODE=sw_emu ./app.exe ydma.xclbin 13 | 14 | -------------------------------------------------------------------------------- /input_src/rendering512/sw_emu/xrt.ini: -------------------------------------------------------------------------------- 1 | [Debug] 2 | profile=true 3 | timeline_trace=true 4 | -------------------------------------------------------------------------------- /input_src/rendering512/zcu102/Makefile: -------------------------------------------------------------------------------- 1 | SRC_DIR=.. 2 | img_name=$(basename $(wildcard $(SRC_DIR)/host/imageLib/*.cpp)) 3 | img_obj=$(addsuffix .o, $(img_name)) 4 | 5 | 6 | all: app.exe 7 | 8 | app.exe: ../host/host.cpp $(img_obj) 9 | ${CXX} -Wall -g -std=c++11 ../host/host.cpp $(img_obj) -o app.exe \ 10 | -I/usr/include/xrt \ 11 | -I${XILINX_VIVADO}/include \ 12 | -lOpenCL \ 13 | -lpthread \ 14 | -lrt \ 15 | -lstdc++ 16 | 17 | $(img_obj):$(SRC_DIR)/%.o:$(SRC_DIR)/%.cpp 18 | $(CXX) -Wall -g -std=c++11 -c $^ -o $@ 19 | 20 | 21 | clean: 22 | rm -rf *xclbin* app.exe *json *xo *csv *log *summary _x package *.json .run .Xil .ipcache *.jou 23 | rm -rf ../host/imageLib/*.o 24 | -------------------------------------------------------------------------------- /input_src/rendering512/zcu102/app.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/input_src/rendering512/zcu102/app.exe -------------------------------------------------------------------------------- /input_src/rendering512/zcu102/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | source /opt/Xilinx/Vitis/2021.1/settings64.sh 4 | export PLATFORM_REPO_PATHS=/opt/xilinx/platforms/xilinx_zcu102_base_dfx_202110_1 5 | export ROOTFS=/opt/xilinx/platforms/xilinx_zcu102_base_dfx_202110_1/sw/xilinx_zcu102_base_dfx_202110_1/xrt/filesystem 6 | 7 | 8 | source /opt/xilinx/xrt/setup.sh 9 | unset LD_LIBRARY_PATH 10 | 11 | source /opt/xilinx-zynqmp-common-v2021.1/ir/environment-setup-cortexa72-cortexa53-xilinx-linux 12 | 13 | # Make sure everything is up to date 14 | make app.exe 15 | -------------------------------------------------------------------------------- /input_src/rendering512_all/cfg/u50_dfx.cfg: -------------------------------------------------------------------------------- 1 | platform=xilinx_u50_gen3x16_xdma_201920_3 2 | debug=1 3 | save-temps=1 4 | 5 | [connectivity] 6 | nk=ydma:1:ydma_1 7 | sp=ydma_1.input1:HBM[0] 8 | sp=ydma_1.input2:HBM[1] 9 | sp=ydma_1.output1:HBM[0] 10 | sp=ydma_1.output2:HBM[1] 11 | 12 | [profile] 13 | data=all:all:all 14 | -------------------------------------------------------------------------------- /input_src/rendering512_all/cfg/zcu102.cfg: -------------------------------------------------------------------------------- 1 | platform=zcu102_custom 2 | debug=1 3 | save-temps=1 4 | 5 | [profile] 6 | data=all:all:all 7 | 8 | 9 | -------------------------------------------------------------------------------- /input_src/rendering512_all/cfg/zcu102_dfx.cfg: -------------------------------------------------------------------------------- 1 | platform=xilinx_zcu102_base_dfx_202020_1 2 | debug=1 3 | save-temps=1 4 | 5 | [profile] 6 | data=all:all:all 7 | 8 | 9 | -------------------------------------------------------------------------------- /input_src/rendering512_all/host/top.h: -------------------------------------------------------------------------------- 1 | /*===============================================================*/ 2 | /* */ 3 | /* rendering.h */ 4 | /* */ 5 | /* C++ kernel for 3D Rendering */ 6 | /* */ 7 | /*===============================================================*/ 8 | 9 | #ifndef __RENDERING_H__ 10 | #define __RENDERING_H__ 11 | 12 | #include "../host/typedefs.h" 13 | 14 | //#pragma SDS data access_pattern(input:SEQUENTIAL, output:SEQUENTIAL) 15 | 16 | void top ( 17 | hls::stream > & Input_1, 18 | hls::stream > & Output_1 19 | ); 20 | 21 | void data_gen( 22 | hls::stream > & Output_1 23 | ); 24 | 25 | void config_parser( 26 | hls::stream< bit64 > & input1, 27 | hls::stream< bit64 > & output1, 28 | hls::stream< bit64 > & output2 29 | ); 30 | #endif 31 | 32 | -------------------------------------------------------------------------------- /input_src/rendering512_all/operators/coloringFB_bot_m.h: -------------------------------------------------------------------------------- 1 | // color the frame buffer 2 | void coloringFB_bot_m( 3 | hls::stream > & Input_1, 4 | hls::stream > & Output_1); 5 | 6 | #pragma map_target = HIPR 7 | #pragma clb =4 ff=1 bram =6 dsp =1.2 8 | -------------------------------------------------------------------------------- /input_src/rendering512_all/operators/coloringFB_top_m.h: -------------------------------------------------------------------------------- 1 | // color the frame buffer 2 | void coloringFB_top_m( 3 | hls::stream > & Input_1, 4 | hls::stream > & Input_2, 5 | hls::stream > & Output_1); 6 | #pragma map_target = HIPR 7 | #pragma clb =4 ff= 1 bram =6 dsp =1.2 8 | -------------------------------------------------------------------------------- /input_src/rendering512_all/operators/data_redir_m.h: -------------------------------------------------------------------------------- 1 | void data_redir_m ( 2 | hls::stream > & Input_1, 3 | hls::stream > & Output_1, 4 | hls::stream > & Output_2 5 | ); 6 | 7 | #pragma map_target = HIPR 8 | #pragma clb =8 ff = 1 bram =6 dsp =1.2 9 | 10 | 11 | -------------------------------------------------------------------------------- /input_src/rendering512_all/operators/data_transfer.cpp: -------------------------------------------------------------------------------- 1 | #include "../host/typedefs.h" 2 | 3 | 4 | void data_transfer ( 5 | hls::stream > & Input_1, 6 | hls::stream > & Output_1 7 | ) 8 | { 9 | #pragma HLS INTERFACE axis register port=Input_1 10 | #pragma HLS INTERFACE axis register port=Output_1 11 | bit512 in_tmp; 12 | bit128 out_tmp; 13 | 14 | for ( int i = 0; i < NUM_3D_TRI/4; i++) 15 | { 16 | in_tmp = Input_1.read(); 17 | 18 | for (int j=0; j<4; j++){ 19 | #pragma HLS PIPELINE II=1 20 | for(int jj=0; jj<4; jj++){ 21 | out_tmp(jj*32+31, jj*32) = in_tmp(j*128+jj*32+31, j*128+jj*32); 22 | } 23 | Output_1.write(out_tmp); 24 | } 25 | } 26 | 27 | } 28 | 29 | -------------------------------------------------------------------------------- /input_src/rendering512_all/operators/data_transfer.h: -------------------------------------------------------------------------------- 1 | void data_transfer ( 2 | hls::stream > & Input_1, 3 | hls::stream > & Output_1 4 | ); 5 | 6 | #pragma map_target = HIPR 7 | #pragma clb =8 ff = 1 bram =6 dsp =1.2 8 | 9 | -------------------------------------------------------------------------------- /input_src/rendering512_all/operators/rasterization2_m.h: -------------------------------------------------------------------------------- 1 | 2 | void rasterization2_m ( 3 | hls::stream > & Input_1, 4 | hls::stream > & Output_1, 5 | hls::stream > & Output_2, 6 | 7 | hls::stream > & Input_2, 8 | hls::stream > & Output_3, 9 | hls::stream > & Output_4 10 | ); 11 | #pragma map_target = HIPR 12 | #pragma clb =4 ff = 1 bram =6 dsp =1.2 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /input_src/rendering512_all/operators/zculling_bot.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | // filter hidden pixels 5 | void zculling_bot ( 6 | hls::stream > & Input_1, 7 | hls::stream > & Input_2, 8 | hls::stream > & Output_1 9 | ); 10 | 11 | #pragma map_target = HIPR 12 | #pragma clb =4 ff = 1 bram =6 dsp =1.2 13 | -------------------------------------------------------------------------------- /input_src/rendering512_all/operators/zculling_top.h: -------------------------------------------------------------------------------- 1 | 2 | // filter hidden pixels 3 | void zculling_top ( 4 | hls::stream > & Input_1, 5 | hls::stream > & Input_2, 6 | hls::stream > & Output_1 7 | ); 8 | #pragma map_target = HIPR 9 | #pragma clb =4 ff=1 bram =6 dsp =1.2 10 | 11 | -------------------------------------------------------------------------------- /input_src/rendering512_all/sw_emu/Makefile: -------------------------------------------------------------------------------- 1 | PRJ_NAME=ydma 2 | SRC_DIR=.. 3 | operators_dir=./input_src/$(prj_name)/operators 4 | operators_src=$(wildcard $(SRC_DIR)/operators/*.cpp) 5 | 6 | all: app.exe emconfig.json $(PRJ_NAME).xclbin 7 | 8 | app.exe: $(SRC_DIR)/host/host.cpp 9 | g++ -Wall -g -std=c++11 $^ -o app.exe \ 10 | -I${XILINX_XRT}/include/ \ 11 | -I${XILINX_VIVADO}/include/ \ 12 | -L${XILINX_XRT}/lib/ -lOpenCL -lpthread -lrt -lstdc++ 13 | 14 | $(PRJ_NAME).xo: $(SRC_DIR)/host/top.cpp $(SRC_DIR)/host/typedefs.h $(operators_src) 15 | v++ -c -t ${TARGET} --config $(SRC_DIR)/cfg/u50_dfx.cfg -k $(PRJ_NAME) \ 16 | -I${XILINX_VIVADO}/include/ \ 17 | -I$(SRC_DIR)/ \ 18 | -I$(SRC_DIR)/host \ 19 | $^ -o $(PRJ_NAME).xo 20 | 21 | $(PRJ_NAME).xclbin: ./$(PRJ_NAME).xo 22 | v++ -l -t ${TARGET} --config $(SRC_DIR)/cfg/u50_dfx.cfg -I$(SRC_DIR)/ $^ -o $(PRJ_NAME).xclbin 23 | 24 | emconfig.json: 25 | emconfigutil --platform xilinx_u50_gen3x16_xdma_201920_3 --nd 1 26 | 27 | clean: 28 | rm -rf $(PRJ_NAME)* app.exe *json *csv *log *summary _x xilinx* .run .Xil .ipcache *.jou 29 | 30 | echo: 31 | echo $(operators_src) 32 | 33 | # Unless specified, use the current directory name as the v++ build target 34 | TARGET ?= $(notdir $(CURDIR)) 35 | -------------------------------------------------------------------------------- /input_src/rendering512_all/sw_emu/build_and_run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Exit when any command fails 4 | set -e 5 | source /opt/Xilinx/Vitis/2021.1/settings64.sh 6 | source /opt/xilinx/xrt/setup.sh 7 | 8 | # Make sure everything is up to date 9 | make all 10 | 11 | # Run the application in HW emulation mode 12 | XCL_EMULATION_MODE=sw_emu ./app.exe ydma.xclbin 13 | 14 | -------------------------------------------------------------------------------- /input_src/rendering512_all/sw_emu/xrt.ini: -------------------------------------------------------------------------------- 1 | [Debug] 2 | profile=true 3 | timeline_trace=true 4 | -------------------------------------------------------------------------------- /input_src/rendering512_all/zcu102/Makefile: -------------------------------------------------------------------------------- 1 | SRC_DIR=.. 2 | img_name=$(basename $(wildcard $(SRC_DIR)/host/imageLib/*.cpp)) 3 | img_obj=$(addsuffix .o, $(img_name)) 4 | 5 | 6 | all: app.exe 7 | 8 | app.exe: ../host/host.cpp $(img_obj) 9 | ${CXX} -Wall -g -std=c++11 ../host/host.cpp $(img_obj) -o app.exe \ 10 | -I/usr/include/xrt \ 11 | -I${XILINX_VIVADO}/include \ 12 | -lOpenCL \ 13 | -lpthread \ 14 | -lrt \ 15 | -lstdc++ 16 | 17 | $(img_obj):$(SRC_DIR)/%.o:$(SRC_DIR)/%.cpp 18 | $(CXX) -Wall -g -std=c++11 -c $^ -o $@ 19 | 20 | 21 | clean: 22 | rm -rf *xclbin* app.exe *json *xo *csv *log *summary _x package *.json .run .Xil .ipcache *.jou 23 | rm -rf ../host/imageLib/*.o 24 | -------------------------------------------------------------------------------- /input_src/rendering512_all/zcu102/app.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/input_src/rendering512_all/zcu102/app.exe -------------------------------------------------------------------------------- /input_src/rendering512_all/zcu102/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | source /opt/Xilinx/Vitis/2021.1/settings64.sh 4 | export PLATFORM_REPO_PATHS=/opt/xilinx/platforms/xilinx_zcu102_base_dfx_202110_1 5 | export ROOTFS=/opt/xilinx/platforms/xilinx_zcu102_base_dfx_202110_1/sw/xilinx_zcu102_base_dfx_202110_1/xrt/filesystem 6 | 7 | 8 | source /opt/xilinx/xrt/setup.sh 9 | unset LD_LIBRARY_PATH 10 | 11 | source /opt/xilinx-zynqmp-common-v2021.1/ir/environment-setup-cortexa72-cortexa53-xilinx-linux 12 | 13 | # Make sure everything is up to date 14 | make app.exe 15 | -------------------------------------------------------------------------------- /pr_flow/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/icgrp/hipr/f7d717144472afcf85f186047346097a0326931b/pr_flow/__init__.py -------------------------------------------------------------------------------- /pr_flow/gen_bft.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | 3 | import os 4 | import subprocess 5 | 6 | class gen_bft: 7 | def __init__(self, prflow_params): 8 | self.prflow_params = prflow_params 9 | 10 | def bft_gen(self): 11 | #cp the bft src to workspace directory and then generate the bft verilog files. 12 | os.system('rm -rf '+self.prflow_params['workspace']+'/F000_bft_gen') 13 | os.system('cp -rf ./input_files/bft_src '+self.prflow_params['workspace']+'/F000_bft_gen') 14 | os.chdir(self.prflow_params['workspace']+'/F000_bft_gen') 15 | os.system('make clean') 16 | os.system('python3 network_tester.py -s -nl ' + self.prflow_params['nl']\ 17 | + ' -p ' + self.prflow_params['p'] + ' -pks ' + self.prflow_params['pks']) 18 | os.chdir('../../') 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /pr_flow/utils.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import sys 3 | import os 4 | import xml.etree.ElementTree 5 | import argparse 6 | import re 7 | import math 8 | 9 | 10 | def load_prflow_params(filename): 11 | prflow_params = { 12 | } 13 | 14 | # parse the common specifications 15 | root = xml.etree.ElementTree.parse(filename).getroot() 16 | specs = root.findall('spec') 17 | network = root.findall('network') 18 | clock =root.findall('clock') 19 | 20 | for child in specs: prflow_params[child.get('name')] = child.get('value') 21 | for child in clock: prflow_params[child.get('name')] = child.get('period') 22 | 23 | print (filename.replace('configure/', 'configure/'+prflow_params['board']+'/')) 24 | board_root = root = xml.etree.ElementTree.parse(filename.replace('configure/', 'configure/'+prflow_params['board']+'/')).getroot() 25 | specs = board_root.findall('spec') 26 | for child in specs: prflow_params[child.get('name')] = child.get('value') 27 | 28 | 29 | return prflow_params 30 | 31 | 32 | 33 | --------------------------------------------------------------------------------