├── .github
    └── workflows
    │   └── rust.yml
├── .gitignore
├── Cargo.toml
├── LICENSE
├── examples
    ├── rv32i.rs
    └── subleq.rs
├── readme.md
├── src
    ├── lib.rs
    └── tests
    │   ├── error.rs
    │   ├── la64.rs
    │   ├── mips.rs
    │   ├── mod.rs
    │   ├── rv32.rs
    │   ├── rv64.rs
    │   └── util.rs
├── test_data
    ├── la64
    │   └── la64.test
    ├── mips
    │   └── mips.test
    ├── rv32
    │   ├── rv32a.test
    │   ├── rv32c.test
    │   ├── rv32f.test
    │   ├── rv32i.test
    │   ├── rv32m.test
    │   ├── rv32zbb.test
    │   ├── rv32zbkb.test
    │   ├── rv32zbs.test
    │   ├── rv32zfa.test
    │   ├── rv32zicsr.test
    │   ├── rv32zknd.test
    │   └── rv32zkne.test
    └── rv64
    │   ├── rv64a.test
    │   ├── rv64c.test
    │   ├── rv64d.test
    │   ├── rv64i.test
    │   ├── rv64m.test
    │   ├── rv64zbb.test
    │   ├── rv64zbkb.test
    │   ├── rv64zbs.test
    │   ├── rv64zcd.test
    │   ├── rv64zfa.test
    │   ├── rv64zfh.test
    │   ├── rv64zicond.test
    │   ├── rv64zknd.test
    │   ├── rv64zkne.test
    │   ├── rvv.test
    │   ├── rvzawrs.test
    │   ├── rvzba.test
    │   ├── rvzbc.test
    │   ├── rvzbkc.test
    │   ├── rvzbkx.test
    │   ├── rvzknh.test
    │   ├── rvzksed.test
    │   ├── rvzksh.test
    │   ├── rvzvbb.test
    │   ├── rvzvbc.test
    │   ├── rvzvkg.test
    │   ├── rvzvkned.test
    │   ├── rvzvknha.test
    │   ├── rvzvknhb.test
    │   ├── rvzvksed.test
    │   └── rvzvksh.test
├── toml-with-errors
    └── mips.toml
├── toml
    ├── RV32A.toml
    ├── RV32C-lower.toml
    ├── RV32C.toml
    ├── RV32F.toml
    ├── RV32I.toml
    ├── RV32M.toml
    ├── RV32_Zacas.toml
    ├── RV32_Zbb.toml
    ├── RV32_Zbkb.toml
    ├── RV32_Zbs.toml
    ├── RV32_Zcb-lower.toml
    ├── RV32_Zcb.toml
    ├── RV32_Zcf-lower.toml
    ├── RV32_Zcf.toml
    ├── RV32_Zfa.toml
    ├── RV32_Zicsr.toml
    ├── RV32_Zknd.toml
    ├── RV32_Zkne.toml
    ├── RV64A.toml
    ├── RV64C-lower.toml
    ├── RV64C.toml
    ├── RV64D.toml
    ├── RV64I.toml
    ├── RV64M.toml
    ├── RV64_Zacas.toml
    ├── RV64_Zbb.toml
    ├── RV64_Zbkb.toml
    ├── RV64_Zbs.toml
    ├── RV64_Zcb-lower.toml
    ├── RV64_Zcb.toml
    ├── RV64_Zcd-lower.toml
    ├── RV64_Zcd.toml
    ├── RV64_Zfa.toml
    ├── RV64_Zknd.toml
    ├── RV64_Zkne.toml
    ├── RVV.toml
    ├── RV_Zawrs.toml
    ├── RV_Zba.toml
    ├── RV_Zbc.toml
    ├── RV_Zbkc.toml
    ├── RV_Zbkx.toml
    ├── RV_Zcd-lower.toml
    ├── RV_Zcd.toml
    ├── RV_Zfh.toml
    ├── RV_Zicbo.toml
    ├── RV_Zicond.toml
    ├── RV_Zifencei.toml
    ├── RV_Zihintntl.toml
    ├── RV_Zimop.toml
    ├── RV_Zknh.toml
    ├── RV_Zksed.toml
    ├── RV_Zksh.toml
    ├── RV_Zvbb.toml
    ├── RV_Zvbc.toml
    ├── RV_Zvkg.toml
    ├── RV_Zvkned.toml
    ├── RV_Zvknha.toml
    ├── RV_Zvknhb.toml
    ├── RV_Zvksed.toml
    ├── RV_Zvksh.toml
    ├── la64.toml
    ├── mips.toml
    └── subleq.toml
└── tomlspec.md


/.github/workflows/rust.yml:
--------------------------------------------------------------------------------
 1 | name: Rust
 2 | 
 3 | on:
 4 |   push:
 5 |     branches: [ "master" ]
 6 |   pull_request:
 7 |     branches: [ "master" ]
 8 | 
 9 | env:
10 |   CARGO_TERM_COLOR: always
11 | 
12 | jobs:
13 |   build:
14 | 
15 |     runs-on: ubuntu-latest
16 | 
17 |     steps:
18 |     - uses: actions/checkout@v4
19 |     - name: Build
20 |       run: cargo build --verbose
21 |     - name: Run tests
22 |       run: cargo test --verbose
23 |     - name: Run Clippy
24 |       run: cargo clippy -- -D warnings --no-deps
25 | 


--------------------------------------------------------------------------------
/.gitignore:
--------------------------------------------------------------------------------
1 | /target
2 | Cargo.lock
3 | 


--------------------------------------------------------------------------------
/Cargo.toml:
--------------------------------------------------------------------------------
1 | [package]
2 | name = "instruction-decoder"
3 | version = "0.1.0"
4 | edition = "2021"
5 | license = "MIT"
6 | 
7 | [dependencies]
8 | toml = "0.8.12"
9 | 


--------------------------------------------------------------------------------
/LICENSE:
--------------------------------------------------------------------------------
 1 | MIT License
 2 | 
 3 | Copyright (c) 2024 Johannes Kepler University Linz
 4 | 
 5 | Permission is hereby granted, free of charge, to any person obtaining a copy
 6 | of this software and associated documentation files (the "Software"), to deal
 7 | in the Software without restriction, including without limitation the rights
 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 9 | copies of the Software, and to permit persons to whom the Software is
10 | furnished to do so, subject to the following conditions:
11 | 
12 | The above copyright notice and this permission notice shall be included in all
13 | copies or substantial portions of the Software.
14 | 
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 | SOFTWARE.
22 | 


--------------------------------------------------------------------------------
/examples/rv32i.rs:
--------------------------------------------------------------------------------
 1 | use instruction_decoder::Decoder;
 2 | 
 3 | pub fn main() {
 4 |     match Decoder::new(&vec![include_str!("../toml/RV32I.toml").to_string()]) {
 5 |         Ok(test_decoder) => {
 6 |             let inst = 0xff460593;
 7 | 
 8 |             if let Ok(iform) = test_decoder.decode_from_i64(inst, 32) {
 9 |                 println!("{:?}", iform);
10 |             }
11 |         }
12 |         Err(error_stacks) => {
13 |             println!("Errors in ../toml/RV32I.toml:");
14 |             for error in &error_stacks[0] {
15 |                 println!("\t{}", error);
16 |             }
17 |         }
18 |     }
19 | }
20 | 


--------------------------------------------------------------------------------
/examples/subleq.rs:
--------------------------------------------------------------------------------
 1 | use instruction_decoder::Decoder;
 2 | 
 3 | pub fn main() {
 4 |     match Decoder::new(&vec![include_str!("../toml/subleq.toml").to_string()]) {
 5 |         Ok(test_decoder) => {
 6 |             let inst = 0x1204;
 7 | 
 8 |             if let Ok(iform) = test_decoder.decode_from_i64(inst, 32) {
 9 |                 println!("{:?}", iform);
10 |             }
11 |         }
12 |         Err(error_stacks) => {
13 |             println!("Errors in ../toml/subleq.toml:");
14 |             for error in &error_stacks[0] {
15 |                 println!("\t{}", error);
16 |             }
17 |         }
18 |     }
19 | }
20 | 


--------------------------------------------------------------------------------
/readme.md:
--------------------------------------------------------------------------------
 1 | example useage:
 2 | 
 3 | ```
 4 | use instruction_decoder::Decoder;
 5 | 
 6 | pub fn main() {
 7 |     let mut test_decoder = Decoder::new(&vec![include_str!("RV32I.toml").to_string()]);
 8 |     let inst = 0xff460593;
 9 | 
10 |     if let Ok(iform) = test_decoder.decode_from_i64(inst, 32) {
11 |         println!("{:?}", iform);
12 |     }
13 | }
14 | ```
15 | 
16 | for the spec, see [tomlspec.md](tomlspec.md) or the github wiki


--------------------------------------------------------------------------------
/src/tests/error.rs:
--------------------------------------------------------------------------------
 1 | use crate::error_test;
 2 | use crate::Decoder;
 3 | 
 4 | #[test]
 5 | fn test_no_error() {
 6 |     error_test!("../../toml/mips.toml", Vec::<String>::new());
 7 | }
 8 | 
 9 | #[test]
10 | fn test_some_error() {
11 |     error_test!(
12 |         "../../toml-with-errors/mips.toml",
13 |         vec!["key 'types.B' not found in toml".to_string()]
14 |     );
15 | }
16 | 


--------------------------------------------------------------------------------
/src/tests/la64.rs:
--------------------------------------------------------------------------------
1 | use crate::isa_test;
2 | use crate::Decoder;
3 | use std::fs::read_to_string;
4 | 
5 | #[test]
6 | fn test_la64() {
7 |     isa_test!("../../toml/la64.toml", "test_data/la64/la64.test");
8 | }
9 | 


--------------------------------------------------------------------------------
/src/tests/mips.rs:
--------------------------------------------------------------------------------
1 | use crate::isa_test;
2 | use crate::Decoder;
3 | use std::fs::read_to_string;
4 | 
5 | #[test]
6 | fn test_mips() {
7 |     isa_test!("../../toml/mips.toml", "test_data/mips/mips.test");
8 | }
9 | 


--------------------------------------------------------------------------------
/src/tests/mod.rs:
--------------------------------------------------------------------------------
1 | mod error;
2 | mod mips;
3 | mod rv32;
4 | mod rv64;
5 | mod la64;
6 | mod util;
7 | 


--------------------------------------------------------------------------------
/src/tests/rv32.rs:
--------------------------------------------------------------------------------
 1 | use crate::isa_test;
 2 | use crate::Decoder;
 3 | use std::fs::read_to_string;
 4 | 
 5 | #[test]
 6 | fn test_rv32i() {
 7 |     isa_test!("../../toml/RV32I.toml", "test_data/rv32/rv32i.test");
 8 | }
 9 | 
10 | #[test]
11 | fn test_rv32m() {
12 |     isa_test!("../../toml/RV32M.toml", "test_data/rv32/rv32m.test");
13 | }
14 | 
15 | #[test]
16 | fn test_rv32a() {
17 |     isa_test!("../../toml/RV32A.toml", "test_data/rv32/rv32a.test");
18 | }
19 | 
20 | #[test]
21 | fn test_rv32f() {
22 |     isa_test!("../../toml/RV32F.toml", "test_data/rv32/rv32f.test");
23 | }
24 | 
25 | #[test]
26 | fn test_rv32zicsr() {
27 |     isa_test!(
28 |         "../../toml/RV32_Zicsr.toml",
29 |         "test_data/rv32/rv32zicsr.test"
30 |     );
31 | }
32 | 
33 | #[test]
34 | fn test_rv32_zbb() {
35 |     isa_test!("../../toml/RV32_Zbb.toml", "test_data/rv32/rv32zbb.test");
36 | }
37 | 
38 | #[test]
39 | fn test_rv32_zbs() {
40 |     isa_test!("../../toml/RV32_Zbs.toml", "test_data/rv32/rv32zbs.test");
41 | }
42 | 
43 | #[test]
44 | fn test_rv32_zbkb() {
45 |     isa_test!("../../toml/RV32_Zbkb.toml", "test_data/rv32/rv32zbkb.test");
46 | }
47 | 
48 | #[test]
49 | fn test_rv32_zkne() {
50 |     isa_test!("../../toml/RV32_Zkne.toml", "test_data/rv32/rv32zkne.test");
51 | }
52 | 
53 | #[test]
54 | fn test_rv32_c() {
55 |     isa_test!("../../toml/RV32C.toml", "test_data/rv32/rv32c.test");
56 | }
57 | 
58 | #[test]
59 | fn test_rv32_zfa() {
60 |     isa_test!("../../toml/RV32_Zfa.toml", "test_data/rv32/rv32zfa.test");
61 | }
62 | 


--------------------------------------------------------------------------------
/src/tests/rv64.rs:
--------------------------------------------------------------------------------
  1 | use crate::isa_test;
  2 | use crate::Decoder;
  3 | use std::fs::read_to_string;
  4 | 
  5 | #[test]
  6 | fn test_rv64i() {
  7 |     isa_test!("../../toml/RV64I.toml", "test_data/rv64/rv64i.test");
  8 | }
  9 | 
 10 | #[test]
 11 | fn test_rv64d() {
 12 |     isa_test!("../../toml/RV64D.toml", "test_data/rv64/rv64d.test");
 13 | }
 14 | 
 15 | #[test]
 16 | fn test_rv64_zba() {
 17 |     isa_test!("../../toml/RV_Zba.toml", "test_data/rv64/rvzba.test");
 18 | }
 19 | 
 20 | #[test]
 21 | fn test_rv64_zbb() {
 22 |     isa_test!("../../toml/RV64_Zbb.toml", "test_data/rv64/rv64zbb.test");
 23 | }
 24 | 
 25 | #[test]
 26 | fn test_rv64_zbc() {
 27 |     isa_test!("../../toml/RV_Zbc.toml", "test_data/rv64/rvzbc.test");
 28 | }
 29 | 
 30 | #[test]
 31 | fn test_rv64_zbs() {
 32 |     isa_test!("../../toml/RV64_Zbs.toml", "test_data/rv64/rv64zbs.test");
 33 | }
 34 | 
 35 | #[test]
 36 | fn test_rv64_zfh() {
 37 |     isa_test!("../../toml/RV_Zfh.toml", "test_data/rv64/rv64zfh.test");
 38 | }
 39 | 
 40 | #[test]
 41 | fn test_rv64_zicond() {
 42 |     isa_test!(
 43 |         "../../toml/RV_Zicond.toml",
 44 |         "test_data/rv64/rv64zicond.test"
 45 |     );
 46 | }
 47 | 
 48 | #[test]
 49 | fn test_rv64_zbkb() {
 50 |     isa_test!("../../toml/RV64_Zbkb.toml", "test_data/rv64/rv64zbkb.test");
 51 | }
 52 | 
 53 | #[test]
 54 | fn test_rv64_zbkc() {
 55 |     isa_test!("../../toml/RV_Zbkc.toml", "test_data/rv64/rvzbkc.test");
 56 | }
 57 | 
 58 | #[test]
 59 | fn test_rv64_zbkx() {
 60 |     isa_test!("../../toml/RV_Zbkx.toml", "test_data/rv64/rvzbkx.test");
 61 | }
 62 | 
 63 | #[test]
 64 | fn test_rv64_zkne() {
 65 |     isa_test!("../../toml/RV64_Zkne.toml", "test_data/rv64/rv64zkne.test");
 66 | }
 67 | 
 68 | #[test]
 69 | fn test_rv64_zknd() {
 70 |     isa_test!("../../toml/RV64_Zknd.toml", "test_data/rv64/rv64zknd.test");
 71 | }
 72 | 
 73 | #[test]
 74 | fn test_rv64_zknh() {
 75 |     isa_test!("../../toml/RV_Zknh.toml", "test_data/rv64/rvzknh.test");
 76 | }
 77 | 
 78 | #[test]
 79 | fn test_rv64_zksed() {
 80 |     isa_test!("../../toml/RV_Zksed.toml", "test_data/rv64/rvzksed.test");
 81 | }
 82 | 
 83 | #[test]
 84 | fn test_rv64_zksh() {
 85 |     isa_test!("../../toml/RV_Zksh.toml", "test_data/rv64/rvzksh.test");
 86 | }
 87 | 
 88 | #[test]
 89 | fn test_rv64_zvbb() {
 90 |     isa_test!("../../toml/RV_Zvbb.toml", "test_data/rv64/rvzvbb.test");
 91 | }
 92 | 
 93 | #[test]
 94 | fn test_rv64_zvbc() {
 95 |     isa_test!("../../toml/RV_Zvbc.toml", "test_data/rv64/rvzvbc.test");
 96 | }
 97 | 
 98 | #[test]
 99 | fn test_rv64_zvkg() {
100 |     isa_test!("../../toml/RV_Zvkg.toml", "test_data/rv64/rvzvkg.test");
101 | }
102 | 
103 | #[test]
104 | fn test_rv64_zvkned() {
105 |     isa_test!("../../toml/RV_Zvkned.toml", "test_data/rv64/rvzvkned.test");
106 | }
107 | 
108 | #[test]
109 | fn test_rv64_zvknha() {
110 |     isa_test!("../../toml/RV_Zvknha.toml", "test_data/rv64/rvzvknha.test");
111 | }
112 | 
113 | #[test]
114 | fn test_rv64_zvknhb() {
115 |     isa_test!("../../toml/RV_Zvknhb.toml", "test_data/rv64/rvzvknhb.test");
116 | }
117 | 
118 | #[test]
119 | fn test_rv64_zvksed() {
120 |     isa_test!("../../toml/RV_Zvksed.toml", "test_data/rv64/rvzvksed.test");
121 | }
122 | 
123 | #[test]
124 | fn test_rv64_zvksh() {
125 |     isa_test!("../../toml/RV_Zvksh.toml", "test_data/rv64/rvzvksh.test");
126 | }
127 | 
128 | #[test]
129 | fn test_rv64_zawrs() {
130 |     isa_test!("../../toml/RV_Zawrs.toml", "test_data/rv64/rvzawrs.test");
131 | }
132 | 
133 | #[test]
134 | fn test_rv64_c() {
135 |     isa_test!("../../toml/RV64C.toml", "test_data/rv64/rv64c.test");
136 | }
137 | 
138 | #[test]
139 | fn test_rv64_zcd() {
140 |     isa_test!("../../toml/RV64_Zcd.toml", "test_data/rv64/rv64zcd.test");
141 | }
142 | 
143 | #[test]
144 | fn test_rv64_zfa() {
145 |     isa_test!("../../toml/RV64_Zfa.toml", "test_data/rv64/rv64zfa.test");
146 | }
147 | 
148 | #[test]
149 | fn test_rvv() {
150 |     isa_test!("../../toml/RVV.toml", "test_data/rv64/rvv.test");
151 | }
152 | 


--------------------------------------------------------------------------------
/src/tests/util.rs:
--------------------------------------------------------------------------------
 1 | #[macro_export]
 2 | macro_rules! isa_test {
 3 |     ($toml:expr, $test:expr) => {
 4 |         match Decoder::new(&vec![include_str!($toml).to_string()]) {
 5 |             Ok(test_decoder) => {
 6 |                 read_to_string($test).unwrap().lines().for_each(|line| {
 7 |                     if let Some((instr_hex, expected)) = line.split_once(' ') {
 8 |                         let instr = i64::from_str_radix(instr_hex, 16).unwrap();
 9 |                         let iform = test_decoder.decode_from_i64(
10 |                             instr,
11 |                             test_decoder.instruction_sets.get(0).unwrap().bit_width,
12 |                         );
13 |                         assert!(
14 |                             iform.is_ok(),
15 |                             "Can not decode {} into expected {}",
16 |                             instr_hex,
17 |                             expected.trim()
18 |                         );
19 |                         if let Ok(iform) = iform {
20 |                             assert_eq!(
21 |                                 iform,
22 |                                 expected.trim(),
23 |                                 "Decoding {} does not match expected value",
24 |                                 instr_hex
25 |                             );
26 |                         }
27 |                     }
28 |                 });
29 |             }
30 |             Err(error_stacks) => {
31 |                 panic!("Got errors when parsing tomls: {:?}", error_stacks)
32 |             }
33 |         }
34 |     };
35 | }
36 | 
37 | #[macro_export]
38 | macro_rules! error_test {
39 |     ($toml:expr, $error_stack:expr) => {
40 |         match Decoder::new(&vec![include_str!($toml).to_string()]) {
41 |             Ok(_) => assert!(
42 |                 $error_stack.is_empty(),
43 |                 "Expected errors {:?} but found none",
44 |                 $error_stack,
45 |             ),
46 |             Err(error_stacks) => {
47 |                 assert_eq!(
48 |                     $error_stack, error_stacks[0],
49 |                     "Expected errors {:?} but found {:?}",
50 |                     $error_stack, error_stacks[0],
51 |                 );
52 |             }
53 |         };
54 |     };
55 | }
56 | 


--------------------------------------------------------------------------------
/test_data/mips/mips.test:
--------------------------------------------------------------------------------
  1 | 24010000 addiu $at, $zero, 0
  2 | 24010029 addiu $at, $zero, 41
  3 | 24210000 addiu $at, $at, 0
  4 | 24210001 addiu $at, $at, 1
  5 | 24610001 addiu $at, $v1, 1
  6 | 24020000 addiu $v0, $zero, 0
  7 | 24020020 addiu $v0, $zero, 32
  8 | 24020027 addiu $v0, $zero, 39
  9 | 24020028 addiu $v0, $zero, 40
 10 | 2402ffff addiu $v0, $zero, -1
 11 | 24220000 addiu $v0, $at, 0
 12 | 24420000 addiu $v0, $v0, 0
 13 | 24420001 addiu $v0, $v0, 1
 14 | 24030000 addiu $v1, $zero, 0
 15 | 2443ffff addiu $v1, $v0, -1
 16 | 2463ffff addiu $v1, $v1, -1
 17 | 24040000 addiu $a0, $zero, 0
 18 | 24040020 addiu $a0, $zero, 32
 19 | 24040027 addiu $a0, $zero, 39
 20 | 24040028 addiu $a0, $zero, 40
 21 | 24040029 addiu $a0, $zero, 41
 22 | 24240000 addiu $a0, $at, 0
 23 | 24050000 addiu $a1, $zero, 0
 24 | 24250000 addiu $a1, $at, 0
 25 | 27c60020 addiu $a2, $fp, 32
 26 | 27c7001c addiu $a3, $fp, 28
 27 | 27bdffb8 addiu $sp, $sp, -72
 28 | 27bdffc0 addiu $sp, $sp, -64
 29 | 00220821 addu $at, $at, $v0 
 30 | 00230821 addu $at, $at, $v1 
 31 | 00410821 addu $at, $v0, $at 
 32 | 00431021 addu $v0, $v0, $v1 
 33 | 00222021 addu $a0, $at, $v0 
 34 | 00222821 addu $a1, $at, $v0 
 35 | 00230824 and $at, $at, $v1 
 36 | 30210001 andi $at, $at, 1
 37 | 30220001 andi $v0, $at, 1
 38 | 0c000000 jal 0
 39 | 03e00008 jr $ra 
 40 | 80210000 lb $at, 0($at) 
 41 | 83c1000f lb $at, 15($fp) 
 42 | 80220000 lb $v0, 0($at) 
 43 | 83c20017 lb $v0, 23($fp) 
 44 | 90210000 lbu $at, 0($at) 
 45 | 97c10000 lhu $at, 0($fp) 
 46 | 97c10010 lhu $at, 16($fp) 
 47 | 97c10018 lhu $at, 24($fp) 
 48 | 97c10020 lhu $at, 32($fp) 
 49 | 97c10028 lhu $at, 40($fp) 
 50 | 97c10030 lhu $at, 48($fp) 
 51 | 97c10038 lhu $at, 56($fp) 
 52 | 97c10048 lhu $at, 72($fp) 
 53 | 8c210000 lw $at, 0($at) 
 54 | 8fc10008 lw $at, 8($fp) 
 55 | 8fc1000c lw $at, 12($fp) 
 56 | 8fc10010 lw $at, 16($fp) 
 57 | 8fc10014 lw $at, 20($fp) 
 58 | 8fc10018 lw $at, 24($fp) 
 59 | 8c220000 lw $v0, 0($at) 
 60 | 8c420000 lw $v0, 0($v0) 
 61 | 8fc20004 lw $v0, 4($fp) 
 62 | 8fc20008 lw $v0, 8($fp) 
 63 | 8fc20018 lw $v0, 24($fp) 
 64 | 8fc2001c lw $v0, 28($fp) 
 65 | 8c230000 lw $v1, 0($at) 
 66 | 8c430000 lw $v1, 0($v0) 
 67 | 8c630000 lw $v1, 0($v1) 
 68 | 8fc30004 lw $v1, 4($fp) 
 69 | 8fc30014 lw $v1, 20($fp) 
 70 | 8c240000 lw $a0, 0($at) 
 71 | 8fc40000 lw $a0, 0($fp) 
 72 | 8fc40024 lw $a0, 36($fp) 
 73 | 8c250000 lw $a1, 0($at) 
 74 | 8fc50018 lw $a1, 24($fp) 
 75 | 8fc5001c lw $a1, 28($fp) 
 76 | 8fc50028 lw $a1, 40($fp) 
 77 | 8fbe0008 lw $fp, 8($sp) 
 78 | 8fbe0010 lw $fp, 16($sp) 
 79 | 8fbf000c lw $ra, 12($sp) 
 80 | 8fbf0014 lw $ra, 20($sp) 
 81 | 8fbf001c lw $ra, 28($sp) 
 82 | 8fbf0054 lw $ra, 84($sp) 
 83 | 00220825 or $at, $at, $v0 
 84 | a0410000 sb $at, 0($v0) 
 85 | a3c10017 sb $at, 23($fp) 
 86 | a0220000 sb $v0, 0($at) 
 87 | a3c4000f sb $a0, 15($fp) 
 88 | a0400000 sb $zero, 0($v0) 
 89 | 28210027 slti $at, $at, 39
 90 | 2c210001 sltiu $at, $at, 1
 91 | 2c410001 sltiu $at, $v0, 1
 92 | 2c220001 sltiu $v0, $at, 1
 93 | 0002082b sltu $at, $zero, $v0 
 94 | 0022082b sltu $at, $at, $v0 
 95 | 0023082b sltu $at, $at, $v1 
 96 | 00222823 subu $a1, $at, $v0 
 97 | afc10000 sw $at, 0($fp) 
 98 | afc10004 sw $at, 4($fp) 
 99 | afc10008 sw $at, 8($fp) 
100 | afc10010 sw $at, 16($fp) 
101 | afc10014 sw $at, 20($fp) 
102 | afc10018 sw $at, 24($fp) 
103 | afc10020 sw $at, 32($fp) 
104 | ac220000 sw $v0, 0($at) 
105 | afc20004 sw $v0, 4($fp) 
106 | afc20008 sw $v0, 8($fp) 
107 | afc20010 sw $v0, 16($fp) 
108 | ac230000 sw $v1, 0($at) 
109 | afc4000c sw $a0, 12($fp) 
110 | afc50008 sw $a1, 8($fp) 
111 | afbe0008 sw $fp, 8($sp) 
112 | afbe0010 sw $fp, 16($sp) 
113 | afbe0018 sw $fp, 24($sp) 
114 | afbe0020 sw $fp, 32($sp) 
115 | afbf000c sw $ra, 12($sp) 
116 | afbf0014 sw $ra, 20($sp) 
117 | afbf001c sw $ra, 28($sp) 
118 | afbf0054 sw $ra, 84($sp) 
119 | afc00014 sw $zero, 20($fp) 
120 | afc00018 sw $zero, 24($fp) 
121 | 00220826 xor $at, $at, $v0 
122 | 00230826 xor $at, $at, $v1 
123 | 00441026 xor $v0, $v0, $a0 
124 | 00431826 xor $v1, $v0, $v1 
125 | 


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/test_data/rv32/rv32zicsr.test:
--------------------------------------------------------------------------------
 1 | 00102473 csrrs s0, fflags, zero 
 2 | 001025f3 csrrs a1, fflags, zero 
 3 | 00102673 csrrs a2, fflags, zero 
 4 | 001026f3 csrrs a3, fflags, zero 
 5 | 00102773 csrrs a4, fflags, zero 
 6 | 001027f3 csrrs a5, fflags, zero 
 7 | 00142073 csrrs zero, fflags, s0 
 8 | 00152073 csrrs zero, fflags, a0 
 9 | 00153073 csrrc zero, fflags, a0 
10 | 00159073 csrrw zero, fflags, a1 
11 | 0015a073 csrrs zero, fflags, a1 
12 | 0015b073 csrrc zero, fflags, a1 
13 | 00161073 csrrw zero, fflags, a2 
14 | 00162073 csrrs zero, fflags, a2 
15 | 00169073 csrrw zero, fflags, a3 
16 | 0016a073 csrrs zero, fflags, a3 
17 | 00171073 csrrw zero, fflags, a4 
18 | 00172073 csrrs zero, fflags, a4 
19 | 00179073 csrrw zero, fflags, a5 
20 | 00186073 csrrsi zero, fflags, 0x10 
21 | 0018a073 csrrs zero, fflags, a7 
22 | 002024f3 csrrs s1, frm, zero 
23 | 00202573 csrrs a0, frm, zero 
24 | 002025f3 csrrs a1, frm, zero 
25 | 00202673 csrrs a2, frm, zero 
26 | 002026f3 csrrs a3, frm, zero 
27 | 00202773 csrrs a4, frm, zero 
28 | 002027f3 csrrs a5, frm, zero 
29 | 00202873 csrrs a6, frm, zero 
30 | 00202973 csrrs s2, frm, zero 
31 | 00202a73 csrrs s4, frm, zero 
32 | 00202af3 csrrs s5, frm, zero 
33 | 00202b73 csrrs s6, frm, zero 
34 | 00251073 csrrw zero, frm, a0 
35 | 00259073 csrrw zero, frm, a1 
36 | 00269073 csrrw zero, frm, a3 
37 | 00279073 csrrw zero, frm, a5 
38 | 003025f3 csrrs a1, fcsr, zero 
39 | 003027f3 csrrs a5, fcsr, zero 
40 | 00331073 csrrw zero, fcsr, t1 
41 | 00351073 csrrw zero, fcsr, a0 
42 | 00371073 csrrw zero, fcsr, a4 
43 | 00379073 csrrw zero, fcsr, a5 
44 | 0037a073 csrrs zero, fcsr, a5 
45 | 0037b073 csrrc zero, fcsr, a5 
46 | 00391073 csrrw zero, fcsr, s2 
47 | 003a1073 csrrw zero, fcsr, s4 
48 | 003a9073 csrrw zero, fcsr, s5 
49 | 003b9073 csrrw zero, fcsr, s7 
50 | 003c1073 csrrw zero, fcsr, s8 
51 | 003c9073 csrrw zero, fcsr, s9 
52 | 003ff773 csrrci a4, fcsr, 0x1f 
53 | 003ff7f3 csrrci a5, fcsr, 0x1f 
54 | 003ff973 csrrci s2, fcsr, 0x1f 
55 | 003ffa73 csrrci s4, fcsr, 0x1f 
56 | 003ffaf3 csrrci s5, fcsr, 0x1f 
57 | 003ffbf3 csrrci s7, fcsr, 0x1f 
58 | 003ffc73 csrrci s8, fcsr, 0x1f 
59 | 003ffcf3 csrrci s9, fcsr, 0x1f 
60 | c0202773 csrrs a4, instret, zero 
61 | c0202af3 csrrs s5, instret, zero 
62 | c82027f3 csrrs a5, instreth, zero 
63 | c8202a73 csrrs s4, instreth, zero 
64 | 


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/test_data/rv32/rv32zknd.test:
--------------------------------------------------------------------------------
 1 | 2a600333 aes32dsi t1, zero, t1, 0x0 
 2 | 2a8a8f33 aes32dsi t5, s5, s0, 0x0 
 3 | 2a918433 aes32dsi s0, gp, s1, 0x0 
 4 | 2a960c33 aes32dsi s8, a2, s1, 0x0 
 5 | 2ad48533 aes32dsi a0, s1, a3, 0x0 
 6 | 2b5c08b3 aes32dsi a7, s8, s5, 0x0 
 7 | 2bc50333 aes32dsi t1, a0, t3, 0x0 
 8 | 2e0e8533 aes32dsmi a0, t4, zero, 0x0 
 9 | 2e5c00b3 aes32dsmi ra, s8, t0, 0x0 
10 | 2e7207b3 aes32dsmi a5, tp, t2, 0x0 
11 | 2ec90e33 aes32dsmi t3, s2, a2, 0x0 
12 | 2fd08bb3 aes32dsmi s7, ra, t4, 0x0 
13 | 6a610f33 aes32dsi t5, sp, t1, 0x1 
14 | 6ae58933 aes32dsi s2, a1, a4, 0x1 
15 | 6b1282b3 aes32dsi t0, t0, a7, 0x1 
16 | 6b358633 aes32dsi a2, a1, s3, 0x1 
17 | 6ba38a33 aes32dsi s4, t2, s10, 0x1 
18 | 6e008433 aes32dsmi s0, ra, zero, 0x1 
19 | 6e268333 aes32dsmi t1, a3, sp, 0x1 
20 | 6e6087b3 aes32dsmi a5, ra, t1, 0x1 
21 | 6e6c8eb3 aes32dsmi t4, s9, t1, 0x1 
22 | 6e7984b3 aes32dsmi s1, s3, t2, 0x1 
23 | 6ecb84b3 aes32dsmi s1, s7, a2, 0x1 
24 | 6f7588b3 aes32dsmi a7, a1, s7, 0x1 
25 | 6fc28a33 aes32dsmi s4, t0, t3, 0x1 
26 | 6fef0ab3 aes32dsmi s5, t5, t5, 0x1 
27 | aa7386b3 aes32dsi a3, t2, t2, 0x2 
28 | aa788ab3 aes32dsi s5, a7, t2, 0x2 
29 | aa8e0533 aes32dsi a0, t3, s0, 0x2 
30 | aaa883b3 aes32dsi t2, a7, a0, 0x2 
31 | aad20f33 aes32dsi t5, tp, a3, 0x2 
32 | ab1380b3 aes32dsi ra, t2, a7, 0x2 
33 | ab3c8533 aes32dsi a0, s9, s3, 0x2 
34 | ab3f0fb3 aes32dsi t6, t5, s3, 0x2 
35 | ae348f33 aes32dsmi t5, s1, gp, 0x2 
36 | ae4101b3 aes32dsmi gp, sp, tp, 0x2 
37 | aef082b3 aes32dsmi t0, ra, a5, 0x2 
38 | aef88033 aes32dsmi zero, a7, a5, 0x2 
39 | af248cb3 aes32dsmi s9, s1, s2, 0x2 
40 | af2f0333 aes32dsmi t1, t5, s2, 0x2 
41 | af5a0433 aes32dsmi s0, s4, s5, 0x2 
42 | afcf02b3 aes32dsmi t0, t5, t3, 0x2 
43 | afd00133 aes32dsmi sp, zero, t4, 0x2 
44 | ea3307b3 aes32dsi a5, t1, gp, 0x3 
45 | ea8c0f33 aes32dsi t5, s8, s0, 0x3 
46 | ea9708b3 aes32dsi a7, a4, s1, 0x3 
47 | eb1c8233 aes32dsi tp, s9, a7, 0x3 
48 | eb3c8d33 aes32dsi s10, s9, s3, 0x3 
49 | eb6206b3 aes32dsi a3, tp, s6, 0x3 
50 | eb6585b3 aes32dsi a1, a1, s6, 0x3 
51 | ee5709b3 aes32dsmi s3, a4, t0, 0x3 
52 | eeea8a33 aes32dsmi s4, s5, a4, 0x3 
53 | ef030b33 aes32dsmi s6, t1, a6, 0x3 
54 | ef7804b3 aes32dsmi s1, a6, s7, 0x3 
55 | ef8b84b3 aes32dsmi s1, s7, s8, 0x3 
56 | efbc85b3 aes32dsmi a1, s9, s11, 0x3 
57 | efdc0333 aes32dsmi t1, s8, t4, 0x3 
58 | 


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/test_data/rv32/rv32zkne.test:
--------------------------------------------------------------------------------
 1 | 22290d33 aes32esi s10, s2, sp, 0x0 
 2 | 22310db3 aes32esi s11, sp, gp, 0x0 
 3 | 22e90db3 aes32esi s11, s2, a4, 0x0 
 4 | 230b8733 aes32esi a4, s7, a6, 0x0 
 5 | 23640333 aes32esi t1, s0, s6, 0x0 
 6 | 238d0733 aes32esi a4, s10, s8, 0x0 
 7 | 23f70e33 aes32esi t3, a4, t6, 0x0 
 8 | 265387b3 aes32esmi a5, t2, t0, 0x0 
 9 | 26908a33 aes32esmi s4, ra, s1, 0x0 
10 | 269289b3 aes32esmi s3, t0, s1, 0x0 
11 | 27168c33 aes32esmi s8, a3, a7, 0x0 
12 | 27de0833 aes32esmi a6, t3, t4, 0x0 
13 | 625a8ab3 aes32esi s5, s5, t0, 0x1 
14 | 62d903b3 aes32esi t2, s2, a3, 0x1 
15 | 62ea82b3 aes32esi t0, s5, a4, 0x1 
16 | 630a01b3 aes32esi gp, s4, a6, 0x1 
17 | 636e04b3 aes32esi s1, t3, s6, 0x1 
18 | 637e88b3 aes32esi a7, t4, s7, 0x1 
19 | 63990c33 aes32esi s8, s2, s9, 0x1 
20 | 63a480b3 aes32esi ra, s1, s10, 0x1 
21 | 63eb8b33 aes32esi s6, s7, t5, 0x1 
22 | 66188bb3 aes32esmi s7, a7, ra, 0x1 
23 | 66958cb3 aes32esmi s9, a1, s1, 0x1 
24 | 66a70cb3 aes32esmi s9, a4, a0, 0x1 
25 | 66d983b3 aes32esmi t2, s3, a3, 0x1 
26 | 66e48ab3 aes32esmi s5, s1, a4, 0x1 
27 | 675502b3 aes32esmi t0, a0, s5, 0x1 
28 | 678603b3 aes32esmi t2, a2, s8, 0x1 
29 | 67c601b3 aes32esmi gp, a2, t3, 0x1 
30 | a2530e33 aes32esi t3, t1, t0, 0x2 
31 | a29d8d33 aes32esi s10, s11, s1, 0x2 
32 | a29f8133 aes32esi sp, t6, s1, 0x2 
33 | a3828433 aes32esi s0, t0, s8, 0x2 
34 | a3e189b3 aes32esi s3, gp, t5, 0x2 
35 | a6000933 aes32esmi s2, zero, zero, 0x2 
36 | a60f08b3 aes32esmi a7, t5, zero, 0x2 
37 | a61387b3 aes32esmi a5, t2, ra, 0x2 
38 | a6340cb3 aes32esmi s9, s0, gp, 0x2 
39 | a64a8133 aes32esmi sp, s5, tp, 0x2 
40 | a65e8ab3 aes32esmi s5, t4, t0, 0x2 
41 | a6cb8a33 aes32esmi s4, s7, a2, 0x2 
42 | e2388e33 aes32esi t3, a7, gp, 0x3 
43 | e2710133 aes32esi sp, sp, t2, 0x3 
44 | e27f8733 aes32esi a4, t6, t2, 0x3 
45 | e2940f33 aes32esi t5, s0, s1, 0x3 
46 | e2a700b3 aes32esi ra, a4, a0, 0x3 
47 | e3d707b3 aes32esi a5, a4, t4, 0x3 
48 | e6070033 aes32esmi zero, a4, zero, 0x3 
49 | e6178533 aes32esmi a0, a5, ra, 0x3 
50 | e65e85b3 aes32esmi a1, t4, t0, 0x3 
51 | e67104b3 aes32esmi s1, sp, t2, 0x3 
52 | e67384b3 aes32esmi s1, t2, t2, 0x3 
53 | e71e8eb3 aes32esmi t4, t4, a7, 0x3 
54 | e74001b3 aes32esmi gp, zero, s4, 0x3 
55 | e7a18333 aes32esmi t1, gp, s10, 0x3 
56 | e7e88033 aes32esmi zero, a7, t5, 0x3 
57 | e7ea8f33 aes32esmi t5, s5, t5, 0x3 
58 | 


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/test_data/rv64/rv64zcd.test:
--------------------------------------------------------------------------------
  1 | 2006 c.fldsp ft0, 0x40(sp) 
  2 | 204a c.fldsp ft0, 0x90(sp) 
  3 | 2138 c.fld fa4, 0x40(a0) 
  4 | 2140 c.fld fs0, 0x80(a0) 
  5 | 2216 c.fldsp ft4, 0x140(sp) 
  6 | 229c c.fld fa5, 0x0(a3) 
  7 | 22d0 c.fld fa2, 0x80(a3) 
  8 | 22e8 c.fld fa0, 0xc0(a3) 
  9 | 2388 c.fld fa0, 0x0(a5) 
 10 | 23c0 c.fld fs0, 0x80(a5) 
 11 | 2432 c.fldsp fs0, 0x108(sp) 
 12 | 2554 c.fld fa3, 0x88(a0) 
 13 | 25ae c.fldsp fa1, 0xc8(sp) 
 14 | 260a c.fldsp fa2, 0x80(sp) 
 15 | 264a c.fldsp fa2, 0x90(sp) 
 16 | 266a c.fldsp fa2, 0x98(sp) 
 17 | 2936 c.fldsp fs2, 0x148(sp) 
 18 | 29b2 c.fldsp fs3, 0x108(sp) 
 19 | 2a50 c.fld fa2, 0x90(a2) 
 20 | 2c82 c.fldsp fs9, 0x0(sp) 
 21 | 2c9c c.fld fa5, 0x18(s1) 
 22 | 2cb0 c.fld fa2, 0x58(s1) 
 23 | 2d2a c.fldsp fs10, 0x88(sp) 
 24 | 2d92 c.fldsp fs11, 0x100(sp) 
 25 | 2da8 c.fld fa0, 0x58(a1) 
 26 | 2db4 c.fld fa3, 0x58(a1) 
 27 | 2fae c.fldsp ft11, 0xc8(sp) 
 28 | 315e c.fldsp ft2, 0x1f0(sp) 
 29 | 31d2 c.fldsp ft3, 0x130(sp) 
 30 | 322e c.fldsp ft4, 0xe8(sp) 
 31 | 337a c.fldsp ft6, 0x1b8(sp) 
 32 | 33d6 c.fldsp ft7, 0x170(sp) 
 33 | 33f2 c.fldsp ft7, 0x138(sp) 
 34 | 33fc c.fld fa5, 0xe0(a5) 
 35 | 340a c.fldsp fs0, 0xa0(sp) 
 36 | 3492 c.fldsp fs1, 0x120(sp) 
 37 | 3498 c.fld fa4, 0x28(s1) 
 38 | 3620 c.fld fs0, 0x68(a2) 
 39 | 364e c.fldsp fa2, 0xf0(sp) 
 40 | 3678 c.fld fa4, 0xe8(a2) 
 41 | 37b0 c.fld fa2, 0x68(a5) 
 42 | 381a c.fldsp fa6, 0x1a0(sp) 
 43 | 39b8 c.fld fa4, 0x70(a1) 
 44 | 3a90 c.fld fa2, 0x30(a3) 
 45 | 3ace c.fldsp fs5, 0xf0(sp) 
 46 | 3c32 c.fldsp fs8, 0x128(sp) 
 47 | 3cba c.fldsp fs9, 0x1a8(sp) 
 48 | 3cd4 c.fld fa3, 0xb8(s1) 
 49 | 3de0 c.fld fs0, 0xf8(a1) 
 50 | 3dea c.fldsp fs11, 0xb8(sp) 
 51 | 3dec c.fld fa1, 0xf8(a1) 
 52 | 3df4 c.fld fa3, 0xf8(a1) 
 53 | 3e36 c.fldsp ft8, 0x168(sp) 
 54 | 3f0c c.fld fa1, 0x38(a4) 
 55 | 3f7e c.fldsp ft10, 0x1f8(sp) 
 56 | 3fbc c.fld fa5, 0x78(a5) 
 57 | a02e c.fsdsp fa1, 0x0(sp) 
 58 | a0e6 c.fsdsp fs9, 0x40(sp) 
 59 | a142 c.fsdsp fa6, 0x80(sp) 
 60 | a310 c.fsd fa2, 0x0(a4) 
 61 | a3ae c.fsdsp fa1, 0x1c0(sp) 
 62 | a3ec c.fsd fa1, 0xc0(a5) 
 63 | a41a c.fsdsp ft6, 0x8(sp) 
 64 | a474 c.fsd fa3, 0xc8(s0) 
 65 | a476 c.fsdsp ft9, 0x8(sp) 
 66 | a57a c.fsdsp ft10, 0x88(sp) 
 67 | a590 c.fsd fa2, 0x8(a1) 
 68 | a5ae c.fsdsp fa1, 0xc8(sp) 
 69 | a644 c.fsd fs1, 0x88(a2) 
 70 | a6d4 c.fsd fa3, 0x88(a3) 
 71 | a702 c.fsdsp ft0, 0x188(sp) 
 72 | a7e4 c.fsd fs1, 0xc8(a5) 
 73 | a92c c.fsd fa1, 0x50(a0) 
 74 | a94e c.fsdsp fs3, 0x90(sp) 
 75 | aa08 c.fsd fa0, 0x10(a2) 
 76 | aa70 c.fsd fa2, 0xd0(a2) 
 77 | abae c.fsdsp fa1, 0x1d0(sp) 
 78 | abb6 c.fsdsp fa3, 0x1d0(sp) 
 79 | ac56 c.fsdsp fs5, 0x18(sp) 
 80 | ac5a c.fsdsp fs6, 0x18(sp) 
 81 | ad08 c.fsd fa0, 0x18(a0) 
 82 | ad54 c.fsd fa3, 0x98(a0) 
 83 | ada8 c.fsd fa0, 0x58(a1) 
 84 | ade4 c.fsd fs1, 0xd8(a1) 
 85 | ae84 c.fsd fs1, 0x18(a3) 
 86 | b11c c.fsd fa5, 0x20(a0) 
 87 | b1da c.fsdsp fs6, 0xe0(sp) 
 88 | b2d2 c.fsdsp fs4, 0x160(sp) 
 89 | b330 c.fsd fa2, 0x60(a4) 
 90 | b3b6 c.fsdsp fa3, 0x1e0(sp) 
 91 | b438 c.fsd fa4, 0x68(s0) 
 92 | b5b4 c.fsd fa3, 0x68(a1) 
 93 | b620 c.fsd fs0, 0x68(a2) 
 94 | b686 c.fsdsp ft1, 0x168(sp) 
 95 | b6c4 c.fsd fs1, 0xa8(a3) 
 96 | b736 c.fsdsp fa3, 0x1a8(sp) 
 97 | b76e c.fsdsp fs11, 0x1a8(sp) 
 98 | b87c c.fsd fa5, 0xf0(s0) 
 99 | b8bc c.fsd fa5, 0x70(s1) 
100 | b92e c.fsdsp fa1, 0xb0(sp) 
101 | b938 c.fsd fa4, 0x70(a0) 
102 | b9b6 c.fsdsp fa3, 0xf0(sp) 
103 | ba48 c.fsd fa0, 0xb0(a2) 
104 | bb3c c.fsd fa5, 0x70(a4) 
105 | bc18 c.fsd fa4, 0x38(s0) 
106 | bc94 c.fsd fa3, 0x38(s1) 
107 | bd36 c.fsdsp fa3, 0xb8(sp) 
108 | bd50 c.fsd fa2, 0xb8(a0) 
109 | bd56 c.fsdsp fs5, 0xb8(sp) 
110 | bf3c c.fsd fa5, 0x78(a4) 
111 | 


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/test_data/rv64/rv64zicond.test:
--------------------------------------------------------------------------------
 1 | 0e067c33 czero.nez s8, a2, zero 
 2 | 0e09d3b3 czero.eqz t2, s3, zero 
 3 | 0e0e7433 czero.nez s0, t3, zero 
 4 | 0e12f033 czero.nez zero, t0, ra 
 5 | 0e14ff33 czero.nez t5, s1, ra 
 6 | 0e1bf833 czero.nez a6, s7, ra 
 7 | 0e2276b3 czero.nez a3, tp, sp 
 8 | 0e275833 czero.eqz a6, a4, sp 
 9 | 0e2edc33 czero.eqz s8, t4, sp 
10 | 0e2fdfb3 czero.eqz t6, t6, sp 
11 | 0e335333 czero.eqz t1, t1, gp 
12 | 0e3affb3 czero.nez t6, s5, gp 
13 | 0e3f7833 czero.nez a6, t5, gp 
14 | 0e41d133 czero.eqz sp, gp, tp 
15 | 0e41f3b3 czero.nez t2, gp, tp 
16 | 0e4f52b3 czero.eqz t0, t5, tp 
17 | 0e50d533 czero.eqz a0, ra, t0 
18 | 0e53f1b3 czero.nez gp, t2, t0 
19 | 0e73d2b3 czero.eqz t0, t2, t2 
20 | 0e94d333 czero.eqz t1, s1, s1 
21 | 0e95d5b3 czero.eqz a1, a1, s1 
22 | 0e99ddb3 czero.eqz s11, s3, s1 
23 | 0e9e5633 czero.eqz a2, t3, s1 
24 | 0ea3f133 czero.nez sp, t2, a0 
25 | 0ea7deb3 czero.eqz t4, a5, a0 
26 | 0ec1fd33 czero.nez s10, gp, a2 
27 | 0ec859b3 czero.eqz s3, a6, a2 
28 | 0ecf7933 czero.nez s2, t5, a2 
29 | 0ee75e33 czero.eqz t3, a4, a4 
30 | 0eebfd33 czero.nez s10, s7, a4 
31 | 0f0edfb3 czero.eqz t6, t4, a6 
32 | 0f14f033 czero.nez zero, s1, a7 
33 | 0f23de33 czero.eqz t3, t2, s2 
34 | 0f25f8b3 czero.nez a7, a1, s2 
35 | 0f27dcb3 czero.eqz s9, a5, s2 
36 | 0f2a7033 czero.nez zero, s4, s2 
37 | 0f5555b3 czero.eqz a1, a0, s5 
38 | 0f6d7033 czero.nez zero, s10, s6 
39 | 0f7fd0b3 czero.eqz ra, t6, s7 
40 | 0f9077b3 czero.nez a5, zero, s9 
41 | 0f94dbb3 czero.eqz s7, s1, s9 
42 | 0fa05c33 czero.eqz s8, zero, s10 
43 | 0fa152b3 czero.eqz t0, sp, s10 
44 | 0fa659b3 czero.eqz s3, a2, s10 
45 | 0faa7733 czero.nez a4, s4, s10 
46 | 0fb37a33 czero.nez s4, t1, s11 
47 | 0fb3ff33 czero.nez t5, t2, s11 
48 | 0fb4d533 czero.eqz a0, s1, s11 
49 | 0fc37733 czero.nez a4, t1, t3 
50 | 0fc7f133 czero.nez sp, a5, t3 
51 | 0fcbf2b3 czero.nez t0, s7, t3 
52 | 0fdb7533 czero.nez a0, s6, t4 
53 | 0fdbf4b3 czero.nez s1, s7, t4 
54 | 0fe558b3 czero.eqz a7, a0, t5 
55 | 0ff6f133 czero.nez sp, a3, t6 
56 | 0ffbf233 czero.nez tp, s7, t6 
57 | 0fffff33 czero.nez t5, t6, t6 
58 | 


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/test_data/rv64/rv64zknd.test:
--------------------------------------------------------------------------------
  1 | 30001f13 aes64im t5, zero 
  2 | 30009893 aes64im a7, ra 
  3 | 30011193 aes64im gp, sp 
  4 | 30011993 aes64im s3, sp 
  5 | 30021893 aes64im a7, tp 
  6 | 30021e93 aes64im t4, tp 
  7 | 30039f13 aes64im t5, t2 
  8 | 30049113 aes64im sp, s1 
  9 | 30049393 aes64im t2, s1 
 10 | 30059f13 aes64im t5, a1 
 11 | 30061693 aes64im a3, a2 
 12 | 30061a93 aes64im s5, a2 
 13 | 30061d93 aes64im s11, a2 
 14 | 30061f93 aes64im t6, a2 
 15 | 30069c13 aes64im s8, a3 
 16 | 30071793 aes64im a5, a4 
 17 | 30071813 aes64im a6, a4 
 18 | 30081b93 aes64im s7, a6 
 19 | 30089b13 aes64im s6, a7 
 20 | 30089b93 aes64im s7, a7 
 21 | 300a9313 aes64im t1, s5 
 22 | 300a9813 aes64im a6, s5 
 23 | 300c1b13 aes64im s6, s8 
 24 | 300c9293 aes64im t0, s9 
 25 | 300c9513 aes64im a0, s9 
 26 | 300d1313 aes64im t1, s10 
 27 | 300d1413 aes64im s0, s10 
 28 | 300f1513 aes64im a0, t5 
 29 | 300f9093 aes64im ra, t6 
 30 | 300f9293 aes64im t0, t6 
 31 | 31021293 aes64ks1i t0, tp, 0x0 
 32 | 31031e93 aes64ks1i t4, t1, 0x0 
 33 | 31051d13 aes64ks1i s10, a0, 0x0 
 34 | 31099993 aes64ks1i s3, s3, 0x0 
 35 | 310b9813 aes64ks1i a6, s7, 0x0 
 36 | 31101793 aes64ks1i a5, zero, 0x1 
 37 | 311c9913 aes64ks1i s2, s9, 0x1 
 38 | 311f1b93 aes64ks1i s7, t5, 0x1 
 39 | 31201c93 aes64ks1i s9, zero, 0x2 
 40 | 31349313 aes64ks1i t1, s1, 0x3 
 41 | 31441f93 aes64ks1i t6, s0, 0x4 
 42 | 31581093 aes64ks1i ra, a6, 0x5 
 43 | 315b1b93 aes64ks1i s7, s6, 0x5 
 44 | 315e9b13 aes64ks1i s6, t4, 0x5 
 45 | 31609313 aes64ks1i t1, ra, 0x6 
 46 | 31611e93 aes64ks1i t4, sp, 0x6 
 47 | 31661313 aes64ks1i t1, a2, 0x6 
 48 | 317a9913 aes64ks1i s2, s5, 0x7 
 49 | 31899a93 aes64ks1i s5, s3, 0x8 
 50 | 318f9513 aes64ks1i a0, t6, 0x8 
 51 | 31a61d93 aes64ks1i s11, a2, 0xa 
 52 | 31b09413 aes64ks1i s0, ra, 0xb 
 53 | 31b21293 aes64ks1i t0, tp, 0xb 
 54 | 31cb1993 aes64ks1i s3, s6, 0xc 
 55 | 31ce1493 aes64ks1i s1, t3, 0xc 
 56 | 31e01f13 aes64ks1i t5, zero, 0xe 
 57 | 31f09a93 aes64ks1i s5, ra, 0xf 
 58 | 31f21093 aes64ks1i ra, tp, 0xf 
 59 | 31f51813 aes64ks1i a6, a0, 0xf 
 60 | 31f81993 aes64ks1i s3, a6, 0xf 
 61 | 3a4d8cb3 aes64ds s9, s11, tp 
 62 | 3a518833 aes64ds a6, gp, t0 
 63 | 3a6a07b3 aes64ds a5, s4, t1 
 64 | 3a9706b3 aes64ds a3, a4, s1 
 65 | 3abe8933 aes64ds s2, t4, a1 
 66 | 3ad50033 aes64ds zero, a0, a3 
 67 | 3aee82b3 aes64ds t0, t4, a4 
 68 | 3aee8733 aes64ds a4, t4, a4 
 69 | 3b0c86b3 aes64ds a3, s9, a6 
 70 | 3b2801b3 aes64ds gp, a6, s2 
 71 | 3b390d33 aes64ds s10, s2, s3 
 72 | 3b4103b3 aes64ds t2, sp, s4 
 73 | 3b448eb3 aes64ds t4, s1, s4 
 74 | 3b460cb3 aes64ds s9, a2, s4 
 75 | 3b470db3 aes64ds s11, a4, s4 
 76 | 3b4f8b33 aes64ds s6, t6, s4 
 77 | 3b5f0d33 aes64ds s10, t5, s5 
 78 | 3b6383b3 aes64ds t2, t2, s6 
 79 | 3b7605b3 aes64ds a1, a2, s7 
 80 | 3b7a07b3 aes64ds a5, s4, s7 
 81 | 3b920b33 aes64ds s6, tp, s9 
 82 | 3bac09b3 aes64ds s3, s8, s10 
 83 | 3bb88f33 aes64ds t5, a7, s11 
 84 | 3bdc09b3 aes64ds s3, s8, t4 
 85 | 3bed0cb3 aes64ds s9, s10, t5 
 86 | 3bf50eb3 aes64ds t4, a0, t6 
 87 | 3bf60433 aes64ds s0, a2, t6 
 88 | 3e490eb3 aes64dsm t4, s2, tp 
 89 | 3e4c0bb3 aes64dsm s7, s8, tp 
 90 | 3e4d0733 aes64dsm a4, s10, tp 
 91 | 3e4e8c33 aes64dsm s8, t4, tp 
 92 | 3e5d8633 aes64dsm a2, s11, t0 
 93 | 3e8d8db3 aes64dsm s11, s11, s0 
 94 | 3e9f0ab3 aes64dsm s5, t5, s1 
 95 | 3eb680b3 aes64dsm ra, a3, a1 
 96 | 3ef304b3 aes64dsm s1, t1, a5 
 97 | 3ef60333 aes64dsm t1, a2, a5 
 98 | 3efd85b3 aes64dsm a1, s11, a5 
 99 | 3f200c33 aes64dsm s8, zero, s2 
100 | 3f2a01b3 aes64dsm gp, s4, s2 
101 | 3f3001b3 aes64dsm gp, zero, s3 
102 | 3f308333 aes64dsm t1, ra, s3 
103 | 3f3c0cb3 aes64dsm s9, s8, s3 
104 | 3f560f33 aes64dsm t5, a2, s5 
105 | 3f650833 aes64dsm a6, a0, s6 
106 | 3f798bb3 aes64dsm s7, s3, s7 
107 | 3f7d8033 aes64dsm zero, s11, s7 
108 | 3f838cb3 aes64dsm s9, t2, s8 
109 | 3fad0933 aes64dsm s2, s10, s10 
110 | 3fb60e33 aes64dsm t3, a2, s11 
111 | 3fbb87b3 aes64dsm a5, s7, s11 
112 | 3fc986b3 aes64dsm a3, s3, t3 
113 | 3fce0d33 aes64dsm s10, t3, t3 
114 | 3fd40233 aes64dsm tp, s0, t4 
115 | 3fde8a33 aes64dsm s4, t4, t4 
116 | 3ff00133 aes64dsm sp, zero, t6 
117 | 3ffd85b3 aes64dsm a1, s11, t6 
118 | 7e058233 aes64ks2 tp, a1, zero 
119 | 7e1b8b33 aes64ks2 s6, s7, ra 
120 | 7e2a8733 aes64ks2 a4, s5, sp 
121 | 7e2d0633 aes64ks2 a2, s10, sp 
122 | 7e4d04b3 aes64ks2 s1, s10, tp 
123 | 7e6c8233 aes64ks2 tp, s9, t1 
124 | 7e740cb3 aes64ks2 s9, s0, t2 
125 | 7e7e88b3 aes64ks2 a7, t4, t2 
126 | 7ea08633 aes64ks2 a2, ra, a0 
127 | 7eba8533 aes64ks2 a0, s5, a1 
128 | 7ec38333 aes64ks2 t1, t2, a2 
129 | 7edb0bb3 aes64ks2 s7, s6, a3 
130 | 7edf07b3 aes64ks2 a5, t5, a3 
131 | 7ef90233 aes64ks2 tp, s2, a5 
132 | 7f128933 aes64ks2 s2, t0, a7 
133 | 7f168233 aes64ks2 tp, a3, a7 
134 | 7f190633 aes64ks2 a2, s2, a7 
135 | 7f2b06b3 aes64ks2 a3, s6, s2 
136 | 7f2b8733 aes64ks2 a4, s7, s2 
137 | 7f400533 aes64ks2 a0, zero, s4 
138 | 7f438033 aes64ks2 zero, t2, s4 
139 | 7f600a33 aes64ks2 s4, zero, s6 
140 | 7f668633 aes64ks2 a2, a3, s6 
141 | 7f6e8033 aes64ks2 zero, t4, s6 
142 | 7f8c0a33 aes64ks2 s4, s8, s8 
143 | 7f8f8933 aes64ks2 s2, t6, s8 
144 | 7fcb01b3 aes64ks2 gp, s6, t3 
145 | 7fd989b3 aes64ks2 s3, s3, t4 
146 | 7fe10533 aes64ks2 a0, sp, t5 
147 | 7fe78ab3 aes64ks2 s5, a5, t5 
148 | 


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/test_data/rv64/rv64zkne.test:
--------------------------------------------------------------------------------
  1 | 310d1793 aes64ks1i a5, s10, 0x0 
  2 | 310e1513 aes64ks1i a0, t3, 0x0 
  3 | 31161f13 aes64ks1i t5, a2, 0x1 
  4 | 31179993 aes64ks1i s3, a5, 0x1 
  5 | 31421d93 aes64ks1i s11, tp, 0x4 
  6 | 31441693 aes64ks1i a3, s0, 0x4 
  7 | 31471913 aes64ks1i s2, a4, 0x4 
  8 | 31489813 aes64ks1i a6, a7, 0x4 
  9 | 31589293 aes64ks1i t0, a7, 0x5 
 10 | 31671293 aes64ks1i t0, a4, 0x6 
 11 | 31729f13 aes64ks1i t5, t0, 0x7 
 12 | 31931513 aes64ks1i a0, t1, 0x9 
 13 | 31951513 aes64ks1i a0, a0, 0x9 
 14 | 319a1693 aes64ks1i a3, s4, 0x9 
 15 | 31a29713 aes64ks1i a4, t0, 0xa 
 16 | 31a39813 aes64ks1i a6, t2, 0xa 
 17 | 31ab1c93 aes64ks1i s9, s6, 0xa 
 18 | 31ab9793 aes64ks1i a5, s7, 0xa 
 19 | 31b49b93 aes64ks1i s7, s1, 0xb 
 20 | 31b71713 aes64ks1i a4, a4, 0xb 
 21 | 31bc1793 aes64ks1i a5, s8, 0xb 
 22 | 31cf1093 aes64ks1i ra, t5, 0xc 
 23 | 31cf1393 aes64ks1i t2, t5, 0xc 
 24 | 31d01e13 aes64ks1i t3, zero, 0xd 
 25 | 31d39593 aes64ks1i a1, t2, 0xd 
 26 | 31d81413 aes64ks1i s0, a6, 0xd 
 27 | 31d89b93 aes64ks1i s7, a7, 0xd 
 28 | 31e01613 aes64ks1i a2, zero, 0xe 
 29 | 31f99593 aes64ks1i a1, s3, 0xf 
 30 | 31fc1493 aes64ks1i s1, s8, 0xf 
 31 | 320a8d33 aes64es s10, s5, zero 
 32 | 32148cb3 aes64es s9, s1, ra 
 33 | 32308c33 aes64es s8, ra, gp 
 34 | 324c88b3 aes64es a7, s9, tp 
 35 | 32558c33 aes64es s8, a1, t0 
 36 | 32588933 aes64es s2, a7, t0 
 37 | 325c89b3 aes64es s3, s9, t0 
 38 | 327984b3 aes64es s1, s3, t2 
 39 | 32810433 aes64es s0, sp, s0 
 40 | 32820233 aes64es tp, tp, s0 
 41 | 328500b3 aes64es ra, a0, s0 
 42 | 32920333 aes64es t1, tp, s1 
 43 | 32a400b3 aes64es ra, s0, a0 
 44 | 32bd8b33 aes64es s6, s11, a1 
 45 | 32c882b3 aes64es t0, a7, a2 
 46 | 32ca07b3 aes64es a5, s4, a2 
 47 | 32cc8433 aes64es s0, s9, a2 
 48 | 32d20a33 aes64es s4, tp, a3 
 49 | 33370fb3 aes64es t6, a4, s3 
 50 | 334287b3 aes64es a5, t0, s4 
 51 | 33478633 aes64es a2, a5, s4 
 52 | 335507b3 aes64es a5, a0, s5 
 53 | 336a0133 aes64es sp, s4, s6 
 54 | 337e0333 aes64es t1, t3, s7 
 55 | 33b408b3 aes64es a7, s0, s11 
 56 | 33b68a33 aes64es s4, a3, s11 
 57 | 33ce02b3 aes64es t0, t3, t3 
 58 | 36490ab3 aes64esm s5, s2, tp 
 59 | 364f8933 aes64esm s2, t6, tp 
 60 | 36760233 aes64esm tp, a2, t2 
 61 | 367e01b3 aes64esm gp, t3, t2 
 62 | 367e8233 aes64esm tp, t4, t2 
 63 | 369009b3 aes64esm s3, zero, s1 
 64 | 36948c33 aes64esm s8, s1, s1 
 65 | 369c8433 aes64esm s0, s9, s1 
 66 | 36c50cb3 aes64esm s9, a0, a2 
 67 | 36e080b3 aes64esm ra, ra, a4 
 68 | 37050733 aes64esm a4, a0, a6 
 69 | 370f88b3 aes64esm a7, t6, a6 
 70 | 370f8eb3 aes64esm t4, t6, a6 
 71 | 37128db3 aes64esm s11, t0, a7 
 72 | 37290333 aes64esm t1, s2, s2 
 73 | 37318c33 aes64esm s8, gp, s3 
 74 | 37350633 aes64esm a2, a0, s3 
 75 | 37408ab3 aes64esm s5, ra, s4 
 76 | 374a00b3 aes64esm ra, s4, s4 
 77 | 374d06b3 aes64esm a3, s10, s4 
 78 | 375085b3 aes64esm a1, ra, s5 
 79 | 376a8a33 aes64esm s4, s5, s6 
 80 | 37738f33 aes64esm t5, t2, s7 
 81 | 37758033 aes64esm zero, a1, s7 
 82 | 377882b3 aes64esm t0, a7, s7 
 83 | 37818033 aes64esm zero, gp, s8 
 84 | 37bf89b3 aes64esm s3, t6, s11 
 85 | 37d58933 aes64esm s2, a1, t4 
 86 | 37f40133 aes64esm sp, s0, t6 
 87 | 37fd8f33 aes64esm t5, s11, t6 
 88 | 7e048433 aes64ks2 s0, s1, zero 
 89 | 7e0c0333 aes64ks2 t1, s8, zero 
 90 | 7e4480b3 aes64ks2 ra, s1, tp 
 91 | 7e568333 aes64ks2 t1, a3, t0 
 92 | 7e7f0ab3 aes64ks2 s5, t5, t2 
 93 | 7e830cb3 aes64ks2 s9, t1, s0 
 94 | 7e928ab3 aes64ks2 s5, t0, s1 
 95 | 7eb68733 aes64ks2 a4, a3, a1 
 96 | 7ec60733 aes64ks2 a4, a2, a2 
 97 | 7ed508b3 aes64ks2 a7, a0, a3 
 98 | 7eeb0cb3 aes64ks2 s9, s6, a4 
 99 | 7f270b33 aes64ks2 s6, a4, s2 
100 | 7f4100b3 aes64ks2 ra, sp, s4 
101 | 7f4301b3 aes64ks2 gp, t1, s4 
102 | 7f460333 aes64ks2 t1, a2, s4 
103 | 7f4a0bb3 aes64ks2 s7, s4, s4 
104 | 7f4f0233 aes64ks2 tp, t5, s4 
105 | 7f5287b3 aes64ks2 a5, t0, s5 
106 | 7f5a0cb3 aes64ks2 s9, s4, s5 
107 | 7f738033 aes64ks2 zero, t2, s7 
108 | 7f8808b3 aes64ks2 a7, a6, s8 
109 | 7f988fb3 aes64ks2 t6, a7, s9 
110 | 7fb78fb3 aes64ks2 t6, a5, s11 
111 | 7fbc8533 aes64ks2 a0, s9, s11 
112 | 7fbd0bb3 aes64ks2 s7, s10, s11 
113 | 7fd60733 aes64ks2 a4, a2, t4 
114 | 7fd78c33 aes64ks2 s8, a5, t4 
115 | 7fdd8133 aes64ks2 sp, s11, t4 
116 | 7fe987b3 aes64ks2 a5, s3, t5 
117 | 7ff98233 aes64ks2 tp, s3, t6 
118 | 


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/test_data/rv64/rvzawrs.test:
--------------------------------------------------------------------------------
1 | 00d00073 wrs.nto 
2 | 01d00073 wrs.sto 
3 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzbc.test:
--------------------------------------------------------------------------------
 1 | 0a12adb3 clmulr s11, t0, ra 
 2 | 0a183a33 clmulh s4, a6, ra 
 3 | 0a1d2e33 clmulr t3, s10, ra 
 4 | 0a212a33 clmulr s4, sp, sp 
 5 | 0a222533 clmulr a0, tp, sp 
 6 | 0a289fb3 clmul t6, a7, sp 
 7 | 0a32acb3 clmulr s9, t0, gp 
 8 | 0a3339b3 clmulh s3, t1, gp 
 9 | 0a369033 clmul zero, a3, gp 
10 | 0a3ebbb3 clmulh s7, t4, gp 
11 | 0a4533b3 clmulh t2, a0, tp 
12 | 0a4bb5b3 clmulh a1, s7, tp 
13 | 0a4c11b3 clmul gp, s8, tp 
14 | 0a553f33 clmulh t5, a0, t0 
15 | 0a559033 clmul zero, a1, t0 
16 | 0a562cb3 clmulr s9, a2, t0 
17 | 0a5796b3 clmul a3, a5, t0 
18 | 0a5bb4b3 clmulh s1, s7, t0 
19 | 0a5f94b3 clmul s1, t6, t0 
20 | 0a601bb3 clmul s7, zero, t1 
21 | 0a6bafb3 clmulr t6, s7, t1 
22 | 0a702933 clmulr s2, zero, t2 
23 | 0a743933 clmulh s2, s0, t2 
24 | 0a7636b3 clmulh a3, a2, t2 
25 | 0a791fb3 clmul t6, s2, t2 
26 | 0a80b7b3 clmulh a5, ra, s0 
27 | 0a83a133 clmulr sp, t2, s0 
28 | 0a923cb3 clmulh s9, tp, s1 
29 | 0a9f94b3 clmul s1, t6, s1 
30 | 0aa2a0b3 clmulr ra, t0, a0 
31 | 0ab83733 clmulh a4, a6, a1 
32 | 0ac8beb3 clmulh t4, a7, a2 
33 | 0ac929b3 clmulr s3, s2, a2 
34 | 0ac9ad33 clmulr s10, s3, a2 
35 | 0ad21c33 clmul s8, tp, a3 
36 | 0ad23f33 clmulh t5, tp, a3 
37 | 0ad5ba33 clmulh s4, a1, a3 
38 | 0adabdb3 clmulh s11, s5, a3 
39 | 0ae6a6b3 clmulr a3, a3, a4 
40 | 0ae91033 clmul zero, s2, a4 
41 | 0ae9a733 clmulr a4, s3, a4 
42 | 0aef9c33 clmul s8, t6, a4 
43 | 0af324b3 clmulr s1, t1, a5 
44 | 0af798b3 clmul a7, a5, a5 
45 | 0af83eb3 clmulh t4, a6, a5 
46 | 0afd2733 clmulr a4, s10, a5 
47 | 0afd36b3 clmulh a3, s10, a5 
48 | 0affad33 clmulr s10, t6, a5 
49 | 0b029033 clmul zero, t0, a6 
50 | 0b05b3b3 clmulh t2, a1, a6 
51 | 0b091033 clmul zero, s2, a6 
52 | 0b0d9633 clmul a2, s11, a6 
53 | 0b0daf33 clmulr t5, s11, a6 
54 | 0b11b8b3 clmulh a7, gp, a7 
55 | 0b2123b3 clmulr t2, sp, s2 
56 | 0b2621b3 clmulr gp, a2, s2 
57 | 0b27a8b3 clmulr a7, a5, s2 
58 | 0b2992b3 clmul t0, s3, s2 
59 | 0b2b2eb3 clmulr t4, s6, s2 
60 | 0b2ea2b3 clmulr t0, t4, s2 
61 | 0b3a9d33 clmul s10, s5, s3 
62 | 0b3c2033 clmulr zero, s8, s3 
63 | 0b619a33 clmul s4, gp, s6 
64 | 0b703833 clmulh a6, zero, s7 
65 | 0b74acb3 clmulr s9, s1, s7 
66 | 0b78ae33 clmulr t3, a7, s7 
67 | 0b7c33b3 clmulh t2, s8, s7 
68 | 0b8926b3 clmulr a3, s2, s8 
69 | 0b8eb933 clmulh s2, t4, s8 
70 | 0b921cb3 clmul s9, tp, s9 
71 | 0b9d9833 clmul a6, s11, s9 
72 | 0b9e3833 clmulh a6, t3, s9 
73 | 0bb337b3 clmulh a5, t1, s11 
74 | 0bb418b3 clmul a7, s0, s11 
75 | 0bb53b33 clmulh s6, a0, s11 
76 | 0bb8ae33 clmulr t3, a7, s11 
77 | 0bbb93b3 clmul t2, s7, s11 
78 | 0bbc10b3 clmul ra, s8, s11 
79 | 0bc338b3 clmulh a7, t1, t3 
80 | 0bc8a333 clmulr t1, a7, t3 
81 | 0bd3b933 clmulh s2, t2, t4 
82 | 0bdb36b3 clmulh a3, s6, t4 
83 | 0be69e33 clmul t3, a3, t5 
84 | 0be795b3 clmul a1, a5, t5 
85 | 0bf62eb3 clmulr t4, a2, t6 
86 | 0bf994b3 clmul s1, s3, t6 
87 | 0bf9bfb3 clmulh t6, s3, t6 
88 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzbkc.test:
--------------------------------------------------------------------------------
 1 | 0a0311b3 clmul gp, t1, zero 
 2 | 0a20bfb3 clmulh t6, ra, sp 
 3 | 0a289633 clmul a2, a7, sp 
 4 | 0a2f3a33 clmulh s4, t5, sp 
 5 | 0a341233 clmul tp, s0, gp 
 6 | 0a429ab3 clmul s5, t0, tp 
 7 | 0a451b33 clmul s6, a0, tp 
 8 | 0a45b233 clmulh tp, a1, tp 
 9 | 0a4a9f33 clmul t5, s5, tp 
10 | 0a5593b3 clmul t2, a1, t0 
11 | 0a5ab333 clmulh t1, s5, t0 
12 | 0a5c1d33 clmul s10, s8, t0 
13 | 0a7034b3 clmulh s1, zero, t2 
14 | 0a749a33 clmul s4, s1, t2 
15 | 0a75bf33 clmulh t5, a1, t2 
16 | 0a763eb3 clmulh t4, a2, t2 
17 | 0a8595b3 clmul a1, a1, s0 
18 | 0a961d33 clmul s10, a2, s1 
19 | 0a9f9933 clmul s2, t6, s1 
20 | 0aa89733 clmul a4, a7, a0 
21 | 0aaf17b3 clmul a5, t5, a0 
22 | 0ab4bd33 clmulh s10, s1, a1 
23 | 0aba1533 clmul a0, s4, a1 
24 | 0ac33b33 clmulh s6, t1, a2 
25 | 0ac939b3 clmulh s3, s2, a2 
26 | 0af19733 clmul a4, gp, a5 
27 | 0af33eb3 clmulh t4, t1, a5 
28 | 0afb33b3 clmulh t2, s6, a5 
29 | 0afbb133 clmulh sp, s7, a5 
30 | 0affbe33 clmulh t3, t6, a5 
31 | 0b0b10b3 clmul ra, s6, a6 
32 | 0b313933 clmulh s2, sp, s3 
33 | 0b371433 clmul s0, a4, s3 
34 | 0b3cb6b3 clmulh a3, s9, s3 
35 | 0b3eb1b3 clmulh gp, t4, s3 
36 | 0b453033 clmulh zero, a0, s4 
37 | 0b463033 clmulh zero, a2, s4 
38 | 0b47b033 clmulh zero, a5, s4 
39 | 0b4835b3 clmulh a1, a6, s4 
40 | 0b593b33 clmulh s6, s2, s5 
41 | 0b663333 clmulh t1, a2, s6 
42 | 0b6d3e33 clmulh t3, s10, s6 
43 | 0b6d9ab3 clmul s5, s11, s6 
44 | 0b729e33 clmul t3, t0, s7 
45 | 0b7612b3 clmul t0, a2, s7 
46 | 0b7c9533 clmul a0, s9, s7 
47 | 0b9993b3 clmul t2, s3, s9 
48 | 0b9c36b3 clmulh a3, s8, s9 
49 | 0b9e39b3 clmulh s3, t3, s9 
50 | 0ba537b3 clmulh a5, a0, s10 
51 | 0ba614b3 clmul s1, a2, s10 
52 | 0bb1bc33 clmulh s8, gp, s11 
53 | 0bb63433 clmulh s0, a2, s11 
54 | 0bd715b3 clmul a1, a4, t4 
55 | 0bdb15b3 clmul a1, s6, t4 
56 | 0bdc1e33 clmul t3, s8, t4 
57 | 0bea3d33 clmulh s10, s4, t5 
58 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzbkx.test:
--------------------------------------------------------------------------------
 1 | 28064833 xperm8 a6, a2, zero 
 2 | 2809cf33 xperm8 t5, s3, zero 
 3 | 28102b33 xperm4 s6, zero, ra 
 4 | 281943b3 xperm8 t2, s2, ra 
 5 | 282fcfb3 xperm8 t6, t6, sp 
 6 | 283c47b3 xperm8 a5, s8, gp 
 7 | 28424fb3 xperm8 t6, tp, tp 
 8 | 284c2633 xperm4 a2, s8, tp 
 9 | 286aab33 xperm4 s6, s5, t1 
10 | 2870c533 xperm8 a0, ra, t2 
11 | 28764633 xperm8 a2, a2, t2 
12 | 28772333 xperm4 t1, a4, t2 
13 | 2881c7b3 xperm8 a5, gp, s0 
14 | 2894c333 xperm8 t1, s1, s1 
15 | 28a14c33 xperm8 s8, sp, a0 
16 | 28b5a133 xperm4 sp, a1, a1 
17 | 28beaeb3 xperm4 t4, t4, a1 
18 | 28c6c8b3 xperm8 a7, a3, a2 
19 | 28c9ceb3 xperm8 t4, s3, a2 
20 | 28cb27b3 xperm4 a5, s6, a2 
21 | 28d2c0b3 xperm8 ra, t0, a3 
22 | 28d42f33 xperm4 t5, s0, a3 
23 | 28d64433 xperm8 s0, a2, a3 
24 | 28d7a033 xperm4 zero, a5, a3 
25 | 28eca033 xperm4 zero, s9, a4 
26 | 290142b3 xperm8 t0, sp, a6 
27 | 29022fb3 xperm4 t6, tp, a6 
28 | 2905aab3 xperm4 s5, a1, a6 
29 | 290b4033 xperm8 zero, s6, a6 
30 | 290fa3b3 xperm4 t2, t6, a6 
31 | 2916cdb3 xperm8 s11, a3, a7 
32 | 291dc033 xperm8 zero, s11, a7 
33 | 29202633 xperm4 a2, zero, s2 
34 | 292c4133 xperm8 sp, s8, s2 
35 | 292d26b3 xperm4 a3, s10, s2 
36 | 29304733 xperm8 a4, zero, s3 
37 | 293f4633 xperm8 a2, t5, s3 
38 | 29422a33 xperm4 s4, tp, s4 
39 | 294daa33 xperm4 s4, s11, s4 
40 | 2951aab3 xperm4 s5, gp, s5 
41 | 297327b3 xperm4 a5, t1, s7 
42 | 297425b3 xperm4 a1, s0, s7 
43 | 29782b33 xperm4 s6, a6, s7 
44 | 297ba633 xperm4 a2, s7, s7 
45 | 298ba7b3 xperm4 a5, s7, s8 
46 | 298bceb3 xperm8 t4, s7, s8 
47 | 29914cb3 xperm8 s9, sp, s9 
48 | 2991a0b3 xperm4 ra, gp, s9 
49 | 2992c6b3 xperm8 a3, t0, s9 
50 | 299c4933 xperm8 s2, s8, s9 
51 | 29ae4933 xperm8 s2, t3, s10 
52 | 29aeadb3 xperm4 s11, t4, s10 
53 | 29baa733 xperm4 a4, s5, s11 
54 | 29bdc333 xperm8 t1, s11, s11 
55 | 29c54cb3 xperm8 s9, a0, t3 
56 | 29d224b3 xperm4 s1, tp, t4 
57 | 29f1cdb3 xperm8 s11, gp, t6 
58 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzknh.test:
--------------------------------------------------------------------------------
  1 | 10001093 sha256sum0 ra, zero 
  2 | 10009b13 sha256sum0 s6, ra 
  3 | 10009b93 sha256sum0 s7, ra 
  4 | 10019313 sha256sum0 t1, gp 
  5 | 10019913 sha256sum0 s2, gp 
  6 | 10019b93 sha256sum0 s7, gp 
  7 | 10039a93 sha256sum0 s5, t2 
  8 | 10041a93 sha256sum0 s5, s0 
  9 | 10041f93 sha256sum0 t6, s0 
 10 | 10049993 sha256sum0 s3, s1 
 11 | 10059513 sha256sum0 a0, a1 
 12 | 10061013 sha256sum0 zero, a2 
 13 | 10061093 sha256sum0 ra, a2 
 14 | 10061a93 sha256sum0 s5, a2 
 15 | 10069913 sha256sum0 s2, a3 
 16 | 10071413 sha256sum0 s0, a4 
 17 | 10089d13 sha256sum0 s10, a7 
 18 | 10089f93 sha256sum0 t6, a7 
 19 | 10099993 sha256sum0 s3, s3 
 20 | 100a9c13 sha256sum0 s8, s5 
 21 | 100b1993 sha256sum0 s3, s6 
 22 | 100b9b93 sha256sum0 s7, s7 
 23 | 100b9e13 sha256sum0 t3, s7 
 24 | 100c1193 sha256sum0 gp, s8 
 25 | 100c1b13 sha256sum0 s6, s8 
 26 | 100d1593 sha256sum0 a1, s10 
 27 | 100d1e93 sha256sum0 t4, s10 
 28 | 100e9813 sha256sum0 a6, t4 
 29 | 100f1213 sha256sum0 tp, t5 
 30 | 100f1713 sha256sum0 a4, t5 
 31 | 10101013 sha256sum1 zero, zero 
 32 | 10101593 sha256sum1 a1, zero 
 33 | 10109293 sha256sum1 t0, ra 
 34 | 10111793 sha256sum1 a5, sp 
 35 | 10111e13 sha256sum1 t3, sp 
 36 | 10119d13 sha256sum1 s10, gp 
 37 | 10121c13 sha256sum1 s8, tp 
 38 | 10129713 sha256sum1 a4, t0 
 39 | 10131c93 sha256sum1 s9, t1 
 40 | 10139293 sha256sum1 t0, t2 
 41 | 10151013 sha256sum1 zero, a0 
 42 | 10159813 sha256sum1 a6, a1 
 43 | 10161913 sha256sum1 s2, a2 
 44 | 10161b13 sha256sum1 s6, a2 
 45 | 10169713 sha256sum1 a4, a3 
 46 | 10169e13 sha256sum1 t3, a3 
 47 | 10179713 sha256sum1 a4, a5 
 48 | 10181213 sha256sum1 tp, a6 
 49 | 10199693 sha256sum1 a3, s3 
 50 | 10199d93 sha256sum1 s11, s3 
 51 | 101a1013 sha256sum1 zero, s4 
 52 | 101a1293 sha256sum1 t0, s4 
 53 | 101b9013 sha256sum1 zero, s7 
 54 | 101b9213 sha256sum1 tp, s7 
 55 | 101b9a93 sha256sum1 s5, s7 
 56 | 101b9d93 sha256sum1 s11, s7 
 57 | 101d1413 sha256sum1 s0, s10 
 58 | 101d1593 sha256sum1 a1, s10 
 59 | 101e9293 sha256sum1 t0, t4 
 60 | 101f1393 sha256sum1 t2, t5 
 61 | 10201013 sha256sig0 zero, zero 
 62 | 10209d93 sha256sig0 s11, ra 
 63 | 10219f13 sha256sig0 t5, gp 
 64 | 10229193 sha256sig0 gp, t0 
 65 | 10229593 sha256sig0 a1, t0 
 66 | 10229893 sha256sig0 a7, t0 
 67 | 10229c13 sha256sig0 s8, t0 
 68 | 10239013 sha256sig0 zero, t2 
 69 | 10239293 sha256sig0 t0, t2 
 70 | 10239913 sha256sig0 s2, t2 
 71 | 10251713 sha256sig0 a4, a0 
 72 | 10251d93 sha256sig0 s11, a0 
 73 | 10261a93 sha256sig0 s5, a2 
 74 | 10269193 sha256sig0 gp, a3 
 75 | 10269493 sha256sig0 s1, a3 
 76 | 10271693 sha256sig0 a3, a4 
 77 | 10279513 sha256sig0 a0, a5 
 78 | 10279693 sha256sig0 a3, a5 
 79 | 10289493 sha256sig0 s1, a7 
 80 | 10289713 sha256sig0 a4, a7 
 81 | 10289b13 sha256sig0 s6, a7 
 82 | 10299293 sha256sig0 t0, s3 
 83 | 102a1993 sha256sig0 s3, s4 
 84 | 102c9093 sha256sig0 ra, s9 
 85 | 102d1c93 sha256sig0 s9, s10 
 86 | 102f1993 sha256sig0 s3, t5 
 87 | 102f9613 sha256sig0 a2, t6 
 88 | 10301193 sha256sig1 gp, zero 
 89 | 10301d13 sha256sig1 s10, zero 
 90 | 10309193 sha256sig1 gp, ra 
 91 | 10309c13 sha256sig1 s8, ra 
 92 | 10311613 sha256sig1 a2, sp 
 93 | 10321593 sha256sig1 a1, tp 
 94 | 10329a93 sha256sig1 s5, t0 
 95 | 10331813 sha256sig1 a6, t1 
 96 | 10341293 sha256sig1 t0, s0 
 97 | 10349313 sha256sig1 t1, s1 
 98 | 10349e13 sha256sig1 t3, s1 
 99 | 10351093 sha256sig1 ra, a0 
100 | 10359a93 sha256sig1 s5, a1 
101 | 10361f13 sha256sig1 t5, a2 
102 | 10369713 sha256sig1 a4, a3 
103 | 10371513 sha256sig1 a0, a4 
104 | 10379113 sha256sig1 sp, a5 
105 | 10379593 sha256sig1 a1, a5 
106 | 10379a93 sha256sig1 s5, a5 
107 | 10379f13 sha256sig1 t5, a5 
108 | 10381813 sha256sig1 a6, a6 
109 | 10391b13 sha256sig1 s6, s2 
110 | 10399d13 sha256sig1 s10, s3 
111 | 103b1193 sha256sig1 gp, s6 
112 | 103c1113 sha256sig1 sp, s8 
113 | 103c1993 sha256sig1 s3, s8 
114 | 103c1b13 sha256sig1 s6, s8 
115 | 103c9193 sha256sig1 gp, s9 
116 | 103d9413 sha256sig1 s0, s11 
117 | 103e1513 sha256sig1 a0, t3 
118 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzksed.test:
--------------------------------------------------------------------------------
 1 | 300103b3 sm4ed t2, sp, zero, 0x0 
 2 | 30098f33 sm4ed t5, s3, zero, 0x0 
 3 | 303f83b3 sm4ed t2, t6, gp, 0x0 
 4 | 30608933 sm4ed s2, ra, t1, 0x0 
 5 | 30790133 sm4ed sp, s2, t2, 0x0 
 6 | 30c701b3 sm4ed gp, a4, a2, 0x0 
 7 | 31c800b3 sm4ed ra, a6, t3, 0x0 
 8 | 34930cb3 sm4ks s9, t1, s1, 0x0 
 9 | 34940933 sm4ks s2, s0, s1, 0x0 
10 | 34b88e33 sm4ks t3, a7, a1, 0x0 
11 | 34c40e33 sm4ks t3, s0, a2, 0x0 
12 | 35910833 sm4ks a6, sp, s9, 0x0 
13 | 35970633 sm4ks a2, a4, s9, 0x0 
14 | 703880b3 sm4ed ra, a7, gp, 0x1 
15 | 70500fb3 sm4ed t6, zero, t0, 0x1 
16 | 70588eb3 sm4ed t4, a7, t0, 0x1 
17 | 711c0e33 sm4ed t3, s8, a7, 0x1 
18 | 713103b3 sm4ed t2, sp, s3, 0x1 
19 | 716b04b3 sm4ed s1, s6, s6, 0x1 
20 | 74080433 sm4ks s0, a6, zero, 0x1 
21 | 74168533 sm4ks a0, a3, ra, 0x1 
22 | 742680b3 sm4ks ra, a3, sp, 0x1 
23 | 74aa8db3 sm4ks s11, s5, a0, 0x1 
24 | 74cc0133 sm4ks sp, s8, a2, 0x1 
25 | 74fc0933 sm4ks s2, s8, a5, 0x1 
26 | 757a0c33 sm4ks s8, s4, s7, 0x1 
27 | 75a20333 sm4ks t1, tp, s10, 0x1 
28 | 75d302b3 sm4ks t0, t1, t4, 0x1 
29 | 75ec0033 sm4ks zero, s8, t5, 0x1 
30 | 75ef0b33 sm4ks s6, t5, t5, 0x1 
31 | b0140ab3 sm4ed s5, s0, ra, 0x2 
32 | b0598fb3 sm4ed t6, s3, t0, 0x2 
33 | b0d68ab3 sm4ed s5, a3, a3, 0x2 
34 | b14101b3 sm4ed gp, sp, s4, 0x2 
35 | b1718e33 sm4ed t3, gp, s7, 0x2 
36 | b1cc87b3 sm4ed a5, s9, t3, 0x2 
37 | b4390033 sm4ks zero, s2, gp, 0x2 
38 | b43c86b3 sm4ks a3, s9, gp, 0x2 
39 | b4818133 sm4ks sp, gp, s0, 0x2 
40 | b4b10bb3 sm4ks s7, sp, a1, 0x2 
41 | b5208233 sm4ks tp, ra, s2, 0x2 
42 | b5250533 sm4ks a0, a0, s2, 0x2 
43 | b5a90cb3 sm4ks s9, s2, s10, 0x2 
44 | b5f90833 sm4ks a6, s2, t6, 0x2 
45 | f03e81b3 sm4ed gp, t4, gp, 0x3 
46 | f05906b3 sm4ed a3, s2, t0, 0x3 
47 | f0688b33 sm4ed s6, a7, t1, 0x3 
48 | f0c78733 sm4ed a4, a5, a2, 0x3 
49 | f0df8c33 sm4ed s8, t6, a3, 0x3 
50 | f19f8d33 sm4ed s10, t6, s9, 0x3 
51 | f1ab0733 sm4ed a4, s6, s10, 0x3 
52 | f1e880b3 sm4ed ra, a7, t5, 0x3 
53 | f46c8533 sm4ks a0, s9, t1, 0x3 
54 | f4a083b3 sm4ks t2, ra, a0, 0x3 
55 | f51d8433 sm4ks s0, s11, a7, 0x3 
56 | f5350333 sm4ks t1, a0, s3, 0x3 
57 | f5aa0b33 sm4ks s6, s4, s10, 0x3 
58 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzksh.test:
--------------------------------------------------------------------------------
 1 | 10801213 sm3p0 tp, zero 
 2 | 10801b13 sm3p0 s6, zero 
 3 | 10811093 sm3p0 ra, sp 
 4 | 10811c13 sm3p0 s8, sp 
 5 | 10821b93 sm3p0 s7, tp 
 6 | 10831913 sm3p0 s2, t1 
 7 | 10839293 sm3p0 t0, t2 
 8 | 10839d13 sm3p0 s10, t2 
 9 | 10849493 sm3p0 s1, s1 
10 | 10851293 sm3p0 t0, a0 
11 | 10851713 sm3p0 a4, a0 
12 | 10851993 sm3p0 s3, a0 
13 | 10881693 sm3p0 a3, a6 
14 | 10881913 sm3p0 s2, a6 
15 | 10889a13 sm3p0 s4, a7 
16 | 10899813 sm3p0 a6, s3 
17 | 108a1313 sm3p0 t1, s4 
18 | 108a1d93 sm3p0 s11, s4 
19 | 108a9e93 sm3p0 t4, s5 
20 | 108b1313 sm3p0 t1, s6 
21 | 108c9113 sm3p0 sp, s9 
22 | 108c9213 sm3p0 tp, s9 
23 | 108d1a93 sm3p0 s5, s10 
24 | 108d1b93 sm3p0 s7, s10 
25 | 108e9b13 sm3p0 s6, t4 
26 | 108f1393 sm3p0 t2, t5 
27 | 108f9b93 sm3p0 s7, t6 
28 | 10909013 sm3p1 zero, ra 
29 | 10909993 sm3p1 s3, ra 
30 | 10929293 sm3p1 t0, t0 
31 | 10931613 sm3p1 a2, t1 
32 | 10939393 sm3p1 t2, t2 
33 | 10941413 sm3p1 s0, s0 
34 | 10941493 sm3p1 s1, s0 
35 | 10949213 sm3p1 tp, s1 
36 | 10949393 sm3p1 t2, s1 
37 | 10961b13 sm3p1 s6, a2 
38 | 10961e93 sm3p1 t4, a2 
39 | 10969e13 sm3p1 t3, a3 
40 | 10971893 sm3p1 a7, a4 
41 | 10971c13 sm3p1 s8, a4 
42 | 10971c93 sm3p1 s9, a4 
43 | 10979513 sm3p1 a0, a5 
44 | 10981013 sm3p1 zero, a6 
45 | 10991713 sm3p1 a4, s2 
46 | 109b1613 sm3p1 a2, s6 
47 | 109b9593 sm3p1 a1, s7 
48 | 109c1693 sm3p1 a3, s8 
49 | 109c1913 sm3p1 s2, s8 
50 | 109c9c93 sm3p1 s9, s9 
51 | 109d1693 sm3p1 a3, s10 
52 | 109d9193 sm3p1 gp, s11 
53 | 109d9d13 sm3p1 s10, s11 
54 | 109e9713 sm3p1 a4, t4 
55 | 109e9d13 sm3p1 s10, t4 
56 | 109f9393 sm3p1 t2, t6 
57 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzvbc.test:
--------------------------------------------------------------------------------
  1 | 300ca1d7 vclmul.vv v3, v0, v25, v0.t 
  2 | 30222657 vclmul.vv v12, v2, v4, v0.t 
  3 | 3024ec57 vclmul.vx v24, v2, s1, v0.t 
  4 | 3042abd7 vclmul.vv v23, v4, v5, v0.t 
  5 | 304aa3d7 vclmul.vv v7, v4, v21, v0.t 
  6 | 305fab57 vclmul.vv v22, v5, v31, v0.t 
  7 | 3074e2d7 vclmul.vx v5, v7, s1, v0.t 
  8 | 309a6c57 vclmul.vx v24, v9, s4, v0.t 
  9 | 30ade057 vclmul.vx v0, v10, s11, v0.t 
 10 | 30bd2cd7 vclmul.vv v25, v11, v26, v0.t 
 11 | 30c425d7 vclmul.vv v11, v12, v8, v0.t 
 12 | 30d62f57 vclmul.vv v30, v13, v12, v0.t 
 13 | 30dde157 vclmul.vx v2, v13, s11, v0.t 
 14 | 30e56057 vclmul.vx v0, v14, a0, v0.t 
 15 | 30ef6957 vclmul.vx v18, v14, t5, v0.t 
 16 | 310020d7 vclmul.vv v1, v16, v0, v0.t 
 17 | 3109a857 vclmul.vv v16, v16, v19, v0.t 
 18 | 31166cd7 vclmul.vx v25, v17, a2, v0.t 
 19 | 31186a57 vclmul.vx v20, v17, a6, v0.t 
 20 | 312629d7 vclmul.vv v19, v18, v12, v0.t 
 21 | 3131a5d7 vclmul.vv v11, v19, v3, v0.t 
 22 | 3154ab57 vclmul.vv v22, v21, v9, v0.t 
 23 | 316526d7 vclmul.vv v13, v22, v10, v0.t 
 24 | 318e6857 vclmul.vx v16, v24, t3, v0.t 
 25 | 3195a357 vclmul.vv v6, v25, v11, v0.t 
 26 | 3199a757 vclmul.vv v14, v25, v19, v0.t 
 27 | 319ca9d7 vclmul.vv v19, v25, v25, v0.t 
 28 | 31a569d7 vclmul.vx v19, v26, a0, v0.t 
 29 | 31d6a957 vclmul.vv v18, v29, v13, v0.t 
 30 | 31e2a657 vclmul.vv v12, v30, v5, v0.t 
 31 | 3204e457 vclmul.vx v8, v0, s1 
 32 | 320bebd7 vclmul.vx v23, v0, s7 
 33 | 32116c57 vclmul.vx v24, v1, sp 
 34 | 3212a1d7 vclmul.vv v3, v1, v5 
 35 | 321aab57 vclmul.vv v22, v1, v21 
 36 | 321b6857 vclmul.vx v16, v1, s6 
 37 | 323fe9d7 vclmul.vx v19, v3, t6 
 38 | 3251a0d7 vclmul.vv v1, v5, v3 
 39 | 3256ad57 vclmul.vv v26, v5, v13 
 40 | 3263a6d7 vclmul.vv v13, v6, v7 
 41 | 3266ef57 vclmul.vx v30, v6, a3 
 42 | 326fead7 vclmul.vx v21, v6, t6 
 43 | 32936957 vclmul.vx v18, v9, t1 
 44 | 32aeed57 vclmul.vx v26, v10, t4 
 45 | 32ccee57 vclmul.vx v28, v12, s9 
 46 | 32f5ee57 vclmul.vx v28, v15, a1 
 47 | 330ca257 vclmul.vv v4, v16, v25 
 48 | 330e68d7 vclmul.vx v17, v16, t3 
 49 | 332ba257 vclmul.vv v4, v18, v23 
 50 | 33386157 vclmul.vx v2, v19, a6 
 51 | 33716557 vclmul.vx v10, v23, sp 
 52 | 33ade1d7 vclmul.vx v3, v26, s11 
 53 | 33b0e4d7 vclmul.vx v9, v27, ra 
 54 | 33be65d7 vclmul.vx v11, v27, t3 
 55 | 33dfebd7 vclmul.vx v23, v29, t6 
 56 | 33e5ec57 vclmul.vx v24, v30, a1 
 57 | 33f22857 vclmul.vv v16, v31, v4 
 58 | 340cea57 vclmulh.vx v20, v0, s9, v0.t 
 59 | 343762d7 vclmulh.vx v5, v3, a4, v0.t 
 60 | 3439a557 vclmulh.vv v10, v3, v19, v0.t 
 61 | 344265d7 vclmulh.vx v11, v4, tp, v0.t 
 62 | 34452c57 vclmulh.vv v24, v4, v10, v0.t 
 63 | 344da1d7 vclmulh.vv v3, v4, v27, v0.t 
 64 | 345365d7 vclmulh.vx v11, v5, t1, v0.t 
 65 | 34b367d7 vclmulh.vx v15, v11, t1, v0.t 
 66 | 34c0e1d7 vclmulh.vx v3, v12, ra, v0.t 
 67 | 34c222d7 vclmulh.vv v5, v12, v4, v0.t 
 68 | 34cd2a57 vclmulh.vv v20, v12, v26, v0.t 
 69 | 34dc2057 vclmulh.vv v0, v13, v24, v0.t 
 70 | 35066fd7 vclmulh.vx v31, v16, a2, v0.t 
 71 | 351560d7 vclmulh.vx v1, v17, a0, v0.t 
 72 | 3525a7d7 vclmulh.vv v15, v18, v11, v0.t 
 73 | 35286c57 vclmulh.vx v24, v18, a6, v0.t 
 74 | 352be057 vclmulh.vx v0, v18, s7, v0.t 
 75 | 3534e2d7 vclmulh.vx v5, v19, s1, v0.t 
 76 | 3537ecd7 vclmulh.vx v25, v19, a5, v0.t 
 77 | 35402857 vclmulh.vv v16, v20, v0, v0.t 
 78 | 354167d7 vclmulh.vx v15, v20, sp, v0.t 
 79 | 35422b57 vclmulh.vv v22, v20, v4, v0.t 
 80 | 35426d57 vclmulh.vx v26, v20, tp, v0.t 
 81 | 3556efd7 vclmulh.vx v31, v21, a3, v0.t 
 82 | 35802dd7 vclmulh.vv v27, v24, v0, v0.t 
 83 | 3580e357 vclmulh.vx v6, v24, ra, v0.t 
 84 | 359f2257 vclmulh.vv v4, v25, v30, v0.t 
 85 | 35b62c57 vclmulh.vv v24, v27, v12, v0.t 
 86 | 35d4a457 vclmulh.vv v8, v29, v9, v0.t 
 87 | 35daa557 vclmulh.vv v10, v29, v21, v0.t 
 88 | 35eee457 vclmulh.vx v8, v30, t4, v0.t 
 89 | 35f02ad7 vclmulh.vv v21, v31, v0, v0.t 
 90 | 35f462d7 vclmulh.vx v5, v31, s0, v0.t 
 91 | 35faa9d7 vclmulh.vv v19, v31, v21, v0.t 
 92 | 36006c57 vclmulh.vx v24, v0, zero 
 93 | 3600a0d7 vclmulh.vv v1, v0, v1 
 94 | 36162dd7 vclmulh.vv v27, v1, v12 
 95 | 361ee957 vclmulh.vx v18, v1, t4 
 96 | 36326a57 vclmulh.vx v20, v3, tp 
 97 | 3632a6d7 vclmulh.vv v13, v3, v5 
 98 | 3659a457 vclmulh.vv v8, v5, v19 
 99 | 366d2057 vclmulh.vv v0, v6, v26 
100 | 3693e7d7 vclmulh.vx v15, v9, t2 
101 | 3697eb57 vclmulh.vx v22, v9, a5 
102 | 36b268d7 vclmulh.vx v17, v11, tp 
103 | 36c6a0d7 vclmulh.vv v1, v12, v13 
104 | 3703a857 vclmulh.vv v16, v16, v7 
105 | 372129d7 vclmulh.vv v19, v18, v2 
106 | 373127d7 vclmulh.vv v15, v19, v2 
107 | 3747e4d7 vclmulh.vx v9, v20, a5 
108 | 374decd7 vclmulh.vx v25, v20, s11 
109 | 37536457 vclmulh.vx v8, v21, t1 
110 | 376dabd7 vclmulh.vv v23, v22, v27 
111 | 3770a657 vclmulh.vv v12, v23, v1 
112 | 37c266d7 vclmulh.vx v13, v28, tp 
113 | 37ce6b57 vclmulh.vx v22, v28, t3 
114 | 37d32e57 vclmulh.vv v28, v29, v6 
115 | 37d46ed7 vclmulh.vx v29, v29, s0 
116 | 37e92657 vclmulh.vv v12, v30, v18 
117 | 37fb2e57 vclmulh.vv v28, v31, v22 
118 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzvkg.test:
--------------------------------------------------------------------------------
 1 | a208a6f7 vgmul.vv v13, v0 
 2 | a208aaf7 vgmul.vv v21, v0 
 3 | a208abf7 vgmul.vv v23, v0 
 4 | a208aff7 vgmul.vv v31, v0 
 5 | a248a777 vgmul.vv v14, v4 
 6 | a268af77 vgmul.vv v30, v6 
 7 | a278a677 vgmul.vv v12, v7 
 8 | a278aef7 vgmul.vv v29, v7 
 9 | a298a3f7 vgmul.vv v7, v9 
10 | a298acf7 vgmul.vv v25, v9 
11 | a2b8a277 vgmul.vv v4, v11 
12 | a2b8acf7 vgmul.vv v25, v11 
13 | a2d8aef7 vgmul.vv v29, v13 
14 | a2f8a877 vgmul.vv v16, v15 
15 | a2f8aa77 vgmul.vv v20, v15 
16 | a338a477 vgmul.vv v8, v19 
17 | a338a877 vgmul.vv v16, v19 
18 | a368a177 vgmul.vv v2, v22 
19 | a368a4f7 vgmul.vv v9, v22 
20 | a368ae77 vgmul.vv v28, v22 
21 | a378ab77 vgmul.vv v22, v23 
22 | a378ad77 vgmul.vv v26, v23 
23 | a388a277 vgmul.vv v4, v24 
24 | a388a877 vgmul.vv v16, v24 
25 | a398a6f7 vgmul.vv v13, v25 
26 | a3b8ab77 vgmul.vv v22, v27 
27 | a3c8a4f7 vgmul.vv v9, v28 
28 | a3d8aef7 vgmul.vv v29, v29 
29 | a3e8a977 vgmul.vv v18, v30 
30 | a3e8acf7 vgmul.vv v25, v30 
31 | b206a3f7 vghsh.vv v7, v0, v13 
32 | b216a177 vghsh.vv v2, v1, v13 
33 | b2312877 vghsh.vv v16, v3, v2 
34 | b2722577 vghsh.vv v10, v7, v4 
35 | b276ac77 vghsh.vv v24, v7, v13 
36 | b277a5f7 vghsh.vv v11, v7, v15 
37 | b277ab77 vghsh.vv v22, v7, v15 
38 | b2842377 vghsh.vv v6, v8, v8 
39 | b28a2bf7 vghsh.vv v23, v8, v20 
40 | b297a877 vghsh.vv v16, v9, v15 
41 | b2a12bf7 vghsh.vv v23, v10, v2 
42 | b2a2a9f7 vghsh.vv v19, v10, v5 
43 | b2d9a377 vghsh.vv v6, v13, v19 
44 | b2df29f7 vghsh.vv v19, v13, v30 
45 | b2e5af77 vghsh.vv v30, v14, v11 
46 | b2f427f7 vghsh.vv v15, v15, v8 
47 | b3072177 vghsh.vv v2, v16, v14 
48 | b30d2077 vghsh.vv v0, v16, v26 
49 | b319a577 vghsh.vv v10, v17, v19 
50 | b31b29f7 vghsh.vv v19, v17, v22 
51 | b31ea577 vghsh.vv v10, v17, v29 
52 | b357a177 vghsh.vv v2, v21, v15 
53 | b36127f7 vghsh.vv v15, v22, v2 
54 | b3672577 vghsh.vv v10, v22, v14 
55 | b38dacf7 vghsh.vv v25, v24, v27 
56 | b397a9f7 vghsh.vv v19, v25, v15 
57 | b3bea177 vghsh.vv v2, v27, v29 
58 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzvknha.test:
--------------------------------------------------------------------------------
 1 | b6062377 vsha2ms.vv v6, v0, v12 
 2 | b60a2af7 vsha2ms.vv v21, v0, v20 
 3 | b621a4f7 vsha2ms.vv v9, v2, v3 
 4 | b63a2477 vsha2ms.vv v8, v3, v20 
 5 | b63ba377 vsha2ms.vv v6, v3, v23 
 6 | b641a577 vsha2ms.vv v10, v4, v3 
 7 | b644acf7 vsha2ms.vv v25, v4, v9 
 8 | b64fadf7 vsha2ms.vv v27, v4, v31 
 9 | b67a2277 vsha2ms.vv v4, v7, v20 
10 | b6a82df7 vsha2ms.vv v27, v10, v16 
11 | b6c6a777 vsha2ms.vv v14, v12, v13 
12 | b6d42d77 vsha2ms.vv v26, v13, v8 
13 | b701ad77 vsha2ms.vv v26, v16, v3 
14 | b701af77 vsha2ms.vv v30, v16, v3 
15 | b703a377 vsha2ms.vv v6, v16, v7 
16 | b7112277 vsha2ms.vv v4, v17, v2 
17 | b7112ff7 vsha2ms.vv v31, v17, v2 
18 | b72c20f7 vsha2ms.vv v1, v18, v24 
19 | b7312577 vsha2ms.vv v10, v19, v2 
20 | b74c26f7 vsha2ms.vv v13, v20, v24 
21 | b74e2af7 vsha2ms.vv v21, v20, v28 
22 | b76a21f7 vsha2ms.vv v3, v22, v20 
23 | b778a0f7 vsha2ms.vv v1, v23, v17 
24 | b7872777 vsha2ms.vv v14, v24, v14 
25 | b78a2df7 vsha2ms.vv v27, v24, v20 
26 | b79a22f7 vsha2ms.vv v5, v25, v20 
27 | b7a129f7 vsha2ms.vv v19, v26, v2 
28 | b7ab2477 vsha2ms.vv v8, v26, v22 
29 | b7ca2ef7 vsha2ms.vv v29, v28, v20 
30 | b7d42cf7 vsha2ms.vv v25, v29, v8 
31 | ba1dab77 vsha2ch.vv v22, v1, v27 
32 | ba212cf7 vsha2ch.vv v25, v2, v2 
33 | ba3da077 vsha2ch.vv v0, v3, v27 
34 | ba3fa3f7 vsha2ch.vv v7, v3, v31 
35 | ba4e2a77 vsha2ch.vv v20, v4, v28 
36 | ba51a177 vsha2ch.vv v2, v5, v3 
37 | ba7b2e77 vsha2ch.vv v28, v7, v22 
38 | ba892ef7 vsha2ch.vv v29, v8, v18 
39 | ba9facf7 vsha2ch.vv v25, v9, v31 
40 | bacb2877 vsha2ch.vv v16, v12, v22 
41 | bad8aef7 vsha2ch.vv v29, v13, v17 
42 | bae82577 vsha2ch.vv v10, v14, v16 
43 | baf9a977 vsha2ch.vv v18, v15, v19 
44 | bb0c21f7 vsha2ch.vv v3, v16, v24 
45 | bb0c2df7 vsha2ch.vv v27, v16, v24 
46 | bb22a877 vsha2ch.vv v16, v18, v5 
47 | bb242af7 vsha2ch.vv v21, v18, v8 
48 | bb312277 vsha2ch.vv v4, v19, v2 
49 | bb4eaf77 vsha2ch.vv v30, v20, v29 
50 | bb602477 vsha2ch.vv v8, v22, v0 
51 | bb64a3f7 vsha2ch.vv v7, v22, v9 
52 | bb712477 vsha2ch.vv v8, v23, v2 
53 | bb722377 vsha2ch.vv v6, v23, v4 
54 | bbc32077 vsha2ch.vv v0, v28, v6 
55 | bbf1a477 vsha2ch.vv v8, v31, v3 
56 | bbf6ae77 vsha2ch.vv v28, v31, v13 
57 | bbf924f7 vsha2ch.vv v9, v31, v18 
58 | be272bf7 vsha2cl.vv v23, v2, v14 
59 | be2e2377 vsha2cl.vv v6, v2, v28 
60 | be382b77 vsha2cl.vv v22, v3, v16 
61 | be3da777 vsha2cl.vv v14, v3, v27 
62 | be3f2877 vsha2cl.vv v16, v3, v30 
63 | be572577 vsha2cl.vv v10, v5, v14 
64 | be62ad77 vsha2cl.vv v26, v6, v5 
65 | be822777 vsha2cl.vv v14, v8, v4 
66 | bea8a077 vsha2cl.vv v0, v10, v17 
67 | bec72077 vsha2cl.vv v0, v12, v14 
68 | bec7ab77 vsha2cl.vv v22, v12, v15 
69 | bed4a3f7 vsha2cl.vv v7, v13, v9 
70 | bedba1f7 vsha2cl.vv v3, v13, v23 
71 | bedeaef7 vsha2cl.vv v29, v13, v29 
72 | bee02977 vsha2cl.vv v18, v14, v0 
73 | bee3aef7 vsha2cl.vv v29, v14, v7 
74 | bef6ab77 vsha2cl.vv v22, v15, v13 
75 | bf1b2a77 vsha2cl.vv v20, v17, v22 
76 | bf20aff7 vsha2cl.vv v31, v18, v1 
77 | bf30a577 vsha2cl.vv v10, v19, v1 
78 | bf38a077 vsha2cl.vv v0, v19, v17 
79 | bf39a277 vsha2cl.vv v4, v19, v19 
80 | bf43ab77 vsha2cl.vv v22, v20, v7 
81 | bf6e2577 vsha2cl.vv v10, v22, v28 
82 | bf72a877 vsha2cl.vv v16, v23, v5 
83 | bf7fa877 vsha2cl.vv v16, v23, v31 
84 | bf8b2d77 vsha2cl.vv v26, v24, v22 
85 | bf8bae77 vsha2cl.vv v28, v24, v23 
86 | bfb9a5f7 vsha2cl.vv v11, v27, v19 
87 | bfd9a7f7 vsha2cl.vv v15, v29, v19 
88 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzvknhb.test:
--------------------------------------------------------------------------------
 1 | b607a477 vsha2ms.vv v8, v0, v15 
 2 | b6092677 vsha2ms.vv v12, v0, v18 
 3 | b60f2bf7 vsha2ms.vv v23, v0, v30 
 4 | b60fa377 vsha2ms.vv v6, v0, v31 
 5 | b6102df7 vsha2ms.vv v27, v1, v0 
 6 | b613a5f7 vsha2ms.vv v11, v1, v7 
 7 | b6382b77 vsha2ms.vv v22, v3, v16 
 8 | b652adf7 vsha2ms.vv v27, v5, v5 
 9 | b65a2177 vsha2ms.vv v2, v5, v20 
10 | b687a2f7 vsha2ms.vv v5, v8, v15 
11 | b69eaf77 vsha2ms.vv v30, v9, v29 
12 | b6bba177 vsha2ms.vv v2, v11, v23 
13 | b6ca2577 vsha2ms.vv v10, v12, v20 
14 | b6d2a877 vsha2ms.vv v16, v13, v5 
15 | b6d82f77 vsha2ms.vv v30, v13, v16 
16 | b6ed25f7 vsha2ms.vv v11, v14, v26 
17 | b6f4aef7 vsha2ms.vv v29, v15, v9 
18 | b70b21f7 vsha2ms.vv v3, v16, v22 
19 | b7102177 vsha2ms.vv v2, v17, v0 
20 | b717a1f7 vsha2ms.vv v3, v17, v15 
21 | b748a0f7 vsha2ms.vv v1, v20, v17 
22 | b7642a77 vsha2ms.vv v20, v22, v8 
23 | b765a477 vsha2ms.vv v8, v22, v11 
24 | b7682df7 vsha2ms.vv v27, v22, v16 
25 | b7862e77 vsha2ms.vv v28, v24, v12 
26 | b79aa5f7 vsha2ms.vv v11, v25, v21 
27 | b7c1a0f7 vsha2ms.vv v1, v28, v3 
28 | b7f72b77 vsha2ms.vv v22, v31, v14 
29 | b7f7a177 vsha2ms.vv v2, v31, v15 
30 | b7f9af77 vsha2ms.vv v30, v31, v19 
31 | ba04ab77 vsha2ch.vv v22, v0, v9 
32 | ba2e26f7 vsha2ch.vv v13, v2, v28 
33 | ba2fa477 vsha2ch.vv v8, v2, v31 
34 | ba2fae77 vsha2ch.vv v28, v2, v31 
35 | ba40a7f7 vsha2ch.vv v15, v4, v1 
36 | ba462b77 vsha2ch.vv v22, v4, v12 
37 | ba4e2ef7 vsha2ch.vv v29, v4, v28 
38 | ba582777 vsha2ch.vv v14, v5, v16 
39 | ba6421f7 vsha2ch.vv v3, v6, v8 
40 | ba692677 vsha2ch.vv v12, v6, v18 
41 | ba73a5f7 vsha2ch.vv v11, v7, v7 
42 | ba8b2a77 vsha2ch.vv v20, v8, v22 
43 | ba94a177 vsha2ch.vv v2, v9, v9 
44 | ba9c2777 vsha2ch.vv v14, v9, v24 
45 | baa02bf7 vsha2ch.vv v23, v10, v0 
46 | bad1a8f7 vsha2ch.vv v17, v13, v3 
47 | baf32a77 vsha2ch.vv v20, v15, v6 
48 | baf6a3f7 vsha2ch.vv v7, v15, v13 
49 | bb13a677 vsha2ch.vv v12, v17, v7 
50 | bb2aa5f7 vsha2ch.vv v11, v18, v21 
51 | bb46a7f7 vsha2ch.vv v15, v20, v13 
52 | bb4c25f7 vsha2ch.vv v11, v20, v24 
53 | bb52a7f7 vsha2ch.vv v15, v21, v5 
54 | bb6baa77 vsha2ch.vv v20, v22, v23 
55 | bb8daef7 vsha2ch.vv v29, v24, v27 
56 | bb9baef7 vsha2ch.vv v29, v25, v23 
57 | bbbaa6f7 vsha2ch.vv v13, v27, v21 
58 | be272b77 vsha2cl.vv v22, v2, v14 
59 | be362c77 vsha2cl.vv v24, v3, v12 
60 | be872b77 vsha2cl.vv v22, v8, v14 
61 | be8b2577 vsha2cl.vv v10, v8, v22 
62 | be972877 vsha2cl.vv v16, v9, v14 
63 | beafa677 vsha2cl.vv v12, v10, v31 
64 | bec92477 vsha2cl.vv v8, v12, v18 
65 | bed4aff7 vsha2cl.vv v31, v13, v9 
66 | bef024f7 vsha2cl.vv v9, v15, v0 
67 | bef0a377 vsha2cl.vv v6, v15, v1 
68 | beffaef7 vsha2cl.vv v29, v15, v31 
69 | bf0bae77 vsha2cl.vv v28, v16, v23 
70 | bf11aff7 vsha2cl.vv v31, v17, v3 
71 | bf13aef7 vsha2cl.vv v29, v17, v7 
72 | bf1faff7 vsha2cl.vv v31, v17, v31 
73 | bf4623f7 vsha2cl.vv v7, v20, v12 
74 | bf4a22f7 vsha2cl.vv v5, v20, v20 
75 | bf5e26f7 vsha2cl.vv v13, v21, v28 
76 | bf632a77 vsha2cl.vv v20, v22, v6 
77 | bf6f2a77 vsha2cl.vv v20, v22, v30 
78 | bf6fa477 vsha2cl.vv v8, v22, v31 
79 | bf7f2077 vsha2cl.vv v0, v23, v30 
80 | bf90aff7 vsha2cl.vv v31, v25, v1 
81 | bf9a20f7 vsha2cl.vv v1, v25, v20 
82 | bfaa28f7 vsha2cl.vv v17, v26, v20 
83 | bfb02df7 vsha2cl.vv v27, v27, v0 
84 | bfcda0f7 vsha2cl.vv v1, v28, v27 
85 | bfde2d77 vsha2cl.vv v26, v29, v28 
86 | bfe025f7 vsha2cl.vv v11, v30, v0 
87 | bfe72577 vsha2cl.vv v10, v30, v14 
88 | 


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/test_data/rv64/rvzvksed.test:
--------------------------------------------------------------------------------
 1 | 8604a777 vsm4k.vi v14, v0, 0x9 
 2 | 860720f7 vsm4k.vi v1, v0, 0xe 
 3 | 86132c77 vsm4k.vi v24, v1, 0x6 
 4 | 8628aaf7 vsm4k.vi v21, v2, 0x11 
 5 | 8633aef7 vsm4k.vi v29, v3, 0x7 
 6 | 864ea677 vsm4k.vi v12, v4, 0x1d 
 7 | 8666ad77 vsm4k.vi v26, v6, 0xd 
 8 | 868ca177 vsm4k.vi v2, v8, 0x19 
 9 | 868faff7 vsm4k.vi v31, v8, 0x1f 
10 | 86942a77 vsm4k.vi v20, v9, 0x8 
11 | 8699a6f7 vsm4k.vi v13, v9, 0x13 
12 | 86baacf7 vsm4k.vi v25, v11, 0x15 
13 | 86be26f7 vsm4k.vi v13, v11, 0x1c 
14 | 86d3ae77 vsm4k.vi v28, v13, 0x7 
15 | 86d5a377 vsm4k.vi v6, v13, 0xb 
16 | 86d72077 vsm4k.vi v0, v13, 0xe 
17 | 86f02477 vsm4k.vi v8, v15, 0x0 
18 | 87422df7 vsm4k.vi v27, v20, 0x4 
19 | 87532ff7 vsm4k.vi v31, v21, 0x6 
20 | 8759a6f7 vsm4k.vi v13, v21, 0x13 
21 | 87622277 vsm4k.vi v4, v22, 0x4 
22 | 8781a577 vsm4k.vi v10, v24, 0x3 
23 | 8796a277 vsm4k.vi v4, v25, 0xd 
24 | 879822f7 vsm4k.vi v5, v25, 0x10 
25 | 87a7af77 vsm4k.vi v30, v26, 0xf 
26 | 87beacf7 vsm4k.vi v25, v27, 0x1d 
27 | 87de2df7 vsm4k.vi v27, v29, 0x1c 
28 | a21824f7 vsm4r.vv v9, v1 
29 | a2182a77 vsm4r.vv v20, v1 
30 | a2382df7 vsm4r.vv v27, v3 
31 | a24821f7 vsm4r.vv v3, v4 
32 | a2482377 vsm4r.vv v6, v4 
33 | a24826f7 vsm4r.vv v13, v4 
34 | a2482977 vsm4r.vv v18, v4 
35 | a2582977 vsm4r.vv v18, v5 
36 | a2582a77 vsm4r.vv v20, v5 
37 | a2582e77 vsm4r.vv v28, v5 
38 | a2682177 vsm4r.vv v2, v6 
39 | a2782ff7 vsm4r.vv v31, v7 
40 | a2882777 vsm4r.vv v14, v8 
41 | a2882cf7 vsm4r.vv v25, v8 
42 | a2882ff7 vsm4r.vv v31, v8 
43 | a29824f7 vsm4r.vv v9, v9 
44 | a2982e77 vsm4r.vv v28, v9 
45 | a2b825f7 vsm4r.vv v11, v11 
46 | a2d82e77 vsm4r.vv v28, v13 
47 | a2e821f7 vsm4r.vv v3, v14 
48 | a2e82df7 vsm4r.vv v27, v14 
49 | a3082f77 vsm4r.vv v30, v16 
50 | a33827f7 vsm4r.vv v15, v19 
51 | a3982777 vsm4r.vv v14, v25 
52 | a3982d77 vsm4r.vv v26, v25 
53 | a3a82177 vsm4r.vv v2, v26 
54 | a3b82077 vsm4r.vv v0, v27 
55 | a3d82af7 vsm4r.vv v21, v29 
56 | a3f825f7 vsm4r.vv v11, v31 
57 | a61821f7 vsm4r.vs v3, v1 
58 | a6282ef7 vsm4r.vs v29, v2 
59 | a6382677 vsm4r.vs v12, v3 
60 | a6482f77 vsm4r.vs v30, v4 
61 | a6582af7 vsm4r.vs v21, v5 
62 | a66821f7 vsm4r.vs v3, v6 
63 | a6882b77 vsm4r.vs v22, v8 
64 | a6982d77 vsm4r.vs v26, v9 
65 | a6c82977 vsm4r.vs v18, v12 
66 | a6c82ef7 vsm4r.vs v29, v12 
67 | a6c82f77 vsm4r.vs v30, v12 
68 | a6d826f7 vsm4r.vs v13, v13 
69 | a6f82577 vsm4r.vs v10, v15 
70 | a6f82af7 vsm4r.vs v21, v15 
71 | a6f82df7 vsm4r.vs v27, v15 
72 | a72824f7 vsm4r.vs v9, v18 
73 | a7582277 vsm4r.vs v4, v21 
74 | a7682b77 vsm4r.vs v22, v22 
75 | a7882177 vsm4r.vs v2, v24 
76 | a7882677 vsm4r.vs v12, v24 
77 | a7982a77 vsm4r.vs v20, v25 
78 | a7982ef7 vsm4r.vs v29, v25 
79 | a7982ff7 vsm4r.vs v31, v25 
80 | a7a826f7 vsm4r.vs v13, v26 
81 | a7b824f7 vsm4r.vs v9, v27 
82 | a7d82277 vsm4r.vs v4, v29 
83 | a7e824f7 vsm4r.vs v9, v30 
84 | a7f82e77 vsm4r.vs v28, v31 
85 | 


--------------------------------------------------------------------------------
/test_data/rv64/rvzvksh.test:
--------------------------------------------------------------------------------
 1 | 8203aaf7 vsm3me.vv v21, v0, v7 
 2 | 8221a4f7 vsm3me.vv v9, v2, v3 
 3 | 823b2777 vsm3me.vv v14, v3, v22 
 4 | 823b28f7 vsm3me.vv v17, v3, v22 
 5 | 823bac77 vsm3me.vv v24, v3, v23 
 6 | 82442df7 vsm3me.vv v27, v4, v8 
 7 | 8253a777 vsm3me.vv v14, v5, v7 
 8 | 826fa477 vsm3me.vv v8, v6, v31 
 9 | 829323f7 vsm3me.vv v7, v9, v6 
10 | 82abae77 vsm3me.vv v28, v10, v23 
11 | 82aeaef7 vsm3me.vv v29, v10, v29 
12 | 82b52277 vsm3me.vv v4, v11, v10 
13 | 82b8aaf7 vsm3me.vv v21, v11, v17 
14 | 82c224f7 vsm3me.vv v9, v12, v4 
15 | 82c6a5f7 vsm3me.vv v11, v12, v13 
16 | 82d42777 vsm3me.vv v14, v13, v8 
17 | 82dca6f7 vsm3me.vv v13, v13, v25 
18 | 82e8a977 vsm3me.vv v18, v14, v17 
19 | 8302ab77 vsm3me.vv v22, v16, v5 
20 | 830a2c77 vsm3me.vv v24, v16, v20 
21 | 831caf77 vsm3me.vv v30, v17, v25 
22 | 833522f7 vsm3me.vv v5, v19, v10 
23 | 83442df7 vsm3me.vv v27, v20, v8 
24 | 834b2877 vsm3me.vv v16, v20, v22 
25 | 83a62cf7 vsm3me.vv v25, v26, v12 
26 | 83c1aef7 vsm3me.vv v29, v28, v3 
27 | 83d026f7 vsm3me.vv v13, v29, v0 
28 | 83df24f7 vsm3me.vv v9, v29, v30 
29 | 83f920f7 vsm3me.vv v1, v31, v18 
30 | 83fb26f7 vsm3me.vv v13, v31, v22 
31 | ae0023f7 vsm3c.vi v7, v0, 0x0 
32 | ae0e28f7 vsm3c.vi v17, v0, 0x1c 
33 | ae182877 vsm3c.vi v16, v1, 0x10 
34 | ae4cab77 vsm3c.vi v22, v4, 0x19 
35 | ae612677 vsm3c.vi v12, v6, 0x2 
36 | ae68a577 vsm3c.vi v10, v6, 0x11 
37 | ae7da6f7 vsm3c.vi v13, v7, 0x1b 
38 | ae8aaef7 vsm3c.vi v29, v8, 0x15 
39 | ae9fa777 vsm3c.vi v14, v9, 0x1f 
40 | aeaa29f7 vsm3c.vi v19, v10, 0x14 
41 | aeb42ef7 vsm3c.vi v29, v11, 0x8 
42 | aeb6a477 vsm3c.vi v8, v11, 0xd 
43 | aeb6adf7 vsm3c.vi v27, v11, 0xd 
44 | aecb24f7 vsm3c.vi v9, v12, 0x16 
45 | aeda28f7 vsm3c.vi v17, v13, 0x14 
46 | aef4a5f7 vsm3c.vi v11, v15, 0x9 
47 | af00aa77 vsm3c.vi v20, v16, 0x1 
48 | af152ef7 vsm3c.vi v29, v17, 0xa 
49 | af48abf7 vsm3c.vi v23, v20, 0x11 
50 | af6426f7 vsm3c.vi v13, v22, 0x8 
51 | af7f2cf7 vsm3c.vi v25, v23, 0x1e 
52 | af852cf7 vsm3c.vi v25, v24, 0xa 
53 | af8d2b77 vsm3c.vi v22, v24, 0x1a 
54 | af9f24f7 vsm3c.vi v9, v25, 0x1e 
55 | afa0a9f7 vsm3c.vi v19, v26, 0x1 
56 | afa22a77 vsm3c.vi v20, v26, 0x4 
57 | afc429f7 vsm3c.vi v19, v28, 0x8 
58 | 


--------------------------------------------------------------------------------
/toml-with-errors/mips.toml:
--------------------------------------------------------------------------------
  1 | set = "MIPS"
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["r", "i", "j", "branch", "mem"]
  6 | parts = [
  7 |     [
  8 |         "opcode",
  9 |         6,
 10 |         "u8",
 11 |     ],
 12 |     [
 13 |         "rs",
 14 |         5,
 15 |         "Register_int",
 16 |     ],
 17 |     [
 18 |         "rt",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rd",
 24 |         5,
 25 |         "Register_int",
 26 |     ],
 27 |     [
 28 |         "shamt",
 29 |         5,
 30 |         "u8",
 31 |     ],
 32 |     [
 33 |         "funct",
 34 |         6,
 35 |         "u8",
 36 |     ],
 37 |     [
 38 |         "imm",
 39 |         32,
 40 |         "VInt",
 41 |     ],
 42 |     [
 43 |         "addr",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 | ]
 48 | 
 49 | [types]
 50 | names = ["R", "I", "J", "B"]
 51 | R = [
 52 |     { name = "opcode", top = 5, bot = 0 },
 53 |     { name = "rs", top = 4, bot = 0 },
 54 |     { name = "rt", top = 4, bot = 0 },
 55 |     { name = "rd", top = 4, bot = 0 },
 56 |     { name = "shamt", top = 4, bot = 0 },
 57 |     { name = "funct", top = 5, bot = 0 },
 58 | ]
 59 | I = [
 60 |     { name = "opcode", top = 5, bot = 0 },
 61 |     { name = "rs", top = 4, bot = 0 },
 62 |     { name = "rt", top = 4, bot = 0 },
 63 |     { name = "imm", top = 15, bot = 0 },
 64 | ]
 65 | J = [
 66 |     { name = "opcode", top = 5, bot = 0 },
 67 |     { name = "addr", top = 25, bot = 0 },
 68 | ]
 69 | 
 70 | [r]
 71 | type = "R"
 72 | [r.repr]
 73 | default = "$name$ %rd%, %rs%, %rt%"
 74 | jr = "$name$ %rs%"
 75 | jalr = "$name$ %rd%, %rs%"
 76 | mfhi = "$name$ %rd%"
 77 | mthi = "$name$ %rd%"
 78 | mflo = "$name$ %rd%"
 79 | mtlo = "$name$ %rd%"
 80 | mfc0 = "$name$ %rd%"
 81 | [r.instructions]
 82 | sll = { mask = 0xfc00003f, match = 0x00 }
 83 | srl = { mask = 0xfc00003f, match = 0x02 }
 84 | sra = { mask = 0xfc00003f, match = 0x03 }
 85 | jr = { mask = 0xfc00003f, match = 0x08 }
 86 | jalr = { mask = 0xfc00003f, match = 0x09 }
 87 | mult = { mask = 0xfc00003f, match = 0x18 }
 88 | multu = { mask = 0xfc00003f, match = 0x19 }
 89 | add = { mask = 0xfc00003f, match = 0x20 }
 90 | addu = { mask = 0xfc00003f, match = 0x21 }
 91 | sub = { mask = 0xfc00003f, match = 0x22 }
 92 | subu = { mask = 0xfc00003f, match = 0x23 }
 93 | and = { mask = 0xfc00003f, match = 0x24 }
 94 | or = { mask = 0xfc00003f, match = 0x25 }
 95 | xor = { mask = 0xfc00003f, match = 0x26 }
 96 | nor = { mask = 0xfc00003f, match = 0x27 }
 97 | div = { mask = 0xfc00003f, match = 0x1a }
 98 | divu = { mask = 0xfc00003f, match = 0x1b }
 99 | slt = { mask = 0xfc00003f, match = 0x2a }
100 | sltu = { mask = 0xfc00003f, match = 0x2b }
101 | 
102 | [i]
103 | type = "I"
104 | [i.repr]
105 | default = "$name$ %rt%, %rs%, %imm%"
106 | [i.instructions]
107 | addi = { mask = 0xfc000000, match = 0x20000000 }
108 | addiu = { mask = 0xfc000000, match = 0x24000000 }
109 | andi = { mask = 0xfc000000, match = 0x30000000 }
110 | ori = { mask = 0xfc000000, match = 0x34000000 }
111 | slti = { mask = 0xfc000000, match = 0x28000000 }
112 | sltiu = { mask = 0xfc000000, match = 0x2c000000 }
113 | 
114 | 
115 | [branch]
116 | type = "I"
117 | [branch.repr]
118 | default = "$name$ %rs%, %rt%"
119 | [branch.instructions]
120 | beq = { mask = 0xfc00000000, match = 0x10000000 }
121 | bne = { mask = 0xfc00000000, match = 0x14000000 }
122 | blez = { mask = 0xfc00000000, match = 0x18000000 }
123 | bgtz = { mask = 0xfc00000000, match = 0x1c000000 }
124 | 
125 | [mem]
126 | type = "I"
127 | [mem.repr]
128 | default = "$name$ %rt%, %imm%(%rs%)"
129 | [mem.instructions]
130 | lb = { mask = 0xfc000000, match = 0x80000000 }
131 | lw = { mask = 0xfc000000, match = 0x8c000000 }
132 | lbu = { mask = 0xfc000000, match = 0x90000000 }
133 | lhu = { mask = 0xfc000000, match = 0x94000000 }
134 | sb = { mask = 0xfc000000, match = 0xa0000000 }
135 | sh = { mask = 0xfc000000, match = 0xa4000000 }
136 | sw = { mask = 0xfc000000, match = 0xac000000 }
137 | 
138 | [j]
139 | type = "J"
140 | [j.repr]
141 | default = "$name$ %addr%"
142 | [j.instructions]
143 | j = { mask = 0xfc000000, match = 0x08000000 }
144 | jal = { mask = 0xfc000000, match = 0x0c000000 }
145 | 
146 | [mappings]
147 | names = ["Register_int"]
148 | number = 32
149 | Register_int = [
150 |     "$zero",
151 |     "$at",
152 |     "$v0",
153 |     "$v1",
154 |     "$a0",
155 |     "$a1",
156 |     "$a2",
157 |     "$a3",
158 |     "$t0",
159 |     "$t1",
160 |     "$t2",
161 |     "$t3",
162 |     "$t4",
163 |     "$t5",
164 |     "$t6",
165 |     "$t7",
166 |     "$s0",
167 |     "$s1",
168 |     "$s2",
169 |     "$s3",
170 |     "$s4",
171 |     "$s5",
172 |     "$s6",
173 |     "$s7",
174 |     "$t8",
175 |     "$t9",
176 |     "$k0",
177 |     "$k1",
178 |     "$gp",
179 |     "$sp",
180 |     "$fp",
181 |     "$ra",
182 | ]
183 | 


--------------------------------------------------------------------------------
/toml/RV32A.toml:
--------------------------------------------------------------------------------
  1 | set = "RV32A" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format_1-0", "format_2-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "aqrl",
 39 |         2,
 40 |         "Mapping_ordering",
 41 |     ],
 42 |     [
 43 |         "none",
 44 |         32,
 45 |         "u32",
 46 |     ],
 47 |     [
 48 |         "imm",
 49 |         32,
 50 |         "VInt",
 51 |     ],
 52 |     [
 53 |         "himm",
 54 |         32,
 55 |         "VInt",
 56 |         "hex",
 57 |     ],
 58 | ]
 59 | 
 60 | [types]
 61 | names = ["type_1-0", "type_2-0"]
 62 | [[types.type_1-0]]
 63 | name = "none"
 64 | top = 31
 65 | bot = 27
 66 | 
 67 | [[types.type_1-0]]
 68 | name = "aqrl"
 69 | top = 1
 70 | bot = 0
 71 | 
 72 | [[types.type_1-0]]
 73 | name = "rs2_Register_int"
 74 | top = 4
 75 | bot = 0
 76 | 
 77 | [[types.type_1-0]]
 78 | name = "rs1_Register_int"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type_1-0]]
 83 | name = "none"
 84 | top = 14
 85 | bot = 12
 86 | 
 87 | [[types.type_1-0]]
 88 | name = "rd_Register_int"
 89 | top = 4
 90 | bot = 0
 91 | 
 92 | [[types.type_1-0]]
 93 | name = "none"
 94 | top = 6
 95 | bot = 0
 96 | 
 97 | [[types.type_2-0]]
 98 | name = "none"
 99 | top = 31
100 | bot = 27
101 | 
102 | [[types.type_2-0]]
103 | name = "aqrl"
104 | top = 1
105 | bot = 0
106 | 
107 | [[types.type_2-0]]
108 | name = "none"
109 | top = 24
110 | bot = 20
111 | 
112 | [[types.type_2-0]]
113 | name = "rs1_Register_int"
114 | top = 4
115 | bot = 0
116 | 
117 | [[types.type_2-0]]
118 | name = "none"
119 | top = 14
120 | bot = 12
121 | 
122 | [[types.type_2-0]]
123 | name = "rd_Register_int"
124 | top = 4
125 | bot = 0
126 | 
127 | [[types.type_2-0]]
128 | name = "none"
129 | top = 6
130 | bot = 0
131 | 
132 | [format_1-0]
133 | type = "type_1-0"
134 | 
135 | [format_2-0]
136 | type = "type_2-0"
137 | 
138 | [mappings]
139 | names = ["Register_int", "Register_float", "Mapping_ordering"]
140 | number = 32
141 | Register_int = [
142 |     "zero",
143 |     "ra",
144 |     "sp",
145 |     "gp",
146 |     "tp",
147 |     "t0",
148 |     "t1",
149 |     "t2",
150 |     "s0",
151 |     "s1",
152 |     "a0",
153 |     "a1",
154 |     "a2",
155 |     "a3",
156 |     "a4",
157 |     "a5",
158 |     "a6",
159 |     "a7",
160 |     "s2",
161 |     "s3",
162 |     "s4",
163 |     "s5",
164 |     "s6",
165 |     "s7",
166 |     "s8",
167 |     "s9",
168 |     "s10",
169 |     "s11",
170 |     "t3",
171 |     "t4",
172 |     "t5",
173 |     "t6",
174 | ]
175 | Register_float = [
176 |     "ft0",
177 |     "ft1",
178 |     "ft2",
179 |     "ft3",
180 |     "ft4",
181 |     "ft5",
182 |     "ft6",
183 |     "ft7",
184 |     "fs0",
185 |     "fs1",
186 |     "fa0",
187 |     "fa1",
188 |     "fa2",
189 |     "fa3",
190 |     "fa4",
191 |     "fa5",
192 |     "fa6",
193 |     "fa7",
194 |     "fs2",
195 |     "fs3",
196 |     "fs4",
197 |     "fs5",
198 |     "fs6",
199 |     "fs7",
200 |     "fs8",
201 |     "fs9",
202 |     "fs10",
203 |     "fs11",
204 |     "ft8",
205 |     "ft9",
206 |     "ft10",
207 |     "ft11",
208 | ]
209 | Mapping_ordering = ["", ".rl", ".aq", ".aqrl"]
210 | 
211 | [format_1-0.repr]
212 | default = "$name$%aqrl% %rd_Register_int%, %rs2_Register_int%, (%rs1_Register_int%)"
213 | 
214 | [format_2-0.repr]
215 | default = "$name$%aqrl% %rd_Register_int%, (%rs1_Register_int%)"
216 | 
217 | [format_1-0.instructions."amoadd.w"]
218 | mask = 0xf800707f
219 | match = 0x202f
220 | 
221 | [format_1-0.instructions."amoand.w"]
222 | mask = 0xf800707f
223 | match = 0x6000202f
224 | 
225 | [format_1-0.instructions."amomax.w"]
226 | mask = 0xf800707f
227 | match = 0xa000202f
228 | 
229 | [format_1-0.instructions."amomaxu.w"]
230 | mask = 0xf800707f
231 | match = 0xe000202f
232 | 
233 | [format_1-0.instructions."amomin.w"]
234 | mask = 0xf800707f
235 | match = 0x8000202f
236 | 
237 | [format_1-0.instructions."amominu.w"]
238 | mask = 0xf800707f
239 | match = 0xc000202f
240 | 
241 | [format_1-0.instructions."amoor.w"]
242 | mask = 0xf800707f
243 | match = 0x4000202f
244 | 
245 | [format_1-0.instructions."amoswap.w"]
246 | mask = 0xf800707f
247 | match = 0x800202f
248 | 
249 | [format_1-0.instructions."amoxor.w"]
250 | mask = 0xf800707f
251 | match = 0x2000202f
252 | 
253 | [format_1-0.instructions."sc.w"]
254 | mask = 0xf800707f
255 | match = 0x1800202f
256 | 
257 | [format_2-0.instructions."lr.w"]
258 | mask = 0xf9f0707f
259 | match = 0x1000202f
260 | 


--------------------------------------------------------------------------------
/toml/RV32M.toml:
--------------------------------------------------------------------------------
  1 | set = "RV32M" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format_1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "none",
 39 |         32,
 40 |         "u32",
 41 |     ],
 42 |     [
 43 |         "imm",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 |     [
 48 |         "himm",
 49 |         32,
 50 |         "VInt",
 51 |         "hex",
 52 |     ],
 53 | ]
 54 | 
 55 | [types]
 56 | names = ["type_1-0"]
 57 | [[types.type_1-0]]
 58 | name = "none"
 59 | top = 31
 60 | bot = 25
 61 | 
 62 | [[types.type_1-0]]
 63 | name = "rs2_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type_1-0]]
 68 | name = "rs1_Register_int"
 69 | top = 4
 70 | bot = 0
 71 | 
 72 | [[types.type_1-0]]
 73 | name = "none"
 74 | top = 14
 75 | bot = 12
 76 | 
 77 | [[types.type_1-0]]
 78 | name = "rd_Register_int"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type_1-0]]
 83 | name = "none"
 84 | top = 6
 85 | bot = 0
 86 | 
 87 | [format_1-0]
 88 | type = "type_1-0"
 89 | 
 90 | [mappings]
 91 | names = ["Register_int", "Register_float"]
 92 | number = 32
 93 | Register_int = [
 94 |     "zero",
 95 |     "ra",
 96 |     "sp",
 97 |     "gp",
 98 |     "tp",
 99 |     "t0",
100 |     "t1",
101 |     "t2",
102 |     "s0",
103 |     "s1",
104 |     "a0",
105 |     "a1",
106 |     "a2",
107 |     "a3",
108 |     "a4",
109 |     "a5",
110 |     "a6",
111 |     "a7",
112 |     "s2",
113 |     "s3",
114 |     "s4",
115 |     "s5",
116 |     "s6",
117 |     "s7",
118 |     "s8",
119 |     "s9",
120 |     "s10",
121 |     "s11",
122 |     "t3",
123 |     "t4",
124 |     "t5",
125 |     "t6",
126 | ]
127 | Register_float = [
128 |     "ft0",
129 |     "ft1",
130 |     "ft2",
131 |     "ft3",
132 |     "ft4",
133 |     "ft5",
134 |     "ft6",
135 |     "ft7",
136 |     "fs0",
137 |     "fs1",
138 |     "fa0",
139 |     "fa1",
140 |     "fa2",
141 |     "fa3",
142 |     "fa4",
143 |     "fa5",
144 |     "fa6",
145 |     "fa7",
146 |     "fs2",
147 |     "fs3",
148 |     "fs4",
149 |     "fs5",
150 |     "fs6",
151 |     "fs7",
152 |     "fs8",
153 |     "fs9",
154 |     "fs10",
155 |     "fs11",
156 |     "ft8",
157 |     "ft9",
158 |     "ft10",
159 |     "ft11",
160 | ]
161 | 
162 | [format_1-0.repr]
163 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
164 | 
165 | [format_1-0.instructions.div]
166 | mask = 0xfe00707f
167 | match = 0x2004033
168 | 
169 | [format_1-0.instructions.divu]
170 | mask = 0xfe00707f
171 | match = 0x2005033
172 | 
173 | [format_1-0.instructions.mul]
174 | mask = 0xfe00707f
175 | match = 0x2000033
176 | 
177 | [format_1-0.instructions.mulh]
178 | mask = 0xfe00707f
179 | match = 0x2001033
180 | 
181 | [format_1-0.instructions.mulhsu]
182 | mask = 0xfe00707f
183 | match = 0x2002033
184 | 
185 | [format_1-0.instructions.mulhu]
186 | mask = 0xfe00707f
187 | match = 0x2003033
188 | 
189 | [format_1-0.instructions.rem]
190 | mask = 0xfe00707f
191 | match = 0x2006033
192 | 
193 | [format_1-0.instructions.remu]
194 | mask = 0xfe00707f
195 | match = 0x2007033
196 | 


--------------------------------------------------------------------------------
/toml/RV32_Zacas.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZacas" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "aqrl",
 39 |         2,
 40 |         "Mapping_ordering",
 41 |     ],
 42 |     [
 43 |         "none",
 44 |         32,
 45 |         "u32",
 46 |     ],
 47 |     [
 48 |         "imm",
 49 |         32,
 50 |         "VInt",
 51 |     ],
 52 |     [
 53 |         "himm",
 54 |         32,
 55 |         "VInt",
 56 |         "hex",
 57 |     ],
 58 | ]
 59 | 
 60 | [types]
 61 | names = ["type-1-0"]
 62 | [[types.type-1-0]]
 63 | name = "none"
 64 | top = 31
 65 | bot = 27
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "aqrl"
 69 | top = 1
 70 | bot = 0
 71 | 
 72 | [[types.type-1-0]]
 73 | name = "rs2_Register_int"
 74 | top = 4
 75 | bot = 0
 76 | 
 77 | [[types.type-1-0]]
 78 | name = "rs1_Register_int"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "none"
 84 | top = 14
 85 | bot = 12
 86 | 
 87 | [[types.type-1-0]]
 88 | name = "rd_Register_int"
 89 | top = 4
 90 | bot = 0
 91 | 
 92 | [[types.type-1-0]]
 93 | name = "none"
 94 | top = 6
 95 | bot = 0
 96 | 
 97 | [format-1-0]
 98 | type = "type-1-0"
 99 | 
100 | [mappings]
101 | names = ["Register_int", "Register_float", "Mapping_ordering"]
102 | number = 32
103 | Register_int = [
104 |     "zero",
105 |     "ra",
106 |     "sp",
107 |     "gp",
108 |     "tp",
109 |     "t0",
110 |     "t1",
111 |     "t2",
112 |     "s0",
113 |     "s1",
114 |     "a0",
115 |     "a1",
116 |     "a2",
117 |     "a3",
118 |     "a4",
119 |     "a5",
120 |     "a6",
121 |     "a7",
122 |     "s2",
123 |     "s3",
124 |     "s4",
125 |     "s5",
126 |     "s6",
127 |     "s7",
128 |     "s8",
129 |     "s9",
130 |     "s10",
131 |     "s11",
132 |     "t3",
133 |     "t4",
134 |     "t5",
135 |     "t6",
136 | ]
137 | Register_float = [
138 |     "ft0",
139 |     "ft1",
140 |     "ft2",
141 |     "ft3",
142 |     "ft4",
143 |     "ft5",
144 |     "ft6",
145 |     "ft7",
146 |     "fs0",
147 |     "fs1",
148 |     "fa0",
149 |     "fa1",
150 |     "fa2",
151 |     "fa3",
152 |     "fa4",
153 |     "fa5",
154 |     "fa6",
155 |     "fa7",
156 |     "fs2",
157 |     "fs3",
158 |     "fs4",
159 |     "fs5",
160 |     "fs6",
161 |     "fs7",
162 |     "fs8",
163 |     "fs9",
164 |     "fs10",
165 |     "fs11",
166 |     "ft8",
167 |     "ft9",
168 |     "ft10",
169 |     "ft11",
170 | ]
171 | Mapping_ordering = ["", ".rl", ".aq", ".aqrl"]
172 | 
173 | [format-1-0.repr]
174 | default = "$name$%aqrl% %rd_Register_int%, %rs2_Register_int%, (%rs1_Register_int%)"
175 | 
176 | [format-1-0.instructions."amocas.d"]
177 | mask = 0xf800707f
178 | match = 0x2800302f
179 | 
180 | [format-1-0.instructions."amocas.w"]
181 | mask = 0xf800707f
182 | match = 0x2800202f
183 | 


--------------------------------------------------------------------------------
/toml/RV32_Zbb.toml:
--------------------------------------------------------------------------------
  1 | set = "RV32Zbb" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format_1-0", "format_2-0", "format_3-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "shamtw",
 39 |         5,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type_1-0", "type_2-0", "type_3-0"]
 63 | [[types.type_1-0]]
 64 | name = "none"
 65 | top = 31
 66 | bot = 25
 67 | 
 68 | [[types.type_1-0]]
 69 | name = "rs2_Register_int"
 70 | top = 4
 71 | bot = 0
 72 | 
 73 | [[types.type_1-0]]
 74 | name = "rs1_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type_1-0]]
 79 | name = "none"
 80 | top = 14
 81 | bot = 12
 82 | 
 83 | [[types.type_1-0]]
 84 | name = "rd_Register_int"
 85 | top = 4
 86 | bot = 0
 87 | 
 88 | [[types.type_1-0]]
 89 | name = "none"
 90 | top = 6
 91 | bot = 0
 92 | 
 93 | [[types.type_2-0]]
 94 | name = "none"
 95 | top = 31
 96 | bot = 20
 97 | 
 98 | [[types.type_2-0]]
 99 | name = "rs1_Register_int"
100 | top = 4
101 | bot = 0
102 | 
103 | [[types.type_2-0]]
104 | name = "none"
105 | top = 14
106 | bot = 12
107 | 
108 | [[types.type_2-0]]
109 | name = "rd_Register_int"
110 | top = 4
111 | bot = 0
112 | 
113 | [[types.type_2-0]]
114 | name = "none"
115 | top = 6
116 | bot = 0
117 | 
118 | [[types.type_3-0]]
119 | name = "none"
120 | top = 31
121 | bot = 25
122 | 
123 | [[types.type_3-0]]
124 | name = "shamtw"
125 | top = 4
126 | bot = 0
127 | 
128 | [[types.type_3-0]]
129 | name = "rs1_Register_int"
130 | top = 4
131 | bot = 0
132 | 
133 | [[types.type_3-0]]
134 | name = "none"
135 | top = 14
136 | bot = 12
137 | 
138 | [[types.type_3-0]]
139 | name = "rd_Register_int"
140 | top = 4
141 | bot = 0
142 | 
143 | [[types.type_3-0]]
144 | name = "none"
145 | top = 6
146 | bot = 0
147 | 
148 | [format_1-0]
149 | type = "type_1-0"
150 | 
151 | [format_2-0]
152 | type = "type_2-0"
153 | 
154 | [format_3-0]
155 | type = "type_3-0"
156 | 
157 | [mappings]
158 | names = ["Register_int", "Register_float"]
159 | number = 32
160 | Register_int = [
161 |     "zero",
162 |     "ra",
163 |     "sp",
164 |     "gp",
165 |     "tp",
166 |     "t0",
167 |     "t1",
168 |     "t2",
169 |     "s0",
170 |     "s1",
171 |     "a0",
172 |     "a1",
173 |     "a2",
174 |     "a3",
175 |     "a4",
176 |     "a5",
177 |     "a6",
178 |     "a7",
179 |     "s2",
180 |     "s3",
181 |     "s4",
182 |     "s5",
183 |     "s6",
184 |     "s7",
185 |     "s8",
186 |     "s9",
187 |     "s10",
188 |     "s11",
189 |     "t3",
190 |     "t4",
191 |     "t5",
192 |     "t6",
193 | ]
194 | Register_float = [
195 |     "ft0",
196 |     "ft1",
197 |     "ft2",
198 |     "ft3",
199 |     "ft4",
200 |     "ft5",
201 |     "ft6",
202 |     "ft7",
203 |     "fs0",
204 |     "fs1",
205 |     "fa0",
206 |     "fa1",
207 |     "fa2",
208 |     "fa3",
209 |     "fa4",
210 |     "fa5",
211 |     "fa6",
212 |     "fa7",
213 |     "fs2",
214 |     "fs3",
215 |     "fs4",
216 |     "fs5",
217 |     "fs6",
218 |     "fs7",
219 |     "fs8",
220 |     "fs9",
221 |     "fs10",
222 |     "fs11",
223 |     "ft8",
224 |     "ft9",
225 |     "ft10",
226 |     "ft11",
227 | ]
228 | 
229 | [format_1-0.repr]
230 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
231 | 
232 | [format_2-0.repr]
233 | default = "$name$ %rd_Register_int%, %rs1_Register_int%"
234 | 
235 | [format_3-0.repr]
236 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %shamtw%"
237 | 
238 | [format_1-0.instructions.andn]
239 | mask = 0xfe00707f
240 | match = 0x40007033
241 | 
242 | [format_1-0.instructions.max]
243 | mask = 0xfe00707f
244 | match = 0xa006033
245 | 
246 | [format_1-0.instructions.maxu]
247 | mask = 0xfe00707f
248 | match = 0xa007033
249 | 
250 | [format_1-0.instructions.min]
251 | mask = 0xfe00707f
252 | match = 0xa004033
253 | 
254 | [format_1-0.instructions.minu]
255 | mask = 0xfe00707f
256 | match = 0xa005033
257 | 
258 | [format_1-0.instructions.orn]
259 | mask = 0xfe00707f
260 | match = 0x40006033
261 | 
262 | [format_1-0.instructions.rol]
263 | mask = 0xfe00707f
264 | match = 0x60001033
265 | 
266 | [format_1-0.instructions.ror]
267 | mask = 0xfe00707f
268 | match = 0x60005033
269 | 
270 | [format_1-0.instructions.xnor]
271 | mask = 0xfe00707f
272 | match = 0x40004033
273 | 
274 | [format_2-0.instructions.clz]
275 | mask = 0xfff0707f
276 | match = 0x60001013
277 | 
278 | [format_2-0.instructions.cpop]
279 | mask = 0xfff0707f
280 | match = 0x60201013
281 | 
282 | [format_2-0.instructions.ctz]
283 | mask = 0xfff0707f
284 | match = 0x60101013
285 | 
286 | [format_2-0.instructions."orc.b"]
287 | mask = 0xfff0707f
288 | match = 0x28705013
289 | 
290 | [format_2-0.instructions.rev8]
291 | mask = 0xfff0707f
292 | match = 0x69805013
293 | 
294 | [format_2-0.instructions."sext.b"]
295 | mask = 0xfff0707f
296 | match = 0x60401013
297 | 
298 | [format_2-0.instructions."sext.h"]
299 | mask = 0xfff0707f
300 | match = 0x60501013
301 | 
302 | [format_2-0.instructions."zext.h"]
303 | mask = 0xfff0707f
304 | match = 0x8004033
305 | 
306 | [format_3-0.instructions.rori]
307 | mask = 0xfe00707f
308 | match = 0x60005013
309 | 


--------------------------------------------------------------------------------
/toml/RV32_Zbkb.toml:
--------------------------------------------------------------------------------
  1 | set = "RV32Zbkb" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0", "format-3-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "shamtw",
 39 |         5,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type-1-0", "type-2-0", "type-3-0"]
 63 | [[types.type-1-0]]
 64 | name = "none"
 65 | top = 31
 66 | bot = 25
 67 | 
 68 | [[types.type-1-0]]
 69 | name = "rs2_Register_int"
 70 | top = 4
 71 | bot = 0
 72 | 
 73 | [[types.type-1-0]]
 74 | name = "rs1_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type-1-0]]
 79 | name = "none"
 80 | top = 14
 81 | bot = 12
 82 | 
 83 | [[types.type-1-0]]
 84 | name = "rd_Register_int"
 85 | top = 4
 86 | bot = 0
 87 | 
 88 | [[types.type-1-0]]
 89 | name = "none"
 90 | top = 6
 91 | bot = 0
 92 | 
 93 | [[types.type-2-0]]
 94 | name = "none"
 95 | top = 31
 96 | bot = 20
 97 | 
 98 | [[types.type-2-0]]
 99 | name = "rs1_Register_int"
100 | top = 4
101 | bot = 0
102 | 
103 | [[types.type-2-0]]
104 | name = "none"
105 | top = 14
106 | bot = 12
107 | 
108 | [[types.type-2-0]]
109 | name = "rd_Register_int"
110 | top = 4
111 | bot = 0
112 | 
113 | [[types.type-2-0]]
114 | name = "none"
115 | top = 6
116 | bot = 0
117 | 
118 | [[types.type-3-0]]
119 | name = "none"
120 | top = 31
121 | bot = 25
122 | 
123 | [[types.type-3-0]]
124 | name = "shamtw"
125 | top = 4
126 | bot = 0
127 | 
128 | [[types.type-3-0]]
129 | name = "rs1_Register_int"
130 | top = 4
131 | bot = 0
132 | 
133 | [[types.type-3-0]]
134 | name = "none"
135 | top = 14
136 | bot = 12
137 | 
138 | [[types.type-3-0]]
139 | name = "rd_Register_int"
140 | top = 4
141 | bot = 0
142 | 
143 | [[types.type-3-0]]
144 | name = "none"
145 | top = 6
146 | bot = 0
147 | 
148 | [format-1-0]
149 | type = "type-1-0"
150 | 
151 | [format-2-0]
152 | type = "type-2-0"
153 | 
154 | [format-3-0]
155 | type = "type-3-0"
156 | 
157 | [mappings]
158 | names = ["Register_int", "Register_float"]
159 | number = 32
160 | Register_int = [
161 |     "zero",
162 |     "ra",
163 |     "sp",
164 |     "gp",
165 |     "tp",
166 |     "t0",
167 |     "t1",
168 |     "t2",
169 |     "s0",
170 |     "s1",
171 |     "a0",
172 |     "a1",
173 |     "a2",
174 |     "a3",
175 |     "a4",
176 |     "a5",
177 |     "a6",
178 |     "a7",
179 |     "s2",
180 |     "s3",
181 |     "s4",
182 |     "s5",
183 |     "s6",
184 |     "s7",
185 |     "s8",
186 |     "s9",
187 |     "s10",
188 |     "s11",
189 |     "t3",
190 |     "t4",
191 |     "t5",
192 |     "t6",
193 | ]
194 | Register_float = [
195 |     "ft0",
196 |     "ft1",
197 |     "ft2",
198 |     "ft3",
199 |     "ft4",
200 |     "ft5",
201 |     "ft6",
202 |     "ft7",
203 |     "fs0",
204 |     "fs1",
205 |     "fa0",
206 |     "fa1",
207 |     "fa2",
208 |     "fa3",
209 |     "fa4",
210 |     "fa5",
211 |     "fa6",
212 |     "fa7",
213 |     "fs2",
214 |     "fs3",
215 |     "fs4",
216 |     "fs5",
217 |     "fs6",
218 |     "fs7",
219 |     "fs8",
220 |     "fs9",
221 |     "fs10",
222 |     "fs11",
223 |     "ft8",
224 |     "ft9",
225 |     "ft10",
226 |     "ft11",
227 | ]
228 | 
229 | [format-1-0.repr]
230 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
231 | 
232 | [format-2-0.repr]
233 | default = "$name$ %rd_Register_int%, %rs1_Register_int%"
234 | 
235 | [format-3-0.repr]
236 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %shamtw%"
237 | 
238 | [format-1-0.instructions.andn]
239 | mask = 0xfe00707f
240 | match = 0x40007033
241 | 
242 | [format-1-0.instructions.orn]
243 | mask = 0xfe00707f
244 | match = 0x40006033
245 | 
246 | [format-1-0.instructions.pack]
247 | mask = 0xfe00707f
248 | match = 0x8004033
249 | 
250 | [format-1-0.instructions.packh]
251 | mask = 0xfe00707f
252 | match = 0x8007033
253 | 
254 | [format-1-0.instructions.rol]
255 | mask = 0xfe00707f
256 | match = 0x60001033
257 | 
258 | [format-1-0.instructions.ror]
259 | mask = 0xfe00707f
260 | match = 0x60005033
261 | 
262 | [format-1-0.instructions.xnor]
263 | mask = 0xfe00707f
264 | match = 0x40004033
265 | 
266 | [format-2-0.instructions.brev8]
267 | mask = 0xfff0707f
268 | match = 0x68705013
269 | 
270 | [format-2-0.instructions.rev8]
271 | mask = 0xfff0707f
272 | match = 0x69805013
273 | 
274 | [format-2-0.instructions.unzip]
275 | mask = 0xfff0707f
276 | match = 0x8f05013
277 | 
278 | [format-2-0.instructions.zip]
279 | mask = 0xfff0707f
280 | match = 0x8f01013
281 | 
282 | [format-3-0.instructions.rori]
283 | mask = 0xfe00707f
284 | match = 0x60005013
285 | 


--------------------------------------------------------------------------------
/toml/RV32_Zbs.toml:
--------------------------------------------------------------------------------
  1 | set = "RV32Zbs" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format_1-0", "format_2-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "shamtw",
 39 |         5,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type_1-0", "type_2-0"]
 63 | [[types.type_1-0]]
 64 | name = "none"
 65 | top = 31
 66 | bot = 25
 67 | 
 68 | [[types.type_1-0]]
 69 | name = "rs2_Register_int"
 70 | top = 4
 71 | bot = 0
 72 | 
 73 | [[types.type_1-0]]
 74 | name = "rs1_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type_1-0]]
 79 | name = "none"
 80 | top = 14
 81 | bot = 12
 82 | 
 83 | [[types.type_1-0]]
 84 | name = "rd_Register_int"
 85 | top = 4
 86 | bot = 0
 87 | 
 88 | [[types.type_1-0]]
 89 | name = "none"
 90 | top = 6
 91 | bot = 0
 92 | 
 93 | [[types.type_2-0]]
 94 | name = "none"
 95 | top = 31
 96 | bot = 25
 97 | 
 98 | [[types.type_2-0]]
 99 | name = "shamtw"
100 | top = 4
101 | bot = 0
102 | 
103 | [[types.type_2-0]]
104 | name = "rs1_Register_int"
105 | top = 4
106 | bot = 0
107 | 
108 | [[types.type_2-0]]
109 | name = "none"
110 | top = 14
111 | bot = 12
112 | 
113 | [[types.type_2-0]]
114 | name = "rd_Register_int"
115 | top = 4
116 | bot = 0
117 | 
118 | [[types.type_2-0]]
119 | name = "none"
120 | top = 6
121 | bot = 0
122 | 
123 | [format_1-0]
124 | type = "type_1-0"
125 | 
126 | [format_2-0]
127 | type = "type_2-0"
128 | 
129 | [mappings]
130 | names = ["Register_int", "Register_float"]
131 | number = 32
132 | Register_int = [
133 |     "zero",
134 |     "ra",
135 |     "sp",
136 |     "gp",
137 |     "tp",
138 |     "t0",
139 |     "t1",
140 |     "t2",
141 |     "s0",
142 |     "s1",
143 |     "a0",
144 |     "a1",
145 |     "a2",
146 |     "a3",
147 |     "a4",
148 |     "a5",
149 |     "a6",
150 |     "a7",
151 |     "s2",
152 |     "s3",
153 |     "s4",
154 |     "s5",
155 |     "s6",
156 |     "s7",
157 |     "s8",
158 |     "s9",
159 |     "s10",
160 |     "s11",
161 |     "t3",
162 |     "t4",
163 |     "t5",
164 |     "t6",
165 | ]
166 | Register_float = [
167 |     "ft0",
168 |     "ft1",
169 |     "ft2",
170 |     "ft3",
171 |     "ft4",
172 |     "ft5",
173 |     "ft6",
174 |     "ft7",
175 |     "fs0",
176 |     "fs1",
177 |     "fa0",
178 |     "fa1",
179 |     "fa2",
180 |     "fa3",
181 |     "fa4",
182 |     "fa5",
183 |     "fa6",
184 |     "fa7",
185 |     "fs2",
186 |     "fs3",
187 |     "fs4",
188 |     "fs5",
189 |     "fs6",
190 |     "fs7",
191 |     "fs8",
192 |     "fs9",
193 |     "fs10",
194 |     "fs11",
195 |     "ft8",
196 |     "ft9",
197 |     "ft10",
198 |     "ft11",
199 | ]
200 | 
201 | [format_1-0.repr]
202 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
203 | 
204 | [format_2-0.repr]
205 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %shamtw%"
206 | 
207 | [format_1-0.instructions.bclr]
208 | mask = 0xfe00707f
209 | match = 0x48001033
210 | 
211 | [format_1-0.instructions.bext]
212 | mask = 0xfe00707f
213 | match = 0x48005033
214 | 
215 | [format_1-0.instructions.binv]
216 | mask = 0xfe00707f
217 | match = 0x68001033
218 | 
219 | [format_1-0.instructions.bset]
220 | mask = 0xfe00707f
221 | match = 0x28001033
222 | 
223 | [format_2-0.instructions.bclri]
224 | mask = 0xfe00707f
225 | match = 0x48001013
226 | 
227 | [format_2-0.instructions.bexti]
228 | mask = 0xfe00707f
229 | match = 0x48005013
230 | 
231 | [format_2-0.instructions.binvi]
232 | mask = 0xfe00707f
233 | match = 0x68001013
234 | 
235 | [format_2-0.instructions.bseti]
236 | mask = 0xfe00707f
237 | match = 0x28001013
238 | 


--------------------------------------------------------------------------------
/toml/RV32_Zknd.toml:
--------------------------------------------------------------------------------
  1 | set = "RV32Zknd" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "bs",
 39 |         2,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type-1-0"]
 63 | [[types.type-1-0]]
 64 | name = "bs"
 65 | top = 1
 66 | bot = 0
 67 | 
 68 | [[types.type-1-0]]
 69 | name = "none"
 70 | top = 29
 71 | bot = 25
 72 | 
 73 | [[types.type-1-0]]
 74 | name = "rs2_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type-1-0]]
 79 | name = "rs1_Register_int"
 80 | top = 4
 81 | bot = 0
 82 | 
 83 | [[types.type-1-0]]
 84 | name = "none"
 85 | top = 14
 86 | bot = 12
 87 | 
 88 | [[types.type-1-0]]
 89 | name = "rd_Register_int"
 90 | top = 4
 91 | bot = 0
 92 | 
 93 | [[types.type-1-0]]
 94 | name = "none"
 95 | top = 6
 96 | bot = 0
 97 | 
 98 | [format-1-0]
 99 | type = "type-1-0"
100 | 
101 | [mappings]
102 | names = ["Register_int", "Register_float"]
103 | number = 32
104 | Register_int = [
105 |     "zero",
106 |     "ra",
107 |     "sp",
108 |     "gp",
109 |     "tp",
110 |     "t0",
111 |     "t1",
112 |     "t2",
113 |     "s0",
114 |     "s1",
115 |     "a0",
116 |     "a1",
117 |     "a2",
118 |     "a3",
119 |     "a4",
120 |     "a5",
121 |     "a6",
122 |     "a7",
123 |     "s2",
124 |     "s3",
125 |     "s4",
126 |     "s5",
127 |     "s6",
128 |     "s7",
129 |     "s8",
130 |     "s9",
131 |     "s10",
132 |     "s11",
133 |     "t3",
134 |     "t4",
135 |     "t5",
136 |     "t6",
137 | ]
138 | Register_float = [
139 |     "ft0",
140 |     "ft1",
141 |     "ft2",
142 |     "ft3",
143 |     "ft4",
144 |     "ft5",
145 |     "ft6",
146 |     "ft7",
147 |     "fs0",
148 |     "fs1",
149 |     "fa0",
150 |     "fa1",
151 |     "fa2",
152 |     "fa3",
153 |     "fa4",
154 |     "fa5",
155 |     "fa6",
156 |     "fa7",
157 |     "fs2",
158 |     "fs3",
159 |     "fs4",
160 |     "fs5",
161 |     "fs6",
162 |     "fs7",
163 |     "fs8",
164 |     "fs9",
165 |     "fs10",
166 |     "fs11",
167 |     "ft8",
168 |     "ft9",
169 |     "ft10",
170 |     "ft11",
171 | ]
172 | 
173 | [format-1-0.repr]
174 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%, %bs%"
175 | 
176 | [format-1-0.instructions.aes32dsi]
177 | mask = 0x3e00707f
178 | match = 0x2a000033
179 | 
180 | [format-1-0.instructions.aes32dsmi]
181 | mask = 0x3e00707f
182 | match = 0x2e000033
183 | 


--------------------------------------------------------------------------------
/toml/RV32_Zkne.toml:
--------------------------------------------------------------------------------
  1 | set = "RV32Zkne" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "bs",
 39 |         2,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type-1-0"]
 63 | [[types.type-1-0]]
 64 | name = "bs"
 65 | top = 1
 66 | bot = 0
 67 | 
 68 | [[types.type-1-0]]
 69 | name = "none"
 70 | top = 29
 71 | bot = 25
 72 | 
 73 | [[types.type-1-0]]
 74 | name = "rs2_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type-1-0]]
 79 | name = "rs1_Register_int"
 80 | top = 4
 81 | bot = 0
 82 | 
 83 | [[types.type-1-0]]
 84 | name = "none"
 85 | top = 14
 86 | bot = 12
 87 | 
 88 | [[types.type-1-0]]
 89 | name = "rd_Register_int"
 90 | top = 4
 91 | bot = 0
 92 | 
 93 | [[types.type-1-0]]
 94 | name = "none"
 95 | top = 6
 96 | bot = 0
 97 | 
 98 | [format-1-0]
 99 | type = "type-1-0"
100 | 
101 | [mappings]
102 | names = ["Register_int", "Register_float"]
103 | number = 32
104 | Register_int = [
105 |     "zero",
106 |     "ra",
107 |     "sp",
108 |     "gp",
109 |     "tp",
110 |     "t0",
111 |     "t1",
112 |     "t2",
113 |     "s0",
114 |     "s1",
115 |     "a0",
116 |     "a1",
117 |     "a2",
118 |     "a3",
119 |     "a4",
120 |     "a5",
121 |     "a6",
122 |     "a7",
123 |     "s2",
124 |     "s3",
125 |     "s4",
126 |     "s5",
127 |     "s6",
128 |     "s7",
129 |     "s8",
130 |     "s9",
131 |     "s10",
132 |     "s11",
133 |     "t3",
134 |     "t4",
135 |     "t5",
136 |     "t6",
137 | ]
138 | Register_float = [
139 |     "ft0",
140 |     "ft1",
141 |     "ft2",
142 |     "ft3",
143 |     "ft4",
144 |     "ft5",
145 |     "ft6",
146 |     "ft7",
147 |     "fs0",
148 |     "fs1",
149 |     "fa0",
150 |     "fa1",
151 |     "fa2",
152 |     "fa3",
153 |     "fa4",
154 |     "fa5",
155 |     "fa6",
156 |     "fa7",
157 |     "fs2",
158 |     "fs3",
159 |     "fs4",
160 |     "fs5",
161 |     "fs6",
162 |     "fs7",
163 |     "fs8",
164 |     "fs9",
165 |     "fs10",
166 |     "fs11",
167 |     "ft8",
168 |     "ft9",
169 |     "ft10",
170 |     "ft11",
171 | ]
172 | 
173 | [format-1-0.repr]
174 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%, %bs%"
175 | 
176 | [format-1-0.instructions.aes32esi]
177 | mask = 0x3e00707f
178 | match = 0x22000033
179 | 
180 | [format-1-0.instructions.aes32esmi]
181 | mask = 0x3e00707f
182 | match = 0x26000033
183 | 


--------------------------------------------------------------------------------
/toml/RV64M.toml:
--------------------------------------------------------------------------------
  1 | set = "RV64M" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "none",
 39 |         32,
 40 |         "u32",
 41 |     ],
 42 |     [
 43 |         "imm",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 |     [
 48 |         "himm",
 49 |         32,
 50 |         "VInt",
 51 |         "hex",
 52 |     ],
 53 | ]
 54 | 
 55 | [types]
 56 | names = ["type-1-0"]
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 31
 60 | bot = 25
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "rs2_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "rs1_Register_int"
 69 | top = 4
 70 | bot = 0
 71 | 
 72 | [[types.type-1-0]]
 73 | name = "none"
 74 | top = 14
 75 | bot = 12
 76 | 
 77 | [[types.type-1-0]]
 78 | name = "rd_Register_int"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "none"
 84 | top = 6
 85 | bot = 0
 86 | 
 87 | [format-1-0]
 88 | type = "type-1-0"
 89 | 
 90 | [mappings]
 91 | names = ["Register_int", "Register_float"]
 92 | number = 32
 93 | Register_int = [
 94 |     "zero",
 95 |     "ra",
 96 |     "sp",
 97 |     "gp",
 98 |     "tp",
 99 |     "t0",
100 |     "t1",
101 |     "t2",
102 |     "s0",
103 |     "s1",
104 |     "a0",
105 |     "a1",
106 |     "a2",
107 |     "a3",
108 |     "a4",
109 |     "a5",
110 |     "a6",
111 |     "a7",
112 |     "s2",
113 |     "s3",
114 |     "s4",
115 |     "s5",
116 |     "s6",
117 |     "s7",
118 |     "s8",
119 |     "s9",
120 |     "s10",
121 |     "s11",
122 |     "t3",
123 |     "t4",
124 |     "t5",
125 |     "t6",
126 | ]
127 | Register_float = [
128 |     "ft0",
129 |     "ft1",
130 |     "ft2",
131 |     "ft3",
132 |     "ft4",
133 |     "ft5",
134 |     "ft6",
135 |     "ft7",
136 |     "fs0",
137 |     "fs1",
138 |     "fa0",
139 |     "fa1",
140 |     "fa2",
141 |     "fa3",
142 |     "fa4",
143 |     "fa5",
144 |     "fa6",
145 |     "fa7",
146 |     "fs2",
147 |     "fs3",
148 |     "fs4",
149 |     "fs5",
150 |     "fs6",
151 |     "fs7",
152 |     "fs8",
153 |     "fs9",
154 |     "fs10",
155 |     "fs11",
156 |     "ft8",
157 |     "ft9",
158 |     "ft10",
159 |     "ft11",
160 | ]
161 | 
162 | [format-1-0.repr]
163 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
164 | 
165 | [format-1-0.instructions.div]
166 | mask = 0xfe00707f
167 | match = 0x2004033
168 | 
169 | [format-1-0.instructions.divu]
170 | mask = 0xfe00707f
171 | match = 0x2005033
172 | 
173 | [format-1-0.instructions.divuw]
174 | mask = 0xfe00707f
175 | match = 0x200503b
176 | 
177 | [format-1-0.instructions.divw]
178 | mask = 0xfe00707f
179 | match = 0x200403b
180 | 
181 | [format-1-0.instructions.mul]
182 | mask = 0xfe00707f
183 | match = 0x2000033
184 | 
185 | [format-1-0.instructions.mulh]
186 | mask = 0xfe00707f
187 | match = 0x2001033
188 | 
189 | [format-1-0.instructions.mulhsu]
190 | mask = 0xfe00707f
191 | match = 0x2002033
192 | 
193 | [format-1-0.instructions.mulhu]
194 | mask = 0xfe00707f
195 | match = 0x2003033
196 | 
197 | [format-1-0.instructions.mulw]
198 | mask = 0xfe00707f
199 | match = 0x200003b
200 | 
201 | [format-1-0.instructions.rem]
202 | mask = 0xfe00707f
203 | match = 0x2006033
204 | 
205 | [format-1-0.instructions.remu]
206 | mask = 0xfe00707f
207 | match = 0x2007033
208 | 
209 | [format-1-0.instructions.remuw]
210 | mask = 0xfe00707f
211 | match = 0x200703b
212 | 
213 | [format-1-0.instructions.remw]
214 | mask = 0xfe00707f
215 | match = 0x200603b
216 | 


--------------------------------------------------------------------------------
/toml/RV64_Zacas.toml:
--------------------------------------------------------------------------------
  1 | set = "RV64Zacas" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "aqrl",
 39 |         2,
 40 |         "Mapping_ordering",
 41 |     ],
 42 |     [
 43 |         "none",
 44 |         32,
 45 |         "u32",
 46 |     ],
 47 |     [
 48 |         "imm",
 49 |         32,
 50 |         "VInt",
 51 |     ],
 52 |     [
 53 |         "himm",
 54 |         32,
 55 |         "VInt",
 56 |         "hex",
 57 |     ],
 58 | ]
 59 | 
 60 | [types]
 61 | names = ["type-1-0"]
 62 | [[types.type-1-0]]
 63 | name = "none"
 64 | top = 31
 65 | bot = 27
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "aqrl"
 69 | top = 1
 70 | bot = 0
 71 | 
 72 | [[types.type-1-0]]
 73 | name = "rs2_Register_int"
 74 | top = 4
 75 | bot = 0
 76 | 
 77 | [[types.type-1-0]]
 78 | name = "rs1_Register_int"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "none"
 84 | top = 14
 85 | bot = 12
 86 | 
 87 | [[types.type-1-0]]
 88 | name = "rd_Register_int"
 89 | top = 4
 90 | bot = 0
 91 | 
 92 | [[types.type-1-0]]
 93 | name = "none"
 94 | top = 6
 95 | bot = 0
 96 | 
 97 | [format-1-0]
 98 | type = "type-1-0"
 99 | 
100 | [mappings]
101 | names = ["Register_int", "Register_float", "Mapping_ordering"]
102 | number = 32
103 | Register_int = [
104 |     "zero",
105 |     "ra",
106 |     "sp",
107 |     "gp",
108 |     "tp",
109 |     "t0",
110 |     "t1",
111 |     "t2",
112 |     "s0",
113 |     "s1",
114 |     "a0",
115 |     "a1",
116 |     "a2",
117 |     "a3",
118 |     "a4",
119 |     "a5",
120 |     "a6",
121 |     "a7",
122 |     "s2",
123 |     "s3",
124 |     "s4",
125 |     "s5",
126 |     "s6",
127 |     "s7",
128 |     "s8",
129 |     "s9",
130 |     "s10",
131 |     "s11",
132 |     "t3",
133 |     "t4",
134 |     "t5",
135 |     "t6",
136 | ]
137 | Register_float = [
138 |     "ft0",
139 |     "ft1",
140 |     "ft2",
141 |     "ft3",
142 |     "ft4",
143 |     "ft5",
144 |     "ft6",
145 |     "ft7",
146 |     "fs0",
147 |     "fs1",
148 |     "fa0",
149 |     "fa1",
150 |     "fa2",
151 |     "fa3",
152 |     "fa4",
153 |     "fa5",
154 |     "fa6",
155 |     "fa7",
156 |     "fs2",
157 |     "fs3",
158 |     "fs4",
159 |     "fs5",
160 |     "fs6",
161 |     "fs7",
162 |     "fs8",
163 |     "fs9",
164 |     "fs10",
165 |     "fs11",
166 |     "ft8",
167 |     "ft9",
168 |     "ft10",
169 |     "ft11",
170 | ]
171 | Mapping_ordering = ["", ".rl", ".aq", ".aqrl"]
172 | 
173 | [format-1-0.repr]
174 | default = "$name$%aqrl% %rd_Register_int%, %rs2_Register_int%, (%rs1_Register_int%)"
175 | 
176 | [format-1-0.instructions."amocas.d"]
177 | mask = 0xf800707f
178 | match = 0x2800302f
179 | 
180 | [format-1-0.instructions."amocas.q"]
181 | mask = 0xf800707f
182 | match = 0x2800402f
183 | 
184 | [format-1-0.instructions."amocas.w"]
185 | mask = 0xf800707f
186 | match = 0x2800202f
187 | 


--------------------------------------------------------------------------------
/toml/RV64_Zbs.toml:
--------------------------------------------------------------------------------
  1 | set = "RV64Zbs" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format_1-0", "format_2-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "shamtd",
 39 |         6,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type_1-0", "type_2-0"]
 63 | [[types.type_1-0]]
 64 | name = "none"
 65 | top = 31
 66 | bot = 25
 67 | 
 68 | [[types.type_1-0]]
 69 | name = "rs2_Register_int"
 70 | top = 4
 71 | bot = 0
 72 | 
 73 | [[types.type_1-0]]
 74 | name = "rs1_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type_1-0]]
 79 | name = "none"
 80 | top = 14
 81 | bot = 12
 82 | 
 83 | [[types.type_1-0]]
 84 | name = "rd_Register_int"
 85 | top = 4
 86 | bot = 0
 87 | 
 88 | [[types.type_1-0]]
 89 | name = "none"
 90 | top = 6
 91 | bot = 0
 92 | 
 93 | [[types.type_2-0]]
 94 | name = "none"
 95 | top = 31
 96 | bot = 26
 97 | 
 98 | [[types.type_2-0]]
 99 | name = "shamtd"
100 | top = 5
101 | bot = 0
102 | 
103 | [[types.type_2-0]]
104 | name = "rs1_Register_int"
105 | top = 4
106 | bot = 0
107 | 
108 | [[types.type_2-0]]
109 | name = "none"
110 | top = 14
111 | bot = 12
112 | 
113 | [[types.type_2-0]]
114 | name = "rd_Register_int"
115 | top = 4
116 | bot = 0
117 | 
118 | [[types.type_2-0]]
119 | name = "none"
120 | top = 6
121 | bot = 0
122 | 
123 | [format_1-0]
124 | type = "type_1-0"
125 | 
126 | [format_2-0]
127 | type = "type_2-0"
128 | 
129 | [mappings]
130 | names = ["Register_int", "Register_float"]
131 | number = 32
132 | Register_int = [
133 |     "zero",
134 |     "ra",
135 |     "sp",
136 |     "gp",
137 |     "tp",
138 |     "t0",
139 |     "t1",
140 |     "t2",
141 |     "s0",
142 |     "s1",
143 |     "a0",
144 |     "a1",
145 |     "a2",
146 |     "a3",
147 |     "a4",
148 |     "a5",
149 |     "a6",
150 |     "a7",
151 |     "s2",
152 |     "s3",
153 |     "s4",
154 |     "s5",
155 |     "s6",
156 |     "s7",
157 |     "s8",
158 |     "s9",
159 |     "s10",
160 |     "s11",
161 |     "t3",
162 |     "t4",
163 |     "t5",
164 |     "t6",
165 | ]
166 | Register_float = [
167 |     "ft0",
168 |     "ft1",
169 |     "ft2",
170 |     "ft3",
171 |     "ft4",
172 |     "ft5",
173 |     "ft6",
174 |     "ft7",
175 |     "fs0",
176 |     "fs1",
177 |     "fa0",
178 |     "fa1",
179 |     "fa2",
180 |     "fa3",
181 |     "fa4",
182 |     "fa5",
183 |     "fa6",
184 |     "fa7",
185 |     "fs2",
186 |     "fs3",
187 |     "fs4",
188 |     "fs5",
189 |     "fs6",
190 |     "fs7",
191 |     "fs8",
192 |     "fs9",
193 |     "fs10",
194 |     "fs11",
195 |     "ft8",
196 |     "ft9",
197 |     "ft10",
198 |     "ft11",
199 | ]
200 | 
201 | [format_1-0.repr]
202 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
203 | 
204 | [format_2-0.repr]
205 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %shamtd%"
206 | 
207 | [format_1-0.instructions.bclr]
208 | mask = 0xfe00707f
209 | match = 0x48001033
210 | 
211 | [format_1-0.instructions.bext]
212 | mask = 0xfe00707f
213 | match = 0x48005033
214 | 
215 | [format_1-0.instructions.binv]
216 | mask = 0xfe00707f
217 | match = 0x68001033
218 | 
219 | [format_1-0.instructions.bset]
220 | mask = 0xfe00707f
221 | match = 0x28001033
222 | 
223 | [format_2-0.instructions.bclri]
224 | mask = 0xfc00707f
225 | match = 0x48001013
226 | 
227 | [format_2-0.instructions.bexti]
228 | mask = 0xfc00707f
229 | match = 0x48005013
230 | 
231 | [format_2-0.instructions.binvi]
232 | mask = 0xfc00707f
233 | match = 0x68001013
234 | 
235 | [format_2-0.instructions.bseti]
236 | mask = 0xfc00707f
237 | match = 0x28001013
238 | 


--------------------------------------------------------------------------------
/toml/RV64_Zcd-lower.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZcd" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-1", "format-3-0", "format-4-1"]
  6 | parts = [
  7 |     [
  8 |         "rd_p_Register_int_c",
  9 |         3,
 10 |         "Register_int_c",
 11 |     ],
 12 |     [
 13 |         "rd_p_Register_float_c",
 14 |         3,
 15 |         "Register_float_c",
 16 |     ],
 17 |     [
 18 |         "rs1_p_Register_int_c",
 19 |         3,
 20 |         "Register_int_c",
 21 |     ],
 22 |     [
 23 |         "rs1_p_Register_float_c",
 24 |         3,
 25 |         "Register_float_c",
 26 |     ],
 27 |     [
 28 |         "rd_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rd_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "rs2_p_Register_int_c",
 39 |         3,
 40 |         "Register_int_c",
 41 |     ],
 42 |     [
 43 |         "rs2_p_Register_float_c",
 44 |         3,
 45 |         "Register_float_c",
 46 |     ],
 47 |     [
 48 |         "c_rs2_Register_int",
 49 |         5,
 50 |         "Register_int",
 51 |     ],
 52 |     [
 53 |         "c_rs2_Register_float",
 54 |         5,
 55 |         "Register_float",
 56 |     ],
 57 |     [
 58 |         "none",
 59 |         32,
 60 |         "u32",
 61 |     ],
 62 |     [
 63 |         "imm",
 64 |         32,
 65 |         "VInt",
 66 |     ],
 67 |     [
 68 |         "himm",
 69 |         32,
 70 |         "VInt",
 71 |         "hex",
 72 |     ],
 73 | ]
 74 | 
 75 | [types]
 76 | names = ["type-1-0", "type-2-1", "type-3-0", "type-4-1"]
 77 | [[types.type-1-0]]
 78 | name = "none"
 79 | top = 31
 80 | bot = 13
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "himm"
 84 | top = 5
 85 | bot = 3
 86 | 
 87 | [[types.type-1-0]]
 88 | name = "rs1_p_Register_int_c"
 89 | top = 2
 90 | bot = 0
 91 | 
 92 | [[types.type-1-0]]
 93 | name = "himm"
 94 | top = 7
 95 | bot = 6
 96 | 
 97 | [[types.type-1-0]]
 98 | name = "rd_p_Register_float_c"
 99 | top = 2
100 | bot = 0
101 | 
102 | [[types.type-1-0]]
103 | name = "none"
104 | top = 1
105 | bot = 0
106 | 
107 | [[types.type-2-1]]
108 | name = "none"
109 | top = 31
110 | bot = 13
111 | 
112 | [[types.type-2-1]]
113 | name = "himm"
114 | top = 5
115 | bot = 5
116 | 
117 | [[types.type-2-1]]
118 | name = "rd_Register_float"
119 | top = 4
120 | bot = 0
121 | 
122 | [[types.type-2-1]]
123 | name = "himm"
124 | top = 4
125 | bot = 3
126 | 
127 | [[types.type-2-1]]
128 | name = "himm"
129 | top = 8
130 | bot = 6
131 | 
132 | [[types.type-2-1]]
133 | name = "none"
134 | top = 1
135 | bot = 0
136 | 
137 | [[types.type-3-0]]
138 | name = "none"
139 | top = 31
140 | bot = 13
141 | 
142 | [[types.type-3-0]]
143 | name = "himm"
144 | top = 5
145 | bot = 3
146 | 
147 | [[types.type-3-0]]
148 | name = "rs1_p_Register_int_c"
149 | top = 2
150 | bot = 0
151 | 
152 | [[types.type-3-0]]
153 | name = "himm"
154 | top = 7
155 | bot = 6
156 | 
157 | [[types.type-3-0]]
158 | name = "rs2_p_Register_float_c"
159 | top = 2
160 | bot = 0
161 | 
162 | [[types.type-3-0]]
163 | name = "none"
164 | top = 1
165 | bot = 0
166 | 
167 | [[types.type-4-1]]
168 | name = "none"
169 | top = 31
170 | bot = 13
171 | 
172 | [[types.type-4-1]]
173 | name = "himm"
174 | top = 5
175 | bot = 3
176 | 
177 | [[types.type-4-1]]
178 | name = "himm"
179 | top = 8
180 | bot = 6
181 | 
182 | [[types.type-4-1]]
183 | name = "c_rs2_Register_float"
184 | top = 4
185 | bot = 0
186 | 
187 | [[types.type-4-1]]
188 | name = "none"
189 | top = 1
190 | bot = 0
191 | 
192 | [format-1-0]
193 | type = "type-1-0"
194 | 
195 | [format-2-1]
196 | type = "type-2-1"
197 | 
198 | [format-3-0]
199 | type = "type-3-0"
200 | 
201 | [format-4-1]
202 | type = "type-4-1"
203 | 
204 | [mappings]
205 | names = ["Register_int", "Register_int_c", "Register_float", "Register_float_c"]
206 | number = 32
207 | Register_int = [
208 |     "zero",
209 |     "ra",
210 |     "sp",
211 |     "gp",
212 |     "tp",
213 |     "t0",
214 |     "t1",
215 |     "t2",
216 |     "s0",
217 |     "s1",
218 |     "a0",
219 |     "a1",
220 |     "a2",
221 |     "a3",
222 |     "a4",
223 |     "a5",
224 |     "a6",
225 |     "a7",
226 |     "s2",
227 |     "s3",
228 |     "s4",
229 |     "s5",
230 |     "s6",
231 |     "s7",
232 |     "s8",
233 |     "s9",
234 |     "s10",
235 |     "s11",
236 |     "t3",
237 |     "t4",
238 |     "t5",
239 |     "t6",
240 | ]
241 | Register_int_c = ["s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5"]
242 | Register_float = [
243 |     "ft0",
244 |     "ft1",
245 |     "ft2",
246 |     "ft3",
247 |     "ft4",
248 |     "ft5",
249 |     "ft6",
250 |     "ft7",
251 |     "fs0",
252 |     "fs1",
253 |     "fa0",
254 |     "fa1",
255 |     "fa2",
256 |     "fa3",
257 |     "fa4",
258 |     "fa5",
259 |     "fa6",
260 |     "fa7",
261 |     "fs2",
262 |     "fs3",
263 |     "fs4",
264 |     "fs5",
265 |     "fs6",
266 |     "fs7",
267 |     "fs8",
268 |     "fs9",
269 |     "fs10",
270 |     "fs11",
271 |     "ft8",
272 |     "ft9",
273 |     "ft10",
274 |     "ft11",
275 | ]
276 | Register_float_c = ["fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5"]
277 | 
278 | [format-1-0.repr]
279 | default = "$name$ %rd_p_Register_float_c%, %himm%(%rs1_p_Register_int_c%)"
280 | 
281 | [format-2-1.repr]
282 | default = "$name$ %rd_Register_float%, %himm%(sp)"
283 | 
284 | [format-3-0.repr]
285 | default = "$name$ %rs2_p_Register_float_c%, %himm%(%rs1_p_Register_int_c%)"
286 | 
287 | [format-4-1.repr]
288 | default = "$name$ %c_rs2_Register_float%, %himm%(sp)"
289 | 
290 | [format-1-0.instructions."c.fld"]
291 | mask = 0xe003
292 | match = 0x2000
293 | unsigned = true
294 | 
295 | [format-2-1.instructions."c.fldsp"]
296 | mask = 0xe003
297 | match = 0x2002
298 | unsigned = true
299 | 
300 | [format-3-0.instructions."c.fsd"]
301 | mask = 0xe003
302 | match = 0xa000
303 | unsigned = true
304 | 
305 | [format-4-1.instructions."c.fsdsp"]
306 | mask = 0xe003
307 | match = 0xa002
308 | unsigned = true
309 | 


--------------------------------------------------------------------------------
/toml/RV64_Zcd.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZcd" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 16
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-1", "format-3-0", "format-4-1"]
  6 | parts = [
  7 |     [
  8 |         "rd_p_Register_int_c",
  9 |         3,
 10 |         "Register_int_c",
 11 |     ],
 12 |     [
 13 |         "rd_p_Register_float_c",
 14 |         3,
 15 |         "Register_float_c",
 16 |     ],
 17 |     [
 18 |         "rs1_p_Register_int_c",
 19 |         3,
 20 |         "Register_int_c",
 21 |     ],
 22 |     [
 23 |         "rs1_p_Register_float_c",
 24 |         3,
 25 |         "Register_float_c",
 26 |     ],
 27 |     [
 28 |         "rd_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rd_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "rs2_p_Register_int_c",
 39 |         3,
 40 |         "Register_int_c",
 41 |     ],
 42 |     [
 43 |         "rs2_p_Register_float_c",
 44 |         3,
 45 |         "Register_float_c",
 46 |     ],
 47 |     [
 48 |         "c_rs2_Register_int",
 49 |         5,
 50 |         "Register_int",
 51 |     ],
 52 |     [
 53 |         "c_rs2_Register_float",
 54 |         5,
 55 |         "Register_float",
 56 |     ],
 57 |     [
 58 |         "none",
 59 |         32,
 60 |         "u32",
 61 |     ],
 62 |     [
 63 |         "imm",
 64 |         32,
 65 |         "VInt",
 66 |     ],
 67 |     [
 68 |         "himm",
 69 |         32,
 70 |         "VInt",
 71 |         "hex",
 72 |     ],
 73 | ]
 74 | 
 75 | [types]
 76 | names = ["type-1-0", "type-2-1", "type-3-0", "type-4-1"]
 77 | [[types.type-1-0]]
 78 | name = "none"
 79 | top = 15
 80 | bot = 13
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "himm"
 84 | top = 5
 85 | bot = 3
 86 | 
 87 | [[types.type-1-0]]
 88 | name = "rs1_p_Register_int_c"
 89 | top = 2
 90 | bot = 0
 91 | 
 92 | [[types.type-1-0]]
 93 | name = "himm"
 94 | top = 7
 95 | bot = 6
 96 | 
 97 | [[types.type-1-0]]
 98 | name = "rd_p_Register_float_c"
 99 | top = 2
100 | bot = 0
101 | 
102 | [[types.type-1-0]]
103 | name = "none"
104 | top = 1
105 | bot = 0
106 | 
107 | [[types.type-2-1]]
108 | name = "none"
109 | top = 15
110 | bot = 13
111 | 
112 | [[types.type-2-1]]
113 | name = "himm"
114 | top = 5
115 | bot = 5
116 | 
117 | [[types.type-2-1]]
118 | name = "rd_Register_float"
119 | top = 4
120 | bot = 0
121 | 
122 | [[types.type-2-1]]
123 | name = "himm"
124 | top = 4
125 | bot = 3
126 | 
127 | [[types.type-2-1]]
128 | name = "himm"
129 | top = 8
130 | bot = 6
131 | 
132 | [[types.type-2-1]]
133 | name = "none"
134 | top = 1
135 | bot = 0
136 | 
137 | [[types.type-3-0]]
138 | name = "none"
139 | top = 15
140 | bot = 13
141 | 
142 | [[types.type-3-0]]
143 | name = "himm"
144 | top = 5
145 | bot = 3
146 | 
147 | [[types.type-3-0]]
148 | name = "rs1_p_Register_int_c"
149 | top = 2
150 | bot = 0
151 | 
152 | [[types.type-3-0]]
153 | name = "himm"
154 | top = 7
155 | bot = 6
156 | 
157 | [[types.type-3-0]]
158 | name = "rs2_p_Register_float_c"
159 | top = 2
160 | bot = 0
161 | 
162 | [[types.type-3-0]]
163 | name = "none"
164 | top = 1
165 | bot = 0
166 | 
167 | [[types.type-4-1]]
168 | name = "none"
169 | top = 15
170 | bot = 13
171 | 
172 | [[types.type-4-1]]
173 | name = "himm"
174 | top = 5
175 | bot = 3
176 | 
177 | [[types.type-4-1]]
178 | name = "himm"
179 | top = 8
180 | bot = 6
181 | 
182 | [[types.type-4-1]]
183 | name = "c_rs2_Register_float"
184 | top = 4
185 | bot = 0
186 | 
187 | [[types.type-4-1]]
188 | name = "none"
189 | top = 1
190 | bot = 0
191 | 
192 | [format-1-0]
193 | type = "type-1-0"
194 | 
195 | [format-2-1]
196 | type = "type-2-1"
197 | 
198 | [format-3-0]
199 | type = "type-3-0"
200 | 
201 | [format-4-1]
202 | type = "type-4-1"
203 | 
204 | [mappings]
205 | names = ["Register_int", "Register_int_c", "Register_float", "Register_float_c"]
206 | number = 32
207 | Register_int = [
208 |     "zero",
209 |     "ra",
210 |     "sp",
211 |     "gp",
212 |     "tp",
213 |     "t0",
214 |     "t1",
215 |     "t2",
216 |     "s0",
217 |     "s1",
218 |     "a0",
219 |     "a1",
220 |     "a2",
221 |     "a3",
222 |     "a4",
223 |     "a5",
224 |     "a6",
225 |     "a7",
226 |     "s2",
227 |     "s3",
228 |     "s4",
229 |     "s5",
230 |     "s6",
231 |     "s7",
232 |     "s8",
233 |     "s9",
234 |     "s10",
235 |     "s11",
236 |     "t3",
237 |     "t4",
238 |     "t5",
239 |     "t6",
240 | ]
241 | Register_int_c = ["s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5"]
242 | Register_float = [
243 |     "ft0",
244 |     "ft1",
245 |     "ft2",
246 |     "ft3",
247 |     "ft4",
248 |     "ft5",
249 |     "ft6",
250 |     "ft7",
251 |     "fs0",
252 |     "fs1",
253 |     "fa0",
254 |     "fa1",
255 |     "fa2",
256 |     "fa3",
257 |     "fa4",
258 |     "fa5",
259 |     "fa6",
260 |     "fa7",
261 |     "fs2",
262 |     "fs3",
263 |     "fs4",
264 |     "fs5",
265 |     "fs6",
266 |     "fs7",
267 |     "fs8",
268 |     "fs9",
269 |     "fs10",
270 |     "fs11",
271 |     "ft8",
272 |     "ft9",
273 |     "ft10",
274 |     "ft11",
275 | ]
276 | Register_float_c = ["fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5"]
277 | 
278 | [format-1-0.repr]
279 | default = "$name$ %rd_p_Register_float_c%, %himm%(%rs1_p_Register_int_c%)"
280 | 
281 | [format-2-1.repr]
282 | default = "$name$ %rd_Register_float%, %himm%(sp)"
283 | 
284 | [format-3-0.repr]
285 | default = "$name$ %rs2_p_Register_float_c%, %himm%(%rs1_p_Register_int_c%)"
286 | 
287 | [format-4-1.repr]
288 | default = "$name$ %c_rs2_Register_float%, %himm%(sp)"
289 | 
290 | [format-1-0.instructions."c.fld"]
291 | mask = 0xe003
292 | match = 0x2000
293 | unsigned = true
294 | 
295 | [format-2-1.instructions."c.fldsp"]
296 | mask = 0xe003
297 | match = 0x2002
298 | unsigned = true
299 | 
300 | [format-3-0.instructions."c.fsd"]
301 | mask = 0xe003
302 | match = 0xa000
303 | unsigned = true
304 | 
305 | [format-4-1.instructions."c.fsdsp"]
306 | mask = 0xe003
307 | match = 0xa002
308 | unsigned = true
309 | 


--------------------------------------------------------------------------------
/toml/RV64_Zknd.toml:
--------------------------------------------------------------------------------
  1 | set = "RV64Zknd" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0", "format-3-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "rnum",
 39 |         4,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type-1-0", "type-2-0", "type-3-0"]
 63 | [[types.type-1-0]]
 64 | name = "none"
 65 | top = 31
 66 | bot = 25
 67 | 
 68 | [[types.type-1-0]]
 69 | name = "rs2_Register_int"
 70 | top = 4
 71 | bot = 0
 72 | 
 73 | [[types.type-1-0]]
 74 | name = "rs1_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type-1-0]]
 79 | name = "none"
 80 | top = 14
 81 | bot = 12
 82 | 
 83 | [[types.type-1-0]]
 84 | name = "rd_Register_int"
 85 | top = 4
 86 | bot = 0
 87 | 
 88 | [[types.type-1-0]]
 89 | name = "none"
 90 | top = 6
 91 | bot = 0
 92 | 
 93 | [[types.type-2-0]]
 94 | name = "none"
 95 | top = 31
 96 | bot = 20
 97 | 
 98 | [[types.type-2-0]]
 99 | name = "rs1_Register_int"
100 | top = 4
101 | bot = 0
102 | 
103 | [[types.type-2-0]]
104 | name = "none"
105 | top = 14
106 | bot = 12
107 | 
108 | [[types.type-2-0]]
109 | name = "rd_Register_int"
110 | top = 4
111 | bot = 0
112 | 
113 | [[types.type-2-0]]
114 | name = "none"
115 | top = 6
116 | bot = 0
117 | 
118 | [[types.type-3-0]]
119 | name = "none"
120 | top = 31
121 | bot = 24
122 | 
123 | [[types.type-3-0]]
124 | name = "rnum"
125 | top = 3
126 | bot = 0
127 | 
128 | [[types.type-3-0]]
129 | name = "rs1_Register_int"
130 | top = 4
131 | bot = 0
132 | 
133 | [[types.type-3-0]]
134 | name = "none"
135 | top = 14
136 | bot = 12
137 | 
138 | [[types.type-3-0]]
139 | name = "rd_Register_int"
140 | top = 4
141 | bot = 0
142 | 
143 | [[types.type-3-0]]
144 | name = "none"
145 | top = 6
146 | bot = 0
147 | 
148 | [format-1-0]
149 | type = "type-1-0"
150 | 
151 | [format-2-0]
152 | type = "type-2-0"
153 | 
154 | [format-3-0]
155 | type = "type-3-0"
156 | 
157 | [mappings]
158 | names = ["Register_int", "Register_float"]
159 | number = 32
160 | Register_int = [
161 |     "zero",
162 |     "ra",
163 |     "sp",
164 |     "gp",
165 |     "tp",
166 |     "t0",
167 |     "t1",
168 |     "t2",
169 |     "s0",
170 |     "s1",
171 |     "a0",
172 |     "a1",
173 |     "a2",
174 |     "a3",
175 |     "a4",
176 |     "a5",
177 |     "a6",
178 |     "a7",
179 |     "s2",
180 |     "s3",
181 |     "s4",
182 |     "s5",
183 |     "s6",
184 |     "s7",
185 |     "s8",
186 |     "s9",
187 |     "s10",
188 |     "s11",
189 |     "t3",
190 |     "t4",
191 |     "t5",
192 |     "t6",
193 | ]
194 | Register_float = [
195 |     "ft0",
196 |     "ft1",
197 |     "ft2",
198 |     "ft3",
199 |     "ft4",
200 |     "ft5",
201 |     "ft6",
202 |     "ft7",
203 |     "fs0",
204 |     "fs1",
205 |     "fa0",
206 |     "fa1",
207 |     "fa2",
208 |     "fa3",
209 |     "fa4",
210 |     "fa5",
211 |     "fa6",
212 |     "fa7",
213 |     "fs2",
214 |     "fs3",
215 |     "fs4",
216 |     "fs5",
217 |     "fs6",
218 |     "fs7",
219 |     "fs8",
220 |     "fs9",
221 |     "fs10",
222 |     "fs11",
223 |     "ft8",
224 |     "ft9",
225 |     "ft10",
226 |     "ft11",
227 | ]
228 | 
229 | [format-1-0.repr]
230 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
231 | 
232 | [format-2-0.repr]
233 | default = "$name$ %rd_Register_int%, %rs1_Register_int%"
234 | 
235 | [format-3-0.repr]
236 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rnum%"
237 | 
238 | [format-1-0.instructions.aes64ds]
239 | mask = 0xfe00707f
240 | match = 0x3a000033
241 | 
242 | [format-1-0.instructions.aes64dsm]
243 | mask = 0xfe00707f
244 | match = 0x3e000033
245 | 
246 | [format-1-0.instructions.aes64ks2]
247 | mask = 0xfe00707f
248 | match = 0x7e000033
249 | 
250 | [format-2-0.instructions.aes64im]
251 | mask = 0xfff0707f
252 | match = 0x30001013
253 | 
254 | [format-3-0.instructions.aes64ks1i]
255 | mask = 0xff00707f
256 | match = 0x31001013
257 | 


--------------------------------------------------------------------------------
/toml/RV64_Zkne.toml:
--------------------------------------------------------------------------------
  1 | set = "RV64Zkne" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "rnum",
 39 |         4,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type-1-0", "type-2-0"]
 63 | [[types.type-1-0]]
 64 | name = "none"
 65 | top = 31
 66 | bot = 25
 67 | 
 68 | [[types.type-1-0]]
 69 | name = "rs2_Register_int"
 70 | top = 4
 71 | bot = 0
 72 | 
 73 | [[types.type-1-0]]
 74 | name = "rs1_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type-1-0]]
 79 | name = "none"
 80 | top = 14
 81 | bot = 12
 82 | 
 83 | [[types.type-1-0]]
 84 | name = "rd_Register_int"
 85 | top = 4
 86 | bot = 0
 87 | 
 88 | [[types.type-1-0]]
 89 | name = "none"
 90 | top = 6
 91 | bot = 0
 92 | 
 93 | [[types.type-2-0]]
 94 | name = "none"
 95 | top = 31
 96 | bot = 24
 97 | 
 98 | [[types.type-2-0]]
 99 | name = "rnum"
100 | top = 3
101 | bot = 0
102 | 
103 | [[types.type-2-0]]
104 | name = "rs1_Register_int"
105 | top = 4
106 | bot = 0
107 | 
108 | [[types.type-2-0]]
109 | name = "none"
110 | top = 14
111 | bot = 12
112 | 
113 | [[types.type-2-0]]
114 | name = "rd_Register_int"
115 | top = 4
116 | bot = 0
117 | 
118 | [[types.type-2-0]]
119 | name = "none"
120 | top = 6
121 | bot = 0
122 | 
123 | [format-1-0]
124 | type = "type-1-0"
125 | 
126 | [format-2-0]
127 | type = "type-2-0"
128 | 
129 | [mappings]
130 | names = ["Register_int", "Register_float"]
131 | number = 32
132 | Register_int = [
133 |     "zero",
134 |     "ra",
135 |     "sp",
136 |     "gp",
137 |     "tp",
138 |     "t0",
139 |     "t1",
140 |     "t2",
141 |     "s0",
142 |     "s1",
143 |     "a0",
144 |     "a1",
145 |     "a2",
146 |     "a3",
147 |     "a4",
148 |     "a5",
149 |     "a6",
150 |     "a7",
151 |     "s2",
152 |     "s3",
153 |     "s4",
154 |     "s5",
155 |     "s6",
156 |     "s7",
157 |     "s8",
158 |     "s9",
159 |     "s10",
160 |     "s11",
161 |     "t3",
162 |     "t4",
163 |     "t5",
164 |     "t6",
165 | ]
166 | Register_float = [
167 |     "ft0",
168 |     "ft1",
169 |     "ft2",
170 |     "ft3",
171 |     "ft4",
172 |     "ft5",
173 |     "ft6",
174 |     "ft7",
175 |     "fs0",
176 |     "fs1",
177 |     "fa0",
178 |     "fa1",
179 |     "fa2",
180 |     "fa3",
181 |     "fa4",
182 |     "fa5",
183 |     "fa6",
184 |     "fa7",
185 |     "fs2",
186 |     "fs3",
187 |     "fs4",
188 |     "fs5",
189 |     "fs6",
190 |     "fs7",
191 |     "fs8",
192 |     "fs9",
193 |     "fs10",
194 |     "fs11",
195 |     "ft8",
196 |     "ft9",
197 |     "ft10",
198 |     "ft11",
199 | ]
200 | 
201 | [format-1-0.repr]
202 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
203 | 
204 | [format-2-0.repr]
205 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rnum%"
206 | 
207 | [format-1-0.instructions.aes64es]
208 | mask = 0xfe00707f
209 | match = 0x32000033
210 | 
211 | [format-1-0.instructions.aes64esm]
212 | mask = 0xfe00707f
213 | match = 0x36000033
214 | 
215 | [format-1-0.instructions.aes64ks2]
216 | mask = 0xfe00707f
217 | match = 0x7e000033
218 | 
219 | [format-2-0.instructions.aes64ks1i]
220 | mask = 0xff00707f
221 | match = 0x31001013
222 | 


--------------------------------------------------------------------------------
/toml/RV_Zawrs.toml:
--------------------------------------------------------------------------------
 1 | set = "RVZawrs" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
 2 | width = 32
 3 | 
 4 | [formats]
 5 | names = ["format-1-0"]
 6 | parts = [["none", 32, "u32"], ["imm", 32, "VInt"], ["himm", 32, "VInt", "hex"]]
 7 | 
 8 | [types]
 9 | names = ["type-1-0"]
10 | [[types.type-1-0]]
11 | name = "none"
12 | top = 31
13 | bot = 0
14 | 
15 | [format-1-0]
16 | type = "type-1-0"
17 | 
18 | [mappings]
19 | names = []
20 | number = 32
21 | 
22 | [format-1-0.repr]
23 | default = "$name$"
24 | 
25 | [format-1-0.instructions."wrs.nto"]
26 | mask = 0xffffffff
27 | match = 0xd00073
28 | 
29 | [format-1-0.instructions."wrs.sto"]
30 | mask = 0xffffffff
31 | match = 0x1d00073
32 | 


--------------------------------------------------------------------------------
/toml/RV_Zba.toml:
--------------------------------------------------------------------------------
  1 | set = "RV64Zba" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format_1-0", "format_2-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "shamtd",
 39 |         6,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type_1-0", "type_2-0"]
 63 | [[types.type_1-0]]
 64 | name = "none"
 65 | top = 31
 66 | bot = 25
 67 | 
 68 | [[types.type_1-0]]
 69 | name = "rs2_Register_int"
 70 | top = 4
 71 | bot = 0
 72 | 
 73 | [[types.type_1-0]]
 74 | name = "rs1_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type_1-0]]
 79 | name = "none"
 80 | top = 14
 81 | bot = 12
 82 | 
 83 | [[types.type_1-0]]
 84 | name = "rd_Register_int"
 85 | top = 4
 86 | bot = 0
 87 | 
 88 | [[types.type_1-0]]
 89 | name = "none"
 90 | top = 6
 91 | bot = 0
 92 | 
 93 | [[types.type_2-0]]
 94 | name = "none"
 95 | top = 31
 96 | bot = 26
 97 | 
 98 | [[types.type_2-0]]
 99 | name = "shamtd"
100 | top = 5
101 | bot = 0
102 | 
103 | [[types.type_2-0]]
104 | name = "rs1_Register_int"
105 | top = 4
106 | bot = 0
107 | 
108 | [[types.type_2-0]]
109 | name = "none"
110 | top = 14
111 | bot = 12
112 | 
113 | [[types.type_2-0]]
114 | name = "rd_Register_int"
115 | top = 4
116 | bot = 0
117 | 
118 | [[types.type_2-0]]
119 | name = "none"
120 | top = 6
121 | bot = 0
122 | 
123 | [format_1-0]
124 | type = "type_1-0"
125 | 
126 | [format_2-0]
127 | type = "type_2-0"
128 | 
129 | [mappings]
130 | names = ["Register_int", "Register_float"]
131 | number = 32
132 | Register_int = [
133 |     "zero",
134 |     "ra",
135 |     "sp",
136 |     "gp",
137 |     "tp",
138 |     "t0",
139 |     "t1",
140 |     "t2",
141 |     "s0",
142 |     "s1",
143 |     "a0",
144 |     "a1",
145 |     "a2",
146 |     "a3",
147 |     "a4",
148 |     "a5",
149 |     "a6",
150 |     "a7",
151 |     "s2",
152 |     "s3",
153 |     "s4",
154 |     "s5",
155 |     "s6",
156 |     "s7",
157 |     "s8",
158 |     "s9",
159 |     "s10",
160 |     "s11",
161 |     "t3",
162 |     "t4",
163 |     "t5",
164 |     "t6",
165 | ]
166 | Register_float = [
167 |     "ft0",
168 |     "ft1",
169 |     "ft2",
170 |     "ft3",
171 |     "ft4",
172 |     "ft5",
173 |     "ft6",
174 |     "ft7",
175 |     "fs0",
176 |     "fs1",
177 |     "fa0",
178 |     "fa1",
179 |     "fa2",
180 |     "fa3",
181 |     "fa4",
182 |     "fa5",
183 |     "fa6",
184 |     "fa7",
185 |     "fs2",
186 |     "fs3",
187 |     "fs4",
188 |     "fs5",
189 |     "fs6",
190 |     "fs7",
191 |     "fs8",
192 |     "fs9",
193 |     "fs10",
194 |     "fs11",
195 |     "ft8",
196 |     "ft9",
197 |     "ft10",
198 |     "ft11",
199 | ]
200 | 
201 | [format_1-0.repr]
202 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
203 | 
204 | [format_2-0.repr]
205 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %shamtd%"
206 | 
207 | [format_1-0.instructions."add.uw"]
208 | mask = 0xfe00707f
209 | match = 0x800003b
210 | 
211 | [format_1-0.instructions.sh1add]
212 | mask = 0xfe00707f
213 | match = 0x20002033
214 | 
215 | [format_1-0.instructions."sh1add.uw"]
216 | mask = 0xfe00707f
217 | match = 0x2000203b
218 | 
219 | [format_1-0.instructions.sh2add]
220 | mask = 0xfe00707f
221 | match = 0x20004033
222 | 
223 | [format_1-0.instructions."sh2add.uw"]
224 | mask = 0xfe00707f
225 | match = 0x2000403b
226 | 
227 | [format_1-0.instructions.sh3add]
228 | mask = 0xfe00707f
229 | match = 0x20006033
230 | 
231 | [format_1-0.instructions."sh3add.uw"]
232 | mask = 0xfe00707f
233 | match = 0x2000603b
234 | 
235 | [format_2-0.instructions."slli.uw"]
236 | mask = 0xfc00707f
237 | match = 0x800101b
238 | 


--------------------------------------------------------------------------------
/toml/RV_Zbc.toml:
--------------------------------------------------------------------------------
  1 | set = "RV64Zbc" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format_1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "none",
 39 |         32,
 40 |         "u32",
 41 |     ],
 42 |     [
 43 |         "imm",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 |     [
 48 |         "himm",
 49 |         32,
 50 |         "VInt",
 51 |         "hex",
 52 |     ],
 53 | ]
 54 | 
 55 | [types]
 56 | names = ["type_1-0"]
 57 | [[types.type_1-0]]
 58 | name = "none"
 59 | top = 31
 60 | bot = 25
 61 | 
 62 | [[types.type_1-0]]
 63 | name = "rs2_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type_1-0]]
 68 | name = "rs1_Register_int"
 69 | top = 4
 70 | bot = 0
 71 | 
 72 | [[types.type_1-0]]
 73 | name = "none"
 74 | top = 14
 75 | bot = 12
 76 | 
 77 | [[types.type_1-0]]
 78 | name = "rd_Register_int"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type_1-0]]
 83 | name = "none"
 84 | top = 6
 85 | bot = 0
 86 | 
 87 | [format_1-0]
 88 | type = "type_1-0"
 89 | 
 90 | [mappings]
 91 | names = ["Register_int", "Register_float"]
 92 | number = 32
 93 | Register_int = [
 94 |     "zero",
 95 |     "ra",
 96 |     "sp",
 97 |     "gp",
 98 |     "tp",
 99 |     "t0",
100 |     "t1",
101 |     "t2",
102 |     "s0",
103 |     "s1",
104 |     "a0",
105 |     "a1",
106 |     "a2",
107 |     "a3",
108 |     "a4",
109 |     "a5",
110 |     "a6",
111 |     "a7",
112 |     "s2",
113 |     "s3",
114 |     "s4",
115 |     "s5",
116 |     "s6",
117 |     "s7",
118 |     "s8",
119 |     "s9",
120 |     "s10",
121 |     "s11",
122 |     "t3",
123 |     "t4",
124 |     "t5",
125 |     "t6",
126 | ]
127 | Register_float = [
128 |     "ft0",
129 |     "ft1",
130 |     "ft2",
131 |     "ft3",
132 |     "ft4",
133 |     "ft5",
134 |     "ft6",
135 |     "ft7",
136 |     "fs0",
137 |     "fs1",
138 |     "fa0",
139 |     "fa1",
140 |     "fa2",
141 |     "fa3",
142 |     "fa4",
143 |     "fa5",
144 |     "fa6",
145 |     "fa7",
146 |     "fs2",
147 |     "fs3",
148 |     "fs4",
149 |     "fs5",
150 |     "fs6",
151 |     "fs7",
152 |     "fs8",
153 |     "fs9",
154 |     "fs10",
155 |     "fs11",
156 |     "ft8",
157 |     "ft9",
158 |     "ft10",
159 |     "ft11",
160 | ]
161 | 
162 | [format_1-0.repr]
163 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
164 | 
165 | [format_1-0.instructions.clmul]
166 | mask = 0xfe00707f
167 | match = 0xa001033
168 | 
169 | [format_1-0.instructions.clmulh]
170 | mask = 0xfe00707f
171 | match = 0xa003033
172 | 
173 | [format_1-0.instructions.clmulr]
174 | mask = 0xfe00707f
175 | match = 0xa002033
176 | 


--------------------------------------------------------------------------------
/toml/RV_Zbkc.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZbkc" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "none",
 39 |         32,
 40 |         "u32",
 41 |     ],
 42 |     [
 43 |         "imm",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 |     [
 48 |         "himm",
 49 |         32,
 50 |         "VInt",
 51 |         "hex",
 52 |     ],
 53 | ]
 54 | 
 55 | [types]
 56 | names = ["type-1-0"]
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 31
 60 | bot = 25
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "rs2_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "rs1_Register_int"
 69 | top = 4
 70 | bot = 0
 71 | 
 72 | [[types.type-1-0]]
 73 | name = "none"
 74 | top = 14
 75 | bot = 12
 76 | 
 77 | [[types.type-1-0]]
 78 | name = "rd_Register_int"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "none"
 84 | top = 6
 85 | bot = 0
 86 | 
 87 | [format-1-0]
 88 | type = "type-1-0"
 89 | 
 90 | [mappings]
 91 | names = ["Register_int", "Register_float"]
 92 | number = 32
 93 | Register_int = [
 94 |     "zero",
 95 |     "ra",
 96 |     "sp",
 97 |     "gp",
 98 |     "tp",
 99 |     "t0",
100 |     "t1",
101 |     "t2",
102 |     "s0",
103 |     "s1",
104 |     "a0",
105 |     "a1",
106 |     "a2",
107 |     "a3",
108 |     "a4",
109 |     "a5",
110 |     "a6",
111 |     "a7",
112 |     "s2",
113 |     "s3",
114 |     "s4",
115 |     "s5",
116 |     "s6",
117 |     "s7",
118 |     "s8",
119 |     "s9",
120 |     "s10",
121 |     "s11",
122 |     "t3",
123 |     "t4",
124 |     "t5",
125 |     "t6",
126 | ]
127 | Register_float = [
128 |     "ft0",
129 |     "ft1",
130 |     "ft2",
131 |     "ft3",
132 |     "ft4",
133 |     "ft5",
134 |     "ft6",
135 |     "ft7",
136 |     "fs0",
137 |     "fs1",
138 |     "fa0",
139 |     "fa1",
140 |     "fa2",
141 |     "fa3",
142 |     "fa4",
143 |     "fa5",
144 |     "fa6",
145 |     "fa7",
146 |     "fs2",
147 |     "fs3",
148 |     "fs4",
149 |     "fs5",
150 |     "fs6",
151 |     "fs7",
152 |     "fs8",
153 |     "fs9",
154 |     "fs10",
155 |     "fs11",
156 |     "ft8",
157 |     "ft9",
158 |     "ft10",
159 |     "ft11",
160 | ]
161 | 
162 | [format-1-0.repr]
163 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
164 | 
165 | [format-1-0.instructions.clmul]
166 | mask = 0xfe00707f
167 | match = 0xa001033
168 | 
169 | [format-1-0.instructions.clmulh]
170 | mask = 0xfe00707f
171 | match = 0xa003033
172 | 


--------------------------------------------------------------------------------
/toml/RV_Zbkx.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZbkx" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "none",
 39 |         32,
 40 |         "u32",
 41 |     ],
 42 |     [
 43 |         "imm",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 |     [
 48 |         "himm",
 49 |         32,
 50 |         "VInt",
 51 |         "hex",
 52 |     ],
 53 | ]
 54 | 
 55 | [types]
 56 | names = ["type-1-0"]
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 31
 60 | bot = 25
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "rs2_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "rs1_Register_int"
 69 | top = 4
 70 | bot = 0
 71 | 
 72 | [[types.type-1-0]]
 73 | name = "none"
 74 | top = 14
 75 | bot = 12
 76 | 
 77 | [[types.type-1-0]]
 78 | name = "rd_Register_int"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "none"
 84 | top = 6
 85 | bot = 0
 86 | 
 87 | [format-1-0]
 88 | type = "type-1-0"
 89 | 
 90 | [mappings]
 91 | names = ["Register_int", "Register_float"]
 92 | number = 32
 93 | Register_int = [
 94 |     "zero",
 95 |     "ra",
 96 |     "sp",
 97 |     "gp",
 98 |     "tp",
 99 |     "t0",
100 |     "t1",
101 |     "t2",
102 |     "s0",
103 |     "s1",
104 |     "a0",
105 |     "a1",
106 |     "a2",
107 |     "a3",
108 |     "a4",
109 |     "a5",
110 |     "a6",
111 |     "a7",
112 |     "s2",
113 |     "s3",
114 |     "s4",
115 |     "s5",
116 |     "s6",
117 |     "s7",
118 |     "s8",
119 |     "s9",
120 |     "s10",
121 |     "s11",
122 |     "t3",
123 |     "t4",
124 |     "t5",
125 |     "t6",
126 | ]
127 | Register_float = [
128 |     "ft0",
129 |     "ft1",
130 |     "ft2",
131 |     "ft3",
132 |     "ft4",
133 |     "ft5",
134 |     "ft6",
135 |     "ft7",
136 |     "fs0",
137 |     "fs1",
138 |     "fa0",
139 |     "fa1",
140 |     "fa2",
141 |     "fa3",
142 |     "fa4",
143 |     "fa5",
144 |     "fa6",
145 |     "fa7",
146 |     "fs2",
147 |     "fs3",
148 |     "fs4",
149 |     "fs5",
150 |     "fs6",
151 |     "fs7",
152 |     "fs8",
153 |     "fs9",
154 |     "fs10",
155 |     "fs11",
156 |     "ft8",
157 |     "ft9",
158 |     "ft10",
159 |     "ft11",
160 | ]
161 | 
162 | [format-1-0.repr]
163 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
164 | 
165 | [format-1-0.instructions.xperm4]
166 | mask = 0xfe00707f
167 | match = 0x28002033
168 | 
169 | [format-1-0.instructions.xperm8]
170 | mask = 0xfe00707f
171 | match = 0x28004033
172 | 


--------------------------------------------------------------------------------
/toml/RV_Zcd-lower.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZcd" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b (manually added Register_int_c)
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0", "format-3-0", "format-4-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_p_Register_int_c",
  9 |         3,
 10 |         "Register_int_c",
 11 |     ],
 12 |     [
 13 |         "rd_p_Register_float_c",
 14 |         3,
 15 |         "Register_float_c",
 16 |     ],
 17 |     [
 18 |         "rs1_p_Register_int_c",
 19 |         3,
 20 |         "Register_int_c",
 21 |     ],
 22 |     [
 23 |         "rs1_p_Register_float_c",
 24 |         3,
 25 |         "Register_float_c",
 26 |     ],
 27 |     [
 28 |         "rd_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rd_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "rs2_p_Register_int_c",
 39 |         3,
 40 |         "Register_int_c",
 41 |     ],
 42 |     [
 43 |         "rs2_p_Register_float_c",
 44 |         3,
 45 |         "Register_float_c",
 46 |     ],
 47 |     [
 48 |         "c_rs2_Register_int",
 49 |         5,
 50 |         "Register_int",
 51 |     ],
 52 |     [
 53 |         "c_rs2_Register_float",
 54 |         5,
 55 |         "Register_float",
 56 |     ],
 57 |     [
 58 |         "none",
 59 |         32,
 60 |         "u32",
 61 |     ],
 62 |     [
 63 |         "imm",
 64 |         32,
 65 |         "VInt",
 66 |     ],
 67 |     [
 68 |         "himm",
 69 |         32,
 70 |         "VInt",
 71 |         "hex",
 72 |     ],
 73 | ]
 74 | 
 75 | [types]
 76 | names = ["type-1-0", "type-2-0", "type-3-0", "type-4-0"]
 77 | [[types.type-1-0]]
 78 | name = "none"
 79 | top = 31
 80 | bot = 13
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "himm"
 84 | top = 5
 85 | bot = 3
 86 | 
 87 | [[types.type-1-0]]
 88 | name = "rs1_p_Register_int_c"
 89 | top = 2
 90 | bot = 0
 91 | 
 92 | [[types.type-1-0]]
 93 | name = "himm"
 94 | top = 7
 95 | bot = 6
 96 | 
 97 | [[types.type-1-0]]
 98 | name = "rd_p_Register_float_c"
 99 | top = 2
100 | bot = 0
101 | 
102 | [[types.type-1-0]]
103 | name = "none"
104 | top = 1
105 | bot = 0
106 | 
107 | [[types.type-2-0]]
108 | name = "none"
109 | top = 31
110 | bot = 13
111 | 
112 | [[types.type-2-0]]
113 | name = "himm"
114 | top = 5
115 | bot = 5
116 | 
117 | [[types.type-2-0]]
118 | name = "rd_Register_float"
119 | top = 4
120 | bot = 0
121 | 
122 | [[types.type-2-0]]
123 | name = "himm"
124 | top = 4
125 | bot = 3
126 | 
127 | [[types.type-2-0]]
128 | name = "himm"
129 | top = 8
130 | bot = 6
131 | 
132 | [[types.type-2-0]]
133 | name = "none"
134 | top = 1
135 | bot = 0
136 | 
137 | [[types.type-3-0]]
138 | name = "none"
139 | top = 31
140 | bot = 13
141 | 
142 | [[types.type-3-0]]
143 | name = "himm"
144 | top = 5
145 | bot = 3
146 | 
147 | [[types.type-3-0]]
148 | name = "rs1_p_Register_int_c"
149 | top = 2
150 | bot = 0
151 | 
152 | [[types.type-3-0]]
153 | name = "himm"
154 | top = 7
155 | bot = 6
156 | 
157 | [[types.type-3-0]]
158 | name = "rs2_p_Register_float_c"
159 | top = 2
160 | bot = 0
161 | 
162 | [[types.type-3-0]]
163 | name = "none"
164 | top = 1
165 | bot = 0
166 | 
167 | [[types.type-4-0]]
168 | name = "none"
169 | top = 31
170 | bot = 13
171 | 
172 | [[types.type-4-0]]
173 | name = "himm"
174 | top = 5
175 | bot = 3
176 | 
177 | [[types.type-4-0]]
178 | name = "himm"
179 | top = 8
180 | bot = 6
181 | 
182 | [[types.type-4-0]]
183 | name = "c_rs2_Register_float"
184 | top = 4
185 | bot = 0
186 | 
187 | [[types.type-4-0]]
188 | name = "none"
189 | top = 1
190 | bot = 0
191 | 
192 | [format-1-0]
193 | type = "type-1-0"
194 | 
195 | [format-2-0]
196 | type = "type-2-0"
197 | 
198 | [format-3-0]
199 | type = "type-3-0"
200 | 
201 | [format-4-0]
202 | type = "type-4-0"
203 | 
204 | [mappings]
205 | names = ["Register_int", "Register_int_c", "Register_float", "Register_float_c"]
206 | number = 32
207 | Register_int = [
208 |     "zero",
209 |     "ra",
210 |     "sp",
211 |     "gp",
212 |     "tp",
213 |     "t0",
214 |     "t1",
215 |     "t2",
216 |     "s0",
217 |     "s1",
218 |     "a0",
219 |     "a1",
220 |     "a2",
221 |     "a3",
222 |     "a4",
223 |     "a5",
224 |     "a6",
225 |     "a7",
226 |     "s2",
227 |     "s3",
228 |     "s4",
229 |     "s5",
230 |     "s6",
231 |     "s7",
232 |     "s8",
233 |     "s9",
234 |     "s10",
235 |     "s11",
236 |     "t3",
237 |     "t4",
238 |     "t5",
239 |     "t6",
240 | ]
241 | Register_int_c = ["s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5"]
242 | Register_float = [
243 |     "ft0",
244 |     "ft1",
245 |     "ft2",
246 |     "ft3",
247 |     "ft4",
248 |     "ft5",
249 |     "ft6",
250 |     "ft7",
251 |     "fs0",
252 |     "fs1",
253 |     "fa0",
254 |     "fa1",
255 |     "fa2",
256 |     "fa3",
257 |     "fa4",
258 |     "fa5",
259 |     "fa6",
260 |     "fa7",
261 |     "fs2",
262 |     "fs3",
263 |     "fs4",
264 |     "fs5",
265 |     "fs6",
266 |     "fs7",
267 |     "fs8",
268 |     "fs9",
269 |     "fs10",
270 |     "fs11",
271 |     "ft8",
272 |     "ft9",
273 |     "ft10",
274 |     "ft11",
275 | ]
276 | Register_float_c = ["fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5"]
277 | 
278 | [format-1-0.repr]
279 | default = "$name$ %rd_p_Register_float_c%, %himm%(%rs1_p_Register_int_c%)"
280 | 
281 | [format-2-0.repr]
282 | default = "$name$ %rd_Register_float%, %himm%(sp)"
283 | 
284 | [format-3-0.repr]
285 | default = "$name$ %rs2_p_Register_float_c%, %himm%(%rs1_p_Register_int_c%)"
286 | 
287 | [format-4-0.repr]
288 | default = "$name$ %c_rs2_Register_float%, %himm%(sp)"
289 | 
290 | [format-1-0.instructions."c.fld"]
291 | mask = 0xe003
292 | match = 0x2000
293 | unsigned = true
294 | 
295 | [format-2-0.instructions."c.fldsp"]
296 | mask = 0xe003
297 | match = 0x2002
298 | unsigned = true
299 | 
300 | [format-3-0.instructions."c.fsd"]
301 | mask = 0xe003
302 | match = 0xa000
303 | unsigned = true
304 | 
305 | [format-4-0.instructions."c.fsdsp"]
306 | mask = 0xe003
307 | match = 0xa002
308 | unsigned = true
309 | 


--------------------------------------------------------------------------------
/toml/RV_Zcd.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZcd" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b (manually added Register_int_c)
  2 | width = 16
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0", "format-3-0", "format-4-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_p_Register_int_c",
  9 |         3,
 10 |         "Register_int_c",
 11 |     ],
 12 |     [
 13 |         "rd_p_Register_float_c",
 14 |         3,
 15 |         "Register_float_c",
 16 |     ],
 17 |     [
 18 |         "rs1_p_Register_int_c",
 19 |         3,
 20 |         "Register_int_c",
 21 |     ],
 22 |     [
 23 |         "rs1_p_Register_float_c",
 24 |         3,
 25 |         "Register_float_c",
 26 |     ],
 27 |     [
 28 |         "rd_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rd_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "rs2_p_Register_int_c",
 39 |         3,
 40 |         "Register_int_c",
 41 |     ],
 42 |     [
 43 |         "rs2_p_Register_float_c",
 44 |         3,
 45 |         "Register_float_c",
 46 |     ],
 47 |     [
 48 |         "c_rs2_Register_int",
 49 |         5,
 50 |         "Register_int",
 51 |     ],
 52 |     [
 53 |         "c_rs2_Register_float",
 54 |         5,
 55 |         "Register_float",
 56 |     ],
 57 |     [
 58 |         "none",
 59 |         32,
 60 |         "u32",
 61 |     ],
 62 |     [
 63 |         "imm",
 64 |         32,
 65 |         "VInt",
 66 |     ],
 67 |     [
 68 |         "himm",
 69 |         32,
 70 |         "VInt",
 71 |         "hex",
 72 |     ],
 73 | ]
 74 | 
 75 | [types]
 76 | names = ["type-1-0", "type-2-0", "type-3-0", "type-4-0"]
 77 | [[types.type-1-0]]
 78 | name = "none"
 79 | top = 15
 80 | bot = 13
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "himm"
 84 | top = 5
 85 | bot = 3
 86 | 
 87 | [[types.type-1-0]]
 88 | name = "rs1_p_Register_int_c"
 89 | top = 2
 90 | bot = 0
 91 | 
 92 | [[types.type-1-0]]
 93 | name = "himm"
 94 | top = 7
 95 | bot = 6
 96 | 
 97 | [[types.type-1-0]]
 98 | name = "rd_p_Register_float_c"
 99 | top = 2
100 | bot = 0
101 | 
102 | [[types.type-1-0]]
103 | name = "none"
104 | top = 1
105 | bot = 0
106 | 
107 | [[types.type-2-0]]
108 | name = "none"
109 | top = 15
110 | bot = 13
111 | 
112 | [[types.type-2-0]]
113 | name = "himm"
114 | top = 5
115 | bot = 5
116 | 
117 | [[types.type-2-0]]
118 | name = "rd_Register_float"
119 | top = 4
120 | bot = 0
121 | 
122 | [[types.type-2-0]]
123 | name = "himm"
124 | top = 4
125 | bot = 3
126 | 
127 | [[types.type-2-0]]
128 | name = "himm"
129 | top = 8
130 | bot = 6
131 | 
132 | [[types.type-2-0]]
133 | name = "none"
134 | top = 1
135 | bot = 0
136 | 
137 | [[types.type-3-0]]
138 | name = "none"
139 | top = 15
140 | bot = 13
141 | 
142 | [[types.type-3-0]]
143 | name = "himm"
144 | top = 5
145 | bot = 3
146 | 
147 | [[types.type-3-0]]
148 | name = "rs1_p_Register_int_c"
149 | top = 2
150 | bot = 0
151 | 
152 | [[types.type-3-0]]
153 | name = "himm"
154 | top = 7
155 | bot = 6
156 | 
157 | [[types.type-3-0]]
158 | name = "rs2_p_Register_float_c"
159 | top = 2
160 | bot = 0
161 | 
162 | [[types.type-3-0]]
163 | name = "none"
164 | top = 1
165 | bot = 0
166 | 
167 | [[types.type-4-0]]
168 | name = "none"
169 | top = 15
170 | bot = 13
171 | 
172 | [[types.type-4-0]]
173 | name = "himm"
174 | top = 5
175 | bot = 3
176 | 
177 | [[types.type-4-0]]
178 | name = "himm"
179 | top = 8
180 | bot = 6
181 | 
182 | [[types.type-4-0]]
183 | name = "c_rs2_Register_float"
184 | top = 4
185 | bot = 0
186 | 
187 | [[types.type-4-0]]
188 | name = "none"
189 | top = 1
190 | bot = 0
191 | 
192 | [format-1-0]
193 | type = "type-1-0"
194 | 
195 | [format-2-0]
196 | type = "type-2-0"
197 | 
198 | [format-3-0]
199 | type = "type-3-0"
200 | 
201 | [format-4-0]
202 | type = "type-4-0"
203 | 
204 | [mappings]
205 | names = ["Register_int", "Register_int_c", "Register_float", "Register_float_c"]
206 | number = 32
207 | Register_int = [
208 |     "zero",
209 |     "ra",
210 |     "sp",
211 |     "gp",
212 |     "tp",
213 |     "t0",
214 |     "t1",
215 |     "t2",
216 |     "s0",
217 |     "s1",
218 |     "a0",
219 |     "a1",
220 |     "a2",
221 |     "a3",
222 |     "a4",
223 |     "a5",
224 |     "a6",
225 |     "a7",
226 |     "s2",
227 |     "s3",
228 |     "s4",
229 |     "s5",
230 |     "s6",
231 |     "s7",
232 |     "s8",
233 |     "s9",
234 |     "s10",
235 |     "s11",
236 |     "t3",
237 |     "t4",
238 |     "t5",
239 |     "t6",
240 | ]
241 | Register_int_c = ["s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5"]
242 | Register_float = [
243 |     "ft0",
244 |     "ft1",
245 |     "ft2",
246 |     "ft3",
247 |     "ft4",
248 |     "ft5",
249 |     "ft6",
250 |     "ft7",
251 |     "fs0",
252 |     "fs1",
253 |     "fa0",
254 |     "fa1",
255 |     "fa2",
256 |     "fa3",
257 |     "fa4",
258 |     "fa5",
259 |     "fa6",
260 |     "fa7",
261 |     "fs2",
262 |     "fs3",
263 |     "fs4",
264 |     "fs5",
265 |     "fs6",
266 |     "fs7",
267 |     "fs8",
268 |     "fs9",
269 |     "fs10",
270 |     "fs11",
271 |     "ft8",
272 |     "ft9",
273 |     "ft10",
274 |     "ft11",
275 | ]
276 | Register_float_c = ["fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5"]
277 | 
278 | [format-1-0.repr]
279 | default = "$name$ %rd_p_Register_float_c%, %himm%(%rs1_p_Register_int_c%)"
280 | 
281 | [format-2-0.repr]
282 | default = "$name$ %rd_Register_float%, %himm%(sp)"
283 | 
284 | [format-3-0.repr]
285 | default = "$name$ %rs2_p_Register_float_c%, %himm%(%rs1_p_Register_int_c%)"
286 | 
287 | [format-4-0.repr]
288 | default = "$name$ %c_rs2_Register_float%, %himm%(sp)"
289 | 
290 | [format-1-0.instructions."c.fld"]
291 | mask = 0xe003
292 | match = 0x2000
293 | unsigned = true
294 | 
295 | [format-2-0.instructions."c.fldsp"]
296 | mask = 0xe003
297 | match = 0x2002
298 | unsigned = true
299 | 
300 | [format-3-0.instructions."c.fsd"]
301 | mask = 0xe003
302 | match = 0xa000
303 | unsigned = true
304 | 
305 | [format-4-0.instructions."c.fsdsp"]
306 | mask = 0xe003
307 | match = 0xa002
308 | unsigned = true
309 | 


--------------------------------------------------------------------------------
/toml/RV_Zicbo.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZicbo" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0"]
  6 | parts = [
  7 |     [
  8 |         "rs1_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rs1_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "none",
 19 |         32,
 20 |         "u32",
 21 |     ],
 22 |     [
 23 |         "imm",
 24 |         32,
 25 |         "VInt",
 26 |     ],
 27 |     [
 28 |         "himm",
 29 |         32,
 30 |         "VInt",
 31 |         "hex",
 32 |     ],
 33 | ]
 34 | 
 35 | [types]
 36 | names = ["type-1-0", "type-2-0"]
 37 | [[types.type-1-0]]
 38 | name = "none"
 39 | top = 31
 40 | bot = 20
 41 | 
 42 | [[types.type-1-0]]
 43 | name = "rs1_Register_int"
 44 | top = 4
 45 | bot = 0
 46 | 
 47 | [[types.type-1-0]]
 48 | name = "none"
 49 | top = 14
 50 | bot = 0
 51 | 
 52 | [[types.type-2-0]]
 53 | name = "himm"
 54 | top = 11
 55 | bot = 5
 56 | 
 57 | [[types.type-2-0]]
 58 | name = "none"
 59 | top = 24
 60 | bot = 20
 61 | 
 62 | [[types.type-2-0]]
 63 | name = "rs1_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-2-0]]
 68 | name = "none"
 69 | top = 14
 70 | bot = 0
 71 | 
 72 | [format-1-0]
 73 | type = "type-1-0"
 74 | 
 75 | [format-2-0]
 76 | type = "type-2-0"
 77 | 
 78 | [mappings]
 79 | names = ["Register_int", "Register_float"]
 80 | number = 32
 81 | Register_int = [
 82 |     "zero",
 83 |     "ra",
 84 |     "sp",
 85 |     "gp",
 86 |     "tp",
 87 |     "t0",
 88 |     "t1",
 89 |     "t2",
 90 |     "s0",
 91 |     "s1",
 92 |     "a0",
 93 |     "a1",
 94 |     "a2",
 95 |     "a3",
 96 |     "a4",
 97 |     "a5",
 98 |     "a6",
 99 |     "a7",
100 |     "s2",
101 |     "s3",
102 |     "s4",
103 |     "s5",
104 |     "s6",
105 |     "s7",
106 |     "s8",
107 |     "s9",
108 |     "s10",
109 |     "s11",
110 |     "t3",
111 |     "t4",
112 |     "t5",
113 |     "t6",
114 | ]
115 | Register_float = [
116 |     "ft0",
117 |     "ft1",
118 |     "ft2",
119 |     "ft3",
120 |     "ft4",
121 |     "ft5",
122 |     "ft6",
123 |     "ft7",
124 |     "fs0",
125 |     "fs1",
126 |     "fa0",
127 |     "fa1",
128 |     "fa2",
129 |     "fa3",
130 |     "fa4",
131 |     "fa5",
132 |     "fa6",
133 |     "fa7",
134 |     "fs2",
135 |     "fs3",
136 |     "fs4",
137 |     "fs5",
138 |     "fs6",
139 |     "fs7",
140 |     "fs8",
141 |     "fs9",
142 |     "fs10",
143 |     "fs11",
144 |     "ft8",
145 |     "ft9",
146 |     "ft10",
147 |     "ft11",
148 | ]
149 | 
150 | [format-1-0.repr]
151 | default = "$name$ %rs1_Register_int%"
152 | 
153 | [format-2-0.repr]
154 | default = "$name$ %himm%(%rs1_Register_int%)"
155 | 
156 | [format-1-0.instructions."cbo.clean"]
157 | mask = 0xfff07fff
158 | match = 0x10200f
159 | 
160 | [format-1-0.instructions."cbo.flush"]
161 | mask = 0xfff07fff
162 | match = 0x20200f
163 | 
164 | [format-1-0.instructions."cbo.inval"]
165 | mask = 0xfff07fff
166 | match = 0x200f
167 | 
168 | [format-1-0.instructions."cbo.zero"]
169 | mask = 0xfff07fff
170 | match = 0x40200f
171 | 
172 | [format-2-0.instructions."prefetch.i"]
173 | mask = 0x1f07fff
174 | match = 0x6013
175 | 
176 | [format-2-0.instructions."prefetch.r"]
177 | mask = 0x1f07fff
178 | match = 0x106013
179 | 
180 | [format-2-0.instructions."prefetch.w"]
181 | mask = 0x1f07fff
182 | match = 0x306013
183 | 


--------------------------------------------------------------------------------
/toml/RV_Zicond.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZicond" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "none",
 39 |         32,
 40 |         "u32",
 41 |     ],
 42 |     [
 43 |         "imm",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 |     [
 48 |         "himm",
 49 |         32,
 50 |         "VInt",
 51 |         "hex",
 52 |     ],
 53 | ]
 54 | 
 55 | [types]
 56 | names = ["type-1-0"]
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 31
 60 | bot = 25
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "rs2_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "rs1_Register_int"
 69 | top = 4
 70 | bot = 0
 71 | 
 72 | [[types.type-1-0]]
 73 | name = "none"
 74 | top = 14
 75 | bot = 12
 76 | 
 77 | [[types.type-1-0]]
 78 | name = "rd_Register_int"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "none"
 84 | top = 6
 85 | bot = 0
 86 | 
 87 | [format-1-0]
 88 | type = "type-1-0"
 89 | 
 90 | [mappings]
 91 | names = ["Register_int", "Register_float"]
 92 | number = 32
 93 | Register_int = [
 94 |     "zero",
 95 |     "ra",
 96 |     "sp",
 97 |     "gp",
 98 |     "tp",
 99 |     "t0",
100 |     "t1",
101 |     "t2",
102 |     "s0",
103 |     "s1",
104 |     "a0",
105 |     "a1",
106 |     "a2",
107 |     "a3",
108 |     "a4",
109 |     "a5",
110 |     "a6",
111 |     "a7",
112 |     "s2",
113 |     "s3",
114 |     "s4",
115 |     "s5",
116 |     "s6",
117 |     "s7",
118 |     "s8",
119 |     "s9",
120 |     "s10",
121 |     "s11",
122 |     "t3",
123 |     "t4",
124 |     "t5",
125 |     "t6",
126 | ]
127 | Register_float = [
128 |     "ft0",
129 |     "ft1",
130 |     "ft2",
131 |     "ft3",
132 |     "ft4",
133 |     "ft5",
134 |     "ft6",
135 |     "ft7",
136 |     "fs0",
137 |     "fs1",
138 |     "fa0",
139 |     "fa1",
140 |     "fa2",
141 |     "fa3",
142 |     "fa4",
143 |     "fa5",
144 |     "fa6",
145 |     "fa7",
146 |     "fs2",
147 |     "fs3",
148 |     "fs4",
149 |     "fs5",
150 |     "fs6",
151 |     "fs7",
152 |     "fs8",
153 |     "fs9",
154 |     "fs10",
155 |     "fs11",
156 |     "ft8",
157 |     "ft9",
158 |     "ft10",
159 |     "ft11",
160 | ]
161 | 
162 | [format-1-0.repr]
163 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
164 | 
165 | [format-1-0.instructions."czero.eqz"]
166 | mask = 0xfe00707f
167 | match = 0xe005033
168 | 
169 | [format-1-0.instructions."czero.nez"]
170 | mask = 0xfe00707f
171 | match = 0xe007033
172 | 


--------------------------------------------------------------------------------
/toml/RV_Zifencei.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZifencei" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rs1_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rs1_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rd_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rd_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "none",
 29 |         32,
 30 |         "u32",
 31 |     ],
 32 |     [
 33 |         "imm",
 34 |         32,
 35 |         "VInt",
 36 |     ],
 37 |     [
 38 |         "himm",
 39 |         32,
 40 |         "VInt",
 41 |         "hex",
 42 |     ],
 43 | ]
 44 | 
 45 | [types]
 46 | names = ["type-1-0"]
 47 | [[types.type-1-0]]
 48 | name = "imm"
 49 | top = 11
 50 | bot = 0
 51 | 
 52 | [[types.type-1-0]]
 53 | name = "rs1_Register_int"
 54 | top = 4
 55 | bot = 0
 56 | 
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 14
 60 | bot = 12
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "rd_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "none"
 69 | top = 6
 70 | bot = 0
 71 | 
 72 | [format-1-0]
 73 | type = "type-1-0"
 74 | 
 75 | [mappings]
 76 | names = ["Register_int", "Register_float"]
 77 | number = 32
 78 | Register_int = [
 79 |     "zero",
 80 |     "ra",
 81 |     "sp",
 82 |     "gp",
 83 |     "tp",
 84 |     "t0",
 85 |     "t1",
 86 |     "t2",
 87 |     "s0",
 88 |     "s1",
 89 |     "a0",
 90 |     "a1",
 91 |     "a2",
 92 |     "a3",
 93 |     "a4",
 94 |     "a5",
 95 |     "a6",
 96 |     "a7",
 97 |     "s2",
 98 |     "s3",
 99 |     "s4",
100 |     "s5",
101 |     "s6",
102 |     "s7",
103 |     "s8",
104 |     "s9",
105 |     "s10",
106 |     "s11",
107 |     "t3",
108 |     "t4",
109 |     "t5",
110 |     "t6",
111 | ]
112 | Register_float = [
113 |     "ft0",
114 |     "ft1",
115 |     "ft2",
116 |     "ft3",
117 |     "ft4",
118 |     "ft5",
119 |     "ft6",
120 |     "ft7",
121 |     "fs0",
122 |     "fs1",
123 |     "fa0",
124 |     "fa1",
125 |     "fa2",
126 |     "fa3",
127 |     "fa4",
128 |     "fa5",
129 |     "fa6",
130 |     "fa7",
131 |     "fs2",
132 |     "fs3",
133 |     "fs4",
134 |     "fs5",
135 |     "fs6",
136 |     "fs7",
137 |     "fs8",
138 |     "fs9",
139 |     "fs10",
140 |     "fs11",
141 |     "ft8",
142 |     "ft9",
143 |     "ft10",
144 |     "ft11",
145 | ]
146 | 
147 | [format-1-0.repr]
148 | default = "$name$"
149 | 
150 | [format-1-0.instructions."fence.i"]
151 | mask = 0x707f
152 | match = 0x100f
153 | 


--------------------------------------------------------------------------------
/toml/RV_Zihintntl.toml:
--------------------------------------------------------------------------------
 1 | set = "RVZihintntl" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
 2 | width = 32
 3 | 
 4 | [formats]
 5 | names = ["format-1-0"]
 6 | parts = [["none", 32, "u32"], ["imm", 32, "VInt"], ["himm", 32, "VInt", "hex"]]
 7 | 
 8 | [types]
 9 | names = ["type-1-0"]
10 | [[types.type-1-0]]
11 | name = "none"
12 | top = 31
13 | bot = 0
14 | 
15 | [format-1-0]
16 | type = "type-1-0"
17 | 
18 | [mappings]
19 | names = []
20 | number = 32
21 | 
22 | [format-1-0.repr]
23 | default = "$name$"
24 | 
25 | [format-1-0.instructions."ntl.all"]
26 | mask = 0xffffffff
27 | match = 0x500033
28 | 
29 | [format-1-0.instructions."ntl.p1"]
30 | mask = 0xffffffff
31 | match = 0x200033
32 | 
33 | [format-1-0.instructions."ntl.pall"]
34 | mask = 0xffffffff
35 | match = 0x300033
36 | 
37 | [format-1-0.instructions."ntl.s1"]
38 | mask = 0xffffffff
39 | match = 0x400033
40 | 


--------------------------------------------------------------------------------
/toml/RV_Zimop.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZimop" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-2-0", "format-4-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "none",
 39 |         32,
 40 |         "u32",
 41 |     ],
 42 |     [
 43 |         "imm",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 |     [
 48 |         "himm",
 49 |         32,
 50 |         "VInt",
 51 |         "hex",
 52 |     ],
 53 | ]
 54 | 
 55 | [types]
 56 | names = ["type-2-0", "type-4-0"]
 57 | 
 58 | [[types.type-2-0]]
 59 | name = "none"
 60 | top = 31
 61 | bot = 31
 62 | 
 63 | [[types.type-2-0]]
 64 | name = "imm"
 65 | top = 4
 66 | bot = 4
 67 | 
 68 | [[types.type-2-0]]
 69 | name = "none"
 70 | top = 29
 71 | bot = 28
 72 | 
 73 | [[types.type-2-0]]
 74 | name = "imm"
 75 | top = 3
 76 | bot = 2
 77 | 
 78 | [[types.type-2-0]]
 79 | name = "none"
 80 | top = 25
 81 | bot = 22
 82 | 
 83 | [[types.type-2-0]]
 84 | name = "imm"
 85 | top = 1
 86 | bot = 0
 87 | 
 88 | [[types.type-2-0]]
 89 | name = "rs1_Register_int"
 90 | top = 4
 91 | bot = 0
 92 | 
 93 | [[types.type-2-0]]
 94 | name = "none"
 95 | top = 14
 96 | bot = 12
 97 | 
 98 | [[types.type-2-0]]
 99 | name = "rd_Register_int"
100 | top = 4
101 | bot = 0
102 | 
103 | [[types.type-2-0]]
104 | name = "none"
105 | top = 6
106 | bot = 0
107 | 
108 | [[types.type-4-0]]
109 | name = "none"
110 | top = 31
111 | bot = 31
112 | 
113 | [[types.type-4-0]]
114 | name = "imm"
115 | top = 2
116 | bot = 2
117 | 
118 | [[types.type-4-0]]
119 | name = "none"
120 | top = 29
121 | bot = 28
122 | 
123 | [[types.type-4-0]]
124 | name = "imm"
125 | top = 1
126 | bot = 0
127 | 
128 | [[types.type-4-0]]
129 | name = "none"
130 | top = 25
131 | bot = 25
132 | 
133 | [[types.type-4-0]]
134 | name = "rs2_Register_int"
135 | top = 4
136 | bot = 0
137 | 
138 | [[types.type-4-0]]
139 | name = "rs1_Register_int"
140 | top = 4
141 | bot = 0
142 | 
143 | [[types.type-4-0]]
144 | name = "none"
145 | top = 14
146 | bot = 12
147 | 
148 | [[types.type-4-0]]
149 | name = "rd_Register_int"
150 | top = 4
151 | bot = 0
152 | 
153 | [[types.type-4-0]]
154 | name = "none"
155 | top = 6
156 | bot = 0
157 | 
158 | [format-2-0]
159 | type = "type-2-0"
160 | 
161 | [format-4-0]
162 | type = "type-4-0"
163 | 
164 | [mappings]
165 | names = ["Register_int", "Register_float"]
166 | number = 32
167 | Register_int = [
168 |     "zero",
169 |     "ra",
170 |     "sp",
171 |     "gp",
172 |     "tp",
173 |     "t0",
174 |     "t1",
175 |     "t2",
176 |     "s0",
177 |     "s1",
178 |     "a0",
179 |     "a1",
180 |     "a2",
181 |     "a3",
182 |     "a4",
183 |     "a5",
184 |     "a6",
185 |     "a7",
186 |     "s2",
187 |     "s3",
188 |     "s4",
189 |     "s5",
190 |     "s6",
191 |     "s7",
192 |     "s8",
193 |     "s9",
194 |     "s10",
195 |     "s11",
196 |     "t3",
197 |     "t4",
198 |     "t5",
199 |     "t6",
200 | ]
201 | Register_float = [
202 |     "ft0",
203 |     "ft1",
204 |     "ft2",
205 |     "ft3",
206 |     "ft4",
207 |     "ft5",
208 |     "ft6",
209 |     "ft7",
210 |     "fs0",
211 |     "fs1",
212 |     "fa0",
213 |     "fa1",
214 |     "fa2",
215 |     "fa3",
216 |     "fa4",
217 |     "fa5",
218 |     "fa6",
219 |     "fa7",
220 |     "fs2",
221 |     "fs3",
222 |     "fs4",
223 |     "fs5",
224 |     "fs6",
225 |     "fs7",
226 |     "fs8",
227 |     "fs9",
228 |     "fs10",
229 |     "fs11",
230 |     "ft8",
231 |     "ft9",
232 |     "ft10",
233 |     "ft11",
234 | ]
235 | 
236 | [format-2-0.repr]
237 | default = "$name$.%imm% %rd_Register_int%, %rs1_Register_int%"
238 | 
239 | [format-4-0.repr]
240 | default = "$name$.%imm% %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%"
241 | 
242 | [format-2-0.instructions."mop.r"]
243 | mask = 0xb3c0707f
244 | match = 0x81c04073
245 | unsigned = true
246 | 
247 | [format-4-0.instructions."mop.rr"]
248 | mask = 0xb200707f
249 | match = 0x82004073
250 | unsigned = true
251 | 


--------------------------------------------------------------------------------
/toml/RV_Zknh.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZknh" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "none",
 29 |         32,
 30 |         "u32",
 31 |     ],
 32 |     [
 33 |         "imm",
 34 |         32,
 35 |         "VInt",
 36 |     ],
 37 |     [
 38 |         "himm",
 39 |         32,
 40 |         "VInt",
 41 |         "hex",
 42 |     ],
 43 | ]
 44 | 
 45 | [types]
 46 | names = ["type-1-0"]
 47 | [[types.type-1-0]]
 48 | name = "none"
 49 | top = 31
 50 | bot = 20
 51 | 
 52 | [[types.type-1-0]]
 53 | name = "rs1_Register_int"
 54 | top = 4
 55 | bot = 0
 56 | 
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 14
 60 | bot = 12
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "rd_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "none"
 69 | top = 6
 70 | bot = 0
 71 | 
 72 | [format-1-0]
 73 | type = "type-1-0"
 74 | 
 75 | [mappings]
 76 | names = ["Register_int", "Register_float"]
 77 | number = 32
 78 | Register_int = [
 79 |     "zero",
 80 |     "ra",
 81 |     "sp",
 82 |     "gp",
 83 |     "tp",
 84 |     "t0",
 85 |     "t1",
 86 |     "t2",
 87 |     "s0",
 88 |     "s1",
 89 |     "a0",
 90 |     "a1",
 91 |     "a2",
 92 |     "a3",
 93 |     "a4",
 94 |     "a5",
 95 |     "a6",
 96 |     "a7",
 97 |     "s2",
 98 |     "s3",
 99 |     "s4",
100 |     "s5",
101 |     "s6",
102 |     "s7",
103 |     "s8",
104 |     "s9",
105 |     "s10",
106 |     "s11",
107 |     "t3",
108 |     "t4",
109 |     "t5",
110 |     "t6",
111 | ]
112 | Register_float = [
113 |     "ft0",
114 |     "ft1",
115 |     "ft2",
116 |     "ft3",
117 |     "ft4",
118 |     "ft5",
119 |     "ft6",
120 |     "ft7",
121 |     "fs0",
122 |     "fs1",
123 |     "fa0",
124 |     "fa1",
125 |     "fa2",
126 |     "fa3",
127 |     "fa4",
128 |     "fa5",
129 |     "fa6",
130 |     "fa7",
131 |     "fs2",
132 |     "fs3",
133 |     "fs4",
134 |     "fs5",
135 |     "fs6",
136 |     "fs7",
137 |     "fs8",
138 |     "fs9",
139 |     "fs10",
140 |     "fs11",
141 |     "ft8",
142 |     "ft9",
143 |     "ft10",
144 |     "ft11",
145 | ]
146 | 
147 | [format-1-0.repr]
148 | default = "$name$ %rd_Register_int%, %rs1_Register_int%"
149 | 
150 | [format-1-0.instructions.sha256sig0]
151 | mask = 0xfff0707f
152 | match = 0x10201013
153 | 
154 | [format-1-0.instructions.sha256sig1]
155 | mask = 0xfff0707f
156 | match = 0x10301013
157 | 
158 | [format-1-0.instructions.sha256sum0]
159 | mask = 0xfff0707f
160 | match = 0x10001013
161 | 
162 | [format-1-0.instructions.sha256sum1]
163 | mask = 0xfff0707f
164 | match = 0x10101013
165 | 


--------------------------------------------------------------------------------
/toml/RV_Zksed.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZksed" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "rs2_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs2_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "bs",
 39 |         2,
 40 |         "u8",
 41 |         "hex",
 42 |     ],
 43 |     [
 44 |         "none",
 45 |         32,
 46 |         "u32",
 47 |     ],
 48 |     [
 49 |         "imm",
 50 |         32,
 51 |         "VInt",
 52 |     ],
 53 |     [
 54 |         "himm",
 55 |         32,
 56 |         "VInt",
 57 |         "hex",
 58 |     ],
 59 | ]
 60 | 
 61 | [types]
 62 | names = ["type-1-0"]
 63 | [[types.type-1-0]]
 64 | name = "bs"
 65 | top = 1
 66 | bot = 0
 67 | 
 68 | [[types.type-1-0]]
 69 | name = "none"
 70 | top = 29
 71 | bot = 25
 72 | 
 73 | [[types.type-1-0]]
 74 | name = "rs2_Register_int"
 75 | top = 4
 76 | bot = 0
 77 | 
 78 | [[types.type-1-0]]
 79 | name = "rs1_Register_int"
 80 | top = 4
 81 | bot = 0
 82 | 
 83 | [[types.type-1-0]]
 84 | name = "none"
 85 | top = 14
 86 | bot = 12
 87 | 
 88 | [[types.type-1-0]]
 89 | name = "rd_Register_int"
 90 | top = 4
 91 | bot = 0
 92 | 
 93 | [[types.type-1-0]]
 94 | name = "none"
 95 | top = 6
 96 | bot = 0
 97 | 
 98 | [format-1-0]
 99 | type = "type-1-0"
100 | 
101 | [mappings]
102 | names = ["Register_int", "Register_float"]
103 | number = 32
104 | Register_int = [
105 |     "zero",
106 |     "ra",
107 |     "sp",
108 |     "gp",
109 |     "tp",
110 |     "t0",
111 |     "t1",
112 |     "t2",
113 |     "s0",
114 |     "s1",
115 |     "a0",
116 |     "a1",
117 |     "a2",
118 |     "a3",
119 |     "a4",
120 |     "a5",
121 |     "a6",
122 |     "a7",
123 |     "s2",
124 |     "s3",
125 |     "s4",
126 |     "s5",
127 |     "s6",
128 |     "s7",
129 |     "s8",
130 |     "s9",
131 |     "s10",
132 |     "s11",
133 |     "t3",
134 |     "t4",
135 |     "t5",
136 |     "t6",
137 | ]
138 | Register_float = [
139 |     "ft0",
140 |     "ft1",
141 |     "ft2",
142 |     "ft3",
143 |     "ft4",
144 |     "ft5",
145 |     "ft6",
146 |     "ft7",
147 |     "fs0",
148 |     "fs1",
149 |     "fa0",
150 |     "fa1",
151 |     "fa2",
152 |     "fa3",
153 |     "fa4",
154 |     "fa5",
155 |     "fa6",
156 |     "fa7",
157 |     "fs2",
158 |     "fs3",
159 |     "fs4",
160 |     "fs5",
161 |     "fs6",
162 |     "fs7",
163 |     "fs8",
164 |     "fs9",
165 |     "fs10",
166 |     "fs11",
167 |     "ft8",
168 |     "ft9",
169 |     "ft10",
170 |     "ft11",
171 | ]
172 | 
173 | [format-1-0.repr]
174 | default = "$name$ %rd_Register_int%, %rs1_Register_int%, %rs2_Register_int%, %bs%"
175 | 
176 | [format-1-0.instructions.sm4ed]
177 | mask = 0x3e00707f
178 | match = 0x30000033
179 | 
180 | [format-1-0.instructions.sm4ks]
181 | mask = 0x3e00707f
182 | match = 0x34000033
183 | 


--------------------------------------------------------------------------------
/toml/RV_Zksh.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZksh" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "rd_Register_int",
  9 |         5,
 10 |         "Register_int",
 11 |     ],
 12 |     [
 13 |         "rd_Register_float",
 14 |         5,
 15 |         "Register_float",
 16 |     ],
 17 |     [
 18 |         "rs1_Register_int",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rs1_Register_float",
 24 |         5,
 25 |         "Register_float",
 26 |     ],
 27 |     [
 28 |         "none",
 29 |         32,
 30 |         "u32",
 31 |     ],
 32 |     [
 33 |         "imm",
 34 |         32,
 35 |         "VInt",
 36 |     ],
 37 |     [
 38 |         "himm",
 39 |         32,
 40 |         "VInt",
 41 |         "hex",
 42 |     ],
 43 | ]
 44 | 
 45 | [types]
 46 | names = ["type-1-0"]
 47 | [[types.type-1-0]]
 48 | name = "none"
 49 | top = 31
 50 | bot = 20
 51 | 
 52 | [[types.type-1-0]]
 53 | name = "rs1_Register_int"
 54 | top = 4
 55 | bot = 0
 56 | 
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 14
 60 | bot = 12
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "rd_Register_int"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "none"
 69 | top = 6
 70 | bot = 0
 71 | 
 72 | [format-1-0]
 73 | type = "type-1-0"
 74 | 
 75 | [mappings]
 76 | names = ["Register_int", "Register_float"]
 77 | number = 32
 78 | Register_int = [
 79 |     "zero",
 80 |     "ra",
 81 |     "sp",
 82 |     "gp",
 83 |     "tp",
 84 |     "t0",
 85 |     "t1",
 86 |     "t2",
 87 |     "s0",
 88 |     "s1",
 89 |     "a0",
 90 |     "a1",
 91 |     "a2",
 92 |     "a3",
 93 |     "a4",
 94 |     "a5",
 95 |     "a6",
 96 |     "a7",
 97 |     "s2",
 98 |     "s3",
 99 |     "s4",
100 |     "s5",
101 |     "s6",
102 |     "s7",
103 |     "s8",
104 |     "s9",
105 |     "s10",
106 |     "s11",
107 |     "t3",
108 |     "t4",
109 |     "t5",
110 |     "t6",
111 | ]
112 | Register_float = [
113 |     "ft0",
114 |     "ft1",
115 |     "ft2",
116 |     "ft3",
117 |     "ft4",
118 |     "ft5",
119 |     "ft6",
120 |     "ft7",
121 |     "fs0",
122 |     "fs1",
123 |     "fa0",
124 |     "fa1",
125 |     "fa2",
126 |     "fa3",
127 |     "fa4",
128 |     "fa5",
129 |     "fa6",
130 |     "fa7",
131 |     "fs2",
132 |     "fs3",
133 |     "fs4",
134 |     "fs5",
135 |     "fs6",
136 |     "fs7",
137 |     "fs8",
138 |     "fs9",
139 |     "fs10",
140 |     "fs11",
141 |     "ft8",
142 |     "ft9",
143 |     "ft10",
144 |     "ft11",
145 | ]
146 | 
147 | [format-1-0.repr]
148 | default = "$name$ %rd_Register_int%, %rs1_Register_int%"
149 | 
150 | [format-1-0.instructions.sm3p0]
151 | mask = 0xfff0707f
152 | match = 0x10801013
153 | 
154 | [format-1-0.instructions.sm3p1]
155 | mask = 0xfff0707f
156 | match = 0x10901013
157 | 


--------------------------------------------------------------------------------
/toml/RV_Zvbc.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZvbc" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0"]
  6 | parts = [
  7 |     [
  8 |         "vm",
  9 |         1,
 10 |         "Mapping_vm",
 11 |     ],
 12 |     [
 13 |         "vs2",
 14 |         5,
 15 |         "Register_vec",
 16 |     ],
 17 |     [
 18 |         "vs1",
 19 |         5,
 20 |         "Register_vec",
 21 |     ],
 22 |     [
 23 |         "vd",
 24 |         5,
 25 |         "Register_vec",
 26 |     ],
 27 |     [
 28 |         "rs1_Register_int",
 29 |         5,
 30 |         "Register_int",
 31 |     ],
 32 |     [
 33 |         "rs1_Register_float",
 34 |         5,
 35 |         "Register_float",
 36 |     ],
 37 |     [
 38 |         "none",
 39 |         32,
 40 |         "u32",
 41 |     ],
 42 |     [
 43 |         "imm",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 |     [
 48 |         "himm",
 49 |         32,
 50 |         "VInt",
 51 |         "hex",
 52 |     ],
 53 | ]
 54 | 
 55 | [types]
 56 | names = ["type-1-0", "type-2-0"]
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 31
 60 | bot = 26
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "vm"
 64 | top = 0
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "vs2"
 69 | top = 4
 70 | bot = 0
 71 | 
 72 | [[types.type-1-0]]
 73 | name = "vs1"
 74 | top = 4
 75 | bot = 0
 76 | 
 77 | [[types.type-1-0]]
 78 | name = "none"
 79 | top = 14
 80 | bot = 12
 81 | 
 82 | [[types.type-1-0]]
 83 | name = "vd"
 84 | top = 4
 85 | bot = 0
 86 | 
 87 | [[types.type-1-0]]
 88 | name = "none"
 89 | top = 6
 90 | bot = 0
 91 | 
 92 | [[types.type-2-0]]
 93 | name = "none"
 94 | top = 31
 95 | bot = 26
 96 | 
 97 | [[types.type-2-0]]
 98 | name = "vm"
 99 | top = 0
100 | bot = 0
101 | 
102 | [[types.type-2-0]]
103 | name = "vs2"
104 | top = 4
105 | bot = 0
106 | 
107 | [[types.type-2-0]]
108 | name = "rs1_Register_int"
109 | top = 4
110 | bot = 0
111 | 
112 | [[types.type-2-0]]
113 | name = "none"
114 | top = 14
115 | bot = 12
116 | 
117 | [[types.type-2-0]]
118 | name = "vd"
119 | top = 4
120 | bot = 0
121 | 
122 | [[types.type-2-0]]
123 | name = "none"
124 | top = 6
125 | bot = 0
126 | 
127 | [format-1-0]
128 | type = "type-1-0"
129 | 
130 | [format-2-0]
131 | type = "type-2-0"
132 | 
133 | [mappings]
134 | names = ["Register_int", "Register_float", "Register_vec", "Mapping_vm"]
135 | number = 32
136 | Register_int = [
137 |     "zero",
138 |     "ra",
139 |     "sp",
140 |     "gp",
141 |     "tp",
142 |     "t0",
143 |     "t1",
144 |     "t2",
145 |     "s0",
146 |     "s1",
147 |     "a0",
148 |     "a1",
149 |     "a2",
150 |     "a3",
151 |     "a4",
152 |     "a5",
153 |     "a6",
154 |     "a7",
155 |     "s2",
156 |     "s3",
157 |     "s4",
158 |     "s5",
159 |     "s6",
160 |     "s7",
161 |     "s8",
162 |     "s9",
163 |     "s10",
164 |     "s11",
165 |     "t3",
166 |     "t4",
167 |     "t5",
168 |     "t6",
169 | ]
170 | Register_float = [
171 |     "ft0",
172 |     "ft1",
173 |     "ft2",
174 |     "ft3",
175 |     "ft4",
176 |     "ft5",
177 |     "ft6",
178 |     "ft7",
179 |     "fs0",
180 |     "fs1",
181 |     "fa0",
182 |     "fa1",
183 |     "fa2",
184 |     "fa3",
185 |     "fa4",
186 |     "fa5",
187 |     "fa6",
188 |     "fa7",
189 |     "fs2",
190 |     "fs3",
191 |     "fs4",
192 |     "fs5",
193 |     "fs6",
194 |     "fs7",
195 |     "fs8",
196 |     "fs9",
197 |     "fs10",
198 |     "fs11",
199 |     "ft8",
200 |     "ft9",
201 |     "ft10",
202 |     "ft11",
203 | ]
204 | Register_vec = [
205 |     "v0",
206 |     "v1",
207 |     "v2",
208 |     "v3",
209 |     "v4",
210 |     "v5",
211 |     "v6",
212 |     "v7",
213 |     "v8",
214 |     "v9",
215 |     "v10",
216 |     "v11",
217 |     "v12",
218 |     "v13",
219 |     "v14",
220 |     "v15",
221 |     "v16",
222 |     "v17",
223 |     "v18",
224 |     "v19",
225 |     "v20",
226 |     "v21",
227 |     "v22",
228 |     "v23",
229 |     "v24",
230 |     "v25",
231 |     "v26",
232 |     "v27",
233 |     "v28",
234 |     "v29",
235 |     "v30",
236 |     "v31",
237 | ]
238 | Mapping_vm = [", v0.t", ""]
239 | 
240 | [format-1-0.repr]
241 | default = "$name$ %vd%, %vs2%, %vs1%%vm%"
242 | 
243 | [format-2-0.repr]
244 | default = "$name$ %vd%, %vs2%, %rs1_Register_int%%vm%"
245 | 
246 | [format-1-0.instructions."vclmul.vv"]
247 | mask = 0xfc00707f
248 | match = 0x30002057
249 | 
250 | [format-1-0.instructions."vclmulh.vv"]
251 | mask = 0xfc00707f
252 | match = 0x34002057
253 | 
254 | [format-2-0.instructions."vclmul.vx"]
255 | mask = 0xfc00707f
256 | match = 0x30006057
257 | 
258 | [format-2-0.instructions."vclmulh.vx"]
259 | mask = 0xfc00707f
260 | match = 0x34006057
261 | 


--------------------------------------------------------------------------------
/toml/RV_Zvkg.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZvkg" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0"]
  6 | parts = [
  7 |     [
  8 |         "vs2",
  9 |         5,
 10 |         "Register_vec",
 11 |     ],
 12 |     [
 13 |         "vs1",
 14 |         5,
 15 |         "Register_vec",
 16 |     ],
 17 |     [
 18 |         "vd",
 19 |         5,
 20 |         "Register_vec",
 21 |     ],
 22 |     [
 23 |         "none",
 24 |         32,
 25 |         "u32",
 26 |     ],
 27 |     [
 28 |         "imm",
 29 |         32,
 30 |         "VInt",
 31 |     ],
 32 |     [
 33 |         "himm",
 34 |         32,
 35 |         "VInt",
 36 |         "hex",
 37 |     ],
 38 | ]
 39 | 
 40 | [types]
 41 | names = ["type-1-0", "type-2-0"]
 42 | [[types.type-1-0]]
 43 | name = "none"
 44 | top = 31
 45 | bot = 25
 46 | 
 47 | [[types.type-1-0]]
 48 | name = "vs2"
 49 | top = 4
 50 | bot = 0
 51 | 
 52 | [[types.type-1-0]]
 53 | name = "vs1"
 54 | top = 4
 55 | bot = 0
 56 | 
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 14
 60 | bot = 12
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "vd"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "none"
 69 | top = 6
 70 | bot = 0
 71 | 
 72 | [[types.type-2-0]]
 73 | name = "none"
 74 | top = 31
 75 | bot = 25
 76 | 
 77 | [[types.type-2-0]]
 78 | name = "vs2"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type-2-0]]
 83 | name = "none"
 84 | top = 19
 85 | bot = 12
 86 | 
 87 | [[types.type-2-0]]
 88 | name = "vd"
 89 | top = 4
 90 | bot = 0
 91 | 
 92 | [[types.type-2-0]]
 93 | name = "none"
 94 | top = 6
 95 | bot = 0
 96 | 
 97 | [format-1-0]
 98 | type = "type-1-0"
 99 | 
100 | [format-2-0]
101 | type = "type-2-0"
102 | 
103 | [mappings]
104 | names = ["Register_vec"]
105 | number = 32
106 | Register_vec = [
107 |     "v0",
108 |     "v1",
109 |     "v2",
110 |     "v3",
111 |     "v4",
112 |     "v5",
113 |     "v6",
114 |     "v7",
115 |     "v8",
116 |     "v9",
117 |     "v10",
118 |     "v11",
119 |     "v12",
120 |     "v13",
121 |     "v14",
122 |     "v15",
123 |     "v16",
124 |     "v17",
125 |     "v18",
126 |     "v19",
127 |     "v20",
128 |     "v21",
129 |     "v22",
130 |     "v23",
131 |     "v24",
132 |     "v25",
133 |     "v26",
134 |     "v27",
135 |     "v28",
136 |     "v29",
137 |     "v30",
138 |     "v31",
139 | ]
140 | 
141 | [format-1-0.repr]
142 | default = "$name$ %vd%, %vs2%, %vs1%"
143 | 
144 | [format-2-0.repr]
145 | default = "$name$ %vd%, %vs2%"
146 | 
147 | [format-1-0.instructions."vghsh.vv"]
148 | mask = 0xfe00707f
149 | match = 0xb2002077
150 | 
151 | [format-2-0.instructions."vgmul.vv"]
152 | mask = 0xfe0ff07f
153 | match = 0xa208a077
154 | 


--------------------------------------------------------------------------------
/toml/RV_Zvkned.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZvkned" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format_1-0", "format_2-0"]
  6 | parts = [
  7 |     [
  8 |         "vs2",
  9 |         5,
 10 |         "Register_vec",
 11 |     ],
 12 |     [
 13 |         "vd",
 14 |         5,
 15 |         "Register_vec",
 16 |     ],
 17 |     [
 18 |         "none",
 19 |         32,
 20 |         "u32",
 21 |     ],
 22 |     [
 23 |         "imm",
 24 |         32,
 25 |         "VInt",
 26 |     ],
 27 |     [
 28 |         "himm",
 29 |         32,
 30 |         "VInt",
 31 |         "hex",
 32 |     ],
 33 | ]
 34 | 
 35 | [types]
 36 | names = ["type_1-0", "type_2-0"]
 37 | [[types.type_1-0]]
 38 | name = "none"
 39 | top = 31
 40 | bot = 25
 41 | 
 42 | [[types.type_1-0]]
 43 | name = "vs2"
 44 | top = 4
 45 | bot = 0
 46 | 
 47 | [[types.type_1-0]]
 48 | name = "none"
 49 | top = 19
 50 | bot = 12
 51 | 
 52 | [[types.type_1-0]]
 53 | name = "vd"
 54 | top = 4
 55 | bot = 0
 56 | 
 57 | [[types.type_1-0]]
 58 | name = "none"
 59 | top = 6
 60 | bot = 0
 61 | 
 62 | [[types.type_2-0]]
 63 | name = "none"
 64 | top = 31
 65 | bot = 25
 66 | 
 67 | [[types.type_2-0]]
 68 | name = "vs2"
 69 | top = 4
 70 | bot = 0
 71 | 
 72 | [[types.type_2-0]]
 73 | name = "himm"
 74 | top = 4
 75 | bot = 0
 76 | 
 77 | [[types.type_2-0]]
 78 | name = "none"
 79 | top = 14
 80 | bot = 12
 81 | 
 82 | [[types.type_2-0]]
 83 | name = "vd"
 84 | top = 4
 85 | bot = 0
 86 | 
 87 | [[types.type_2-0]]
 88 | name = "none"
 89 | top = 6
 90 | bot = 0
 91 | 
 92 | [format_1-0]
 93 | type = "type_1-0"
 94 | 
 95 | [format_2-0]
 96 | type = "type_2-0"
 97 | 
 98 | [mappings]
 99 | names = ["Register_vec"]
100 | number = 32
101 | Register_vec = [
102 |     "v0",
103 |     "v1",
104 |     "v2",
105 |     "v3",
106 |     "v4",
107 |     "v5",
108 |     "v6",
109 |     "v7",
110 |     "v8",
111 |     "v9",
112 |     "v10",
113 |     "v11",
114 |     "v12",
115 |     "v13",
116 |     "v14",
117 |     "v15",
118 |     "v16",
119 |     "v17",
120 |     "v18",
121 |     "v19",
122 |     "v20",
123 |     "v21",
124 |     "v22",
125 |     "v23",
126 |     "v24",
127 |     "v25",
128 |     "v26",
129 |     "v27",
130 |     "v28",
131 |     "v29",
132 |     "v30",
133 |     "v31",
134 | ]
135 | 
136 | [format_1-0.repr]
137 | default = "$name$ %vd%, %vs2%"
138 | 
139 | [format_2-0.repr]
140 | default = "$name$ %vd%, %vs2%, %himm%"
141 | 
142 | [format_1-0.instructions."vaesdf.vs"]
143 | mask = 0xfe0ff07f
144 | match = 0xa600a077
145 | 
146 | [format_1-0.instructions."vaesdf.vv"]
147 | mask = 0xfe0ff07f
148 | match = 0xa200a077
149 | 
150 | [format_1-0.instructions."vaesdm.vs"]
151 | mask = 0xfe0ff07f
152 | match = 0xa6002077
153 | 
154 | [format_1-0.instructions."vaesdm.vv"]
155 | mask = 0xfe0ff07f
156 | match = 0xa2002077
157 | 
158 | [format_1-0.instructions."vaesef.vs"]
159 | mask = 0xfe0ff07f
160 | match = 0xa601a077
161 | 
162 | [format_1-0.instructions."vaesef.vv"]
163 | mask = 0xfe0ff07f
164 | match = 0xa201a077
165 | 
166 | [format_1-0.instructions."vaesem.vs"]
167 | mask = 0xfe0ff07f
168 | match = 0xa6012077
169 | 
170 | [format_1-0.instructions."vaesem.vv"]
171 | mask = 0xfe0ff07f
172 | match = 0xa2012077
173 | 
174 | [format_1-0.instructions."vaesz.vs"]
175 | mask = 0xfe0ff07f
176 | match = 0xa603a077
177 | 
178 | [format_2-0.instructions."vaeskf1.vi"]
179 | mask = 0xfe00707f
180 | match = 0x8a002077
181 | unsigned = true
182 | 
183 | [format_2-0.instructions."vaeskf2.vi"]
184 | mask = 0xfe00707f
185 | match = 0xaa002077
186 | unsigned = true
187 | 


--------------------------------------------------------------------------------
/toml/RV_Zvknha.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZvknha" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "vs2",
  9 |         5,
 10 |         "Register_vec",
 11 |     ],
 12 |     [
 13 |         "vs1",
 14 |         5,
 15 |         "Register_vec",
 16 |     ],
 17 |     [
 18 |         "vd",
 19 |         5,
 20 |         "Register_vec",
 21 |     ],
 22 |     [
 23 |         "none",
 24 |         32,
 25 |         "u32",
 26 |     ],
 27 |     [
 28 |         "imm",
 29 |         32,
 30 |         "VInt",
 31 |     ],
 32 |     [
 33 |         "himm",
 34 |         32,
 35 |         "VInt",
 36 |         "hex",
 37 |     ],
 38 | ]
 39 | 
 40 | [types]
 41 | names = ["type-1-0"]
 42 | [[types.type-1-0]]
 43 | name = "none"
 44 | top = 31
 45 | bot = 25
 46 | 
 47 | [[types.type-1-0]]
 48 | name = "vs2"
 49 | top = 4
 50 | bot = 0
 51 | 
 52 | [[types.type-1-0]]
 53 | name = "vs1"
 54 | top = 4
 55 | bot = 0
 56 | 
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 14
 60 | bot = 12
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "vd"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "none"
 69 | top = 6
 70 | bot = 0
 71 | 
 72 | [format-1-0]
 73 | type = "type-1-0"
 74 | 
 75 | [mappings]
 76 | names = ["Register_vec"]
 77 | number = 32
 78 | Register_vec = [
 79 |     "v0",
 80 |     "v1",
 81 |     "v2",
 82 |     "v3",
 83 |     "v4",
 84 |     "v5",
 85 |     "v6",
 86 |     "v7",
 87 |     "v8",
 88 |     "v9",
 89 |     "v10",
 90 |     "v11",
 91 |     "v12",
 92 |     "v13",
 93 |     "v14",
 94 |     "v15",
 95 |     "v16",
 96 |     "v17",
 97 |     "v18",
 98 |     "v19",
 99 |     "v20",
100 |     "v21",
101 |     "v22",
102 |     "v23",
103 |     "v24",
104 |     "v25",
105 |     "v26",
106 |     "v27",
107 |     "v28",
108 |     "v29",
109 |     "v30",
110 |     "v31",
111 | ]
112 | 
113 | [format-1-0.repr]
114 | default = "$name$ %vd%, %vs2%, %vs1%"
115 | 
116 | [format-1-0.instructions."vsha2ch.vv"]
117 | mask = 0xfe00707f
118 | match = 0xba002077
119 | 
120 | [format-1-0.instructions."vsha2cl.vv"]
121 | mask = 0xfe00707f
122 | match = 0xbe002077
123 | 
124 | [format-1-0.instructions."vsha2ms.vv"]
125 | mask = 0xfe00707f
126 | match = 0xb6002077
127 | 


--------------------------------------------------------------------------------
/toml/RV_Zvknhb.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZvknhb" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0"]
  6 | parts = [
  7 |     [
  8 |         "vs2",
  9 |         5,
 10 |         "Register_vec",
 11 |     ],
 12 |     [
 13 |         "vs1",
 14 |         5,
 15 |         "Register_vec",
 16 |     ],
 17 |     [
 18 |         "vd",
 19 |         5,
 20 |         "Register_vec",
 21 |     ],
 22 |     [
 23 |         "none",
 24 |         32,
 25 |         "u32",
 26 |     ],
 27 |     [
 28 |         "imm",
 29 |         32,
 30 |         "VInt",
 31 |     ],
 32 |     [
 33 |         "himm",
 34 |         32,
 35 |         "VInt",
 36 |         "hex",
 37 |     ],
 38 | ]
 39 | 
 40 | [types]
 41 | names = ["type-1-0"]
 42 | [[types.type-1-0]]
 43 | name = "none"
 44 | top = 31
 45 | bot = 25
 46 | 
 47 | [[types.type-1-0]]
 48 | name = "vs2"
 49 | top = 4
 50 | bot = 0
 51 | 
 52 | [[types.type-1-0]]
 53 | name = "vs1"
 54 | top = 4
 55 | bot = 0
 56 | 
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 14
 60 | bot = 12
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "vd"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "none"
 69 | top = 6
 70 | bot = 0
 71 | 
 72 | [format-1-0]
 73 | type = "type-1-0"
 74 | 
 75 | [mappings]
 76 | names = ["Register_vec"]
 77 | number = 32
 78 | Register_vec = [
 79 |     "v0",
 80 |     "v1",
 81 |     "v2",
 82 |     "v3",
 83 |     "v4",
 84 |     "v5",
 85 |     "v6",
 86 |     "v7",
 87 |     "v8",
 88 |     "v9",
 89 |     "v10",
 90 |     "v11",
 91 |     "v12",
 92 |     "v13",
 93 |     "v14",
 94 |     "v15",
 95 |     "v16",
 96 |     "v17",
 97 |     "v18",
 98 |     "v19",
 99 |     "v20",
100 |     "v21",
101 |     "v22",
102 |     "v23",
103 |     "v24",
104 |     "v25",
105 |     "v26",
106 |     "v27",
107 |     "v28",
108 |     "v29",
109 |     "v30",
110 |     "v31",
111 | ]
112 | 
113 | [format-1-0.repr]
114 | default = "$name$ %vd%, %vs2%, %vs1%"
115 | 
116 | [format-1-0.instructions."vsha2ch.vv"]
117 | mask = 0xfe00707f
118 | match = 0xba002077
119 | 
120 | [format-1-0.instructions."vsha2cl.vv"]
121 | mask = 0xfe00707f
122 | match = 0xbe002077
123 | 
124 | [format-1-0.instructions."vsha2ms.vv"]
125 | mask = 0xfe00707f
126 | match = 0xb6002077
127 | 


--------------------------------------------------------------------------------
/toml/RV_Zvksed.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZvksed" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0"]
  6 | parts = [
  7 |     [
  8 |         "vs2",
  9 |         5,
 10 |         "Register_vec",
 11 |     ],
 12 |     [
 13 |         "vd",
 14 |         5,
 15 |         "Register_vec",
 16 |     ],
 17 |     [
 18 |         "none",
 19 |         32,
 20 |         "u32",
 21 |     ],
 22 |     [
 23 |         "imm",
 24 |         32,
 25 |         "VInt",
 26 |     ],
 27 |     [
 28 |         "himm",
 29 |         32,
 30 |         "VInt",
 31 |         "hex",
 32 |     ],
 33 | ]
 34 | 
 35 | [types]
 36 | names = ["type-1-0", "type-2-0"]
 37 | [[types.type-1-0]]
 38 | name = "none"
 39 | top = 31
 40 | bot = 25
 41 | 
 42 | [[types.type-1-0]]
 43 | name = "vs2"
 44 | top = 4
 45 | bot = 0
 46 | 
 47 | [[types.type-1-0]]
 48 | name = "himm"
 49 | top = 4
 50 | bot = 0
 51 | 
 52 | [[types.type-1-0]]
 53 | name = "none"
 54 | top = 14
 55 | bot = 12
 56 | 
 57 | [[types.type-1-0]]
 58 | name = "vd"
 59 | top = 4
 60 | bot = 0
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "none"
 64 | top = 6
 65 | bot = 0
 66 | 
 67 | [[types.type-2-0]]
 68 | name = "none"
 69 | top = 31
 70 | bot = 25
 71 | 
 72 | [[types.type-2-0]]
 73 | name = "vs2"
 74 | top = 4
 75 | bot = 0
 76 | 
 77 | [[types.type-2-0]]
 78 | name = "none"
 79 | top = 19
 80 | bot = 12
 81 | 
 82 | [[types.type-2-0]]
 83 | name = "vd"
 84 | top = 4
 85 | bot = 0
 86 | 
 87 | [[types.type-2-0]]
 88 | name = "none"
 89 | top = 6
 90 | bot = 0
 91 | 
 92 | [format-1-0]
 93 | type = "type-1-0"
 94 | 
 95 | [format-2-0]
 96 | type = "type-2-0"
 97 | 
 98 | [mappings]
 99 | names = ["Register_vec"]
100 | number = 32
101 | Register_vec = [
102 |     "v0",
103 |     "v1",
104 |     "v2",
105 |     "v3",
106 |     "v4",
107 |     "v5",
108 |     "v6",
109 |     "v7",
110 |     "v8",
111 |     "v9",
112 |     "v10",
113 |     "v11",
114 |     "v12",
115 |     "v13",
116 |     "v14",
117 |     "v15",
118 |     "v16",
119 |     "v17",
120 |     "v18",
121 |     "v19",
122 |     "v20",
123 |     "v21",
124 |     "v22",
125 |     "v23",
126 |     "v24",
127 |     "v25",
128 |     "v26",
129 |     "v27",
130 |     "v28",
131 |     "v29",
132 |     "v30",
133 |     "v31",
134 | ]
135 | 
136 | [format-1-0.repr]
137 | default = "$name$ %vd%, %vs2%, %himm%"
138 | 
139 | [format-2-0.repr]
140 | default = "$name$ %vd%, %vs2%"
141 | 
142 | [format-1-0.instructions."vsm4k.vi"]
143 | mask = 0xfe00707f
144 | match = 0x86002077
145 | unsigned = true
146 | 
147 | [format-2-0.instructions."vsm4r.vs"]
148 | mask = 0xfe0ff07f
149 | match = 0xa6082077
150 | 
151 | [format-2-0.instructions."vsm4r.vv"]
152 | mask = 0xfe0ff07f
153 | match = 0xa2082077
154 | 


--------------------------------------------------------------------------------
/toml/RV_Zvksh.toml:
--------------------------------------------------------------------------------
  1 | set = "RVZvksh" # auto-generated, based on riscv-opcodes 5181d13bef845edfb511e3132a7e661090e3204b
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["format-1-0", "format-2-0"]
  6 | parts = [
  7 |     [
  8 |         "vs2",
  9 |         5,
 10 |         "Register_vec",
 11 |     ],
 12 |     [
 13 |         "vd",
 14 |         5,
 15 |         "Register_vec",
 16 |     ],
 17 |     [
 18 |         "vs1",
 19 |         5,
 20 |         "Register_vec",
 21 |     ],
 22 |     [
 23 |         "none",
 24 |         32,
 25 |         "u32",
 26 |     ],
 27 |     [
 28 |         "imm",
 29 |         32,
 30 |         "VInt",
 31 |     ],
 32 |     [
 33 |         "himm",
 34 |         32,
 35 |         "VInt",
 36 |         "hex",
 37 |     ],
 38 | ]
 39 | 
 40 | [types]
 41 | names = ["type-1-0", "type-2-0"]
 42 | [[types.type-1-0]]
 43 | name = "none"
 44 | top = 31
 45 | bot = 25
 46 | 
 47 | [[types.type-1-0]]
 48 | name = "vs2"
 49 | top = 4
 50 | bot = 0
 51 | 
 52 | [[types.type-1-0]]
 53 | name = "himm"
 54 | top = 4
 55 | bot = 0
 56 | 
 57 | [[types.type-1-0]]
 58 | name = "none"
 59 | top = 14
 60 | bot = 12
 61 | 
 62 | [[types.type-1-0]]
 63 | name = "vd"
 64 | top = 4
 65 | bot = 0
 66 | 
 67 | [[types.type-1-0]]
 68 | name = "none"
 69 | top = 6
 70 | bot = 0
 71 | 
 72 | [[types.type-2-0]]
 73 | name = "none"
 74 | top = 31
 75 | bot = 25
 76 | 
 77 | [[types.type-2-0]]
 78 | name = "vs2"
 79 | top = 4
 80 | bot = 0
 81 | 
 82 | [[types.type-2-0]]
 83 | name = "vs1"
 84 | top = 4
 85 | bot = 0
 86 | 
 87 | [[types.type-2-0]]
 88 | name = "none"
 89 | top = 14
 90 | bot = 12
 91 | 
 92 | [[types.type-2-0]]
 93 | name = "vd"
 94 | top = 4
 95 | bot = 0
 96 | 
 97 | [[types.type-2-0]]
 98 | name = "none"
 99 | top = 6
100 | bot = 0
101 | 
102 | [format-1-0]
103 | type = "type-1-0"
104 | 
105 | [format-2-0]
106 | type = "type-2-0"
107 | 
108 | [mappings]
109 | names = ["Register_vec"]
110 | number = 32
111 | Register_vec = [
112 |     "v0",
113 |     "v1",
114 |     "v2",
115 |     "v3",
116 |     "v4",
117 |     "v5",
118 |     "v6",
119 |     "v7",
120 |     "v8",
121 |     "v9",
122 |     "v10",
123 |     "v11",
124 |     "v12",
125 |     "v13",
126 |     "v14",
127 |     "v15",
128 |     "v16",
129 |     "v17",
130 |     "v18",
131 |     "v19",
132 |     "v20",
133 |     "v21",
134 |     "v22",
135 |     "v23",
136 |     "v24",
137 |     "v25",
138 |     "v26",
139 |     "v27",
140 |     "v28",
141 |     "v29",
142 |     "v30",
143 |     "v31",
144 | ]
145 | 
146 | [format-1-0.repr]
147 | default = "$name$ %vd%, %vs2%, %himm%"
148 | 
149 | [format-2-0.repr]
150 | default = "$name$ %vd%, %vs2%, %vs1%"
151 | 
152 | [format-1-0.instructions."vsm3c.vi"]
153 | mask = 0xfe00707f
154 | match = 0xae002077
155 | unsigned = true
156 | 
157 | [format-2-0.instructions."vsm3me.vv"]
158 | mask = 0xfe00707f
159 | match = 0x82002077
160 | 


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/toml/mips.toml:
--------------------------------------------------------------------------------
  1 | set = "MIPS"
  2 | width = 32
  3 | 
  4 | [formats]
  5 | names = ["r", "i", "j", "branch", "mem"]
  6 | parts = [
  7 |     [
  8 |         "opcode",
  9 |         6,
 10 |         "u8",
 11 |     ],
 12 |     [
 13 |         "rs",
 14 |         5,
 15 |         "Register_int",
 16 |     ],
 17 |     [
 18 |         "rt",
 19 |         5,
 20 |         "Register_int",
 21 |     ],
 22 |     [
 23 |         "rd",
 24 |         5,
 25 |         "Register_int",
 26 |     ],
 27 |     [
 28 |         "shamt",
 29 |         5,
 30 |         "u8",
 31 |     ],
 32 |     [
 33 |         "funct",
 34 |         6,
 35 |         "u8",
 36 |     ],
 37 |     [
 38 |         "imm",
 39 |         32,
 40 |         "VInt",
 41 |     ],
 42 |     [
 43 |         "addr",
 44 |         32,
 45 |         "VInt",
 46 |     ],
 47 | ]
 48 | 
 49 | [types]
 50 | names = ["R", "I", "J"]
 51 | R = [
 52 |     { name = "opcode", top = 5, bot = 0 },
 53 |     { name = "rs", top = 4, bot = 0 },
 54 |     { name = "rt", top = 4, bot = 0 },
 55 |     { name = "rd", top = 4, bot = 0 },
 56 |     { name = "shamt", top = 4, bot = 0 },
 57 |     { name = "funct", top = 5, bot = 0 },
 58 | ]
 59 | I = [
 60 |     { name = "opcode", top = 5, bot = 0 },
 61 |     { name = "rs", top = 4, bot = 0 },
 62 |     { name = "rt", top = 4, bot = 0 },
 63 |     { name = "imm", top = 15, bot = 0 },
 64 | ]
 65 | J = [
 66 |     { name = "opcode", top = 5, bot = 0 },
 67 |     { name = "addr", top = 25, bot = 0 },
 68 | ]
 69 | 
 70 | [r]
 71 | type = "R"
 72 | [r.repr]
 73 | default = "$name$ %rd%, %rs%, %rt%"
 74 | jr = "$name$ %rs%"
 75 | jalr = "$name$ %rd%, %rs%"
 76 | mfhi = "$name$ %rd%"
 77 | mthi = "$name$ %rd%"
 78 | mflo = "$name$ %rd%"
 79 | mtlo = "$name$ %rd%"
 80 | mfc0 = "$name$ %rd%"
 81 | [r.instructions]
 82 | sll = { mask = 0xfc00003f, match = 0x00 }
 83 | srl = { mask = 0xfc00003f, match = 0x02 }
 84 | sra = { mask = 0xfc00003f, match = 0x03 }
 85 | jr = { mask = 0xfc00003f, match = 0x08 }
 86 | jalr = { mask = 0xfc00003f, match = 0x09 }
 87 | mult = { mask = 0xfc00003f, match = 0x18 }
 88 | multu = { mask = 0xfc00003f, match = 0x19 }
 89 | add = { mask = 0xfc00003f, match = 0x20 }
 90 | addu = { mask = 0xfc00003f, match = 0x21 }
 91 | sub = { mask = 0xfc00003f, match = 0x22 }
 92 | subu = { mask = 0xfc00003f, match = 0x23 }
 93 | and = { mask = 0xfc00003f, match = 0x24 }
 94 | or = { mask = 0xfc00003f, match = 0x25 }
 95 | xor = { mask = 0xfc00003f, match = 0x26 }
 96 | nor = { mask = 0xfc00003f, match = 0x27 }
 97 | div = { mask = 0xfc00003f, match = 0x1a }
 98 | divu = { mask = 0xfc00003f, match = 0x1b }
 99 | slt = { mask = 0xfc00003f, match = 0x2a }
100 | sltu = { mask = 0xfc00003f, match = 0x2b }
101 | 
102 | [i]
103 | type = "I"
104 | [i.repr]
105 | default = "$name$ %rt%, %rs%, %imm%"
106 | [i.instructions]
107 | addi = { mask = 0xfc000000, match = 0x20000000 }
108 | addiu = { mask = 0xfc000000, match = 0x24000000 }
109 | andi = { mask = 0xfc000000, match = 0x30000000 }
110 | ori = { mask = 0xfc000000, match = 0x34000000 }
111 | slti = { mask = 0xfc000000, match = 0x28000000 }
112 | sltiu = { mask = 0xfc000000, match = 0x2c000000 }
113 | 
114 | 
115 | [branch]
116 | type = "I"
117 | [branch.repr]
118 | default = "$name$ %rs%, %rt%"
119 | [branch.instructions]
120 | beq = { mask = 0xfc00000000, match = 0x10000000 }
121 | bne = { mask = 0xfc00000000, match = 0x14000000 }
122 | blez = { mask = 0xfc00000000, match = 0x18000000 }
123 | bgtz = { mask = 0xfc00000000, match = 0x1c000000 }
124 | 
125 | [mem]
126 | type = "I"
127 | [mem.repr]
128 | default = "$name$ %rt%, %imm%(%rs%)"
129 | [mem.instructions]
130 | lb = { mask = 0xfc000000, match = 0x80000000 }
131 | lw = { mask = 0xfc000000, match = 0x8c000000 }
132 | lbu = { mask = 0xfc000000, match = 0x90000000 }
133 | lhu = { mask = 0xfc000000, match = 0x94000000 }
134 | sb = { mask = 0xfc000000, match = 0xa0000000 }
135 | sh = { mask = 0xfc000000, match = 0xa4000000 }
136 | sw = { mask = 0xfc000000, match = 0xac000000 }
137 | 
138 | [j]
139 | type = "J"
140 | [j.repr]
141 | default = "$name$ %addr%"
142 | [j.instructions]
143 | j = { mask = 0xfc000000, match = 0x08000000 }
144 | jal = { mask = 0xfc000000, match = 0x0c000000 }
145 | 
146 | [mappings]
147 | names = ["Register_int"]
148 | number = 32
149 | Register_int = [
150 |     "$zero",
151 |     "$at",
152 |     "$v0",
153 |     "$v1",
154 |     "$a0",
155 |     "$a1",
156 |     "$a2",
157 |     "$a3",
158 |     "$t0",
159 |     "$t1",
160 |     "$t2",
161 |     "$t3",
162 |     "$t4",
163 |     "$t5",
164 |     "$t6",
165 |     "$t7",
166 |     "$s0",
167 |     "$s1",
168 |     "$s2",
169 |     "$s3",
170 |     "$s4",
171 |     "$s5",
172 |     "$s6",
173 |     "$s7",
174 |     "$t8",
175 |     "$t9",
176 |     "$k0",
177 |     "$k1",
178 |     "$gp",
179 |     "$sp",
180 |     "$fp",
181 |     "$ra",
182 | ]
183 | 


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/toml/subleq.toml:
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 1 | set = "SUBLEQ"
 2 | width = 16
 3 | 
 4 | [formats]
 5 | names = ["subleq"]
 6 | parts = [
 7 |     [
 8 |         "opcode",
 9 |         1,
10 |         "u8",
11 |     ],
12 |     [
13 |         "r1",
14 |         5,
15 |         "Register",
16 |     ],
17 |     [
18 |         "r2",
19 |         5,
20 |         "Register",
21 |     ],
22 |     [
23 |         "jump",
24 |         8,
25 |         "i8",
26 |     ],
27 | ]
28 | 
29 | [types]
30 | names = ["SUBLEQ"]
31 | SUBLEQ = [
32 |     { name = "r1", top = 3, bot = 0 },
33 |     { name = "r2", top = 3, bot = 0 },
34 |     { name = "jump", top = 7, bot = 0 },
35 | ]
36 | 
37 | [subleq]
38 | type = "SUBLEQ"
39 | [subleq.repr]
40 | default = "%r1% %r2% %jump%"
41 | [subleq.instructions]
42 | subleq = { mask = 0, match = 0 }
43 | 
44 | [register]
45 | names = ["Register"]
46 | number = 16
47 | Register = [
48 |     "TMP0",
49 |     "PC",
50 |     "SRC1",
51 |     "TMP1",
52 |     "RSLT",
53 |     "TMP2",
54 |     "TMP3",
55 |     "TMP4",
56 |     "IMM",
57 |     "TMP5",
58 |     "ONE",
59 |     "WORD",
60 |     "INC",
61 |     "NEXT",
62 |     "TWP",
63 |     "TMP7",
64 | ]
65 | 


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/tomlspec.md:
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 1 | # Creating a valid TOML file
 2 | 
 3 | required entries:
 4 | - `set` type `string`, the name of the Instruction Set, currently unused
 5 | - `width` type `integer`, the width of an instruction defined by the set, in bits, used by the decoder to filter which set to search for a valid instruction in
 6 | - `formats` type `map`
 7 |   - `names` type `list`, list of all different output format names that are contained in the file, given as `string`
 8 |   - `parts` type `list`, list of all parts that may appear in a type. Each part is a `list` itself, with the entries, the last marked as optional: name, bitwidth, type[, format]
 9 |     - name is a `string`
10 |     - bitwidth is an `integer`
11 |     - type is a `string` and can be `"boolean", "char", "i8", "i16", "i32", "i64", "u8", "u16", "u32", "u64", "isize", "usize", "f32", "f64"` or the slightly special type `"VInt"`, which is an unsigned or signed number of 128 bit size, depending on an argument in the instructions section later on
12 |     All other type names are also accepted (as long as they do not contain the reserved character `.`), but are treated as custom Mappings that must be defined in the toml itself
13 |     - the optional value of format is of type `string` and can be any of the following: `"", "decimal", "dec", "d", "10"` for decoding as a base 10 number, `"hexadecimal", "hex", "h", "x", "0x", "16"` for decoding as a base 16 number, `"Octal", "oct", "o", "0o", "8"` for decoding as a base 8 number and `"Binary", "bin", "b", "0b", "2"` for decoding as a base 2 number. Since `""` is included in base 10, leaving out the format value implies base 10
14 | - `types` type `map`
15 |   - `names` type `list`, list of all different type names that are contained in the file, given as `string`
16 |   - `<name>` of type `list`, one exists for each type named in `type.names` with `<name>` being replaced with the value from the list
17 |   The parts are also listed in the exact order they appear in the instruction type that is to be decoded, from MSB to LSB
18 |   Each entry in the list is of type `map` with the following values:
19 |     - `name` name of the part (type `string`), corresponding to the name from the `types.parts` list
20 |     - `top` top bit index of the part (type `integer`) that is being mapped onto the instruction
21 |     - `bot` bottom bit index of the part (type `integer`) that is being mapped onto the instruction
22 |     - [`extend_top`] optional, type `integer`, value for how many extra bits the top bit should be extended for, absence implies 0
23 | - `mappings`type `map`
24 |   - `names` type `list`, a list of strings which define all custom mappings in the file
25 |   - `<name>`of type `list` or `map` (where all keys need to be numbers, either in decimal format or in number prefix form, eg 0x10)
26 |   If the type is `list`, then the index of the element is used for the mapping, and if an index that would be out of range were to appear, it would cause an error
27 |   If the type is `map`, then the key would be used for mapping, and if the key does not exist, it will not cause an error, but instead just print out the unmapped value
28 | 
29 | - `<format-name>` type `map`, one for every entry in the format names list
30 |   - `type` type `string`, corresponds to the type used to parse the instruction, which will directly impact what parts are available to use for the format
31 |   - `instructions`type `map`
32 |     - `<name-of-instruction>` type `map`, one for every instruction hat should be represented by the format
33 |       - `mask` the value that is applied to an incoming instruction via an AND operation
34 |       - `match` the value that the incoming instruction & mask should be, if the incoming instruction should be decoded as this one
35 |       - [`unsigned`] type `boolean`, True if all `VInt` parts in the type should be decoded as unsigned. If the entry is missing, it implies False, and thus all `VInt` will be signed
36 |   - `repr` type `map` 
37 |     - `default` for representing the default formatting
38 |       - the format string works in the way, that it replaces certain parts of the string, i.e. `%<name_of_part>%` with the corresponding decoded value of the part in the type, as well as `$name$` with the name of the instruction
39 |     - `<name-of-instruction>` for overriding the formatting for single instructions


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