├── .gitignore ├── Source ├── ipcore_dir │ ├── image2.ncf │ ├── chip_scope.ncf │ ├── image_mem.ncf │ ├── map_sprites.ncf │ ├── chip_scope_2.ncf │ ├── ghost_sprites.ncf │ ├── map_mem_read.ncf │ ├── map_sprite_mem.ncf │ ├── map_temp_store.ncf │ ├── movement_sprites.ncf │ ├── score_sprites.ncf │ ├── chip_scope_icon_core.ncf │ ├── map_collision_detect.ncf │ ├── xaw2verilog.log │ ├── image2_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── image_mem_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── ghost_sprites_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── map_mem_read_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── map_sprites_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── score_sprites_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── map_sprite_mem_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── map_temp_store_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── quad_pump_flist.txt │ ├── blk_mem_gen_v6_2_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── movement_sprites_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── quad_pump_2_flist.txt │ ├── double_pump_2_flist.txt │ ├── map_collision_detect_ste │ │ └── implement │ │ │ ├── xst.prj │ │ │ ├── xst.scr │ │ │ └── implement.sh │ ├── coregen.cgp │ ├── chip_scope_flist.txt │ ├── chip_scope_icon_core.asy │ ├── chip_scope_2_flist.txt │ ├── tmp │ │ └── _xmsgs │ │ │ ├── ngcbuild.xmsgs │ │ │ └── pn_parser.xmsgs │ ├── image2.asy │ ├── image_mem.asy │ ├── map_sprites.asy │ ├── score_sprites.asy │ ├── blk_mem_gen_v6_2.asy │ ├── chip_scope_2.asy │ ├── chip_scope_icon_core_flist.txt │ ├── chip_scope.asy │ ├── summary.log │ ├── map_mem_read.asy │ ├── ghost_sprites.asy │ ├── map_sprite_mem.asy │ ├── quad_pump_arwz.ucf │ ├── movement_sprites.asy │ ├── double_pump_2_arwz.ucf │ ├── image2_flist.txt │ ├── map_collision_detect.asy │ ├── image_mem_flist.txt │ ├── _xmsgs │ │ ├── pn_parser.xmsgs │ │ └── cg.xmsgs │ ├── map_sprites_flist.txt │ ├── map_mem_read_flist.txt │ ├── ghost_sprites_flist.txt │ ├── map_temp_store_flist.txt │ ├── score_sprites_flist.txt │ ├── map_sprite_mem_flist.txt │ ├── chip_scope_icon_core.sym │ ├── blk_mem_gen_v6_2_flist.txt │ ├── movement_sprites_flist.txt │ ├── chip_scope_icon_core.v │ ├── chip_scope_2.v │ ├── chip_scope.v │ ├── image2.sym │ ├── map_collision_detect_flist.txt │ ├── image_mem.sym │ ├── map_sprites.sym │ ├── score_sprites.sym │ ├── blk_mem_gen_v6_2.sym │ ├── map_temp_store.asy │ ├── chip_scope_2.sym │ ├── chip_scope_icon_core.veo │ ├── edit_chip_scope.tcl │ ├── edit_image_mem.tcl │ ├── edit_chip_scope_2.tcl │ ├── edit_map_mem_read.tcl │ ├── edit_map_sprites.tcl │ ├── gen_image2.tcl │ ├── edit_map_sprite_mem.tcl │ ├── edit_map_temp_store.tcl │ ├── chip_scope_2.veo │ ├── edit_movement_sprites.tcl │ ├── edit_chip_scope_icon_core.tcl │ ├── edit_map_collision_detect.tcl │ ├── gen_ghost_sprites.tcl │ ├── gen_map_mem_read.tcl │ ├── gen_map_sprite_mem.tcl │ ├── update_map_sprite_mem.tcl │ ├── gen_movement_sprites.tcl │ ├── chip_scope.veo │ ├── gen_map_collision_detect.tcl │ ├── quad_pump_2_arwz.ucf │ ├── chip_scope.sym │ ├── create_quad_pump.tcl │ ├── create_double_pump_2.tcl │ ├── create_image.tcl │ ├── create_image2.tcl │ ├── create_image_mem.tcl │ ├── create_score_map.tcl │ ├── create_map_mem_read.tcl │ ├── create_map_sprites.tcl │ ├── create_ghost_sprites.tcl │ ├── create_map_sprite_mem.tcl │ ├── create_map_temp_store.tcl │ ├── create_score_sprites.tcl │ ├── create_map_state.tcl │ ├── create_movement_sprites.tcl │ ├── create_quad_pump_2.tcl │ ├── create_map_collision_detect.tcl │ ├── create_chip_scope.tcl │ ├── create_chip_scope_2.tcl │ ├── chip_scope.gise │ ├── chip_scope_2.gise │ ├── create_chip_scope_icon_core.tcl │ ├── chip_scope_icon_core.gise │ ├── image2.gise │ ├── image_mem.gise │ ├── map_sprites.gise │ ├── map_mem_read.gise │ ├── ghost_sprites.gise │ ├── score_sprites.gise │ ├── map_sprite_mem.gise │ ├── map_temp_store.gise │ ├── blk_mem_gen_v6_2.gise │ ├── movement_sprites.gise │ ├── map_collision_detect.gise │ ├── chip_scope_icon_core.xco │ ├── ghost_sprites.sym │ ├── map_mem_read.sym │ ├── map_sprite_mem.sym │ ├── movement_sprites.sym │ ├── map_collision_detect.sym │ ├── chip_scope.xco │ ├── chip_scope_2.xco │ └── chip_scope_2.cdc ├── coe_files │ ├── pacman_full_motion_sprites │ │ ├── Thumbs.db │ │ ├── pac_man_down_wide.coe │ │ ├── pac_man_left_wide.coe │ │ ├── pac_man_right_wide.coe │ │ ├── pac_man_sprites.coe │ │ ├── pac_man_up_narrow.coe │ │ ├── pac_man_up_wide.coe │ │ ├── pac_man_down_narrow.coe │ │ ├── pac_man_left_narrow.coe │ │ └── pac_man_right_narrow.coe │ ├── pac_man_sprites_bak.txt │ ├── three_plane_to_hex.py │ ├── map_sprites_tmp │ │ ├── three_plane_to_hex.py │ │ └── map.coe │ ├── map_to_collision_detect.py │ ├── map_collision_detect.coe │ ├── map.coe │ └── in_use │ │ └── map.coe ├── map_controller_beh.prj ├── top_bitgen.xwbt ├── impact_impact.xwbt ├── fuseRelaunch.cmd ├── fuse.xmsgs ├── clock_divider.v ├── layer_compositor.v ├── _xmsgs │ └── pn_parser.xmsgs ├── grid_controller.v ├── quad_pump_arwz.ucf ├── double_pump_2_arwz.ucf ├── clock_manager.v ├── t_keyboard_buffer.v ├── quad_pump_2_arwz.ucf ├── impact.xsl ├── map_collision_detect.mif ├── pacman_death.v ├── background_effects.v ├── Project.gise ├── vga_controller_640_60.v ├── keyboard_buffer.v ├── score_bcd_converter.v ├── ps2key.v ├── t_map_controller.v └── sin_lut.v └── bitstream_file_for_xc3s1200.bit /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image2.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image_mem.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprites.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_2.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/ghost_sprites.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_mem_read.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprite_mem.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_temp_store.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/movement_sprites.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/score_sprites.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_icon_core.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_collision_detect.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /Source/ipcore_dir/xaw2verilog.log: -------------------------------------------------------------------------------- 1 | xaw2verilog: Completed successfully 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image2_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/image2_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image_mem_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/image_mem_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/ghost_sprites_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/ghost_sprites_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_mem_read_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/map_mem_read_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprites_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/map_sprites_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/score_sprites_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/score_sprites_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprite_mem_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/map_sprite_mem_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_temp_store_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/map_temp_store_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/quad_pump_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | quad_pump_flist.txt 3 | -------------------------------------------------------------------------------- /Source/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/blk_mem_gen_v6_2_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/movement_sprites_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/movement_sprites_top.vhd 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/quad_pump_2_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | quad_pump_2_flist.txt 3 | -------------------------------------------------------------------------------- /Source/ipcore_dir/double_pump_2_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | double_pump_2_flist.txt 3 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_collision_detect_ste/implement/xst.prj: -------------------------------------------------------------------------------- 1 | work ../example_design/map_collision_detect_top.vhd 2 | -------------------------------------------------------------------------------- /bitstream_file_for_xc3s1200.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idanw/Verilog-Pac-Man/HEAD/bitstream_file_for_xc3s1200.bit -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/Thumbs.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idanw/Verilog-Pac-Man/HEAD/Source/coe_files/pacman_full_motion_sprites/Thumbs.db -------------------------------------------------------------------------------- /Source/map_controller_beh.prj: -------------------------------------------------------------------------------- 1 | verilog work "quad_pump.v" 2 | verilog work "ipcore_dir/map_mem_read.v" 3 | verilog work "map_controller.v" 4 | verilog work "C:/Xilinx/13.2/ISE_DS/ISE//verilog/src/glbl.v" 5 | -------------------------------------------------------------------------------- /Source/top_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=C:\temp\Idan\Project\top.ncd 3 | OUTFILE=C:\temp\Idan\Project\top.bit 4 | FAMILY=Spartan3 5 | PART=xc3s1000-5ft256 6 | WORKINGDIR=C:\temp\Idan\Project 7 | LICENSE=ISE 8 | USER_INFO=__174135685_174135686_174419191 9 | -------------------------------------------------------------------------------- /Source/impact_impact.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=impact 2 | INFILE=X:\Desktop\EC551\Project\Project\impact.xsl 3 | OUTFILE=X:\Desktop\EC551\Project\Project\impact.xsl 4 | FAMILY=Multiple 5 | PART=Multiple 6 | WORKINGDIR=X:\Desktop\EC551\Project\Project 7 | LICENSE=iMPACT 8 | USER_INFO=iMPACT 9 | -------------------------------------------------------------------------------- /Source/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "X:/Desktop/EC551/Project/Project/t_collision_detect_isim_beh.exe" -prj "X:/Desktop/EC551/Project/Project/t_collision_detect_beh.prj" "work.t_collision_detect" "work.glbl" 2 | -------------------------------------------------------------------------------- /Source/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = Verilog 3 | SET device = xc3s1000 4 | SET devicefamily = spartan3 5 | SET flowvendor = Other 6 | SET package = ft256 7 | SET speedgrade = -5 8 | SET verilogsim = true 9 | SET vhdlsim = false 10 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image2_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent image2_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn image2_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image_mem_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent image_mem_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn image_mem_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprites_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent map_sprites_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn map_sprites_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_mem_read_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent map_mem_read_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn map_mem_read_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/ghost_sprites_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent ghost_sprites_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn ghost_sprites_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprite_mem_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent map_sprite_mem_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn map_sprite_mem_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_temp_store_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent map_temp_store_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn map_temp_store_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/score_sprites_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent score_sprites_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn score_sprites_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/blk_mem_gen_v6_2_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent blk_mem_gen_v6_2_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn blk_mem_gen_v6_2_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/movement_sprites_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent movement_sprites_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn movement_sprites_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_collision_detect_ste/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt VHDL 3 | -ent map_collision_detect_top 4 | -p xc3s1000-ft256-5 5 | -ifn xst.prj 6 | -write_timing_constraints No 7 | -iobuf YES 8 | -max_fanout 100 9 | -ofn map_collision_detect_top 10 | -ofmt NGC 11 | -bus_delimiter () 12 | -hierarchy_separator / 13 | -case Maintain 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | chip_scope.asy 4 | chip_scope.cdc 5 | chip_scope.gise 6 | chip_scope.ngc 7 | chip_scope.sym 8 | chip_scope.v 9 | chip_scope.veo 10 | chip_scope.xco 11 | chip_scope.xise 12 | chip_scope_flist.txt 13 | chip_scope_readme.txt 14 | chip_scope_xmdf.tcl 15 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_icon_core.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 chip_scope_icon_core 4 | RECTANGLE Normal 32 32 544 864 5 | LINE Wide 576 112 544 112 6 | PIN 576 112 RIGHT 36 7 | PINATTR PinName control0[35:0] 8 | PINATTR Polarity BOTH 9 | LINE Wide 576 144 544 144 10 | PIN 576 144 RIGHT 36 11 | PINATTR PinName control1[35:0] 12 | PINATTR Polarity BOTH 13 | 14 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_2_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | chip_scope_2.asy 4 | chip_scope_2.cdc 5 | chip_scope_2.gise 6 | chip_scope_2.ngc 7 | chip_scope_2.sym 8 | chip_scope_2.v 9 | chip_scope_2.veo 10 | chip_scope_2.xco 11 | chip_scope_2.xise 12 | chip_scope_2_flist.txt 13 | chip_scope_2_readme.txt 14 | chip_scope_2_xmdf.tcl 15 | -------------------------------------------------------------------------------- /Source/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Source/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image2.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 image2 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[7:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 576 80 544 80 14 | PIN 576 80 RIGHT 36 15 | PINATTR PinName douta[383:0] 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image_mem.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 image_mem 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[6:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 576 80 544 80 14 | PIN 576 80 RIGHT 36 15 | PINATTR PinName douta[383:0] 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprites.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 map_sprites 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[7:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 576 80 544 80 14 | PIN 576 80 RIGHT 36 15 | PINATTR PinName douta[63:0] 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /Source/ipcore_dir/score_sprites.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 score_sprites 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[7:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 576 80 544 80 14 | PIN 576 80 RIGHT 36 15 | PINATTR PinName douta[15:0] 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /Source/ipcore_dir/blk_mem_gen_v6_2.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 blk_mem_gen_v6_2 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[7:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 576 80 544 80 14 | PIN 576 80 RIGHT 36 15 | PINATTR PinName douta[383:0] 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /Source/coe_files/pac_man_sprites_bak.txt: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000033333300000, 4 | 0000333333330000, 5 | 0033333333333300, 6 | 0033333333333300, 7 | 0333333333333330, 8 | 3333333333333330, 9 | 3333333333333333, 10 | 3333333333333333, 11 | 3333333333333333, 12 | 3333333333333333, 13 | 3333333333333330, 14 | 0333333333333330, 15 | 0033333333333300, 16 | 0033333333333300, 17 | 0000333333330000, 18 | 0000003333000000; -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_2.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 chip_scope_2 4 | RECTANGLE Normal 32 32 320 224 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName control[35:0] 8 | PINATTR Polarity BOTH 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName async_in[18:0] 12 | PINATTR Polarity IN 13 | LINE Wide 352 80 320 80 14 | PIN 352 80 RIGHT 36 15 | PINATTR PinName async_out[32:0] 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_icon_core_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | chip_scope_icon_core.asy 4 | chip_scope_icon_core.gise 5 | chip_scope_icon_core.ngc 6 | chip_scope_icon_core.sym 7 | chip_scope_icon_core.v 8 | chip_scope_icon_core.veo 9 | chip_scope_icon_core.xco 10 | chip_scope_icon_core.xise 11 | chip_scope_icon_core_flist.txt 12 | chip_scope_icon_core_readme.txt 13 | chip_scope_icon_core_xmdf.tcl 14 | -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/pac_man_down_wide.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000033333300000, 4 | 0000333333330000, 5 | 0033333333333300, 6 | 0033333333333300, 7 | 0333333333333330, 8 | 3333333333333330, 9 | 3333333003333333, 10 | 3333330000333333, 11 | 3333300000033333, 12 | 3333000000003333, 13 | 0330000000000330, 14 | 0000000000000000, 15 | 0000000000000000, 16 | 0000000000000000, 17 | 0000000000000000, 18 | 0000000000000000; -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/pac_man_left_wide.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000033333300000, 4 | 0000333333330000, 5 | 0000033333333300, 6 | 0000003333333300, 7 | 0000000333333330, 8 | 0000000033333330, 9 | 0000000003333333, 10 | 0000000000333333, 11 | 0000000000333333, 12 | 0000000003333333, 13 | 0000000033333330, 14 | 0000000333333330, 15 | 0000003333333300, 16 | 0000033333333300, 17 | 0000333333330000, 18 | 0000003333000000; -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/pac_man_right_wide.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000033333300000, 4 | 0000333333330000, 5 | 0033333333300000, 6 | 0033333333000000, 7 | 0333333330000000, 8 | 3333333300000000, 9 | 3333333000000000, 10 | 3333330000000000, 11 | 3333330000000000, 12 | 3333333000000000, 13 | 3333333300000000, 14 | 0333333330000000, 15 | 0033333333000000, 16 | 0033333333300000, 17 | 0000333333330000, 18 | 0000003333000000; -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/pac_man_sprites.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000033333300000, 4 | 0000333333330000, 5 | 0033333333333300, 6 | 0033333333333300, 7 | 0333333333333330, 8 | 3333333333333330, 9 | 3333333333333333, 10 | 3333333333333333, 11 | 3333333333333333, 12 | 3333333333333333, 13 | 3333333333333330, 14 | 0333333333333330, 15 | 0033333333333300, 16 | 0033333333333300, 17 | 0000333333330000, 18 | 0000003333000000; -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/pac_man_up_narrow.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000000000000000, 4 | 0000000000000000, 5 | 0003300000033000, 6 | 0033300000033300, 7 | 0333330000333330, 8 | 3333330000333330, 9 | 3333330000333333, 10 | 3333333003333333, 11 | 3333333003333333, 12 | 3333333003333333, 13 | 3333333333333330, 14 | 0333333333333330, 15 | 0033333333333300, 16 | 0033333333333300, 17 | 0000333333330000, 18 | 0000003333000000; -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/pac_man_up_wide.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000000000000000, 4 | 0000000000000000, 5 | 0000000000000000, 6 | 0000000000000000, 7 | 0000000000000000, 8 | 0330000000000330, 9 | 3333000000003333, 10 | 3333300000033333, 11 | 3333330000333333, 12 | 3333333003333333, 13 | 3333333333333330, 14 | 0333333333333330, 15 | 0033333333333300, 16 | 0033333333333300, 17 | 0000333333330000, 18 | 0000003333000000; -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/pac_man_down_narrow.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000033333300000, 4 | 0000333333330000, 5 | 0033333333333300, 6 | 0033333333333300, 7 | 0333333333333330, 8 | 3333333333333330, 9 | 3333333003333333, 10 | 3333333003333333, 11 | 3333333003333333, 12 | 3333330000333333, 13 | 3333330000333330, 14 | 0333330000333330, 15 | 0033300000033300, 16 | 0003300000033000, 17 | 0000000000000000, 18 | 0000000000000000; -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/pac_man_left_narrow.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000033333300000, 4 | 0000333333330000, 5 | 0003333333333300, 6 | 0033333333333300, 7 | 0033333333333330, 8 | 0000333333333330, 9 | 0000000333333333, 10 | 0000000000333333, 11 | 0000000000333333, 12 | 0000000333333333, 13 | 0000333333333330, 14 | 0033333333333330, 15 | 0033333333333300, 16 | 0003333333333300, 17 | 0000333333330000, 18 | 0000003333000000; -------------------------------------------------------------------------------- /Source/coe_files/pacman_full_motion_sprites/pac_man_right_narrow.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 0000033333300000, 4 | 0000333333330000, 5 | 0033333333333000, 6 | 0033333333333300, 7 | 0333333333333300, 8 | 3333333333330000, 9 | 3333333330000000, 10 | 3333330000000000, 11 | 3333330000000000, 12 | 3333333330000000, 13 | 3333333333330000, 14 | 0333333333333300, 15 | 0033333333333300, 16 | 0033333333333000, 17 | 0000333333330000, 18 | 0000003333000000; -------------------------------------------------------------------------------- /Source/clock_divider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | * File Primary Author: Idan Warsawski 4 | * See LICENSE for license information 5 | */ 6 | 7 | module clock_divider(out, out8x, clk); 8 | output out, out8x; 9 | input clk; 10 | reg out, out8x; 11 | reg [20:0] counter; 12 | 13 | 14 | always @(posedge clk) begin 15 | if(counter == 21'b1_1111_1111_1111_1111_1111) out <= ~out; 16 | if(counter[17:0] == 18'b11_1111_1111_1111_1111) out8x <= ~out8x; 17 | counter <= counter + 1; 18 | end 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 chip_scope 4 | RECTANGLE Normal 32 32 320 224 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName control[35:0] 8 | PINATTR Polarity BOTH 9 | LINE Wide 0 144 32 144 10 | PIN 0 144 LEFT 36 11 | PINATTR PinName sync_in[63:0] 12 | PINATTR Polarity IN 13 | LINE Normal 0 176 32 176 14 | PIN 0 176 LEFT 36 15 | PINATTR PinName clk 16 | PINATTR Polarity IN 17 | LINE Wide 352 112 320 112 18 | PIN 352 112 RIGHT 36 19 | PINATTR PinName sync_out[63:0] 20 | PINATTR Polarity OUT 21 | 22 | -------------------------------------------------------------------------------- /Source/layer_compositor.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module layer_compositor(screenout, blank, scoreval, mazeval, movingval, backval); 4 | input [2:0] mazeval, movingval, scoreval, backval; 5 | input blank; 6 | output [2:0] screenout; 7 | reg [2:0] screenout; 8 | 9 | always begin 10 | if (blank) 11 | screenout = 3'b000; 12 | else if (scoreval != 3'b000) 13 | screenout = scoreval; 14 | else if(movingval != 3'b000) 15 | screenout = movingval; 16 | else if(mazeval != 3'b000) 17 | screenout = mazeval; 18 | else 19 | screenout = backval; 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /Source/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Source/ipcore_dir/summary.log: -------------------------------------------------------------------------------- 1 | 2 | User Configuration 3 | ------------------------------------- 4 | Algorithm : Minimum_Area 5 | Memory Type : Single_Port_ROM 6 | Port A Read Width : 384 7 | Memory Depth : 256 8 | -------------------------------------------------------------- 9 | 10 | Block RAM resource(s) (18K BRAMs) : 6 11 | -------------------------------------------------------------- 12 | Clock A Frequency : 100 13 | Port A Enable Rate : 100 14 | Port A Write Rate : 0 15 | ---------------------------------------------------------- 16 | Estimated Power for IP : 54.699051 mW 17 | ---------------------------------------------------------- 18 | -------------------------------------------------------------------------------- /Source/grid_controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:44:27 11/01/2011 7 | // Design Name: 8 | // Module Name: grid_controller 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module grid_controller(pixel_clk, HS, VS, hcounter, vcounter, blank); 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /Source/quad_pump_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_INST CLK_FEEDBACK = 1X; 5 | INST DCM_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_INST CLKFX_DIVIDE = 1; 7 | INST DCM_INST CLKFX_MULTIPLY = 4; 8 | INST DCM_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_INST CLKIN_PERIOD = 20.000; 10 | INST DCM_INST CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_INST FACTORY_JF = 8080; 16 | INST DCM_INST PHASE_SHIFT = 0; 17 | INST DCM_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /Source/double_pump_2_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_INST CLK_FEEDBACK = 1X; 5 | INST DCM_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_INST CLKFX_DIVIDE = 1; 7 | INST DCM_INST CLKFX_MULTIPLY = 4; 8 | INST DCM_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_INST CLKIN_PERIOD = 20.000; 10 | INST DCM_INST CLKOUT_PHASE_SHIFT = FIXED; 11 | INST DCM_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_INST FACTORY_JF = 8080; 16 | INST DCM_INST PHASE_SHIFT = 32; 17 | INST DCM_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_mem_read.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 map_mem_read 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[7:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 0 432 32 432 14 | PIN 0 432 LEFT 36 15 | PINATTR PinName addrb[7:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 624 32 624 18 | PIN 0 624 LEFT 36 19 | PINATTR PinName clkb 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[75:0] 24 | PINATTR Polarity OUT 25 | LINE Wide 576 368 544 368 26 | PIN 576 368 RIGHT 36 27 | PINATTR PinName doutb[75:0] 28 | PINATTR Polarity OUT 29 | 30 | -------------------------------------------------------------------------------- /Source/ipcore_dir/ghost_sprites.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 ghost_sprites 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[7:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 0 432 32 432 14 | PIN 0 432 LEFT 36 15 | PINATTR PinName addrb[7:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 624 32 624 18 | PIN 0 624 LEFT 36 19 | PINATTR PinName clkb 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[63:0] 24 | PINATTR Polarity OUT 25 | LINE Wide 576 368 544 368 26 | PIN 576 368 RIGHT 36 27 | PINATTR PinName doutb[63:0] 28 | PINATTR Polarity OUT 29 | 30 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprite_mem.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 map_sprite_mem 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[7:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 0 432 32 432 14 | PIN 0 432 LEFT 36 15 | PINATTR PinName addrb[7:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 624 32 624 18 | PIN 0 624 LEFT 36 19 | PINATTR PinName clkb 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[63:0] 24 | PINATTR Polarity OUT 25 | LINE Wide 576 368 544 368 26 | PIN 576 368 RIGHT 36 27 | PINATTR PinName doutb[63:0] 28 | PINATTR Polarity OUT 29 | 30 | -------------------------------------------------------------------------------- /Source/ipcore_dir/quad_pump_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_INST CLK_FEEDBACK = 1X; 5 | INST DCM_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_INST CLKFX_DIVIDE = 1; 7 | INST DCM_INST CLKFX_MULTIPLY = 4; 8 | INST DCM_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_INST CLKIN_PERIOD = 20.000; 10 | INST DCM_INST CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_INST FACTORY_JF = 8080; 16 | INST DCM_INST PHASE_SHIFT = 0; 17 | INST DCM_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /Source/ipcore_dir/movement_sprites.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 movement_sprites 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[7:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 0 432 32 432 14 | PIN 0 432 LEFT 36 15 | PINATTR PinName addrb[7:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 624 32 624 18 | PIN 0 624 LEFT 36 19 | PINATTR PinName clkb 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[63:0] 24 | PINATTR Polarity OUT 25 | LINE Wide 576 368 544 368 26 | PIN 576 368 RIGHT 36 27 | PINATTR PinName doutb[63:0] 28 | PINATTR Polarity OUT 29 | 30 | -------------------------------------------------------------------------------- /Source/ipcore_dir/double_pump_2_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_INST CLK_FEEDBACK = 1X; 5 | INST DCM_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_INST CLKFX_DIVIDE = 1; 7 | INST DCM_INST CLKFX_MULTIPLY = 4; 8 | INST DCM_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_INST CLKIN_PERIOD = 20.000; 10 | INST DCM_INST CLKOUT_PHASE_SHIFT = FIXED; 11 | INST DCM_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_INST FACTORY_JF = 8080; 16 | INST DCM_INST PHASE_SHIFT = 64; 17 | INST DCM_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image2_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | image2.asy 6 | image2.gise 7 | image2.mif 8 | image2.ngc 9 | image2.sym 10 | image2.v 11 | image2.veo 12 | image2.xco 13 | image2.xise 14 | image2_flist.txt 15 | image2_ste\example_design\bmg_wrapper.vhd 16 | image2_ste\example_design\image2_top.ucf 17 | image2_ste\example_design\image2_top.vhd 18 | image2_ste\example_design\image2_top.xdc 19 | image2_ste\implement\implement.sh 20 | image2_ste\implement\planAhead_rdn.bat 21 | image2_ste\implement\planAhead_rdn.sh 22 | image2_ste\implement\planAhead_rdn.tcl 23 | image2_ste\implement\xst.prj 24 | image2_ste\implement\xst.scr 25 | image2_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_collision_detect.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 map_collision_detect 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[6:0] 8 | PINATTR Polarity IN 9 | LINE Normal 0 272 32 272 10 | PIN 0 272 LEFT 36 11 | PINATTR PinName clka 12 | PINATTR Polarity IN 13 | LINE Wide 0 432 32 432 14 | PIN 0 432 LEFT 36 15 | PINATTR PinName addrb[6:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 624 32 624 18 | PIN 0 624 LEFT 36 19 | PINATTR PinName clkb 20 | PINATTR Polarity IN 21 | LINE Wide 576 80 544 80 22 | PIN 576 80 RIGHT 36 23 | PINATTR PinName douta[75:0] 24 | PINATTR Polarity OUT 25 | LINE Wide 576 368 544 368 26 | PIN 576 368 RIGHT 36 27 | PINATTR PinName doutb[75:0] 28 | PINATTR Polarity OUT 29 | 30 | -------------------------------------------------------------------------------- /Source/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file \"C:/temp/Idan/Project/ipcore_dir/image2.v\" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image_mem_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | image_mem.asy 6 | image_mem.gise 7 | image_mem.mif 8 | image_mem.ngc 9 | image_mem.sym 10 | image_mem.v 11 | image_mem.veo 12 | image_mem.xco 13 | image_mem.xise 14 | image_mem_flist.txt 15 | image_mem_ste\example_design\bmg_wrapper.vhd 16 | image_mem_ste\example_design\image_mem_top.ucf 17 | image_mem_ste\example_design\image_mem_top.vhd 18 | image_mem_ste\example_design\image_mem_top.xdc 19 | image_mem_ste\implement\implement.sh 20 | image_mem_ste\implement\planAhead_rdn.bat 21 | image_mem_ste\implement\planAhead_rdn.sh 22 | image_mem_ste\implement\planAhead_rdn.tcl 23 | image_mem_ste\implement\xst.prj 24 | image_mem_ste\implement\xst.scr 25 | image_mem_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file "C:/Users/idan/Desktop/Project_to_github/Project_to_github/Source/ipcore_dir/image2.v" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprites_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | map_sprites.asy 6 | map_sprites.gise 7 | map_sprites.mif 8 | map_sprites.ngc 9 | map_sprites.sym 10 | map_sprites.v 11 | map_sprites.veo 12 | map_sprites.xco 13 | map_sprites.xise 14 | map_sprites_flist.txt 15 | map_sprites_ste\example_design\bmg_wrapper.vhd 16 | map_sprites_ste\example_design\map_sprites_top.ucf 17 | map_sprites_ste\example_design\map_sprites_top.vhd 18 | map_sprites_ste\example_design\map_sprites_top.xdc 19 | map_sprites_ste\implement\implement.sh 20 | map_sprites_ste\implement\planAhead_rdn.bat 21 | map_sprites_ste\implement\planAhead_rdn.sh 22 | map_sprites_ste\implement\planAhead_rdn.tcl 23 | map_sprites_ste\implement\xst.prj 24 | map_sprites_ste\implement\xst.scr 25 | map_sprites_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_mem_read_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | map_mem_read.asy 6 | map_mem_read.gise 7 | map_mem_read.mif 8 | map_mem_read.ngc 9 | map_mem_read.sym 10 | map_mem_read.v 11 | map_mem_read.veo 12 | map_mem_read.xco 13 | map_mem_read.xise 14 | map_mem_read_flist.txt 15 | map_mem_read_ste\example_design\bmg_wrapper.vhd 16 | map_mem_read_ste\example_design\map_mem_read_top.ucf 17 | map_mem_read_ste\example_design\map_mem_read_top.vhd 18 | map_mem_read_ste\example_design\map_mem_read_top.xdc 19 | map_mem_read_ste\implement\implement.sh 20 | map_mem_read_ste\implement\planAhead_rdn.bat 21 | map_mem_read_ste\implement\planAhead_rdn.sh 22 | map_mem_read_ste\implement\planAhead_rdn.tcl 23 | map_mem_read_ste\implement\xst.prj 24 | map_mem_read_ste\implement\xst.scr 25 | map_mem_read_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/ghost_sprites_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | ghost_sprites.asy 6 | ghost_sprites.gise 7 | ghost_sprites.mif 8 | ghost_sprites.ngc 9 | ghost_sprites.sym 10 | ghost_sprites.v 11 | ghost_sprites.veo 12 | ghost_sprites.xco 13 | ghost_sprites.xise 14 | ghost_sprites_flist.txt 15 | ghost_sprites_ste\example_design\bmg_wrapper.vhd 16 | ghost_sprites_ste\example_design\ghost_sprites_top.ucf 17 | ghost_sprites_ste\example_design\ghost_sprites_top.vhd 18 | ghost_sprites_ste\example_design\ghost_sprites_top.xdc 19 | ghost_sprites_ste\implement\implement.sh 20 | ghost_sprites_ste\implement\planAhead_rdn.bat 21 | ghost_sprites_ste\implement\planAhead_rdn.sh 22 | ghost_sprites_ste\implement\planAhead_rdn.tcl 23 | ghost_sprites_ste\implement\xst.prj 24 | ghost_sprites_ste\implement\xst.scr 25 | ghost_sprites_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_temp_store_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | map_temp_store.asy 6 | map_temp_store.gise 7 | map_temp_store.ngc 8 | map_temp_store.sym 9 | map_temp_store.v 10 | map_temp_store.veo 11 | map_temp_store.xco 12 | map_temp_store.xise 13 | map_temp_store_flist.txt 14 | map_temp_store_ste\example_design\bmg_wrapper.vhd 15 | map_temp_store_ste\example_design\map_temp_store_top.ucf 16 | map_temp_store_ste\example_design\map_temp_store_top.vhd 17 | map_temp_store_ste\example_design\map_temp_store_top.xdc 18 | map_temp_store_ste\implement\implement.sh 19 | map_temp_store_ste\implement\planAhead_rdn.bat 20 | map_temp_store_ste\implement\planAhead_rdn.sh 21 | map_temp_store_ste\implement\planAhead_rdn.tcl 22 | map_temp_store_ste\implement\xst.prj 23 | map_temp_store_ste\implement\xst.scr 24 | map_temp_store_xmdf.tcl 25 | summary.log 26 | -------------------------------------------------------------------------------- /Source/ipcore_dir/score_sprites_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | score_sprites.asy 6 | score_sprites.gise 7 | score_sprites.mif 8 | score_sprites.ngc 9 | score_sprites.sym 10 | score_sprites.v 11 | score_sprites.veo 12 | score_sprites.xco 13 | score_sprites.xise 14 | score_sprites_flist.txt 15 | score_sprites_ste\example_design\bmg_wrapper.vhd 16 | score_sprites_ste\example_design\score_sprites_top.ucf 17 | score_sprites_ste\example_design\score_sprites_top.vhd 18 | score_sprites_ste\example_design\score_sprites_top.xdc 19 | score_sprites_ste\implement\implement.sh 20 | score_sprites_ste\implement\planAhead_rdn.bat 21 | score_sprites_ste\implement\planAhead_rdn.sh 22 | score_sprites_ste\implement\planAhead_rdn.tcl 23 | score_sprites_ste\implement\xst.prj 24 | score_sprites_ste\implement\xst.scr 25 | score_sprites_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprite_mem_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | map_sprite_mem.asy 6 | map_sprite_mem.gise 7 | map_sprite_mem.mif 8 | map_sprite_mem.ngc 9 | map_sprite_mem.sym 10 | map_sprite_mem.v 11 | map_sprite_mem.veo 12 | map_sprite_mem.xco 13 | map_sprite_mem.xise 14 | map_sprite_mem_flist.txt 15 | map_sprite_mem_ste\example_design\bmg_wrapper.vhd 16 | map_sprite_mem_ste\example_design\map_sprite_mem_top.ucf 17 | map_sprite_mem_ste\example_design\map_sprite_mem_top.vhd 18 | map_sprite_mem_ste\example_design\map_sprite_mem_top.xdc 19 | map_sprite_mem_ste\implement\implement.sh 20 | map_sprite_mem_ste\implement\planAhead_rdn.bat 21 | map_sprite_mem_ste\implement\planAhead_rdn.sh 22 | map_sprite_mem_ste\implement\planAhead_rdn.tcl 23 | map_sprite_mem_ste\implement\xst.prj 24 | map_sprite_mem_ste\implement\xst.scr 25 | map_sprite_mem_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_icon_core.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-5T22:17:45 5 | 6 | 7 | 8 | chip_scope_icon_core 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Source/ipcore_dir/blk_mem_gen_v6_2_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2.asy 5 | blk_mem_gen_v6_2.gise 6 | blk_mem_gen_v6_2.mif 7 | blk_mem_gen_v6_2.ngc 8 | blk_mem_gen_v6_2.sym 9 | blk_mem_gen_v6_2.v 10 | blk_mem_gen_v6_2.veo 11 | blk_mem_gen_v6_2.xco 12 | blk_mem_gen_v6_2.xise 13 | blk_mem_gen_v6_2_flist.txt 14 | blk_mem_gen_v6_2_readme.txt 15 | blk_mem_gen_v6_2_ste\example_design\blk_mem_gen_v6_2_top.ucf 16 | blk_mem_gen_v6_2_ste\example_design\blk_mem_gen_v6_2_top.vhd 17 | blk_mem_gen_v6_2_ste\example_design\blk_mem_gen_v6_2_top.xdc 18 | blk_mem_gen_v6_2_ste\example_design\bmg_wrapper.vhd 19 | blk_mem_gen_v6_2_ste\implement\implement.sh 20 | blk_mem_gen_v6_2_ste\implement\planAhead_rdn.bat 21 | blk_mem_gen_v6_2_ste\implement\planAhead_rdn.sh 22 | blk_mem_gen_v6_2_ste\implement\planAhead_rdn.tcl 23 | blk_mem_gen_v6_2_ste\implement\xst.prj 24 | blk_mem_gen_v6_2_ste\implement\xst.scr 25 | blk_mem_gen_v6_2_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/movement_sprites_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | movement_sprites.asy 6 | movement_sprites.gise 7 | movement_sprites.mif 8 | movement_sprites.ngc 9 | movement_sprites.sym 10 | movement_sprites.v 11 | movement_sprites.veo 12 | movement_sprites.xco 13 | movement_sprites.xise 14 | movement_sprites_flist.txt 15 | movement_sprites_ste\example_design\bmg_wrapper.vhd 16 | movement_sprites_ste\example_design\movement_sprites_top.ucf 17 | movement_sprites_ste\example_design\movement_sprites_top.vhd 18 | movement_sprites_ste\example_design\movement_sprites_top.xdc 19 | movement_sprites_ste\implement\implement.sh 20 | movement_sprites_ste\implement\planAhead_rdn.bat 21 | movement_sprites_ste\implement\planAhead_rdn.sh 22 | movement_sprites_ste\implement\planAhead_rdn.tcl 23 | movement_sprites_ste\implement\xst.prj 24 | movement_sprites_ste\implement\xst.scr 25 | movement_sprites_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_icon_core.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011 Xilinx, Inc. 3 | // All Rights Reserved 4 | /////////////////////////////////////////////////////////////////////////////// 5 | // ____ ____ 6 | // / /\/ / 7 | // /___/ \ / Vendor : Xilinx 8 | // \ \ \/ Version : 13.2 9 | // \ \ Application: Xilinx CORE Generator 10 | // / / Filename : chip_scope_icon_core.v 11 | // /___/ /\ Timestamp : Mon Dec 05 17:17:33 Eastern Standard Time 2011 12 | // \ \ / \ 13 | // \___\/\___\ 14 | // 15 | // Design Name: Verilog Synthesis Wrapper 16 | /////////////////////////////////////////////////////////////////////////////// 17 | // This wrapper is used to integrate with Project Navigator and PlanAhead 18 | 19 | `timescale 1ns/1ps 20 | 21 | module chip_scope_icon_core( 22 | CONTROL0, 23 | CONTROL1); 24 | 25 | 26 | inout [35 : 0] CONTROL0; 27 | inout [35 : 0] CONTROL1; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_2.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011 Xilinx, Inc. 3 | // All Rights Reserved 4 | /////////////////////////////////////////////////////////////////////////////// 5 | // ____ ____ 6 | // / /\/ / 7 | // /___/ \ / Vendor : Xilinx 8 | // \ \ \/ Version : 13.2 9 | // \ \ Application: Xilinx CORE Generator 10 | // / / Filename : chip_scope_2.v 11 | // /___/ /\ Timestamp : Tue Dec 13 20:18:42 Eastern Standard Time 2011 12 | // \ \ / \ 13 | // \___\/\___\ 14 | // 15 | // Design Name: Verilog Synthesis Wrapper 16 | /////////////////////////////////////////////////////////////////////////////// 17 | // This wrapper is used to integrate with Project Navigator and PlanAhead 18 | 19 | `timescale 1ns/1ps 20 | 21 | module chip_scope_2( 22 | CONTROL, 23 | ASYNC_IN, 24 | ASYNC_OUT); 25 | 26 | 27 | inout [35 : 0] CONTROL; 28 | input [18 : 0] ASYNC_IN; 29 | output [32 : 0] ASYNC_OUT; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011 Xilinx, Inc. 3 | // All Rights Reserved 4 | /////////////////////////////////////////////////////////////////////////////// 5 | // ____ ____ 6 | // / /\/ / 7 | // /___/ \ / Vendor : Xilinx 8 | // \ \ \/ Version : 13.2 9 | // \ \ Application: Xilinx CORE Generator 10 | // / / Filename : chip_scope.v 11 | // /___/ /\ Timestamp : Sat Dec 03 15:58:19 Eastern Standard Time 2011 12 | // \ \ / \ 13 | // \___\/\___\ 14 | // 15 | // Design Name: Verilog Synthesis Wrapper 16 | /////////////////////////////////////////////////////////////////////////////// 17 | // This wrapper is used to integrate with Project Navigator and PlanAhead 18 | 19 | `timescale 1ns/1ps 20 | 21 | module chip_scope( 22 | CONTROL, 23 | CLK, 24 | SYNC_IN, 25 | SYNC_OUT); 26 | 27 | 28 | inout [35 : 0] CONTROL; 29 | input CLK; 30 | input [63 : 0] SYNC_IN; 31 | output [63 : 0] SYNC_OUT; 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /Source/clock_manager.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | * File Primary Author: Idan Warsawski 4 | * See LICENSE for license information 5 | */ 6 | 7 | module clock_manager(clk_100mhz, clk_100mhz_phase, clk_25mhz, clk_6hz, clk_24hz, clk_50mhz, reset); 8 | output clk_100mhz; 9 | output [1:0] clk_100mhz_phase; 10 | output clk_25mhz; 11 | output clk_6hz; 12 | output clk_24hz; 13 | 14 | input clk_50mhz; 15 | input reset; 16 | 17 | wire clk_100mhz, clk_6hz, clk_24hz; 18 | 19 | reg clk_25mhz; 20 | reg [1:0] clk_100mhz_phase; 21 | 22 | quad_pump dp1 ( 23 | .CLKIN_IN(clk_50mhz), 24 | .RST_IN(1'b0), 25 | //.CLK0_OUT(CLK0_OUT), 26 | .CLK2X_OUT(clk_100mhz) 27 | //.CLK2X180_OUT(clk_100mhz_180), 28 | //.LOCKED_OUT(LOCKED_OUT) 29 | ); 30 | 31 | always @(posedge clk_50mhz) begin 32 | clk_25mhz <= ~clk_25mhz; 33 | end 34 | 35 | always @(posedge clk_100mhz) begin 36 | if(clk_25mhz & clk_50mhz) begin 37 | clk_100mhz_phase <= 2'b01; 38 | end else begin 39 | clk_100mhz_phase <= clk_100mhz_phase + 1; 40 | end 41 | end 42 | 43 | clock_divider slow_clk(clk_6hz, clk_24hz, clk_50mhz); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image2.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-15T20:58:53 5 | 6 | 7 | 8 | 9 | image2 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /Source/coe_files/three_plane_to_hex.py: -------------------------------------------------------------------------------- 1 | f = open("map_sprite_blue.coe", "r") 2 | lines = f.readlines() 3 | 4 | blue = [] 5 | 6 | for line in lines: 7 | if(len(line) == 18): 8 | if(line[16] == ','): 9 | blue.append(line[0:16]) 10 | f.close() 11 | f = open("map_sprite_red.coe", "r") 12 | lines = f.readlines() 13 | 14 | red = [] 15 | 16 | for line in lines: 17 | if(len(line) == 18): 18 | if(line[16] == ','): 19 | red.append(line[0:16]) 20 | f.close() 21 | f = open("map_sprite_green.coe", "r") 22 | lines = f.readlines() 23 | 24 | green = [] 25 | 26 | for line in lines: 27 | if(len(line) == 18): 28 | if(line[16] == ','): 29 | green.append(line[0:16]) 30 | f.close() 31 | output_lines = [] 32 | for i in range(0, len(red)): 33 | asdf = [] 34 | for j in range(0,16): 35 | asdf.append("%x" % ((int(red[i][j]) << 2) + (int(green[i][j]) << 1) + int(blue[i][j]))) 36 | output_lines.append(''.join(asdf) + ',\n') 37 | 38 | f = open("map_sprite_combined_hex.coe", "w") 39 | f.writelines(output_lines) 40 | f.flush() 41 | f.close() 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_collision_detect_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs\pn_parser.xmsgs 3 | blk_mem_gen_ds512.pdf 4 | blk_mem_gen_v6_2_readme.txt 5 | map_collision_detect.asy 6 | map_collision_detect.gise 7 | map_collision_detect.mif 8 | map_collision_detect.ngc 9 | map_collision_detect.sym 10 | map_collision_detect.v 11 | map_collision_detect.veo 12 | map_collision_detect.xco 13 | map_collision_detect.xise 14 | map_collision_detect_flist.txt 15 | map_collision_detect_ste\example_design\bmg_wrapper.vhd 16 | map_collision_detect_ste\example_design\map_collision_detect_top.ucf 17 | map_collision_detect_ste\example_design\map_collision_detect_top.vhd 18 | map_collision_detect_ste\example_design\map_collision_detect_top.xdc 19 | map_collision_detect_ste\implement\implement.sh 20 | map_collision_detect_ste\implement\planAhead_rdn.bat 21 | map_collision_detect_ste\implement\planAhead_rdn.sh 22 | map_collision_detect_ste\implement\planAhead_rdn.tcl 23 | map_collision_detect_ste\implement\xst.prj 24 | map_collision_detect_ste\implement\xst.scr 25 | map_collision_detect_xmdf.tcl 26 | summary.log 27 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image_mem.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-15T19:43:15 5 | 6 | 7 | 8 | 9 | image_mem 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprites.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-7T23:31:36 5 | 6 | 7 | 8 | 9 | map_sprites 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /Source/coe_files/map_sprites_tmp/three_plane_to_hex.py: -------------------------------------------------------------------------------- 1 | f = open("map_sprite_blue.coe", "r") 2 | lines = f.readlines() 3 | 4 | blue = [] 5 | 6 | for line in lines: 7 | if(len(line) == 18): 8 | if(line[16] == ','): 9 | blue.append(line[0:16]) 10 | f.close() 11 | f = open("map_sprite_red.coe", "r") 12 | lines = f.readlines() 13 | 14 | red = [] 15 | 16 | for line in lines: 17 | if(len(line) == 18): 18 | if(line[16] == ','): 19 | red.append(line[0:16]) 20 | f.close() 21 | f = open("map_sprite_green.coe", "r") 22 | lines = f.readlines() 23 | 24 | green = [] 25 | 26 | for line in lines: 27 | if(len(line) == 18): 28 | if(line[16] == ','): 29 | green.append(line[0:16]) 30 | f.close() 31 | output_lines = [] 32 | for i in range(0, len(red)): 33 | asdf = [] 34 | for j in range(0,16): 35 | asdf.append("%x" % ((int(red[i][j]) << 2) + (int(green[i][j]) << 1) + int(blue[i][j]))) 36 | output_lines.append(''.join(asdf) + ',\n') 37 | 38 | f = open("map_sprite_combined_hex.coe", "w") 39 | f.writelines(output_lines) 40 | f.flush() 41 | f.close() 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/score_sprites.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-5T22:34:28 5 | 6 | 7 | 8 | 9 | score_sprites 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /Source/ipcore_dir/blk_mem_gen_v6_2.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-15T20:42:8 5 | 6 | 7 | 8 | 9 | blk_mem_gen_v6_2 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_temp_store.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 map_temp_store 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[4:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[18:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[0:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 0 432 32 432 22 | PIN 0 432 LEFT 36 23 | PINATTR PinName addrb[4:0] 24 | PINATTR Polarity IN 25 | LINE Wide 0 464 32 464 26 | PIN 0 464 LEFT 36 27 | PINATTR PinName dinb[18:0] 28 | PINATTR Polarity IN 29 | LINE Wide 0 560 32 560 30 | PIN 0 560 LEFT 36 31 | PINATTR PinName web[0:0] 32 | PINATTR Polarity IN 33 | LINE Normal 0 624 32 624 34 | PIN 0 624 LEFT 36 35 | PINATTR PinName clkb 36 | PINATTR Polarity IN 37 | LINE Wide 576 80 544 80 38 | PIN 576 80 RIGHT 36 39 | PINATTR PinName douta[18:0] 40 | PINATTR Polarity OUT 41 | LINE Wide 576 368 544 368 42 | PIN 576 368 RIGHT 36 43 | PINATTR PinName doutb[18:0] 44 | PINATTR Polarity OUT 45 | 46 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_2.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-14T1:18:54 5 | 6 | 7 | 8 | 9 | chip_scope_2 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_icon_core.veo: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011 Xilinx, Inc. 3 | // All Rights Reserved 4 | /////////////////////////////////////////////////////////////////////////////// 5 | // ____ ____ 6 | // / /\/ / 7 | // /___/ \ / Vendor : Xilinx 8 | // \ \ \/ Version : 13.2 9 | // \ \ Application: Xilinx CORE Generator 10 | // / / Filename : chip_scope_icon_core.veo 11 | // /___/ /\ Timestamp : Mon Dec 05 17:17:33 Eastern Standard Time 2011 12 | // \ \ / \ 13 | // \___\/\___\ 14 | // 15 | // Design Name: ISE Instantiation template 16 | /////////////////////////////////////////////////////////////////////////////// 17 | 18 | // The following must be inserted into your Verilog file for this 19 | // core to be instantiated. Change the instance name and port connections 20 | // (in parentheses) to your own signal names. 21 | 22 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 23 | chip_scope_icon_core YourInstanceName ( 24 | .CONTROL0(CONTROL0), // INOUT BUS [35:0] 25 | .CONTROL1(CONTROL1) // INOUT BUS [35:0] 26 | ); 27 | 28 | // INST_TAG_END ------ End INSTANTIATION Template --------- 29 | 30 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image2_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp image2_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../image2.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/image2_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 image2_top 26 | 27 | echo 'Running map' 28 | map image2_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm image2_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_chip_scope.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "chip_scope" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_image_mem.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "image_mem" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_chip_scope_2.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "chip_scope_2" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_map_mem_read.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "map_mem_read" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_map_sprites.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "map_sprites" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/gen_image2.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator regen command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_regen "image2" xc3s1000-5ft256 Verilog CURRENT ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator regen command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator regen command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator regen cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_map_sprite_mem.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "map_sprite_mem" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_map_temp_store.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "map_temp_store" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_2.veo: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011 Xilinx, Inc. 3 | // All Rights Reserved 4 | /////////////////////////////////////////////////////////////////////////////// 5 | // ____ ____ 6 | // / /\/ / 7 | // /___/ \ / Vendor : Xilinx 8 | // \ \ \/ Version : 13.2 9 | // \ \ Application: Xilinx CORE Generator 10 | // / / Filename : chip_scope_2.veo 11 | // /___/ /\ Timestamp : Tue Dec 13 20:18:42 Eastern Standard Time 2011 12 | // \ \ / \ 13 | // \___\/\___\ 14 | // 15 | // Design Name: ISE Instantiation template 16 | /////////////////////////////////////////////////////////////////////////////// 17 | 18 | // The following must be inserted into your Verilog file for this 19 | // core to be instantiated. Change the instance name and port connections 20 | // (in parentheses) to your own signal names. 21 | 22 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 23 | chip_scope_2 YourInstanceName ( 24 | .CONTROL(CONTROL), // INOUT BUS [35:0] 25 | .ASYNC_IN(ASYNC_IN), // IN BUS [18:0] 26 | .ASYNC_OUT(ASYNC_OUT) // OUT BUS [32:0] 27 | ); 28 | 29 | // INST_TAG_END ------ End INSTANTIATION Template --------- 30 | 31 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_movement_sprites.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "movement_sprites" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image_mem_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp image_mem_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../image_mem.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/image_mem_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 image_mem_top 26 | 27 | echo 'Running map' 28 | map image_mem_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm image_mem_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_chip_scope_icon_core.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "chip_scope_icon_core" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/edit_map_collision_detect.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "map_collision_detect" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/gen_ghost_sprites.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator regen command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_regen "ghost_sprites" xc3s1000-5ft256 Verilog CURRENT ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator regen command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator regen command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator regen cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/gen_map_mem_read.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator regen command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_regen "map_mem_read" xc3s1000-5ft256 Verilog CURRENT ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator regen command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator regen command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator regen cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/gen_map_sprite_mem.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator regen command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_regen "map_sprite_mem" xc3s1000-5ft256 Verilog CURRENT ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator regen command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator regen command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator regen cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/update_map_sprite_mem.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator update command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_update "map_sprite_mem" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator update command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator update command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator update cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/gen_movement_sprites.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator regen command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_regen "movement_sprites" xc3s1000-5ft256 Verilog CURRENT ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator regen command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator regen command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator regen cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope.veo: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2011 Xilinx, Inc. 3 | // All Rights Reserved 4 | /////////////////////////////////////////////////////////////////////////////// 5 | // ____ ____ 6 | // / /\/ / 7 | // /___/ \ / Vendor : Xilinx 8 | // \ \ \/ Version : 13.2 9 | // \ \ Application: Xilinx CORE Generator 10 | // / / Filename : chip_scope.veo 11 | // /___/ /\ Timestamp : Sat Dec 03 15:58:19 Eastern Standard Time 2011 12 | // \ \ / \ 13 | // \___\/\___\ 14 | // 15 | // Design Name: ISE Instantiation template 16 | /////////////////////////////////////////////////////////////////////////////// 17 | 18 | // The following must be inserted into your Verilog file for this 19 | // core to be instantiated. Change the instance name and port connections 20 | // (in parentheses) to your own signal names. 21 | 22 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 23 | chip_scope YourInstanceName ( 24 | .CONTROL(CONTROL), // INOUT BUS [35:0] 25 | .CLK(CLK), // IN 26 | .SYNC_IN(SYNC_IN), // IN BUS [63:0] 27 | .SYNC_OUT(SYNC_OUT) // OUT BUS [63:0] 28 | ); 29 | 30 | // INST_TAG_END ------ End INSTANTIATION Template --------- 31 | 32 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprites_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp map_sprites_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../map_sprites.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/map_sprites_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 map_sprites_top 26 | 27 | echo 'Running map' 28 | map map_sprites_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm map_sprites_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/gen_map_collision_detect.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator regen command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_regen "map_collision_detect" xc3s1000-5ft256 Verilog CURRENT ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator regen command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator regen command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator regen cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_mem_read_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp map_mem_read_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../map_mem_read.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/map_mem_read_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 map_mem_read_top 26 | 27 | echo 'Running map' 28 | map map_mem_read_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm map_mem_read_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/ghost_sprites_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp ghost_sprites_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../ghost_sprites.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/ghost_sprites_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 ghost_sprites_top 26 | 27 | echo 'Running map' 28 | map ghost_sprites_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm ghost_sprites_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/score_sprites_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp score_sprites_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../score_sprites.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/score_sprites_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 score_sprites_top 26 | 27 | echo 'Running map' 28 | map score_sprites_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm score_sprites_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprite_mem_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp map_sprite_mem_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../map_sprite_mem.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/map_sprite_mem_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 map_sprite_mem_top 26 | 27 | echo 'Running map' 28 | map map_sprite_mem_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm map_sprite_mem_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_temp_store_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp map_temp_store_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../map_temp_store.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/map_temp_store_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 map_temp_store_top 26 | 27 | echo 'Running map' 28 | map map_temp_store_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm map_temp_store_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/blk_mem_gen_v6_2_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp blk_mem_gen_v6_2_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../blk_mem_gen_v6_2.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/blk_mem_gen_v6_2_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 blk_mem_gen_v6_2_top 26 | 27 | echo 'Running map' 28 | map blk_mem_gen_v6_2_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm blk_mem_gen_v6_2_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/ipcore_dir/movement_sprites_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp movement_sprites_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../movement_sprites.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/movement_sprites_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 movement_sprites_top 26 | 27 | echo 'Running map' 28 | map movement_sprites_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm movement_sprites_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/t_keyboard_buffer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 22:26:43 11/01/2011 8 | // Design Name: keyboard_buffer 9 | // Module Name: X:/Desktop/EC551/Lab3/Lab3/t_keyboard_buffer.v 10 | // Project Name: Lab3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: keyboard_buffer 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module t_keyboard_buffer; 26 | 27 | // Inputs 28 | reg ps2d; 29 | reg ps2c; 30 | reg clk_50mhz; 31 | reg reset; 32 | 33 | // Outputs 34 | wire [7:0] key_out; 35 | 36 | // Instantiate the Unit Under Test (UUT) 37 | keyboard_buffer uut ( 38 | .key_out(key_out), 39 | .ps2d(ps2d), 40 | .ps2c(ps2c), 41 | .clk_50mhz(clk_50mhz), 42 | .reset(reset) 43 | ); 44 | 45 | initial begin 46 | // Initialize Inputs 47 | ps2d = 0; 48 | ps2c = 0; 49 | clk_50mhz = 0; 50 | reset = 0; 51 | 52 | // Wait 100 ns for global reset to finish 53 | #100; 54 | 55 | // Add stimulus here 56 | 57 | end 58 | 59 | endmodule 60 | 61 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_collision_detect_ste/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Clean up the results directory 4 | rm -rf results 5 | mkdir results 6 | 7 | #Synthesize the Wrapper Files 8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; 9 | echo 'Synthesizing example design with XST'; 10 | xst -ifn xst.scr 11 | cp map_collision_detect_top.ngc ./results/ 12 | 13 | 14 | # Copy the netlist generated by Coregen 15 | echo 'Copying files from the netlist directory to the results directory' 16 | cp ../../map_collision_detect.ngc results/ 17 | 18 | # Copy the constraints files generated by Coregen 19 | echo 'Copying files from constraints directory to results directory' 20 | cp ../example_design/map_collision_detect_top.ucf results/ 21 | 22 | cd results 23 | 24 | echo 'Running ngdbuild' 25 | ngdbuild -p xc3s1000-ft256-5 map_collision_detect_top 26 | 27 | echo 'Running map' 28 | map map_collision_detect_top -o mapped.ncd -pr i 29 | 30 | echo 'Running par' 31 | par mapped.ncd routed.ncd 32 | 33 | echo 'Running trce' 34 | trce -e 10 routed.ncd mapped.pcf -o routed 35 | 36 | echo 'Running design through bitgen' 37 | bitgen -w routed 38 | 39 | echo 'Running netgen to create gate level Verilog model' 40 | netgen -ofmt verilog -sim -tm map_collision_detect_top -pcf mapped.pcf -w routed.ncd routed.v 41 | cp routed.sdf ../../production/timing/ 42 | -------------------------------------------------------------------------------- /Source/quad_pump_2_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_INST1 CLK_FEEDBACK = 2X; 5 | INST DCM_INST1 CLKDV_DIVIDE = 2.0; 6 | INST DCM_INST1 CLKFX_DIVIDE = 1; 7 | INST DCM_INST1 CLKFX_MULTIPLY = 4; 8 | INST DCM_INST1 CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_INST1 CLKIN_PERIOD = 20.000; 10 | INST DCM_INST1 CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_INST1 DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_INST1 DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_INST1 DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_INST1 DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_INST1 FACTORY_JF = 8080; 16 | INST DCM_INST1 PHASE_SHIFT = 0; 17 | INST DCM_INST1 STARTUP_WAIT = FALSE; 18 | INST DCM_INST2 CLK_FEEDBACK = 1X; 19 | INST DCM_INST2 CLKDV_DIVIDE = 2.0; 20 | INST DCM_INST2 CLKFX_DIVIDE = 1; 21 | INST DCM_INST2 CLKFX_MULTIPLY = 4; 22 | INST DCM_INST2 CLKIN_DIVIDE_BY_2 = FALSE; 23 | INST DCM_INST2 CLKIN_PERIOD = 10.000; 24 | INST DCM_INST2 CLKOUT_PHASE_SHIFT = NONE; 25 | INST DCM_INST2 DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 26 | INST DCM_INST2 DFS_FREQUENCY_MODE = LOW; 27 | INST DCM_INST2 DLL_FREQUENCY_MODE = LOW; 28 | INST DCM_INST2 DUTY_CYCLE_CORRECTION = TRUE; 29 | INST DCM_INST2 FACTORY_JF = 8080; 30 | INST DCM_INST2 PHASE_SHIFT = 0; 31 | INST DCM_INST2 STARTUP_WAIT = FALSE; 32 | -------------------------------------------------------------------------------- /Source/ipcore_dir/quad_pump_2_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_INST1 CLK_FEEDBACK = 2X; 5 | INST DCM_INST1 CLKDV_DIVIDE = 2.0; 6 | INST DCM_INST1 CLKFX_DIVIDE = 1; 7 | INST DCM_INST1 CLKFX_MULTIPLY = 4; 8 | INST DCM_INST1 CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_INST1 CLKIN_PERIOD = 20.000; 10 | INST DCM_INST1 CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_INST1 DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_INST1 DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_INST1 DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_INST1 DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_INST1 FACTORY_JF = 8080; 16 | INST DCM_INST1 PHASE_SHIFT = 0; 17 | INST DCM_INST1 STARTUP_WAIT = FALSE; 18 | INST DCM_INST2 CLK_FEEDBACK = 1X; 19 | INST DCM_INST2 CLKDV_DIVIDE = 2.0; 20 | INST DCM_INST2 CLKFX_DIVIDE = 1; 21 | INST DCM_INST2 CLKFX_MULTIPLY = 4; 22 | INST DCM_INST2 CLKIN_DIVIDE_BY_2 = FALSE; 23 | INST DCM_INST2 CLKIN_PERIOD = 10.000; 24 | INST DCM_INST2 CLKOUT_PHASE_SHIFT = NONE; 25 | INST DCM_INST2 DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 26 | INST DCM_INST2 DFS_FREQUENCY_MODE = LOW; 27 | INST DCM_INST2 DLL_FREQUENCY_MODE = LOW; 28 | INST DCM_INST2 DUTY_CYCLE_CORRECTION = TRUE; 29 | INST DCM_INST2 FACTORY_JF = 8080; 30 | INST DCM_INST2 PHASE_SHIFT = 0; 31 | INST DCM_INST2 STARTUP_WAIT = FALSE; 32 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-3T20:58:32 5 | 6 | 7 | 8 | 9 | 10 | chip_scope 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_quad_pump.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:dcm:13.1" "quad_pump" "Single DCM" "Single DCM (xilinx.com:ip:dcm:13.1) generated by Project Navigator" xc3s200-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_double_pump_2.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:dcm:13.1" "double_pump_2" "Single DCM" "Single DCM (xilinx.com:ip:dcm:13.1) generated by Project Navigator" xc3s200-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/_xmsgs/cg.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Generating component instance 'image2' of 'xilinx.com:ip:blk_mem_gen:6.2' from 'C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml'. 9 | 10 | 11 | A core named 'image2' already exists in the project. Output products for this core may be overwritten. 12 | 13 | 14 | Can't find 'Verilog' synthesis view; using general synthesis view 15 | 16 | 17 | Pre-processing HDL files for 'image2'... 18 | 19 | 20 | Finished FLIST file generation. 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_image.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "image" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_image2.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "image2" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_image_mem.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "image_mem" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_score_map.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "score_map" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_map_mem_read.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "map_mem_read" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s200-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_map_sprites.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "map_sprites" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_ghost_sprites.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "ghost_sprites" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_map_sprite_mem.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "map_sprite_mem" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_map_temp_store.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "map_temp_store" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_score_sprites.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "score_sprites" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_map_state.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:dist_mem_gen:6.2" "map_state" "Distributed Memory Generator" "Distributed Memory Generator (xilinx.com:ip:dist_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_movement_sprites.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "movement_sprites" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_quad_pump_2.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:dcmca:13.1" "quad_pump_2" "Cascading in Series with Two DCMs" "Cascading in Series with Two DCMs (xilinx.com:ip:dcmca:13.1) generated by Project Navigator" xc3s200-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_map_collision_detect.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "map_collision_detect" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_chip_scope.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:chipscope_vio:1.04.a" "chip_scope" "VIO (ChipScope Pro - Virtual Input/Output)" "VIO (ChipScope Pro - Virtual Input/Output) (xilinx.com:ip:chipscope_vio:1.04.a) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_chip_scope_2.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:chipscope_vio:1.04.a" "chip_scope_2" "VIO (ChipScope Pro - Virtual Input/Output)" "VIO (ChipScope Pro - Virtual Input/Output) (xilinx.com:ip:chipscope_vio:1.04.a) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_2.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /Source/coe_files/map_to_collision_detect.py: -------------------------------------------------------------------------------- 1 | map_raw = "3555555555555555551,6888868888888788887,6855868555558785587,6888888888888888887,6185835185835187837,2086824085824087820,8886888885888887888,3182448444448440831,6788888888888888867,6783558318318551867,6786888688878887867,6786868688878787867,2086868244408787820,8888868888888788888,3184444485844444831,6788888885888888867,6084448444448444827,6888888888888888887,6831835585855183187,6867868885888786787,6820868444448782087,6888888888888888887,2444444444444444440" 2 | 3 | lines = map_raw.split(',') 4 | 5 | coll_detect_map = [] 6 | valid_move_space = ['8'] 7 | 8 | num_lines = len(lines) 9 | for i in range(0, num_lines): 10 | tmp = []; 11 | line_len = len(lines[i]) 12 | for char_num in range(0, line_len): 13 | if lines[i][char_num] in valid_move_space: 14 | can_go_left = (lines[i][char_num - 1] in valid_move_space) 15 | can_go_right = (lines[i][(char_num + 1) % line_len] in valid_move_space) 16 | can_go_up = (lines[i - 1][char_num] in valid_move_space) 17 | can_go_down = (lines[(i + 1) % num_lines][char_num] in valid_move_space) 18 | code = int(can_go_down << 3) + int(can_go_up << 2) + int(can_go_right << 1) + can_go_left 19 | tmp.append("%x" % (code)) 20 | else: 21 | tmp.append("f") 22 | coll_detect_map.append(''.join(tmp)) 23 | 24 | -------------------------------------------------------------------------------- /Source/ipcore_dir/create_chip_scope_icon_core.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:chipscope_icon:1.05.a" "chip_scope_icon_core" "ICON (ChipScope Pro - Integrated Controller)" "ICON (ChipScope Pro - Integrated Controller) (xilinx.com:ip:chipscope_icon:1.05.a) generated by Project Navigator" xc3s1000-5ft256 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Source/coe_files/map_collision_detect.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | fffffffffffffffffff, 4 | fa339fa333339fa339f, 5 | fcffcfcfffffcfcffcf, 6 | f6b3f373b3b373f3b5f, 7 | ffcfcfffcfcfffcfcff, 8 | ffcfcfffcfcfffcfcff, 9 | 33df63b35f63b35fe33, 10 | ffcfffcfffffcfffcff, 11 | ffe333f33b33f333dff, 12 | ffcfffcffcffcfffcff, 13 | ffcfa3dfaf9fe39fcff, 14 | ffcfcfcf675fcfcfcff, 15 | ffcfcfcfffffcfcfcff, 16 | 33f35f63b3b35f63f33, 17 | ffcfffffcfcfffffcff, 18 | ffe333b35f63b333dff, 19 | ffcfffcfffffcfffcff, 20 | fa73b373b3b373b379f, 21 | fcffcfffcfcfffcffcf, 22 | fcffcfa35f639fcffcf, 23 | fcffcfcfffffcfcffcf, 24 | f63373733333737335f, 25 | fffffffffffffffffff, 26 | 27 | fffffffffffffffffff, 28 | fffffffffffffffffff, 29 | fffffffffffffffffff, 30 | fffffffffffffffffff, 31 | fffffffffffffffffff, 32 | fffffffffffffffffff, 33 | fffffffffffffffffff, 34 | fffffffffffffffffff, 35 | fffffffffffffffffff, 36 | 37 | fffffffffcfffffffff, 38 | fa39ffa3b7b39ffa39f, 39 | fcf63b5fcfcf6b35fcf, 40 | fcfffcffcfcffcfffcf, 41 | fcfa379fe3dfa739fcf, 42 | fcfcffcfcfcfcffcfcf, 43 | fe379fe35f63dfa73df, 44 | fcffcfcfffffcfcffcf, 45 | f69fcfe33b33dfcfa5f, 46 | ff63f35ffcff63f35ff, 47 | ffffcfffaf9fffcffff, 48 | 3b3b739f675fa37b3a3, 49 | fcfcffcfffffcffcfcf, 50 | fcfe3373b33379fcfcf, 51 | fcfcffffcffffcfcfcf, 52 | fe37339fe339fcfcfcf, 53 | fcffffcfcffcf6373df, 54 | fcffa3df69fcfffffcf, 55 | f6b3dfcffe3dffa3b5f, 56 | ffcfcfe3b5fe33dfcff, 57 | ffcfcfcfcffcffcfcff, 58 | 335f635f6b37335f633, 59 | fffffffffcfffffffff; -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_icon_core.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image2.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/ipcore_dir/image_mem.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprites.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_mem_read.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/ipcore_dir/ghost_sprites.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/ipcore_dir/score_sprites.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/coe_files/map.coe: -------------------------------------------------------------------------------- 1 | ; VG7 Memory M7p 2 | ; .COE file with hex coefficients 3 | ; Height: 254, Width: 254 4 | 5 | memory_initialization_radix=16; 6 | memory_initialization_vector= 7 | 3555555555555555551, 8 | 7888878888888788887, 9 | 7855878555558785587, 10 | 7888888888888888887, 11 | 7185835185835187837, 12 | 2087824085824087820, 13 | 8887888885888887888, 14 | 3182448444448440831, 15 | 7788888888888888877, 16 | 7783558318318551877, 17 | 7787888788878887877, 18 | 7787878788878787877, 19 | 2087878244408787820, 20 | 8888878888888788888, 21 | 3184444485844444831, 22 | 7788888885888888877, 23 | 7084448444448444827, 24 | 7888888888888888887, 25 | 7831835585855183187, 26 | 7877878885888787787, 27 | 7820878444448782087, 28 | 7888888888888888887, 29 | 2444444444444444440, 30 | 31 | fffffffffffffffffff, 32 | fffffffffffffffffff, 33 | fffffffffffffffffff, 34 | fffffffffffffffffff, 35 | fffffffffffffffffff, 36 | fffffffffffffffffff, 37 | fffffffffffffffffff, 38 | fffffffffffffffffff, 39 | fffffffffffffffffff, 40 | 41 | ;;M0P 42 | 3222222220222222221, 43 | 4fee65eeeeeee65eef4, 44 | 4e7eeee7e7e7eeee7e4, 45 | 4e429ea4e8e49ea24e4, 46 | 4e4eeee4eee4eeee4e4, 47 | 4e8ea148e7e8e39e8e4, 48 | 4eeee4eee4eee4eeee4, 49 | 4ea1e4ea2229e4e39e4, 50 | 4ee8e8eeeeeee8e8ee4, 51 | 41eeeee390a1eeeee34, 52 | 6229ea24000429ea225, 53 | 0eeeeee40004eeeeee0, 54 | 7e7ea9e62225ea1e7e4, 55 | 4e4eeeeeeeeeee8e4e4, 56 | 4e8ea221ea221e4e4e4, 57 | 4eeeeee4eeee4e8e8e4, 58 | 4e3229e4ea1e4eeeee4, 59 | 4e65eee4ee8e42229e4, 60 | 4eeee7e69eee65eeee4, 61 | 41e7e4eeee7eeee7e34, 62 | 65e4e8e7ea5ea9e4e65, 63 | 0ee4fee4eeeeeef4ee0, 64 | a222222220222222229; -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprite_mem.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_temp_store.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/ipcore_dir/blk_mem_gen_v6_2.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/ipcore_dir/movement_sprites.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/coe_files/in_use/map.coe: -------------------------------------------------------------------------------- 1 | ; VG9 Memory M9p 2 | ; .COE file wit3 3ex coefficients 3 | ; 3eig3t: 264, Widt3: 264 4 | 5 | memory_initialization_radix=16; 6 | memory_initialization_vector= 7 | 8 | 3222222222222222221, 9 | 4feee4eeeeeee4eeef4, 10 | 4ea9e8ea2229e8ea9e4, 11 | 4eeeeeeeeeeeeeeeee4, 12 | 41e7e321e7e321e7e34, 13 | 65e4e625e4e625e4e65, 14 | 00e4eeeee4eeeee4e00, 15 | 31e6290a22290a25e31, 16 | 44e0000000000000e44, 17 | 44e3290390a10a21e44, 18 | 44e4000400040004e44, 19 | 44e4070400040704e44, 20 | 65e8040622250408e65, 21 | 00e0040000000400e00, 22 | 31ea2229070a2229e31, 23 | 44eeeee00400eeeee44, 24 | 45ea29ea2229ea29e64, 25 | 4eeeeeeee0eeeeeeee4, 26 | 4e31e329e7ea21e31e4, 27 | 4e44e4eee4eee4e44e4, 28 | 4f65e8ea2229e8e65f4, 29 | 4eeeeeeeeeeeeeeeee4, 30 | 6222222222222222225, 31 | 32 | fffffffffffffffffff, 33 | fffffffffffffffffff, 34 | fffffffffffffffffff, 35 | fffffffffffffffffff, 36 | fffffffffffffffffff, 37 | fffffffffffffffffff, 38 | fffffffffffffffffff, 39 | fffffffffffffffffff, 40 | fffffffffffffffffff, 41 | 42 | ;;M0P 43 | 3222222220222222221, 44 | 4fee65eeeeeee65eef4, 45 | 4e7eeee7e7e7eeee7e4, 46 | 4e429ea4e8e49ea24e4, 47 | 4e4eeee4eee4eeee4e4, 48 | 4e8ea148e7e8e39e8e4, 49 | 4eeee4eee4eee4eeee4, 50 | 4ea1e4ea2229e4e39e4, 51 | 4ee8e8eeeeeee8e8ee4, 52 | 41eeeee390a1eeeee34, 53 | 6229ea24000429ea225, 54 | 0eeeeee40004eeeeee0, 55 | 7e7ea9e62225ea1e7e4, 56 | 4e4eeeeeeeeeee8e4e4, 57 | 4e8ea221ea221e4e4e4, 58 | 4eeeeee4eeee4e8e8e4, 59 | 4e3229e4ea1e4eeeee4, 60 | 4e65eee4ee8e42229e4, 61 | 4eeee7e69eee65eeee4, 62 | 41e7e4eeee7eeee7e34, 63 | 65e4e8e7ea5ea9e4e65, 64 | 0ee4fee4eeeeeef4ee0, 65 | a222222220222222229; -------------------------------------------------------------------------------- /Source/coe_files/map_sprites_tmp/map.coe: -------------------------------------------------------------------------------- 1 | ; VG9 Memory M9p 2 | ; .COE file wit3 3ex coefficients 3 | ; 3eig3t: 264, Widt3: 264 4 | 5 | memory_initialization_radix=16; 6 | memory_initialization_vector= 7 | 8 | 3222222222222222221, 9 | 4feee4eeeeeee4eeef4, 10 | 4ea9e8ea2229e8ea9e4, 11 | 4eeeeeeeeeeeeeeeee4, 12 | 41e7e321e7e321e7e34, 13 | 65e4e625e4e625e4e65, 14 | 00e4eeeee4eeeee4e00, 15 | 31e6290a22290a25e31, 16 | 44e0000000000000e44, 17 | 44e3290390a10a21e44, 18 | 44e4000400040004e44, 19 | 44e4070400040704e44, 20 | 65e8040622250408e65, 21 | 00e0040000000400e00, 22 | 31ea2229070a2229e31, 23 | 44eeeee00400eeeee44, 24 | 45ea29ea2229ea29e64, 25 | 4eeeeeeee0eeeeeeee4, 26 | 4e31e329e7ea21e31e4, 27 | 4e44e4eee4eee4e44e4, 28 | 4f65e8ea2229e8e65f4, 29 | 4eeeeeeeeeeeeeeeee4, 30 | 6222222222222222225, 31 | 32 | fffffffffffffffffff, 33 | fffffffffffffffffff, 34 | fffffffffffffffffff, 35 | fffffffffffffffffff, 36 | fffffffffffffffffff, 37 | fffffffffffffffffff, 38 | fffffffffffffffffff, 39 | fffffffffffffffffff, 40 | fffffffffffffffffff, 41 | 42 | ;;M0P 43 | 3222222220222222221, 44 | 4fee65eeeeeee65eef4, 45 | 4e7eeee7e7e7eeee7e4, 46 | 4e429ea4e8e49ea24e4, 47 | 4e4eeee4eee4eeee4e4, 48 | 4e8ea148e7e8e39e8e4, 49 | 4eeee4eee4eee4eeee4, 50 | 4ea1e4ea2229e4e39e4, 51 | 4ee8e8eeeeeee8e8ee4, 52 | 41eeeee390a1eeeee34, 53 | 6229ea24000429ea225, 54 | 0eeeeee40004eeeeee0, 55 | 7e7ea9e62225ea1e7e4, 56 | 4e4eeeeeeeeeee8e4e4, 57 | 4e8ea221ea221e4e4e4, 58 | 4eeeeee4eeee4e8e8e4, 59 | 4e3229e4ea1e4eeeee4, 60 | 4e65eee4ee8e42229e4, 61 | 4eeee7e69eee65eeee4, 62 | 41e7e4eeee7eeee7e34, 63 | 65e4e8e7ea5ea9e4e65, 64 | 0ee4fee4eeeeeef4ee0, 65 | a222222220222222229; -------------------------------------------------------------------------------- /Source/ipcore_dir/map_collision_detect.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Source/impact.xsl: -------------------------------------------------------------------------------- 1 | 4 | 5 | 6 | 7 | 8 | 9 | Current iMPACT Usage Statistics. 10 |

11 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 12 | 13 |

14 |

15 | This page displays the current iMPACT device usage statistics that will be sent to Xilinx using WebTalk. 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
49 | 50 | 51 | 52 | 53 | 56 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_icon_core.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Mon Dec 05 22:16:33 2011 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_icon:1.05.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc3s1000 26 | SET devicefamily = spartan3 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ft256 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -5 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.05.a 40 | # END Select 41 | # BEGIN Parameters 42 | CSET component_name=chip_scope_icon_core 43 | CSET enable_jtag_bufg=true 44 | CSET example_design=false 45 | CSET number_control_ports=2 46 | CSET use_ext_bscan=false 47 | CSET use_softbscan=false 48 | CSET use_unused_bscan=false 49 | CSET user_scan_chain=USER1 50 | # END Parameters 51 | GENERATE 52 | # CRC: 4f4f7e0f 53 | -------------------------------------------------------------------------------- /Source/map_collision_detect.mif: -------------------------------------------------------------------------------- 1 | 1111111111111111111111111111111111111111111111111111111111111111111111111111 2 | 1111101000110011100111111010001100110011001100111001111110100011001110011111 3 | 1111110011111111110011111100111111111111111111111100111111001111111111001111 4 | 1111011010110011111100110111001110110011101100110111001111110011101101011111 5 | 1111111111001111110011111111111111001111110011111111111111001111110011111111 6 | 1111111111001111110011111111111111001111110011111111111111001111110011111111 7 | 0011001111011111011000111011001101011111011000111011001101011111111000110011 8 | 1111111111001111111111111100111111111111111111111100111111111111110011111111 9 | 1111111111100011001100111111001100111011001100111111001100110011110111111111 10 | 1111111111001111111111111100111111111100111111111100111111111111110011111111 11 | 1111111111001111101000111101111110101111100111111110001110011111110011111111 12 | 1111111111001111110011111100111101100111010111111100111111001111110011111111 13 | 1111111111001111110011111100111111111111111111111100111111001111110011111111 14 | 0011001111110011010111110110001110110011101100110101111101100011111100110011 15 | 1111111111001111111111111111111111001111110011111111111111111111110011111111 16 | 1111111111100011001100111011001101011111011000111011001100110011110111111111 17 | 1111111111001111111111111100111111111111111111111100111111111111110011111111 18 | 1111101001110011101100110111001110110011101100110111001110110011011110011111 19 | 1111110011111111110011111111111111001111110011111111111111001111111111001111 20 | 1111110011111111110011111010001101011111011000111001111111001111111111001111 21 | 1111110011111111110011111100111111111111111111111100111111001111111111001111 22 | 1111011000110011011100110111001100110011001100110111001101110011001101011111 23 | 1111111111111111111111111111111111111111111111111111111111111111111111111111 24 | -------------------------------------------------------------------------------- /Source/pacman_death.v: -------------------------------------------------------------------------------- 1 | /* 2 | * File Primary Author: Derek Heyman 3 | * See LICENSE for license information 4 | */ 5 | 6 | module pacman_death( 7 | input reset, 8 | input animation_clk, 9 | input clk_50mhz, 10 | input [1:0] GhostMode, 11 | input [6:0] PacManPosition_x, 12 | input [6:0] PacManPosition_y, 13 | input [6:0] BlinkyPosition_x, 14 | input [6:0] BlinkyPosition_y, 15 | input [6:0] InkyPosition_x, 16 | input [6:0] InkyPosition_y, 17 | input [6:0] ClydePosition_x, 18 | input [6:0] ClydePosition_y, 19 | input [6:0] PinkyPosition_x, 20 | input [6:0] PinkyPosition_y, 21 | output reg [3:0] pacman_cur_dir, 22 | output reg PacManDead 23 | ); 24 | 25 | 26 | reg startsequence; 27 | reg [2:0] animation_counter; 28 | 29 | always @(posedge animation_clk) begin 30 | if(PacManDead == 1) begin 31 | 32 | case(animation_counter[1:0]) 33 | 2'b00: pacman_cur_dir <= 4'b0001; 34 | 2'b01: pacman_cur_dir <= 4'b0100; 35 | 2'b10: pacman_cur_dir <= 4'b0010; 36 | 2'b11: pacman_cur_dir <= 4'b1000; 37 | endcase 38 | animation_counter <= animation_counter + 1; 39 | end 40 | end 41 | 42 | always@ (posedge clk_50mhz) begin 43 | if(reset) begin 44 | PacManDead <= 0; 45 | end else begin 46 | // if ghosts are not BLUE and heading back to jail 47 | // check for collision with PacMan 48 | if(GhostMode != 2'b11) begin 49 | 50 | if((PacManPosition_x == BlinkyPosition_x && PacManPosition_y == BlinkyPosition_y) || 51 | (PacManPosition_x == InkyPosition_x && PacManPosition_y == InkyPosition_y) || 52 | (PacManPosition_x == PinkyPosition_x && PacManPosition_y == PinkyPosition_y) || 53 | (PacManPosition_x == ClydePosition_x && PacManPosition_y == ClydePosition_y)) 54 | PacManDead <= 1; 55 | 56 | end 57 | 58 | end 59 | end 60 | endmodule 61 | -------------------------------------------------------------------------------- /Source/background_effects.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /* 3 | * File Primary Author: Idan Warsawski 4 | * See LICENSE for license information 5 | */ 6 | 7 | module background_effects(pixel_color, x, y, enable_effect, clk, slow_clk); 8 | output [3:0] pixel_color; 9 | input [9:0] x; 10 | input [8:0] y; 11 | input [2:0] enable_effect; 12 | input clk, slow_clk; 13 | reg [2:0] pixel_color; 14 | 15 | wire [4:0] h_count_sin; 16 | 17 | reg [5:0] h_count_increment; 18 | reg [5:0] increment; 19 | 20 | 21 | wire [6:0] x_shift; 22 | 23 | assign x_shift = x[6:0] - 6'b10_0000; 24 | wire [383:0] image_mem_out; 25 | 26 | image2 image ( 27 | .clka(clk), // input clka 28 | .addra({enable_effect[2], y[6:0]}), // input [6 : 0] addra 29 | .douta(image_mem_out) // output [383 : 0] douta 30 | ); 31 | sin_lut sin_val(h_count_sin, h_count_increment); 32 | 33 | always @(posedge clk) begin 34 | 35 | if((y[8:4] < 8) & (x[9:4] > 33) & enable_effect[1]) begin 36 | pixel_color <= ({image_mem_out[{x_shift[6:0] ,2'b00}], //9-2 = 7 37 | image_mem_out[{x_shift[6:0] ,2'b01}], 38 | image_mem_out[{x_shift[6:0] ,2'b10}]}); 39 | end else begin 40 | if((y[8:4] == h_count_sin) & enable_effect[0]) begin 41 | if(h_count_sin[3:1] == 3'b000) begin 42 | pixel_color[0] <= 1; 43 | end else begin 44 | pixel_color[0] <= h_count_sin[3]; 45 | end 46 | 47 | pixel_color[1] <= h_count_sin[1]; 48 | pixel_color[2] <= h_count_sin[2]; 49 | 50 | end else begin 51 | pixel_color <= 3'b000; 52 | end 53 | 54 | 55 | if((increment + x[9:4]) < 40) 56 | h_count_increment <= increment + x[9:4]; 57 | else 58 | h_count_increment <= increment + x[9:4] - 40; 59 | end 60 | end 61 | 62 | always @(posedge slow_clk) begin 63 | if(increment == 39) increment <= 0; 64 | else increment <= increment + 1; 65 | end 66 | 67 | endmodule 68 | -------------------------------------------------------------------------------- /Source/ipcore_dir/ghost_sprites.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-5T1:46:36 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ghost_sprites 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_mem_read.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-14T4:51:34 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | map_mem_read 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_sprite_mem.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-11-30T21:37:15 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | map_sprite_mem 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Source/ipcore_dir/movement_sprites.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-5T1:53:57 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | movement_sprites 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Source/ipcore_dir/map_collision_detect.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2011-12-15T18:31:53 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | map_collision_detect 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Sat Dec 03 20:57:32 2011 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_vio:1.04.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc3s1000 26 | SET devicefamily = spartan3 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ft256 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -5 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.04.a 40 | # END Select 41 | # BEGIN Parameters 42 | CSET asynchronous_input_port_width=8 43 | CSET asynchronous_output_port_width=8 44 | CSET component_name=chip_scope 45 | CSET enable_asynchronous_input_port=false 46 | CSET enable_asynchronous_output_port=false 47 | CSET enable_synchronous_input_port=true 48 | CSET enable_synchronous_output_port=true 49 | CSET example_design=false 50 | CSET invert_clock_input=false 51 | CSET synchronous_input_port_width=64 52 | CSET synchronous_output_port_width=64 53 | # END Parameters 54 | GENERATE 55 | # CRC: 2185df1d 56 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_2.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 13.2 4 | # Date: Wed Dec 14 01:17:59 2011 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:chipscope_vio:1.04.a 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc3s1000 26 | SET devicefamily = spartan3 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ft256 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -5 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.04.a 40 | # END Select 41 | # BEGIN Parameters 42 | CSET asynchronous_input_port_width=19 43 | CSET asynchronous_output_port_width=33 44 | CSET component_name=chip_scope_2 45 | CSET enable_asynchronous_input_port=true 46 | CSET enable_asynchronous_output_port=true 47 | CSET enable_synchronous_input_port=false 48 | CSET enable_synchronous_output_port=false 49 | CSET example_design=false 50 | CSET invert_clock_input=false 51 | CSET synchronous_input_port_width=8 52 | CSET synchronous_output_port_width=8 53 | # END Parameters 54 | GENERATE 55 | # CRC: 20d364cd 56 | -------------------------------------------------------------------------------- /Source/Project.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /Source/vga_controller_640_60.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:15:53 04/29/2011 7 | // Design Name: 8 | // Module Name: VGAcontrol 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module vga_controller_640_60 (pixel_clk,HS,VS,hcounter,vcounter,blank); 22 | 23 | input pixel_clk; 24 | output HS, VS, blank; 25 | output [10:0] hcounter, vcounter; 26 | 27 | parameter HMAX = 800; // maxium value for the horizontal pixel counter 28 | parameter VMAX = 525; // maxium value for the vertical pixel counter 29 | parameter HLINES = 640; // total number of visible columns 30 | parameter HFP = 648; // value for the horizontal counter where front porch ends 31 | parameter HSP = 744; // value for the horizontal counter where the synch pulse ends 32 | parameter VLINES = 480; // total number of visible lines 33 | parameter VFP = 482; // value for the vertical counter where the frone proch ends 34 | parameter VSP = 484; // value for the vertical counter where the synch pulse ends 35 | parameter SPP = 0; 36 | 37 | 38 | wire video_enable; 39 | reg HS,VS,blank; 40 | reg [10:0] hcounter,vcounter; 41 | 42 | always@(posedge pixel_clk)begin 43 | blank <= ~video_enable; 44 | end 45 | 46 | always@(posedge pixel_clk)begin 47 | if (hcounter == HMAX) hcounter <= 0; 48 | else hcounter <= hcounter + 1; 49 | end 50 | 51 | always@(posedge pixel_clk)begin 52 | if(hcounter == HMAX) begin 53 | if(vcounter == VMAX) vcounter <= 0; 54 | else vcounter <= vcounter + 1; 55 | end 56 | end 57 | 58 | always@(posedge pixel_clk)begin 59 | if(hcounter >= HFP && hcounter < HSP) HS <= SPP; 60 | else HS <= ~SPP; 61 | end 62 | 63 | always@(posedge pixel_clk)begin 64 | if(vcounter >= VFP && vcounter < VSP) VS <= SPP; 65 | else VS <= ~SPP; 66 | end 67 | 68 | assign video_enable = (hcounter < HLINES && vcounter < VLINES) ? 1'b1 : 1'b0; 69 | 70 | endmodule -------------------------------------------------------------------------------- /Source/keyboard_buffer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:36:10 11/01/2011 7 | // Design Name: 8 | // Module Name: keyboard_buffer 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | /* 23 | * File Primary Author: Idan Warsawski 24 | * See LICENSE for license information 25 | */ 26 | 27 | module keyboard_buffer(key_out, ps2d, ps2c, clk_50mhz, reset); 28 | input ps2d, ps2c, clk_50mhz, reset; 29 | output [7:0] key_out; 30 | 31 | wire ps2d, ps2c, clk_50mhz; 32 | reg [7:0] key_out; 33 | reg [7:0] last_key; 34 | wire [7:0] key_code; 35 | 36 | ps2key ps2(clk_50mhz, ps2d, ps2c, key_code); 37 | reg key_down; 38 | 39 | always @(posedge clk_50mhz) begin 40 | if(reset) begin 41 | key_out <= 8'h00; 42 | key_down <= 0; 43 | last_key <= key_code; 44 | end else begin 45 | //This makes sure we only output for 1 clock cycle 46 | if((key_out == last_key) || ((last_key == key_code) && key_down)) begin 47 | key_out <= 8'h00; 48 | key_down <= 1; 49 | last_key <= key_code; 50 | end else begin 51 | //This is valid for 1 character codes ONLY 52 | //It ensures that we catch the upcode (F0) and don't modify anything by setting 53 | //key_down equal to 1 54 | if(key_code == 8'hE0) begin 55 | last_key <= key_code; 56 | key_down <= key_down; 57 | key_out <= 8'h00; 58 | end else begin 59 | if(key_code == 8'hF0) begin 60 | key_down <= 1; 61 | key_out <= 8'h00; 62 | last_key <= key_code; 63 | end else begin 64 | if(key_down) begin //this indicates an endcode 65 | key_down <= 0; 66 | key_out <= 8'h00; 67 | last_key <= key_code; 68 | end else begin 69 | key_out <= key_code; 70 | last_key <= key_code; 71 | key_down <= 1; 72 | end 73 | end 74 | end 75 | end 76 | end 77 | 78 | 79 | end 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /Source/score_bcd_converter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 17:20:08 12/05/2011 7 | // Design Name: 8 | // Module Name: Score_in 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | /* 23 | * File Primary Author: Greg Zoeller 24 | * See LICENSE for license information 25 | */ 26 | 27 | module score_bcd_converter(s1,s2,s3,s4,s5,s6, scorein1, scorein2, clk,reset); 28 | input [19:0] scorein1, scorein2; 29 | input clk, reset; 30 | output [3:0] s1,s2,s3,s4,s5,s6; 31 | reg [3:0] s2,s3,s4,s5,s6,s1; 32 | reg [20:0] s_total, s_current; 33 | 34 | wire [4:0] s_difference; 35 | assign s_difference = s_total - s_current; 36 | 37 | always @ (posedge clk) 38 | begin 39 | if(reset == 1) 40 | begin 41 | s_current <=0; 42 | s_total <= 0; 43 | s1 <= 0; 44 | s2 <= 0; 45 | s3 <= 0; 46 | s4 <= 0; 47 | s5 <= 0; 48 | s6 <= 0; 49 | end 50 | else begin 51 | s_total <= scorein1 + scorein2; 52 | 53 | if( s1 > 9) 54 | begin 55 | s2 <= s2 + 1; 56 | s1 <= s1 - 10; 57 | end 58 | else if ( s2 > 9) 59 | begin 60 | s3 <= s3 +1; 61 | s2 <= s2 - 10; 62 | end 63 | else if( s3 >9) 64 | begin 65 | s4 <= s4 +1; 66 | s3 <= s3-10; 67 | end 68 | else if( s4 >9) 69 | begin 70 | s5 <= s5 +1; 71 | s4 <= s4-10; 72 | end 73 | else if( s5 >9) 74 | begin 75 | s6 <= s6 +1; 76 | s5 <= s4-10; 77 | end 78 | else if( s6 >9) 79 | begin 80 | s1 <=0; 81 | s2 <=0; 82 | s3 <=0; 83 | s4 <=0; 84 | s5 <=0; 85 | s6 <=0; 86 | end 87 | else if(s_difference != 5'b0_0000) 88 | begin 89 | s1 <= s1 + s_difference[3:0]; 90 | s_current <= s_total; 91 | end 92 | end 93 | 94 | 95 | 96 | 97 | end 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | endmodule 106 | -------------------------------------------------------------------------------- /Source/ps2key.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ps2key( 4 | clk50, // 50 MHz Clock 5 | kin, // serial keyboard data input 6 | kclk, // keyboard clock 7 | code // parallel scan code 8 | ); 9 | 10 | input kin, kclk, clk50; 11 | output [7:0] code; 12 | reg [7:0] code; 13 | reg [3:0] i; // counter variable 14 | reg [10:0] ksr; // keyboard shift register 15 | reg [11:0] cnt; // large count variable used for reset 16 | reg reset; // signal used to reset i 17 | 18 | initial begin // Initialization block that resets all valuse 19 | ksr = 0; // to zero by default 20 | i = 0; 21 | code = 0; 22 | cnt = 0; 23 | end 24 | 25 | always @ (posedge clk50) begin // This block will drive a signal, reset, high 26 | if (cnt > 3000) begin // if kclk is ever high for longer than 60 27 | reset <= 0; // microsec. This is used to reset the value of 28 | cnt <= 0; // i in the block below if the system ever gets 29 | end // off in count or a new device is connected. 30 | else if (kclk == 1) begin // Under normal conditions, kclk should never be 31 | reset <= 1; // asserted for longer than at max 30 microsec as 32 | cnt <= cnt + 1; // the period of kcclk is 60 microsec. 33 | end 34 | else begin 35 | reset <= 1; 36 | cnt <= 0; 37 | end 38 | end 39 | 40 | always @ (negedge kclk or negedge reset) begin 41 | if (reset == 0) begin // Here, the reset condition for i is checked. 42 | ksr <= ksr; // If the system is not keyboard is not sending 43 | i <= 0; // any signals, i is set to 0. This allows the 44 | code <= code; // keyboard to be unplugged and plugged back in 45 | end // without i getting messed up. 46 | else if (i < 10) begin // If i is less than 10, go through the usual 47 | ksr[i] <= kin; // motions of assigning the bit value to the 48 | i <= i + 1; // correct place in ksr, increment i, and keep 49 | code <= code; // code the same. 50 | end // 51 | else begin // If i is equal to 10, i.e. this is the last 52 | i <= 0; // bit... read that bit in, set i to 0, and 53 | ksr[i] <= kin; // set code to its approproate section of ksr. 54 | code <= ksr[8:1]; 55 | end 56 | end 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /Source/t_map_controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 17:22:43 11/06/2011 8 | // Design Name: map_controller 9 | // Module Name: X:/Desktop/EC551/Lab3/Lab3/t_map_controller.v 10 | // Project Name: Lab3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: map_controller 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module t_map_controller; 26 | 27 | // Inputs 28 | reg [9:0] x; 29 | reg [8:0] y; 30 | reg clk; 31 | reg clk_25mhz; 32 | reg reset; 33 | reg [1:0] map_num; 34 | // Outputs 35 | wire [2:0] block_color; 36 | wire [3:0] valid_dir; 37 | 38 | // Instantiate the Unit Under Test (UUT) 39 | map_controller uut ( 40 | .vga_out(block_color), 41 | .valid_dir(valid_dir), 42 | .pixel_x(x), 43 | .pixel_y(y), 44 | .map_num(map_num), 45 | .reset(reset), 46 | .clk_50mhz(clk), 47 | .clk_25mhz(clk_25mhz), 48 | .tmp_in(2'b00) 49 | ); 50 | integer i; 51 | 52 | initial begin 53 | #100; 54 | 55 | // Initialize Inputs 56 | x = 0; 57 | y = 16; 58 | clk = 0; 59 | clk_25mhz = 0; 60 | map_num = 0; 61 | // Wait 100 ns for global reset to finish 62 | #10 clk = 1; #10 clk = 0; 63 | reset = 1; 64 | #10 clk = 1; #10 clk = 0; 65 | #10 clk = 1; #10 clk = 0; 66 | #10 clk = 1; #10 clk = 0; 67 | reset = 0; 68 | 69 | repeat(50) begin 70 | #10 clk = 1; #10 clk = 0; 71 | end 72 | #10 clk = 1; #10 clk = 0; 73 | reset = 1; 74 | #10 clk = 1; #10 clk = 0; 75 | #10 clk = 1; #10 clk = 0; 76 | #10 clk = 1; #10 clk = 0; 77 | reset = 0; 78 | 79 | repeat(100) begin 80 | #10 clk = 1; #10 clk = 0; 81 | end 82 | map_num = 1; 83 | repeat(1000) begin 84 | #10 clk = 1; #10 clk = 0; 85 | end 86 | 87 | x = 0; 88 | y = 1; 89 | #10 clk = 1; #10 clk = 0; 90 | x = 1; 91 | y = 1; 92 | #10 clk = 1; #10 clk = 0; 93 | 94 | // Add stimulus here 95 | 96 | end 97 | 98 | always @(posedge clk) begin 99 | clk_25mhz <= ~clk_25mhz; 100 | end 101 | 102 | always @(posedge clk_25mhz) begin 103 | if(x == 76) begin 104 | x <= 44; 105 | y <= y + 1; 106 | end else begin 107 | x <= x + 1; 108 | y <= y; 109 | end 110 | end 111 | endmodule 112 | 113 | -------------------------------------------------------------------------------- /Source/sin_lut.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:40:21 10/30/2011 7 | // Design Name: 8 | // Module Name: sin_lut 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | /* 23 | * File Primary Author: Idan Warsawski 24 | * See LICENSE for license information 25 | */ 26 | 27 | module sin_lut(out, in); 28 | output [4:0] out; 29 | input [5:0] in; 30 | reg [4:0] out; 31 | always begin 32 | case(in) 33 | /*0: out = 8; 34 | 1: out = 10; 35 | 2: out = 13; 36 | 3: out = 14; 37 | 4: out = 15; 38 | 5: out = 14; 39 | 6: out = 13; 40 | 7: out = 10; 41 | 8: out = 8; 42 | 9: out = 5; 43 | 10: out = 2; 44 | 11: out = 1; 45 | 12: out = 0; 46 | 13: out = 1; 47 | 14: out = 2; 48 | 15: out = 5;*/ 49 | 50 | /*0: out = 15; 51 | 1: out = 17; 52 | 2: out = 20; 53 | 3: out = 23; 54 | 4: out = 25; 55 | 5: out = 27; 56 | 6: out = 28; 57 | 7: out = 29; 58 | 8: out = 29; 59 | 9: out = 29; 60 | 10: out = 28; 61 | 11: out = 27; 62 | 12: out = 25; 63 | 13: out = 23; 64 | 14: out = 20; 65 | 15: out = 17; 66 | 16: out = 15; 67 | 17: out = 12; 68 | 18: out = 9; 69 | 19: out = 6; 70 | 20: out = 4; 71 | 21: out = 2; 72 | 22: out = 1; 73 | 23: out = 0; 74 | 24: out = 0; 75 | 25: out = 0; 76 | 26: out = 1; 77 | 27: out = 2; 78 | 28: out = 4; 79 | 29: out = 6; 80 | 30: out = 9; 81 | 31: out = 12;*/ 82 | 0: out = 15; 83 | 1: out = 17; 84 | 2: out = 19; 85 | 3: out = 21; 86 | 4: out = 23; 87 | 5: out = 25; 88 | 6: out = 26; 89 | 7: out = 27; 90 | 8: out = 28; 91 | 9: out = 29; 92 | 10: out = 29; 93 | 11: out = 29; 94 | 12: out = 28; 95 | 13: out = 27; 96 | 14: out = 26; 97 | 15: out = 25; 98 | 16: out = 23; 99 | 17: out = 21; 100 | 18: out = 19; 101 | 19: out = 17; 102 | 20: out = 15; 103 | 21: out = 12; 104 | 22: out = 10; 105 | 23: out = 8; 106 | 24: out = 6; 107 | 25: out = 4; 108 | 26: out = 3; 109 | 27: out = 2; 110 | 28: out = 1; 111 | 29: out = 0; 112 | 30: out = 0; 113 | 31: out = 0; 114 | 32: out = 1; 115 | 33: out = 2; 116 | 34: out = 3; 117 | 35: out = 4; 118 | 36: out = 6; 119 | 37: out = 8; 120 | 38: out = 10; 121 | 39: out = 12; 122 | default: out = 0; 123 | endcase 124 | 125 | end 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /Source/ipcore_dir/chip_scope_2.cdc: -------------------------------------------------------------------------------- 1 | #ChipScope Core Generator Project File Version 3.0 2 | #Tue Dec 13 20:18:48 Eastern Standard Time 2011 3 | SignalExport.asyncInput<0000>=AsyncIn[0] 4 | SignalExport.asyncInput<0001>=AsyncIn[1] 5 | SignalExport.asyncInput<0002>=AsyncIn[2] 6 | SignalExport.asyncInput<0003>=AsyncIn[3] 7 | SignalExport.asyncInput<0004>=AsyncIn[4] 8 | SignalExport.asyncInput<0005>=AsyncIn[5] 9 | SignalExport.asyncInput<0006>=AsyncIn[6] 10 | SignalExport.asyncInput<0007>=AsyncIn[7] 11 | SignalExport.asyncInput<0008>=AsyncIn[8] 12 | SignalExport.asyncInput<0009>=AsyncIn[9] 13 | SignalExport.asyncInput<0010>=AsyncIn[10] 14 | SignalExport.asyncInput<0011>=AsyncIn[11] 15 | SignalExport.asyncInput<0012>=AsyncIn[12] 16 | SignalExport.asyncInput<0013>=AsyncIn[13] 17 | SignalExport.asyncInput<0014>=AsyncIn[14] 18 | SignalExport.asyncInput<0015>=AsyncIn[15] 19 | SignalExport.asyncInput<0016>=AsyncIn[16] 20 | SignalExport.asyncInput<0017>=AsyncIn[17] 21 | SignalExport.asyncInput<0018>=AsyncIn[18] 22 | SignalExport.asyncInputWidth=19 23 | SignalExport.asyncOutput<0000>=AsyncOut[0] 24 | SignalExport.asyncOutput<0001>=AsyncOut[1] 25 | SignalExport.asyncOutput<0002>=AsyncOut[2] 26 | SignalExport.asyncOutput<0003>=AsyncOut[3] 27 | SignalExport.asyncOutput<0004>=AsyncOut[4] 28 | SignalExport.asyncOutput<0005>=AsyncOut[5] 29 | SignalExport.asyncOutput<0006>=AsyncOut[6] 30 | SignalExport.asyncOutput<0007>=AsyncOut[7] 31 | SignalExport.asyncOutput<0008>=AsyncOut[8] 32 | SignalExport.asyncOutput<0009>=AsyncOut[9] 33 | SignalExport.asyncOutput<0010>=AsyncOut[10] 34 | SignalExport.asyncOutput<0011>=AsyncOut[11] 35 | SignalExport.asyncOutput<0012>=AsyncOut[12] 36 | SignalExport.asyncOutput<0013>=AsyncOut[13] 37 | SignalExport.asyncOutput<0014>=AsyncOut[14] 38 | SignalExport.asyncOutput<0015>=AsyncOut[15] 39 | SignalExport.asyncOutput<0016>=AsyncOut[16] 40 | SignalExport.asyncOutput<0017>=AsyncOut[17] 41 | SignalExport.asyncOutput<0018>=AsyncOut[18] 42 | SignalExport.asyncOutput<0019>=AsyncOut[19] 43 | SignalExport.asyncOutput<0020>=AsyncOut[20] 44 | SignalExport.asyncOutput<0021>=AsyncOut[21] 45 | SignalExport.asyncOutput<0022>=AsyncOut[22] 46 | SignalExport.asyncOutput<0023>=AsyncOut[23] 47 | SignalExport.asyncOutput<0024>=AsyncOut[24] 48 | SignalExport.asyncOutput<0025>=AsyncOut[25] 49 | SignalExport.asyncOutput<0026>=AsyncOut[26] 50 | SignalExport.asyncOutput<0027>=AsyncOut[27] 51 | SignalExport.asyncOutput<0028>=AsyncOut[28] 52 | SignalExport.asyncOutput<0029>=AsyncOut[29] 53 | SignalExport.asyncOutput<0030>=AsyncOut[30] 54 | SignalExport.asyncOutput<0031>=AsyncOut[31] 55 | SignalExport.asyncOutput<0032>=AsyncOut[32] 56 | SignalExport.asyncOutputWidth=33 57 | SignalExport.syncInputWidth=0 58 | SignalExport.syncOutputWidth=0 59 | SignalExport.type=vio 60 | 61 | --------------------------------------------------------------------------------