├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile ├── README.md ├── check_env.py ├── config ├── generator_config.json ├── generator_config_12.json └── platform_config.json ├── database ├── Makefile ├── adcInst.json ├── connect_cloud.py ├── insert_json_cloud.py └── readme.md ├── doc ├── Cadre Flow Guide.pdf └── SoC Integrator Walkthrough.pdf ├── generators ├── adc-gen │ ├── 0_spice_template │ │ ├── gf12lp │ │ │ ├── cdac │ │ │ ├── cdac.v │ │ │ ├── cdac_ideal │ │ │ ├── comp_nand.cdl │ │ │ ├── comp_nand.v │ │ │ ├── dac │ │ │ ├── meas_card │ │ │ ├── meas_card_pex │ │ │ ├── sar │ │ │ ├── sar.pex │ │ │ ├── sar.v │ │ │ ├── sar_logic │ │ │ ├── sar_logic.v │ │ │ ├── tbSar.pex.sp │ │ │ └── tbSar.sp │ │ └── tsmc65lp │ │ │ ├── cdac │ │ │ ├── cdac.v │ │ │ ├── comp_nand.cdl │ │ │ ├── comp_nand.v │ │ │ ├── dac │ │ │ ├── meas_card │ │ │ ├── meas_card_pex │ │ │ ├── sar │ │ │ ├── sar.pex │ │ │ ├── sar.v │ │ │ ├── sar_logic │ │ │ ├── sar_logic.v │ │ │ ├── tbSar.pex.sp │ │ │ └── tbSar.sp │ ├── adc_data.json │ ├── bk0_spice_template │ │ ├── cdac │ │ ├── cdac.v │ │ ├── comp_nand.cdl │ │ ├── comp_nand.v │ │ ├── dac │ │ ├── meas_card │ │ ├── sar │ │ ├── sar.v │ │ ├── sar_logic │ │ └── sar_logic.v │ ├── clear_file │ ├── makefile │ ├── models │ │ ├── gf12lp.model_adc.xlsx │ │ └── tsmc65lp.model_adc.xlsx │ ├── netlist_gen │ ├── readme.md │ ├── result_gen │ ├── result_gen_pex │ ├── run_sim │ ├── run_sim_pex │ ├── search_result_adc.csv │ ├── temp │ │ ├── cdac_autogen_temp │ │ └── cdac_autogen_temp_v │ ├── tools │ │ ├── ADC_netlist.py │ │ ├── ADC_netlist_pex.py │ │ ├── Makefile_backup │ │ ├── Readme │ │ ├── adc-gen.py │ │ ├── auto_netgen.py │ │ ├── clear_file │ │ ├── fft_sar.py │ │ ├── function.py │ │ ├── meas_card │ │ ├── readparamgen.py │ │ ├── result.py │ │ ├── tbSar.pex.sp │ │ └── tbSar.sp │ └── work │ │ ├── adcInst.json │ │ └── sar.json ├── cdc-gen │ ├── .gitignore │ ├── makefile │ ├── models │ │ ├── gf12lp.model_cdcprecharge │ │ ├── gf12lp.model_cdcsweep │ │ ├── tsmc65lp.model_cdcprecharge │ │ └── tsmc65lp.model_cdcsweep │ ├── readme.md │ ├── src │ │ ├── CDCW_CNT.v │ │ ├── CDCW_CNT_template.v │ │ ├── CDC_ANALOG.nl.v │ │ ├── CDC_ANALOG2.nl.v │ │ ├── CDC_ANALOG2_template.nl.v │ │ ├── CDC_ANALOG_template.nl.v │ │ ├── CDC_ANALOG_template_generic.nl.v │ │ ├── CDC_AUTO.v │ │ ├── CDC_def.v │ │ ├── CDC_template.v │ │ ├── DLY_COMP.nl.v │ │ ├── DLY_COMP_template.nl.v │ │ ├── INVCHAIN_ISOVDD.nl.v │ │ ├── INVCHAIN_ISOVDD_template.nl.v │ │ ├── INVCHAIN_ISOVDD_template_generic.nl.v │ │ ├── NEXT_EDGE_GEN.nl.v │ │ ├── NEXT_EDGE_GEN_template.nl.v │ │ ├── SRLATCH.nl.v │ │ ├── cdcInst.v │ │ └── counter_16b.v │ ├── test.json │ └── tools │ │ ├── CDC_netlist.py │ │ ├── TEMP_netlist.py │ │ ├── VERILOG_wrapper.py │ │ ├── cdc-gen.py │ │ ├── code.py │ │ ├── code_measure.inc │ │ ├── function.py │ │ ├── parse.py │ │ ├── readparamgen.py │ │ └── result_error.py ├── dcdc-gen │ ├── Makefile │ ├── README.md │ ├── test.json │ ├── tools │ │ └── dcdc-gen.py │ └── verilog │ │ ├── DCDC_CONV2to1.v │ │ ├── DCDC_HUNIT_CONV2to1.v │ │ └── DCDC_TOP.template.v ├── ldo-gen │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── models │ │ ├── gf12lp_9T_model.json │ │ ├── gf12lp_model.json │ │ ├── gfbicmos8hp_model.json │ │ └── tsmc65lp_model.json │ ├── test.json │ ├── tools │ │ ├── ldo_gen.py │ │ ├── ldo_model.py │ │ ├── ldo_model_verilog_gen.py │ │ └── supported_inputs.json │ └── verilog │ │ ├── LDO_CONTROLLER_TEMPLATE.v │ │ └── LDO_TEMPLATE.v ├── memory-gen │ ├── MemGen.py │ ├── README.md │ ├── SRAM │ │ ├── __init__.py │ │ ├── bitcell_array.py │ │ ├── bitcellprops.py │ │ ├── cellprops.py │ │ ├── col_periphery.py │ │ ├── row_periphery.py │ │ ├── sram_arch.py │ │ ├── sram_model.py │ │ └── sram_top.py │ ├── deo │ │ ├── __init__.py │ │ ├── auxcell_char.py │ │ ├── deo.py │ │ └── sram_char.py │ ├── globals │ │ ├── __init__.py │ │ ├── configs │ │ │ ├── mem_arch.yaml │ │ │ ├── mem_config.yaml │ │ │ └── verified_tools.yaml │ │ ├── global_utils.py │ │ ├── mem_arch_config_parser.py │ │ └── toolenv_check.py │ ├── macro_gen │ │ ├── __init__.py │ │ ├── apr │ │ │ ├── __init__.py │ │ │ ├── floorplan.py │ │ │ ├── power_plan.py │ │ │ └── setup.py │ │ ├── lef_parser.py │ │ ├── macro_gen.py │ │ ├── synthesis │ │ │ ├── __init__.py │ │ │ └── synth_constraints.py │ │ └── verilog_gen │ │ │ ├── __init__.py │ │ │ ├── bank_verilog_gen.py │ │ │ ├── bitcell_array_verilog.py │ │ │ ├── col_periphery_verilog.py │ │ │ ├── contol_unit_verilog.py │ │ │ ├── multi_bank_verilog_gen.py │ │ │ └── row_periphery_verilog.py │ └── tech_collaterals │ │ └── collateral--12nm--gf--lp.yaml ├── pll-gen │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── ble_design_params.json │ ├── bleach.mk │ ├── formats │ │ ├── :run │ │ ├── BLE │ │ │ ├── ble_dco │ │ │ │ ├── dco_CC_se_3st.v │ │ │ │ ├── dco_FC_se2_half.v │ │ │ │ └── form_ble_dco.v │ │ │ ├── ble_pll_top │ │ │ │ ├── FUNCTIONS.v │ │ │ │ ├── dltdc_lut_lib.sv │ │ │ │ ├── form_ble_pll_top.sv │ │ │ │ ├── form_pll_controller.sv │ │ │ │ ├── form_tstdc_controller.sv │ │ │ │ └── ssc_generator.v │ │ │ ├── ble_top │ │ │ │ ├── FREQ_DIV.v │ │ │ │ ├── FUNCTIONS.v │ │ │ │ ├── GFSK_CTRL_V2.v │ │ │ │ ├── PLL_CONTROLLER.v │ │ │ │ ├── PLL_CONTROLLER_TDC_COUNTER.v │ │ │ │ ├── SCPA_Final.v │ │ │ │ ├── SCPA_with_Decoupling_Cap.v │ │ │ │ ├── SSC_GENERATOR.v │ │ │ │ ├── TDC_COUNTER.v │ │ │ │ ├── TOP_FSM_V1.sv │ │ │ │ ├── ble_top.sv │ │ │ │ ├── ble_top_spi_slave.sv │ │ │ │ ├── ble_top_spi_wrap.sv │ │ │ │ ├── bu_pll6.v │ │ │ │ ├── dco_CC.v │ │ │ │ ├── dco_FC.v │ │ │ │ ├── synth_pll_dco_interp.v │ │ │ │ └── synth_pll_dco_outbuff.v │ │ │ ├── form_ble_dco.v │ │ │ └── tstdc_counter │ │ │ │ ├── form_dltdc_v3.sv │ │ │ │ ├── form_tstdc_counter.sv │ │ │ │ └── lpdtc_v2.sv │ │ ├── dummy_hspicesim.mk │ │ ├── dummy_pex_hspicesim.mk │ │ ├── form_PDpll_always_source.tcl │ │ ├── form_TB_PLL_CONTROLLER_TDC_COUNTER.sv │ │ ├── form_analog_core.v │ │ ├── form_dco_model_noise.v │ │ ├── form_dco_v2.v │ │ ├── form_dump_irun.tcl │ │ ├── form_ffdco.v │ │ ├── form_flist.f │ │ ├── form_flist_beh.f │ │ ├── form_form_Makefile │ │ ├── form_hspicesim.mk │ │ ├── form_model.json │ │ ├── form_pex_hspicesim.mk │ │ ├── form_pex_model.json │ │ ├── form_pll_PD.v │ │ ├── form_pll_controller_v2.sv │ │ ├── form_pll_dc.filelist.tcl │ │ ├── form_pll_include.mk │ │ ├── form_pll_top_v2.sv │ │ ├── form_run │ │ ├── form_spec_out.json │ │ ├── form_synth_pll.v │ │ ├── form_tb_pll_top.sv │ │ ├── form_tdc_counter_v2.sv │ │ └── tdc_counter_v2.sv │ ├── pll_pex_model_gf12lp.json │ ├── pll_pex_model_gf12lp_FCv2.json │ ├── publicModel │ │ ├── gf12lp_pll_model.json │ │ └── tsmc65lp_pll_model.json │ ├── pymodules │ │ ├── .gitignore │ │ ├── modeling.py │ │ ├── preparations.py │ │ ├── run_digital_flow.py │ │ ├── run_pex_flow.py │ │ ├── run_pex_sim.py │ │ ├── run_pre_sim.py │ │ └── txt_mds.py │ ├── std_cell_names.json │ ├── std_cell_names_public.json │ ├── test_alpha12.json │ ├── test_beta65.json │ ├── tools │ │ ├── BLE_GEN.py │ │ ├── BLE_PLL_GEN.py │ │ ├── DCO_TO_PREP.py │ │ ├── MDL_GEN_Beta.py │ │ ├── MDL_GEN_Beta_KBR.py │ │ └── PLL_GEN_Beta.py │ ├── verilog_sim │ │ ├── :run │ │ ├── :run_beh │ │ ├── dco_model_noise.v │ │ ├── differential_dco │ │ │ ├── :run │ │ │ ├── INCA_libs │ │ │ │ ├── .history.lock │ │ │ │ ├── history │ │ │ │ ├── irun.lnx8664.15.20.nc │ │ │ │ │ ├── .nclib.lock │ │ │ │ │ ├── .ncrun.lock │ │ │ │ │ ├── .ncv.lock │ │ │ │ │ ├── .timestamp.ts │ │ │ │ │ ├── OVMHOME │ │ │ │ │ ├── UVMHOME │ │ │ │ │ ├── bind.lst.lnx8664 │ │ │ │ │ ├── cdsrun.lib │ │ │ │ │ ├── files.ts │ │ │ │ │ ├── grandtraverse.eecs.umich.edu_27473 │ │ │ │ │ │ ├── irun.args │ │ │ │ │ │ ├── ncsim.args │ │ │ │ │ │ └── ncsim.env │ │ │ │ │ ├── hdlrun.var │ │ │ │ │ ├── irun.args │ │ │ │ │ ├── ncelab.args │ │ │ │ │ ├── ncelab.env │ │ │ │ │ ├── ncelab.hrd │ │ │ │ │ ├── ncvlog.args │ │ │ │ │ ├── ncvlog.env │ │ │ │ │ ├── ncvlog.files │ │ │ │ │ └── ncvlog.hrd │ │ │ │ ├── irun.nc │ │ │ │ └── worklib │ │ │ │ │ ├── .cdsvmod │ │ │ │ │ ├── .inca.db.150.lnx8664 │ │ │ │ │ ├── cdsinfo.tag │ │ │ │ │ └── inca.lnx8664.150.pak │ │ │ ├── dump_irun.tcl │ │ │ ├── flist.f │ │ │ ├── irun.history │ │ │ ├── irun.key │ │ │ ├── irun_comp.history │ │ │ ├── irun_run.history │ │ │ ├── pll_lock_report.txt │ │ │ ├── signals │ │ │ │ ├── SIG_C_controller.svwf │ │ │ │ ├── SIG_PLL_CNTRL_TDC_CNTR_top.svwf │ │ │ │ ├── SIG_TDC_to_DCO_CCW.svwf │ │ │ │ └── SIG_phase_ramp.svwf │ │ │ ├── tb │ │ │ │ ├── TB_PLL_CONTROLLER_TDC_COUNTER.sv │ │ │ │ └── TB_synth_pll.v │ │ │ └── verilog │ │ │ │ ├── ANALOG_CORE.v │ │ │ │ ├── DCO_MODEL.v │ │ │ │ ├── FUNCTIONS.v │ │ │ │ ├── PLL_CONTROLLER.v │ │ │ │ ├── PLL_CONTROLLER_TDC_COUNTER.v │ │ │ │ ├── SSC_GENERATOR.v │ │ │ │ ├── TB_synth_pll.v │ │ │ │ ├── TDC_COUNTER.v │ │ │ │ ├── bu_dco_8stg.v │ │ │ │ ├── dco_8stg.v │ │ │ │ ├── dco_CC.v │ │ │ │ ├── dco_FC.v │ │ │ │ ├── synth_dco.v │ │ │ │ ├── synth_pll.v │ │ │ │ ├── synth_pll_dco_interp.v │ │ │ │ └── synth_pll_dco_outbuff.v │ │ ├── dump_irun.tcl │ │ ├── flist_beh.f │ │ ├── pllClkfreq.csv │ │ ├── single_ended_dco │ │ │ ├── :run │ │ │ ├── INCA_libs │ │ │ │ ├── .history.lock │ │ │ │ ├── history │ │ │ │ ├── irun.lnx8664.15.20.nc │ │ │ │ │ ├── .nclib.lock │ │ │ │ │ ├── .ncrun.lock │ │ │ │ │ ├── .ncv.lock │ │ │ │ │ ├── .timestamp.ts │ │ │ │ │ ├── OVMHOME │ │ │ │ │ ├── UVMHOME │ │ │ │ │ ├── bind.lst.lnx8664 │ │ │ │ │ ├── cdsrun.lib │ │ │ │ │ ├── files.ts │ │ │ │ │ ├── hdl.var │ │ │ │ │ ├── hdlrun.var │ │ │ │ │ ├── irun.args │ │ │ │ │ ├── ncelab.args │ │ │ │ │ ├── ncelab.env │ │ │ │ │ ├── ncelab.hrd │ │ │ │ │ ├── ncsim.args │ │ │ │ │ ├── ncsim.env │ │ │ │ │ ├── ncsim_restart.args │ │ │ │ │ ├── ncsim_restart.env │ │ │ │ │ ├── ncvlog.args │ │ │ │ │ ├── ncvlog.env │ │ │ │ │ ├── ncvlog.files │ │ │ │ │ └── ncvlog.hrd │ │ │ │ ├── irun.nc │ │ │ │ └── worklib │ │ │ │ │ ├── .cdsvmod │ │ │ │ │ ├── .inca.db.150.lnx8664 │ │ │ │ │ ├── cdsinfo.tag │ │ │ │ │ └── inca.lnx8664.150.pak │ │ │ ├── dump_irun.tcl │ │ │ ├── flist.f │ │ │ ├── irun.history │ │ │ ├── irun.key │ │ │ ├── irun_comp.history │ │ │ ├── irun_run.history │ │ │ ├── pll_lock_report.txt │ │ │ ├── verilog │ │ │ │ ├── DCO_MODEL.v │ │ │ │ ├── analog_core.v │ │ │ │ ├── dco_model.v │ │ │ │ ├── dco_model_noise.v │ │ │ │ ├── dco_model_therm_test.v │ │ │ │ ├── functions.v │ │ │ │ ├── pll_controller.sv │ │ │ │ ├── pll_controller_tdc_counter.sv │ │ │ │ ├── pll_fsm_define.sv │ │ │ │ ├── ssc_generator.v │ │ │ │ ├── tb_pll_controller.sv │ │ │ │ ├── tb_pll_controller_tdc_counter.sv │ │ │ │ └── tdc_counter.v │ │ │ └── xrun.key │ │ ├── two_step_tdc │ │ │ ├── tstdc_pre_dltdc │ │ │ │ ├── :run │ │ │ │ ├── dump_irun.tcl │ │ │ │ ├── flist.f │ │ │ │ └── verilog │ │ │ │ │ ├── DCO_MODEL.v │ │ │ │ │ ├── DFF.v │ │ │ │ │ ├── analog_core.v │ │ │ │ │ ├── bu_dltdc_model.sv │ │ │ │ │ ├── dco_CC_se.v │ │ │ │ │ ├── dco_FC_se2.v │ │ │ │ │ ├── dco_model.v │ │ │ │ │ ├── dco_model_noise.v │ │ │ │ │ ├── dco_model_therm_test.v │ │ │ │ │ ├── dltdc_model.sv │ │ │ │ │ ├── dltdc_v2.sv │ │ │ │ │ ├── dltdc_v2_for_synth.sv │ │ │ │ │ ├── functions.v │ │ │ │ │ ├── pll_controller.sv │ │ │ │ │ ├── pll_controller_tdc_counter.sv │ │ │ │ │ ├── pll_fsm_define.sv │ │ │ │ │ ├── pre_dltdc.sv │ │ │ │ │ ├── ssc_generator.v │ │ │ │ │ ├── tb_dltdc_model.sv │ │ │ │ │ ├── tb_pll_controller.sv │ │ │ │ │ ├── tb_pll_controller_tdc_counter.sv │ │ │ │ │ ├── tb_tstdc_counter.sv │ │ │ │ │ └── tstdc_counter.v │ │ │ └── tstdc_top │ │ │ │ ├── :run │ │ │ │ ├── dltdc_dump_irun.tcl │ │ │ │ ├── dltdc_flist.f │ │ │ │ ├── dump_irun.tcl │ │ │ │ ├── flist.f │ │ │ │ ├── irun.key │ │ │ │ └── verilog │ │ │ │ ├── DCO_MODEL.v │ │ │ │ ├── analog_core.v │ │ │ │ ├── bu_dltdc_model.sv │ │ │ │ ├── dco_model.v │ │ │ │ ├── dco_model_noise.v │ │ │ │ ├── dco_model_therm_test.v │ │ │ │ ├── dltdc_model.sv │ │ │ │ ├── functions.v │ │ │ │ ├── pll_controller.sv │ │ │ │ ├── pll_controller_tdc_counter.sv │ │ │ │ ├── pll_fsm_define.sv │ │ │ │ ├── pre_dltdc.sv │ │ │ │ ├── ssc_generator.v │ │ │ │ ├── tb_dltdc_model.sv │ │ │ │ ├── tb_pll_controller.sv │ │ │ │ ├── tb_pll_controller_tdc_counter.sv │ │ │ │ ├── tb_tstdc_counter.sv │ │ │ │ └── tstdc_counter.v │ │ └── verilog │ │ │ ├── analog_core.v │ │ │ ├── dco_model_noise.v │ │ │ ├── functions.v │ │ │ ├── pll7.sv │ │ │ ├── pll_controller.sv │ │ │ ├── ssc_generator.v │ │ │ ├── tb_pll_top.sv │ │ │ └── tdc_counter.sv │ └── verilogs │ │ ├── ANALOG_CORE.v │ │ ├── DCO_MODEL.v │ │ ├── FUNCTIONS.v │ │ ├── PLL_CONTROLLER.v │ │ ├── PLL_CONTROLLER_TDC_COUNTER.v │ │ ├── SSC_GENERATOR.v │ │ ├── TB_synth_pll.v │ │ ├── TDC_COUNTER.v │ │ ├── bu_dco_8stg.v │ │ ├── dco_10drv_10cc_30fc_18stg.v │ │ ├── dco_8stg.v │ │ ├── dco_CC.v │ │ ├── dco_CC_se.v │ │ ├── dco_CC_se_3st.v │ │ ├── dco_FC.v │ │ ├── dco_FC_se.v │ │ ├── dco_FC_se2.v │ │ ├── dco_FC_se2_half.v │ │ ├── dco_FC_se_half.v │ │ ├── pll_controller_v2.sv │ │ ├── ssc_generator.v │ │ ├── synth_dco.v │ │ ├── synth_pll_dco_interp_gf12lp.v │ │ ├── synth_pll_dco_interp_tsmc65lp.v │ │ ├── synth_pll_dco_outbuff_gf12lp.v │ │ └── synth_pll_dco_outbuff_tsmc65lp.v ├── scpa-gen │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── bu_test.json │ ├── models │ │ └── tsmc65lp_model.json │ ├── test.json │ ├── tools │ │ ├── ldo_gen.py │ │ ├── ldo_model.py │ │ ├── ldo_model_verilog_gen.py │ │ ├── scpa_gen.py │ │ ├── scpa_gen_pex.py │ │ ├── scpa_model.py │ │ └── supported_inputs.json │ └── verilog │ │ ├── CLK_DRIVER.v │ │ ├── SCPA.v │ │ └── SCPA_MIMCAP_new.v └── temp-sense-gen │ ├── .gitignore │ ├── golden_error_opt.csv │ ├── makefile │ ├── models │ └── tsmc65lp.model_tempsense │ ├── readme.md │ ├── search_result.csv │ ├── src │ ├── TEMP_ANALOG_hv.nl.v │ ├── TEMP_ANALOG_hv.v │ ├── TEMP_ANALOG_lv.nl.v │ ├── TEMP_ANALOG_lv.v │ ├── TEMP_AUTO_def.v │ ├── counter.v │ ├── counter_generic.v │ └── tempsenseInst.v │ ├── test.json │ ├── tools │ ├── TEMP_netlist.py │ ├── data_collection.py │ ├── function.py │ ├── parse.py │ ├── readparamgen.py │ ├── result.py │ ├── result_error.py │ ├── run_sim_top.py │ └── temp-sense-gen.py │ └── work │ └── .gitignore ├── soc ├── README.md ├── config │ └── soc_model_config.json ├── docs │ ├── flow.jpg │ └── platform_config.png ├── python │ ├── .nfs0000000000b80a310000210c │ ├── ML_model.py │ ├── Verilog_Parser.py │ ├── analogGen.py │ ├── checkDB.py │ ├── clean.py │ ├── closedLoop.py │ ├── connectionGen.py │ ├── fastAnalogGen.py │ ├── fastSoc.py │ ├── hierarchy.py │ ├── hierarchy_checker.py │ ├── jsonXmlGenerator.py │ ├── modifyDBFiles.py │ ├── power_area_estimator │ │ ├── algebric_model_evaluator.py │ │ ├── equation_solver.py │ │ ├── ml_regression_merged.py │ │ ├── modifying_csv_columns_ml.py │ │ ├── wrapper.py │ │ └── y_interception.py │ ├── rtlXmlGenerator.py │ ├── soc.py │ └── synthesis.py └── rubi │ ├── Add_Components_Parameters.rb │ ├── Define_SoCParameters.rb │ ├── Status_utilities.rb │ ├── VE_utilities.rb │ ├── clean.rb │ ├── convert_json.rb │ ├── generate.rb │ ├── parse_json.rb │ └── report.rb └── tests ├── demo-feb-2021 ├── Makefile └── design_ldo.json ├── demo-jan-2020 ├── Makefile ├── design_ldo.json ├── design_ldo_pll.json └── design_ldo_pll_mem.json ├── pll ├── Makefile └── design.json ├── power_area_model └── Makefile ├── tape_out ├── Makefile └── design.json └── temp_sens ├── Makefile └── design_temp_sens.json /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/.gitignore -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/.gitmodules -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/LICENSE -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/Makefile -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/README.md -------------------------------------------------------------------------------- /check_env.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/check_env.py -------------------------------------------------------------------------------- /config/generator_config.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/config/generator_config.json -------------------------------------------------------------------------------- /config/generator_config_12.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/config/generator_config_12.json -------------------------------------------------------------------------------- /config/platform_config.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/config/platform_config.json -------------------------------------------------------------------------------- /database/Makefile: -------------------------------------------------------------------------------- 1 | database: 2 | ./insert_json_cloud.py --filename ./adcInst.json -------------------------------------------------------------------------------- /database/adcInst.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/database/adcInst.json -------------------------------------------------------------------------------- /database/connect_cloud.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/database/connect_cloud.py -------------------------------------------------------------------------------- /database/insert_json_cloud.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/database/insert_json_cloud.py -------------------------------------------------------------------------------- /database/readme.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/database/readme.md -------------------------------------------------------------------------------- /doc/Cadre Flow Guide.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/doc/Cadre Flow Guide.pdf -------------------------------------------------------------------------------- /doc/SoC Integrator Walkthrough.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/doc/SoC Integrator Walkthrough.pdf -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/cdac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/cdac -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/cdac.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/cdac.v -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/cdac_ideal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/cdac_ideal -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/comp_nand.cdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/comp_nand.cdl -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/comp_nand.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/comp_nand.v -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/dac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/dac -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/meas_card: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/meas_card -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/meas_card_pex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/meas_card_pex -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/sar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/sar -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/sar.pex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/sar.pex -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/sar.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/sar.v -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/sar_logic: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/sar_logic -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/sar_logic.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/sar_logic.v -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/tbSar.pex.sp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/tbSar.pex.sp -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/tbSar.sp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/gf12lp/tbSar.sp -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/cdac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/cdac -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/cdac.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/cdac.v -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/comp_nand.cdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/comp_nand.cdl -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/comp_nand.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/comp_nand.v -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/dac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/dac -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/meas_card: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/meas_card -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/meas_card_pex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/meas_card_pex -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/sar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/sar -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/sar.pex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/sar.pex -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/sar.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/sar.v -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/sar_logic: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/sar_logic -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/sar_logic.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/sar_logic.v -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/tbSar.pex.sp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/tbSar.pex.sp -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/tbSar.sp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/0_spice_template/tsmc65lp/tbSar.sp -------------------------------------------------------------------------------- /generators/adc-gen/adc_data.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/adc_data.json -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/cdac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/cdac -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/cdac.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/cdac.v -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/comp_nand.cdl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/comp_nand.cdl -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/comp_nand.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/comp_nand.v -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/dac: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/dac -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/meas_card: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/meas_card -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/sar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/sar -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/sar.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/sar.v -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/sar_logic: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/sar_logic -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/sar_logic.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/bk0_spice_template/sar_logic.v -------------------------------------------------------------------------------- /generators/adc-gen/clear_file: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/clear_file -------------------------------------------------------------------------------- /generators/adc-gen/makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/makefile -------------------------------------------------------------------------------- /generators/adc-gen/models/gf12lp.model_adc.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/models/gf12lp.model_adc.xlsx -------------------------------------------------------------------------------- /generators/adc-gen/models/tsmc65lp.model_adc.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/models/tsmc65lp.model_adc.xlsx -------------------------------------------------------------------------------- /generators/adc-gen/netlist_gen: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/netlist_gen -------------------------------------------------------------------------------- /generators/adc-gen/readme.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/readme.md -------------------------------------------------------------------------------- /generators/adc-gen/result_gen: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/result_gen -------------------------------------------------------------------------------- /generators/adc-gen/result_gen_pex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/result_gen_pex -------------------------------------------------------------------------------- /generators/adc-gen/run_sim: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/run_sim -------------------------------------------------------------------------------- /generators/adc-gen/run_sim_pex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/run_sim_pex -------------------------------------------------------------------------------- /generators/adc-gen/search_result_adc.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/search_result_adc.csv -------------------------------------------------------------------------------- /generators/adc-gen/temp/cdac_autogen_temp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/temp/cdac_autogen_temp -------------------------------------------------------------------------------- /generators/adc-gen/temp/cdac_autogen_temp_v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/temp/cdac_autogen_temp_v -------------------------------------------------------------------------------- /generators/adc-gen/tools/ADC_netlist.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/ADC_netlist.py -------------------------------------------------------------------------------- /generators/adc-gen/tools/ADC_netlist_pex.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/ADC_netlist_pex.py -------------------------------------------------------------------------------- /generators/adc-gen/tools/Makefile_backup: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/Makefile_backup -------------------------------------------------------------------------------- /generators/adc-gen/tools/Readme: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/Readme -------------------------------------------------------------------------------- /generators/adc-gen/tools/adc-gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/adc-gen.py -------------------------------------------------------------------------------- /generators/adc-gen/tools/auto_netgen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/auto_netgen.py -------------------------------------------------------------------------------- /generators/adc-gen/tools/clear_file: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/clear_file -------------------------------------------------------------------------------- /generators/adc-gen/tools/fft_sar.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/fft_sar.py -------------------------------------------------------------------------------- /generators/adc-gen/tools/function.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/function.py -------------------------------------------------------------------------------- /generators/adc-gen/tools/meas_card: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/meas_card -------------------------------------------------------------------------------- /generators/adc-gen/tools/readparamgen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/readparamgen.py -------------------------------------------------------------------------------- /generators/adc-gen/tools/result.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/result.py -------------------------------------------------------------------------------- /generators/adc-gen/tools/tbSar.pex.sp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/tbSar.pex.sp -------------------------------------------------------------------------------- /generators/adc-gen/tools/tbSar.sp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/tools/tbSar.sp -------------------------------------------------------------------------------- /generators/adc-gen/work/adcInst.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/work/adcInst.json -------------------------------------------------------------------------------- /generators/adc-gen/work/sar.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/adc-gen/work/sar.json -------------------------------------------------------------------------------- /generators/cdc-gen/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/.gitignore -------------------------------------------------------------------------------- /generators/cdc-gen/makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/makefile -------------------------------------------------------------------------------- /generators/cdc-gen/models/gf12lp.model_cdcprecharge: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/models/gf12lp.model_cdcprecharge -------------------------------------------------------------------------------- /generators/cdc-gen/models/gf12lp.model_cdcsweep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/models/gf12lp.model_cdcsweep -------------------------------------------------------------------------------- /generators/cdc-gen/models/tsmc65lp.model_cdcprecharge: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/models/tsmc65lp.model_cdcprecharge -------------------------------------------------------------------------------- /generators/cdc-gen/models/tsmc65lp.model_cdcsweep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/models/tsmc65lp.model_cdcsweep -------------------------------------------------------------------------------- /generators/cdc-gen/readme.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/readme.md -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDCW_CNT.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDCW_CNT.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDCW_CNT_template.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDCW_CNT_template.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_ANALOG.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDC_ANALOG.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_ANALOG2.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDC_ANALOG2.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_ANALOG2_template.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDC_ANALOG2_template.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_ANALOG_template.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDC_ANALOG_template.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_ANALOG_template_generic.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDC_ANALOG_template_generic.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_AUTO.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDC_AUTO.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_def.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDC_def.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_template.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/CDC_template.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/DLY_COMP.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/DLY_COMP.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/DLY_COMP_template.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/DLY_COMP_template.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/INVCHAIN_ISOVDD.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/INVCHAIN_ISOVDD.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/INVCHAIN_ISOVDD_template.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/INVCHAIN_ISOVDD_template.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/INVCHAIN_ISOVDD_template_generic.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/INVCHAIN_ISOVDD_template_generic.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/NEXT_EDGE_GEN.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/NEXT_EDGE_GEN.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/NEXT_EDGE_GEN_template.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/NEXT_EDGE_GEN_template.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/SRLATCH.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/SRLATCH.nl.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/cdcInst.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/cdcInst.v -------------------------------------------------------------------------------- /generators/cdc-gen/src/counter_16b.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/src/counter_16b.v -------------------------------------------------------------------------------- /generators/cdc-gen/test.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/test.json -------------------------------------------------------------------------------- /generators/cdc-gen/tools/CDC_netlist.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/CDC_netlist.py -------------------------------------------------------------------------------- /generators/cdc-gen/tools/TEMP_netlist.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/TEMP_netlist.py -------------------------------------------------------------------------------- /generators/cdc-gen/tools/VERILOG_wrapper.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/VERILOG_wrapper.py -------------------------------------------------------------------------------- /generators/cdc-gen/tools/cdc-gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/cdc-gen.py -------------------------------------------------------------------------------- /generators/cdc-gen/tools/code.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/code.py -------------------------------------------------------------------------------- /generators/cdc-gen/tools/code_measure.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/code_measure.inc -------------------------------------------------------------------------------- /generators/cdc-gen/tools/function.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/function.py -------------------------------------------------------------------------------- /generators/cdc-gen/tools/parse.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/parse.py -------------------------------------------------------------------------------- /generators/cdc-gen/tools/readparamgen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/readparamgen.py -------------------------------------------------------------------------------- /generators/cdc-gen/tools/result_error.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/cdc-gen/tools/result_error.py -------------------------------------------------------------------------------- /generators/dcdc-gen/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/dcdc-gen/Makefile -------------------------------------------------------------------------------- /generators/dcdc-gen/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/dcdc-gen/README.md -------------------------------------------------------------------------------- /generators/dcdc-gen/test.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/dcdc-gen/test.json -------------------------------------------------------------------------------- /generators/dcdc-gen/tools/dcdc-gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/dcdc-gen/tools/dcdc-gen.py -------------------------------------------------------------------------------- /generators/dcdc-gen/verilog/DCDC_CONV2to1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/dcdc-gen/verilog/DCDC_CONV2to1.v -------------------------------------------------------------------------------- /generators/dcdc-gen/verilog/DCDC_HUNIT_CONV2to1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/dcdc-gen/verilog/DCDC_HUNIT_CONV2to1.v -------------------------------------------------------------------------------- /generators/dcdc-gen/verilog/DCDC_TOP.template.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/dcdc-gen/verilog/DCDC_TOP.template.v -------------------------------------------------------------------------------- /generators/ldo-gen/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/.gitignore -------------------------------------------------------------------------------- /generators/ldo-gen/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/Makefile -------------------------------------------------------------------------------- /generators/ldo-gen/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/README.md -------------------------------------------------------------------------------- /generators/ldo-gen/models/gf12lp_9T_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/models/gf12lp_9T_model.json -------------------------------------------------------------------------------- /generators/ldo-gen/models/gf12lp_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/models/gf12lp_model.json -------------------------------------------------------------------------------- /generators/ldo-gen/models/gfbicmos8hp_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/models/gfbicmos8hp_model.json -------------------------------------------------------------------------------- /generators/ldo-gen/models/tsmc65lp_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/models/tsmc65lp_model.json -------------------------------------------------------------------------------- /generators/ldo-gen/test.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/test.json -------------------------------------------------------------------------------- /generators/ldo-gen/tools/ldo_gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/tools/ldo_gen.py -------------------------------------------------------------------------------- /generators/ldo-gen/tools/ldo_model.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/tools/ldo_model.py -------------------------------------------------------------------------------- /generators/ldo-gen/tools/ldo_model_verilog_gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/tools/ldo_model_verilog_gen.py -------------------------------------------------------------------------------- /generators/ldo-gen/tools/supported_inputs.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/tools/supported_inputs.json -------------------------------------------------------------------------------- /generators/ldo-gen/verilog/LDO_CONTROLLER_TEMPLATE.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/verilog/LDO_CONTROLLER_TEMPLATE.v -------------------------------------------------------------------------------- /generators/ldo-gen/verilog/LDO_TEMPLATE.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/ldo-gen/verilog/LDO_TEMPLATE.v -------------------------------------------------------------------------------- /generators/memory-gen/MemGen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/MemGen.py -------------------------------------------------------------------------------- /generators/memory-gen/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/README.md -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/bitcell_array.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/SRAM/bitcell_array.py -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/bitcellprops.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/SRAM/bitcellprops.py -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/cellprops.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/SRAM/cellprops.py -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/col_periphery.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/SRAM/col_periphery.py -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/row_periphery.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/SRAM/row_periphery.py -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/sram_arch.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/SRAM/sram_arch.py -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/sram_model.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/SRAM/sram_model.py -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/sram_top.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/SRAM/sram_top.py -------------------------------------------------------------------------------- /generators/memory-gen/deo/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/memory-gen/deo/auxcell_char.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/deo/auxcell_char.py -------------------------------------------------------------------------------- /generators/memory-gen/deo/deo.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/deo/deo.py -------------------------------------------------------------------------------- /generators/memory-gen/deo/sram_char.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/deo/sram_char.py -------------------------------------------------------------------------------- /generators/memory-gen/globals/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/memory-gen/globals/configs/mem_arch.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/globals/configs/mem_arch.yaml -------------------------------------------------------------------------------- /generators/memory-gen/globals/configs/mem_config.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/globals/configs/mem_config.yaml -------------------------------------------------------------------------------- /generators/memory-gen/globals/configs/verified_tools.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/globals/configs/verified_tools.yaml -------------------------------------------------------------------------------- /generators/memory-gen/globals/global_utils.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/globals/global_utils.py -------------------------------------------------------------------------------- /generators/memory-gen/globals/mem_arch_config_parser.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/globals/mem_arch_config_parser.py -------------------------------------------------------------------------------- /generators/memory-gen/globals/toolenv_check.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/globals/toolenv_check.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/apr/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/apr/floorplan.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/apr/floorplan.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/apr/power_plan.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/apr/power_plan.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/apr/setup.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/apr/setup.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/lef_parser.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/lef_parser.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/macro_gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/macro_gen.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/synthesis/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/synthesis/synth_constraints.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/synthesis/synth_constraints.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/verilog_gen/__init__.py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/verilog_gen/bank_verilog_gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/verilog_gen/bank_verilog_gen.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/verilog_gen/bitcell_array_verilog.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/verilog_gen/bitcell_array_verilog.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/verilog_gen/col_periphery_verilog.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/verilog_gen/col_periphery_verilog.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/verilog_gen/contol_unit_verilog.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/verilog_gen/contol_unit_verilog.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/verilog_gen/multi_bank_verilog_gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/verilog_gen/multi_bank_verilog_gen.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/verilog_gen/row_periphery_verilog.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/macro_gen/verilog_gen/row_periphery_verilog.py -------------------------------------------------------------------------------- /generators/memory-gen/tech_collaterals/collateral--12nm--gf--lp.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/memory-gen/tech_collaterals/collateral--12nm--gf--lp.yaml -------------------------------------------------------------------------------- /generators/pll-gen/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/.gitignore -------------------------------------------------------------------------------- /generators/pll-gen/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/Makefile -------------------------------------------------------------------------------- /generators/pll-gen/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/README.md -------------------------------------------------------------------------------- /generators/pll-gen/ble_design_params.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/ble_design_params.json -------------------------------------------------------------------------------- /generators/pll-gen/bleach.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/bleach.mk -------------------------------------------------------------------------------- /generators/pll-gen/formats/:run: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/:run -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_dco/dco_CC_se_3st.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_dco/dco_CC_se_3st.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_dco/dco_FC_se2_half.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_dco/dco_FC_se2_half.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_dco/form_ble_dco.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_dco/form_ble_dco.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_pll_top/FUNCTIONS.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_pll_top/FUNCTIONS.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_pll_top/dltdc_lut_lib.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_pll_top/dltdc_lut_lib.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_pll_top/form_ble_pll_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_pll_top/form_ble_pll_top.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_pll_top/form_pll_controller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_pll_top/form_pll_controller.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_pll_top/form_tstdc_controller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_pll_top/form_tstdc_controller.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_pll_top/ssc_generator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_pll_top/ssc_generator.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/FREQ_DIV.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/FREQ_DIV.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/FUNCTIONS.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/FUNCTIONS.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/GFSK_CTRL_V2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/GFSK_CTRL_V2.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/PLL_CONTROLLER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/PLL_CONTROLLER.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/PLL_CONTROLLER_TDC_COUNTER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/PLL_CONTROLLER_TDC_COUNTER.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/SCPA_Final.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/SCPA_Final.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/SCPA_with_Decoupling_Cap.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/SCPA_with_Decoupling_Cap.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/SSC_GENERATOR.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/SSC_GENERATOR.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/TDC_COUNTER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/TDC_COUNTER.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/TOP_FSM_V1.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/TOP_FSM_V1.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/ble_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/ble_top.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/ble_top_spi_slave.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/ble_top_spi_slave.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/ble_top_spi_wrap.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/ble_top_spi_wrap.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/bu_pll6.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/bu_pll6.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/dco_CC.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/dco_CC.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/dco_FC.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/dco_FC.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/synth_pll_dco_interp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/synth_pll_dco_interp.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/synth_pll_dco_outbuff.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/ble_top/synth_pll_dco_outbuff.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/form_ble_dco.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/form_ble_dco.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/tstdc_counter/form_dltdc_v3.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/tstdc_counter/form_dltdc_v3.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/tstdc_counter/form_tstdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/tstdc_counter/form_tstdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/tstdc_counter/lpdtc_v2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/BLE/tstdc_counter/lpdtc_v2.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/dummy_hspicesim.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/dummy_hspicesim.mk -------------------------------------------------------------------------------- /generators/pll-gen/formats/dummy_pex_hspicesim.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/dummy_pex_hspicesim.mk -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_PDpll_always_source.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_PDpll_always_source.tcl -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_TB_PLL_CONTROLLER_TDC_COUNTER.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_TB_PLL_CONTROLLER_TDC_COUNTER.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_analog_core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_analog_core.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_dco_model_noise.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_dco_model_noise.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_dco_v2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_dco_v2.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_dump_irun.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_dump_irun.tcl -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_ffdco.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_ffdco.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_flist.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_flist.f -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_flist_beh.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_flist_beh.f -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_form_Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_form_Makefile -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_hspicesim.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_hspicesim.mk -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_model.json -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pex_hspicesim.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_pex_hspicesim.mk -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pex_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_pex_model.json -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pll_PD.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_pll_PD.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pll_controller_v2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_pll_controller_v2.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pll_dc.filelist.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_pll_dc.filelist.tcl -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pll_include.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_pll_include.mk -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pll_top_v2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_pll_top_v2.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_run: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_run -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_spec_out.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_spec_out.json -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_synth_pll.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_synth_pll.v -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_tb_pll_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_tb_pll_top.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_tdc_counter_v2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/form_tdc_counter_v2.sv -------------------------------------------------------------------------------- /generators/pll-gen/formats/tdc_counter_v2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/formats/tdc_counter_v2.sv -------------------------------------------------------------------------------- /generators/pll-gen/pll_pex_model_gf12lp.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pll_pex_model_gf12lp.json -------------------------------------------------------------------------------- /generators/pll-gen/pll_pex_model_gf12lp_FCv2.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pll_pex_model_gf12lp_FCv2.json -------------------------------------------------------------------------------- /generators/pll-gen/publicModel/gf12lp_pll_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/publicModel/gf12lp_pll_model.json -------------------------------------------------------------------------------- /generators/pll-gen/publicModel/tsmc65lp_pll_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/publicModel/tsmc65lp_pll_model.json -------------------------------------------------------------------------------- /generators/pll-gen/pymodules/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pymodules/.gitignore -------------------------------------------------------------------------------- /generators/pll-gen/pymodules/modeling.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pymodules/modeling.py -------------------------------------------------------------------------------- /generators/pll-gen/pymodules/preparations.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pymodules/preparations.py -------------------------------------------------------------------------------- /generators/pll-gen/pymodules/run_digital_flow.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pymodules/run_digital_flow.py -------------------------------------------------------------------------------- /generators/pll-gen/pymodules/run_pex_flow.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pymodules/run_pex_flow.py -------------------------------------------------------------------------------- /generators/pll-gen/pymodules/run_pex_sim.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pymodules/run_pex_sim.py -------------------------------------------------------------------------------- /generators/pll-gen/pymodules/run_pre_sim.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pymodules/run_pre_sim.py -------------------------------------------------------------------------------- /generators/pll-gen/pymodules/txt_mds.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/pymodules/txt_mds.py -------------------------------------------------------------------------------- /generators/pll-gen/std_cell_names.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/std_cell_names.json -------------------------------------------------------------------------------- /generators/pll-gen/std_cell_names_public.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/std_cell_names_public.json -------------------------------------------------------------------------------- /generators/pll-gen/test_alpha12.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/test_alpha12.json -------------------------------------------------------------------------------- /generators/pll-gen/test_beta65.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/test_beta65.json -------------------------------------------------------------------------------- /generators/pll-gen/tools/BLE_GEN.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/tools/BLE_GEN.py -------------------------------------------------------------------------------- /generators/pll-gen/tools/BLE_PLL_GEN.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/tools/BLE_PLL_GEN.py -------------------------------------------------------------------------------- /generators/pll-gen/tools/DCO_TO_PREP.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/tools/DCO_TO_PREP.py -------------------------------------------------------------------------------- /generators/pll-gen/tools/MDL_GEN_Beta.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/tools/MDL_GEN_Beta.py -------------------------------------------------------------------------------- /generators/pll-gen/tools/MDL_GEN_Beta_KBR.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/tools/MDL_GEN_Beta_KBR.py -------------------------------------------------------------------------------- /generators/pll-gen/tools/PLL_GEN_Beta.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/tools/PLL_GEN_Beta.py -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/:run: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/:run -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/:run_beh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/:run_beh -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/dco_model_noise.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/dco_model_noise.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/:run: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/:run -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/.history.lock: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/history: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/history -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.nclib.lock: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncrun.lock: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncv.lock: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/OVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/UVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/bind.lst.lnx8664: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/bind.lst.lnx8664 -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/files.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/files.ts -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473/irun.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473/irun.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473/ncsim.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473/ncsim.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473/ncsim.env: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473/ncsim.env -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/irun.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/irun.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.env: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.env -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.hrd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.hrd -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.env: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.env -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.files: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.files -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.hrd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.hrd -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.nc: -------------------------------------------------------------------------------- 1 | irun.lnx8664.12.20.nc -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/.cdsvmod: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/.inca.db.150.lnx8664: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/.inca.db.150.lnx8664 -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/cdsinfo.tag: -------------------------------------------------------------------------------- 1 | CDSLIBRARY 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/inca.lnx8664.150.pak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/inca.lnx8664.150.pak -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/dump_irun.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/dump_irun.tcl -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/flist.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/flist.f -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/irun.history: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/irun.history -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/irun.key: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/irun_comp.history: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/irun_comp.history -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/irun_run.history: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/irun_run.history -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/pll_lock_report.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/pll_lock_report.txt -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/signals/SIG_C_controller.svwf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/signals/SIG_C_controller.svwf -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/signals/SIG_PLL_CNTRL_TDC_CNTR_top.svwf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/signals/SIG_PLL_CNTRL_TDC_CNTR_top.svwf -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/signals/SIG_TDC_to_DCO_CCW.svwf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/signals/SIG_TDC_to_DCO_CCW.svwf -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/signals/SIG_phase_ramp.svwf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/signals/SIG_phase_ramp.svwf -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/tb/TB_PLL_CONTROLLER_TDC_COUNTER.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/tb/TB_PLL_CONTROLLER_TDC_COUNTER.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/tb/TB_synth_pll.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/tb/TB_synth_pll.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/ANALOG_CORE.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/ANALOG_CORE.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/DCO_MODEL.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/DCO_MODEL.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/FUNCTIONS.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/FUNCTIONS.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/PLL_CONTROLLER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/PLL_CONTROLLER.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/PLL_CONTROLLER_TDC_COUNTER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/PLL_CONTROLLER_TDC_COUNTER.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/SSC_GENERATOR.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/SSC_GENERATOR.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/TB_synth_pll.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/TB_synth_pll.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/TDC_COUNTER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/TDC_COUNTER.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/bu_dco_8stg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/bu_dco_8stg.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/dco_8stg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/dco_8stg.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/dco_CC.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/dco_CC.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/dco_FC.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/dco_FC.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/synth_dco.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/synth_dco.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/synth_pll.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/synth_pll.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/synth_pll_dco_interp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/synth_pll_dco_interp.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/synth_pll_dco_outbuff.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/differential_dco/verilog/synth_pll_dco_outbuff.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/dump_irun.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/dump_irun.tcl -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/flist_beh.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/flist_beh.f -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/pllClkfreq.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/pllClkfreq.csv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/:run: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/:run -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/.history.lock: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/history: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/history -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.nclib.lock: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncrun.lock: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncv.lock: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/OVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/UVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/bind.lst.lnx8664: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/bind.lst.lnx8664 -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/files.ts: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/files.ts -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/hdl.var: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/hdl.var -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/irun.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/irun.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.env: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.env -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.hrd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.hrd -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim.env: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim.env -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.env: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.env -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.env: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.env -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.files: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.files -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.hrd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.hrd -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.nc: -------------------------------------------------------------------------------- 1 | irun.lnx8664.15.20.nc -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/.cdsvmod: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/.inca.db.150.lnx8664: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/.inca.db.150.lnx8664 -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/cdsinfo.tag: -------------------------------------------------------------------------------- 1 | CDSLIBRARY 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/inca.lnx8664.150.pak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/inca.lnx8664.150.pak -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/dump_irun.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/dump_irun.tcl -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/flist.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/flist.f -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/irun.history: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/irun.history -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/irun.key: -------------------------------------------------------------------------------- 1 | exit 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/irun_comp.history: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/irun_comp.history -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/irun_run.history: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/irun_run.history -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/pll_lock_report.txt: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/DCO_MODEL.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/DCO_MODEL.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/analog_core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/analog_core.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/dco_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/dco_model.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/dco_model_noise.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/dco_model_noise.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/dco_model_therm_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/dco_model_therm_test.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/functions.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/functions.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller_tdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller_tdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_fsm_define.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_fsm_define.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/ssc_generator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/ssc_generator.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/tb_pll_controller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/tb_pll_controller.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/tb_pll_controller_tdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/tb_pll_controller_tdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/tdc_counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/single_ended_dco/verilog/tdc_counter.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/xrun.key: -------------------------------------------------------------------------------- 1 | exit 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/:run: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/:run -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/dump_irun.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/dump_irun.tcl -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/flist.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/flist.f -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/DCO_MODEL.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/DCO_MODEL.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/DFF.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/DFF.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/analog_core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/analog_core.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/bu_dltdc_model.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/bu_dltdc_model.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_CC_se.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_CC_se.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_FC_se2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_FC_se2.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_model.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_model_noise.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_model_noise.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_model_therm_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_model_therm_test.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dltdc_model.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dltdc_model.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dltdc_v2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dltdc_v2.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dltdc_v2_for_synth.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dltdc_v2_for_synth.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/functions.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/functions.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/pll_controller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/pll_controller.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/pll_controller_tdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/pll_controller_tdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/pll_fsm_define.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/pll_fsm_define.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/pre_dltdc.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/pre_dltdc.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/ssc_generator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/ssc_generator.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tb_dltdc_model.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tb_dltdc_model.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tb_pll_controller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tb_pll_controller.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tb_pll_controller_tdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tb_pll_controller_tdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tb_tstdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tb_tstdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tstdc_counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/tstdc_counter.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/:run: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/:run -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/dltdc_dump_irun.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/dltdc_dump_irun.tcl -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/dltdc_flist.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/dltdc_flist.f -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/dump_irun.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/dump_irun.tcl -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/flist.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/flist.f -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/irun.key: -------------------------------------------------------------------------------- 1 | exit 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/DCO_MODEL.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/DCO_MODEL.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/analog_core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/analog_core.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/bu_dltdc_model.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/bu_dltdc_model.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/dco_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/dco_model.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/dco_model_noise.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/dco_model_noise.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/dco_model_therm_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/dco_model_therm_test.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/dltdc_model.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/dltdc_model.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/functions.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/functions.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/pll_controller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/pll_controller.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/pll_controller_tdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/pll_controller_tdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/pll_fsm_define.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/pll_fsm_define.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/pre_dltdc.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/pre_dltdc.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/ssc_generator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/ssc_generator.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tb_dltdc_model.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tb_dltdc_model.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tb_pll_controller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tb_pll_controller.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tb_pll_controller_tdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tb_pll_controller_tdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tb_tstdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tb_tstdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tstdc_counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/tstdc_counter.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/analog_core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/verilog/analog_core.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/dco_model_noise.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/verilog/dco_model_noise.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/functions.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/verilog/functions.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/pll7.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/verilog/pll7.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/pll_controller.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/verilog/pll_controller.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/ssc_generator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/verilog/ssc_generator.v -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/tb_pll_top.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/verilog/tb_pll_top.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/tdc_counter.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilog_sim/verilog/tdc_counter.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/ANALOG_CORE.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/ANALOG_CORE.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/DCO_MODEL.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/DCO_MODEL.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/FUNCTIONS.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/FUNCTIONS.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/PLL_CONTROLLER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/PLL_CONTROLLER.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/PLL_CONTROLLER_TDC_COUNTER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/PLL_CONTROLLER_TDC_COUNTER.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/SSC_GENERATOR.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/SSC_GENERATOR.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/TB_synth_pll.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/TB_synth_pll.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/TDC_COUNTER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/TDC_COUNTER.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/bu_dco_8stg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/bu_dco_8stg.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_10drv_10cc_30fc_18stg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_10drv_10cc_30fc_18stg.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_8stg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_8stg.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_CC.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_CC.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_CC_se.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_CC_se.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_CC_se_3st.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_CC_se_3st.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_FC.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC_se.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_FC_se.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC_se2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_FC_se2.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC_se2_half.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_FC_se2_half.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC_se_half.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/dco_FC_se_half.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/pll_controller_v2.sv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/pll_controller_v2.sv -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/ssc_generator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/ssc_generator.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/synth_dco.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/synth_dco.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/synth_pll_dco_interp_gf12lp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/synth_pll_dco_interp_gf12lp.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/synth_pll_dco_interp_tsmc65lp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/synth_pll_dco_interp_tsmc65lp.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/synth_pll_dco_outbuff_gf12lp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/synth_pll_dco_outbuff_gf12lp.v -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/synth_pll_dco_outbuff_tsmc65lp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/pll-gen/verilogs/synth_pll_dco_outbuff_tsmc65lp.v -------------------------------------------------------------------------------- /generators/scpa-gen/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/.gitignore -------------------------------------------------------------------------------- /generators/scpa-gen/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/Makefile -------------------------------------------------------------------------------- /generators/scpa-gen/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/README.md -------------------------------------------------------------------------------- /generators/scpa-gen/bu_test.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/bu_test.json -------------------------------------------------------------------------------- /generators/scpa-gen/models/tsmc65lp_model.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/models/tsmc65lp_model.json -------------------------------------------------------------------------------- /generators/scpa-gen/test.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/test.json -------------------------------------------------------------------------------- /generators/scpa-gen/tools/ldo_gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/tools/ldo_gen.py -------------------------------------------------------------------------------- /generators/scpa-gen/tools/ldo_model.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/tools/ldo_model.py -------------------------------------------------------------------------------- /generators/scpa-gen/tools/ldo_model_verilog_gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/tools/ldo_model_verilog_gen.py -------------------------------------------------------------------------------- /generators/scpa-gen/tools/scpa_gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/tools/scpa_gen.py -------------------------------------------------------------------------------- /generators/scpa-gen/tools/scpa_gen_pex.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/tools/scpa_gen_pex.py -------------------------------------------------------------------------------- /generators/scpa-gen/tools/scpa_model.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/tools/scpa_model.py -------------------------------------------------------------------------------- /generators/scpa-gen/tools/supported_inputs.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/tools/supported_inputs.json -------------------------------------------------------------------------------- /generators/scpa-gen/verilog/CLK_DRIVER.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/verilog/CLK_DRIVER.v -------------------------------------------------------------------------------- /generators/scpa-gen/verilog/SCPA.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/verilog/SCPA.v -------------------------------------------------------------------------------- /generators/scpa-gen/verilog/SCPA_MIMCAP_new.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/scpa-gen/verilog/SCPA_MIMCAP_new.v -------------------------------------------------------------------------------- /generators/temp-sense-gen/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/.gitignore -------------------------------------------------------------------------------- /generators/temp-sense-gen/golden_error_opt.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/golden_error_opt.csv -------------------------------------------------------------------------------- /generators/temp-sense-gen/makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/makefile -------------------------------------------------------------------------------- /generators/temp-sense-gen/models/tsmc65lp.model_tempsense: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/models/tsmc65lp.model_tempsense -------------------------------------------------------------------------------- /generators/temp-sense-gen/readme.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/readme.md -------------------------------------------------------------------------------- /generators/temp-sense-gen/search_result.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/search_result.csv -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_ANALOG_hv.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/src/TEMP_ANALOG_hv.nl.v -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_ANALOG_hv.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/src/TEMP_ANALOG_hv.v -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_ANALOG_lv.nl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/src/TEMP_ANALOG_lv.nl.v -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_ANALOG_lv.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/src/TEMP_ANALOG_lv.v -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_AUTO_def.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/src/TEMP_AUTO_def.v -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/src/counter.v -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/counter_generic.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/src/counter_generic.v -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/tempsenseInst.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/src/tempsenseInst.v -------------------------------------------------------------------------------- /generators/temp-sense-gen/test.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/test.json -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/TEMP_netlist.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/tools/TEMP_netlist.py -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/data_collection.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/tools/data_collection.py -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/function.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/tools/function.py -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/parse.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/tools/parse.py -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/readparamgen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/tools/readparamgen.py -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/result.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/tools/result.py -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/result_error.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/tools/result_error.py -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/run_sim_top.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/tools/run_sim_top.py -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/temp-sense-gen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/tools/temp-sense-gen.py -------------------------------------------------------------------------------- /generators/temp-sense-gen/work/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/generators/temp-sense-gen/work/.gitignore -------------------------------------------------------------------------------- /soc/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/README.md -------------------------------------------------------------------------------- /soc/config/soc_model_config.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/config/soc_model_config.json -------------------------------------------------------------------------------- /soc/docs/flow.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/docs/flow.jpg -------------------------------------------------------------------------------- /soc/docs/platform_config.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/docs/platform_config.png -------------------------------------------------------------------------------- /soc/python/.nfs0000000000b80a310000210c: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /soc/python/ML_model.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/ML_model.py -------------------------------------------------------------------------------- /soc/python/Verilog_Parser.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/Verilog_Parser.py -------------------------------------------------------------------------------- /soc/python/analogGen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/analogGen.py -------------------------------------------------------------------------------- /soc/python/checkDB.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/checkDB.py -------------------------------------------------------------------------------- /soc/python/clean.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/clean.py -------------------------------------------------------------------------------- /soc/python/closedLoop.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/closedLoop.py -------------------------------------------------------------------------------- /soc/python/connectionGen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/connectionGen.py -------------------------------------------------------------------------------- /soc/python/fastAnalogGen.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/fastAnalogGen.py -------------------------------------------------------------------------------- /soc/python/fastSoc.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/fastSoc.py -------------------------------------------------------------------------------- /soc/python/hierarchy.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/hierarchy.py -------------------------------------------------------------------------------- /soc/python/hierarchy_checker.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/hierarchy_checker.py -------------------------------------------------------------------------------- /soc/python/jsonXmlGenerator.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/jsonXmlGenerator.py -------------------------------------------------------------------------------- /soc/python/modifyDBFiles.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/modifyDBFiles.py -------------------------------------------------------------------------------- /soc/python/power_area_estimator/algebric_model_evaluator.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/power_area_estimator/algebric_model_evaluator.py -------------------------------------------------------------------------------- /soc/python/power_area_estimator/equation_solver.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/power_area_estimator/equation_solver.py -------------------------------------------------------------------------------- /soc/python/power_area_estimator/ml_regression_merged.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/power_area_estimator/ml_regression_merged.py -------------------------------------------------------------------------------- /soc/python/power_area_estimator/modifying_csv_columns_ml.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/power_area_estimator/modifying_csv_columns_ml.py -------------------------------------------------------------------------------- /soc/python/power_area_estimator/wrapper.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/power_area_estimator/wrapper.py -------------------------------------------------------------------------------- /soc/python/power_area_estimator/y_interception.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/power_area_estimator/y_interception.py -------------------------------------------------------------------------------- /soc/python/rtlXmlGenerator.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/rtlXmlGenerator.py -------------------------------------------------------------------------------- /soc/python/soc.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/soc.py -------------------------------------------------------------------------------- /soc/python/synthesis.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/python/synthesis.py -------------------------------------------------------------------------------- /soc/rubi/Add_Components_Parameters.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/rubi/Add_Components_Parameters.rb -------------------------------------------------------------------------------- /soc/rubi/Define_SoCParameters.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/rubi/Define_SoCParameters.rb -------------------------------------------------------------------------------- /soc/rubi/Status_utilities.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/rubi/Status_utilities.rb -------------------------------------------------------------------------------- /soc/rubi/VE_utilities.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/rubi/VE_utilities.rb -------------------------------------------------------------------------------- /soc/rubi/clean.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/rubi/clean.rb -------------------------------------------------------------------------------- /soc/rubi/convert_json.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/rubi/convert_json.rb -------------------------------------------------------------------------------- /soc/rubi/generate.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/rubi/generate.rb -------------------------------------------------------------------------------- /soc/rubi/parse_json.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/rubi/parse_json.rb -------------------------------------------------------------------------------- /soc/rubi/report.rb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/soc/rubi/report.rb -------------------------------------------------------------------------------- /tests/demo-feb-2021/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/demo-feb-2021/Makefile -------------------------------------------------------------------------------- /tests/demo-feb-2021/design_ldo.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/demo-feb-2021/design_ldo.json -------------------------------------------------------------------------------- /tests/demo-jan-2020/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/demo-jan-2020/Makefile -------------------------------------------------------------------------------- /tests/demo-jan-2020/design_ldo.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/demo-jan-2020/design_ldo.json -------------------------------------------------------------------------------- /tests/demo-jan-2020/design_ldo_pll.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/demo-jan-2020/design_ldo_pll.json -------------------------------------------------------------------------------- /tests/demo-jan-2020/design_ldo_pll_mem.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/demo-jan-2020/design_ldo_pll_mem.json -------------------------------------------------------------------------------- /tests/pll/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/pll/Makefile -------------------------------------------------------------------------------- /tests/pll/design.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/pll/design.json -------------------------------------------------------------------------------- /tests/power_area_model/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/power_area_model/Makefile -------------------------------------------------------------------------------- /tests/tape_out/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/tape_out/Makefile -------------------------------------------------------------------------------- /tests/tape_out/design.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/tape_out/design.json -------------------------------------------------------------------------------- /tests/temp_sens/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/temp_sens/Makefile -------------------------------------------------------------------------------- /tests/temp_sens/design_temp_sens.json: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/HEAD/tests/temp_sens/design_temp_sens.json --------------------------------------------------------------------------------