├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile ├── README.md ├── check_env.py ├── config ├── generator_config.json ├── generator_config_12.json └── platform_config.json ├── database ├── Makefile ├── adcInst.json ├── connect_cloud.py ├── insert_json_cloud.py └── readme.md ├── doc ├── Cadre Flow Guide.pdf └── SoC Integrator Walkthrough.pdf ├── generators ├── adc-gen │ ├── 0_spice_template │ │ ├── gf12lp │ │ │ ├── cdac │ │ │ ├── cdac.v │ │ │ ├── cdac_ideal │ │ │ ├── comp_nand.cdl │ │ │ ├── comp_nand.v │ │ │ ├── dac │ │ │ ├── meas_card │ │ │ ├── meas_card_pex │ │ │ ├── sar │ │ │ ├── sar.pex │ │ │ ├── sar.v │ │ │ ├── sar_logic │ │ │ ├── sar_logic.v │ │ │ ├── tbSar.pex.sp │ │ │ └── tbSar.sp │ │ └── tsmc65lp │ │ │ ├── cdac │ │ │ ├── cdac.v │ │ │ ├── comp_nand.cdl │ │ │ ├── comp_nand.v │ │ │ ├── dac │ │ │ ├── meas_card │ │ │ ├── meas_card_pex │ │ │ ├── sar │ │ │ ├── sar.pex │ │ │ ├── sar.v │ │ │ ├── sar_logic │ │ │ ├── sar_logic.v │ │ │ ├── tbSar.pex.sp │ │ │ └── tbSar.sp │ ├── adc_data.json │ ├── bk0_spice_template │ │ ├── cdac │ │ ├── cdac.v │ │ ├── comp_nand.cdl │ │ ├── comp_nand.v │ │ ├── dac │ │ ├── meas_card │ │ ├── sar │ │ ├── sar.v │ │ ├── sar_logic │ │ └── sar_logic.v │ ├── clear_file │ ├── makefile │ ├── models │ │ ├── gf12lp.model_adc.xlsx │ │ └── tsmc65lp.model_adc.xlsx │ ├── netlist_gen │ ├── readme.md │ ├── result_gen │ ├── result_gen_pex │ ├── run_sim │ ├── run_sim_pex │ ├── search_result_adc.csv │ ├── temp │ │ ├── cdac_autogen_temp │ │ └── cdac_autogen_temp_v │ ├── tools │ │ ├── ADC_netlist.py │ │ ├── ADC_netlist_pex.py │ │ ├── Makefile_backup │ │ ├── Readme │ │ ├── adc-gen.py │ │ ├── auto_netgen.py │ │ ├── clear_file │ │ ├── fft_sar.py │ │ ├── function.py │ │ ├── meas_card │ │ ├── readparamgen.py │ │ ├── result.py │ │ ├── tbSar.pex.sp │ │ └── tbSar.sp │ └── work │ │ ├── adcInst.json │ │ └── sar.json ├── cdc-gen │ ├── .gitignore │ ├── makefile │ ├── models │ │ ├── gf12lp.model_cdcprecharge │ │ ├── gf12lp.model_cdcsweep │ │ ├── tsmc65lp.model_cdcprecharge │ │ └── tsmc65lp.model_cdcsweep │ ├── readme.md │ ├── src │ │ ├── CDCW_CNT.v │ │ ├── CDCW_CNT_template.v │ │ ├── CDC_ANALOG.nl.v │ │ ├── CDC_ANALOG2.nl.v │ │ ├── CDC_ANALOG2_template.nl.v │ │ ├── CDC_ANALOG_template.nl.v │ │ ├── CDC_ANALOG_template_generic.nl.v │ │ ├── CDC_AUTO.v │ │ ├── CDC_def.v │ │ ├── CDC_template.v │ │ ├── DLY_COMP.nl.v │ │ ├── DLY_COMP_template.nl.v │ │ ├── INVCHAIN_ISOVDD.nl.v │ │ ├── INVCHAIN_ISOVDD_template.nl.v │ │ ├── INVCHAIN_ISOVDD_template_generic.nl.v │ │ ├── NEXT_EDGE_GEN.nl.v │ │ ├── NEXT_EDGE_GEN_template.nl.v │ │ ├── SRLATCH.nl.v │ │ ├── cdcInst.v │ │ └── counter_16b.v │ ├── test.json │ └── tools │ │ ├── CDC_netlist.py │ │ ├── TEMP_netlist.py │ │ ├── VERILOG_wrapper.py │ │ ├── cdc-gen.py │ │ ├── code.py │ │ ├── code_measure.inc │ │ ├── function.py │ │ ├── parse.py │ │ ├── readparamgen.py │ │ └── result_error.py ├── dcdc-gen │ ├── Makefile │ ├── README.md │ ├── test.json │ ├── tools │ │ └── dcdc-gen.py │ └── verilog │ │ ├── DCDC_CONV2to1.v │ │ ├── DCDC_HUNIT_CONV2to1.v │ │ └── DCDC_TOP.template.v ├── ldo-gen │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── models │ │ ├── gf12lp_9T_model.json │ │ ├── gf12lp_model.json │ │ ├── gfbicmos8hp_model.json │ │ └── tsmc65lp_model.json │ ├── test.json │ ├── tools │ │ ├── ldo_gen.py │ │ ├── ldo_model.py │ │ ├── ldo_model_verilog_gen.py │ │ └── supported_inputs.json │ └── verilog │ │ ├── LDO_CONTROLLER_TEMPLATE.v │ │ └── LDO_TEMPLATE.v ├── memory-gen │ ├── MemGen.py │ ├── README.md │ ├── SRAM │ │ ├── __init__.py │ │ ├── bitcell_array.py │ │ ├── bitcellprops.py │ │ ├── cellprops.py │ │ ├── col_periphery.py │ │ ├── row_periphery.py │ │ ├── sram_arch.py │ │ ├── sram_model.py │ │ └── sram_top.py │ ├── deo │ │ ├── __init__.py │ │ ├── auxcell_char.py │ │ ├── deo.py │ │ └── sram_char.py │ ├── globals │ │ ├── __init__.py │ │ ├── configs │ │ │ ├── mem_arch.yaml │ │ │ ├── mem_config.yaml │ │ │ └── verified_tools.yaml │ │ ├── global_utils.py │ │ ├── mem_arch_config_parser.py │ │ └── toolenv_check.py │ ├── macro_gen │ │ ├── __init__.py │ │ ├── apr │ │ │ ├── __init__.py │ │ │ ├── floorplan.py │ │ │ ├── power_plan.py │ │ │ └── setup.py │ │ ├── lef_parser.py │ │ ├── macro_gen.py │ │ ├── synthesis │ │ │ ├── __init__.py │ │ │ └── synth_constraints.py │ │ └── verilog_gen │ │ │ ├── __init__.py │ │ │ ├── bank_verilog_gen.py │ │ │ ├── bitcell_array_verilog.py │ │ │ ├── col_periphery_verilog.py │ │ │ ├── contol_unit_verilog.py │ │ │ ├── multi_bank_verilog_gen.py │ │ │ └── row_periphery_verilog.py │ └── tech_collaterals │ │ └── collateral--12nm--gf--lp.yaml ├── pll-gen │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── ble_design_params.json │ ├── bleach.mk │ ├── formats │ │ ├── :run │ │ ├── BLE │ │ │ ├── ble_dco │ │ │ │ ├── dco_CC_se_3st.v │ │ │ │ ├── dco_FC_se2_half.v │ │ │ │ └── form_ble_dco.v │ │ │ ├── ble_pll_top │ │ │ │ ├── FUNCTIONS.v │ │ │ │ ├── dltdc_lut_lib.sv │ │ │ │ ├── form_ble_pll_top.sv │ │ │ │ ├── form_pll_controller.sv │ │ │ │ ├── form_tstdc_controller.sv │ │ │ │ └── ssc_generator.v │ │ │ ├── ble_top │ │ │ │ ├── FREQ_DIV.v │ │ │ │ ├── FUNCTIONS.v │ │ │ │ ├── GFSK_CTRL_V2.v │ │ │ │ ├── PLL_CONTROLLER.v │ │ │ │ ├── PLL_CONTROLLER_TDC_COUNTER.v │ │ │ │ ├── SCPA_Final.v │ │ │ │ ├── SCPA_with_Decoupling_Cap.v │ │ │ │ ├── SSC_GENERATOR.v │ │ │ │ ├── TDC_COUNTER.v │ │ │ │ ├── TOP_FSM_V1.sv │ │ │ │ ├── ble_top.sv │ │ │ │ ├── ble_top_spi_slave.sv │ │ │ │ ├── ble_top_spi_wrap.sv │ │ │ │ ├── bu_pll6.v │ │ │ │ ├── dco_CC.v │ │ │ │ ├── dco_FC.v │ │ │ │ ├── synth_pll_dco_interp.v │ │ │ │ └── synth_pll_dco_outbuff.v │ │ │ ├── form_ble_dco.v │ │ │ └── tstdc_counter │ │ │ │ ├── form_dltdc_v3.sv │ │ │ │ ├── form_tstdc_counter.sv │ │ │ │ └── lpdtc_v2.sv │ │ ├── dummy_hspicesim.mk │ │ ├── dummy_pex_hspicesim.mk │ │ ├── form_PDpll_always_source.tcl │ │ ├── form_TB_PLL_CONTROLLER_TDC_COUNTER.sv │ │ ├── form_analog_core.v │ │ ├── form_dco_model_noise.v │ │ ├── form_dco_v2.v │ │ ├── form_dump_irun.tcl │ │ ├── form_ffdco.v │ │ ├── form_flist.f │ │ ├── form_flist_beh.f │ │ ├── form_form_Makefile │ │ ├── form_hspicesim.mk │ │ ├── form_model.json │ │ ├── form_pex_hspicesim.mk │ │ ├── form_pex_model.json │ │ ├── form_pll_PD.v │ │ ├── form_pll_controller_v2.sv │ │ ├── form_pll_dc.filelist.tcl │ │ ├── form_pll_include.mk │ │ ├── form_pll_top_v2.sv │ │ ├── form_run │ │ ├── form_spec_out.json │ │ ├── form_synth_pll.v │ │ ├── form_tb_pll_top.sv │ │ ├── form_tdc_counter_v2.sv │ │ └── tdc_counter_v2.sv │ ├── pll_pex_model_gf12lp.json │ ├── pll_pex_model_gf12lp_FCv2.json │ ├── publicModel │ │ ├── gf12lp_pll_model.json │ │ └── tsmc65lp_pll_model.json │ ├── pymodules │ │ ├── .gitignore │ │ ├── modeling.py │ │ ├── preparations.py │ │ ├── run_digital_flow.py │ │ ├── run_pex_flow.py │ │ ├── run_pex_sim.py │ │ ├── run_pre_sim.py │ │ └── txt_mds.py │ ├── std_cell_names.json │ ├── std_cell_names_public.json │ ├── test_alpha12.json │ ├── test_beta65.json │ ├── tools │ │ ├── BLE_GEN.py │ │ ├── BLE_PLL_GEN.py │ │ ├── DCO_TO_PREP.py │ │ ├── MDL_GEN_Beta.py │ │ ├── MDL_GEN_Beta_KBR.py │ │ └── PLL_GEN_Beta.py │ ├── verilog_sim │ │ ├── :run │ │ ├── :run_beh │ │ ├── dco_model_noise.v │ │ ├── differential_dco │ │ │ ├── :run │ │ │ ├── INCA_libs │ │ │ │ ├── .history.lock │ │ │ │ ├── history │ │ │ │ ├── irun.lnx8664.15.20.nc │ │ │ │ │ ├── .nclib.lock │ │ │ │ │ ├── .ncrun.lock │ │ │ │ │ ├── .ncv.lock │ │ │ │ │ ├── .timestamp.ts │ │ │ │ │ ├── OVMHOME │ │ │ │ │ ├── UVMHOME │ │ │ │ │ ├── bind.lst.lnx8664 │ │ │ │ │ ├── cdsrun.lib │ │ │ │ │ ├── files.ts │ │ │ │ │ ├── grandtraverse.eecs.umich.edu_27473 │ │ │ │ │ │ ├── irun.args │ │ │ │ │ │ ├── ncsim.args │ │ │ │ │ │ └── ncsim.env │ │ │ │ │ ├── hdlrun.var │ │ │ │ │ ├── irun.args │ │ │ │ │ ├── ncelab.args │ │ │ │ │ ├── ncelab.env │ │ │ │ │ ├── ncelab.hrd │ │ │ │ │ ├── ncvlog.args │ │ │ │ │ ├── ncvlog.env │ │ │ │ │ ├── ncvlog.files │ │ │ │ │ └── ncvlog.hrd │ │ │ │ ├── irun.nc │ │ │ │ └── worklib │ │ │ │ │ ├── .cdsvmod │ │ │ │ │ ├── .inca.db.150.lnx8664 │ │ │ │ │ ├── cdsinfo.tag │ │ │ │ │ └── inca.lnx8664.150.pak │ │ │ ├── dump_irun.tcl │ │ │ ├── flist.f │ │ │ ├── irun.history │ │ │ ├── irun.key │ │ │ ├── irun_comp.history │ │ │ ├── irun_run.history │ │ │ ├── pll_lock_report.txt │ │ │ ├── signals │ │ │ │ ├── SIG_C_controller.svwf │ │ │ │ ├── SIG_PLL_CNTRL_TDC_CNTR_top.svwf │ │ │ │ ├── SIG_TDC_to_DCO_CCW.svwf │ │ │ │ └── SIG_phase_ramp.svwf │ │ │ ├── tb │ │ │ │ ├── TB_PLL_CONTROLLER_TDC_COUNTER.sv │ │ │ │ └── TB_synth_pll.v │ │ │ └── verilog │ │ │ │ ├── ANALOG_CORE.v │ │ │ │ ├── DCO_MODEL.v │ │ │ │ ├── FUNCTIONS.v │ │ │ │ ├── PLL_CONTROLLER.v │ │ │ │ ├── PLL_CONTROLLER_TDC_COUNTER.v │ │ │ │ ├── SSC_GENERATOR.v │ │ │ │ ├── TB_synth_pll.v │ │ │ │ ├── TDC_COUNTER.v │ │ │ │ ├── bu_dco_8stg.v │ │ │ │ ├── dco_8stg.v │ │ │ │ ├── dco_CC.v │ │ │ │ ├── dco_FC.v │ │ │ │ ├── synth_dco.v │ │ │ │ ├── synth_pll.v │ │ │ │ ├── synth_pll_dco_interp.v │ │ │ │ └── synth_pll_dco_outbuff.v │ │ ├── dump_irun.tcl │ │ ├── flist_beh.f │ │ ├── pllClkfreq.csv │ │ ├── single_ended_dco │ │ │ ├── :run │ │ │ ├── INCA_libs │ │ │ │ ├── .history.lock │ │ │ │ ├── history │ │ │ │ ├── irun.lnx8664.15.20.nc │ │ │ │ │ ├── .nclib.lock │ │ │ │ │ ├── .ncrun.lock │ │ │ │ │ ├── .ncv.lock │ │ │ │ │ ├── .timestamp.ts │ │ │ │ │ ├── OVMHOME │ │ │ │ │ ├── UVMHOME │ │ │ │ │ ├── bind.lst.lnx8664 │ │ │ │ │ ├── cdsrun.lib │ │ │ │ │ ├── files.ts │ │ │ │ │ ├── hdl.var │ │ │ │ │ ├── hdlrun.var │ │ │ │ │ ├── irun.args │ │ │ │ │ ├── ncelab.args │ │ │ │ │ ├── ncelab.env │ │ │ │ │ ├── ncelab.hrd │ │ │ │ │ ├── ncsim.args │ │ │ │ │ ├── ncsim.env │ │ │ │ │ ├── ncsim_restart.args │ │ │ │ │ ├── ncsim_restart.env │ │ │ │ │ ├── ncvlog.args │ │ │ │ │ ├── ncvlog.env │ │ │ │ │ ├── ncvlog.files │ │ │ │ │ └── ncvlog.hrd │ │ │ │ ├── irun.nc │ │ │ │ └── worklib │ │ │ │ │ ├── .cdsvmod │ │ │ │ │ ├── .inca.db.150.lnx8664 │ │ │ │ │ ├── cdsinfo.tag │ │ │ │ │ └── inca.lnx8664.150.pak │ │ │ ├── dump_irun.tcl │ │ │ ├── flist.f │ │ │ ├── irun.history │ │ │ ├── irun.key │ │ │ ├── irun_comp.history │ │ │ ├── irun_run.history │ │ │ ├── pll_lock_report.txt │ │ │ ├── verilog │ │ │ │ ├── DCO_MODEL.v │ │ │ │ ├── analog_core.v │ │ │ │ ├── dco_model.v │ │ │ │ ├── dco_model_noise.v │ │ │ │ ├── dco_model_therm_test.v │ │ │ │ ├── functions.v │ │ │ │ ├── pll_controller.sv │ │ │ │ ├── pll_controller_tdc_counter.sv │ │ │ │ ├── pll_fsm_define.sv │ │ │ │ ├── ssc_generator.v │ │ │ │ ├── tb_pll_controller.sv │ │ │ │ ├── tb_pll_controller_tdc_counter.sv │ │ │ │ └── tdc_counter.v │ │ │ └── xrun.key │ │ ├── two_step_tdc │ │ │ ├── tstdc_pre_dltdc │ │ │ │ ├── :run │ │ │ │ ├── dump_irun.tcl │ │ │ │ ├── flist.f │ │ │ │ └── verilog │ │ │ │ │ ├── DCO_MODEL.v │ │ │ │ │ ├── DFF.v │ │ │ │ │ ├── analog_core.v │ │ │ │ │ ├── bu_dltdc_model.sv │ │ │ │ │ ├── dco_CC_se.v │ │ │ │ │ ├── dco_FC_se2.v │ │ │ │ │ ├── dco_model.v │ │ │ │ │ ├── dco_model_noise.v │ │ │ │ │ ├── dco_model_therm_test.v │ │ │ │ │ ├── dltdc_model.sv │ │ │ │ │ ├── dltdc_v2.sv │ │ │ │ │ ├── dltdc_v2_for_synth.sv │ │ │ │ │ ├── functions.v │ │ │ │ │ ├── pll_controller.sv │ │ │ │ │ ├── pll_controller_tdc_counter.sv │ │ │ │ │ ├── pll_fsm_define.sv │ │ │ │ │ ├── pre_dltdc.sv │ │ │ │ │ ├── ssc_generator.v │ │ │ │ │ ├── tb_dltdc_model.sv │ │ │ │ │ ├── tb_pll_controller.sv │ │ │ │ │ ├── tb_pll_controller_tdc_counter.sv │ │ │ │ │ ├── tb_tstdc_counter.sv │ │ │ │ │ └── tstdc_counter.v │ │ │ └── tstdc_top │ │ │ │ ├── :run │ │ │ │ ├── dltdc_dump_irun.tcl │ │ │ │ ├── dltdc_flist.f │ │ │ │ ├── dump_irun.tcl │ │ │ │ ├── flist.f │ │ │ │ ├── irun.key │ │ │ │ └── verilog │ │ │ │ ├── DCO_MODEL.v │ │ │ │ ├── analog_core.v │ │ │ │ ├── bu_dltdc_model.sv │ │ │ │ ├── dco_model.v │ │ │ │ ├── dco_model_noise.v │ │ │ │ ├── dco_model_therm_test.v │ │ │ │ ├── dltdc_model.sv │ │ │ │ ├── functions.v │ │ │ │ ├── pll_controller.sv │ │ │ │ ├── pll_controller_tdc_counter.sv │ │ │ │ ├── pll_fsm_define.sv │ │ │ │ ├── pre_dltdc.sv │ │ │ │ ├── ssc_generator.v │ │ │ │ ├── tb_dltdc_model.sv │ │ │ │ ├── tb_pll_controller.sv │ │ │ │ ├── tb_pll_controller_tdc_counter.sv │ │ │ │ ├── tb_tstdc_counter.sv │ │ │ │ └── tstdc_counter.v │ │ └── verilog │ │ │ ├── analog_core.v │ │ │ ├── dco_model_noise.v │ │ │ ├── functions.v │ │ │ ├── pll7.sv │ │ │ ├── pll_controller.sv │ │ │ ├── ssc_generator.v │ │ │ ├── tb_pll_top.sv │ │ │ └── tdc_counter.sv │ └── verilogs │ │ ├── ANALOG_CORE.v │ │ ├── DCO_MODEL.v │ │ ├── FUNCTIONS.v │ │ ├── PLL_CONTROLLER.v │ │ ├── PLL_CONTROLLER_TDC_COUNTER.v │ │ ├── SSC_GENERATOR.v │ │ ├── TB_synth_pll.v │ │ ├── TDC_COUNTER.v │ │ ├── bu_dco_8stg.v │ │ ├── dco_10drv_10cc_30fc_18stg.v │ │ ├── dco_8stg.v │ │ ├── dco_CC.v │ │ ├── dco_CC_se.v │ │ ├── dco_CC_se_3st.v │ │ ├── dco_FC.v │ │ ├── dco_FC_se.v │ │ ├── dco_FC_se2.v │ │ ├── dco_FC_se2_half.v │ │ ├── dco_FC_se_half.v │ │ ├── pll_controller_v2.sv │ │ ├── ssc_generator.v │ │ ├── synth_dco.v │ │ ├── synth_pll_dco_interp_gf12lp.v │ │ ├── synth_pll_dco_interp_tsmc65lp.v │ │ ├── synth_pll_dco_outbuff_gf12lp.v │ │ └── synth_pll_dco_outbuff_tsmc65lp.v ├── scpa-gen │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── bu_test.json │ ├── models │ │ └── tsmc65lp_model.json │ ├── test.json │ ├── tools │ │ ├── ldo_gen.py │ │ ├── ldo_model.py │ │ ├── ldo_model_verilog_gen.py │ │ ├── scpa_gen.py │ │ ├── scpa_gen_pex.py │ │ ├── scpa_model.py │ │ └── supported_inputs.json │ └── verilog │ │ ├── CLK_DRIVER.v │ │ ├── SCPA.v │ │ └── SCPA_MIMCAP_new.v └── temp-sense-gen │ ├── .gitignore │ ├── golden_error_opt.csv │ ├── makefile │ ├── models │ └── tsmc65lp.model_tempsense │ ├── readme.md │ ├── search_result.csv │ ├── src │ ├── TEMP_ANALOG_hv.nl.v │ ├── TEMP_ANALOG_hv.v │ ├── TEMP_ANALOG_lv.nl.v │ ├── TEMP_ANALOG_lv.v │ ├── TEMP_AUTO_def.v │ ├── counter.v │ ├── counter_generic.v │ └── tempsenseInst.v │ ├── test.json │ ├── tools │ ├── TEMP_netlist.py │ ├── data_collection.py │ ├── function.py │ ├── parse.py │ ├── readparamgen.py │ ├── result.py │ ├── result_error.py │ ├── run_sim_top.py │ └── temp-sense-gen.py │ └── work │ └── .gitignore ├── soc ├── README.md ├── config │ └── soc_model_config.json ├── docs │ ├── flow.jpg │ └── platform_config.png ├── python │ ├── .nfs0000000000b80a310000210c │ ├── ML_model.py │ ├── Verilog_Parser.py │ ├── analogGen.py │ ├── checkDB.py │ ├── clean.py │ ├── closedLoop.py │ ├── connectionGen.py │ ├── fastAnalogGen.py │ ├── fastSoc.py │ ├── hierarchy.py │ ├── hierarchy_checker.py │ ├── jsonXmlGenerator.py │ ├── modifyDBFiles.py │ ├── power_area_estimator │ │ ├── algebric_model_evaluator.py │ │ ├── equation_solver.py │ │ ├── ml_regression_merged.py │ │ ├── modifying_csv_columns_ml.py │ │ ├── wrapper.py │ │ └── y_interception.py │ ├── rtlXmlGenerator.py │ ├── soc.py │ └── synthesis.py └── rubi │ ├── Add_Components_Parameters.rb │ ├── Define_SoCParameters.rb │ ├── Status_utilities.rb │ ├── VE_utilities.rb │ ├── clean.rb │ ├── convert_json.rb │ ├── generate.rb │ ├── parse_json.rb │ └── report.rb └── tests ├── demo-feb-2021 ├── Makefile └── design_ldo.json ├── demo-jan-2020 ├── Makefile ├── design_ldo.json ├── design_ldo_pll.json └── design_ldo_pll_mem.json ├── pll ├── Makefile └── design.json ├── power_area_model └── Makefile ├── tape_out ├── Makefile └── design.json └── temp_sens ├── Makefile └── design_temp_sens.json /.gitignore: -------------------------------------------------------------------------------- 1 | generators/clkdiv/work 2 | 3 | 4 | 5 | 6 | #### CADRE FLOW FILES FOLLOW 7 | ##################################### 8 | 9 | # Design generated directories 10 | checkDesign/ 11 | checkPoints/ 12 | export/ 13 | extLogDir/ 14 | logs/ 15 | ref_data/ 16 | reports/ 17 | results/ 18 | vpath/ 19 | *_dclib/ 20 | *_mwlib/ 21 | *_oalib/ 22 | *.htmreports/ 23 | *.htm/ 24 | 25 | /memory/ 26 | 27 | # Generated files 28 | tool_versions.txt 29 | doc_versions.txt 30 | sverilog_filelist_dc.txt 31 | ucli.key 32 | sdfAnnotateInfo 33 | *.cmd* 34 | *.log* 35 | *.lib_sh5p1cm 36 | *.rpt 37 | *.rpt.old 38 | *.dat 39 | .back 40 | *.vcd 41 | *.vpd 42 | *.antenna.lef 43 | *.gds.gz 44 | *.spef.gz 45 | 46 | # Foundation Flow generated scripts 47 | generated/ 48 | 49 | # Sublime Text 50 | *.sublime-project 51 | *.sublime-workspace 52 | 53 | # python 54 | __pycache__/ 55 | *.pyc 56 | 57 | # Vim 58 | *.swp 59 | *.swo 60 | *.swn 61 | 62 | # Gedit 63 | *~ 64 | 65 | # svn 66 | .svn/ 67 | .metadata/ 68 | 69 | # Virtuoso 70 | .cadence/ 71 | *.reflib 72 | cds.lib 73 | display.drf 74 | display.drf.orig 75 | rc_model.bin 76 | 77 | # Calibre 78 | .cgidrcdb 79 | DVEfiles 80 | 81 | # bsg_riscv will be created with symlinks to the dreslinskilab group dir 82 | bsg_riscv 83 | 84 | # VCS 85 | vcs_initreg_instance_name.txt 86 | vcs_initreg_random_value.txt 87 | 88 | # Rocket-specific VCS sim generated files 89 | dramsim2_ini 90 | 91 | 92 | 93 | snapshot_img_floorplan* 94 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "private"] 2 | path = private 3 | url = git@github.com:idea-fasoc/fasoc_private.git 4 | branch = master 5 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 CADRE - Michigan 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | check_env: 2 | python check_env.py -------------------------------------------------------------------------------- /config/platform_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": 0.1, 3 | "synthTool": "dc", 4 | "simTool": "hspice", 5 | "extractionTool": "calibre", 6 | "netlistTool": "calibredrv", 7 | "calibreRules": "/net/gaylord/l/yaswanth/Research/LDO_Automation/extraction/ruleFiles", 8 | "socratesInstall": "/afs/eecs.umich.edu/cadre/projects/fasoc/soft/arm-socrates-1.4.0", 9 | "socrates_DRC_config": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/socrates_DRC_config", 10 | "platforms": { 11 | "tsmc65lp": { 12 | "nominal_voltage": 1.2, 13 | "aux_lib": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/aux_lib_tsmc65lp", 14 | "model_lib": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/model_tsmc65", 15 | "calibreRules": "/net/gaylord/l/yaswanth/Research/LDO_Automation/extraction/ruleFiles", 16 | "hspiceModels": "/afs/eecs.umich.edu/kits/TSMC/CRN65LP/2013.03/rf1p9m6x2z0u2ff2p5v/models/hspice", 17 | "database": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database_65lp", 18 | "socModel": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/integration_tool_model" 19 | }, 20 | "gfbicmos8hp": { 21 | "nominal_voltage": 1.2, 22 | "aux_lib": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/aux_lib_8hp", 23 | "model_lib": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/model_8hp", 24 | "calibreRules": "/net/gaylord/l/yaswanth/Research/forTutu/ruleFiles_8hp", 25 | "hspiceModels": "/afs/eecs.umich.edu/kits/GF/130HPSIGE-8HP/V1.8_0.1HP/Models/HSPICE/models" 26 | }, 27 | "gf12lp": { 28 | "nominal_voltage": 0.8, 29 | "aux_lib": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/aux_lib_gf12lp_10p5_track", 30 | "model_lib": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/model_12lp_10p5_track", 31 | "calibreRules": "/net/gaylord/l/yaswanth/Research/forTutu/ruleFiles_12lp", 32 | "hspiceModels": "/afs/eecs.umich.edu/kits/GF/12LP/V1.0_2.1/Models/HSPICE/models", 33 | "database": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database_12lp" 34 | } 35 | } 36 | } 37 | -------------------------------------------------------------------------------- /database/Makefile: -------------------------------------------------------------------------------- 1 | database: 2 | ./insert_json_cloud.py --filename ./adcInst.json -------------------------------------------------------------------------------- /database/adcInst.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance_name": "adcInst", 3 | "generator": "adc-gen", 4 | "specifications": { 5 | "fsampling": 1000000, 6 | "target enob": 7.4, 7 | "optimization": "area", 8 | "model": "modelfile.csv" 9 | }, 10 | "results": { 11 | "platform": "gf12lp", 12 | "area": 18269, 13 | "enob": 7.652437, 14 | "power": 1.7095e-06 15 | } 16 | } -------------------------------------------------------------------------------- /database/connect_cloud.py: -------------------------------------------------------------------------------- 1 | from pymongo import MongoClient 2 | 3 | #class to connect to cloud mongodb 4 | class Connect(object): 5 | @staticmethod 6 | def get_connection(): 7 | return MongoClient("mongodb+srv://admin:admin@clusterfasoc.hrzi9.mongodb.net/Fasoc?retryWrites=true&w=majority") 8 | -------------------------------------------------------------------------------- /database/readme.md: -------------------------------------------------------------------------------- 1 | # FASoC Database 2 | 3 | ## Populate DB with json files 4 | Fasoc Database is a MongoDB atlas cloud instance. 5 | In order to insert/populate new records into the DB, please follow the steps below: 6 | 7 | Run insert_json_cloud.py by writing `./insert_json_cloud.py` in the terminal while you have navigated to `fasoc/database`. `--filename` indicates the argument for the path to the json file to insert in the DB. Please see the Makefile as an example to run. 8 | -------------------------------------------------------------------------------- /doc/Cadre Flow Guide.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/doc/Cadre Flow Guide.pdf -------------------------------------------------------------------------------- /doc/SoC Integrator Walkthrough.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/doc/SoC Integrator Walkthrough.pdf -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/comp_nand.cdl: -------------------------------------------------------------------------------- 1 | .subckt comp_nand_ver0 clk_sar vinn vinp outn outp vdd vnw vpw vss 2 | xi3 outp vdd vnw vpw vss net10 INV_X0P6N_A10P5PP84TR_C14 3 | xi2 outn vdd vnw vpw vss net5 INV_X0P6N_A10P5PP84TR_C14 4 | xi1 net12 vdd vnw vpw vss op INV_X0P6N_A10P5PP84TR_C14 5 | xi0 net11 vdd vnw vpw vss on INV_X0P6N_A10P5PP84TR_C14 6 | xi5 op vdd vnw vpw vss on clk_sar vinn NAND3_X2N_A10P5PP84TR_C14 7 | xi4 on vdd vnw vpw vss op clk_sar vinp NAND3_X2N_A10P5PP84TR_C14 8 | xi7 net5 vdd vnw vpw vss net12 net10 NOR2_X2N_A10P5PP84TR_C14 9 | xi6 net10 vdd vnw vpw vss net11 net5 NOR2_X2N_A10P5PP84TR_C14 10 | 11 | .ends comp_nand_ver0 12 | 13 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/comp_nand.v: -------------------------------------------------------------------------------- 1 | module comp_nand_ver0 ( input clk_sar, 2 | input vinn, 3 | input vinp, 4 | output outn, 5 | output outp); 6 | 7 | //input vinp; 8 | //input vinn; 9 | //input clk_sar; 10 | //output outp; 11 | //output outn; 12 | 13 | wire net10, net5, net12, net11, op, on; 14 | 15 | INV_X0P6N_A10P5PP84TR_C14 i3 (.Y(outp), .A(net10)); 16 | INV_X0P6N_A10P5PP84TR_C14 i2 (.Y(outn), .A(net5)); 17 | 18 | INV_X0P6N_A10P5PP84TR_C14 i1 (.Y(net12), .A(op)); 19 | INV_X0P6N_A10P5PP84TR_C14 i0 (.Y(net11), .A(on)); 20 | 21 | 22 | NAND3_X2N_A10P5PP84TR_C14 i5 (.Y(op), .A(on), .B(clk_sar), .C(vinn)); 23 | NAND3_X2N_A10P5PP84TR_C14 i4 (.Y(on), .A(op), .B(clk_sar), .C(vinp)); 24 | 25 | NOR2_X2N_A10P5PP84TR_C14 i7 (.Y(net5), .A(net12), .B(net10)); 26 | NOR2_X2N_A10P5PP84TR_C14 i6 (.Y(net10), .A(net11), .B(net5)); 27 | 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/dac: -------------------------------------------------------------------------------- 1 | `include "constants.vams" 2 | `include "disciplines.vams" 3 | 4 | module dac(out, in, clk); 5 | parameter integer bits = @NBIT from [1:24]; // resolution (bits) 6 | parameter real vmin = 0.0; // minimum input voltage (V) 7 | parameter real vmax = pow(2,@NBIT) from (vmin:inf); // maximum input voltage (V) 8 | parameter real td = 0; // delay from clock edge to output (s) 9 | parameter real tt = 0; // transition time of output (s) 10 | parameter real vdd = 0.8; // voltage level of logic 0.8 (V) 11 | parameter real vss = 0; // voltage level of logic 0 (V) 12 | parameter real thresh = (vdd+vss)/2; // logic threshold level (V) 13 | parameter integer dir = +1 from [-1:1] exclude 0; 14 | // 1 for trigger on rising edge 15 | // -1 for falling 16 | localparam real fullscale = vmax - vmin; 17 | 18 | output out; 19 | input [0:bits-1] in; 20 | input clk; 21 | voltage out, clk; 22 | voltage [0:bits-1] in; 23 | real aout; 24 | integer weight; 25 | genvar i; 26 | 27 | analog begin 28 | @(cross(V(clk) - thresh, dir) or initial_step) begin 29 | aout = 0; 30 | weight = 2; 31 | for (i = bits - 1; i >= 0; i = i - 1) begin 32 | if (V(in[i]) > thresh) begin 33 | aout = aout + fullscale/weight; 34 | end 35 | weight = weight*2; 36 | end 37 | end 38 | V(out) <+ transition(aout + vmin, td, tt); 39 | end 40 | endmodule 41 | 42 | module ainv (in, out, dd); 43 | 44 | output out; voltage out; 45 | input in; voltage in; 46 | input dd; voltage dd; 47 | parameter real td = 1n from [0:inf); // delay to start of output transition 48 | parameter real tt = 1n from [0:inf); // transition time of output signals 49 | 50 | integer lout; 51 | 52 | analog begin 53 | // make sure simulator sees the threshold crossing 54 | @(cross(V(in) - V(dd)/2)) 55 | ; 56 | 57 | // compute the logical value of the output 58 | if (V(in) > V(dd)/2) 59 | lout = 0; 60 | else 61 | lout = 1; 62 | 63 | // create an analog version of logical output 64 | V(out) <+ V(dd)*transition(lout, td, tt); 65 | end 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/sar: -------------------------------------------------------------------------------- 1 | xsar_logic 2 | + @value 3 | + @result_out 4 | + clk_sar en sample out_n clk_comp 5 | + vdd vnw vpw vss 6 | + sar_logic 7 | 8 | xcdac 9 | + vcm_p vcm_n vin_p vin_n vrefh vrefl vtop_p vtop_n sample 10 | + @value 11 | + vdd vnw vpw vss 12 | + cdac 13 | 14 | xcomp clk_comp vtop_n vtop_p out_n out_p vdd vnw vpw vss comp_nand_ver0 15 | 16 | 17 | xdac dac_out @result_out enb dac 18 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/sar.pex: -------------------------------------------------------------------------------- 1 | xsar 2 | +en 3 | +clk_sar 4 | +vss 5 | +vdd 6 | +@result_out 7 | +vrefh 8 | +vin_p 9 | +vcm 10 | +vrefl 11 | +vin_n 12 | +sar 13 | 14 | xdac dac_out @result_out enb dac 15 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/gf12lp/sar.v: -------------------------------------------------------------------------------- 1 | 2 | module sar( input clk, 3 | input en, 4 | input vin_p, 5 | input vin_n, 6 | output [@NBIT-1:0] result, 7 | inout vcm, 8 | input vrefh, 9 | input vrefl); 10 | //ANSI sytle port definition is needed to write out sverilog 11 | /////////////////////////////////// 12 | ////////// Digital inputs////////// 13 | /////////////////////////////////// 14 | 15 | //input clk; // sar clock input 16 | //input en; // sar control signal // en=0 : sample phase. minimum 1 cycle. // en=1 : conversion phase. minimum WIDTH+2 cycles are needed. 17 | 18 | //input vin_p; // sar analog positive input 19 | //input vin_n; // sar analog negative input (Differential config. : connect negative input / Single-ended config. : connect vcm) 20 | 21 | //output [@NBIT-1:0] result; // ADC output 22 | 23 | /////////////////////////////////// 24 | ////////// Analog inputs ////////// 25 | /////////////////////////////////// 26 | 27 | //inout vcm; // common mode reference input. VDD/2 should be connected 28 | //input vrefh; 29 | //input vrefl; 30 | /////////////////////////////////// 31 | ////////// Internal wires ////////// 32 | /////////////////////////////////// 33 | 34 | wire vtop_p, vtop_n; // cdac output => comparator positive, negative input 35 | wire sample; // input is sampled when sample=1 36 | wire outp, outn; // comparator output 37 | wire clk_comp; // comparator clk 38 | 39 | wire [@NBIT-1:0] value; //CDAC cap control signal 40 | //This part only works with 8 bit 41 | sar_logic isar_logic( 42 | .clk_sar(clk), 43 | .en(en), 44 | .sample(sample), 45 | .value(value), 46 | .result_out(result), 47 | .cmp(outn), 48 | .cmp_clk(clk_comp) 49 | ); 50 | 51 | cdac icdac( 52 | .vin_p(vin_p), 53 | .vin_n(vin_n), 54 | .vrefh(vrefh), 55 | .vrefl(vrefl), 56 | .vcm_p(vcm), 57 | .vcm_n(vcm), 58 | .vtop_n(vtop_n), 59 | .vtop_p(vtop_p), 60 | .sample(sample), 61 | .value(value) 62 | ); 63 | 64 | comp_nand_ver0 icomparator( 65 | .clk_sar(clk_comp), 66 | .vinn(vtop_n), 67 | .vinp(vtop_p), 68 | .outp(outp), 69 | .outn(outn) 70 | ); 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/comp_nand.cdl: -------------------------------------------------------------------------------- 1 | ** Library name: SYN_ANALOG 2 | ** Cell name: COMP_NAND_VER0 3 | ** View name: schematic 4 | .subckt comp_nand_ver0 clk_sar vinn vinp outn outp vdd vss 5 | xi11 outp vdd vdd vss vss net018 INV_X0P5B_A9TR 6 | xi10 outn vdd vdd vss vss net024 INV_X0P5B_A9TR 7 | xi7 net026 vdd vdd vss vss op INV_X0P5B_A9TR 8 | xi4 net027 vdd vdd vss vss on INV_X0P5B_A9TR 9 | xi1 op vdd vdd vss vss on clk_sar vinn NAND3_X2A_A9TR 10 | xi0 on vdd vdd vss vss op clk_sar vinp NAND3_X2A_A9TR 11 | xi6 net024 vdd vdd vss vss net018 net026 NOR2_X0P5A_A9TR 12 | xi5 net018 vdd vdd vss vss net027 net024 NOR2_X0P5A_A9TR 13 | .ends comp_nand_ver0 14 | ** End of subcircuit definition. 15 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/comp_nand.v: -------------------------------------------------------------------------------- 1 | module comp_nand (clk_sar, vinn, vinp, outn, outp); //vdd,vss power domain 2 | 3 | input vinp; 4 | input vinn; 5 | input clk_sar; 6 | 7 | output outp; 8 | output outn; 9 | 10 | wire net018, net024, net026, net027, op, on; 11 | 12 | INV_X0P5B_A9TR i11 (.Y(outp), .A(net018)); 13 | INV_X0P5B_A9TR i10 (.Y(outn), .A(net024)); 14 | 15 | INV_X0P5B_A9TR i7 (.Y(net026), .A(op)); 16 | INV_X0P5B_A9TR i4 (.Y(net027), .A(on)); 17 | 18 | 19 | NAND3_X2A_A9TR i1 (.Y(op), .A(on), .B(clk_sar), .C(vinn)); 20 | NAND3_X2A_A9TR i0 (.Y(on), .A(op), .B(clk_sar), .C(vinp)); 21 | 22 | NOR2_X0P5A_A9TR i6 (.Y(net024), .A(net018), .B(net026)); 23 | NOR2_X0P5A_A9TR i5 (.Y(net018), .A(net027), .B(net024)); 24 | 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/dac: -------------------------------------------------------------------------------- 1 | `include "constants.vams" 2 | `include "disciplines.vams" 3 | 4 | module dac(out, in, clk); 5 | parameter integer bits = @NBIT from [1:24]; // resolution (bits) 6 | parameter real vmin = 0.0; // minimum input voltage (V) 7 | parameter real vmax = pow(2,@NBIT) from (vmin:inf); // maximum input voltage (V) 8 | parameter real td = 0; // delay from clock edge to output (s) 9 | parameter real tt = 0; // transition time of output (s) 10 | parameter real vdd = 1.0; // voltage level of logic 1 (V) 11 | parameter real vss = 0; // voltage level of logic 0 (V) 12 | parameter real thresh = (vdd+vss)/2; // logic threshold level (V) 13 | parameter integer dir = +1 from [-1:1] exclude 0; 14 | // 1 for trigger on rising edge 15 | // -1 for falling 16 | localparam real fullscale = vmax - vmin; 17 | 18 | output out; 19 | input [0:bits-1] in; 20 | input clk; 21 | voltage out, clk; 22 | voltage [0:bits-1] in; 23 | real aout; 24 | integer weight; 25 | genvar i; 26 | 27 | analog begin 28 | @(cross(V(clk) - thresh, dir) or initial_step) begin 29 | aout = 0; 30 | weight = 2; 31 | for (i = bits - 1; i >= 0; i = i - 1) begin 32 | if (V(in[i]) > thresh) begin 33 | aout = aout + fullscale/weight; 34 | end 35 | weight = weight*2; 36 | end 37 | end 38 | V(out) <+ transition(aout + vmin, td, tt); 39 | end 40 | endmodule 41 | 42 | module ainv (in, out, dd); 43 | 44 | output out; voltage out; 45 | input in; voltage in; 46 | input dd; voltage dd; 47 | parameter real td = 1n from [0:inf); // delay to start of output transition 48 | parameter real tt = 1n from [0:inf); // transition time of output signals 49 | 50 | integer lout; 51 | 52 | analog begin 53 | // make sure simulator sees the threshold crossing 54 | @(cross(V(in) - V(dd)/2)) 55 | ; 56 | 57 | // compute the logical value of the output 58 | if (V(in) > V(dd)/2) 59 | lout = 0; 60 | else 61 | lout = 1; 62 | 63 | // create an analog version of logical output 64 | V(out) <+ V(dd)*transition(lout, td, tt); 65 | end 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/sar: -------------------------------------------------------------------------------- 1 | xsar_logic 2 | + @value 3 | + @result_out 4 | + clk_sar en sample out_n clk_comp 5 | + vdd vss 6 | + sar_logic 7 | 8 | xcdac 9 | + vcm_p vcm_n vin_p vin_n vrefh vrefl vtop_p vtop_n sample 10 | + @value 11 | + vdd vss 12 | + cdac 13 | 14 | xcomp clk_comp vtop_n vtop_p out_n out_p vdd vss comp_nand_ver0 15 | 16 | 17 | xdac dac_out @result_out enb dac 18 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/sar.pex: -------------------------------------------------------------------------------- 1 | xsar 2 | +en 3 | +clk_sar 4 | +vss 5 | +vdd 6 | +@result_out 7 | +vrefh 8 | +vin_p 9 | +vcm 10 | +vrefl 11 | +vin_n 12 | +sar 13 | 14 | xdac dac_out @result_out enb dac 15 | -------------------------------------------------------------------------------- /generators/adc-gen/0_spice_template/tsmc65lp/sar.v: -------------------------------------------------------------------------------- 1 | 2 | module sar( input clk, // sar clock input 3 | input en, // sar control signal // en=0 : sample phase. minimum 1 cycle. // en=1 : conversion phase. minimum WIDTH+2 cycles are needed. 4 | input vinp, // sar analog positive input 5 | input vinn, // sar analog negative input (Differential config. : connect negative input / Single-ended config. : connect vcm) 6 | output [@NBIT-1:0] result, 7 | input vcm, // common mode reference input. VDD/2 should be connected 8 | input vrefh, 9 | input vrefl); 10 | 11 | /////////////////////////////////// 12 | ////////// Internal wires ////////// 13 | /////////////////////////////////// 14 | 15 | //wire vcmpp, vcmpn; // cdac output => comparator positive, negative input 16 | wire sample; // input is sampled when sample=1 17 | wire outp, outn; // comparator output 18 | wire comp_clk; // comparator clk 19 | wire vtop_n, vtop_p; 20 | wire [@NBIT-1:0] value; //CDAC cap control signal 21 | 22 | sar_logic isar_logic( 23 | .clk_sar(clk), 24 | .en(en), 25 | .sample(sample), 26 | .value(value), 27 | .result_out(result), 28 | .cmp(outn), 29 | .cmp_clk(comp_clk) 30 | ); 31 | 32 | cdac icdac( 33 | .vin_p(vinp), 34 | .vin_n(vinn), 35 | .vrefh(vrefh), 36 | .vrefl(vrefl), 37 | .vcm_p(vcm), 38 | .vcm_n(vcm), 39 | .vtop_n(vtop_n), 40 | .vtop_p(vtop_p), 41 | .sample(sample), 42 | .value(value) 43 | ); 44 | 45 | 46 | comp_nand icomparator( 47 | .clk_sar(comp_clk), 48 | .vinn(vtop_n), 49 | .vinp(vtop_p), 50 | .outp(outp), 51 | .outn(outn) 52 | ); 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /generators/adc-gen/adc_data.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance_name": "sar", 3 | "generator": "adc-gen", 4 | "specifications": { 5 | "fsampling": 1000000, 6 | "target enob": 7.4, 7 | "optimization":"area", 8 | "model" :"modelfile.csv" 9 | } 10 | } 11 | -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/comp_nand.cdl: -------------------------------------------------------------------------------- 1 | .subckt comp_nand_ver0 clk_sar vinn vinp outn outp vdd vnw vpw vss 2 | xi3 outp vdd vnw vpw vss net10 INV_X0P6N_A10P5PP84TR_C14 3 | xi2 outn vdd vnw vpw vss net5 INV_X0P6N_A10P5PP84TR_C14 4 | xi1 net12 vdd vnw vpw vss op INV_X0P6N_A10P5PP84TR_C14 5 | xi0 net11 vdd vnw vpw vss on INV_X0P6N_A10P5PP84TR_C14 6 | xi5 op vdd vnw vpw vss on clk_sar vinn NAND3_X2N_A10P5PP84TR_C14 7 | xi4 on vdd vnw vpw vss op clk_sar vinp NAND3_X2N_A10P5PP84TR_C14 8 | xi7 net5 vdd vnw vpw vss net12 net10 NOR2_X2N_A10P5PP84TR_C14 9 | xi6 net10 vdd vnw vpw vss net11 net5 NOR2_X2N_A10P5PP84TR_C14 10 | 11 | .ends comp_nand_ver0 12 | 13 | -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/comp_nand.v: -------------------------------------------------------------------------------- 1 | module comp_nand_ver0 (clk_sar, vinn, vinp, outn, outp, vdd, vnw, vpw, vss); //vdd,vss,vnw,vpw power domain 2 | 3 | input vinp; 4 | input vinn; 5 | input clk_sar; 6 | inout vdd; 7 | inout vnw; 8 | inout vpw; 9 | inout vss; 10 | output outp; 11 | output outn; 12 | 13 | wire net10, net5, net12, net11, op, on; 14 | 15 | INV_X0P6N_A10P5PP84TR_C14 i3 (.Y(outp), .A(net10), .VDD(vdd), .VNW(vnw), .VPW(vpw), .VSS(vss)); 16 | INV_X0P6N_A10P5PP84TR_C14 i2 (.Y(outn), .A(net5), .VDD(vdd), .VNW(vnw), .VPW(vpw), .VSS(vss)); 17 | 18 | INV_X0P6N_A10P5PP84TR_C14 i1 (.Y(net12), .A(op), .VDD(vdd), .VNW(vnw), .VPW(vpw), .VSS(vss)); 19 | INV_X0P6N_A10P5PP84TR_C14 i0 (.Y(net11), .A(on), .VDD(vdd), .VNW(vnw), .VPW(vpw), .VSS(vss)); 20 | 21 | 22 | NAND3_X2N_A10P5PP84TR_C14 i5 (.Y(op), .A(on), .B(clk_sar), .C(vinn), .VDD(vdd), .VNW(vnw), .VPW(vpw), .VSS(vss)); 23 | NAND3_X2N_A10P5PP84TR_C14 i4 (.Y(on), .A(op), .B(clk_sar), .C(vinp), .VDD(vdd), .VNW(vnw), .VPW(vpw), .VSS(vss)); 24 | 25 | NOR2_X2N_A10P5PP84TR_C14 i7 (.Y(net5), .A(net12), .B(net10), .VDD(vdd), .VNW(vnw), .VPW(vpw), .VSS(vss)); 26 | NOR2_X2N_A10P5PP84TR_C14 i6 (.Y(net10), .A(net11), .B(net5), .VDD(vdd), .VNW(vnw), .VPW(vpw), .VSS(vss)); 27 | 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/dac: -------------------------------------------------------------------------------- 1 | `include "constants.vams" 2 | `include "disciplines.vams" 3 | 4 | module dac(out, in, clk); 5 | parameter integer bits = @NBIT from [1:24]; // resolution (bits) 6 | parameter real vmin = 0.0; // minimum input voltage (V) 7 | parameter real vmax = pow(2,@NBIT) from (vmin:inf); // maximum input voltage (V) 8 | parameter real td = 0; // delay from clock edge to output (s) 9 | parameter real tt = 0; // transition time of output (s) 10 | parameter real vdd = 0.8; // voltage level of logic 0.8 (V) 11 | parameter real vss = 0; // voltage level of logic 0 (V) 12 | parameter real thresh = (vdd+vss)/2; // logic threshold level (V) 13 | parameter integer dir = +1 from [-1:1] exclude 0; 14 | // 1 for trigger on rising edge 15 | // -1 for falling 16 | localparam real fullscale = vmax - vmin; 17 | 18 | output out; 19 | input [0:bits-1] in; 20 | input clk; 21 | voltage out, clk; 22 | voltage [0:bits-1] in; 23 | real aout; 24 | integer weight; 25 | genvar i; 26 | 27 | analog begin 28 | @(cross(V(clk) - thresh, dir) or initial_step) begin 29 | aout = 0; 30 | weight = 2; 31 | for (i = bits - 1; i >= 0; i = i - 1) begin 32 | if (V(in[i]) > thresh) begin 33 | aout = aout + fullscale/weight; 34 | end 35 | weight = weight*2; 36 | end 37 | end 38 | V(out) <+ transition(aout + vmin, td, tt); 39 | end 40 | endmodule 41 | 42 | module ainv (in, out, dd); 43 | 44 | output out; voltage out; 45 | input in; voltage in; 46 | input dd; voltage dd; 47 | parameter real td = 1n from [0:inf); // delay to start of output transition 48 | parameter real tt = 1n from [0:inf); // transition time of output signals 49 | 50 | integer lout; 51 | 52 | analog begin 53 | // make sure simulator sees the threshold crossing 54 | @(cross(V(in) - V(dd)/2)) 55 | ; 56 | 57 | // compute the logical value of the output 58 | if (V(in) > V(dd)/2) 59 | lout = 0; 60 | else 61 | lout = 1; 62 | 63 | // create an analog version of logical output 64 | V(out) <+ V(dd)*transition(lout, td, tt); 65 | end 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/sar: -------------------------------------------------------------------------------- 1 | xsar_logic 2 | + @value 3 | + @result_out 4 | + clk_sar en sample out_n clk_comp 5 | + vdd vnw vpw vss 6 | + sar_logic 7 | 8 | xcdac 9 | + vcm_p vcm_n vin_p vin_n vrefh vrefl vtop_p vtop_n sample 10 | + @value 11 | + vdd vnw vpw vss 12 | + cdac 13 | 14 | xcomp clk_comp vtop_n vtop_p out_n out_p vdd vnw vpw vss comp_nand_ver0 15 | 16 | 17 | xdac dac_out @result_out enb dac 18 | -------------------------------------------------------------------------------- /generators/adc-gen/bk0_spice_template/sar.v: -------------------------------------------------------------------------------- 1 | 2 | module sar(clk, en, vin_p, vin_n, result, vcm, vdd, vnw, vpw, vss); 3 | 4 | /////////////////////////////////// 5 | ////////// Digital inputs////////// 6 | /////////////////////////////////// 7 | 8 | input clk; // sar clock input 9 | input en; // sar control signal // en=0 : sample phase. minimum 1 cycle. // en=1 : conversion phase. minimum WIDTH+2 cycles are needed. 10 | 11 | input vin_p; // sar analog positive input 12 | input vin_n; // sar analog negative input (Differential config. : connect negative input / Single-ended config. : connect vcm) 13 | 14 | output [@NBIT-1:0] result; // ADC output 15 | 16 | /////////////////////////////////// 17 | ////////// Analog inputs ////////// 18 | /////////////////////////////////// 19 | 20 | inout vcm; // common mode reference input. VDD/2 should be connected 21 | inout vdd; // power supply 22 | inout vss; // ground 23 | inout vnw; // power supply 24 | inout vpw; // ground 25 | 26 | /////////////////////////////////// 27 | ////////// Internal wires ////////// 28 | /////////////////////////////////// 29 | 30 | wire vtop_p, vtop_n; // cdac output => comparator positive, negative input 31 | wire sample; // input is sampled when sample=1 32 | wire outp, outn; // comparator output 33 | wire clk_comp; // comparator clk 34 | 35 | wire [@NBIT-1:0] value; //CDAC cap control signal 36 | //This part only works with 8 bit 37 | sar_logic isar_logic( 38 | .clk_sar(clk), 39 | .en(en), 40 | .sample(sample), 41 | .value(value), 42 | .result_out(result), 43 | .cmp(outn), 44 | .cmp_clk(clk_comp), 45 | .VDD(vdd), 46 | .VNW(vnw), 47 | .VPW(vpw), 48 | .VSS(vss) 49 | ); 50 | 51 | cdac icdac( 52 | .vin_p(vin_p), 53 | .vin_n(vin_n), 54 | .vrefh(vdd), 55 | .vrefl(vss), 56 | .vcm_p(vcm), 57 | .vcm_n(vcm), 58 | .vtop_n(vtop_n), 59 | .vtop_p(vtop_p), 60 | .sample(sample), 61 | .value(value), 62 | .vdd(vdd), 63 | .vnw(vnw), 64 | .vpw(vpw), 65 | .vss(vss) 66 | ); 67 | 68 | comp_nand_ver0 icomparator( 69 | .clk_sar(clk_comp), 70 | .vinn(vtop_n), 71 | .vinp(vtop_p), 72 | .outp(outp), 73 | .outn(outn), 74 | .vdd(vdd), 75 | .vnw(vnw), 76 | .vpw(vpw), 77 | .vss(vss) 78 | ); 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /generators/adc-gen/clear_file: -------------------------------------------------------------------------------- 1 | \rm -r *e-* 2 | \rm -r net_generated 3 | \rm -r run_dir 4 | \rm log 5 | \rm run_sim 6 | \rm *log* 7 | \rm result_gen 8 | \rm result_sorted 9 | \rm *.cdl 10 | \rm *temp 11 | \rm dac* 12 | \rm netlist_gen 13 | \rm ./flow/src/* 14 | \rm search_result_adc.csv 15 | \rm ./hspice/run/* 16 | -------------------------------------------------------------------------------- /generators/adc-gen/makefile: -------------------------------------------------------------------------------- 1 | gen_65lp_verilog: 2 | python tools/adc-gen.py --specfile adc_data.json --output ./work --platform tsmc65lp --mode verilog 3 | #python tools/adc-gen.py --specfile adc_data.json --output ./work --platform gf12lp --mode verilog 4 | 5 | gen_65lp_macro: 6 | python tools/adc-gen.py --specfile adc_data.json --output ./work --platform tsmc65lp --mode macro 7 | 8 | gen_65lp_full: 9 | python tools/adc-gen.py --specfile adc_data.json --output ./work --platform tsmc65lp --mode full 10 | 11 | 65lp_clean: 12 | python tools/adc-gen.py --specfile adc_data.json --output ./work --platform tsmc65lp --mode macro --clean 13 | 14 | gen_12lp_verilog: 15 | python tools/adc-gen.py --specfile adc_data.json --output ./work --platform gf12lp --mode verilog 16 | 17 | gen_12lp_macro: 18 | python tools/adc-gen.py --specfile adc_data.json --output ./work --platform gf12lp --mode macro 19 | #python tools/adc-gen.py --specfile adc_data.json --output ./work --platform gf12lp --mode verilog 20 | 21 | model: 22 | python tools/adc-gen-model.py --platform gf12lp 23 | 24 | 25 | clean: 26 | python tools/adc-gen.py --specfile adc_data.json --output ./work --platform gf12lp --clean 27 | #python tools/adc-gen-model.py --platform tsmc65lp --clean 28 | 29 | 30 | code_reset: 31 | git checkout ./flow 32 | git clean -f -d ./flow 33 | 34 | -------------------------------------------------------------------------------- /generators/adc-gen/models/gf12lp.model_adc.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/adc-gen/models/gf12lp.model_adc.xlsx -------------------------------------------------------------------------------- /generators/adc-gen/models/tsmc65lp.model_adc.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/adc-gen/models/tsmc65lp.model_adc.xlsx -------------------------------------------------------------------------------- /generators/adc-gen/netlist_gen: -------------------------------------------------------------------------------- 1 | python tools/../tools/auto_netgen.py 8 1 1 1 tsmc65lp 2 | -------------------------------------------------------------------------------- /generators/adc-gen/result_gen: -------------------------------------------------------------------------------- 1 | echo cap_val,widthi,widthc,fsmpl,nbit,nisw,ncsw,ncv,pwr,area,enob >> result_sorted 2 | python ./tools/result.py tools/../../../private/generators/adc-gen/hspice/run/tbSar_capVal_3.2e-15_widthi_2_widthc_2_fsmpl_1000000.0_config_8_1_1_1.mt0 >> result_sorted 3 | -------------------------------------------------------------------------------- /generators/adc-gen/result_gen_pex: -------------------------------------------------------------------------------- 1 | echo cap_val,widthi,widthc,fsmpl,nbit,nisw,ncsw,ncv,pwr,area,enob >> result_sorted 2 | python ./tools/result.py tools/../../../private/generators/adc-gen/hspice/run/tbSar_capVal_3.2e-15_widthi_2_widthc_2_fsmpl_1000000.0_config_8_1_1_1.pex.mt0 >> result_sorted_pex 3 | -------------------------------------------------------------------------------- /generators/adc-gen/run_sim: -------------------------------------------------------------------------------- 1 | finesim -spice -np 4 tools/../../../private/generators/adc-gen/hspice/run/tbSar_capVal_3.2e-15_widthi_2_widthc_2_fsmpl_1000000.0_config_8_1_1_1.sp -o tools/../../../private/generators/adc-gen/hspice/run/tbSar_capVal_3.2e-15_widthi_2_widthc_2_fsmpl_1000000.0_config_8_1_1_1 2 | -------------------------------------------------------------------------------- /generators/adc-gen/run_sim_pex: -------------------------------------------------------------------------------- 1 | finesim -spice -np 8 tools/../../../private/generators/adc-gen/hspice/run/tbSar_capVal_3.2e-15_widthi_2_widthc_2_fsmpl_1000000.0_config_8_1_1_1.pex.sp -o tools/../../../private/generators/adc-gen/hspice/run/tbSar_capVal_3.2e-15_widthi_2_widthc_2_fsmpl_1000000.0_config_8_1_1_1.pex 2 | -------------------------------------------------------------------------------- /generators/adc-gen/search_result_adc.csv: -------------------------------------------------------------------------------- 1 | power_min,fsampling,resolution,enob,area,nisw,ncsw,search_param 2 | 3.68e-06,1000000,7,6.930803,7492,1,1,"fsampling:1000000,enob:6.8,optimization:area" 3 | 1.7262e-06,1000000,8,8.026176,18781,1,2,"fsampling:1000000,enob:7.8,optimization:area" 4 | 1.7095e-06,1000000,8,7.652437,18269,1,1,"fsampling:1000000,enob:7.4,optimization:area" 5 | -------------------------------------------------------------------------------- /generators/adc-gen/tools/Makefile_backup: -------------------------------------------------------------------------------- 1 | input: 2 | python input_gen.py tbSar.sp 3 | net: 4 | netlist_gen 5 | run: 6 | run_sim 7 | data: 8 | result_gen 9 | 10 | -------------------------------------------------------------------------------- /generators/adc-gen/tools/Readme: -------------------------------------------------------------------------------- 1 | 1. Testbench / script generation : parameters can be specified in "input_gen.py" 2 | make input 3 | 4 | 2. netlist generation 5 | make net 6 | 7 | 3. run simulation 8 | make run 9 | 10 | 4. data sorting 11 | make data 12 | => "result_sorted" file is generated 13 | 14 | 5. clear 15 | clear 16 | -------------------------------------------------------------------------------- /generators/adc-gen/tools/clear_file: -------------------------------------------------------------------------------- 1 | \rm -r *e-* 2 | \rm -r net_generated 3 | \rm -r run_dir 4 | \rm log 5 | \rm run_sim 6 | \rm *log* 7 | \rm result_gen 8 | \rm result_sorted 9 | \rm *.cdl 10 | \rm *temp 11 | \rm dac* 12 | \rm netlist_gen 13 | -------------------------------------------------------------------------------- /generators/adc-gen/tools/fft_sar.py: -------------------------------------------------------------------------------- 1 | import numpy as np 2 | from scipy.fftpack import fft 3 | import matplotlib.pyplot as plt 4 | from numpy import array 5 | import sys 6 | import os 7 | 8 | file_name = sys.argv[1] 9 | r_file = open(file_name, "r") 10 | lines = r_file.readlines() 11 | 12 | stripped = lines[3].strip() 13 | 14 | data_in = stripped.split() 15 | data_in = data_in[0:256] 16 | 17 | for i in range(0,len(data_in)): 18 | data_in[i] = float(data_in[i]) 19 | 20 | ### input data => np array conversion 21 | fft_data_in = np.array(data_in) 22 | 23 | ### fft calculation 24 | fft_data_complex = fft(fft_data_in) 25 | 26 | ### fft complex => real abs magnitude conversion 27 | fft_data_abs = np.abs(fft_data_complex) 28 | 29 | ### fft abs magnitude => power spectral density conversion 30 | fft_pden = np.square(fft_data_abs)/len(fft_data_abs)/len(fft_data_abs) 31 | 32 | ### fft plot range set ( 0~128) : 129ea 33 | fft_pden = fft_pden[0:len(fft_pden)/2+1] 34 | 35 | ### fft => log conversion 36 | fft_pden_log = 10*np.log10(fft_pden) 37 | 38 | ### max value find for normalization 39 | fft_max_log=np.max(fft_pden_log[2:256]) 40 | 41 | ### fft normalization to 0dB 42 | fft_pden_log = fft_pden_log - fft_max_log 43 | 44 | ### plot fft 45 | #plt.plot(fft_pden_log) 46 | #plt.show() 47 | 48 | fft_pden_sort = np.sort(fft_pden[1:])[::-1] 49 | 50 | max_val = fft_pden_sort[0] 51 | max_val_2nd = fft_pden_sort[1] 52 | fft_sum = np.sum(fft_pden[1:]) 53 | 54 | sndr = 10*np.log10(max_val/(fft_sum-max_val-fft_pden[-1]/2)) 55 | sfdr = 10*np.log10(max_val/max_val_2nd) 56 | 57 | print("sndr = %f\n"%sndr) 58 | print("sfdr = %f\n"%sfdr) 59 | -------------------------------------------------------------------------------- /generators/adc-gen/work/adcInst.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance_name": "adcInst", 3 | "generator": "adc-gen", 4 | "specifications": { 5 | "fsampling": 1000000, 6 | "target enob": 7.4, 7 | "optimization": "area", 8 | "model": "modelfile.csv" 9 | }, 10 | "results": { 11 | "platform": "gf12lp", 12 | "area": 18269, 13 | "enob": 7.652437, 14 | "power": 1.7095e-06 15 | } 16 | } -------------------------------------------------------------------------------- /generators/adc-gen/work/sar.json: -------------------------------------------------------------------------------- 1 | { 2 | "instance_name": "sar", 3 | "generator": "adc-gen", 4 | "specifications": { 5 | "fsampling": 1000000, 6 | "target enob": 7.4, 7 | "optimization": "area", 8 | "model": "modelfile.csv" 9 | }, 10 | "results": { 11 | "platform": "tsmc65lp", 12 | "area": 1000, 13 | "enob": 7.652437, 14 | "power": 1.7095e-06 15 | } 16 | } -------------------------------------------------------------------------------- /generators/cdc-gen/.gitignore: -------------------------------------------------------------------------------- 1 | golden_* 2 | power_within_x.csv 3 | error_within_x.csv 4 | 5 | search_result_cdc.csv -------------------------------------------------------------------------------- /generators/cdc-gen/makefile: -------------------------------------------------------------------------------- 1 | gen_65lp: 2 | python tools/cdc-gen.py --specfile test.json --output ./work --platform tsmc65lp --mode verilog 3 | 4 | gen_12lp: 5 | python tools/cdc-gen.py --specfile test.json --output ./work --platform gf12lp --mode macro 6 | 7 | # model: 8 | # python tools/temp-sense-gen-model.py --platform tsmc65lp 9 | 10 | clean: 11 | git checkout ./flow 12 | git clean -f -d ./flow -------------------------------------------------------------------------------- /generators/cdc-gen/models/gf12lp.model_cdcprecharge: -------------------------------------------------------------------------------- 1 | Precharge,Max Capacitor,Max Capacitor (1us settling) 2 | 1,10pF,10 3 | 10,100pF,100 4 | 20,300pF,300 5 | 30,500pF,500 6 | 40,700pF,700 7 | 50,900pF,900 8 | 60,1.1nF,1100 9 | 70,1.3nF,1300 10 | 80,1.5nF,1500 11 | 90,1.7nF,1700 12 | 100,1.9nF,1900 13 | 200,4nF,4000 14 | 300,6nF,6000 15 | 400,8nF,8000 16 | 500,10nF,10000 17 | 600,12nF,12000 18 | 700,14nF,14000 19 | 800,16nF,16000 20 | 900,18nF,18000 21 | 1000,20nF,20000 -------------------------------------------------------------------------------- /generators/cdc-gen/models/tsmc65lp.model_cdcprecharge: -------------------------------------------------------------------------------- 1 | Precharge,Max Capacitor,Max Capacitor (1us settling) 2 | 1,10pF,10 3 | 10,100pF,100 4 | 20,300pF,300 5 | 30,500pF,500 6 | 40,700pF,700 7 | 50,900pF,900 8 | 60,1.1nF,1100 9 | 70,1.3nF,1300 10 | 80,1.5nF,1500 11 | 90,1.7nF,1700 12 | 100,1.9nF,1900 13 | 200,4nF,4000 14 | 300,6nF,6000 15 | 400,8nF,8000 16 | 500,10nF,10000 17 | 600,12nF,12000 18 | 700,14nF,14000 19 | 800,16nF,16000 20 | 900,18nF,18000 21 | 1000,20nF,20000 -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDCW_CNT_template.v: -------------------------------------------------------------------------------- 1 | module CDCW_CNT (TICK_TOTAL, TICK_RISE, TICK_FALL, RESETn, OE, OUT_TOTAL, OUT_RISE, OUT_FALL); 2 | 3 | input TICK_TOTAL, TICK_RISE, TICK_FALL, RESETn, OE; 4 | output [23:0] OUT_TOTAL, OUT_RISE, OUT_FALL; 5 | 6 | CNT_24_OE CNT_TOTAL (.CLK(TICK_TOTAL), .OE(OE), .RESETn(RESETn), .OUT(OUT_TOTAL)); 7 | CNT_24_OE CNT_RISE (.CLK(TICK_RISE), .OE(OE), .RESETn(RESETn), .OUT(OUT_RISE)); 8 | CNT_24_OE CNT_FALL (.CLK(TICK_FALL), .OE(OE), .RESETn(RESETn), .OUT(OUT_FALL)); 9 | endmodule 10 | 11 | module CNT_24_OE (CLK, OE, RESETn, OUT); 12 | 13 | input CLK, OE, RESETn; 14 | output [23:0] OUT; 15 | 16 | wire next_0, next_1, next_2, next_3, next_4, next_5; 17 | 18 | CNT_4_OE CNT_4_0 (.CLK(CLK), .OE(OE), .RESETn(RESETn), .NEXT(next_0), .OUT(OUT[3:0])); 19 | CNT_4_OE CNT_4_1 (.CLK(next_0), .OE(OE), .RESETn(RESETn), .NEXT(next_1), .OUT(OUT[7:4])); 20 | CNT_4_OE CNT_4_2 (.CLK(next_1), .OE(OE), .RESETn(RESETn), .NEXT(next_2), .OUT(OUT[11:8])); 21 | CNT_4_OE CNT_4_3 (.CLK(next_2), .OE(OE), .RESETn(RESETn), .NEXT(next_3), .OUT(OUT[15:12])); 22 | CNT_4_OE CNT_4_4 (.CLK(next_3), .OE(OE), .RESETn(RESETn), .NEXT(next_4), .OUT(OUT[19:16])); 23 | CNT_4_OE CNT_4_5 (.CLK(next_4), .OE(OE), .RESETn(RESETn), .NEXT(next_5), .OUT(OUT[23:20])); 24 | endmodule 25 | 26 | module CNT_4_OE (CLK, OE, RESETn, NEXT, OUT); 27 | 28 | input CLK, OE, RESETn; 29 | output NEXT; 30 | output [3:0] OUT; 31 | 32 | wire next_0, next_1, next_2; 33 | 34 | CNT_1_OE CNT_1_0 (.CLK(CLK), .OE(OE), .RESETn(RESETn), .NEXT(next_0), .OUT(OUT[0])); 35 | CNT_1_OE CNT_1_1 (.CLK(next_0), .OE(OE), .RESETn(RESETn), .NEXT(next_1), .OUT(OUT[1])); 36 | CNT_1_OE CNT_1_2 (.CLK(next_1), .OE(OE), .RESETn(RESETn), .NEXT(next_2), .OUT(OUT[2])); 37 | CNT_1_OE CNT_1_3 (.CLK(next_2), .OE(OE), .RESETn(RESETn), .NEXT(NEXT), .OUT(OUT[3])); 38 | endmodule 39 | 40 | module CNT_1_OE (CLK, OE, RESETn, NEXT, OUT); 41 | 42 | input CLK, OE, RESETn; 43 | output NEXT, OUT; 44 | 45 | wire qb, out_pre, nextb; 46 | 47 | @@ @na DFF0 (.Q(nextb), .D(qb), .CK(CLK), .R(RESETn)); 48 | @@ @nb INVX1_0 (.Y(qb), .A(nextb)); 49 | @@ @nb INVX1_1 (.Y(NEXT), .A(nextb)); 50 | @@ @nc NAND0 (.Y(out_pre), .A(OE), .B(qb)); 51 | @@ @nd BUFX4_0 (.Y(OUT), .A(out_pre)); 52 | endmodule 53 | 54 | 55 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_ANALOG2.nl.v: -------------------------------------------------------------------------------- 1 | module CDC_ANALOG2 (IN, OREF); 2 | 3 | input IN; 4 | output OREF; 5 | 6 | 7 | wire n1; 8 | wire n2; 9 | wire n3; 10 | wire n4; 11 | wire n5; 12 | wire n6; 13 | wire n7; 14 | wire n8; 15 | wire n9; 16 | wire n10; 17 | wire n11; 18 | wire n12; 19 | wire n13; 20 | wire n14; 21 | wire n15; 22 | wire n16; 23 | wire n17; 24 | wire n18; 25 | wire n19; 26 | wire n20; 27 | wire n21; 28 | wire out_pre; 29 | 30 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_0 (.A(IN), .Y(n1)); 31 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_1 (.A(n1), .Y(n2)); 32 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_2 (.A(n2), .Y(n3)); 33 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_3 (.A(n3), .Y(n4)); 34 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_4 (.A(n4), .Y(n5)); 35 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_5 (.A(n5), .Y(n6)); 36 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_6 (.A(n6), .Y(n7)); 37 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_7 (.A(n7), .Y(n8)); 38 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_8 (.A(n8), .Y(n9)); 39 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_9 (.A(n9), .Y(n10)); 40 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_10 (.A(n10), .Y(n11)); 41 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_11 (.A(n11), .Y(n12)); 42 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_12 (.A(n12), .Y(n13)); 43 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_13 (.A(n13), .Y(n14)); 44 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_14 (.A(n14), .Y(n15)); 45 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_15 (.A(n15), .Y(n16)); 46 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_16 (.A(n16), .Y(n17)); 47 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_17 (.A(n17), .Y(n18)); 48 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_18 (.A(n18), .Y(n19)); 49 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_19 (.A(n19), .Y(n20)); 50 | INVP_X0P4N_A10P5PP84TR_C14 inv_ic_20 (.A(n20), .Y(n21)); 51 | 52 | BUF_X0P4N_A10P5PP84TR_C14 buf_ic_0 (.A(n21), .Y(OREF)); 53 | 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_ANALOG2_template.nl.v: -------------------------------------------------------------------------------- 1 | module CDC_ANALOG2 (IN, OREF); 2 | 3 | input IN; 4 | output OREF; 5 | 6 | 7 | @@ wire n@nn; 8 | wire out_pre; 9 | 10 | @@ @na inv_ic_0 (.A(IN), .Y(n1)); 11 | @@ @nb inv_ic_@ni (.A(n@n1), .Y(n@n2)); 12 | 13 | @@ @nc buf_ic_0 (.A(n@n3), .Y(OREF)); 14 | 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_ANALOG_template.nl.v: -------------------------------------------------------------------------------- 1 | module CDC_ANALOG (PRECHARGE, PRECHARGEB, in_vin, IN, INB, OSEN, LCOUT); 2 | inout in_vin; 3 | input PRECHARGE, PRECHARGEB, IN, INB; 4 | output OSEN, LCOUT; 5 | 6 | 7 | wire pre; 8 | 9 | INVCHAIN_ISOVDD a_iniso_0 (.IN(LCOUT), .in_vin(in_vin), .OUT(OSEN)); 10 | //INVCHAIN a_iniso_1 (.IN(LCOUT), .OUT(OREF)); 11 | 12 | @@ @na a_precharge_@ni (.IN(pre), .VIN(in_vin)); 13 | 14 | @@ @nb a_lc_2 (.A(PRECHARGE), .AB(PRECHARGEB), .VIN(vin_in), .Y(pre)); 15 | @@ @nb a_lc_1 (.A(IN), .AB(INB), .VIN(vin_in), .Y(LCOUT)); 16 | 17 | 18 | //BUFX4HVT_ISOVDD a_buf_0 (.A(lc_out), .Y(LCOUT)); 19 | //BUFX4HVT a_buf_1 (.A(IN), .Y(in_buf)); 20 | //INVX1HVT a_inv_0 (.A(IN), .Y(inb)); 21 | //BUFX4HVT_ISOVDD a_buf_2 (.A(inb), .Y(inb_buf));:13 22 | 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_ANALOG_template_generic.nl.v: -------------------------------------------------------------------------------- 1 | module CDC_ANALOG (PRECHARGE, PRECHARGEB, in_vin, IN, INB, OSEN, LCOUT); 2 | inout in_vin; 3 | input PRECHARGE, PRECHARGEB, IN, INB; 4 | output OSEN, LCOUT; 5 | 6 | 7 | wire pre; 8 | 9 | INVCHAIN_ISOVDD a_iniso_0 (.IN(LCOUT), .OUT(OSEN)); 10 | //INVCHAIN a_iniso_1 (.IN(LCOUT), .OUT(OREF)); 11 | 12 | @@ @na a_precharge_@ni (.IN(pre), .VIN(in_vin)); 13 | 14 | @@ @nb a_lc_2 (.A(PRECHARGE), .AB(PRECHARGEB), .Y(pre)); 15 | @@ @nb a_lc_1 (.A(IN), .AB(INB), .Y(LCOUT)); 16 | 17 | 18 | //BUFX4HVT_ISOVDD a_buf_0 (.A(lc_out), .Y(LCOUT)); 19 | //BUFX4HVT a_buf_1 (.A(IN), .Y(in_buf)); 20 | //INVX1HVT a_inv_0 (.A(IN), .Y(inb)); 21 | //BUFX4HVT_ISOVDD a_buf_2 (.A(inb), .Y(inb_buf));:13 22 | 23 | endmodule 24 | 25 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/CDC_def.v: -------------------------------------------------------------------------------- 1 | //******************************************************************************************* 2 | 3 | //******************************************************************************************* 4 | `define SD #1 5 | 6 | `define NUM_TUNE_BITS_DEC_DLY 5 7 | `define NUM_TUNE_BITS_WL_WIDTH 3 8 | 9 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/DLY_COMP.nl.v: -------------------------------------------------------------------------------- 1 | module DLY_COMP (DLYP, DLYM, EN, DONE, YB); 2 | input DLYP, DLYM, EN; 3 | output DONE, YB; 4 | wire n1, n2, n3, n4, n5, n6, n7, d, db, DONE, YB; 5 | 6 | INVP_X0P4N_A10P5PP84TR_C14 inv_dc_0 (.A(DLYP), .Y(n1)); 7 | INVP_X0P4N_A10P5PP84TR_C14 inv_dc_1 (.A(DLYM), .Y(n2)); 8 | INVP_X0P4N_A10P5PP84TR_C14 inv_dc_2 (.A(n3), .Y(n5)); 9 | INVP_X0P4N_A10P5PP84TR_C14 inv_dc_3 (.A(n4), .Y(n6)); 10 | INVP_X0P4N_A10P5PP84TR_C14 inv_dc_4 (.A(db), .Y(d)); 11 | 12 | NAND2_X0P4N_A10P5PP84TR_C14 nand_dc_0 (.A(n1), .B(n4), .Y(n3)); 13 | NAND2_X0P4N_A10P5PP84TR_C14 nand_dc_1 (.A(n3), .B(n2), .Y(n4)); 14 | 15 | BUF_X0P4N_A10P5PP84TR_C14 buf_dc_0 (.A(n7), .Y(YB)); 16 | BUF_X0P4N_A10P5PP84TR_C14 buf_dc_2 (.A(d), .Y(DONE)); 17 | 18 | NAND3_X0P4N_A10P5PP84TR_C14 nand_dc_2 (.A(n6), .B(n1), .C(EN), .Y(n7)); 19 | XNOR2_X0P6N_A10P5PP84TR_C14 xnor_dc_0 (.A(n5), .B(n6), .Y(db)); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/DLY_COMP_template.nl.v: -------------------------------------------------------------------------------- 1 | module DLY_COMP (DLYP, DLYM, EN, DONE, YB); 2 | input DLYP, DLYM, EN; 3 | output DONE, YB; 4 | wire n1, n2, n3, n4, n5, n6, n7, d, db, DONE, YB; 5 | 6 | @@ @na inv_dc_0 (.A(DLYP), .Y(n1)); 7 | @@ @na inv_dc_1 (.A(DLYM), .Y(n2)); 8 | @@ @na inv_dc_2 (.A(n3), .Y(n5)); 9 | @@ @na inv_dc_3 (.A(n4), .Y(n6)); 10 | @@ @na inv_dc_4 (.A(db), .Y(d)); 11 | 12 | @@ @nb nand_dc_0 (.A(n1), .B(n4), .Y(n3)); 13 | @@ @nb nand_dc_1 (.A(n3), .B(n2), .Y(n4)); 14 | 15 | @@ @nc buf_dc_0 (.A(n7), .Y(YB)); 16 | @@ @nc buf_dc_2 (.A(d), .Y(DONE)); 17 | 18 | @@ @nd nand_dc_2 (.A(n6), .B(n1), .C(EN), .Y(n7)); 19 | @@ @nf xnor_dc_0 (.A(n5), .B(n6), .Y(db)); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/INVCHAIN_ISOVDD.nl.v: -------------------------------------------------------------------------------- 1 | module INVCHAIN_ISOVDD (IN, OUT); 2 | 3 | input IN; 4 | //inout in_vin; 5 | 6 | output OUT; 7 | 8 | wire n1; 9 | wire n2; 10 | wire n3; 11 | wire n4; 12 | wire n5; 13 | wire n6; 14 | wire n7; 15 | wire n8; 16 | wire n9; 17 | wire n10; 18 | wire n11; 19 | wire n12; 20 | wire n13; 21 | wire n14; 22 | wire n15; 23 | wire n16; 24 | wire n17; 25 | wire n18; 26 | wire n19; 27 | wire n20; 28 | wire n21; 29 | wire out_pre; 30 | 31 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_0 (.A(IN), .Y(n1)); 32 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_1 (.A(n1), .Y(n2)); 33 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_2 (.A(n2), .Y(n3)); 34 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_3 (.A(n3), .Y(n4)); 35 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_4 (.A(n4), .Y(n5)); 36 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_5 (.A(n5), .Y(n6)); 37 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_6 (.A(n6), .Y(n7)); 38 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_7 (.A(n7), .Y(n8)); 39 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_8 (.A(n8), .Y(n9)); 40 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_9 (.A(n9), .Y(n10)); 41 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_10 (.A(n10), .Y(n11)); 42 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_11 (.A(n11), .Y(n12)); 43 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_12 (.A(n12), .Y(n13)); 44 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_13 (.A(n13), .Y(n14)); 45 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_14 (.A(n14), .Y(n15)); 46 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_15 (.A(n15), .Y(n16)); 47 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_16 (.A(n16), .Y(n17)); 48 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_17 (.A(n17), .Y(n18)); 49 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_18 (.A(n18), .Y(n19)); 50 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_19 (.A(n19), .Y(n20)); 51 | INVP_X0P4N_A10P5PP84TR_C14 inv_iciso_20 (.A(n20), .Y(n21)); 52 | 53 | BUF_X0P4N_A10P5PP84TR_C14 buf_iciso_0 (.A(n21), .Y(OUT)); 54 | 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/INVCHAIN_ISOVDD_template.nl.v: -------------------------------------------------------------------------------- 1 | module INVCHAIN_ISOVDD (IN, in_vin, OUT); 2 | 3 | input IN; 4 | inout in_vin; 5 | 6 | output OUT; 7 | 8 | @@ wire n@nn; 9 | wire out_pre; 10 | 11 | @@ @na inv_iciso_0 (.A(IN), .VIN(in_vin), .Y(n1)); 12 | @@ @nb inv_iciso_@ni (.A(n@n1), .VIN(in_vin), .Y(n@n2)); 13 | 14 | @@ @nc buf_iciso_0 (.A(n@n3), .VIN(in_vin), .Y(OUT)); 15 | 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/INVCHAIN_ISOVDD_template_generic.nl.v: -------------------------------------------------------------------------------- 1 | module INVCHAIN_ISOVDD (IN, OUT); 2 | 3 | input IN; 4 | //inout in_vin; 5 | 6 | output OUT; 7 | 8 | @@ wire n@nn; 9 | wire out_pre; 10 | 11 | @@ @na inv_iciso_0 (.A(IN), .Y(n1)); 12 | @@ @nb inv_iciso_@ni (.A(n@n1), .Y(n@n2)); 13 | 14 | @@ @nc buf_iciso_0 (.A(n@n3), .Y(OUT)); 15 | 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/NEXT_EDGE_GEN_template.nl.v: -------------------------------------------------------------------------------- 1 | module NEXT_EDGE_GEN (RESET, VLOWDLY, FINISH, DONEF, DONER, OUTR, OUTF, CONVFINISH, CLK, SENSE); 2 | input RESET, VLOWDLY, FINISH, DONEF, DONER; 3 | output OUTR, OUTF, CONVFINISH, CLK, SENSE; 4 | wire n1, n2, n3, n4, n5, n6, n7, d, db, DONE, YB, reset_in, vlowdly_in, finish_in, donef_in, doner_in, outf_out, outr_out, convfinish_out, clk_out, sens_out; 5 | wire n8, n9, n10, n11, n12, n13; 6 | 7 | 8 | 9 | //input 10 | @@ @na buf_neg_0 (.A(RESET), .Y(reset_in)); 11 | @@ @na buf_neg_1 (.A(VLOWDLY), .Y(vlowdly_in)); 12 | @@ @na buf_neg_2 (.A(FINISH), .Y(finish_in)); 13 | @@ @na buf_neg_3 (.A(DONEF), .Y(donef_in)); 14 | @@ @na buf_neg_4 (.A(DONER), .Y(doner_in)); 15 | 16 | //output 17 | @@ @na buf_neg_5 (.A(outf_out), .Y(OUTF)); 18 | @@ @na buf_neg_6 (.A(outr_out), .Y(OUTR)); 19 | @@ @na buf_neg_7 (.A(convfinish_out), .Y(CONVFINISH)); 20 | @@ @na buf_neg_8 (.A(clk_out), .Y(CLK)); 21 | @@ @na buf_neg_9 (.A(sens_out), .Y(SENSE)); 22 | 23 | 24 | @@ @na buf_neg_10 (.A(n1), .Y(n2)); 25 | @@ @na buf_neg_11 (.A(n4), .Y(n5)); 26 | @@ @nb nand_neg_0 (.A(donef_in), .B(n3), .Y(n1)); 27 | @@ @nb nand_neg_1 (.A(vlowdly_in), .B(doner_in), .Y(n4)); 28 | @@ @nb nand_neg_2 (.A(n7), .B(n11), .Y(n12)); 29 | @@ @nb nand_neg_3 (.A(outf_out), .B(sens_out), .Y(n13)); 30 | @@ @nc inv_neg_0 (.A(vlowdly_in), .Y(n3)); 31 | @@ @nc inv_neg_1 (.A(outf_out), .Y(outr_out)); 32 | @@ @nc inv_neg_2 (.A(reset_in), .Y(n7)); 33 | @@ @nc inv_neg_3 (.A(n7), .Y(n8)); 34 | @@ @nc inv_neg_4 (.A(finish_in), .Y(n9)); 35 | @@ @nc inv_neg_5 (.A(convfinish_out), .Y(n11)); 36 | @@ @nc inv_neg_6 (.A(n12), .Y(sens_out)); 37 | @@ @nc inv_neg_7 (.A(n13), .Y(clk_out)); 38 | SRLATCH sr_neg_0 (.R(n5), .S(n2), .Q(outf_out), .QB(n6)); 39 | SRLATCH sr_neg_1 (.R(n8), .S(n9), .Q(convfinish_out), .QB(n10)); 40 | endmodule 41 | 42 | 43 | 44 | module SRLATCH(R, S, Q, QB); 45 | input R, S; 46 | output Q, QB; 47 | 48 | @@ @nd a_nor_0 (.A(R), .B(QB), .Y(Q)); 49 | @@ @nd a_nor_1 (.A(S), .B(Q), .Y(QB)); 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/SRLATCH.nl.v: -------------------------------------------------------------------------------- 1 | module SRLATCH(R, S, Q, QB); 2 | input R, S; 3 | output Q, QB; 4 | 5 | NOR2X1HVT a_nor_0 (.A(R), .B(QB), .Y(Q)); 6 | NOR2X1HVT a_nor_1 (.A(S), .B(Q), .Y(QB)); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /generators/cdc-gen/src/counter_16b.v: -------------------------------------------------------------------------------- 1 | module counter_16b(CLK_SENS, RESET_COUNTERn, DOUT); 2 | input RESET_COUNTERn; 3 | input CLK_SENS; 4 | 5 | output reg [15:0] DOUT; 6 | 7 | // reg [15:0] DOUT; 8 | wire clk_sens_in; 9 | //reg WAKE; 10 | //reg WAKE_pre; 11 | 12 | 13 | // assign clk_sens_in = done_sens && CLK_SENS; 14 | // assign clk_ref_in = done_ref && CLK_REF; 15 | // assign done_pre = ~doneb; 16 | // assign done_sens = WAKE_pre && doneb; 17 | // assign done_ref = WAKE && doneb; 18 | BUFX2HVT Buf_DONE(.A(CLK_SENS), .Y(clk_sens_in)); 19 | //assign RESET_CLK_REF = ~q1; 20 | 21 | // always @ (*) begin 22 | // case (done_pre) 23 | // 1'd0: DOUT = 24'd0; 24 | // 1'd1: DOUT = DOUT; 25 | // endcase 26 | // end 27 | 28 | // always @ (negedge RESET_COUNTERn or posedge CLK_REF) begin 29 | // if (~RESET_COUNTERn) begin WAKE <= 1'd0; 30 | // WAKE_pre <= 1'd0; 31 | // end 32 | // else if (WAKE_pre == 0) WAKE_pre <= 1'd1; 33 | // else WAKE <= WAKE_pre; 34 | // end 35 | // CLK_Sens DIV count 36 | always @ (negedge RESET_COUNTERn or posedge clk_sens_in) begin 37 | if (~RESET_COUNTERn) DOUT[0] <= 1'd0; 38 | else DOUT[0] <= ~DOUT[0]; 39 | end 40 | 41 | genvar j; 42 | generate 43 | for (j=1; j<16; j=j+1) begin 44 | always @ (negedge RESET_COUNTERn or negedge DOUT[j-1]) begin 45 | if (~RESET_COUNTERn) DOUT[j] <= 1'd0; 46 | else DOUT[j] <= ~DOUT[j]; 47 | end 48 | end 49 | endgenerate 50 | endmodule 51 | -------------------------------------------------------------------------------- /generators/cdc-gen/test.json: -------------------------------------------------------------------------------- 1 | { 2 | "module_name": "cdcInst_LC", 3 | "generator": "cdc-gen", 4 | "specifications": { 5 | "capacitance range": { "min": 1, "max": 100 }, 6 | "error": 0.1 7 | } 8 | } -------------------------------------------------------------------------------- /generators/cdc-gen/tools/TEMP_netlist.py: -------------------------------------------------------------------------------- 1 | ##for HSPICE netlist 2 | import function 3 | 4 | 5 | def gen_temp_netlist(ninv,nhead,aux1,aux2,aux3,aux4,aux5): 6 | r_netlist=open("flow/src/TEMP_ANALOG_test.nl.v","r") 7 | lines=list(r_netlist.readlines()) 8 | w_netlist=open("flow/src/TEMP_ANALOG.nl.v","w") 9 | 10 | 11 | 12 | netmap1=function.netmap() #modify here 13 | netmap1.get_net('nn',None,1,int(ninv),1) 14 | netmap1.get_net('n0',None,int(ninv),int(ninv),1) 15 | netmap1.get_net('na',aux1,1,1,1) 16 | netmap1.get_net('nb',aux2,0,int(ninv)-2,1) 17 | netmap1.get_net('ni',None,0,int(ninv)-2,1) 18 | netmap1.get_net('n1',None,1,int(ninv)-1,1) 19 | netmap1.get_net('n2',None,2,int(ninv),1) 20 | netmap1.get_net('ng',aux2,1,1,1) 21 | netmap1.get_net('n3',None,int(ninv),int(ninv),1) 22 | netmap1.get_net('nk',aux2,1,1,1) 23 | netmap1.get_net('n4',None,int(ninv),int(ninv),1) 24 | netmap1.get_net('nm',aux2,1,1,1) 25 | netmap1.get_net('np',aux3,1,1,1) 26 | netmap1.get_net('nc',aux3,1,1,1) 27 | netmap1.get_net('nd',aux4,1,1,1) 28 | netmap1.get_net('ne',aux4,1,1,1) 29 | netmap1.get_net('nf',aux5,0,int(nhead)-1,1) 30 | netmap1.get_net('nh',None,0,int(nhead)-1,1) 31 | for line in lines: 32 | netmap1.printline(line,w_netlist) 33 | 34 | 35 | 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /generators/cdc-gen/tools/VERILOG_wrapper.py: -------------------------------------------------------------------------------- 1 | #======== Verilog wrapper ========== 2 | import function 3 | import TEMP_netlist 4 | 5 | print("Number of INV(odd number):") 6 | ninv=int(input()) 7 | print("Number of HEADER:") 8 | nhead=int(input()) 9 | print("INV:{0} HEADER:{1}".format(ninv,nhead)) 10 | aux1 = 'NAND2X1HVT_ISOVDD' 11 | aux2 = 'INVX1HVT_ISOVDD' 12 | aux3 = 'BUFX1HVT_ISOVDD' 13 | aux4 = 'BUFX8HVT_ISOVDD' 14 | aux5 = 'HEADERX1HVT' 15 | 16 | 17 | TEMP_netlist.gen_temp_netlist(ninv,nhead,aux1,aux2,aux3,aux4,aux5) 18 | -------------------------------------------------------------------------------- /generators/cdc-gen/tools/code.py: -------------------------------------------------------------------------------- 1 | 2 | import re 3 | import sys 4 | 5 | #with open(sys.argv[1],'r') as r_mt0 6 | 7 | file_name = sys.argv[1] 8 | r_mt0 = open(file_name) 9 | 10 | 11 | mt0_lines=r_mt0.readlines() 12 | 13 | 14 | #################################################### 15 | str_list0=list() 16 | 17 | i=0 18 | 19 | for line in mt0_lines: 20 | result_pre=list() 21 | if i>2: 22 | result_pre=line.split() 23 | str_list0.append(result_pre) 24 | i=i+1 25 | 26 | 27 | #################################################### 28 | 29 | str_list1=list() 30 | 31 | for line in str_list0: 32 | result_pre2=list() 33 | i=0 34 | for val in line: 35 | if i<(len(line)-2): 36 | if float(val)>0.5: 37 | result_pre2.append(1.0) 38 | else: 39 | result_pre2.append(0.0) 40 | i=i+1 41 | 42 | str_list1=result_pre2 43 | 44 | 45 | code_f=0 46 | code_r=0 47 | code_t=0 48 | 49 | i=0 50 | for val in str_list1: 51 | if i<24: 52 | code_f = code_f+float(val*(2**i)) 53 | if i>23 and i<48: 54 | code_r = code_r+float(val*(2**(i-24))) 55 | if i>47 and i<72: 56 | code_t = code_t+float(val*(2**(i-48))) 57 | i=i+1 58 | 59 | code_final = code_t*2-code_f-code_r 60 | 61 | print("%s %s %s" %(result_pre[len(result_pre)-6], result_pre[len(result_pre)-3], code_final)) 62 | 63 | 64 | -------------------------------------------------------------------------------- /generators/cdc-gen/tools/result_error.py: -------------------------------------------------------------------------------- 1 | 2 | import math 3 | import numpy 4 | import os 5 | 6 | 7 | ##### generate list with result data [[code_var0], [code_var1], [code_var2], ...] 8 | ##### data0 is code for capacitance 9 | data0 = list() 10 | r_file = open("./code_result") 11 | mt0_data = r_file.readlines() 12 | data_col = 1 13 | new_list = list() 14 | multi = 2 15 | 16 | for line in mt0_data: 17 | stripped = line.strip() 18 | split_line=stripped.split() 19 | data0.append(split_line[2]) 20 | #### data1: code difference based on last code 21 | data1 = list() 22 | data2 = list() 23 | i=0 24 | last_code= data0[len(data0)-1] 25 | for val in data0: 26 | i=i+1 27 | if val == 'failed': 28 | val_cal = 'failed' 29 | else: 30 | val_cal = float(val)-(float(last_code)*pow(1/float(multi),len(data0)-i)) 31 | error = 100*(val_cal/float(val)) 32 | data1.append(val_cal) 33 | data2.append(error) 34 | 35 | r_result_list = open("./code_result", "r") 36 | result_lines= r_result_list.readlines() 37 | result_list = list() 38 | i=0 39 | print(os.getcwd()) 40 | print('ConversionTime Power CODE CODEdifference Error ') 41 | for line in result_lines: 42 | result_list = result_lines[i].split() 43 | print('%s %s %s %s %s %s'%(result_list[0], result_list[1], result_list[2], data0[i], data1[i], data2[i])) 44 | i=i+1 45 | 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /generators/dcdc-gen/Makefile: -------------------------------------------------------------------------------- 1 | gen_12lp: 2 | ./tools/dcdc-gen.py --specfile test.json --output ./work --platform gf12lp 3 | 4 | gen_12lp_macro: 5 | ./tools/dcdc-gen.py --specfile test.json --output ./work --platform gf12lp --mode macro 6 | 7 | clean: 8 | ./tools/dcdc-gen.py --specfile test.json --output ./work --platform gf12lp --clean 9 | 10 | clean_12lp_full: 11 | ./tools/dcdc-gen.py --specfile test.json --output ./work --platform gf12lp --clean --mode full 12 | 13 | code_reset: 14 | git checkout ./flow 15 | git clean -f -d ./flow 16 | -------------------------------------------------------------------------------- /generators/dcdc-gen/test.json: -------------------------------------------------------------------------------- 1 | { 2 | "module_name": "DCDC_TOP_0p56V_0p2mA", 3 | "generator": "dcdc-gen", 4 | "specifications": { 5 | "Iload (mA)": 0.2, 6 | "Output voltage (V)": 0.56, 7 | "Clock frequency (kHz)" : 30000 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /generators/dcdc-gen/verilog/DCDC_CONV2to1.v: -------------------------------------------------------------------------------- 1 | 2 | module DCDC_CONV2to1 ( 3 | // inout VDD, 4 | // inout VSS, 5 | // inout vhigh, 6 | // inout vlow, 7 | // inout vmid, 8 | // inout y1_top, 9 | // inout y0_top, 10 | // inout y1_bot, 11 | // inout y0_bot, 12 | 13 | input clk0, 14 | input clk0b, 15 | input clk1, 16 | input clk1b 17 | ); 18 | 19 | DCDC_HUNIT_CONV2to1 u_high_DCDC_HUNIT_CONV2to1 ( 20 | //.VDD(VDD), 21 | //.VSS(VSS), 22 | //.vhigh(vhigh), 23 | //.vlow(vmid), 24 | //.y0(y0_top), 25 | //.y1(y1_top), 26 | 27 | .clk0(clk0), 28 | .clk0b(clk0b), 29 | .clk1(clk1), 30 | .clk1b(clk1b) 31 | ); 32 | 33 | DCDC_HUNIT_CONV2to1 u_low_DCDC_HUNIT_CONV2to1 ( 34 | //.VDD(VDD), 35 | //.VSS(VSS), 36 | //.vhigh(vmid), 37 | //.vlow(vlow), 38 | //.y0(y0_bot), 39 | //.y1(y1_bot), 40 | 41 | .clk0(clk0), 42 | .clk0b(clk0b), 43 | .clk1(clk1), 44 | .clk1b(clk1b) 45 | ); 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /generators/dcdc-gen/verilog/DCDC_HUNIT_CONV2to1.v: -------------------------------------------------------------------------------- 1 | 2 | module DCDC_HUNIT_CONV2to1 ( 3 | // inout VDD, 4 | // inout VSS, 5 | // inout vhigh, 6 | // inout vlow, 7 | // inout y0, 8 | // inout y1, 9 | 10 | input clk0, 11 | input clk0b, 12 | input clk1, 13 | input clk1b 14 | ); 15 | 16 | DCDC_XSW_PMOS u_DCDC_XSW_PMOS ( 17 | //.VDD(VDD), 18 | //.VSS(VSS), 19 | //.vIN(vhigh), 20 | //.vOUT0(y0), 21 | //.vOUT1(y1), 22 | .clk(clk1b), 23 | .clkb(clk0b) 24 | ); 25 | 26 | DCDC_XSW_NMOS u_DCDC_XSW_NMOS ( 27 | //.VDD(VDD), 28 | //.VSS(VSS), 29 | //.vIN(vlow), 30 | //.vOUT0(y0), 31 | //.vOUT1(y1), 32 | .clk(clk1), 33 | .clkb(clk0) 34 | ); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /generators/ldo-gen/.gitignore: -------------------------------------------------------------------------------- 1 | IBM_CMOS8HP_SC.cdl 2 | PT_UNIT_CELL.cdl 3 | .cshrc_8hp 4 | work 5 | -------------------------------------------------------------------------------- /generators/ldo-gen/Makefile: -------------------------------------------------------------------------------- 1 | gen_65lp: 2 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform tsmc65lp 3 | 4 | gen_65lp_macro: 5 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform tsmc65lp --mode macro 6 | 7 | gen_65lp_full: 8 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform tsmc65lp --mode full 9 | 10 | model_65lp: 11 | ./tools/ldo_model.py --platform tsmc65lp 12 | 13 | gen_8hp: 14 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform gfbicmos8hp 15 | 16 | gen_8hp_macro: 17 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform gfbicmos8hp --mode macro 18 | 19 | gen_8hp_full: 20 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform gfbicmos8hp --mode full 21 | 22 | model_8hp: 23 | ./tools/ldo_model.py --platform gfbicmos8hp 24 | 25 | gen_12lp: 26 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform gf12lp 27 | 28 | gen_12lp_macro: 29 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform gf12lp --mode macro 30 | 31 | gen_12lp_full: 32 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform gf12lp --mode full 33 | 34 | model_12lp: 35 | ./tools/ldo_model.py --platform gf12lp 36 | 37 | clean: 38 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform tsmc65lp --clean 39 | 40 | clean_65lp_full: 41 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform tsmc65lp --clean --mode full 42 | ./tools/ldo_model.py --platform tsmc65lp --clean 43 | 44 | clean_8hp_full: 45 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform gfbicmos8hp --clean --mode full 46 | ./tools/ldo_model.py --platform gfbicmos8hp --clean 47 | 48 | clean_12lp_full: 49 | ./tools/ldo_gen.py --specfile test.json --output ./work --platform gf12lp --clean --mode full 50 | ./tools/ldo_model.py --platform gf12lp --clean 51 | 52 | code_reset: 53 | git checkout ./flow 54 | git clean -f -d ./flow 55 | -------------------------------------------------------------------------------- /generators/ldo-gen/test.json: -------------------------------------------------------------------------------- 1 | 2 | { 3 | "module_name": "ldo", 4 | "generator": "ldo-gen", 5 | "specifications": { 6 | "vin": 0.8, 7 | "imax": "1e-03", 8 | "dropout": "0.05" 9 | } 10 | } 11 | -------------------------------------------------------------------------------- /generators/ldo-gen/tools/supported_inputs.json: -------------------------------------------------------------------------------- 1 | 2 | { 3 | "platforms": { 4 | "tsmc65lp": { 5 | "vin": { 6 | "max": 1.3, 7 | "min": 0.6 8 | }, 9 | "dropout": { 10 | "max": 0.05, 11 | "min": 0.05 12 | }, 13 | "maxLoad": { 14 | "max": "25e-03", 15 | "min": "0.5e-03" 16 | } 17 | }, 18 | "gfbicmos8hp": { 19 | "vin": { 20 | "max": 1.3, 21 | "min": 0.6 22 | }, 23 | "dropout": { 24 | "max": 0.05, 25 | "min": 0.05 26 | }, 27 | "maxLoad": { 28 | "max": "25e-03", 29 | "min": "0.5e-03" 30 | } 31 | }, 32 | "gf12lp": { 33 | "vin": { 34 | "max": 0.9, 35 | "min": 0.6 36 | }, 37 | "dropout": { 38 | "max": 0.1, 39 | "min": 0.05 40 | }, 41 | "maxLoad": { 42 | "max": "15e-03", 43 | "min": "0.5e-03" 44 | } 45 | } 46 | } 47 | } 48 | -------------------------------------------------------------------------------- /generators/ldo-gen/verilog/LDO_CONTROLLER_TEMPLATE.v: -------------------------------------------------------------------------------- 1 | module LDO_CONTROLLER( 2 | clk, reset, mode, ctrl_in, 3 | std_pt_in_cnt, ctrl_word, ctrl_word_cnt); 4 | 5 | parameter integer ARRSZ = 50; 6 | 7 | input clk, reset, ctrl_in, mode; 8 | input [8:0] std_pt_in_cnt; 9 | output reg [8:0] ctrl_word_cnt; 10 | output reg [ARRSZ-1:0] ctrl_word; 11 | 12 | wire [ARRSZ-1:0] ctrl_rst = 50'h3ffffffffffff; 13 | 14 | always @(posedge clk) begin 15 | if (reset) begin 16 | ctrl_word <= ctrl_rst; 17 | ctrl_word_cnt <= 9'h0; 18 | end 19 | else if (mode) begin 20 | if (ctrl_in) begin 21 | ctrl_word <= {1'b1, ctrl_word[ARRSZ-1:1]}; 22 | if (~ctrl_word[0]) 23 | ctrl_word_cnt <= ctrl_word_cnt - 1; 24 | end 25 | else begin 26 | ctrl_word <= {ctrl_word[ARRSZ-2:0], 1'b0}; 27 | if (ctrl_word[ARRSZ-1]) 28 | ctrl_word_cnt <= ctrl_word_cnt + 1; 29 | end 30 | end 31 | else begin 32 | ctrl_word <= ctrl_rst << std_pt_in_cnt; 33 | ctrl_word_cnt <= std_pt_in_cnt; 34 | end 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /generators/ldo-gen/verilog/LDO_TEMPLATE.v: -------------------------------------------------------------------------------- 1 | module ldoInst( 2 | input clk, 3 | input reset, 4 | 5 | input [1:0] mode_sel, // 2'b00 (Comparator & PT Array Test Mode) 6 | // 2'b01 (Controller Test Mode) 7 | // 2'b1X (LDO Run Mode) 8 | 9 | input std_ctrl_in, // Standalone Controller Test Input 10 | input [8:0] std_pt_in_cnt, // Standalone PT Array Test Input 11 | 12 | output cmp_out, // Comparator Output 13 | output [8:0] ctrl_out, // Controller Output Count 14 | 15 | input VREF // Reference Voltage 16 | ); 17 | 18 | parameter integer ARRSZ = 50; 19 | 20 | reg ctrl_in, mode; 21 | reg [ARRSZ-1:0] pt_ctrl_word; 22 | 23 | LDO_COMPARATOR cmp1 (.CLK(clk), 24 | .VREF(VREF), 25 | .OUT(cmp_out)); 26 | 27 | LDO_CONTROLLER #(.ARRSZ(ARRSZ)) 28 | ctrl1 (.clk(clk), 29 | .reset(reset), 30 | .mode(mode), 31 | .ctrl_in(ctrl_in), 32 | .std_pt_in_cnt(std_pt_in_cnt), 33 | .ctrl_word(pt_ctrl_word), 34 | .ctrl_word_cnt(ctrl_out)); 35 | 36 | PT_UNIT_CELL pt_array_unit [ARRSZ-1:0] (.CTRL(pt_ctrl_word)); 37 | 38 | always @(*) begin 39 | mode = mode_sel[0] || mode_sel[1]; 40 | 41 | if (mode_sel[1]) 42 | ctrl_in = cmp_out; 43 | else 44 | ctrl_in = std_ctrl_in; 45 | end 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/memory-gen/SRAM/__init__.py -------------------------------------------------------------------------------- /generators/memory-gen/SRAM/bitcellprops.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3.7.3 2 | from collections import namedtuple 3 | 4 | from .cellprops import CellProps 5 | 6 | 7 | class BitCellProps(CellProps): 8 | """ 9 | Common attributes of all the auxcells are abstracted thourgh the CellProps Class. 10 | """ 11 | 12 | def __init__(self): 13 | super().__init__() 14 | 15 | def update_orientations(self, orientations=[]): 16 | self.orientations = orientations 17 | 18 | def update_energy(self, energy=[0,0,0,0,0]): 19 | self.read_energy = energy[0] 20 | self.read_leakage_energy = energy[1] 21 | self.write_energy = energy[2] 22 | self.write_leakage_energy = energy[3] 23 | self.hold_energy = energy[4] #-> hold energy itself is leakage energy 24 | 25 | def update_delay(self, delay=[0, 0]): 26 | self.read_delay = delay[0] 27 | self.write_delay = delay[1] 28 | 29 | def get_read_energy(self): 30 | return self.read_energy 31 | 32 | def get_write_energy(self): 33 | return self.write_energy 34 | 35 | def get_hold_energy(self): 36 | return self.hold_energy 37 | 38 | def get_read_leakage_energy(self): 39 | return self.read_leakage_energy 40 | 41 | def get_write_leakage_energy(self): 42 | return self.read_energy 43 | 44 | def get_read_delay(self): 45 | return self.delay 46 | 47 | def get_write_delay(self): 48 | return self.delay 49 | 50 | def get_layout_props(self): 51 | return self.layer_props 52 | 53 | def get_size(self): 54 | _get_size = namedtuple("get_size", ["size_x", "size_y"]) 55 | return _get_size(self.size_x, self.size_y) 56 | 57 | def get_orientations(self): 58 | return self.orientations 59 | 60 | def is_column_muxed(self): 61 | return self.column_muxing 62 | -------------------------------------------------------------------------------- /generators/memory-gen/deo/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/memory-gen/deo/__init__.py -------------------------------------------------------------------------------- /generators/memory-gen/globals/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/memory-gen/globals/__init__.py -------------------------------------------------------------------------------- /generators/memory-gen/globals/configs/mem_arch.yaml: -------------------------------------------------------------------------------- 1 | min_words_prow_pbank : 1 2 | max_rows_pbank : 512 3 | min_words_pcol_pbank : 1 4 | max_cols_pbank : 512 5 | max_no_hierarchies : 3 6 | -------------------------------------------------------------------------------- /generators/memory-gen/globals/configs/mem_config.yaml: -------------------------------------------------------------------------------- 1 | min_words_prow_pbank : 1 2 | max_rows_pbank : 512 3 | min_words_pcol_pbank : 1 4 | max_cols_pbank : 512 5 | max_no_hierarchies : 3 6 | -------------------------------------------------------------------------------- /generators/memory-gen/globals/configs/verified_tools.yaml: -------------------------------------------------------------------------------- 1 | hspice : 2016.01-SP2 2 | spectre : 2018.05 3 | cadence_innovus : 2018 4 | synopsys_dc_compiler : 2018 5 | calibre : 2018 6 | -------------------------------------------------------------------------------- /generators/memory-gen/globals/mem_arch_config_parser.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | """ 3 | Created on Fri Oct 4 12:14:17 2019 4 | @author: SumanthKamineni 5 | """ 6 | import os 7 | # import matplotlib.pyplot as plt 8 | from optparse import OptionParser 9 | # import numpy as np 10 | from globals import global_utils 11 | 12 | 13 | def mem_arch_config_parser(mem_arch_config): 14 | """ 15 | Parsers the input spec file and creates the necessary variables. 16 | """ 17 | from globals import global_utils 18 | 19 | arch_config_dic = global_utils.yaml_config_parser(mem_arch_config) 20 | 21 | return arch_config_dic 22 | 23 | 24 | def main(): 25 | parser = OptionParser() 26 | parser.add_option('-s', '--specfile', 27 | type='string', 28 | dest='Spec', 29 | help='''Configuration file in Json format with Specifications of the memory to be generated. 30 | Ex: -c sram_config.json or --Config= sram_config.json ''', 31 | default='') 32 | 33 | (options, argv) = parser.parse_args() 34 | global p_options 35 | p_options = {} 36 | p_options['SpecFile'] = options.Spec 37 | global rundir 38 | rundir = os.getcwd() 39 | sram_comps, no_words, word_size, voltage, frequency, BC_6T, min_colspb, max_rowspb, max_colspb = mem_arch_config_parser( 40 | p_options['Specfile']); # Parses the spec file to grab the SRAM specs 41 | 42 | if __name__ == '__main__': 43 | main() 44 | -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/memory-gen/macro_gen/__init__.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/apr/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/memory-gen/macro_gen/apr/__init__.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/synthesis/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/memory-gen/macro_gen/synthesis/__init__.py -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/synthesis/synth_constraints.py: -------------------------------------------------------------------------------- 1 | def constraints_gen(fh): 2 | from private.apr_pymodules.constraints import * 3 | fh.write(set_donot_touch('dc', '*')) 4 | -------------------------------------------------------------------------------- /generators/memory-gen/macro_gen/verilog_gen/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/memory-gen/macro_gen/verilog_gen/__init__.py -------------------------------------------------------------------------------- /generators/pll-gen/.gitignore: -------------------------------------------------------------------------------- 1 | pymodules/test* 2 | tsmc40gp/ 3 | *.swp 4 | *.swo 5 | *.shm 6 | *.vcd 7 | *.svwf 8 | *INCA_libs/ 9 | *simvision/ 10 | *xcelium* 11 | *.diag 12 | *.log 13 | *.history 14 | *ignore* 15 | -------------------------------------------------------------------------------- /generators/pll-gen/ble_design_params.json: -------------------------------------------------------------------------------- 1 | { 2 | "std_cell_names": 3 | { 4 | "buf8x_name":"BUFH_X8N_PlaceHolder", 5 | "buf2x_name":"BUFH_X2N_PlaceHolder", 6 | "buf4x_name":"BUFH_X4N_PlaceHolder", 7 | "buf10x_name":"BUFH_X10N_PlaceHolder", 8 | "dff_name":"DFFRPQ_X3N_PlaceHolder", 9 | "inv0p6x_name":"INV_X0P6N_PlaceHolder" , 10 | "buf16x_name":"BUFH_X16N_PlaceHolder", 11 | "buf14x_name":"BUFH_X14N_PlaceHolder", 12 | "embtdc_dff_name":"DFFQ_X1N_PlaceHolder" , 13 | "xnor2_0p6_name":"XNOR2_X0P6N_PlaceHolder", 14 | "dffrpq_3x_name":"DFFRPQ_X3N_PlaceHolder", 15 | "dffq_name":"DFFQ_X1N_PlaceHolder" 16 | }, 17 | "dco_design_params": 18 | { 19 | "nstg":5, 20 | "ndrv":24, 21 | "ncc":20, 22 | "nfc":24, 23 | "ncc_dead":4 24 | }, 25 | "tstdc_counter_design_params": 26 | { 27 | "pre_ls_ref_nstg_cc_tune":2, 28 | "pre_ls_ref_ncc_tune":2, 29 | "pre_ls_ref_nfc":63, 30 | "dltdc_num_ph":10, 31 | "dltdc_nfc":4, 32 | "dltdc_ndrv":2, 33 | "dltdc_ncc":2, 34 | "pre_nstg_ref_ls":18, 35 | "pre_nstg_ref":30, 36 | "pre_nstg_fb":12, 37 | "ppath_nstg":3, 38 | "pre_ls_ref_nstg":18, 39 | "post_ls_ref_nstg":6, 40 | "post_ls_ref_nstg_cc_tune":2, 41 | "post_ls_ref_ncc_tune":2, 42 | "pre_es_fb_nstg":8, 43 | "pre_es_fb_nstg_cc_tune":2, 44 | "pre_es_fb_ncc_tune":2, 45 | "post_es_fb_nstg":4, 46 | "post_es_fb_nstg_cc_tune":2, 47 | "post_es_fb_ncc_tune":2 48 | } 49 | } 50 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/:run: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | irun -64bit \ 3 | -elaborate \ 4 | -sv \ 5 | -sem2009 \ 6 | -sysv_ext +.vh \ 7 | -access +rwc \ 8 | -timescale 1ps/1fs \ 9 | -f ./flist_beh.f \ 10 | -l irun_comp.log 11 | 12 | #-define BEH \ 13 | #-tfile embtdc_dis.tfile \ 14 | #-notimingcheck \ 15 | #-define TDC_APR \ 16 | #-define APR \ 17 | #-define SYN \ 18 | 19 | irun -64bit \ 20 | -R \ 21 | -sv \ 22 | -sem2009 \ 23 | -access +rwc \ 24 | -input dump_irun.tcl \ 25 | +delay_mode_unit \ 26 | -timescale 1ps/1fs \ 27 | -l irun_run.log 28 | 29 | 30 | 31 | #diff goldenbrick/gb_out_mult_add_res_reuse.txt ./testbench_mult_add_res_reuse.txt | tee ./diff_functional_mult_add_res_reuse.txt #5 32 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_dco/dco_CC_se_3st.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | 3 | module dco_CC_se_3st (IN, OUT, EN); 4 | input IN; 5 | output OUT; 6 | input EN; 7 | endmodule 8 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_dco/dco_FC_se2_half.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | // 3 | 4 | module dco_FC_se2_half (IN, EN, ENB); 5 | input IN; 6 | input EN; 7 | input ENB; 8 | endmodule 9 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_pll_top/FUNCTIONS.v: -------------------------------------------------------------------------------- 1 | // Functions 2 | 3 | function automatic integer func_clog2; 4 | // task automatic func_clog2; 5 | // calculate how many bits are needed to express the input value N 6 | 7 | input integer func_clog2_N; 8 | integer func_clog2_ii; 9 | 10 | // keep going until 2^ii is larger than N 11 | //for (func_clog2_ii=0;2**func_clog2_ii= func_MAX_B) 25 | func_MAX = func_MAX_A; 26 | else 27 | func_MAX = func_MAX_B; 28 | 29 | endfunction 30 | 31 | 32 | function automatic integer func_MIN; 33 | // return the max of A or B 34 | 35 | input integer func_MIN_A; 36 | input integer func_MIN_B; 37 | 38 | if (func_MIN_A >= func_MIN_B) 39 | func_MIN = func_MIN_A; 40 | else 41 | func_MIN = func_MIN_B; 42 | 43 | endfunction 44 | 45 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_pll_top/ssc_generator.v: -------------------------------------------------------------------------------- 1 | `ifndef __SSC_GENERATOR__ 2 | `define __SSC_GENERATOR__ 3 | 4 | `timescale 1ns/1ps 5 | 6 | module ssc_generator( 7 | CLKREF, 8 | RST, 9 | SSC_EN, 10 | COUNT_LIM, 11 | STEP, 12 | SHIFT, 13 | MOD_OUT 14 | ); 15 | 16 | // Functions 17 | // `include "functions.v" 18 | 19 | // Parameters 20 | parameter COUNT_WIDTH = 12; 21 | parameter ACCUM_WIDTH = 16; 22 | parameter MOD_WIDTH = 5; 23 | parameter SHIFT_WIDTH = func_clog2(ACCUM_WIDTH-1); 24 | 25 | input CLKREF, RST, SSC_EN; 26 | input [COUNT_WIDTH-1:0] COUNT_LIM; 27 | input [3:0] STEP; 28 | input [SHIFT_WIDTH-1:0] SHIFT; 29 | 30 | output [MOD_WIDTH-1:0] MOD_OUT; 31 | 32 | reg [ACCUM_WIDTH-1:0] accum; 33 | wire [ACCUM_WIDTH-1:0] accum_shift; 34 | 35 | reg [COUNT_WIDTH-1:0] count; 36 | 37 | assign accum_shift = accum >> SHIFT; 38 | assign MOD_OUT = accum_shift[MOD_WIDTH-1:0]; 39 | 40 | always @(posedge CLKREF) begin 41 | if (RST) begin 42 | accum <= 0; 43 | count <= 0; 44 | end 45 | else if (SSC_EN) begin 46 | if (count < (COUNT_LIM >> 1)) begin 47 | accum <= accum + STEP; 48 | end 49 | else begin 50 | accum <= accum - STEP; 51 | end 52 | 53 | if (count >= COUNT_LIM-1) begin 54 | count <= 0; 55 | accum <= 0; //ensure accum is reset every cycle regardless of bugs 56 | end 57 | else begin 58 | count <= count +1; 59 | end 60 | end 61 | end 62 | 63 | endmodule 64 | `endif 65 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/FREQ_DIV.v: -------------------------------------------------------------------------------- 1 | //`timescale 1ns/1ps 2 | module FREQ_DIV (RESET, CLK_40M, CLK_8M); 3 | 4 | input RESET; 5 | input CLK_40M; 6 | output reg CLK_8M; 7 | 8 | reg [2:0] cnt; 9 | 10 | always@ ( posedge CLK_40M or posedge RESET) begin 11 | if (RESET) begin 12 | cnt <= 0; 13 | CLK_8M <= 0; 14 | end else begin 15 | if (cnt < 4) begin 16 | cnt <= cnt+1; 17 | if(cnt==1) begin 18 | CLK_8M <= 1; 19 | end else if (cnt == 3) begin 20 | CLK_8M <= 0; 21 | end 22 | end else if (cnt==4) begin 23 | cnt <= 0; 24 | end 25 | end 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/FUNCTIONS.v: -------------------------------------------------------------------------------- 1 | // Functions 2 | 3 | function automatic integer func_clog2; 4 | // task automatic func_clog2; 5 | // calculate how many bits are needed to express the input value N 6 | 7 | input integer func_clog2_N; 8 | integer func_clog2_ii; 9 | 10 | // keep going until 2^ii is larger than N 11 | //for (func_clog2_ii=0;2**func_clog2_ii= func_MAX_B) 25 | func_MAX = func_MAX_A; 26 | else 27 | func_MAX = func_MAX_B; 28 | 29 | endfunction 30 | 31 | 32 | function automatic integer func_MIN; 33 | // return the max of A or B 34 | 35 | input integer func_MIN_A; 36 | input integer func_MIN_B; 37 | 38 | if (func_MIN_A >= func_MIN_B) 39 | func_MIN = func_MIN_A; 40 | else 41 | func_MIN = func_MIN_B; 42 | 43 | endfunction 44 | 45 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/SCPA_Final.v: -------------------------------------------------------------------------------- 1 | 2 | module SCPA_Final ( 3 | PA_TEST, 4 | SEL[31:0] 5 | ); 6 | 7 | input PA_TEST; 8 | input [31:0] SEL; 9 | 10 | // inout RF_IN; 11 | // inout PLL_IN; 12 | // inout VO; 13 | // inout VDD_BUFF; 14 | // inout VDD; 15 | // inout VSS; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/SCPA_with_Decoupling_Cap.v: -------------------------------------------------------------------------------- 1 | 2 | module SCPA_with_Decoupling_Cap ( 3 | SEL[31:0], 4 | RF, 5 | VO); 6 | 7 | input [31:0] SEL; 8 | input RF; 9 | output VO; 10 | 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/SSC_GENERATOR.v: -------------------------------------------------------------------------------- 1 | `ifndef __SSC_GENERATOR__ 2 | `define __SSC_GENERATOR__ 3 | 4 | `timescale 1ns/1ps 5 | 6 | module SSC_GENERATOR( 7 | CLKREF, 8 | RST, 9 | SSC_EN, 10 | COUNT_LIM, 11 | STEP, 12 | SHIFT, 13 | MOD_OUT 14 | ); 15 | 16 | // Functions 17 | `include "FUNCTIONS.v" 18 | 19 | // Parameters 20 | parameter COUNT_WIDTH = 12; 21 | parameter ACCUM_WIDTH = 16; 22 | parameter MOD_WIDTH = 5; 23 | parameter SHIFT_WIDTH = func_clog2(ACCUM_WIDTH-1); 24 | 25 | input CLKREF, RST, SSC_EN; 26 | input [COUNT_WIDTH-1:0] COUNT_LIM; 27 | input [3:0] STEP; 28 | input [SHIFT_WIDTH-1:0] SHIFT; 29 | 30 | output [MOD_WIDTH-1:0] MOD_OUT; 31 | 32 | reg [ACCUM_WIDTH-1:0] accum; 33 | wire [ACCUM_WIDTH-1:0] accum_shift; 34 | 35 | reg [COUNT_WIDTH-1:0] count; 36 | 37 | assign accum_shift = accum >> SHIFT; 38 | assign MOD_OUT = accum_shift[MOD_WIDTH-1:0]; 39 | 40 | always @(posedge CLKREF) begin 41 | if (RST) begin 42 | accum <= 0; 43 | count <= 0; 44 | end 45 | else if (SSC_EN) begin 46 | if (count < (COUNT_LIM >> 1)) begin 47 | accum <= accum + STEP; 48 | end 49 | else begin 50 | accum <= accum - STEP; 51 | end 52 | 53 | if (count >= COUNT_LIM-1) begin 54 | count <= 0; 55 | accum <= 0; //ensure accum is reset every cycle regardless of bugs 56 | end 57 | else begin 58 | count <= count +1; 59 | end 60 | end 61 | end 62 | 63 | endmodule 64 | `endif 65 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/dco_CC.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | 3 | module dco_CC (IN, IP, ON, OP, EN); 4 | input IN; 5 | input IP; 6 | output ON; 7 | output OP; 8 | input EN; 9 | endmodule 10 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/dco_FC.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | // 3 | 4 | module dco_FC (IN, IP,EN); 5 | input IN; 6 | input IP; 7 | input EN; 8 | endmodule 9 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/synth_pll_dco_interp.v: -------------------------------------------------------------------------------- 1 | module synth_pll_dco_interp ( INA, INB, IPA, IPB, ON, OP); 2 | input INA, INB, IPA, IPB; 3 | output ON, OP; 4 | wire int1, int2; 5 | 6 | INV_X2N_A10P5PP84TR_C14 inva1 (.A(INA), .Y(int1) ); 7 | INV_X2N_A10P5PP84TR_C14 inva2 (.A(INB), .Y(int1) ); 8 | INV_X2N_A10P5PP84TR_C14 inva3 (.A(int1), .Y(ON) ); 9 | 10 | INV_X2N_A10P5PP84TR_C14 invb1 (.A(IPA), .Y(int2) ); 11 | INV_X2N_A10P5PP84TR_C14 invb2 (.A(IPB), .Y(int2) ); 12 | INV_X2N_A10P5PP84TR_C14 invb3 (.A(int2), .Y(OP) ); 13 | endmodule 14 | 15 | module synth_pll_dco_interp_40 ( INA, INB, IPA, IPB, ON, OP); 16 | input INA, INB, IPA, IPB; 17 | output ON, OP; 18 | wire int1, int2; 19 | 20 | INVD2BWP12T inva1 (.I(INA), .ZN(int1) ); 21 | INVD2BWP12T inva2 (.I(INB), .ZN(int1) ); 22 | INVD2BWP12T inva3 (.I(int1), .ZN(ON) ); 23 | 24 | INVD2BWP12T invb1 (.I(IPA), .ZN(int2) ); 25 | INVD2BWP12T invb2 (.I(IPB), .ZN(int2) ); 26 | INVD2BWP12T invb3 (.I(int2), .ZN(OP) ); 27 | endmodule 28 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/BLE/ble_top/synth_pll_dco_outbuff.v: -------------------------------------------------------------------------------- 1 | module synth_pll_dco_outbuff ( IN, IP, ON, OP); 2 | input IN, IP; 3 | output ON, OP; 4 | wire int1, int2; 5 | 6 | INV_X2N_A10P5PP84TR_C14 inva1 (.A(IN), .Y(int1) ); 7 | INV_X2N_A10P5PP84TR_C14 inva2 (.A(IN), .Y(int1) ); 8 | INV_X2N_A10P5PP84TR_C14 inva3 (.A(int1), .Y(ON) ); 9 | 10 | INV_X2N_A10P5PP84TR_C14 invb1 (.A(IP), .Y(int2) ); 11 | INV_X2N_A10P5PP84TR_C14 invb2 (.A(IP), .Y(int2) ); 12 | INV_X2N_A10P5PP84TR_C14 invb3 (.A(int2), .Y(OP) ); 13 | endmodule 14 | 15 | module synth_pll_dco_outbuff_40 ( in, ip, on, op); 16 | input in, ip; 17 | output on, op; 18 | wire int1, int2; 19 | 20 | INVD2BWP12T inva1 (.I(in), .ZN(int1) ); 21 | INVD2BWP12T inva2 (.I(in), .ZN(int1) ); 22 | INVD2BWP12T inva3 (.I(int1), .ZN(on) ); 23 | 24 | INVD2BWP12T invb1 (.I(ip), .ZN(int2) ); 25 | INVD2BWP12T invb2 (.I(ip), .ZN(int2) ); 26 | INVD2BWP12T invb3 (.I(int2), .ZN(op) ); 27 | endmodule 28 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/dummy_pex_hspicesim.mk: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # format for making form_Makefile 3 | # This is the point of modification if any needed for Makefile 4 | # make presim: generates model 5 | #======================================================================= 6 | 7 | pex_hspicesim: 8 | cd $(HSPICE_DIR)/pex_DUMP_result; hspice -mp 4 -i ./../pex_TB/tb_10ring10_osc18_FC30.sp 9 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_dump_irun.tcl: -------------------------------------------------------------------------------- 1 | database -open tb_pll_top -shm -event 2 | ##probe -create tb_top -all -dynamic -memories -depth all -tasks -shm -database tb_top 3 | probe -create tb_pll_top -all -dynamic -memories -depth all -tasks -functions -shm -database tb_pll_top 4 | run 5 | #exit 6 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_flist.f: -------------------------------------------------------------------------------- 1 | ./verilog/tb_pll_top.sv 2 | ./verilog/pll_top.sv 3 | ./verilog/pll_controller.sv 4 | ./verilog/ssc_generator.v 5 | ./../tdc_counter_v2/verilog/tdc_counter.sv 6 | ./verilog/functions.v 7 | ./verilog/analog_core.v 8 | ./verilog/dco_model_noise.v 9 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_flist_beh.f: -------------------------------------------------------------------------------- 1 | ./verilog/tb_pll_top.sv 2 | @@ ./verilog/@dn.sv 3 | ./verilog/pll_controller.sv 4 | ./verilog/ssc_generator.v 5 | ./verilog/tdc_counter.sv 6 | ./verilog/functions.v 7 | ./verilog/analog_core.v 8 | ./verilog/dco_model_noise.v 9 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_form_Makefile: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # format for making form_Makefile 3 | # This is the point of modification if any needed for Makefile 4 | # make presim: generates model 5 | #======================================================================= 6 | 7 | @@ HOME_PATH= @hp 8 | @@ HSPICE_DIR= @sd 9 | 10 | 11 | clean_everything: 12 | cd $(HOME_PATH)$(HSPICE_DIR)/NETLIST; rm *.sp 13 | cd $(HOME_PATH)$(HSPICE_DIR)/TB; rm *.sp 14 | cd $(HOME_PATH)$(HSPICE_DIR)/TBrf; rm *.sp 15 | cd $(HOME_PATH)$(HSPICE_DIR)/DUMP_result; rm * 16 | cd $(HOME_PATH)$(HSPICE_DIR)/DUMPrf_result; rm * 17 | 18 | clean_v: 19 | cd ./VERILOG; rm synth_pll* 20 | cd ./VERILOG; rm spec* 21 | apr_clean: 22 | rm -f apr/*.apr.v 23 | 24 | ###hspicesim: 25 | ###@@#@@ @s2 @RA; hspice -mp @mp -i @TAtb_@mdring@mt_o@nt_FC@nf.sp 26 | 27 | hspicesim: 28 | @@#@@ @s2 $(HOME_PATH)$(HSPICE_DIR)/DUMP_result; hspice -mp @mp -i ./../TB/tb_@mdring@mt_o@nt_FC@nf.sp 29 | 30 | #1 hspicerfsim: 31 | @@##@@ @s1 $(HOME_PATH)$(HSPICE_DIR)/DUMPrf_result; hspicerf -mp @rm -i ./../TBrf/tbrf_@rdring@mr_o@nr_fc@Nf.sp 32 | 33 | modeling: 34 | @@ cd $(HOME_PATH); python ./pymodules/MDL_GEN_@tn.py 35 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_hspicesim.mk: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # format for making form_Makefile 3 | # This is the point of modification if any needed for Makefile 4 | # make presim: generates model 5 | #======================================================================= 6 | 7 | @@ hspicesim@TN: 8 | @@ @s2 $(HSPICE_DIR_@tn)/DUMP_result; hspice -mp @mp -i ./../TB/tb_@mdring@mt_o@nt_FC@nf.sp 9 | 10 | #1 hspicerfsim: 11 | #@@ @s1 $(HSPICE_DIR)/DUMPrf_result; hspicerf -mp @rm -i ./../TBrf/tbrf_@rdring@mr_o@nr_fc@Nf.sp 12 | 13 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_model.json: -------------------------------------------------------------------------------- 1 | { 2 | "pll_model_constants": 3 | { 4 | @@ "CF":@CF, 5 | @@ "Cc":@Cc, 6 | @@ "Cf":@Cf, 7 | @@ "Iavg_const":@Ic 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pex_hspicesim.mk: -------------------------------------------------------------------------------- 1 | #======================================================================= 2 | # format for making form_Makefile 3 | # This is the point of modification if any needed for Makefile 4 | # make presim: generates model 5 | #======================================================================= 6 | 7 | pex_hspicesim: 8 | @@ @s2 $(HSPICE_DIR)/@Rd; hspice -mp @mp -i ./../@Td/tb_@mdring@mt_o@nt_FC@nf.sp 9 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pex_model.json: -------------------------------------------------------------------------------- 1 | { 2 | "pll_pex_model_constants": 3 | { 4 | @@ "mult_Con":@mo, 5 | @@ "mult_Coff":@mf, 6 | @@ "Iavg_const":@Ic 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_pll_dc.filelist.tcl: -------------------------------------------------------------------------------- 1 | @@ set SVERILOG_SOURCE_FILES "$::env(DESIGN_ROOT_DIR)/src/@DN.v $::env(DESIGN_ROOT_DIR)/src/synth_dco.v $::env(DESIGN_ROOT_DIR)/src/PLL_CONTROLLER_TDC_COUNTER.v $::env(DESIGN_ROOT_DIR)/src/PLL_CONTROLLER.v $::env(DESIGN_ROOT_DIR)/src/TDC_COUNTER.v $::env(DESIGN_ROOT_DIR)/src/dco_CC.v $::env(DESIGN_ROOT_DIR)/src/dco_FC.v $::env(DESIGN_ROOT_DIR)/src/synth_pll_dco_interp.v $::env(DESIGN_ROOT_DIR)/src/synth_pll_dco_outbuff.v $::env(DESIGN_ROOT_DIR)/src/FUNCTIONS.v" 2 | set NETLIST_SOURCE_FILES "" 3 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_run: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | irun -64bit \ 3 | -elaborate \ 4 | -sv \ 5 | -sem2009 \ 6 | -sysv_ext +.vh \ 7 | -access +rwc \ 8 | -timescale 1ps/1fs \ 9 | @@ -f ./@fl.f \ 10 | -l irun_comp.log 11 | 12 | #-define BEH \ 13 | #-tfile embtdc_dis.tfile \ 14 | #-notimingcheck \ 15 | #-define TDC_APR \ 16 | #-define APR \ 17 | #-define SYN \ 18 | 19 | irun -64bit \ 20 | -R \ 21 | -sv \ 22 | -sem2009 \ 23 | -access +rwc \ 24 | -input dump_irun.tcl \ 25 | +delay_mode_unit \ 26 | -timescale 1ps/1fs \ 27 | -l irun_run.log 28 | 29 | 30 | 31 | #diff goldenbrick/gb_out_mult_add_res_reuse.txt ./testbench_mult_add_res_reuse.txt | tee ./diff_functional_mult_add_res_reuse.txt #5 32 | -------------------------------------------------------------------------------- /generators/pll-gen/formats/form_spec_out.json: -------------------------------------------------------------------------------- 1 | { 2 | "generator": "pll", 3 | "input_specifications": 4 | { 5 | "Fnom_min":1.05e8, 6 | "Fnom_max":1.20e8, 7 | "FCR_min":1 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /generators/pll-gen/pll_pex_model_gf12lp.json: -------------------------------------------------------------------------------- 1 | { 2 | "pll_model_constants": 3 | { 4 | "CF":2.720805e-13, 5 | "Cc":4.529067e-11, 6 | "Cf":1.803006e-11, 7 | "Iavg_const":7.625868e+05 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /generators/pll-gen/pll_pex_model_gf12lp_FCv2.json: -------------------------------------------------------------------------------- 1 | { 2 | "pll_model_constants": 3 | { 4 | "CF":2.835483e-12, 5 | "Cc":4.034064e-11, 6 | "Cf":1.535166e-11, 7 | "Iavg_const":8.435114e+05 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /generators/pll-gen/publicModel/gf12lp_pll_model.json: -------------------------------------------------------------------------------- 1 | { 2 | "pll_model_constants": 3 | { 4 | "CF":5.344763e-14, 5 | "Cc":6.366690e-12, 6 | "Cf":1.817906e-12, 7 | "Iavg_const":3.193209e+07 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /generators/pll-gen/publicModel/tsmc65lp_pll_model.json: -------------------------------------------------------------------------------- 1 | { 2 | "pll_model_constants": { 3 | "CF": 2.965883e-13, 4 | "Cc": 4.36437e-11, 5 | "Cf": 9.941385e-13, 6 | "Iavg_const": 10082590.0, 7 | "1M_PN_const": 1.4e-11, 8 | "A_CC": 16.92, 9 | "A_FC": 6.84 10 | }, 11 | "pex coefficients": { 12 | "mult_Con": 2.53, 13 | "mult_Coff": 2.53, 14 | "pex_Iavg_const": 10082590.0 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /generators/pll-gen/pymodules/.gitignore: -------------------------------------------------------------------------------- 1 | test* 2 | bu* 3 | ignore_* 4 | *swp 5 | *swo 6 | -------------------------------------------------------------------------------- /generators/pll-gen/std_cell_names.json: -------------------------------------------------------------------------------- 1 | { 2 | "tsmc65lp": 3 | { 4 | "buf_small":"BUFH_X2M_placeHolder", 5 | "buf_big":"BUFH_X9M_placeHolder", 6 | "bufz":"BUFZ_X4M_placeHolder", 7 | "tdc_dff":"DFFRPQ_X0P5M_placeHolder", 8 | "buf1_name":"placeHolder", 9 | "buf2_name":"placeHolder", 10 | "buf3_name":"placeHolder", 11 | "bufz":"BUFZ_X4M_placeHolder", 12 | "Height":1.8 13 | }, 14 | "gf12lp": 15 | { 16 | "10.5": 17 | { 18 | "buf_small":"BUFH_X2N_placeHolder", 19 | "buf_big":"BUFH_X8N_placeHolder", 20 | "buf1_name":"BUFH_X8N_placeHolder", 21 | "buf2_name":"BUFH_X10N_placeHolder", 22 | "buf3_name":"BUFH_X10N_placeHolder", 23 | "tdc_dff":"DFFQ_X1N_placeHolder", 24 | "bufz":"placeHolder", 25 | "Height":0.672 26 | }, 27 | "9": 28 | { 29 | "buf_small":"BUFH_X2N_placeHolder", 30 | "buf_big":"BUFH_X8N_placeHolder", 31 | "buf1_name":"BUFH_X8N_placeHolder", 32 | "buf2_name":"BUFH_X10N_placeHolder", 33 | "buf3_name":"BUFH_X10N_placeHolder", 34 | "tdc_dff":"DFFQ_X1N_placeHolder", 35 | "bufz":"placeHolder", 36 | "Height":0.576 37 | } 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /generators/pll-gen/std_cell_names_public.json: -------------------------------------------------------------------------------- 1 | { 2 | "tsmc65lp": 3 | { 4 | "buf_small":"BUFH_X2M_placeHolder", 5 | "buf_big":"BUFH_X9M_placeHolder", 6 | "bufz":"BUFZ_X4M_placeHolder", 7 | "tdc_dff":"DFFRPQ_X0P5M_placeHolder", 8 | "buf1_name":"placeHolder", 9 | "buf2_name":"placeHolder", 10 | "buf3_name":"placeHolder", 11 | "bufz":"BUFZ_X4M_placeHolder", 12 | "Height":1.8 13 | }, 14 | "gf12lp": 15 | { 16 | "10.5": 17 | { 18 | "buf_small":"BUFH_X2N_placeHolder", 19 | "buf_big":"BUFH_X8N_placeHolder", 20 | "buf1_name":"BUFH_X8N_placeHolder", 21 | "buf2_name":"BUFH_X10N_placeHolder", 22 | "buf3_name":"BUFH_X10N_placeHolder", 23 | "tdc_dff":"DFFQ_X1N_placeHolder", 24 | "bufz":"placeHolder", 25 | "Height":0.672 26 | }, 27 | "9": 28 | { 29 | "buf_small":"BUFH_X2N_placeHolder", 30 | "buf_big":"BUFH_X8N_placeHolder", 31 | "buf1_name":"BUFH_X8N_placeHolder", 32 | "buf2_name":"BUFH_X10N_placeHolder", 33 | "buf3_name":"BUFH_X10N_placeHolder", 34 | "tdc_dff":"DFFQ_X1N_placeHolder", 35 | "bufz":"placeHolder", 36 | "Height":0.576 37 | } 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /generators/pll-gen/test_alpha12.json: -------------------------------------------------------------------------------- 1 | { 2 | "generator": "pll-gen", 3 | "module_name": "pll7", 4 | "specifications": 5 | { 6 | "frequency": 7 | { 8 | "reference":10e6, 9 | "nom_min":0.80e9, 10 | "nom_max":0.88e9, 11 | "max":1e9, 12 | "min":0.7e9, 13 | "res":50e3 14 | }, 15 | "FCR_min":0.5, 16 | "dco_PWR": 15 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /generators/pll-gen/test_beta65.json: -------------------------------------------------------------------------------- 1 | { 2 | "generator": "pll-gen", 3 | "module_name": "pll6", 4 | "specifications": 5 | { 6 | "frequency": 7 | { 8 | "reference":10e6, 9 | "nom_min":2.80e8, 10 | "nom_max":3.00e8, 11 | "max":480e6, 12 | "min":100e6, 13 | "res":30e3 14 | }, 15 | "FCR_min":1, 16 | "inband_PN":-80, 17 | "dco_PWR":34 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/:run: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | irun -64bit \ 3 | -elaborate \ 4 | -sv \ 5 | -sem2009 \ 6 | -sysv_ext +.vh \ 7 | -access +rwc \ 8 | -timescale 1ps/1fs \ 9 | -f ./flist_beh.f \ 10 | -l irun_comp.log 11 | 12 | #-define BEH \ 13 | #-tfile embtdc_dis.tfile \ 14 | #-notimingcheck \ 15 | #-define TDC_APR \ 16 | #-define APR \ 17 | #-define SYN \ 18 | 19 | irun -64bit \ 20 | -R \ 21 | -sv \ 22 | -sem2009 \ 23 | -access +rwc \ 24 | -input dump_irun.tcl \ 25 | +delay_mode_unit \ 26 | -timescale 1ps/1fs \ 27 | -l irun_run.log 28 | 29 | 30 | 31 | #diff goldenbrick/gb_out_mult_add_res_reuse.txt ./testbench_mult_add_res_reuse.txt | tee ./diff_functional_mult_add_res_reuse.txt #5 32 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/:run_beh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | irun -64bit \ 3 | -elaborate \ 4 | -sv \ 5 | -sem2009 \ 6 | -sysv_ext +.vh \ 7 | -access +rwc \ 8 | -timescale 1ps/1fs \ 9 | -f ./flist_beh.f \ 10 | -l irun_comp.log 11 | 12 | #-define BEH \ 13 | #-tfile embtdc_dis.tfile \ 14 | #-notimingcheck \ 15 | #-define TDC_APR \ 16 | #-define APR \ 17 | #-define SYN \ 18 | 19 | irun -64bit \ 20 | -R \ 21 | -sv \ 22 | -sem2009 \ 23 | -access +rwc \ 24 | -input dump_irun.tcl \ 25 | +delay_mode_unit \ 26 | -timescale 1ps/1fs \ 27 | -l irun_run.log 28 | 29 | 30 | 31 | #diff goldenbrick/gb_out_mult_add_res_reuse.txt ./testbench_mult_add_res_reuse.txt | tee ./diff_functional_mult_add_res_reuse.txt #5 32 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/:run: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | irun -64bit \ 3 | -elaborate \ 4 | -sv \ 5 | -sem2009 \ 6 | -sysv_ext +.vh \ 7 | -access +rwc \ 8 | -timescale 1ns/1ps \ 9 | -f ./flist.f \ 10 | -l irun_comp.log 11 | 12 | irun -64bit \ 13 | -R \ 14 | -sv \ 15 | -sem2009 \ 16 | -access +rwc \ 17 | -input dump_irun.tcl \ 18 | +delay_mode_unit \ 19 | -timescale 1ns/1ps \ 20 | -l irun_run.log 21 | 22 | 23 | 24 | #diff goldenbrick/gb_out_mult_add_res_reuse.txt ./testbench_mult_add_res_reuse.txt | tee ./diff_functional_mult_add_res_reuse.txt #5 25 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/.history.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/.history.lock -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/history: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | 5 | s1::(09Jan2020:16:49:47):( irun -64bit -elaborate -sv -sem2009 -sysv_ext +.vh -access +rwc -timescale 1ns/1ps -f ./flist.f -l irun_comp.log ) 6 | s2::(09Jan2020:16:49:50):( irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log ) 7 | s3::(09Jan2020:16:52:22):( irun -64bit -elaborate -sv -sem2009 -sysv_ext +.vh -access +rwc -timescale 1ns/1ps -f ./flist.f -l irun_comp.log ) 8 | s4::(09Jan2020:16:52:23):( irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log ) 9 | s5::(09Jan2020:16:54:03):( irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log ) 10 | s6::(09Jan2020:16:56:49):( irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log ) 11 | s7::(09Jan2020:17:04:42):( irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log ) 12 | s8::(26Jul2020:13:49:34):( irun -64bit -elaborate -sv -sem2009 -sysv_ext +.vh -access +rwc -timescale 1ns/1ps -f ./flist.f -l irun_comp.log ) 13 | s9::(26Jul2020:13:49:36):( irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log ) 14 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.nclib.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.nclib.lock -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncrun.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncrun.lock -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncv.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncv.lock -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts: -------------------------------------------------------------------------------- 1 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/FUNCTIONS.v 2 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/tb/TB_PLL_CONTROLLER_TDC_COUNTER.sv 3 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/DCO_MODEL.v 4 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/TDC_COUNTER.v 5 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/PLL_CONTROLLER_TDC_COUNTER.v 6 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/PLL_CONTROLLER.v 7 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/ANALOG_CORE.v 8 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/SSC_GENERATOR.v 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/OVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/UVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/bind.lst.lnx8664: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/bind.lst.lnx8664 -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /usr/caen/incisive-15.20.005/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/files.ts: -------------------------------------------------------------------------------- 1 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/tb/TB_PLL_CONTROLLER_TDC_COUNTER.sv 2 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/ANALOG_CORE.v 3 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/PLL_CONTROLLER_TDC_COUNTER.v 4 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/PLL_CONTROLLER.v 5 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/TDC_COUNTER.v 6 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/DCO_MODEL.v 7 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/SSC_GENERATOR.v 8 | 1568666801 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/FUNCTIONS.v 9 | 1589851407 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/differential_dco/tb/TB_PLL_CONTROLLER_TDC_COUNTER.sv 10 | 1589851407 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/differential_dco/verilog/ANALOG_CORE.v 11 | 1589851407 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/differential_dco/verilog/PLL_CONTROLLER_TDC_COUNTER.v 12 | 1589851407 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/differential_dco/verilog/PLL_CONTROLLER.v 13 | 1589851407 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/differential_dco/verilog/TDC_COUNTER.v 14 | 1589851407 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/differential_dco/verilog/DCO_MODEL.v 15 | 1589851407 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/differential_dco/verilog/SSC_GENERATOR.v 16 | 1589851407 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/differential_dco/verilog/FUNCTIONS.v 17 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473/irun.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -64bit 6 | -R 7 | -sv 8 | -sem2009 9 | -access 10 | +rwc 11 | -input 12 | dump_irun.tcl 13 | +delay_mode_unit 14 | -timescale 15 | 1ns/1ps 16 | -l 17 | irun_run.log 18 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473/ncsim.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | +delay_mode_unit 6 | -INPUT 7 | dump_irun.tcl 8 | -MESSAGES 9 | +EMGRLOG 10 | irun_run.log 11 | -XLSTIME 12 | 1578606843 13 | -XLKEEP 14 | -XLMODE 15 | ./INCA_libs/irun.lnx8664.15.20.nc 16 | -RUNMODE 17 | -CDSLIB 18 | ./INCA_libs/irun.lnx8664.15.20.nc/cds.lib 19 | -HDLVAR 20 | ./INCA_libs/irun.lnx8664.15.20.nc/hdl.var 21 | -XLNAME 22 | irun 23 | -XLVERSION 24 | "TOOL: irun(64) 15.20-s005" 25 | -CMDPSIM 26 | -XLNAME 27 | ./INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473 28 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_27473/ncsim.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: irun 4 | # Do not modify this file 5 | # 6 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | .vh => systemverilog,\ 62 | DEF => unknown\ 63 | ) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | , .vh => vh \ 86 | ) 87 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/irun.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -64bit 6 | -elaborate 7 | -sv 8 | -sem2009 9 | -sysv_ext 10 | +.vh 11 | -access 12 | +rwc 13 | -timescale 14 | 1ns/1ps 15 | -f 16 | ./flist.f 17 | -l 18 | irun_comp.log 19 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -SEM2009 6 | -ACCESS 7 | +rwc 8 | -timescale 9 | 1ns/1ps 10 | -MESSAGES 11 | -XLMODE 12 | ./INCA_libs/irun.lnx8664.15.20.nc 13 | -RUNMODE 14 | -CDSLIB 15 | ./INCA_libs/irun.lnx8664.15.20.nc/cds.lib 16 | -HDLVAR 17 | ./INCA_libs/irun.lnx8664.15.20.nc/hdl.var 18 | -WORK 19 | worklib 20 | -HASXLMODE 21 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: irun 4 | # Do not modify this file 5 | # 6 | #<< : <#3 irun:/afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/INCA_libs/irun.lnx8664.15.20.nc>#> <#3 irun:./INCA_libs/irun.lnx8664.15.20.nc>#> 7 | setenv NCRUNMODE "irun:./INCA_libs/irun.lnx8664.15.20.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -SEM2009 6 | -ACCESS 7 | +rwc 8 | -timescale 9 | 1ns/1ps 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -XLMODE 6 | ./INCA_libs/irun.lnx8664.15.20.nc 7 | -RUNMODE 8 | -sv 9 | ./tb/TB_PLL_CONTROLLER_TDC_COUNTER.sv 10 | ./verilog/ANALOG_CORE.v 11 | ./verilog/PLL_CONTROLLER_TDC_COUNTER.v 12 | ./verilog/PLL_CONTROLLER.v 13 | ./verilog/TDC_COUNTER.v 14 | ./verilog/DCO_MODEL.v 15 | ./verilog/SSC_GENERATOR.v 16 | ./verilog/FUNCTIONS.v 17 | -CDSLIB 18 | ./INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib 19 | -HDLVAR 20 | ./INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var 21 | -MESSAGES 22 | -UPDATE 23 | -XLLIBSTORE 24 | ./INCA_libs/irun.lnx8664.15.20.nc/xllibs 25 | -ALLOWUNBOUND 26 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: irun 4 | # Do not modify this file 5 | # 6 | #<< : <#3 irun:/afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc>#> <#3 irun:./INCA_libs/irun.lnx8664.15.20.nc>#> 7 | setenv NCRUNMODE "irun:./INCA_libs/irun.lnx8664.15.20.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.files: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/tb/TB_PLL_CONTROLLER_TDC_COUNTER.sv 6 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/ANALOG_CORE.v 7 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/PLL_CONTROLLER_TDC_COUNTER.v 8 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/PLL_CONTROLLER.v 9 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/TDC_COUNTER.v 10 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/DCO_MODEL.v 11 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/SSC_GENERATOR.v 12 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/public/fasoc/generators/pll-gen/tsmc65lp/verilog_sim/verilog/FUNCTIONS.v 13 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -sv 6 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/irun.nc: -------------------------------------------------------------------------------- 1 | irun.lnx8664.12.20.nc -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/.cdsvmod: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/.cdsvmod -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/.inca.db.150.lnx8664: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/cdsinfo.tag: -------------------------------------------------------------------------------- 1 | CDSLIBRARY 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/inca.lnx8664.150.pak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/differential_dco/INCA_libs/worklib/inca.lnx8664.150.pak -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/dump_irun.tcl: -------------------------------------------------------------------------------- 1 | database -open TB_PLL_CONTROLLER_TDC_COUNTER -shm -event 2 | ##probe -create tb_top -all -dynamic -memories -depth all -tasks -shm -database tb_top 3 | probe -create TB_PLL_CONTROLLER_TDC_COUNTER -all -dynamic -memories -depth all -tasks -functions -shm -database TB_PLL_CONTROLLER_TDC_COUNTER 4 | run 5 | #exit 6 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/flist.f: -------------------------------------------------------------------------------- 1 | ./tb/TB_PLL_CONTROLLER_TDC_COUNTER.sv 2 | ./verilog/ANALOG_CORE.v 3 | ./verilog/PLL_CONTROLLER_TDC_COUNTER.v 4 | ./verilog/PLL_CONTROLLER.v 5 | ./verilog/TDC_COUNTER.v 6 | ./verilog/DCO_MODEL.v 7 | ./verilog/SSC_GENERATOR.v 8 | ./verilog/FUNCTIONS.v 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/irun.history: -------------------------------------------------------------------------------- 1 | s1(29Apr2019:21:13:19): irun :run 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/irun.key: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/differential_dco/irun.key -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/irun_comp.history: -------------------------------------------------------------------------------- 1 | s1(09Jan2020:16:49:47): irun -64bit -elaborate -sv -sem2009 -sysv_ext +.vh -access +rwc -timescale 1ns/1ps -f ./flist.f -l irun_comp.log 2 | s2(09Jan2020:16:49:50): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 3 | s3(09Jan2020:16:52:22): irun -64bit -elaborate -sv -sem2009 -sysv_ext +.vh -access +rwc -timescale 1ns/1ps -f ./flist.f -l irun_comp.log 4 | s4(09Jan2020:16:52:23): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 5 | s5(09Jan2020:16:54:03): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 6 | s6(09Jan2020:16:56:49): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 7 | s7(09Jan2020:17:04:42): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 8 | s8(26Jul2020:13:49:34): irun -64bit -elaborate -sv -sem2009 -sysv_ext +.vh -access +rwc -timescale 1ns/1ps -f ./flist.f -l irun_comp.log 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/irun_run.history: -------------------------------------------------------------------------------- 1 | s1(09Jan2020:16:49:47): irun -64bit -elaborate -sv -sem2009 -sysv_ext +.vh -access +rwc -timescale 1ns/1ps -f ./flist.f -l irun_comp.log 2 | s2(09Jan2020:16:49:50): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 3 | s3(09Jan2020:16:52:22): irun -64bit -elaborate -sv -sem2009 -sysv_ext +.vh -access +rwc -timescale 1ns/1ps -f ./flist.f -l irun_comp.log 4 | s4(09Jan2020:16:52:23): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 5 | s5(09Jan2020:16:54:03): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 6 | s6(09Jan2020:16:56:49): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 7 | s7(09Jan2020:17:04:42): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 8 | s8(26Jul2020:13:49:34): irun -64bit -elaborate -sv -sem2009 -sysv_ext +.vh -access +rwc -timescale 1ns/1ps -f ./flist.f -l irun_comp.log 9 | s9(26Jul2020:13:49:36): irun -64bit -R -sv -sem2009 -access +rwc -input dump_irun.tcl +delay_mode_unit -timescale 1ns/1ps -l irun_run.log 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/pll_lock_report.txt: -------------------------------------------------------------------------------- 1 | fine lock detected on 213592 ns -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/FUNCTIONS.v: -------------------------------------------------------------------------------- 1 | // Functions 2 | 3 | function automatic integer func_clog2; 4 | // task automatic func_clog2; 5 | // calculate how many bits are needed to express the input value N 6 | 7 | input integer func_clog2_N; 8 | integer func_clog2_ii; 9 | 10 | // keep going until 2^ii is larger than N 11 | for (func_clog2_ii=0;2**func_clog2_ii= func_MAX_B) 24 | func_MAX = func_MAX_A; 25 | else 26 | func_MAX = func_MAX_B; 27 | 28 | endfunction 29 | 30 | 31 | function automatic integer func_MIN; 32 | // return the max of A or B 33 | 34 | input integer func_MIN_A; 35 | input integer func_MIN_B; 36 | 37 | if (func_MIN_A >= func_MIN_B) 38 | func_MIN = func_MIN_A; 39 | else 40 | func_MIN = func_MIN_B; 41 | 42 | endfunction 43 | 44 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/SSC_GENERATOR.v: -------------------------------------------------------------------------------- 1 | `ifndef __SSC_GENERATOR__ 2 | `define __SSC_GENERATOR__ 3 | 4 | `timescale 1ns/1ps 5 | 6 | module SSC_GENERATOR( 7 | CLKREF, 8 | RST, 9 | SSC_EN, 10 | COUNT_LIM, 11 | STEP, 12 | SHIFT, 13 | MOD_OUT 14 | ); 15 | 16 | // Functions 17 | 18 | // Parameters 19 | parameter COUNT_WIDTH = 12; 20 | parameter ACCUM_WIDTH = 16; 21 | parameter MOD_WIDTH = 5; 22 | parameter SHIFT_WIDTH = func_clog2(ACCUM_WIDTH-1); 23 | 24 | input CLKREF, RST, SSC_EN; 25 | input [COUNT_WIDTH-1:0] COUNT_LIM; 26 | input [3:0] STEP; 27 | input [SHIFT_WIDTH-1:0] SHIFT; 28 | 29 | output [MOD_WIDTH-1:0] MOD_OUT; 30 | 31 | reg [ACCUM_WIDTH-1:0] accum; 32 | wire [ACCUM_WIDTH-1:0] accum_shift; 33 | 34 | reg [COUNT_WIDTH-1:0] count; 35 | 36 | assign accum_shift = accum >> SHIFT; 37 | assign MOD_OUT = accum_shift[MOD_WIDTH-1:0]; 38 | 39 | always @(posedge CLKREF) begin 40 | if (RST) begin 41 | accum <= 0; 42 | count <= 0; 43 | end 44 | else if (SSC_EN) begin 45 | if (count < (COUNT_LIM >> 1)) begin 46 | accum <= accum + STEP; 47 | end 48 | else begin 49 | accum <= accum - STEP; 50 | end 51 | 52 | if (count >= COUNT_LIM-1) begin 53 | count <= 0; 54 | accum <= 0; //ensure accum is reset every cycle regardless of bugs 55 | end 56 | else begin 57 | count <= count +1; 58 | end 59 | end 60 | end 61 | 62 | endmodule 63 | `endif 64 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/dco_CC.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | 3 | module dco_CC (IN, IP, ON, OP, EN); 4 | input IN; 5 | input IP; 6 | output ON; 7 | output OP; 8 | input EN; 9 | endmodule 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/dco_FC.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | // 3 | 4 | module dco_FC (IN, IP,EN); 5 | input IN; 6 | input IP; 7 | input EN; 8 | endmodule 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/synth_pll_dco_interp.v: -------------------------------------------------------------------------------- 1 | module synth_pll_dco_interp ( INA, INB, IPA, IPB, ON, OP); 2 | input INA, INB, IPA, IPB; 3 | output ON, OP; 4 | wire int1, int2; 5 | 6 | INV_X2M_A9TR inva1 (.A(INA), .Y(int1) ); 7 | INV_X2M_A9TR inva2 (.A(INB), .Y(int1) ); 8 | INV_X2M_A9TR inva3 (.A(int1), .Y(ON) ); 9 | 10 | INV_X2M_A9TR invb1 (.A(IPA), .Y(int2) ); 11 | INV_X2M_A9TR invb2 (.A(IPB), .Y(int2) ); 12 | INV_X2M_A9TR invb3 (.A(int2), .Y(OP) ); 13 | endmodule 14 | 15 | module synth_pll_dco_interp_40 ( INA, INB, IPA, IPB, ON, OP); 16 | input INA, INB, IPA, IPB; 17 | output ON, OP; 18 | wire int1, int2; 19 | 20 | INVD2BWP12T inva1 (.I(INA), .ZN(int1) ); 21 | INVD2BWP12T inva2 (.I(INB), .ZN(int1) ); 22 | INVD2BWP12T inva3 (.I(int1), .ZN(ON) ); 23 | 24 | INVD2BWP12T invb1 (.I(IPA), .ZN(int2) ); 25 | INVD2BWP12T invb2 (.I(IPB), .ZN(int2) ); 26 | INVD2BWP12T invb3 (.I(int2), .ZN(OP) ); 27 | endmodule 28 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/differential_dco/verilog/synth_pll_dco_outbuff.v: -------------------------------------------------------------------------------- 1 | module synth_pll_dco_outbuff ( IN, IP, ON, OP); 2 | input IN, IP; 3 | output ON, OP; 4 | wire int1, int2; 5 | 6 | INV_X2M_A9TR inva1 (.A(IN), .Y(int1) ); 7 | INV_X2M_A9TR inva2 (.A(IN), .Y(int1) ); 8 | INV_X2M_A9TR inva3 (.A(int1), .Y(ON) ); 9 | 10 | INV_X2M_A9TR invb1 (.A(IP), .Y(int2) ); 11 | INV_X2M_A9TR invb2 (.A(IP), .Y(int2) ); 12 | INV_X2M_A9TR invb3 (.A(int2), .Y(OP) ); 13 | endmodule 14 | 15 | module synth_pll_dco_outbuff_40 ( in, ip, on, op); 16 | input in, ip; 17 | output on, op; 18 | wire int1, int2; 19 | 20 | INVD2BWP12T inva1 (.I(in), .ZN(int1) ); 21 | INVD2BWP12T inva2 (.I(in), .ZN(int1) ); 22 | INVD2BWP12T inva3 (.I(int1), .ZN(on) ); 23 | 24 | INVD2BWP12T invb1 (.I(ip), .ZN(int2) ); 25 | INVD2BWP12T invb2 (.I(ip), .ZN(int2) ); 26 | INVD2BWP12T invb3 (.I(int2), .ZN(op) ); 27 | endmodule 28 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/dump_irun.tcl: -------------------------------------------------------------------------------- 1 | database -open tb_pll_top -shm -event 2 | ##probe -create tb_top -all -dynamic -memories -depth all -tasks -shm -database tb_top 3 | probe -create tb_pll_top -all -dynamic -memories -depth all -tasks -functions -shm -database tb_pll_top 4 | run 5 | #exit 6 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/flist_beh.f: -------------------------------------------------------------------------------- 1 | ./verilog/tb_pll_top.sv 2 | ./verilog/pll7.sv 3 | ./verilog/pll_controller.sv 4 | ./verilog/ssc_generator.v 5 | ./verilog/tdc_counter.sv 6 | ./verilog/functions.v 7 | ./verilog/analog_core.v 8 | ./verilog/dco_model_noise.v 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/:run: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | irun -64bit \ 3 | -elaborate \ 4 | -sv \ 5 | -sem2009 \ 6 | -sysv_ext +.vh \ 7 | -access +rwc \ 8 | -timescale 1ns/1ps \ 9 | -f ./flist.f \ 10 | -l irun_comp.log 11 | 12 | irun -64bit \ 13 | -R \ 14 | -sv \ 15 | -sem2009 \ 16 | -access +rwc \ 17 | -input dump_irun.tcl \ 18 | +delay_mode_unit \ 19 | -timescale 1ns/1ps \ 20 | -l irun_run.log 21 | 22 | 23 | 24 | #diff goldenbrick/gb_out_mult_add_res_reuse.txt ./testbench_mult_add_res_reuse.txt | tee ./diff_functional_mult_add_res_reuse.txt #5 25 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/.history.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/.history.lock -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.nclib.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.nclib.lock -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncrun.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncrun.lock -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncv.lock: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.ncv.lock -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts: -------------------------------------------------------------------------------- 1 | 1595821449 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/dco_model_noise.v 2 | 1595785753 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/tb_pll_controller_tdc_counter.sv 3 | 1594767139 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/ssc_generator.v 4 | 1594767139 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/functions.v 5 | 1595619935 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/tdc_counter.v 6 | 1595622125 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller.sv 7 | 1595534324 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller_tdc_counter.sv 8 | 1595785160 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/analog_core.v 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/OVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/UVMHOME: -------------------------------------------------------------------------------- 1 | (null) 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/bind.lst.lnx8664: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/bind.lst.lnx8664 -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib: -------------------------------------------------------------------------------- 1 | SOFTINCLUDE /usr/caen/incisiv-15.20.084/tools/inca/files/cds.lib 2 | define worklib ../worklib 3 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/files.ts: -------------------------------------------------------------------------------- 1 | 1595785753 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/tb_pll_controller_tdc_counter.sv 2 | 1595785160 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/analog_core.v 3 | 1595534324 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller_tdc_counter.sv 4 | 1595622125 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller.sv 5 | 1595619935 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/tdc_counter.v 6 | 1595821449 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/dco_model_noise.v 7 | 1594767139 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/ssc_generator.v 8 | 1594767139 /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/functions.v 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/hdl.var: -------------------------------------------------------------------------------- 1 | define NCSIMRC ( /usr/caen/incisiv-15.20.084/tools/inca/files/ncsimrc, ~/.ncsimrc ) 2 | include ./hdlrun.var 3 | define SNAPSHOT worklib.tb_pll_controller_tdc_counter:sv 4 | DEFINE RUNMODEDEFAULT 1 5 | DEFINE LIB_MAP ( + => worklib ) 6 | define ELAB_SNAPSHOT 7 | define SNAPSHOT worklib.tb_pll_controller_tdc_counter:sv 8 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var: -------------------------------------------------------------------------------- 1 | DEFINE LANG_MAP (\ 2 | .v => verilog,\ 3 | .vp => verilog,\ 4 | .vs => verilog,\ 5 | .V => verilog,\ 6 | .VP => verilog,\ 7 | .VS => verilog,\ 8 | .v95 => verilog95,\ 9 | .v95p => verilog95,\ 10 | .V95 => verilog95,\ 11 | .V95P => verilog95,\ 12 | .vhd => vhdl,\ 13 | .vhdp => vhdl,\ 14 | .vhdl => vhdl,\ 15 | .vhdlp => vhdl,\ 16 | .VHDL => vhdl,\ 17 | .VHDLP => vhdl,\ 18 | .VHD => vhdl,\ 19 | .VHDP => vhdl,\ 20 | .e => e,\ 21 | .E => e,\ 22 | .elib => elib,\ 23 | .ELIB => elib,\ 24 | .viplib => elib,\ 25 | .VIPLIB => elib,\ 26 | .sv => systemverilog,\ 27 | .svp => systemverilog,\ 28 | .SV => systemverilog,\ 29 | .SVP => systemverilog,\ 30 | .svi => systemverilog,\ 31 | .svh => systemverilog,\ 32 | .vlib => systemverilog,\ 33 | .VLIB => systemverilog,\ 34 | .vams => verilog-ams,\ 35 | .VAMS => verilog-ams,\ 36 | .svams => sv-ams,\ 37 | .SVAMS => sv-ams,\ 38 | .svms => sv-ams,\ 39 | .SVMS => sv-ams,\ 40 | .vha => vhdl-ams,\ 41 | .VHA => vhdl-ams,\ 42 | .vhams => vhdl-ams,\ 43 | .VHAMS => vhdl-ams,\ 44 | .vhms => vhdl-ams,\ 45 | .VHMS => vhdl-ams,\ 46 | .scs => scs,\ 47 | .sp => scs,\ 48 | .s => assembly,\ 49 | .c => c,\ 50 | .o => o,\ 51 | .cpp => cpp,\ 52 | .cc => cpp,\ 53 | .a => a,\ 54 | .so => so,\ 55 | .sl => so,\ 56 | .pslvlog => psl_vlog,\ 57 | .pslvhdl => psl_vhdl,\ 58 | .pslsc => psl_sc,\ 59 | .vhcfg => vhcfg,\ 60 | .vhcfgp => vhcfg,\ 61 | .vh => systemverilog,\ 62 | DEF => unknown\ 63 | ) 64 | define VIEW_MAP ( $VIEW_MAP \ 65 | , .v => v \ 66 | , .vp => vp \ 67 | , .vs => vs \ 68 | , .V => V \ 69 | , .VP => VP \ 70 | , .VS => VS \ 71 | , .sv => sv \ 72 | , .svp => svp \ 73 | , .SV => SV \ 74 | , .SVP => SVP \ 75 | , .svi => svi \ 76 | , .svh => svh \ 77 | , .vlib => vlib \ 78 | , .VLIB => VLIB \ 79 | , .vams => vams \ 80 | , .VAMS => VAMS \ 81 | , .svams => svams \ 82 | , .SVAMS => SVAMS \ 83 | , .svms => svms \ 84 | , .SVMS => SVMS \ 85 | , .vh => vh \ 86 | ) 87 | define ELAB_SNAPSHOT 88 | define SNAPSHOT worklib.tb_pll_controller_tdc_counter:sv 89 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/irun.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -64bit 6 | -elaborate 7 | -sv 8 | -sem2009 9 | -sysv_ext 10 | +.vh 11 | -access 12 | +rwc 13 | -timescale 14 | 1ns/1ps 15 | -f 16 | ./flist.f 17 | -l 18 | irun_comp.log 19 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -SEM2009 6 | -ACCESS 7 | +rwc 8 | -timescale 9 | 1ns/1ps 10 | -MESSAGES 11 | -XLMODE 12 | ./INCA_libs/irun.lnx8664.15.20.nc 13 | -RUNMODE 14 | -CDSLIB 15 | ./INCA_libs/irun.lnx8664.15.20.nc/cds.lib 16 | -HDLVAR 17 | ./INCA_libs/irun.lnx8664.15.20.nc/hdl.var 18 | -WORK 19 | worklib 20 | -HASXLMODE 21 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: irun 4 | # Do not modify this file 5 | # 6 | #<< : <#3 irun:/afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc>#> <#3 irun:./INCA_libs/irun.lnx8664.15.20.nc>#> 7 | setenv NCRUNMODE "irun:./INCA_libs/irun.lnx8664.15.20.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncelab.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -SEM2009 6 | -ACCESS 7 | +rwc 8 | -timescale 9 | 1ns/1ps 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -MESSAGES 6 | +EMGRLOG 7 | irun_comp.log 8 | -XLSTIME 9 | 1595821465 10 | -XLKEEP 11 | -XLMODE 12 | ./INCA_libs/irun.lnx8664.15.20.nc 13 | -RUNMODE 14 | -CDSLIB 15 | ./INCA_libs/irun.lnx8664.15.20.nc/cds.lib 16 | -HDLVAR 17 | ./INCA_libs/irun.lnx8664.15.20.nc/hdl.var 18 | -XLNAME 19 | irun 20 | -XLVERSION 21 | "TOOL: irun(64) 15.20-s084" 22 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: irun 4 | # Do not modify this file 5 | # 6 | #<< : <#3 irun:./INCA_libs/irun.lnx8664.15.20.nc>#> 7 | setenv NCRUNMODE "irun:./INCA_libs/irun.lnx8664.15.20.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -MESSAGES 6 | +EMGRLOG 7 | irun_comp.log 8 | -XLSTIME 9 | 1595821465 10 | -XLKEEP 11 | -XLMODE 12 | ./INCA_libs/irun.lnx8664.15.20.nc 13 | -RUNMODE 14 | -CDSLIB 15 | ./INCA_libs/irun.lnx8664.15.20.nc/cds.lib 16 | -HDLVAR 17 | ./INCA_libs/irun.lnx8664.15.20.nc/hdl.var 18 | -XLNAME 19 | irun 20 | -XLVERSION 21 | "TOOL: irun(64) 15.20-s084" 22 | -XLNAME 23 | ./INCA_libs/irun.lnx8664.15.20.nc/grandtraverse.eecs.umich.edu_13912 24 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: irun 4 | # Do not modify this file 5 | # 6 | #<< : <#3 irun:./INCA_libs/irun.lnx8664.15.20.nc>#> 7 | setenv NCRUNMODE "irun:./INCA_libs/irun.lnx8664.15.20.nc" 8 | #<< : <#3 FALSE>#> 9 | setenv IRUNBATCH "FALSE" 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -XLMODE 6 | ./INCA_libs/irun.lnx8664.15.20.nc 7 | -RUNMODE 8 | -sv 9 | ./verilog/tb_pll_controller_tdc_counter.sv 10 | ./verilog/analog_core.v 11 | ./verilog/pll_controller_tdc_counter.sv 12 | ./verilog/pll_controller.sv 13 | ./verilog/tdc_counter.v 14 | ./verilog/dco_model_noise.v 15 | ./verilog/ssc_generator.v 16 | ./verilog/functions.v 17 | -CDSLIB 18 | ./INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib 19 | -HDLVAR 20 | ./INCA_libs/irun.lnx8664.15.20.nc/hdlrun.var 21 | -MESSAGES 22 | -UPDATE 23 | -XLLIBSTORE 24 | ./INCA_libs/irun.lnx8664.15.20.nc/xllibs 25 | -ALLOWUNBOUND 26 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.env: -------------------------------------------------------------------------------- 1 | #!/bin/csh 2 | # 3 | # File created by: irun 4 | # Do not modify this file 5 | # 6 | #<< : <#3 irun:/afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc>#> <#3 irun:./INCA_libs/irun.lnx8664.15.20.nc>#> 7 | setenv NCRUNMODE "irun:./INCA_libs/irun.lnx8664.15.20.nc" 8 | #<< : <#3 TRUE>#> 9 | setenv IRUNBATCH "TRUE" 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.files: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/tb_pll_controller_tdc_counter.sv 6 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/analog_core.v 7 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller_tdc_counter.sv 8 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_controller.sv 9 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/tdc_counter.v 10 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/dco_model_noise.v 11 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/ssc_generator.v 12 | /afs/eecs.umich.edu/wics/users/kmkwon/IDEA/fasoc/fasoc/generators/pll-gen/verilog_sim/single_ended_dco/verilog/functions.v 13 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.hrd: -------------------------------------------------------------------------------- 1 | // 2 | // File created by: irun 3 | // Do not modify this file 4 | // 5 | -sv 6 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/irun.nc: -------------------------------------------------------------------------------- 1 | irun.lnx8664.15.20.nc -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/.cdsvmod: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/.cdsvmod -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/.inca.db.150.lnx8664: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/.inca.db.150.lnx8664 -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/cdsinfo.tag: -------------------------------------------------------------------------------- 1 | CDSLIBRARY 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/inca.lnx8664.150.pak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/single_ended_dco/INCA_libs/worklib/inca.lnx8664.150.pak -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/dump_irun.tcl: -------------------------------------------------------------------------------- 1 | database -open tb_pll_controller_tdc_counter -shm -event 2 | ##probe -create tb_top -all -dynamic -memories -depth all -tasks -shm -database tb_top 3 | probe -create tb_pll_controller_tdc_counter -all -dynamic -memories -depth all -tasks -functions -shm -database tb_pll_controller_tdc_counter 4 | run 5 | #exit 6 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/flist.f: -------------------------------------------------------------------------------- 1 | ./verilog/tb_pll_controller_tdc_counter.sv 2 | ./verilog/analog_core.v 3 | ./verilog/pll_controller_tdc_counter.sv 4 | ./verilog/pll_controller.sv 5 | ./verilog/tdc_counter.v 6 | ./verilog/dco_model_noise.v 7 | ./verilog/ssc_generator.v 8 | ./verilog/functions.v 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/irun.history: -------------------------------------------------------------------------------- 1 | s1(29Apr2019:21:13:19): irun :run 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/irun.key: -------------------------------------------------------------------------------- 1 | exit 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/pll_lock_report.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/generators/pll-gen/verilog_sim/single_ended_dco/pll_lock_report.txt -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/functions.v: -------------------------------------------------------------------------------- 1 | // Functions 2 | 3 | function automatic integer func_clog2; 4 | // task automatic func_clog2; 5 | // calculate how many bits are needed to express the input value N 6 | 7 | input integer func_clog2_N; 8 | integer func_clog2_ii; 9 | 10 | // keep going until 2^ii is larger than N 11 | for (func_clog2_ii=0;2**func_clog2_ii= func_MAX_B) 24 | func_MAX = func_MAX_A; 25 | else 26 | func_MAX = func_MAX_B; 27 | 28 | endfunction 29 | 30 | 31 | function automatic integer func_MIN; 32 | // return the max of A or B 33 | 34 | input integer func_MIN_A; 35 | input integer func_MIN_B; 36 | 37 | if (func_MIN_A >= func_MIN_B) 38 | func_MIN = func_MIN_A; 39 | else 40 | func_MIN = func_MIN_B; 41 | 42 | endfunction 43 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/pll_fsm_define.sv: -------------------------------------------------------------------------------- 1 | 2 | package pll_fsm_define; 3 | 4 | typedef enum logic [3:0] {PLL_INIT, // 0 5 | PLL_FREQ_TRACK, // 1 6 | PLL_PHASE_TRACK // 2 7 | } pll_fsm; 8 | 9 | endpackage // ip740adpll_pkg 10 | 11 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/verilog/ssc_generator.v: -------------------------------------------------------------------------------- 1 | `ifndef __SSC_GENERATOR__ 2 | `define __SSC_GENERATOR__ 3 | 4 | `timescale 1ns/1ps 5 | 6 | module ssc_generator( 7 | CLKREF, 8 | RST, 9 | SSC_EN, 10 | COUNT_LIM, 11 | STEP, 12 | SHIFT, 13 | MOD_OUT 14 | ); 15 | 16 | // Functions 17 | // `include "functions.v" 18 | 19 | // Parameters 20 | parameter COUNT_WIDTH = 12; 21 | parameter ACCUM_WIDTH = 16; 22 | parameter MOD_WIDTH = 5; 23 | parameter SHIFT_WIDTH = func_clog2(ACCUM_WIDTH-1); 24 | 25 | input CLKREF, RST, SSC_EN; 26 | input [COUNT_WIDTH-1:0] COUNT_LIM; 27 | input [3:0] STEP; 28 | input [SHIFT_WIDTH-1:0] SHIFT; 29 | 30 | output [MOD_WIDTH-1:0] MOD_OUT; 31 | 32 | reg [ACCUM_WIDTH-1:0] accum; 33 | wire [ACCUM_WIDTH-1:0] accum_shift; 34 | 35 | reg [COUNT_WIDTH-1:0] count; 36 | 37 | assign accum_shift = accum >> SHIFT; 38 | assign MOD_OUT = accum_shift[MOD_WIDTH-1:0]; 39 | 40 | always @(posedge CLKREF) begin 41 | if (RST) begin 42 | accum <= 0; 43 | count <= 0; 44 | end 45 | else if (SSC_EN) begin 46 | if (count < (COUNT_LIM >> 1)) begin 47 | accum <= accum + STEP; 48 | end 49 | else begin 50 | accum <= accum - STEP; 51 | end 52 | 53 | if (count >= COUNT_LIM-1) begin 54 | count <= 0; 55 | accum <= 0; //ensure accum is reset every cycle regardless of bugs 56 | end 57 | else begin 58 | count <= count +1; 59 | end 60 | end 61 | end 62 | 63 | endmodule 64 | `endif 65 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/single_ended_dco/xrun.key: -------------------------------------------------------------------------------- 1 | exit 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/:run: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | irun -64bit \ 3 | -elaborate \ 4 | -sv \ 5 | -sem2009 \ 6 | -sysv_ext +.vh \ 7 | -access +rwc \ 8 | -timescale 1ns/1ps \ 9 | -f ./flist.f \ 10 | -l irun_comp.log 11 | 12 | irun -64bit \ 13 | -R \ 14 | -sv \ 15 | -sem2009 \ 16 | -access +rwc \ 17 | -input dump_irun.tcl \ 18 | +delay_mode_unit \ 19 | -timescale 1ns/1ps \ 20 | -l irun_run.log 21 | 22 | 23 | 24 | #diff goldenbrick/gb_out_mult_add_res_reuse.txt ./testbench_mult_add_res_reuse.txt | tee ./diff_functional_mult_add_res_reuse.txt #5 25 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/dump_irun.tcl: -------------------------------------------------------------------------------- 1 | database -open tb_tstdc_counter -shm -event 2 | ##probe -create tb_top -all -dynamic -memories -depth all -tasks -shm -database tb_top 3 | probe -create tb_tstdc_counter -all -dynamic -memories -depth all -tasks -functions -shm -database tb_tstdc_counter 4 | run 5 | #exit 6 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/flist.f: -------------------------------------------------------------------------------- 1 | ./verilog/tb_tstdc_counter.sv 2 | ./verilog/dltdc_v2.sv 3 | ./verilog/dco_CC_se.v 4 | ./verilog/dco_FC_se2.v 5 | ./verilog/DFF.v 6 | ./verilog/tstdc_counter.v 7 | ./verilog/functions.v 8 | ./verilog/analog_core.v 9 | ./verilog/dco_model_noise.v 10 | 11 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/DFF.v: -------------------------------------------------------------------------------- 1 | // DFF 2 | `timescale 1ps/1ps 3 | 4 | module DFFQ_X1N_A10P5PP84TR_C14 ( Q, D, CK); 5 | parameter su_time = 14e-12; 6 | 7 | real TIME_SCALE=1e-12; 8 | 9 | input D; 10 | input CK; 11 | output reg Q; 12 | 13 | always @(posedge CK) begin 14 | Q <= #(su_time/TIME_SCALE) D; 15 | end 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_CC_se.v: -------------------------------------------------------------------------------- 1 | // dco_CC_se model 2 | `timescale 1ps/1ps 3 | 4 | module dco_CC_se (EN, IN, OUT); 5 | 6 | input EN; 7 | input IN; 8 | output reg OUT; 9 | 10 | parameter CC_delay = 17e-12; 11 | real TIME_SCALE=1e-12; 12 | 13 | always @(posedge IN or negedge IN) begin 14 | if (EN) begin 15 | OUT = #(CC_delay/TIME_SCALE) ~IN; 16 | end 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/dco_FC_se2.v: -------------------------------------------------------------------------------- 1 | // dco_FC_se 2 | 3 | module dco_FC_se2 (EN, IN); 4 | 5 | input EN; 6 | input IN; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/functions.v: -------------------------------------------------------------------------------- 1 | // Functions 2 | 3 | function automatic integer func_clog2; 4 | // task automatic func_clog2; 5 | // calculate how many bits are needed to express the input value N 6 | 7 | input integer func_clog2_N; 8 | integer func_clog2_ii; 9 | 10 | // keep going until 2^ii is larger than N 11 | for (func_clog2_ii=0;2**func_clog2_ii= func_MAX_B) 24 | func_MAX = func_MAX_A; 25 | else 26 | func_MAX = func_MAX_B; 27 | 28 | endfunction 29 | 30 | 31 | function automatic integer func_MIN; 32 | // return the max of A or B 33 | 34 | input integer func_MIN_A; 35 | input integer func_MIN_B; 36 | 37 | if (func_MIN_A >= func_MIN_B) 38 | func_MIN = func_MIN_A; 39 | else 40 | func_MIN = func_MIN_B; 41 | 42 | endfunction 43 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/pll_fsm_define.sv: -------------------------------------------------------------------------------- 1 | 2 | package pll_fsm_define; 3 | 4 | typedef enum logic [3:0] {PLL_INIT, // 0 5 | PLL_FREQ_TRACK, // 1 6 | PLL_PHASE_TRACK // 2 7 | } pll_fsm; 8 | 9 | endpackage // ip740adpll_pkg 10 | 11 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_pre_dltdc/verilog/ssc_generator.v: -------------------------------------------------------------------------------- 1 | `ifndef __SSC_GENERATOR__ 2 | `define __SSC_GENERATOR__ 3 | 4 | `timescale 1ns/1ps 5 | 6 | module ssc_generator( 7 | CLKREF, 8 | RST, 9 | SSC_EN, 10 | COUNT_LIM, 11 | STEP, 12 | SHIFT, 13 | MOD_OUT 14 | ); 15 | 16 | // Functions 17 | // `include "functions.v" 18 | 19 | // Parameters 20 | parameter COUNT_WIDTH = 12; 21 | parameter ACCUM_WIDTH = 16; 22 | parameter MOD_WIDTH = 5; 23 | parameter SHIFT_WIDTH = func_clog2(ACCUM_WIDTH-1); 24 | 25 | input CLKREF, RST, SSC_EN; 26 | input [COUNT_WIDTH-1:0] COUNT_LIM; 27 | input [3:0] STEP; 28 | input [SHIFT_WIDTH-1:0] SHIFT; 29 | 30 | output [MOD_WIDTH-1:0] MOD_OUT; 31 | 32 | reg [ACCUM_WIDTH-1:0] accum; 33 | wire [ACCUM_WIDTH-1:0] accum_shift; 34 | 35 | reg [COUNT_WIDTH-1:0] count; 36 | 37 | assign accum_shift = accum >> SHIFT; 38 | assign MOD_OUT = accum_shift[MOD_WIDTH-1:0]; 39 | 40 | always @(posedge CLKREF) begin 41 | if (RST) begin 42 | accum <= 0; 43 | count <= 0; 44 | end 45 | else if (SSC_EN) begin 46 | if (count < (COUNT_LIM >> 1)) begin 47 | accum <= accum + STEP; 48 | end 49 | else begin 50 | accum <= accum - STEP; 51 | end 52 | 53 | if (count >= COUNT_LIM-1) begin 54 | count <= 0; 55 | accum <= 0; //ensure accum is reset every cycle regardless of bugs 56 | end 57 | else begin 58 | count <= count +1; 59 | end 60 | end 61 | end 62 | 63 | endmodule 64 | `endif 65 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/:run: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | irun -64bit \ 3 | -elaborate \ 4 | -sv \ 5 | -sem2009 \ 6 | -sysv_ext +.vh \ 7 | -access +rwc \ 8 | -timescale 1ns/1ps \ 9 | -f ./flist.f \ 10 | -l irun_comp.log 11 | 12 | irun -64bit \ 13 | -R \ 14 | -sv \ 15 | -sem2009 \ 16 | -access +rwc \ 17 | -input dump_irun.tcl \ 18 | +delay_mode_unit \ 19 | -timescale 1ns/1ps \ 20 | -l irun_run.log 21 | 22 | 23 | 24 | #diff goldenbrick/gb_out_mult_add_res_reuse.txt ./testbench_mult_add_res_reuse.txt | tee ./diff_functional_mult_add_res_reuse.txt #5 25 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/dltdc_dump_irun.tcl: -------------------------------------------------------------------------------- 1 | database -open tb_dltdc_model -shm -event 2 | ##probe -create tb_top -all -dynamic -memories -depth all -tasks -shm -database tb_top 3 | probe -create tb_dltdc_model -all -dynamic -memories -depth all -tasks -functions -shm -database tb_dltdc_model 4 | run 5 | #exit 6 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/dltdc_flist.f: -------------------------------------------------------------------------------- 1 | ./verilog/tb_dltdc_model.sv 2 | ./verilog/dltdc_model.sv 3 | ./verilog/functions.v 4 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/dump_irun.tcl: -------------------------------------------------------------------------------- 1 | database -open tb_tstdc_counter -shm -event 2 | ##probe -create tb_top -all -dynamic -memories -depth all -tasks -shm -database tb_top 3 | probe -create tb_tstdc_counter -all -dynamic -memories -depth all -tasks -functions -shm -database tb_tstdc_counter 4 | run 5 | #exit 6 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/flist.f: -------------------------------------------------------------------------------- 1 | ./verilog/tb_tstdc_counter.sv 2 | ./verilog/dltdc_model.sv 3 | ./verilog/pre_dltdc.sv 4 | ./verilog/tstdc_counter.v 5 | ./verilog/functions.v 6 | ./verilog/analog_core.v 7 | ./verilog/dco_model_noise.v 8 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/irun.key: -------------------------------------------------------------------------------- 1 | exit 2 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/functions.v: -------------------------------------------------------------------------------- 1 | // Functions 2 | 3 | function automatic integer func_clog2; 4 | // task automatic func_clog2; 5 | // calculate how many bits are needed to express the input value N 6 | 7 | input integer func_clog2_N; 8 | integer func_clog2_ii; 9 | 10 | // keep going until 2^ii is larger than N 11 | for (func_clog2_ii=0;2**func_clog2_ii= func_MAX_B) 24 | func_MAX = func_MAX_A; 25 | else 26 | func_MAX = func_MAX_B; 27 | 28 | endfunction 29 | 30 | 31 | function automatic integer func_MIN; 32 | // return the max of A or B 33 | 34 | input integer func_MIN_A; 35 | input integer func_MIN_B; 36 | 37 | if (func_MIN_A >= func_MIN_B) 38 | func_MIN = func_MIN_A; 39 | else 40 | func_MIN = func_MIN_B; 41 | 42 | endfunction 43 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/pll_fsm_define.sv: -------------------------------------------------------------------------------- 1 | 2 | package pll_fsm_define; 3 | 4 | typedef enum logic [3:0] {PLL_INIT, // 0 5 | PLL_FREQ_TRACK, // 1 6 | PLL_PHASE_TRACK // 2 7 | } pll_fsm; 8 | 9 | endpackage // ip740adpll_pkg 10 | 11 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/two_step_tdc/tstdc_top/verilog/ssc_generator.v: -------------------------------------------------------------------------------- 1 | `ifndef __SSC_GENERATOR__ 2 | `define __SSC_GENERATOR__ 3 | 4 | `timescale 1ns/1ps 5 | 6 | module ssc_generator( 7 | CLKREF, 8 | RST, 9 | SSC_EN, 10 | COUNT_LIM, 11 | STEP, 12 | SHIFT, 13 | MOD_OUT 14 | ); 15 | 16 | // Functions 17 | // `include "functions.v" 18 | 19 | // Parameters 20 | parameter COUNT_WIDTH = 12; 21 | parameter ACCUM_WIDTH = 16; 22 | parameter MOD_WIDTH = 5; 23 | parameter SHIFT_WIDTH = func_clog2(ACCUM_WIDTH-1); 24 | 25 | input CLKREF, RST, SSC_EN; 26 | input [COUNT_WIDTH-1:0] COUNT_LIM; 27 | input [3:0] STEP; 28 | input [SHIFT_WIDTH-1:0] SHIFT; 29 | 30 | output [MOD_WIDTH-1:0] MOD_OUT; 31 | 32 | reg [ACCUM_WIDTH-1:0] accum; 33 | wire [ACCUM_WIDTH-1:0] accum_shift; 34 | 35 | reg [COUNT_WIDTH-1:0] count; 36 | 37 | assign accum_shift = accum >> SHIFT; 38 | assign MOD_OUT = accum_shift[MOD_WIDTH-1:0]; 39 | 40 | always @(posedge CLKREF) begin 41 | if (RST) begin 42 | accum <= 0; 43 | count <= 0; 44 | end 45 | else if (SSC_EN) begin 46 | if (count < (COUNT_LIM >> 1)) begin 47 | accum <= accum + STEP; 48 | end 49 | else begin 50 | accum <= accum - STEP; 51 | end 52 | 53 | if (count >= COUNT_LIM-1) begin 54 | count <= 0; 55 | accum <= 0; //ensure accum is reset every cycle regardless of bugs 56 | end 57 | else begin 58 | count <= count +1; 59 | end 60 | end 61 | end 62 | 63 | endmodule 64 | `endif 65 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/functions.v: -------------------------------------------------------------------------------- 1 | // Functions 2 | 3 | function automatic integer func_clog2; 4 | // task automatic func_clog2; 5 | // calculate how many bits are needed to express the input value N 6 | 7 | input integer func_clog2_N; 8 | integer func_clog2_ii; 9 | 10 | // keep going until 2^ii is larger than N 11 | //for (func_clog2_ii=0;2**func_clog2_ii= func_MAX_B) 25 | func_MAX = func_MAX_A; 26 | else 27 | func_MAX = func_MAX_B; 28 | 29 | endfunction 30 | 31 | 32 | function automatic integer func_MIN; 33 | // return the max of A or B 34 | 35 | input integer func_MIN_A; 36 | input integer func_MIN_B; 37 | 38 | if (func_MIN_A >= func_MIN_B) 39 | func_MIN = func_MIN_A; 40 | else 41 | func_MIN = func_MIN_B; 42 | 43 | endfunction 44 | 45 | -------------------------------------------------------------------------------- /generators/pll-gen/verilog_sim/verilog/ssc_generator.v: -------------------------------------------------------------------------------- 1 | `ifndef __SSC_GENERATOR__ 2 | `define __SSC_GENERATOR__ 3 | 4 | //`timescale 1ps/1fs 5 | 6 | module ssc_generator( 7 | CLKREF, 8 | RST, 9 | SSC_EN, 10 | COUNT_LIM, 11 | STEP, 12 | SHIFT, 13 | MOD_OUT 14 | ); 15 | 16 | // Functions 17 | // `include "functions.v" 18 | 19 | // Parameters 20 | parameter COUNT_WIDTH = 12; 21 | parameter ACCUM_WIDTH = 16; 22 | parameter MOD_WIDTH = 5; 23 | parameter SHIFT_WIDTH = func_clog2(ACCUM_WIDTH-1); 24 | 25 | input CLKREF, RST, SSC_EN; 26 | input [COUNT_WIDTH-1:0] COUNT_LIM; 27 | input [3:0] STEP; 28 | input [SHIFT_WIDTH-1:0] SHIFT; 29 | 30 | output [MOD_WIDTH-1:0] MOD_OUT; 31 | 32 | reg [ACCUM_WIDTH-1:0] accum; 33 | wire [ACCUM_WIDTH-1:0] accum_shift; 34 | 35 | reg [COUNT_WIDTH-1:0] count; 36 | 37 | assign accum_shift = accum >> SHIFT; 38 | assign MOD_OUT = accum_shift[MOD_WIDTH-1:0]; 39 | 40 | always @(posedge CLKREF) begin 41 | if (RST) begin 42 | accum <= 0; 43 | count <= 0; 44 | end 45 | else if (SSC_EN) begin 46 | if (count < (COUNT_LIM >> 1)) begin 47 | accum <= accum + STEP; 48 | end 49 | else begin 50 | accum <= accum - STEP; 51 | end 52 | 53 | if (count >= COUNT_LIM-1) begin 54 | count <= 0; 55 | accum <= 0; //ensure accum is reset every cycle regardless of bugs 56 | end 57 | else begin 58 | count <= count +1; 59 | end 60 | end 61 | end 62 | 63 | endmodule 64 | `endif 65 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/FUNCTIONS.v: -------------------------------------------------------------------------------- 1 | // Functions 2 | 3 | function automatic integer func_clog2; 4 | // task automatic func_clog2; 5 | // calculate how many bits are needed to express the input value N 6 | 7 | input integer func_clog2_N; 8 | integer func_clog2_ii; 9 | 10 | // keep going until 2^ii is larger than N 11 | //for (func_clog2_ii=0;2**func_clog2_ii= func_MAX_B) 25 | func_MAX = func_MAX_A; 26 | else 27 | func_MAX = func_MAX_B; 28 | 29 | endfunction 30 | 31 | 32 | function automatic integer func_MIN; 33 | // return the max of A or B 34 | 35 | input integer func_MIN_A; 36 | input integer func_MIN_B; 37 | 38 | if (func_MIN_A >= func_MIN_B) 39 | func_MIN = func_MIN_A; 40 | else 41 | func_MIN = func_MIN_B; 42 | 43 | endfunction 44 | 45 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/SSC_GENERATOR.v: -------------------------------------------------------------------------------- 1 | `ifndef __SSC_GENERATOR__ 2 | `define __SSC_GENERATOR__ 3 | 4 | `timescale 1ns/1ps 5 | 6 | module SSC_GENERATOR( 7 | CLKREF, 8 | RST, 9 | SSC_EN, 10 | COUNT_LIM, 11 | STEP, 12 | SHIFT, 13 | MOD_OUT 14 | ); 15 | 16 | // Functions 17 | `include "FUNCTIONS.v" 18 | 19 | // Parameters 20 | parameter COUNT_WIDTH = 12; 21 | parameter ACCUM_WIDTH = 16; 22 | parameter MOD_WIDTH = 5; 23 | parameter SHIFT_WIDTH = func_clog2(ACCUM_WIDTH-1); 24 | 25 | input CLKREF, RST, SSC_EN; 26 | input [COUNT_WIDTH-1:0] COUNT_LIM; 27 | input [3:0] STEP; 28 | input [SHIFT_WIDTH-1:0] SHIFT; 29 | 30 | output [MOD_WIDTH-1:0] MOD_OUT; 31 | 32 | reg [ACCUM_WIDTH-1:0] accum; 33 | wire [ACCUM_WIDTH-1:0] accum_shift; 34 | 35 | reg [COUNT_WIDTH-1:0] count; 36 | 37 | assign accum_shift = accum >> SHIFT; 38 | assign MOD_OUT = accum_shift[MOD_WIDTH-1:0]; 39 | 40 | always @(posedge CLKREF) begin 41 | if (RST) begin 42 | accum <= 0; 43 | count <= 0; 44 | end 45 | else if (SSC_EN) begin 46 | if (count < (COUNT_LIM >> 1)) begin 47 | accum <= accum + STEP; 48 | end 49 | else begin 50 | accum <= accum - STEP; 51 | end 52 | 53 | if (count >= COUNT_LIM-1) begin 54 | count <= 0; 55 | accum <= 0; //ensure accum is reset every cycle regardless of bugs 56 | end 57 | else begin 58 | count <= count +1; 59 | end 60 | end 61 | end 62 | 63 | endmodule 64 | `endif 65 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_CC.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | 3 | module dco_CC (IN, IP, ON, OP, EN); 4 | input IN; 5 | input IP; 6 | output ON; 7 | output OP; 8 | input EN; 9 | endmodule 10 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_CC_se.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | 3 | module dco_CC_se (IN, OUT, EN); 4 | input IN; 5 | output OUT; 6 | input EN; 7 | endmodule 8 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_CC_se_3st.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | 3 | module dco_CC_se_3st (IN, OUT, EN); 4 | input IN; 5 | output OUT; 6 | input EN; 7 | endmodule 8 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | // 3 | 4 | module dco_FC (IN, IP,EN); 5 | input IN; 6 | input IP; 7 | input EN; 8 | endmodule 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC_se.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | // 3 | 4 | module dco_FC_se (IN, EN); 5 | input IN; 6 | input EN; 7 | endmodule 8 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC_se2.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | // 3 | 4 | module dco_FC_se2 (IN, EN); 5 | input IN; 6 | input EN; 7 | endmodule 8 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC_se2_half.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | // 3 | 4 | module dco_FC_se2_half (IN, EN, ENB); 5 | input IN; 6 | input EN; 7 | input ENB; 8 | endmodule 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/dco_FC_se_half.v: -------------------------------------------------------------------------------- 1 | //DCO coarse cell verilog format 2 | // 3 | 4 | module dco_FC_se_half (IN, EN, ENB); 5 | input IN; 6 | input EN; 7 | input ENB; 8 | endmodule 9 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/ssc_generator.v: -------------------------------------------------------------------------------- 1 | `ifndef __SSC_GENERATOR__ 2 | `define __SSC_GENERATOR__ 3 | 4 | //`timescale 1ps/1fs 5 | 6 | module ssc_generator( 7 | CLKREF, 8 | RST, 9 | SSC_EN, 10 | COUNT_LIM, 11 | STEP, 12 | SHIFT, 13 | MOD_OUT 14 | ); 15 | 16 | // Functions 17 | // `include "functions.v" 18 | 19 | // Parameters 20 | parameter COUNT_WIDTH = 12; 21 | parameter ACCUM_WIDTH = 16; 22 | parameter MOD_WIDTH = 5; 23 | parameter SHIFT_WIDTH = func_clog2(ACCUM_WIDTH-1); 24 | 25 | input CLKREF, RST, SSC_EN; 26 | input [COUNT_WIDTH-1:0] COUNT_LIM; 27 | input [3:0] STEP; 28 | input [SHIFT_WIDTH-1:0] SHIFT; 29 | 30 | output [MOD_WIDTH-1:0] MOD_OUT; 31 | 32 | reg [ACCUM_WIDTH-1:0] accum; 33 | wire [ACCUM_WIDTH-1:0] accum_shift; 34 | 35 | reg [COUNT_WIDTH-1:0] count; 36 | 37 | assign accum_shift = accum >> SHIFT; 38 | assign MOD_OUT = accum_shift[MOD_WIDTH-1:0]; 39 | 40 | always @(posedge CLKREF) begin 41 | if (RST) begin 42 | accum <= 0; 43 | count <= 0; 44 | end 45 | else if (SSC_EN) begin 46 | if (count < (COUNT_LIM >> 1)) begin 47 | accum <= accum + STEP; 48 | end 49 | else begin 50 | accum <= accum - STEP; 51 | end 52 | 53 | if (count >= COUNT_LIM-1) begin 54 | count <= 0; 55 | accum <= 0; //ensure accum is reset every cycle regardless of bugs 56 | end 57 | else begin 58 | count <= count +1; 59 | end 60 | end 61 | end 62 | 63 | endmodule 64 | `endif 65 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/synth_pll_dco_interp_gf12lp.v: -------------------------------------------------------------------------------- 1 | module synth_pll_dco_interp ( INA, INB, IPA, IPB, ON, OP); 2 | input INA, INB, IPA, IPB; 3 | output ON, OP; 4 | wire int1, int2; 5 | 6 | INV_X2N_A10P5PP84TR_C14 inva1 (.A(INA), .Y(int1) ); 7 | INV_X2N_A10P5PP84TR_C14 inva2 (.A(INB), .Y(int1) ); 8 | INV_X2N_A10P5PP84TR_C14 inva3 (.A(int1), .Y(ON) ); 9 | 10 | INV_X2N_A10P5PP84TR_C14 invb1 (.A(IPA), .Y(int2) ); 11 | INV_X2N_A10P5PP84TR_C14 invb2 (.A(IPB), .Y(int2) ); 12 | INV_X2N_A10P5PP84TR_C14 invb3 (.A(int2), .Y(OP) ); 13 | endmodule 14 | 15 | module synth_pll_dco_interp_40 ( INA, INB, IPA, IPB, ON, OP); 16 | input INA, INB, IPA, IPB; 17 | output ON, OP; 18 | wire int1, int2; 19 | 20 | INVD2BWP12T inva1 (.I(INA), .ZN(int1) ); 21 | INVD2BWP12T inva2 (.I(INB), .ZN(int1) ); 22 | INVD2BWP12T inva3 (.I(int1), .ZN(ON) ); 23 | 24 | INVD2BWP12T invb1 (.I(IPA), .ZN(int2) ); 25 | INVD2BWP12T invb2 (.I(IPB), .ZN(int2) ); 26 | INVD2BWP12T invb3 (.I(int2), .ZN(OP) ); 27 | endmodule 28 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/synth_pll_dco_interp_tsmc65lp.v: -------------------------------------------------------------------------------- 1 | module synth_pll_dco_interp ( INA, INB, IPA, IPB, ON, OP); 2 | input INA, INB, IPA, IPB; 3 | output ON, OP; 4 | wire int1, int2; 5 | 6 | INV_X2M_A9TR inva1 (.A(INA), .Y(int1) ); 7 | INV_X2M_A9TR inva2 (.A(INB), .Y(int1) ); 8 | INV_X2M_A9TR inva3 (.A(int1), .Y(ON) ); 9 | 10 | INV_X2M_A9TR invb1 (.A(IPA), .Y(int2) ); 11 | INV_X2M_A9TR invb2 (.A(IPB), .Y(int2) ); 12 | INV_X2M_A9TR invb3 (.A(int2), .Y(OP) ); 13 | endmodule 14 | 15 | module synth_pll_dco_interp_40 ( INA, INB, IPA, IPB, ON, OP); 16 | input INA, INB, IPA, IPB; 17 | output ON, OP; 18 | wire int1, int2; 19 | 20 | INVD2BWP12T inva1 (.I(INA), .ZN(int1) ); 21 | INVD2BWP12T inva2 (.I(INB), .ZN(int1) ); 22 | INVD2BWP12T inva3 (.I(int1), .ZN(ON) ); 23 | 24 | INVD2BWP12T invb1 (.I(IPA), .ZN(int2) ); 25 | INVD2BWP12T invb2 (.I(IPB), .ZN(int2) ); 26 | INVD2BWP12T invb3 (.I(int2), .ZN(OP) ); 27 | endmodule 28 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/synth_pll_dco_outbuff_gf12lp.v: -------------------------------------------------------------------------------- 1 | module synth_pll_dco_outbuff ( IN, IP, ON, OP); 2 | input IN, IP; 3 | output ON, OP; 4 | wire int1, int2; 5 | 6 | INV_X2N_A10P5PP84TR_C14 inva1 (.A(IN), .Y(int1) ); 7 | INV_X2N_A10P5PP84TR_C14 inva2 (.A(IN), .Y(int1) ); 8 | INV_X2N_A10P5PP84TR_C14 inva3 (.A(int1), .Y(ON) ); 9 | 10 | INV_X2N_A10P5PP84TR_C14 invb1 (.A(IP), .Y(int2) ); 11 | INV_X2N_A10P5PP84TR_C14 invb2 (.A(IP), .Y(int2) ); 12 | INV_X2N_A10P5PP84TR_C14 invb3 (.A(int2), .Y(OP) ); 13 | endmodule 14 | 15 | module synth_pll_dco_outbuff_40 ( in, ip, on, op); 16 | input in, ip; 17 | output on, op; 18 | wire int1, int2; 19 | 20 | INVD2BWP12T inva1 (.I(in), .ZN(int1) ); 21 | INVD2BWP12T inva2 (.I(in), .ZN(int1) ); 22 | INVD2BWP12T inva3 (.I(int1), .ZN(on) ); 23 | 24 | INVD2BWP12T invb1 (.I(ip), .ZN(int2) ); 25 | INVD2BWP12T invb2 (.I(ip), .ZN(int2) ); 26 | INVD2BWP12T invb3 (.I(int2), .ZN(op) ); 27 | endmodule 28 | -------------------------------------------------------------------------------- /generators/pll-gen/verilogs/synth_pll_dco_outbuff_tsmc65lp.v: -------------------------------------------------------------------------------- 1 | module synth_pll_dco_outbuff ( IN, IP, ON, OP); 2 | input IN, IP; 3 | output ON, OP; 4 | wire int1, int2; 5 | 6 | INV_X2M_A9TR inva1 (.A(IN), .Y(int1) ); 7 | INV_X2M_A9TR inva2 (.A(IN), .Y(int1) ); 8 | INV_X2M_A9TR inva3 (.A(int1), .Y(ON) ); 9 | 10 | INV_X2M_A9TR invb1 (.A(IP), .Y(int2) ); 11 | INV_X2M_A9TR invb2 (.A(IP), .Y(int2) ); 12 | INV_X2M_A9TR invb3 (.A(int2), .Y(OP) ); 13 | endmodule 14 | 15 | module synth_pll_dco_outbuff_40 ( in, ip, on, op); 16 | input in, ip; 17 | output on, op; 18 | wire int1, int2; 19 | 20 | INVD2BWP12T inva1 (.I(in), .ZN(int1) ); 21 | INVD2BWP12T inva2 (.I(in), .ZN(int1) ); 22 | INVD2BWP12T inva3 (.I(int1), .ZN(on) ); 23 | 24 | INVD2BWP12T invb1 (.I(ip), .ZN(int2) ); 25 | INVD2BWP12T invb2 (.I(ip), .ZN(int2) ); 26 | INVD2BWP12T invb3 (.I(int2), .ZN(op) ); 27 | endmodule 28 | -------------------------------------------------------------------------------- /generators/scpa-gen/.gitignore: -------------------------------------------------------------------------------- 1 | IBM_CMOS8HP_SC.cdl 2 | PT_UNIT_CELL.cdl 3 | .cshrc_8hp 4 | work 5 | -------------------------------------------------------------------------------- /generators/scpa-gen/Makefile: -------------------------------------------------------------------------------- 1 | gen_12lp: 2 | ./tools/scpa_gen.py --specfile test.json --output ./work --platform gf12lp 3 | 4 | gen_12lp_macro: 5 | ./tools/scpa_gen.py --specfile test.json --output ./work --platform gf12lp --mode macro 6 | 7 | gen_12lp_full: 8 | ./tools/scpa_gen.py --specfile test.json --output ./work --platform gf12lp --mode full 9 | 10 | gen_12lp_pex: 11 | ./tools/scpa_gen_pex.py --specfile test.json --output ./work --platform gf12lp --mode pex 12 | 13 | model_12lp: 14 | ./tools/scpa_model.py --platform gf12lp 15 | 16 | clean_12lp_full: 17 | ./tools/scpa_gen.py --specfile test.json --output ./work --platform gf12lp --clean --mode full 18 | ./tools/scpa_model.py --platform gf12lp --clean 19 | 20 | code_reset: 21 | git checkout ./flow 22 | git clean -f -d ./flow 23 | -------------------------------------------------------------------------------- /generators/scpa-gen/bu_test.json: -------------------------------------------------------------------------------- 1 | 2 | { 3 | "module_name": "ldo", 4 | "generator": "ldo-gen", 5 | "specifications": { 6 | "vin": 0.8, 7 | "imax": "1e-03" 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /generators/scpa-gen/test.json: -------------------------------------------------------------------------------- 1 | 2 | { 3 | "module_name": "SCPA", 4 | "generator": "scpa-gen", 5 | "specifications": { 6 | } 7 | } 8 | -------------------------------------------------------------------------------- /generators/scpa-gen/tools/supported_inputs.json: -------------------------------------------------------------------------------- 1 | 2 | { 3 | "platforms": { 4 | "tsmc65lp": { 5 | "vin": { 6 | "max": 1.3, 7 | "min": 0.6 8 | }, 9 | "maxLoad": { 10 | "max": "25e-03", 11 | "min": "0.5e-03" 12 | } 13 | }, 14 | "gfbicmos8hp": { 15 | "vin": { 16 | "max": 1.3, 17 | "min": 0.6 18 | }, 19 | "maxLoad": { 20 | "max": "25e-03", 21 | "min": "0.5e-03" 22 | } 23 | }, 24 | "gf12lp": { 25 | "vin": { 26 | "max": 0.9, 27 | "min": 0.6 28 | }, 29 | "maxLoad": { 30 | "max": "16e-03", 31 | "min": "0.5e-03" 32 | } 33 | } 34 | } 35 | } 36 | -------------------------------------------------------------------------------- /generators/scpa-gen/verilog/CLK_DRIVER.v: -------------------------------------------------------------------------------- 1 | module CLK_DRIVER( 2 | input rf, 3 | input sel, 4 | output vout 5 | ); 6 | logic w0, w1, w2, w3; 7 | NAND2_X1N_A10P5PP84TR_C14 nand1 (.A(sel), .B(rf), .Y(w0)); 8 | INV_X2N_A10P5PP84TR_C14 inv1 (.A(w0), .Y(w1)); 9 | INV_X4N_A10P5PP84TR_C14 inv2 (.A(w1), .Y(w2)); 10 | INV_X8N_A10P5PP84TR_C14 inv3 (.A(w2), .Y(w3)); 11 | INV_X16N_A10P5PP84TR_C14 inv4 (.A(w3), .Y(vout)); 12 | 13 | endmodule 14 | 15 | 16 | -------------------------------------------------------------------------------- /generators/scpa-gen/verilog/SCPA.v: -------------------------------------------------------------------------------- 1 | module SCPA( 2 | input dum_clk, 3 | input dum_in, 4 | output logic dum_out, 5 | input clk, 6 | input [31:0] cap_sel, 7 | output cap_out 8 | ); 9 | 10 | parameter integer ARRSZ = 32; 11 | logic [ARRSZ-1:0] cap_bot_in; 12 | 13 | logic dum_inter; 14 | 15 | always_ff @ (posedge dum_clk) begin 16 | dum_inter <= ~dum_in; 17 | dum_out <= dum_inter + dum_in; 18 | end 19 | 20 | genvar i; 21 | generate 22 | for (i = 0; i < ARRSZ; i = i + 1) begin 23 | CLK_DRIVER clk_drv (.rf(clk), .sel(cap_sel[i]), .vout(cap_bot_in[i])); 24 | SCPA_MIMCAP_new cap_array (.TOP(cap_out), .BOT(cap_bot_in[i])); 25 | 26 | end 27 | endgenerate 28 | 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /generators/scpa-gen/verilog/SCPA_MIMCAP_new.v: -------------------------------------------------------------------------------- 1 | //SCPA_MIMCAP_new verilog format 2 | 3 | module SCPA_MIMCAP_new (TOP, BOT); 4 | inout TOP; 5 | inout BOT; 6 | endmodule 7 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/.gitignore: -------------------------------------------------------------------------------- 1 | golden_* 2 | power_within_x.csv 3 | error_within_x.csv 4 | 5 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/golden_error_opt.csv: -------------------------------------------------------------------------------- 1 | Temp,Frequency,Power,Error,inv,header 2 | 20.0,296000.0,1.8600000000000002e-09,-0.029785664,6.0,9.0 3 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/makefile: -------------------------------------------------------------------------------- 1 | gen_65lp: 2 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform tsmc65lp --mode verilog 3 | 4 | gen_65lp_macro: 5 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform tsmc65lp --mode macro 6 | 7 | gen_65lp_full: 8 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform tsmc65lp --mode full 9 | 10 | 65lp_clean: 11 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform tsmc65lp --mode macro --clean 12 | 13 | gen_12lp: 14 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform gf12lp --mode macro 15 | 16 | gen_12lp_verilog: 17 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform gf12lp --mode verilog 18 | 19 | gen_12lp_macro: 20 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform gf12lp --mode macro 21 | 22 | gen_12lp_full: 23 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform gf12lp --mode full 24 | 25 | 12lp_clean: 26 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform gf12lp --mode macro --clean 27 | 28 | gen_sky130: 29 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform sky130 --mode macro 30 | 31 | gen_sky130_verilog: 32 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform sky130 --mode verilog 33 | 34 | gen_sky130_macro: 35 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform sky130 --mode macro 36 | 37 | gen_sky130_full: 38 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform sky130 --mode full 39 | 40 | sky130_clean: 41 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform sky130 --mode macro --clean 42 | # model: 43 | # python tools/temp-sense-gen-model.py --platform tsmc65lp 44 | 45 | 46 | clean: 47 | python tools/temp-sense-gen.py --specfile test.json --output ./work --platform sky130 --mode verilog --clean 48 | #python tools/temp-sense-gen-model.py --platform tsmc65lp --clean 49 | 50 | 51 | code_reset: 52 | git checkout ./flow 53 | git clean -f -d ./flow 54 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/search_result.csv: -------------------------------------------------------------------------------- 1 | Temp,Power,Error,Inv,Header,search_param 2 | 20.0,1.65e-09,-0.031256129,6.0,7.0,"Tempmin:-20,Tempmax:100,Optimization:error,Model:/afs/eecs.umich.edu/cadre/projects/fasoc/share/model_12lp/modelfile.csv,Delta_1st_pass:10" 3 | 20.0,1.65e-09,-0.031256129,6.0,7.0,"Tempmin:-20,Tempmax:100,Optimization:error,Model:/afs/eecs.umich.edu/cadre/projects/fasoc/share/model_tsmc65/modelfile.csv,Delta_1st_pass:10" 4 | 20.0,1.65e-09,-0.031256129,6.0,7.0,"Tempmin:-20,Tempmax:100,Optimization:error,Model:/afs/eecs.umich.edu/cadre/projects/fasoc/share/model_sky130/modelfile.csv,Delta_1st_pass:10" 5 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_ANALOG_hv.nl.v: -------------------------------------------------------------------------------- 1 | module TEMP_ANALOG_hv 2 | ( 3 | input CLK_REF, 4 | input RESET_COUNTERn, 5 | input [3:0] SEL_CONV_TIME, 6 | input en, 7 | input out, outb, 8 | 9 | output [23:0] DOUT, 10 | output DONE, 11 | output lc_out, 12 | inout VIN 13 | ); 14 | 15 | wire lc_0; 16 | // reg iso; 17 | // assign iso = 0 ; 18 | counter async_counter_0( 19 | // Input 20 | .CLK_SENS (lc_out), 21 | .CLK_REF (CLK_REF), 22 | .RESET_COUNTERn (RESET_COUNTERn), 23 | .SEL_CONV_TIME (SEL_CONV_TIME), 24 | // Output 25 | .DOUT (DOUT), 26 | .DONE (DONE) 27 | ); 28 | 29 | 30 | HEADERX1RVT a_header_0(.VIN(VIN)); 31 | HEADERX1RVT a_header_1(.VIN(VIN)); 32 | HEADERX1RVT a_header_2(.VIN(VIN)); 33 | HEADERX1RVT a_header_3(.VIN(VIN)); 34 | HEADERX1RVT a_header_4(.VIN(VIN)); 35 | HEADERX1RVT a_header_5(.VIN(VIN)); 36 | HEADERX1RVT a_header_6(.VIN(VIN)); 37 | LC1P2TO3P6X1RVT_VDDX4 a_lc_0(.A(out), .AB(outb), .Y(lc_0)); 38 | BUFX4RVT_ISOVDD a_buffer_0 (.A(lc_0), .Y(lc_out)); 39 | 40 | endmodule 41 | 42 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_ANALOG_hv.v: -------------------------------------------------------------------------------- 1 | module TEMP_ANALOG_hv 2 | ( 3 | input CLK_REF, 4 | input RESET_COUNTERn, 5 | input [3:0] SEL_CONV_TIME, 6 | input en, 7 | input out, outb, 8 | 9 | output [23:0] DOUT, 10 | output DONE, 11 | output lc_out, 12 | inout VIN 13 | ); 14 | 15 | wire lc_0; 16 | // reg iso; 17 | // assign iso = 0 ; 18 | counter async_counter_0( 19 | // Input 20 | .CLK_SENS (lc_out), 21 | .CLK_REF (CLK_REF), 22 | .RESET_COUNTERn (RESET_COUNTERn), 23 | .SEL_CONV_TIME (SEL_CONV_TIME), 24 | // Output 25 | .DOUT (DOUT), 26 | .DONE (DONE) 27 | ); 28 | 29 | 30 | @@ @nf a_header_@nh(.VIN(VIN)); 31 | SLC 32 | @@ @no a_buffer_0 (.A(lc_0), .nbout(lc_out)); 33 | 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_ANALOG_lv.nl.v: -------------------------------------------------------------------------------- 1 | module TEMP_ANALOG_lv (EN, OUT, OUTB); 2 | input EN; 3 | // inout in_vin; 4 | output OUT, OUTB; 5 | wire n; 6 | wire n1; 7 | wire n2; 8 | wire n3; 9 | wire n4; 10 | wire n5; 11 | wire n6; 12 | wire n7; 13 | wire nx1, nx2, nx3, nb1, nb2; 14 | NAND2X1RVT_ISOVDD a_nand_0 ( .A(EN), .B(n7), .Y(n1), .VIN(1'b1)); 15 | INVXRVT_ISOVDD a_inv_0 ( .A(n1), .Y(n2), .VIN(1'b1)); 16 | INVXRVT_ISOVDD a_inv_1 ( .A(n2), .Y(n3), .VIN(1'b1)); 17 | INVXRVT_ISOVDD a_inv_2 ( .A(n3), .Y(n4), .VIN(1'b1)); 18 | INVXRVT_ISOVDD a_inv_3 ( .A(n4), .Y(n5), .VIN(1'b1)); 19 | INVXRVT_ISOVDD a_inv_4 ( .A(n5), .Y(n6), .VIN(1'b1)); 20 | INVXRVT_ISOVDD a_inv_5 ( .A(n6), .Y(n7), .VIN(1'b1)); 21 | INVXRVT_ISOVDD a_inv_m1 ( .A(n7), .Y(nx1), .VIN(1'b1)); 22 | INVXRVT_ISOVDD a_inv_m2 ( .A(n7), .Y(nx2), .VIN(1'b1)); 23 | INVXRVT_ISOVDD a_inv_m3 ( .A(nx2), .Y(nx3), .VIN(1'b1)); 24 | BUFX4RVT_ISOVDD a_buf_3 ( .A(nx3), .Y(nb2), .VIN(1'b1)); 25 | BUFX4RVT_ISOVDD a_buf_0 ( .A(nx1), .Y(nb1), .VIN(1'b1)); 26 | BUFX4RVT_ISOVDD a_buf_1 ( .A(nb1), .Y(OUT), .VIN(1'b1)); 27 | BUFX4RVT_ISOVDD a_buf_2 ( .A(nb2), .Y(OUTB), .VIN(1'b1)); 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_ANALOG_lv.v: -------------------------------------------------------------------------------- 1 | module TEMP_ANALOG_lv (EN, OUT, OUTB); 2 | input EN; 3 | // inout in_vin; 4 | output OUT, OUTB; 5 | wire n; 6 | @@ wire n@nn; 7 | wire nx1, nx2, nx3, nb1, nb2; 8 | @@ @na a_nand_0 ( .A(EN), .B(n@n0), .Y(n1)); 9 | @@ @nb a_inv_@ni ( .A(n@n1), .Y(n@n2)); 10 | @@ @ng a_inv_m1 ( .A(n@n3), .Y(nx1)); 11 | @@ @nk a_inv_m2 ( .A(n@n4), .Y(nx2)); 12 | @@ @nm a_inv_m3 ( .A(nx2), .Y(nx3)); 13 | @@ @np a_buf_3 ( .A(nx3), .nbout(nb2)); 14 | @@ @nc a_buf_0 ( .A(nx1), .nbout(nb1)); 15 | @@ @nd a_buf_1 ( .A(nb1), .nbout(OUT)); 16 | @@ @ne a_buf_2 ( .A(nb2), .nbout(OUTB)); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/TEMP_AUTO_def.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | `define SD #1 4 | 5 | `define NUM_TUNE_BITS_DEC_DLY 5 6 | `define NUM_TUNE_BITS_WL_WIDTH 3 7 | 8 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/src/tempsenseInst.v: -------------------------------------------------------------------------------- 1 | module tempsenseInst 2 | ( 3 | input CLK_REF, 4 | input RESET_COUNTERn, 5 | input [3:0] SEL_CONV_TIME, 6 | input en, 7 | 8 | output [23:0] DOUT, 9 | output DONE, 10 | output out, outb, 11 | output lc_out 12 | ); 13 | 14 | wire VIN; 15 | TEMP_ANALOG_lv temp_analog_0( 16 | .EN(en), 17 | .OUT(out), 18 | .OUTB(outb) 19 | ); 20 | 21 | TEMP_ANALOG_hv temp_analog_1( 22 | .CLK_REF(CLK_REF), 23 | .RESET_COUNTERn(RESET_COUNTERn), 24 | .SEL_CONV_TIME(SEL_CONV_TIME), 25 | .out(out), 26 | .outb(outb), 27 | .DOUT(DOUT), 28 | .DONE(DONE), 29 | .lc_out(lc_out), 30 | .VIN(VIN) 31 | ); 32 | 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/test.json: -------------------------------------------------------------------------------- 1 | { 2 | "module_name": "tempsenseInst_error", 3 | "generator": "temp-sense-gen", 4 | "specifications": { 5 | "temperature": { "min": -20, "max": 100 }, 6 | "power": "", 7 | "error": "", 8 | "area": "", 9 | "optimization":"error", 10 | "model" :"modelfile.csv" 11 | } 12 | } -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/data_collection.py: -------------------------------------------------------------------------------- 1 | import os 2 | genDir = os.path.join(os.path.dirname(os.path.relpath(__file__)),"../") 3 | 4 | dir_name = 'run' 5 | folders = os.listdir(genDir + "./%s"%(dir_name)) 6 | current = os.getcwd() 7 | print("Temp,Frequency,Power,Error") 8 | #print(current) 9 | for folder in folders: 10 | os.chdir("%s/%s/%s"%(current,dir_name,folder)) 11 | os.system("source cal_result") 12 | for folder in folders: 13 | f = open("%s/%s/%s/code_result_with_error"%(current,dir_name,folder),'r') 14 | data = f.read() 15 | print(data) 16 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/result.py: -------------------------------------------------------------------------------- 1 | 2 | import sys 3 | 4 | ##### get result file name from cmd 5 | file_name = sys.argv[1] 6 | 7 | ##### open mt0 file 8 | r_mt0 = open(file_name) 9 | mt0_lines=r_mt0.readlines() 10 | 11 | ##### mt0 parse & data organizing 12 | ##### actual data starts from line 4 13 | data_start_line = 4 14 | result = list() 15 | result = mt0_lines[data_start_line-1].split() 16 | 17 | ##### print to output file 18 | #print("%s %s %s"%(result[3], result[1], result[2])) 19 | print("%s %s %s"%(result[4], result[1], result[2]), file=open("code_result", "a")) 20 | 21 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/tools/run_sim_top.py: -------------------------------------------------------------------------------- 1 | import os 2 | genDir = os.path.join(os.path.dirname(os.path.relpath(__file__)),"../") 3 | 4 | dir_name='run' 5 | folders = os.listdir(genDir + "./%s"%(dir_name)) 6 | current = os.getcwd() 7 | #w_file4 = open("./run_sim_top","w") 8 | for folder in folders: 9 | print(folder) 10 | os.chdir("%s/%s/%s"%(current,dir_name,folder)) 11 | os.system("source run_sim") 12 | -------------------------------------------------------------------------------- /generators/temp-sense-gen/work/.gitignore: -------------------------------------------------------------------------------- 1 | golden_* 2 | power_within_x.csv 3 | error_within_x.csv 4 | 5 | -------------------------------------------------------------------------------- /soc/config/soc_model_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": 0.1, 3 | "platforms": { 4 | "tsmc65lp": { 5 | "socModel": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/integration_tool_model", 6 | "generators":[ 7 | { 8 | "name":"ldo-gen", 9 | "train_test_input":"ldo_train_test_input.xlsx", 10 | "train_test_output":"ldo_train_test_output.xlsx", 11 | "whole":"ldo.csv", 12 | "inputs":["vin","imax"] 13 | }, 14 | { 15 | "name":"pll-gen", 16 | "train_test_input":"pll_train_test_input.xlsx", 17 | "train_test_output":"pll_train_test_output.xlsx", 18 | "whole":"pll.csv", 19 | "inputs":["fnom"] 20 | }, 21 | { 22 | "name":"memory-gen", 23 | "train_test_input":"memory_train_test_input.xlsx", 24 | "train_test_output":"memory_train_test_output.xlsx", 25 | "whole":"memory.csv", 26 | "inputs":["multiplication"] 27 | } 28 | ] 29 | } 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /soc/docs/flow.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/soc/docs/flow.jpg -------------------------------------------------------------------------------- /soc/docs/platform_config.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/soc/docs/platform_config.png -------------------------------------------------------------------------------- /soc/python/.nfs0000000000b80a310000210c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/idea-fasoc/fasoc/cd0dee46923bcc0abcbc5e8b76706a6188ede38f/soc/python/.nfs0000000000b80a310000210c -------------------------------------------------------------------------------- /soc/python/power_area_estimator/equation_solver.py: -------------------------------------------------------------------------------- 1 | from scipy.optimize import fsolve 2 | import math 3 | 4 | def equations(p): 5 | #vin, imax = p 6 | #return (-78*vin + 3700*imax-2194*vin*imax-23410*imax**2+22.9*vin**3+716382*imax**3) 7 | #vin, imax = fsolve(equations, (0.9, 0.01)) 8 | #print (equations((vin, imax))) 9 | fnom = p 10 | return(3.7442024014121142e04 + -6.846677e-05*fnom + 2.229949e-14*fnom**2 + 3.062494e-23*fnom**3 + -1.706576e-50*(fnom**6) - 8424) 11 | fnom = fsolve(equations, (512120593.997046)) 12 | print(equations(fnom)) 13 | print(fnom) -------------------------------------------------------------------------------- /soc/python/power_area_estimator/modifying_csv_columns_ml.py: -------------------------------------------------------------------------------- 1 | import csv 2 | import os 3 | import pandas as pd 4 | 5 | cwd = os.getcwd() 6 | pwd = os.path.abspath(os.path.join(cwd, os.pardir)) 7 | root_path_ml = os.path.join(pwd,'database','sheets','ML','generator') 8 | 9 | #df = pd.read_csv(os.path.join(root_path_ml,'inv_train_test_input.csv')) #For CSV files 10 | df = pd.read_excel(os.path.join(root_path_ml,'pll_train_test_output.xlsx'), sheet_name=0, header=0,index_col=False,keep_default_na=True) #For XLSX files 11 | 12 | saved_column = df['area'] 13 | #updated_column = saved_column / 10000 #ldo area 14 | updated_column = saved_column / 10000 #pll area 15 | 16 | df['area'] = updated_column 17 | #df.to_csv(os.path.join(root_path_ml,'ldo_area_train_test_input.csv'),index = False) #For CSV files 18 | df.to_excel(excel_writer = os.path.join(root_path_ml,'pll_train_test_output.xlsx'),index = False) #For XLSX files -------------------------------------------------------------------------------- /soc/python/power_area_estimator/y_interception.py: -------------------------------------------------------------------------------- 1 | import os 2 | import pandas as pd 3 | import numpy as np 4 | 5 | def y_interception(inputPath,outName,genName,inputsName): 6 | 7 | df = pd.read_csv(inputPath) #For CSV files 8 | input_list = ['None'] * len(inputsName) 9 | for counter,inputs in enumerate(inputsName): 10 | input_list[counter] = df[inputs] 11 | y_real = df[outName] 12 | 13 | 14 | if genName == 'ldo' and outName == 'area': 15 | y_pred = -1.423940e+05*input_list[0] + 4.189547e+06*input_list[1] + 1.787496e+04*(input_list[0]**2) + -1.412762e+06*input_list[0]*input_list[1] + 4.790724e+04*(input_list[0]**3) + -1.341138e+06*(input_list[0]**2)*input_list[1] + -4.912363e+07*input_list[0]*(input_list[1]**2) + 3.292007e+03*(input_list[0]**4) + -7.892173e+03*(input_list[0]**6) + 1.442646e+05*(input_list[0]**5)*input_list[1] + 2.869955e+07*(input_list[0]**4)*(input_list[1]**2) + -5.204883e+10*(input_list[0]**2)*(input_list[1]**4) + -7.779279e+11*input_list[0]*(input_list[1]**5) + 2.295740e+14*(input_list[1]**6) # ldo area 16 | 17 | elif genName == 'ldo' and outName == 'power': 18 | y_pred = 0*input_list[0] + 0*input_list[1] # ldo power 19 | 20 | elif genName == 'pll' and outName == 'area': 21 | y_pred = -6.846677e-05*input_list[0] + 2.229949e-14*input_list[0]**2 + 3.062494e-23*input_list[0]**3 + -1.706576e-50*(input_list[0]**6) # pll area 22 | 23 | elif genName == 'mem' and outName == 'area': 24 | y_pred = 4.891463*input_list[0] 25 | 26 | elif genName == 'mem' and outName == 'power': 27 | y_pred = 7.316895e-09*input_list[0] 28 | 29 | Y_diff = (y_real - y_pred) 30 | Y_interception = np.mean(Y_diff) 31 | print("Y interception: " + str(Y_interception)) -------------------------------------------------------------------------------- /soc/rubi/Define_SoCParameters.rb: -------------------------------------------------------------------------------- 1 | # MIT License 2 | 3 | # Copyright (c) 2018 The University of Michigan 4 | 5 | # Permission is hereby granted, free of charge, to any person obtaining a copy 6 | # of this software and associated documentation files (the "Software"), to deal 7 | # in the Software without restriction, including without limitation the rights 8 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | # copies of the Software, and to permit persons to whom the Software is 10 | # furnished to do so, subject to the following conditions: 11 | 12 | # The above copyright notice and this permission notice shall be included in all 13 | # copies or substantial portions of the Software. 14 | 15 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | # SOFTWARE. 22 | 23 | INCLUDE_ADCGEN = 0 24 | INCLUDE_CDCGEN = 0 25 | INCLUDE_DCDCGEN = 0 26 | INCLUDE_LDOGEN = 1 27 | INCLUDE_MEMGEN = 1 28 | INCLUDE_PLLGEN = 1 29 | INCLUDE_TEMPGEN = 1 -------------------------------------------------------------------------------- /soc/rubi/clean.rb: -------------------------------------------------------------------------------- 1 | require 'IPXACT2009API' 2 | 3 | design = getConfigItem("arg1", :default => ("arg1")) 4 | if component = findComponent(:name => "#{design}") 5 | deleteComponent(component) 6 | end 7 | -------------------------------------------------------------------------------- /soc/rubi/convert_json.rb: -------------------------------------------------------------------------------- 1 | # MIT License 2 | 3 | # Copyright (c) 2018 The University of Michigan 4 | 5 | # Permission is hereby granted, free of charge, to any person obtaining a copy 6 | # of this software and associated documentation files (the "Software"), to deal 7 | # in the Software without restriction, including without limitation the rights 8 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | # copies of the Software, and to permit persons to whom the Software is 10 | # furnished to do so, subject to the following conditions: 11 | 12 | # The above copyright notice and this permission notice shall be included in all 13 | # copies or substantial portions of the Software. 14 | 15 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | # SOFTWARE. 22 | 23 | require "json" 24 | require 'IPXACT2009API' 25 | 26 | infile = getConfigItem("arg1", :default => ("arg1")) 27 | design = getConfigItem("arg2", :default => ("arg2")) 28 | rubiDir = getConfigItem("arg3", :default => ("arg3")) 29 | load("#{rubiDir}/parse_json.rb") 30 | outfile_hier = getConfigItem("arg4", :default => ("arg4")) 31 | outfile_conn = getConfigItem("arg5", :default => ("arg5")) 32 | parse_json(infile, design, outfile_hier, outfile_conn) -------------------------------------------------------------------------------- /soc/rubi/generate.rb: -------------------------------------------------------------------------------- 1 | # MIT License 2 | 3 | # Copyright (c) 2018 The University of Michigan 4 | 5 | # Permission is hereby granted, free of charge, to any person obtaining a copy 6 | # of this software and associated documentation files (the "Software"), to deal 7 | # in the Software without restriction, including without limitation the rights 8 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | # copies of the Software, and to permit persons to whom the Software is 10 | # furnished to do so, subject to the following conditions: 11 | 12 | # The above copyright notice and this permission notice shall be included in all 13 | # copies or substantial portions of the Software. 14 | 15 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | # SOFTWARE. 22 | 23 | require 'IPXACT2009API' 24 | 25 | design_name = getConfigItem("arg1", :default => ("arg1")) 26 | component = findComponent(:name => design_name) 27 | LOGICAL_DIR = getConfigItem("arg2", :default => ("arg2")) 28 | system 'mkdir #{LOGICAL_DIR}/#{design_name}' 29 | system 'mkdir #{VERILOG_OUTPUT_DIR}' 30 | VERILOG_OUTPUT_DIR = "#{LOGICAL_DIR}/#{design_name}/verilog" 31 | 32 | runDRC(component, :checks => "IDEA_Checks") 33 | system "mv #{LOGICAL_DIR}/../../CheckResults.log #{LOGICAL_DIR}/../DRC.log" 34 | generateVerilog(component, :od => VERILOG_OUTPUT_DIR, :gen_leaf => true) -------------------------------------------------------------------------------- /soc/rubi/report.rb: -------------------------------------------------------------------------------- 1 | # MIT License 2 | 3 | # Copyright (c) 2018 The University of Michigan 4 | 5 | # Permission is hereby granted, free of charge, to any person obtaining a copy 6 | # of this software and associated documentation files (the "Software"), to deal 7 | # in the Software without restriction, including without limitation the rights 8 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | # copies of the Software, and to permit persons to whom the Software is 10 | # furnished to do so, subject to the following conditions: 11 | 12 | # The above copyright notice and this permission notice shall be included in all 13 | # copies or substantial portions of the Software. 14 | 15 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | # SOFTWARE. 22 | 23 | require 'IPXACT2009API' 24 | rubiDir = getConfigItem("arg1", :default => ("arg1")) 25 | load("#{rubiDir}/Status_utilities.rb") 26 | load("#{rubiDir}/VE_utilities.rb") 27 | 28 | design_name = getConfigItem("arg2", :default => ("arg2")) 29 | component = findComponent(:name => design_name) 30 | design = findDesign(:component => component, :stop_when_nil => true) 31 | 32 | #connStatus(component, :mode => :port, :filter => ".*", :sort_by => :instance) 33 | outfile = getConfigItem("arg3", :default => ("arg3")) 34 | 35 | insts = design.element("ComponentInstances").elements("ComponentInstance") 36 | f = File.open(outfile, "w") 37 | # Generate connectivity status report 38 | f.printf("#{connStatus(component, :mode => :port, :filter => ".*", :sort_by => :instance)}") 39 | # Generate Vendor Extensions report 40 | f.printf("Vendor Extensions Report\n\n") 41 | insts.each do |inst| 42 | comp = findComponent(:name => "#{inst.element("ComponentRef").get("Name")}") 43 | if !(comp.element("VendorExtensions").nil?) 44 | f.printf("#{getIDEA_VE(comp, :VE => "all")}") 45 | end 46 | end 47 | f.close 48 | -------------------------------------------------------------------------------- /tests/demo-feb-2021/Makefile: -------------------------------------------------------------------------------- 1 | ldo: 2 | ../../soc/python/soc.py --design ./design_ldo.json --platform gf12lp --mode verilog --database add --generator_config ../../config/generator_config_12.json --filelist ./file_list_12.tcl --synthesis_req False --socrates_req False 3 | clean_ldo: 4 | ../../soc/python/clean.py --design ./design_ldo.json --platform gf12lp --connection remove --synthesis do_not_remove -------------------------------------------------------------------------------- /tests/demo-feb-2021/design_ldo.json: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": 0.1, 3 | "design_name": "1ldo_1pll_1mem_1m0", 4 | "tech": "tsmc65lp", 5 | "strategy": "power", 6 | "units": { 7 | "vin": "V", 8 | "imax": "A", 9 | "power": "W", 10 | "word_size": "bit", 11 | "capacity": "bit", 12 | "Fnom_min": "Hz", 13 | "Fnom_max": "Hz", 14 | "nominal frequency": "Hz", 15 | "maximum frequency": "Hz", 16 | "minimum frequency": "Hz", 17 | "temperature": "C", 18 | "area": "um2" 19 | }, 20 | "constraints": { 21 | "power": 300, 22 | "area": 14000000 23 | }, 24 | "modules": [ 25 | { 26 | "module_name": "ldo1", 27 | "instance_name": "i_ldo1", 28 | "generator": "ldo-gen", 29 | "specifications": { 30 | "vin": 0.8, 31 | "imax": 0.001 32 | } 33 | }, 34 | { 35 | "module_name": "cmsdk_apb_slave_mux2", 36 | "instance_name": "u_apb_slave_mux2", 37 | "generator": "cmsdk_apb_slave_mux_rtl", 38 | "src": "/n/trenton/v/fayazi/fasoc/private/tests/tool/tape_out/fasoc_test/m0sdk/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v", 39 | "parameters": { 40 | "PORT0_ENABLE": 0, 41 | "PORT1_ENABLE": 1, 42 | "PORT2_ENABLE": 0, 43 | "PORT3_ENABLE": 0, 44 | "PORT4_ENABLE": 0, 45 | "PORT5_ENABLE": 1, 46 | "PORT6_ENABLE": 1, 47 | "PORT7_ENABLE": 0, 48 | "PORT8_ENABLE": 0, 49 | "PORT9_ENABLE": 0, 50 | "PORT10_ENABLE": 0, 51 | "PORT11_ENABLE": 0, 52 | "PORT12_ENABLE": 0, 53 | "PORT13_ENABLE": 0, 54 | "PORT14_ENABLE": 0, 55 | "PORT15_ENABLE": 0 56 | } 57 | }, 58 | { 59 | "module_name": "m0mcu2", 60 | "instance_name": "i_m0mcu2", 61 | "generator": "m0mcu_rtl", 62 | "area": 11129, 63 | "aspect_ratio": "1:1", 64 | "src": "/n/trenton/v/fayazi/fasoc/private/tests/tool/tape_out/fasoc_test/m0sdk/systems/cortex_m0_mcu/verilog/m0_wrapper.v" 65 | }, 66 | { 67 | "module_name": "ldo_mux2", 68 | "instance_name": "i_ldo_mux2", 69 | "generator": "ldo_mux_rtl", 70 | "src": "/n/trenton/v/fayazi/fasoc/private/tests/tool/tape_out/fasoc_test/src/ldo_mux.v" 71 | }, 72 | { 73 | "module_name": "gpio2", 74 | "instance_name": "i_gpio2", 75 | "generator": "gpio_rtl", 76 | "src": "/n/trenton/v/fayazi/fasoc/private/tests/tool/tape_out/fasoc_test/src/gpio_apb.v" 77 | } 78 | ] 79 | } -------------------------------------------------------------------------------- /tests/demo-jan-2020/Makefile: -------------------------------------------------------------------------------- 1 | soc1: 2 | ../../soc/python/soc.py --design ./design_ldo.json --mode verilog --database add 3 | soc2: 4 | ../../soc/python/soc.py --design ./design_ldo_pll.json --mode verilog --database add 5 | soc3: 6 | ../../soc/python/soc.py --design ./design_ldo_pll_mem.json --mode verilog --database add 7 | soc4: 8 | ../../soc/python/soc.py --design ./design_ldo.json --mode macro --database add 9 | soc_macro: 10 | ../../soc/python/soc.py --design ./design.json --mode macro --database add 11 | soc_full: 12 | ../../soc/python/soc.py --design ./design.json --mode full --database add 13 | clean1: 14 | ../../soc/python/clean.py --design ./design_ldo.json --connection remove --database remove 15 | clean2: 16 | ../../soc/python/clean.py --design ./design_ldo_pll.json --connection remove --database remove 17 | clean3: 18 | ../../soc/python/clean.py --design ./design_ldo_pll_mem.json --connection remove --database remove 19 | clean4: 20 | ../../soc/python/clean.py --design ./design_ldo.json --connection remove --database remove -------------------------------------------------------------------------------- /tests/demo-jan-2020/design_ldo.json: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": 0.1, 3 | "design_name": "1ldo_1m0", 4 | "tech": "tsmc65lp", 5 | "strategy": "power", 6 | "units": { 7 | "vin": "V", 8 | "imax": "A", 9 | "power": "W", 10 | "word_size": "bit", 11 | "capacity": "bit", 12 | "Fnom_min": "Hz", 13 | "Fnom_max": "Hz", 14 | "nominal frequency": "Hz", 15 | "maximum frequency": "Hz", 16 | "minimum frequency": "Hz", 17 | "temperature": "C", 18 | "area": "um2" 19 | }, 20 | "constraints": { 21 | "power": 0.3, 22 | "area": 13000 23 | }, 24 | "modules": [ 25 | { 26 | "module_name": "ldo1", 27 | "instance_name": "i_ldo1", 28 | "generator": "ldo-gen", 29 | "specifications": { 30 | "vin": 1.1, 31 | "imax": 0.006 32 | } 33 | }, 34 | { 35 | "module_name": "cmsdk_apb_slave_mux2", 36 | "instance_name": "u_apb_slave_mux2", 37 | "generator": "cmsdk_apb_slave_mux_rtl", 38 | "src": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database/verilog/cmsdk_apb_slave_mux.v", 39 | "parameters": { 40 | "PORT0_ENABLE": 0, 41 | "PORT1_ENABLE": 1, 42 | "PORT2_ENABLE": 0, 43 | "PORT3_ENABLE": 0, 44 | "PORT4_ENABLE": 0, 45 | "PORT5_ENABLE": 1, 46 | "PORT6_ENABLE": 1, 47 | "PORT7_ENABLE": 0, 48 | "PORT8_ENABLE": 0, 49 | "PORT9_ENABLE": 0, 50 | "PORT10_ENABLE": 0, 51 | "PORT11_ENABLE": 0, 52 | "PORT12_ENABLE": 0, 53 | "PORT13_ENABLE": 0, 54 | "PORT14_ENABLE": 0, 55 | "PORT15_ENABLE": 0 56 | } 57 | }, 58 | { 59 | "module_name": "cmsdk_ahb_to_apb2", 60 | "instance_name": "u_ahb_to_apb2", 61 | "generator": "cmsdk_ahb_to_apb_rtl", 62 | "src": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database/verilog/cmsdk_ahb_to_apb.v", 63 | "parameters": { 64 | "ADDRWIDTH": 16, 65 | "REGISTER_RDATA": 1, 66 | "REGISTER_WDATA": 0 67 | } 68 | }, 69 | { 70 | "module_name": "fasoc_m0mcu2", 71 | "instance_name": "i_fasoc_m0mcu2", 72 | "generator": "fasoc_m0mcu_rtl", 73 | "src": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database/verilog/fasoc_m0mcu.v" 74 | } 75 | ] 76 | } -------------------------------------------------------------------------------- /tests/pll/Makefile: -------------------------------------------------------------------------------- 1 | soc: 2 | ../../soc/python/fastSoc.py --design ./design.json --mode verilog --database add 3 | soc_macro: 4 | ../../soc/python/fastSoc.py --design ./design.json --mode macro --database add 5 | soc_full: 6 | ../../soc/python/fastSoc.py --design ./design.json --mode full --database add 7 | clean: 8 | ../../soc/python/clean.py --design ./design.json --connection remove -------------------------------------------------------------------------------- /tests/pll/design.json: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": 0.1, 3 | "design_name": "1mem", 4 | "tech": "tsmc65lp", 5 | "strategy": "power", 6 | "units": { 7 | "vin": "V", 8 | "imax": "A", 9 | "power": "W", 10 | "word_size": "bit", 11 | "capacity": "bit", 12 | "Fnom_min": "Hz", 13 | "Fnom_max": "Hz", 14 | "nominal frequency": "Hz", 15 | "maximum frequency": "Hz", 16 | "minimum frequency": "Hz", 17 | "temperature": "C", 18 | "area": "um2" 19 | }, 20 | "constraints": { 21 | "power": 0.3, 22 | "area": 500000 23 | }, 24 | "modules": [ 25 | { 26 | "module_name": "pll17", 27 | "generator": "pll-gen", 28 | "specifications": { 29 | "Fnom_min": 940000000.0, 30 | "Fnom_max": 960000000.0 31 | }, 32 | "instance_name": "i_pll18" 33 | }, 34 | { 35 | "module_name": "cmsdk_apb_slave_mux2", 36 | "instance_name": "u_apb_slave_mux2", 37 | "generator": "cmsdk_apb_slave_mux_rtl", 38 | "src": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database/verilog/cmsdk_apb_slave_mux.v", 39 | "parameters": { 40 | "PORT0_ENABLE": 0, 41 | "PORT1_ENABLE": 1, 42 | "PORT2_ENABLE": 0, 43 | "PORT3_ENABLE": 0, 44 | "PORT4_ENABLE": 0, 45 | "PORT5_ENABLE": 1, 46 | "PORT6_ENABLE": 1, 47 | "PORT7_ENABLE": 0, 48 | "PORT8_ENABLE": 0, 49 | "PORT9_ENABLE": 0, 50 | "PORT10_ENABLE": 0, 51 | "PORT11_ENABLE": 0, 52 | "PORT12_ENABLE": 0, 53 | "PORT13_ENABLE": 0, 54 | "PORT14_ENABLE": 0, 55 | "PORT15_ENABLE": 0 56 | } 57 | }, 58 | { 59 | "module_name": "cmsdk_ahb_to_apb2", 60 | "instance_name": "u_ahb_to_apb2", 61 | "generator": "cmsdk_ahb_to_apb_rtl", 62 | "src": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database/verilog/cmsdk_ahb_to_apb.v", 63 | "parameters": { 64 | "ADDRWIDTH": 16, 65 | "REGISTER_RDATA": 1, 66 | "REGISTER_WDATA": 0 67 | } 68 | }, 69 | { 70 | "module_name": "fasoc_m0mcu2", 71 | "instance_name": "i_fasoc_m0mcu2", 72 | "generator": "fasoc_m0mcu_rtl", 73 | "src": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database/verilog/fasoc_m0mcu.v" 74 | } 75 | ] 76 | } -------------------------------------------------------------------------------- /tests/power_area_model/Makefile: -------------------------------------------------------------------------------- 1 | model: 2 | ../../soc/python/power_area_estimator/wrapper.py --mode ml_regression --generator ldo-gen --constraint area 3 | evaluate: 4 | ../../soc/python/power_area_estimator/wrapper.py --mode model_evaluator --generator memory-gen --constraint power -------------------------------------------------------------------------------- /tests/tape_out/Makefile: -------------------------------------------------------------------------------- 1 | soc: 2 | ../../soc/python/soc.py --design ./design.json --mode verilog --database add 3 | soc_macro: 4 | ../../soc/python/soc.py --design ./design.json --mode macro --database add 5 | soc_full: 6 | ../../soc/python/soc.py --design ./design.json --mode full --database add 7 | clean: 8 | ../../soc/python/clean.py --design ./design.json --connection remove -------------------------------------------------------------------------------- /tests/temp_sens/Makefile: -------------------------------------------------------------------------------- 1 | soc: 2 | ../../soc/python/soc.py --design ./design_temp_sens.json --mode verilog --database add 3 | soc_macro: 4 | ../../soc/python/soc.py --design ./design_temp_sens.json --mode macro --database add 5 | soc_full: 6 | ../../soc/python/soc.py --design ./design_temp_sens.json --mode full --database add 7 | clean: 8 | ../../soc/python/clean.py --design ./design_temp_sens.json --connection remove --database remove -------------------------------------------------------------------------------- /tests/temp_sens/design_temp_sens.json: -------------------------------------------------------------------------------- 1 | { 2 | "schema_version": 0.1, 3 | "design_name": "1temp_snes_1m0", 4 | "tech": "tsmc65lp", 5 | "strategy": "power", 6 | "units": { 7 | "vin": "V", 8 | "imax": "A", 9 | "power": "W", 10 | "word_size": "bit", 11 | "capacity": "bit", 12 | "Fnom_min": "Hz", 13 | "Fnom_max": "Hz", 14 | "nominal frequency": "Hz", 15 | "maximum frequency": "Hz", 16 | "minimum frequency": "Hz", 17 | "temperature": "C", 18 | "area": "um2" 19 | }, 20 | "constraints": { 21 | "power": 0.3, 22 | "area": 13000 23 | }, 24 | "modules": [ 25 | { 26 | "instance_name": "tempsenseInst_error", 27 | "module_name": "temp_sens_1", 28 | "generator": "temp-sense-gen", 29 | "specifications": { 30 | "temperature": { 31 | "min": -20, 32 | "max": 100 33 | }, 34 | "power": "", 35 | "error": "", 36 | "area": "", 37 | "optimization": "error", 38 | "model": "modelfile.csv" 39 | } 40 | }, 41 | { 42 | "module_name": "cmsdk_apb_slave_mux2", 43 | "instance_name": "u_apb_slave_mux2", 44 | "generator": "cmsdk_apb_slave_mux_rtl", 45 | "src": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database/verilog/cmsdk_apb_slave_mux.v", 46 | "parameters": { 47 | "PORT0_ENABLE": 0, 48 | "PORT1_ENABLE": 1, 49 | "PORT2_ENABLE": 0, 50 | "PORT3_ENABLE": 0, 51 | "PORT4_ENABLE": 0, 52 | "PORT5_ENABLE": 1, 53 | "PORT6_ENABLE": 1, 54 | "PORT7_ENABLE": 0, 55 | "PORT8_ENABLE": 0, 56 | "PORT9_ENABLE": 0, 57 | "PORT10_ENABLE": 0, 58 | "PORT11_ENABLE": 0, 59 | "PORT12_ENABLE": 0, 60 | "PORT13_ENABLE": 0, 61 | "PORT14_ENABLE": 0, 62 | "PORT15_ENABLE": 0 63 | } 64 | }, 65 | { 66 | "module_name": "cmsdk_ahb_to_apb2", 67 | "instance_name": "u_ahb_to_apb2", 68 | "generator": "cmsdk_ahb_to_apb_rtl", 69 | "src": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database/verilog/cmsdk_ahb_to_apb.v", 70 | "parameters": { 71 | "ADDRWIDTH": 16, 72 | "REGISTER_RDATA": 1, 73 | "REGISTER_WDATA": 0 74 | } 75 | }, 76 | { 77 | "module_name": "fasoc_m0mcu2", 78 | "instance_name": "i_fasoc_m0mcu2", 79 | "generator": "fasoc_m0mcu_rtl", 80 | "src": "/afs/eecs.umich.edu/cadre/projects/fasoc/share/database/verilog/fasoc_m0mcu.v" 81 | } 82 | ] 83 | } --------------------------------------------------------------------------------