├── LICENSE ├── README.md ├── images ├── 0-1.jpg ├── 0-2.jpg ├── 0-3.jpg ├── 1-1.bmp ├── 1-10.bmp ├── 1-2.bmp ├── 1-3.bmp ├── 1-4.bmp ├── 1-5.bmp ├── 1-6.bmp ├── 1-7.bmp ├── 1-8.bmp ├── 1-9.bmp ├── 2-1.jpg ├── 2-10.jpg ├── 2-11.jpg ├── 2-12.jpg ├── 2-2.jpg ├── 2-3.jpg ├── 2-4.jpg ├── 2-5.jpg ├── 2-6.jpg ├── 2-7.jpg ├── 2-8.jpg └── 2-9.jpg └── isp_base ├── isp_base.cache └── wt │ ├── gui_handlers.wdf │ ├── java_command_handlers.wdf │ ├── project.wpc │ ├── synthesis.wdf │ ├── synthesis_details.wdf │ ├── webtalk_pa.xml │ └── xsim.wdf ├── isp_base.hw └── isp_base.lpr ├── isp_base.ip_user_files ├── README.txt ├── ip │ └── shift_RAM_3X3_8bit │ │ ├── shift_RAM_3X3_8bit.veo │ │ ├── shift_RAM_3X3_8bit.vho │ │ ├── shift_RAM_3X3_8bit_stub.v │ │ └── shift_RAM_3X3_8bit_stub.vhdl ├── ipstatic │ └── hdl │ │ ├── c_mux_bit_v12_0_vh_rfs.vhd │ │ ├── c_reg_fd_v12_0_vh_rfs.vhd │ │ ├── c_shift_ram_v12_0_vh_rfs.vhd │ │ └── xbip_utils_v3_0_vh_rfs.vhd └── sim_scripts │ └── shift_RAM_3X3_8bit │ ├── README.txt │ ├── activehdl │ ├── README.txt │ ├── compile.do │ ├── file_info.txt │ ├── shift_RAM_3X3_8bit.sh │ ├── shift_RAM_3X3_8bit.udo │ ├── simulate.do │ └── wave.do │ ├── ies │ ├── README.txt │ ├── file_info.txt │ ├── run.f │ └── shift_RAM_3X3_8bit.sh │ ├── modelsim │ ├── README.txt │ ├── compile.do │ ├── file_info.txt │ ├── shift_RAM_3X3_8bit.sh │ ├── shift_RAM_3X3_8bit.udo │ ├── simulate.do │ └── wave.do │ ├── questa │ ├── README.txt │ ├── compile.do │ ├── elaborate.do │ ├── file_info.txt │ ├── shift_RAM_3X3_8bit.sh │ ├── shift_RAM_3X3_8bit.udo │ ├── simulate.do │ └── wave.do │ ├── riviera │ ├── README.txt │ ├── compile.do │ ├── file_info.txt │ ├── shift_RAM_3X3_8bit.sh │ ├── shift_RAM_3X3_8bit.udo │ ├── simulate.do │ └── wave.do │ ├── vcs │ ├── README.txt │ ├── file_info.txt │ ├── shift_RAM_3X3_8bit.sh │ └── simulate.do │ ├── xcelium │ ├── README.txt │ ├── file_info.txt │ ├── run.f │ └── shift_RAM_3X3_8bit.sh │ └── xsim │ ├── README.txt │ ├── cmd.tcl │ ├── elab.opt │ ├── file_info.txt │ ├── shift_RAM_3X3_8bit.sh │ ├── vhdl.prj │ └── xsim.ini ├── isp_base.runs ├── .jobs │ ├── vrs_config_1.xml │ ├── vrs_config_2.xml │ └── vrs_config_3.xml ├── shift_RAM_3X3_8bit_synth_1 │ ├── .Vivado_Synthesis.queue.rst │ ├── .vivado.begin.rst │ ├── .vivado.end.rst │ ├── ISEWrap.js │ ├── ISEWrap.sh │ ├── __synthesis_is_complete__ │ ├── dont_touch.xdc │ ├── gen_run.xml │ ├── htr.txt │ ├── project.wdf │ ├── rundef.js │ ├── runme.bat │ ├── runme.log │ ├── runme.sh │ ├── shift_RAM_3X3_8bit.dcp │ ├── shift_RAM_3X3_8bit.tcl │ ├── shift_RAM_3X3_8bit.vds │ ├── shift_RAM_3X3_8bit_utilization_synth.pb │ ├── shift_RAM_3X3_8bit_utilization_synth.rpt │ ├── vivado.jou │ └── vivado.pb └── synth_1 │ ├── .Vivado_Synthesis.queue.rst │ ├── .vivado.begin.rst │ ├── .vivado.end.rst │ ├── ISEWrap.js │ ├── ISEWrap.sh │ ├── __synthesis_is_complete__ │ ├── gen_run.xml │ ├── htr.txt │ ├── project.wdf │ ├── rundef.js │ ├── runme.bat │ ├── runme.log │ ├── runme.sh │ ├── top.dcp │ ├── top.tcl │ ├── top.vds │ ├── top_utilization_synth.pb │ ├── top_utilization_synth.rpt │ ├── vivado.jou │ └── vivado.pb ├── isp_base.sim └── sim_1 │ └── behav │ └── xsim │ ├── compile.bat │ ├── compile.log │ ├── elaborate.bat │ ├── elaborate.log │ ├── glbl.v │ ├── simulate.bat │ ├── simulate.log │ ├── tb_rgb2gray.tcl │ ├── tb_rgb2gray_behav.wdb │ ├── tb_rgb2gray_vlog.prj │ ├── tb_top.tcl │ ├── tb_top_behav.wdb │ ├── tb_top_vhdl.prj │ ├── tb_top_vlog.prj │ ├── webtalk.jou │ ├── webtalk.log │ ├── webtalk_13860.backup.jou │ ├── webtalk_13860.backup.log │ ├── webtalk_23448.backup.jou │ ├── webtalk_23448.backup.log │ ├── webtalk_5072.backup.jou │ ├── webtalk_5072.backup.log │ ├── webtalk_5100.backup.jou │ ├── webtalk_5100.backup.log │ ├── webtalk_9352.backup.jou │ ├── webtalk_9352.backup.log │ ├── xelab.pb │ ├── xsim.dir │ ├── tb_top_behav │ │ ├── Compile_Options.txt │ │ ├── TempBreakPointFile.txt │ │ ├── obj │ │ │ ├── xsim_0.win64.obj │ │ │ ├── xsim_1.c │ │ │ └── xsim_1.win64.obj │ │ ├── webtalk │ │ │ ├── .xsim_webtallk.info │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ └── xsim_webtalk.tcl │ │ ├── xsim.dbg │ │ ├── xsim.mem │ │ ├── xsim.reloc │ │ ├── xsim.rlx │ │ ├── xsim.rtti │ │ ├── xsim.svtype │ │ ├── xsim.type │ │ ├── xsim.xdbg │ │ ├── xsimSettings.ini │ │ ├── xsimcrash.log │ │ ├── xsimk.exe │ │ └── xsimkernel.log │ └── xil_defaultlib │ │ ├── dilation.sdb │ │ ├── erosion.sdb │ │ ├── glbl.sdb │ │ ├── gray2bin.sdb │ │ ├── median_filter.sdb │ │ ├── rgb2gray.sdb │ │ ├── shift_ram_3x3_8bit.vdb │ │ ├── sobel.sdb │ │ ├── sort3.sdb │ │ ├── tb_top.sdb │ │ ├── top.sdb │ │ └── xil_defaultlib.rlx │ ├── xsim.ini │ ├── xsim.ini.bak │ ├── xvhdl.log │ ├── xvhdl.pb │ ├── xvlog.log │ └── xvlog.pb ├── isp_base.srcs ├── sim_1 │ └── new │ │ ├── tb_rgb2gray.v │ │ └── tb_top.v └── sources_1 │ ├── ip │ └── shift_RAM_3X3_8bit │ │ ├── doc │ │ └── c_shift_ram_v12_0_changelog.txt │ │ ├── hdl │ │ ├── c_mux_bit_v12_0_vh_rfs.vhd │ │ ├── c_reg_fd_v12_0_vh_rfs.vhd │ │ ├── c_shift_ram_v12_0_vh_rfs.vhd │ │ └── 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