├── doc ├── voltage_dac.png ├── sensor_simulation_result.png ├── synthesized_temperature_sensor.png ├── sensor_simulation_result.py ├── synthesized_temperature_sensor.drawio └── voltage_dac.drawio ├── src ├── pin_order.cfg ├── tb.gtkw ├── test.py ├── tb.v ├── seg7.v ├── Makefile ├── bin2dec.v ├── tempsense_paper.v ├── vdac.v ├── vdac_cell.v ├── config.tcl ├── tempsense.v └── hpretl_tt03_temperature_sensor.v ├── sim ├── simulation │ ├── tempsens.gds │ ├── tempsens_layout.png │ ├── .spiceinit │ ├── tb_tempsens.spice │ ├── tb_tempsens.xyce.spice │ └── sim.sh ├── sim.sh ├── build.sh ├── tb_bin2dec.v ├── tb_tempsens.v ├── hpretl_tt03_temperature_sensor.sym └── tb_tempsens.sch ├── .github ├── FUNDING.yml ├── ISSUE_TEMPLATE │ └── bug_report.md └── workflows │ ├── test.yaml │ ├── docs.yaml │ └── gds.yaml ├── .gitignore ├── archive └── delay_cell.v ├── README.md ├── info.yaml └── LICENSE /doc/voltage_dac.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iic-jku/tt03-tempsensor/HEAD/doc/voltage_dac.png -------------------------------------------------------------------------------- /src/pin_order.cfg: -------------------------------------------------------------------------------- 1 | #N 2 | 3 | #S 4 | 5 | #E 6 | 7 | #W 8 | io_in.* 9 | io_out.* 10 | -------------------------------------------------------------------------------- /sim/simulation/tempsens.gds: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iic-jku/tt03-tempsensor/HEAD/sim/simulation/tempsens.gds -------------------------------------------------------------------------------- /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | # These are supported funding model platforms 2 | 3 | custom: ['https://zerotoasiccourse.com'] 4 | -------------------------------------------------------------------------------- /doc/sensor_simulation_result.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iic-jku/tt03-tempsensor/HEAD/doc/sensor_simulation_result.png -------------------------------------------------------------------------------- /sim/simulation/tempsens_layout.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iic-jku/tt03-tempsensor/HEAD/sim/simulation/tempsens_layout.png -------------------------------------------------------------------------------- /doc/synthesized_temperature_sensor.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/iic-jku/tt03-tempsensor/HEAD/doc/synthesized_temperature_sensor.png -------------------------------------------------------------------------------- /sim/simulation/.spiceinit: -------------------------------------------------------------------------------- 1 | set num_threads=8 2 | set ngbehavior=hsa 3 | set ng_nomodcheck 4 | set enable_noisy_r 5 | set filetype=ascii 6 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | .idea 3 | .vscode 4 | *.vcd 5 | runs 6 | src/sim_build 7 | src/__pycache__/ 8 | src/results.xml 9 | src/user_config.tcl 10 | *.raw 11 | *.cvcrc 12 | *.out 13 | *.bkp 14 | .pycache 15 | -------------------------------------------------------------------------------- /sim/sim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | [ -f tb_tempsens.vcd ] && rm tb_tempsens.vcd 4 | [ -f tb_tempsens.out ] && rm tb_tempsens.out 5 | 6 | iverilog -o tb_tempsens.out -I ../src -D SIMULATION tb_tempsens.v 7 | ./tb_tempsens.out 8 | gtkwave tb_tempsens.vcd 9 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug_report.md: -------------------------------------------------------------------------------- 1 | --- 2 | name: Bug report 3 | about: Create a report to help us improve 4 | title: '' 5 | labels: '' 6 | assignees: mattvenn 7 | 8 | --- 9 | 10 | **Link to your wokwi project** 11 | 12 | Please put a link to your wokwi project here. 13 | -------------------------------------------------------------------------------- /doc/sensor_simulation_result.py: -------------------------------------------------------------------------------- 1 | import numpy as np 2 | import matplotlib.pyplot as plt 3 | 4 | # This values have been found by parasitic extraction of the .mag file produced 5 | # by OpenLane, and this resulting SPICE netlist has been included in a xschem- 6 | # based simulation testbench for ngspice. 7 | 8 | temperature = [-30, 0, 30, 60, 90, 120] 9 | code_result = [26, 24, 21, 17, 13, 7] 10 | 11 | plt.xlabel('Temperature (degree Celsius)') 12 | plt.ylabel('Output Code') 13 | plt.xticks(np.arange(-30,130,10)) 14 | plt.yticks(np.arange(0,30,5)) 15 | plt.grid() 16 | plt.title('Temperature Sensor Simulation Result') 17 | plt.plot(temperature, code_result, '-bv', markersize = '5') 18 | plt.axis([-30, 120, 0, 30]) 19 | plt.show() 20 | -------------------------------------------------------------------------------- /sim/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | [ -f hpretl_tt03_temperature_sensor.mag ] && rm hpretl_tt03_temperature_sensor.mag 4 | [ -f pretl_tt03_temperature_sensor.pex.spice ] && rm pretl_tt03_temperature_sensor.pex.spice 5 | 6 | # Run OpenLane flow to build layout 7 | flow.tcl -design ../src -tag foo -overwrite 8 | cp ../src/runs/foo/results/final/mag/hpretl_tt03_temperature_sensor.mag . 9 | 10 | # Extract netlist from layout 11 | iic-pex.sh -m 1 -s 1 hpretl_tt03_temperature_sensor.mag 12 | 13 | # Get rid of MOSFET for decoupling 14 | TMP=tmp.spice 15 | mv hpretl_tt03_temperature_sensor.pex.spice $TMP 16 | cat $TMP | grep -v "vccd1 vssd1 vccd1 vccd1" | grep -v "vssd1 vccd1 vssd1 vssd1" > hpretl_tt03_temperature_sensor.pex.spice 17 | rm $TMP 18 | -------------------------------------------------------------------------------- /sim/tb_bin2dec.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `define SIMULATION 3 | `include "bin2dec.v" 4 | `timescale 1us/1ns 5 | 6 | module tb_bin2dec; 7 | 8 | reg [6:0] BIN; 9 | reg ONES = 1, TENS = 0; 10 | wire [3:0] DEC; 11 | integer i; 12 | 13 | 14 | initial begin 15 | $dumpfile ("tb_bin2dec.vcd"); 16 | $dumpvars (0, tb_bin2dec); 17 | 18 | for (i=0; i<100; i=i+1) begin 19 | BIN = i; 20 | 21 | #1 TENS = 1; 22 | ONES = 0; 23 | 24 | #1 TENS = 0; 25 | ONES = 1; 26 | end 27 | 28 | $finish; 29 | end 30 | 31 | 32 | // instantiate the DUT 33 | bin2dec b2d ( 34 | .i_bin(BIN), 35 | .i_tens(TENS), 36 | .i_ones(ONES), 37 | .o_dec(DEC) 38 | ); 39 | 40 | endmodule // tb_bin2dec 41 | -------------------------------------------------------------------------------- /src/tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Mon Mar 6 16:19:53 2023 4 | [*] 5 | [dumpfile] "/home/matt/work/asic-workshop/shuttle9/tt03-verilog-demo/src/tb.vcd" 6 | [dumpfile_mtime] "Mon Mar 6 16:18:34 2023" 7 | [dumpfile_size] 723297 8 | [savefile] "/home/matt/work/asic-workshop/shuttle9/tt03-verilog-demo/src/tb.gtkw" 9 | [timestart] 0 10 | [size] 2286 698 11 | [pos] -1 -1 12 | *-30.600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] tb. 14 | [sst_width] 343 15 | [signals_width] 264 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 190 18 | @28 19 | tb.clk 20 | tb.rst 21 | @22 22 | tb.segments[6:0] 23 | @800022 24 | tb.seven_segment_seconds.io_out[7:0] 25 | @28 26 | (0)tb.seven_segment_seconds.io_out[7:0] 27 | @1001200 28 | -group_end 29 | [pattern_trace] 1 30 | [pattern_trace] 0 31 | -------------------------------------------------------------------------------- /src/test.py: -------------------------------------------------------------------------------- 1 | import cocotb 2 | from cocotb.clock import Clock 3 | from cocotb.triggers import RisingEdge, FallingEdge, Timer, ClockCycles 4 | 5 | 6 | segments = [ 63, 6, 91, 79, 102, 109, 124, 7, 127, 103 ] 7 | 8 | @cocotb.test() 9 | async def test_tempsens(dut): 10 | dut._log.info("start") 11 | clock = Clock(dut.clk, 100, units="us") 12 | cocotb.start_soon(clock.start()) 13 | 14 | dut._log.info("configuration") 15 | dut.en_quick_transition.value = 0 16 | dut.tempsens_cfg = 3 17 | 18 | dut._log.info("reset") 19 | dut.rst.value = 1 20 | await ClockCycles(dut.clk, 10) 21 | dut.rst.value = 0 22 | 23 | dut._log.info("check all segments") 24 | for i in range(10): 25 | dut._log.info("check segment {}".format(i)) 26 | await ClockCycles(dut.clk, 1000) 27 | assert int(dut.segments.value) == segments[i] 28 | -------------------------------------------------------------------------------- /.github/workflows/test.yaml: -------------------------------------------------------------------------------- 1 | name: test 2 | # either manually started, or on a schedule 3 | on: [ push, workflow_dispatch ] 4 | jobs: 5 | test: 6 | # ubuntu 7 | runs-on: ubuntu-latest 8 | steps: 9 | # need the repo checked out 10 | - name: checkout repo 11 | uses: actions/checkout@v3 12 | 13 | # install oss fpga tools 14 | - name: install oss-cad-suite 15 | uses: YosysHQ/setup-oss-cad-suite@v2 16 | with: 17 | python-override: true 18 | github-token: ${{ secrets.GITHUB_TOKEN }} 19 | - run: | 20 | yosys --version 21 | iverilog -V 22 | cocotb-config --libpython 23 | cocotb-config --python-bin 24 | 25 | - name: test 26 | run: | 27 | cd src 28 | make clean 29 | make 30 | # make will return success even if the test fails, so check for failure in the results.xml 31 | ! grep failure results.xml 32 | 33 | - name: upload vcd 34 | if: success() || failure() 35 | uses: actions/upload-artifact@v3 36 | with: 37 | name: test-vcd 38 | path: src/tb.vcd 39 | 40 | -------------------------------------------------------------------------------- /src/tb.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `timescale 1ns/1ps 3 | 4 | /* 5 | this testbench just instantiates the module and makes some convenient wires 6 | that can be driven / tested by the cocotb test.py 7 | */ 8 | 9 | module tb ( 10 | // testbench is controlled by test.py 11 | input clk, 12 | input rst, 13 | input en_quick_transition, 14 | input [4:0] tempsens_cfg, 15 | output tempsens_pwm, 16 | output [6:0] segments 17 | ); 18 | 19 | // this part dumps the trace to a vcd file that can be viewed with GTKWave 20 | initial begin 21 | $dumpfile ("tb.vcd"); 22 | $dumpvars (0, tb); 23 | #1; 24 | end 25 | 26 | // wire up the inputs and outputs 27 | wire [7:0] inputs = {tempsens_cfg, en_quick_transition, rst, clk}; 28 | wire [7:0] outputs; 29 | assign segments = outputs[6:0]; 30 | assign tempsens_pwm = outputs[7]; 31 | 32 | // instantiate the DUT 33 | hpretl_tt03_temperature_sensor tempsens ( 34 | `ifdef GL_TEST 35 | .vccd1( 1'b1), 36 | .vssd1( 1'b0), 37 | `endif 38 | .io_in (inputs), 39 | .io_out (outputs) 40 | ); 41 | 42 | endmodule // tb 43 | -------------------------------------------------------------------------------- /sim/tb_tempsens.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `define SIMULATION 3 | `include "hpretl_tt03_temperature_sensor.v" 4 | `timescale 1us/1ns 5 | 6 | //`define RAW_MODE 7 | 8 | module tb_tempsens; 9 | 10 | reg CLK = 0; 11 | reg RESET = 1; 12 | reg CAL_CLK = 0; 13 | reg CAL_DAT = 0; 14 | reg CAL_ENA = 1; 15 | `ifdef RAW_MODE 16 | reg [2:0] DBG = 3'b011; 17 | `endif 18 | `ifndef RAW_MODE 19 | reg [2:0] DBG = 0; 20 | `endif 21 | wire [7:0] LEDDISP; 22 | 23 | 24 | initial begin 25 | $dumpfile ("tb_tempsens.vcd"); 26 | $dumpvars (0, tb_tempsens); 27 | 28 | #50 CAL_CLK = 1; 29 | #150 CAL_CLK = 0; 30 | 31 | #100 RESET = 0; 32 | 33 | #1200000 $finish; 34 | end 35 | 36 | // make clock 10kHz 37 | always #50 CLK = ~CLK; 38 | 39 | 40 | // wire up the inputs and outputs 41 | wire [7:0] inputs = {DBG, CAL_ENA, CAL_DAT, CAL_CLK, RESET, CLK}; 42 | wire [7:0] outputs; 43 | assign LEDDISP = outputs[7:0]; 44 | 45 | // instantiate the DUT 46 | hpretl_tt03_temperature_sensor tempsens ( 47 | .io_in (inputs), 48 | .io_out (outputs) 49 | ); 50 | 51 | endmodule // tb_tempsens 52 | -------------------------------------------------------------------------------- /src/seg7.v: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | -- 1 -- 4 | | | 5 | 6 2 6 | | | 7 | -- 7 -- 8 | | | 9 | 5 3 10 | | | 11 | -- 4 -- 12 | */ 13 | 14 | `ifndef __SEG7__ 15 | `define __SEG7__ 16 | 17 | `default_nettype none 18 | 19 | module seg7 ( 20 | input wire [3:0] i_disp, 21 | output reg [6:0] o_segments 22 | ); 23 | 24 | always @(*) begin 25 | case(i_disp) 26 | // 7654321 27 | // numeric characters 28 | 0: o_segments = 7'b0111111; // O 29 | 1: o_segments = 7'b0000110; 30 | 2: o_segments = 7'b1011011; 31 | 3: o_segments = 7'b1001111; 32 | 4: o_segments = 7'b1100110; 33 | 5: o_segments = 7'b1101101; 34 | 6: o_segments = 7'b1111100; 35 | 7: o_segments = 7'b0000111; 36 | 8: o_segments = 7'b1111111; 37 | 9: o_segments = 7'b1100111; 38 | // special characters 39 | 10: o_segments = 7'b0000000; // blank 40 | 11: o_segments = 7'b1111111; // full 41 | 12: o_segments = 7'b1110110; // X 42 | 13: o_segments = 7'b0000001; // top bar 43 | 14: o_segments = 7'b1000000; // middle bar 44 | 15: o_segments = 7'b0001000; // bottom bar 45 | default: 46 | o_segments = 7'b0000000; 47 | endcase 48 | end 49 | 50 | endmodule // seg7 51 | `endif 52 | -------------------------------------------------------------------------------- /src/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile 2 | # See https://docs.cocotb.org/en/stable/quickstart.html for more info 3 | 4 | # defaults 5 | SIM ?= icarus 6 | TOPLEVEL_LANG ?= verilog 7 | 8 | # normal simulation 9 | ifneq ($(GATES),yes) 10 | 11 | # this is the only part you should need to modify: 12 | VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/hpretl_tt03_temperature_sensor.v $(PWD)/tempsense.v $(PWD)/vdac.v $(PWD)/vdac_cell.v $(PWD)/seg7.v 13 | 14 | else 15 | 16 | # gate level simulation requires some extra setup, you shouldn't need to touch this 17 | COMPILE_ARGS += -DGL_TEST 18 | COMPILE_ARGS += -DFUNCTIONAL 19 | COMPILE_ARGS += -DUSE_POWER_PINS 20 | COMPILE_ARGS += -DSIM 21 | COMPILE_ARGS += -DUNIT_DELAY=#1 22 | VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v 23 | VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v 24 | 25 | # this gets copied in by the GDS action workflow 26 | VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/gate_level_netlist.v 27 | endif 28 | 29 | # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file 30 | TOPLEVEL = tb 31 | 32 | # MODULE is the basename of the Python test file 33 | MODULE = test 34 | 35 | # include cocotb's make rules to take care of the simulator setup 36 | include $(shell cocotb-config --makefiles)/Makefile.sim 37 | -------------------------------------------------------------------------------- /.github/workflows/docs.yaml: -------------------------------------------------------------------------------- 1 | name: docs 2 | # either manually started, or on a schedule 3 | on: [ push, workflow_dispatch ] 4 | permissions: 5 | contents: write 6 | pages: write 7 | id-token: write 8 | jobs: 9 | docs: 10 | # ubuntu 11 | runs-on: ubuntu-latest 12 | steps: 13 | # need the repo checked out 14 | - name: checkout repo 15 | uses: actions/checkout@v3 16 | 17 | # tt tools 18 | - name: checkout tt tools repo 19 | uses: actions/checkout@v3 20 | with: 21 | repository: tinytapeout/tt-support-tools 22 | path: tt 23 | 24 | # for debugging, show all the files 25 | - name: show files 26 | run: find . 27 | 28 | # need python 29 | - name: setup python 30 | uses: actions/setup-python@v4 31 | with: 32 | python-version: '3.10' 33 | - run: pip install -r tt/requirements.txt 34 | 35 | # check docs 36 | - name: build pdf 37 | run: ./tt/tt_tool.py --check-docs 38 | 39 | # pandoc deps 40 | - name: Pandoc deps 41 | run: | 42 | sudo apt-get update -y 43 | sudo apt-get install -y pandoc texlive-xetex 44 | 45 | # create the pdf 46 | - name: create pdf 47 | run: ./tt/tt_tool.py --create-pdf 48 | 49 | # archive the PDF 50 | - name: Archive PDF 51 | uses: actions/upload-artifact@v3 52 | with: 53 | name: PDF 54 | path: datasheet.pdf 55 | -------------------------------------------------------------------------------- /sim/simulation/tb_tempsens.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /foss/designs/sim/tb_tempsens.sch 2 | **.subckt tb_tempsens 3 | VDD1 net1 GND 1.8 4 | V19 ts_cfg5 GND 0 5 | V20 ts_cfg4 GND 1.8 6 | V21 ts_cfg3 GND 1.8 7 | V22 ts_cfg2 GND 0 8 | V23 ts_cfg1 GND 0 9 | V24 ts_cfg0 GND 0 10 | VCM clk GND 0 pulse(0 1.8 1u 1n 1n {0.5/fclk} {1/fclk}) 11 | VRES rst GND 1.8 pwl(0 1.8 {0.5/fclk} 1.8 {0.5/fclk+1n} 0) 12 | x1 rst ts_cfg0 ts_cfg1 ts_cfg2 ts_cfg3 ts_cfg4 ts_cfg5 st0 st1 st2 st3 st4 st5 st6 st7 clk VDD GND hpretl_tt03_temperature_sensor 13 | C1 st7 GND 10f m=1 14 | C3 st1 GND 10f m=1 15 | C4 st0 GND 10f m=1 16 | C2 st3 GND 10f m=1 17 | C5 st2 GND 10f m=1 18 | C6 st5 GND 10f m=1 19 | C7 st4 GND 10f m=1 20 | C8 st6 GND 10f m=1 21 | Visupply VDD net1 0 22 | .save i(visupply) 23 | .save v(st0) 24 | .save v(st1) 25 | .save v(st2) 26 | .save v(st3) 27 | .save v(st4) 28 | .save v(st5) 29 | .save v(st6) 30 | .save v(st7) 31 | **** begin user architecture code 32 | 33 | ** opencircuitdesign pdks install 34 | .lib sky130.lib.spice.tt.red tt 35 | 36 | 37 | 38 | 39 | 40 | * ngspice commands 41 | **************** 42 | .include hpretl_tt03_temperature_sensor_golden.pex.spice 43 | 44 | **************** 45 | * Misc 46 | **************** 47 | .param fclk=10k 48 | .options method=gear maxord=2 49 | .temp 30 50 | 51 | .control 52 | tran 10u 30m 53 | *tran 10u 20u 54 | 55 | let k=length(time)-1 56 | print st0[k] st1[k] st2[k] st3[k] st4[k] st5[k] st6[k] st7[k] > res.txt 57 | 58 | exit 59 | .endc 60 | 61 | 62 | 63 | **** end user architecture code 64 | **.ends 65 | .GLOBAL VDD 66 | .GLOBAL GND 67 | .end 68 | -------------------------------------------------------------------------------- /sim/simulation/tb_tempsens.xyce.spice: -------------------------------------------------------------------------------- 1 | ** sch_path: /foss/designs/sim/tb_tempsens.sch 2 | **.subckt tb_tempsens 3 | VDD1 net1 GND 1.8 4 | V19 ts_cfg5 GND 0 5 | V20 ts_cfg4 GND 1.8 6 | V21 ts_cfg3 GND 1.8 7 | V22 ts_cfg2 GND 0 8 | V23 ts_cfg1 GND 0 9 | V24 ts_cfg0 GND 0 10 | VCM clk GND 0 pulse(0 1.8 1u 1n 1n {0.5/fclk} {1/fclk}) 11 | VRES rst GND 1.8 pwl(0 1.8 {0.5/fclk} 1.8 {0.5/fclk+1n} 0) 12 | x1 rst ts_cfg0 ts_cfg1 ts_cfg2 ts_cfg3 ts_cfg4 ts_cfg5 st0 st1 st2 st3 st4 st5 st6 st7 clk VDD GND hpretl_tt03_temperature_sensor 13 | C1 st7 GND 10f m=1 14 | C3 st1 GND 10f m=1 15 | C4 st0 GND 10f m=1 16 | C2 st3 GND 10f m=1 17 | C5 st2 GND 10f m=1 18 | C6 st5 GND 10f m=1 19 | C7 st4 GND 10f m=1 20 | C8 st6 GND 10f m=1 21 | Visupply VDD net1 0 22 | *.save i(visupply) 23 | *.save v(st0) 24 | *.save v(st1) 25 | *.save v(st2) 26 | *.save v(st3) 27 | *.save v(st4) 28 | *.save v(st5) 29 | *.save v(st6) 30 | *.save v(st7) 31 | **** begin user architecture code 32 | 33 | ** opencircuitdesign pdks install 34 | .lib sky130.lib.spice.tt.red tt 35 | 36 | 37 | 38 | 39 | 40 | * ngspice commands 41 | **************** 42 | .include hpretl_tt03_temperature_sensor_golden.pex.xyce.spice 43 | 44 | **************** 45 | * Misc 46 | **************** 47 | .param fclk=10k 48 | .options method=gear maxord=2 49 | .options linsol klu 50 | .options device temp=30 51 | 52 | .tran 10u 30m 53 | 54 | .print tran format=csv file=tb_tempsense.xyce.csv v(st0) v(st1) v(st2) v(st3) v(st4) v(st5) v(st6) v(st7) i(visupply) 55 | 56 | 57 | 58 | **** end user architecture code 59 | **.ends 60 | .GLOBAL VDD 61 | .GLOBAL GND 62 | .end 63 | -------------------------------------------------------------------------------- /sim/simulation/sim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Copyright 2023 Harald Pretl 3 | # 4 | # Licensed under the Apache License, Version 2.0 (the "License"); 5 | # you may not use this file except in compliance with the License. 6 | # You may obtain a copy of the License at 7 | # 8 | # http://www.apache.org/licenses/LICENSE-2.0 9 | # 10 | # Unless required by applicable law or agreed to in writing, software 11 | # distributed under the License is distributed on an "AS IS" BASIS, 12 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | # See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | # 16 | # This is a simple shell-based simulation runner for ngspice using 17 | # GNU parallel. 18 | 19 | echo "[INFO] Simulation runner starting." 20 | 21 | TMP_NAME=tmp 22 | TMP_SUFFIX=spice 23 | LOG_SUFFIX=log 24 | RAW_SUFFIX=raw 25 | 26 | # Remove old files, to make sure that new ones are created 27 | rm -f ./*.${LOG_SUFFIX} 28 | rm -f ./*.${RAW_SUFFIX} 29 | rm -f ./$TMP_NAME*.$TMP_SUFFIX 30 | 31 | # Prepare parameter sweeps 32 | cp tb_tempsens.spice $TMP_NAME.$TMP_SUFFIX 33 | for temp in $(seq -w 0 5 100) 34 | do 35 | echo "[INFO] Creating simulation for temperature = $temp degC" 36 | sed "s/__TEMP__/$temp/g" $TMP_NAME.$TMP_SUFFIX > "${TMP_NAME}${temp}.${TMP_SUFFIX}" 37 | done 38 | rm $TMP_NAME.$TMP_SUFFIX 39 | 40 | # Run the simulations in parallel by fully loading the machine 41 | find . -name "${TMP_NAME}*.$TMP_SUFFIX" | parallel ngspice -b -o {}.${LOG_SUFFIX} -r {}.${RAW_SUFFIX} {} 42 | 43 | # Wait for all to finish 44 | echo "[DONE] All simulations finished!" 45 | -------------------------------------------------------------------------------- /src/bin2dec.v: -------------------------------------------------------------------------------- 1 | // Copyright 2023 Harald Pretl 2 | // 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at 6 | // 7 | // http://www.apache.org/licenses/LICENSE-2.0 8 | // 9 | // Unless required by applicable law or agreed to in writing, software 10 | // distributed under the License is distributed on an "AS IS" BASIS, 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | // See the License for the specific language governing permissions and 13 | // limitations under the License. 14 | 15 | `ifndef __BIN2DEC__ 16 | `define __BIN2DEC__ 17 | 18 | `default_nettype none 19 | 20 | module bin2dec ( 21 | input wire [6:0] i_bin, 22 | input wire i_tens, 23 | input wire i_ones, 24 | output wire [3:0] o_dec 25 | ); 26 | 27 | // we use this algorithm for BIN to BCD conversion (called "double-dabble"): 28 | // https://www.realdigital.org/doc/6dae6583570fd816d1d675b93578203d 29 | 30 | reg [11:0] bcd; 31 | integer i; 32 | 33 | assign o_dec = (i_tens == 1'b1) ? bcd[7:4] : 34 | (i_ones == 1'b1) ? bcd[3:0] : 35 | 4'd10; 36 | 37 | always @(*) begin 38 | bcd=0; 39 | for (i=0; i<7 ; i=i+1) begin 40 | if (bcd[03:00] >= 5) bcd[03:00] = bcd[03:00] + 3; 41 | if (bcd[07:04] >= 5) bcd[07:04] = bcd[07:04] + 3; 42 | if (bcd[11:08] >= 5) bcd[11:08] = bcd[11:08] + 3; 43 | bcd = {bcd[10:0],i_bin[6-i]}; 44 | end 45 | end 46 | 47 | endmodule // bin2dec 48 | `endif 49 | -------------------------------------------------------------------------------- /src/tempsense_paper.v: -------------------------------------------------------------------------------- 1 | module tempsense #( parameter NDAC=6, parameter NCAP=4 )( 2 | input wire [NDAC-1:0] i_dat, input wire i_en, input wire i_prchrg_n, 3 | output wire o_tmpdel); 4 | wire dac_vout; 5 | vdac #(.NBIT(NDAC)) dac (.i_dat(i_dat), .i_en(i_en), .vout(dac_vout)); 6 | wire tie0 = 1'b0, capn, del_n; 7 | wire [NCAP-1:0] dummy; 8 | sky130_fd_sc_hd__einvp_1 dcdc (.A(i_prchrg_n), .TE(dac_vout), .Z(capn)); 9 | sky130_fd_sc_hd__inv_1 inv1 (.A(capn), .Y(del_n)); 10 | sky130_fd_sc_hd__inv_1 inv2 (.A(del_n), .Y(o_tmpdel)); 11 | genvar i; generate 12 | for (i=0; i> $GITHUB_STEP_SUMMARY 61 | 62 | # print some routing stats 63 | - name: add summary 64 | run: ./tt/tt_tool.py --print-stats >> $GITHUB_STEP_SUMMARY 65 | 66 | # print some cell stats 67 | - name: cell usage summary 68 | run: ./tt/tt_tool.py --print-cell-category >> $GITHUB_STEP_SUMMARY 69 | 70 | - name: populate src cache 71 | uses: actions/cache@v3 72 | with: 73 | path: src 74 | key: ${{ runner.os }}-src-${{ github.run_id }} 75 | 76 | - name: populate runs cache 77 | uses: actions/cache@v3 78 | with: 79 | path: runs 80 | key: ${{ runner.os }}-runs-${{ github.run_id }} 81 | 82 | - name: populate PDK cache 83 | uses: actions/cache@v3 84 | with: 85 | path: ${{ env.PDK_ROOT }} 86 | key: ${{ runner.os }}-pdk-${{ github.run_id }} 87 | 88 | # create png 89 | - name: png 90 | run: ./tt/tt_tool.py --create-png 91 | 92 | - name: populate png cache 93 | uses: actions/cache@v3 94 | with: 95 | path: 'gds_render.png' 96 | key: ${{ runner.os }}-png-${{ github.run_id }} 97 | 98 | ############################################################## 99 | # GateLevel sim 100 | gatelevel: 101 | if: ${{ false }} 102 | needs: gds 103 | env: 104 | PDK_ROOT: /home/runner/pdk 105 | runs-on: ubuntu-latest 106 | steps: 107 | - name: checkout 108 | uses: actions/checkout@v3 109 | with: 110 | submodules: recursive 111 | 112 | - name: restore runs cache 113 | uses: actions/cache@v3 114 | with: 115 | path: runs 116 | key: ${{ runner.os }}-runs-${{ github.run_id }} 117 | 118 | - name: restore pdk cache for the primitives needed for GL verification 119 | uses: actions/cache@v3 120 | with: 121 | path: ${{ env.PDK_ROOT }} 122 | key: ${{ runner.os }}-pdk-${{ github.run_id }} 123 | 124 | # for debugging, show all the files 125 | - name: show files 126 | run: | 127 | pwd 128 | find . 129 | 130 | # install oss fpga tools for iVerilog 131 | - name: install oss-cad-suite 132 | uses: YosysHQ/setup-oss-cad-suite@v2 133 | with: 134 | python-override: true 135 | github-token: ${{ secrets.GITHUB_TOKEN }} 136 | - run: | 137 | yosys --version 138 | iverilog -V 139 | cocotb-config --libpython 140 | cocotb-config --python-bin 141 | 142 | - name: test 143 | run: | 144 | pwd 145 | rm runs/wokwi/results/final/verilog/gl/*.nl.v 146 | cp runs/wokwi/results/final/verilog/gl/*.v src/gate_level_netlist.v 147 | cd src 148 | make clean 149 | GATES=yes make 150 | # make will return success even if the test fails, so check for failure in the results.xml 151 | ! grep failure results.xml 152 | 153 | - name: upload vcd 154 | if: success() || failure() 155 | uses: actions/upload-artifact@v3 156 | with: 157 | name: gatelevel-test-vcd 158 | path: src/tb.vcd 159 | 160 | ############################################################## 161 | # Generate files for the 3D viewer 162 | 163 | viewer: 164 | needs: gds 165 | runs-on: ubuntu-latest 166 | steps: 167 | - name: checkout GDS2glTF repo 168 | uses: actions/checkout@v3 169 | with: 170 | repository: mbalestrini/GDS2glTF 171 | 172 | - name: setup python 173 | uses: actions/setup-python@v4 174 | with: 175 | python-version: '3.10' 176 | 177 | - name: restore runs cache 178 | uses: actions/cache@v3 179 | with: 180 | path: runs 181 | key: ${{ runner.os }}-runs-${{ github.run_id }} 182 | 183 | - name: gds2gltf 184 | run: | 185 | python -m pip install numpy gdspy triangle pygltflib 186 | cp runs/wokwi/results/final/gds/*.gds tinytapeout.gds 187 | python3 gds2gltf.py tinytapeout.gds 188 | 189 | - name: populate viewer cache 190 | uses: actions/cache@v3 191 | with: 192 | path: 'tinytapeout.gds.gltf' 193 | key: ${{ runner.os }}-viewer-${{ github.run_id }} 194 | 195 | ############################################################## 196 | # Downloadable results from OpenLane 197 | 198 | artifact: 199 | needs: 200 | - gds 201 | runs-on: ubuntu-latest 202 | steps: 203 | - name: restore src cache 204 | uses: actions/cache@v3 205 | with: 206 | path: src 207 | key: ${{ runner.os }}-src-${{ github.run_id }} 208 | 209 | - name: restore runs cache 210 | uses: actions/cache@v3 211 | with: 212 | path: runs 213 | key: ${{ runner.os }}-runs-${{ github.run_id }} 214 | 215 | - name: upload artifact 216 | uses: actions/upload-artifact@v3 217 | with: 218 | # path depends on the tag and the module name 219 | name: GDS 220 | path: | 221 | src/* 222 | runs/wokwi/results/final/* 223 | runs/wokwi/reports/metrics.csv 224 | runs/wokwi/reports/synthesis/1-synthesis.AREA 0.stat.rpt 225 | 226 | ############################################################## 227 | # Publish to pages to get a nicely formatted result 228 | 229 | pages: 230 | needs: 231 | - viewer 232 | environment: 233 | name: github-pages 234 | url: ${{ steps.deployment.outputs.page_url }} 235 | outputs: 236 | page_url: ${{ steps.deployment.outputs.page_url }} 237 | runs-on: ubuntu-latest 238 | steps: 239 | - name: restore png cache 240 | uses: actions/cache@v3 241 | with: 242 | path: 'gds_render.png' 243 | key: ${{ runner.os }}-png-${{ github.run_id }} 244 | - name: restore viewer cache 245 | uses: actions/cache@v3 246 | with: 247 | path: 'tinytapeout.gds.gltf' 248 | key: ${{ runner.os }}-viewer-${{ github.run_id }} 249 | - name: generate redirect to viewer 250 | run: | 251 | cat << EOF >> index.html 252 | 253 | 254 | 255 | 256 | 257 | 258 | Redirecting to GDS Viewer... 259 | 260 | 261 | 264 | 265 | 266 | EOF 267 | - name: Setup Pages 268 | uses: actions/configure-pages@v2 269 | - name: Upload artifact 270 | uses: actions/upload-pages-artifact@v1 271 | with: 272 | path: '.' 273 | - name: Deploy to GitHub Pages 274 | id: deployment 275 | uses: actions/deploy-pages@v1.2.2 276 | 277 | ############################################################## 278 | # Add the 3D and 2D preview to the page 279 | 280 | preview: 281 | needs: pages 282 | runs-on: ubuntu-latest 283 | steps: 284 | - name: add gds preview 285 | run: | 286 | PAGE_URL=${{ needs.pages.outputs.page_url }} 287 | PAGE_URL=$(echo "$PAGE_URL" | sed -e 's/\/$//') 288 | cat << EOF >> $GITHUB_STEP_SUMMARY 289 | # 3D Viewer 290 | [open 3D viewer](https://gds-viewer.tinytapeout.com/?model=$PAGE_URL/tinytapeout.gds.gltf) 291 | # 2D Preview 292 | ![png]($PAGE_URL/gds_render.png) 293 | EOF 294 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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