├── ExtIO_sddc ├── ExtIO_sddc.sln ├── ExtIO_sddc │ ├── ExtIO_sddc.cpp │ ├── ExtIO_sddc.def │ ├── ExtIO_sddc.h │ ├── ExtIO_sddc.vcproj │ ├── ExtIO_sddc.vcxproj │ ├── LC_ExtIO_Types.h │ ├── LICENSE.txt │ ├── README.txt │ ├── VersionNo.h │ ├── fftw3.h │ ├── i2c_r820t2.cpp │ ├── i2c_r820t2.h │ ├── i2c_si5351.cpp │ ├── i2c_si5351.h │ ├── rfddc.cpp │ └── rfddc.h └── library │ ├── inc │ ├── CyAPI.h │ ├── CyUSB30_def.h │ ├── UsbdStatus.h │ ├── VersionNo.h │ ├── cyioctl.h │ ├── usb100.h │ └── usb200.h │ └── lib │ └── librariesReadme.txt ├── FX3Firmware ├── BBRF103_GPIFII_SM │ ├── BBRF103_SM.cyfx │ ├── cyfxgpif2config.h │ └── projectfiles │ │ ├── gpif2model.xml │ │ ├── gpif2timingsimulation.xml │ │ └── gpif2view.xml ├── BBRF103_SRC │ ├── .cproject │ ├── .project │ ├── cyfx_gcc_startup.S │ ├── cyfxbulkdscr.c │ ├── cyfxgpif2config.h │ ├── cyfxtx.c │ ├── i2cmodule.c │ ├── i2cmodule.h │ ├── makefile │ ├── readme.txt │ ├── sdrx3.c │ └── sdrx3.h └── readme.txt ├── HARDWARE ├── BBRF103TopPCBview.pdf ├── BBRF103_scheme.pdf ├── BBRF103bottomPCBview.pdf └── BLOCKscheme01.pdf └── README.md /ExtIO_sddc/ExtIO_sddc.sln: -------------------------------------------------------------------------------- 1 |  2 | Microsoft Visual Studio Solution File, Format Version 12.00 3 | # Visual Studio 15 4 | VisualStudioVersion = 15.0.26228.9 5 | MinimumVisualStudioVersion = 10.0.40219.1 6 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ExtIO_sddc", "ExtIO_sddc\ExtIO_sddc.vcxproj", "{FA808BC2-46FB-4B99-9DF1-E335432930B9}" 7 | EndProject 8 | Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Solution Items", "Solution Items", "{B51E28C7-0931-486D-AC52-D7724B8E35DB}" 9 | EndProject 10 | Global 11 | GlobalSection(SolutionConfigurationPlatforms) = preSolution 12 | Debug|Win32 = Debug|Win32 13 | Release|Win32 = Release|Win32 14 | EndGlobalSection 15 | GlobalSection(ProjectConfigurationPlatforms) = postSolution 16 | {FA808BC2-46FB-4B99-9DF1-E335432930B9}.Debug|Win32.ActiveCfg = Debug|Win32 17 | {FA808BC2-46FB-4B99-9DF1-E335432930B9}.Debug|Win32.Build.0 = Debug|Win32 18 | {FA808BC2-46FB-4B99-9DF1-E335432930B9}.Release|Win32.ActiveCfg = Release|Win32 19 | {FA808BC2-46FB-4B99-9DF1-E335432930B9}.Release|Win32.Build.0 = Release|Win32 20 | EndGlobalSection 21 | GlobalSection(SolutionProperties) = preSolution 22 | HideSolutionNode = FALSE 23 | EndGlobalSection 24 | EndGlobal 25 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/ExtIO_sddc.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ik1xpv/BBRF103/443ce80aafdcd5b524f8caa6b1429b11dca53158/ExtIO_sddc/ExtIO_sddc/ExtIO_sddc.cpp -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/ExtIO_sddc.def: -------------------------------------------------------------------------------- 1 | 2 | LIBRARY ExtIO_sddc.DLL 3 | 4 | EXPORTS 5 | InitHW 6 | OpenHW 7 | StartHW 8 | ; StartHW64 9 | StopHW 10 | CloseHW 11 | SetHWLO 12 | GetStatus 13 | SetCallback 14 | 15 | GetHWLO 16 | GetHWSR 17 | 18 | ; GetTune 19 | ; GetFilters 20 | ; GetMode 21 | ; ModeChanged 22 | ; IFLimitsChanged 23 | ; TuneChanged 24 | 25 | ; ShowGUI 26 | ; HideGUI 27 | 28 | ; RawDataReady 29 | 30 | VersionInfo 31 | 32 | GetAttenuators 33 | GetActualAttIdx 34 | SetAttenuator 35 | 36 | ExtIoGetAGCs 37 | ExtIoGetActualAGCidx 38 | ExtIoSetAGC 39 | ExtIoShowMGC 40 | 41 | ExtIoGetMGCs 42 | ExtIoGetActualMgcIdx 43 | ExtIoSetMGC 44 | 45 | ; 64 Bit: 46 | 47 | SetHWLO64 48 | GetHWLO64 49 | ; GetTune 50 | ; IFLimitsChanged64 51 | ; TuneChanged64 52 | 53 | ; Samplerate / Bandwidth: 54 | ExtIoGetSrates 55 | ExtIoGetActualSrateIdx 56 | ExtIoSetSrate 57 | ExtIoGetBandwidth 58 | 59 | ; Settings 60 | ExtIoGetSetting 61 | ExtIoSetSetting 62 | 63 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/ExtIO_sddc.h: -------------------------------------------------------------------------------- 1 | #ifndef EXTIO_SDDC_H_ 2 | #define EXTIO_SDDC_H_ 3 | 4 | #ifdef EXTIO_EXPORTS 5 | #define EXTIO_API __declspec(dllexport) __stdcall 6 | #else 7 | #define EXTIO_API __declspec(dllimport) 8 | #endif 9 | 10 | #include // UINT8 11 | #include "LC_ExtIO_Types.h" 12 | 13 | #ifdef _DEBUG 14 | #define _MYDEBUG // Activate a debug console 15 | #endif 16 | 17 | #ifdef __cplusplus 18 | inline void null_func(char *format, ...) { } 19 | #define DbgEmpty null_func 20 | #else 21 | #define DbgEmpty { } 22 | #endif 23 | #ifdef _MYDEBUG 24 | /* Debug Trace Enabled */ 25 | #include 26 | #define DbgPrintf printf 27 | #else 28 | /* Debug Trace Disabled */ 29 | #define DbgPrintf DbgEmpty 30 | #endif 31 | 32 | #define CY_FX_RQT_I2C_WRITE (0xBA) 33 | #define CY_FX_RQT_I2C_READ (0xBB) 34 | #define CY_FX_RQT_GPIO_WRITE (0xBC) 35 | #define CY_FX_RQT_GPIO_PWM (0xBD) 36 | 37 | 38 | 39 | extern bool SendI2cbyte(UINT8 i2caddr, UINT8 regaddr, UINT8 data); 40 | extern bool SendI2cbytes(UINT8 i2caddr, UINT8 regaddr, UINT8 * pdata, UINT8 len); 41 | extern bool ReadI2cbytes(UINT8 i2caddr, UINT8 regaddr, UINT8 * pdata, UINT8 len); 42 | 43 | #define VERNUM "0.2" 44 | #define FRQSMP (64000000) // ADC sampling frequency 45 | #define FRQINIT (8000000) // default initial frequency if no valid settings 46 | #define R820T_FREQ (32000000) // R820T reference frequency 47 | 48 | 49 | extern "C" bool EXTIO_API InitHW(char *name, char *model, int& type); 50 | extern "C" int64_t EXTIO_API StartHW64(int64_t freq); 51 | extern "C" bool EXTIO_API OpenHW(void); 52 | extern "C" int EXTIO_API StartHW(long freq); 53 | extern "C" void EXTIO_API StopHW(void); 54 | extern "C" void EXTIO_API CloseHW(void); 55 | extern "C" int EXTIO_API SetHWLO(long LOfreq); 56 | extern "C" int64_t EXTIO_API SetHWLO64(int64_t LOfreq); 57 | extern "C" int EXTIO_API GetStatus(void); 58 | extern "C" void EXTIO_API SetCallback(pfnExtIOCallback funcptr); 59 | 60 | 61 | extern "C" long EXTIO_API GetHWLO(void); 62 | extern "C" int64_t EXTIO_API GetHWLO64(void); 63 | extern "C" long EXTIO_API GetHWSR(void); 64 | 65 | // extern "C" long EXTIO_API GetTune(void); 66 | // extern "C" void EXTIO_API GetFilters(int& loCut, int& hiCut, int& pitch); 67 | // extern "C" char EXTIO_API GetMode(void); 68 | // extern "C" void EXTIO_API ModeChanged(char mode); 69 | // extern "C" void EXTIO_API IFLimitsChanged(long low, long high); 70 | // extern "C" void EXTIO_API TuneChanged(long freq); 71 | 72 | // extern "C" void EXTIO_API TuneChanged64(int64_t freq); 73 | // extern "C" int64_t EXTIO_API GetTune64(void); 74 | // extern "C" void EXTIO_API IFLimitsChanged64(int64_t low, int64_t high); 75 | 76 | // extern "C" void EXTIO_API RawDataReady(long samprate, int *Ldata, int *Rdata, int numsamples); 77 | 78 | extern "C" void EXTIO_API VersionInfo(const char * progname, int ver_major, int ver_minor); 79 | 80 | extern "C" int EXTIO_API GetAttenuators(int idx, float * attenuation); // fill in attenuation 81 | // use positive attenuation levels if signal is amplified (LNA) 82 | // use negative attenuation levels if signal is attenuated 83 | // sort by attenuation: use idx 0 for highest attenuation / most damping 84 | // this functions is called with incrementing idx 85 | // - until this functions return != 0 for no more attenuator setting 86 | extern "C" int EXTIO_API GetActualAttIdx(void); // returns -1 on error 87 | extern "C" int EXTIO_API SetAttenuator(int idx); // returns != 0 on error 88 | 89 | extern "C" int EXTIO_API ExtIoGetAGCs(int agc_idx, char * text); 90 | extern "C" int EXTIO_API ExtIoGetActualAGCidx(void); 91 | extern "C" int EXTIO_API ExtIoSetAGC(int agc_idx); 92 | extern "C" int EXTIO_API ExtIoShowMGC(int agc_idx); 93 | 94 | extern "C" int EXTIO_API ExtIoGetMGCs(int mgc_idx, float * gain); 95 | extern "C" int EXTIO_API ExtIoGetActualMgcIdx(void); 96 | extern "C" int EXTIO_API ExtIoSetMGC(int mgc_idx); 97 | 98 | extern "C" int EXTIO_API ExtIoGetSrates(int idx, double * samplerate); // fill in possible samplerates 99 | extern "C" int EXTIO_API ExtIoGetActualSrateIdx(void); // returns -1 on error 100 | extern "C" int EXTIO_API ExtIoSetSrate(int idx); // returns != 0 on error 101 | extern "C" long EXTIO_API ExtIoGetBandwidth(int srate_idx); // returns != 0 on error 102 | 103 | extern "C" int EXTIO_API ExtIoGetSetting( int idx, char * description, char * value ); // will be called (at least) before exiting application 104 | extern "C" void EXTIO_API ExtIoSetSetting( int idx, const char * value ); // before calling InitHW() !!! 105 | 106 | 107 | int ExtIoGetIFgains(int mgc_idx, float * gain); 108 | #endif -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/ExtIO_sddc.vcproj: -------------------------------------------------------------------------------- 1 | 2 | 11 | 12 | 15 | 16 | 17 | 18 | 19 | 26 | 29 | 32 | 35 | 38 | 41 | 54 | 57 | 60 | 63 | 71 | 74 | 77 | 80 | 83 | 86 | 89 | 92 | 93 | 101 | 104 | 107 | 110 | 113 | 116 | 129 | 132 | 135 | 138 | 149 | 152 | 155 | 158 | 161 | 164 | 167 | 170 | 171 | 172 | 173 | 174 | 175 | 180 | 183 | 184 | 187 | 188 | 189 | 194 | 197 | 198 | 201 | 202 | 203 | 208 | 209 | 210 | 211 | 212 | 213 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/ExtIO_sddc.vcxproj: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | Debug 6 | Win32 7 | 8 | 9 | Debug 10 | x64 11 | 12 | 13 | Release 14 | Win32 15 | 16 | 17 | Release 18 | x64 19 | 20 | 21 | 22 | {FA808BC2-46FB-4B99-9DF1-E335432930B9} 23 | ExtIO_sddc 24 | Win32Proj 25 | 10.0.14393.0 26 | ExtIO_sddc 27 | 28 | 29 | 30 | DynamicLibrary 31 | v141 32 | NotSet 33 | false 34 | 35 | 36 | DynamicLibrary 37 | v141 38 | NotSet 39 | false 40 | 41 | 42 | DynamicLibrary 43 | v141 44 | NotSet 45 | 46 | 47 | DynamicLibrary 48 | v141 49 | NotSet 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | <_ProjectFileVersion>12.0.21005.1 69 | 70 | 71 | $(SolutionDir)$(Configuration)\ 72 | $(Configuration)\ 73 | false 74 | ..\library\lib\x86;$(LibraryPath) 75 | ..\library\inc\;$(IncludePath) 76 | 77 | 78 | false 79 | ..\library\lib\x64;$(LibraryPath) 80 | 81 | 82 | $(SolutionDir)$(Configuration)\ 83 | $(Configuration)\ 84 | false 85 | ..\library\lib\x86;$(LibraryPath) 86 | ..\library\inc\;$(IncludePath) 87 | 88 | 89 | false 90 | ..\library\lib\x64;$(LibraryPath) 91 | 92 | 93 | 94 | Disabled 95 | WIN32;_DEBUG;_CRT_SECURE_NO_WARNINGS;_WINDOWS;_USRDLL;EXTIO_EXPORTS;%(PreprocessorDefinitions) 96 | true 97 | false 98 | Sync 99 | EnableFastChecks 100 | MultiThreadedDebugDLL 101 | 102 | Level3 103 | ProgramDatabase 104 | 105 | 106 | ExtIO_sddc.def 107 | true 108 | Windows 109 | MachineX86 110 | CyAPI.lib;libfftw3f-3.lib;SetupAPI.lib;legacy_stdio_definitions.lib;%(AdditionalDependencies) 111 | LIBCMT 112 | false 113 | 1.0 114 | 115 | 116 | 117 | 118 | Disabled 119 | WIN32;_DEBUG;_CRT_SECURE_NO_WARNINGS;_WINDOWS;_USRDLL;EXTIO_EXPORTS;%(PreprocessorDefinitions) 120 | true 121 | false 122 | Sync 123 | EnableFastChecks 124 | MultiThreadedDebugDLL 125 | 126 | 127 | Level3 128 | ProgramDatabase 129 | 130 | 131 | ExtIO_sddc.def 132 | true 133 | Windows 134 | libfftw3f-3.lib;SetupAPI.lib;legacy_stdio_definitions.lib;%(AdditionalDependencies) 135 | LIBCMT 136 | false 137 | 1.0 138 | 139 | 140 | 141 | 142 | MaxSpeed 143 | true 144 | WIN32;NDEBUG;_WINDOWS;_USRDLL;EXTIO_EXPORTS;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) 145 | true 146 | 147 | MultiThreaded 148 | true 149 | 150 | Level3 151 | ProgramDatabase 152 | Neither 153 | Default 154 | 155 | 156 | 1.0 157 | ExtIO_sddc.def 158 | false 159 | Windows 160 | false 161 | true 162 | MachineX86 163 | CyAPI.lib;libfftw3f-3.lib;SetupAPI.lib;legacy_stdio_definitions.lib;%(AdditionalDependencies) 164 | 165 | 166 | 167 | 168 | MaxSpeed 169 | true 170 | WIN32;NDEBUG;_WINDOWS;_USRDLL;EXTIO_EXPORTS;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions) 171 | true 172 | 173 | 174 | MultiThreadedDLL 175 | true 176 | 177 | 178 | Level3 179 | ProgramDatabase 180 | 181 | 182 | 1.0 183 | ExtIO_sddc.def 184 | false 185 | Windows 186 | false 187 | true 188 | libfftw3f-3.lib;SetupAPI.lib;legacy_stdio_definitions.lib;%(AdditionalDependencies) 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/LC_ExtIO_Types.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ik1xpv/BBRF103/443ce80aafdcd5b524f8caa6b1429b11dca53158/ExtIO_sddc/ExtIO_sddc/LC_ExtIO_Types.h -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/LICENSE.txt: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2017 Oscar Steila 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE.The MIT License (MIT) 22 | The MIT License (MIT) 23 | 24 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/README.txt: -------------------------------------------------------------------------------- 1 | # ExtIO_sddc 2 | ExtIO.dll Software Digital Down Converter for BBRF103 by Oscar Steila ik1xpv 3 | 4 | links: 5 | http://www.steila.com/blog/ 6 | 7 | http://www.hdsdr.de/ -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/VersionNo.h: -------------------------------------------------------------------------------- 1 | /* 2 | ## Cypress CyAPI C++ library version number header file (VersionNo.h) 3 | ## ======================================================= 4 | ## 5 | ## Copyright Cypress Semiconductor Corporation, 2009-2012, 6 | ## All Rights Reserved 7 | ## UNPUBLISHED, LICENSED SOFTWARE. 8 | ## 9 | ## CONFIDENTIAL AND PROPRIETARY INFORMATION 10 | ## WHICH IS THE PROPERTY OF CYPRESS. 11 | ## 12 | ## Use of this file is governed 13 | ## by the license agreement included in the file 14 | ## 15 | ## /license/license.rtf 16 | ## 17 | ## where is the Cypress software 18 | ## install root directory path. 19 | ## 20 | ## ======================================================= 21 | */ 22 | #define FILEVER 1,2,1,0 23 | #define PRODUCTVER 1,2,1,0 24 | #define STRFILEVER "1, 2, 1, 0" 25 | #define STRPRODUCTVER "1, 2, 1, 0" 26 | #define STRFILEVER_ASSENBLY "1.2.1.0" 27 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/fftw3.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2003, 2007-14 Matteo Frigo 3 | * Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology 4 | * 5 | * The following statement of license applies *only* to this header file, 6 | * and *not* to the other files distributed with FFTW or derived therefrom: 7 | * 8 | * Redistribution and use in source and binary forms, with or without 9 | * modification, are permitted provided that the following conditions 10 | * are met: 11 | * 12 | * 1. Redistributions of source code must retain the above copyright 13 | * notice, this list of conditions and the following disclaimer. 14 | * 15 | * 2. Redistributions in binary form must reproduce the above copyright 16 | * notice, this list of conditions and the following disclaimer in the 17 | * documentation and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 20 | * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 25 | * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | */ 31 | 32 | /***************************** NOTE TO USERS ********************************* 33 | * 34 | * THIS IS A HEADER FILE, NOT A MANUAL 35 | * 36 | * If you want to know how to use FFTW, please read the manual, 37 | * online at http://www.fftw.org/doc/ and also included with FFTW. 38 | * For a quick start, see the manual's tutorial section. 39 | * 40 | * (Reading header files to learn how to use a library is a habit 41 | * stemming from code lacking a proper manual. Arguably, it's a 42 | * *bad* habit in most cases, because header files can contain 43 | * interfaces that are not part of the public, stable API.) 44 | * 45 | ****************************************************************************/ 46 | 47 | #ifndef FFTW3_H 48 | #define FFTW3_H 49 | 50 | #include 51 | 52 | #ifdef __cplusplus 53 | extern "C" 54 | { 55 | #endif /* __cplusplus */ 56 | 57 | /* If is included, use the C99 complex type. Otherwise 58 | define a type bit-compatible with C99 complex */ 59 | #if !defined(FFTW_NO_Complex) && defined(_Complex_I) && defined(complex) && defined(I) 60 | # define FFTW_DEFINE_COMPLEX(R, C) typedef R _Complex C 61 | #else 62 | # define FFTW_DEFINE_COMPLEX(R, C) typedef R C[2] 63 | #endif 64 | 65 | #define FFTW_CONCAT(prefix, name) prefix ## name 66 | #define FFTW_MANGLE_DOUBLE(name) FFTW_CONCAT(fftw_, name) 67 | #define FFTW_MANGLE_FLOAT(name) FFTW_CONCAT(fftwf_, name) 68 | #define FFTW_MANGLE_LONG_DOUBLE(name) FFTW_CONCAT(fftwl_, name) 69 | #define FFTW_MANGLE_QUAD(name) FFTW_CONCAT(fftwq_, name) 70 | 71 | /* IMPORTANT: for Windows compilers, you should add a line 72 | */ 73 | #define FFTW_DLL 74 | /* 75 | here and in kernel/ifftw.h if you are compiling/using FFTW as a 76 | DLL, in order to do the proper importing/exporting, or 77 | alternatively compile with -DFFTW_DLL or the equivalent 78 | command-line flag. This is not necessary under MinGW/Cygwin, where 79 | libtool does the imports/exports automatically. */ 80 | #if defined(FFTW_DLL) && (defined(_WIN32) || defined(__WIN32__)) 81 | /* annoying Windows syntax for shared-library declarations */ 82 | # if defined(COMPILING_FFTW) /* defined in api.h when compiling FFTW */ 83 | # define FFTW_EXTERN extern __declspec(dllexport) 84 | # else /* user is calling FFTW; import symbol */ 85 | # define FFTW_EXTERN extern __declspec(dllimport) 86 | # endif 87 | #else 88 | # define FFTW_EXTERN extern 89 | #endif 90 | 91 | enum fftw_r2r_kind_do_not_use_me { 92 | FFTW_R2HC=0, FFTW_HC2R=1, FFTW_DHT=2, 93 | FFTW_REDFT00=3, FFTW_REDFT01=4, FFTW_REDFT10=5, FFTW_REDFT11=6, 94 | FFTW_RODFT00=7, FFTW_RODFT01=8, FFTW_RODFT10=9, FFTW_RODFT11=10 95 | }; 96 | 97 | struct fftw_iodim_do_not_use_me { 98 | int n; /* dimension size */ 99 | int is; /* input stride */ 100 | int os; /* output stride */ 101 | }; 102 | 103 | #include /* for ptrdiff_t */ 104 | struct fftw_iodim64_do_not_use_me { 105 | ptrdiff_t n; /* dimension size */ 106 | ptrdiff_t is; /* input stride */ 107 | ptrdiff_t os; /* output stride */ 108 | }; 109 | 110 | typedef void (*fftw_write_char_func_do_not_use_me)(char c, void *); 111 | typedef int (*fftw_read_char_func_do_not_use_me)(void *); 112 | 113 | /* 114 | huge second-order macro that defines prototypes for all API 115 | functions. We expand this macro for each supported precision 116 | 117 | X: name-mangling macro 118 | R: real data type 119 | C: complex data type 120 | */ 121 | 122 | #define FFTW_DEFINE_API(X, R, C) \ 123 | \ 124 | FFTW_DEFINE_COMPLEX(R, C); \ 125 | \ 126 | typedef struct X(plan_s) *X(plan); \ 127 | \ 128 | typedef struct fftw_iodim_do_not_use_me X(iodim); \ 129 | typedef struct fftw_iodim64_do_not_use_me X(iodim64); \ 130 | \ 131 | typedef enum fftw_r2r_kind_do_not_use_me X(r2r_kind); \ 132 | \ 133 | typedef fftw_write_char_func_do_not_use_me X(write_char_func); \ 134 | typedef fftw_read_char_func_do_not_use_me X(read_char_func); \ 135 | \ 136 | FFTW_EXTERN void X(execute)(const X(plan) p); \ 137 | \ 138 | FFTW_EXTERN X(plan) X(plan_dft)(int rank, const int *n, \ 139 | C *in, C *out, int sign, unsigned flags); \ 140 | \ 141 | FFTW_EXTERN X(plan) X(plan_dft_1d)(int n, C *in, C *out, int sign, \ 142 | unsigned flags); \ 143 | FFTW_EXTERN X(plan) X(plan_dft_2d)(int n0, int n1, \ 144 | C *in, C *out, int sign, unsigned flags); \ 145 | FFTW_EXTERN X(plan) X(plan_dft_3d)(int n0, int n1, int n2, \ 146 | C *in, C *out, int sign, unsigned flags); \ 147 | \ 148 | FFTW_EXTERN X(plan) X(plan_many_dft)(int rank, const int *n, \ 149 | int howmany, \ 150 | C *in, const int *inembed, \ 151 | int istride, int idist, \ 152 | C *out, const int *onembed, \ 153 | int ostride, int odist, \ 154 | int sign, unsigned flags); \ 155 | \ 156 | FFTW_EXTERN X(plan) X(plan_guru_dft)(int rank, const X(iodim) *dims, \ 157 | int howmany_rank, \ 158 | const X(iodim) *howmany_dims, \ 159 | C *in, C *out, \ 160 | int sign, unsigned flags); \ 161 | FFTW_EXTERN X(plan) X(plan_guru_split_dft)(int rank, const X(iodim) *dims, \ 162 | int howmany_rank, \ 163 | const X(iodim) *howmany_dims, \ 164 | R *ri, R *ii, R *ro, R *io, \ 165 | unsigned flags); \ 166 | \ 167 | FFTW_EXTERN X(plan) X(plan_guru64_dft)(int rank, \ 168 | const X(iodim64) *dims, \ 169 | int howmany_rank, \ 170 | const X(iodim64) *howmany_dims, \ 171 | C *in, C *out, \ 172 | int sign, unsigned flags); \ 173 | FFTW_EXTERN X(plan) X(plan_guru64_split_dft)(int rank, \ 174 | const X(iodim64) *dims, \ 175 | int howmany_rank, \ 176 | const X(iodim64) *howmany_dims, \ 177 | R *ri, R *ii, R *ro, R *io, \ 178 | unsigned flags); \ 179 | \ 180 | FFTW_EXTERN void X(execute_dft)(const X(plan) p, C *in, C *out); \ 181 | FFTW_EXTERN void X(execute_split_dft)(const X(plan) p, R *ri, R *ii, \ 182 | R *ro, R *io); \ 183 | \ 184 | FFTW_EXTERN X(plan) X(plan_many_dft_r2c)(int rank, const int *n, \ 185 | int howmany, \ 186 | R *in, const int *inembed, \ 187 | int istride, int idist, \ 188 | C *out, const int *onembed, \ 189 | int ostride, int odist, \ 190 | unsigned flags); \ 191 | \ 192 | FFTW_EXTERN X(plan) X(plan_dft_r2c)(int rank, const int *n, \ 193 | R *in, C *out, unsigned flags); \ 194 | \ 195 | FFTW_EXTERN X(plan) X(plan_dft_r2c_1d)(int n,R *in,C *out,unsigned flags); \ 196 | FFTW_EXTERN X(plan) X(plan_dft_r2c_2d)(int n0, int n1, \ 197 | R *in, C *out, unsigned flags); \ 198 | FFTW_EXTERN X(plan) X(plan_dft_r2c_3d)(int n0, int n1, \ 199 | int n2, \ 200 | R *in, C *out, unsigned flags); \ 201 | \ 202 | \ 203 | FFTW_EXTERN X(plan) X(plan_many_dft_c2r)(int rank, const int *n, \ 204 | int howmany, \ 205 | C *in, const int *inembed, \ 206 | int istride, int idist, \ 207 | R *out, const int *onembed, \ 208 | int ostride, int odist, \ 209 | unsigned flags); \ 210 | \ 211 | FFTW_EXTERN X(plan) X(plan_dft_c2r)(int rank, const int *n, \ 212 | C *in, R *out, unsigned flags); \ 213 | \ 214 | FFTW_EXTERN X(plan) X(plan_dft_c2r_1d)(int n,C *in,R *out,unsigned flags); \ 215 | FFTW_EXTERN X(plan) X(plan_dft_c2r_2d)(int n0, int n1, \ 216 | C *in, R *out, unsigned flags); \ 217 | FFTW_EXTERN X(plan) X(plan_dft_c2r_3d)(int n0, int n1, \ 218 | int n2, \ 219 | C *in, R *out, unsigned flags); \ 220 | \ 221 | FFTW_EXTERN X(plan) X(plan_guru_dft_r2c)(int rank, const X(iodim) *dims, \ 222 | int howmany_rank, \ 223 | const X(iodim) *howmany_dims, \ 224 | R *in, C *out, \ 225 | unsigned flags); \ 226 | FFTW_EXTERN X(plan) X(plan_guru_dft_c2r)(int rank, const X(iodim) *dims, \ 227 | int howmany_rank, \ 228 | const X(iodim) *howmany_dims, \ 229 | C *in, R *out, \ 230 | unsigned flags); \ 231 | \ 232 | FFTW_EXTERN X(plan) X(plan_guru_split_dft_r2c)( \ 233 | int rank, const X(iodim) *dims, \ 234 | int howmany_rank, \ 235 | const X(iodim) *howmany_dims, \ 236 | R *in, R *ro, R *io, \ 237 | unsigned flags); \ 238 | FFTW_EXTERN X(plan) X(plan_guru_split_dft_c2r)( \ 239 | int rank, const X(iodim) *dims, \ 240 | int howmany_rank, \ 241 | const X(iodim) *howmany_dims, \ 242 | R *ri, R *ii, R *out, \ 243 | unsigned flags); \ 244 | \ 245 | FFTW_EXTERN X(plan) X(plan_guru64_dft_r2c)(int rank, \ 246 | const X(iodim64) *dims, \ 247 | int howmany_rank, \ 248 | const X(iodim64) *howmany_dims, \ 249 | R *in, C *out, \ 250 | unsigned flags); \ 251 | FFTW_EXTERN X(plan) X(plan_guru64_dft_c2r)(int rank, \ 252 | const X(iodim64) *dims, \ 253 | int howmany_rank, \ 254 | const X(iodim64) *howmany_dims, \ 255 | C *in, R *out, \ 256 | unsigned flags); \ 257 | \ 258 | FFTW_EXTERN X(plan) X(plan_guru64_split_dft_r2c)( \ 259 | int rank, const X(iodim64) *dims, \ 260 | int howmany_rank, \ 261 | const X(iodim64) *howmany_dims, \ 262 | R *in, R *ro, R *io, \ 263 | unsigned flags); \ 264 | FFTW_EXTERN X(plan) X(plan_guru64_split_dft_c2r)( \ 265 | int rank, const X(iodim64) *dims, \ 266 | int howmany_rank, \ 267 | const X(iodim64) *howmany_dims, \ 268 | R *ri, R *ii, R *out, \ 269 | unsigned flags); \ 270 | \ 271 | FFTW_EXTERN void X(execute_dft_r2c)(const X(plan) p, R *in, C *out); \ 272 | FFTW_EXTERN void X(execute_dft_c2r)(const X(plan) p, C *in, R *out); \ 273 | \ 274 | FFTW_EXTERN void X(execute_split_dft_r2c)(const X(plan) p, \ 275 | R *in, R *ro, R *io); \ 276 | FFTW_EXTERN void X(execute_split_dft_c2r)(const X(plan) p, \ 277 | R *ri, R *ii, R *out); \ 278 | \ 279 | FFTW_EXTERN X(plan) X(plan_many_r2r)(int rank, const int *n, \ 280 | int howmany, \ 281 | R *in, const int *inembed, \ 282 | int istride, int idist, \ 283 | R *out, const int *onembed, \ 284 | int ostride, int odist, \ 285 | const X(r2r_kind) *kind, unsigned flags); \ 286 | \ 287 | FFTW_EXTERN X(plan) X(plan_r2r)(int rank, const int *n, R *in, R *out, \ 288 | const X(r2r_kind) *kind, unsigned flags); \ 289 | \ 290 | FFTW_EXTERN X(plan) X(plan_r2r_1d)(int n, R *in, R *out, \ 291 | X(r2r_kind) kind, unsigned flags); \ 292 | FFTW_EXTERN X(plan) X(plan_r2r_2d)(int n0, int n1, R *in, R *out, \ 293 | X(r2r_kind) kind0, X(r2r_kind) kind1, \ 294 | unsigned flags); \ 295 | FFTW_EXTERN X(plan) X(plan_r2r_3d)(int n0, int n1, int n2, \ 296 | R *in, R *out, X(r2r_kind) kind0, \ 297 | X(r2r_kind) kind1, X(r2r_kind) kind2, \ 298 | unsigned flags); \ 299 | \ 300 | FFTW_EXTERN X(plan) X(plan_guru_r2r)(int rank, const X(iodim) *dims, \ 301 | int howmany_rank, \ 302 | const X(iodim) *howmany_dims, \ 303 | R *in, R *out, \ 304 | const X(r2r_kind) *kind, unsigned flags); \ 305 | \ 306 | FFTW_EXTERN X(plan) X(plan_guru64_r2r)(int rank, const X(iodim64) *dims, \ 307 | int howmany_rank, \ 308 | const X(iodim64) *howmany_dims, \ 309 | R *in, R *out, \ 310 | const X(r2r_kind) *kind, unsigned flags); \ 311 | \ 312 | FFTW_EXTERN void X(execute_r2r)(const X(plan) p, R *in, R *out); \ 313 | \ 314 | FFTW_EXTERN void X(destroy_plan)(X(plan) p); \ 315 | FFTW_EXTERN void X(forget_wisdom)(void); \ 316 | FFTW_EXTERN void X(cleanup)(void); \ 317 | \ 318 | FFTW_EXTERN void X(set_timelimit)(double t); \ 319 | \ 320 | FFTW_EXTERN void X(plan_with_nthreads)(int nthreads); \ 321 | FFTW_EXTERN int X(init_threads)(void); \ 322 | FFTW_EXTERN void X(cleanup_threads)(void); \ 323 | FFTW_EXTERN void X(make_planner_thread_safe)(void); \ 324 | \ 325 | FFTW_EXTERN int X(export_wisdom_to_filename)(const char *filename); \ 326 | FFTW_EXTERN void X(export_wisdom_to_file)(FILE *output_file); \ 327 | FFTW_EXTERN char *X(export_wisdom_to_string)(void); \ 328 | FFTW_EXTERN void X(export_wisdom)(X(write_char_func) write_char, \ 329 | void *data); \ 330 | FFTW_EXTERN int X(import_system_wisdom)(void); \ 331 | FFTW_EXTERN int X(import_wisdom_from_filename)(const char *filename); \ 332 | FFTW_EXTERN int X(import_wisdom_from_file)(FILE *input_file); \ 333 | FFTW_EXTERN int X(import_wisdom_from_string)(const char *input_string); \ 334 | FFTW_EXTERN int X(import_wisdom)(X(read_char_func) read_char, void *data); \ 335 | \ 336 | FFTW_EXTERN void X(fprint_plan)(const X(plan) p, FILE *output_file); \ 337 | FFTW_EXTERN void X(print_plan)(const X(plan) p); \ 338 | FFTW_EXTERN char *X(sprint_plan)(const X(plan) p); \ 339 | \ 340 | FFTW_EXTERN void *X(malloc)(size_t n); \ 341 | FFTW_EXTERN R *X(alloc_real)(size_t n); \ 342 | FFTW_EXTERN C *X(alloc_complex)(size_t n); \ 343 | FFTW_EXTERN void X(free)(void *p); \ 344 | \ 345 | FFTW_EXTERN void X(flops)(const X(plan) p, \ 346 | double *add, double *mul, double *fmas); \ 347 | FFTW_EXTERN double X(estimate_cost)(const X(plan) p); \ 348 | FFTW_EXTERN double X(cost)(const X(plan) p); \ 349 | \ 350 | FFTW_EXTERN int X(alignment_of)(R *p); \ 351 | FFTW_EXTERN const char X(version)[]; \ 352 | FFTW_EXTERN const char X(cc)[]; \ 353 | FFTW_EXTERN const char X(codelet_optim)[]; 354 | 355 | 356 | /* end of FFTW_DEFINE_API macro */ 357 | 358 | FFTW_DEFINE_API(FFTW_MANGLE_DOUBLE, double, fftw_complex) 359 | FFTW_DEFINE_API(FFTW_MANGLE_FLOAT, float, fftwf_complex) 360 | FFTW_DEFINE_API(FFTW_MANGLE_LONG_DOUBLE, long double, fftwl_complex) 361 | 362 | /* __float128 (quad precision) is a gcc extension on i386, x86_64, and ia64 363 | for gcc >= 4.6 (compiled in FFTW with --enable-quad-precision) */ 364 | #if (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)) \ 365 | && !(defined(__ICC) || defined(__INTEL_COMPILER) || defined(__CUDACC__) || defined(__PGI)) \ 366 | && (defined(__i386__) || defined(__x86_64__) || defined(__ia64__)) 367 | # if !defined(FFTW_NO_Complex) && defined(_Complex_I) && defined(complex) && defined(I) 368 | /* note: __float128 is a typedef, which is not supported with the _Complex 369 | keyword in gcc, so instead we use this ugly __attribute__ version. 370 | However, we can't simply pass the __attribute__ version to 371 | FFTW_DEFINE_API because the __attribute__ confuses gcc in pointer 372 | types. Hence redefining FFTW_DEFINE_COMPLEX. Ugh. */ 373 | # undef FFTW_DEFINE_COMPLEX 374 | # define FFTW_DEFINE_COMPLEX(R, C) typedef _Complex float __attribute__((mode(TC))) C 375 | # endif 376 | FFTW_DEFINE_API(FFTW_MANGLE_QUAD, __float128, fftwq_complex) 377 | #endif 378 | 379 | #define FFTW_FORWARD (-1) 380 | #define FFTW_BACKWARD (+1) 381 | 382 | #define FFTW_NO_TIMELIMIT (-1.0) 383 | 384 | /* documented flags */ 385 | #define FFTW_MEASURE (0U) 386 | #define FFTW_DESTROY_INPUT (1U << 0) 387 | #define FFTW_UNALIGNED (1U << 1) 388 | #define FFTW_CONSERVE_MEMORY (1U << 2) 389 | #define FFTW_EXHAUSTIVE (1U << 3) /* NO_EXHAUSTIVE is default */ 390 | #define FFTW_PRESERVE_INPUT (1U << 4) /* cancels FFTW_DESTROY_INPUT */ 391 | #define FFTW_PATIENT (1U << 5) /* IMPATIENT is default */ 392 | #define FFTW_ESTIMATE (1U << 6) 393 | #define FFTW_WISDOM_ONLY (1U << 21) 394 | 395 | /* undocumented beyond-guru flags */ 396 | #define FFTW_ESTIMATE_PATIENT (1U << 7) 397 | #define FFTW_BELIEVE_PCOST (1U << 8) 398 | #define FFTW_NO_DFT_R2HC (1U << 9) 399 | #define FFTW_NO_NONTHREADED (1U << 10) 400 | #define FFTW_NO_BUFFERING (1U << 11) 401 | #define FFTW_NO_INDIRECT_OP (1U << 12) 402 | #define FFTW_ALLOW_LARGE_GENERIC (1U << 13) /* NO_LARGE_GENERIC is default */ 403 | #define FFTW_NO_RANK_SPLITS (1U << 14) 404 | #define FFTW_NO_VRANK_SPLITS (1U << 15) 405 | #define FFTW_NO_VRECURSE (1U << 16) 406 | #define FFTW_NO_SIMD (1U << 17) 407 | #define FFTW_NO_SLOW (1U << 18) 408 | #define FFTW_NO_FIXED_RADIX_LARGE_N (1U << 19) 409 | #define FFTW_ALLOW_PRUNING (1U << 20) 410 | 411 | #ifdef __cplusplus 412 | } /* extern "C" */ 413 | #endif /* __cplusplus */ 414 | 415 | #endif /* FFTW3_H */ 416 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/i2c_r820t2.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * I2C_R820T2.c - driver 3 | */ 4 | 5 | #include "i2c_r820t2.h" 6 | 7 | /* 8 | * I2C 9 | */ 10 | 11 | #define FLAG_TIMEOUT ((uint32_t)0x1000) 12 | #define LONG_TIMEOUT ((uint32_t)(10 * FLAG_TIMEOUT)) 13 | 14 | /* 15 | * Freq calcs 16 | */ 17 | 18 | 19 | #define CALIBRATION_LO 88000000 20 | 21 | /* registers */ 22 | #define R820T2_NUM_REGS 0x20 23 | #define R820T2_WRITE_START 5 24 | /* 25 | static const int r820t2_lna_gain_steps[] = { 26 | 0, 9, 13, 40, 38, 13, 31, 22, 27 | 26, 31, 26, 14, 19, 5, 35, 13 28 | }; 29 | */ 30 | 31 | const int r820t2_lna_gain_steps[16] = { 32 | 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 33 | }; 34 | 35 | const int r820t2_mixer_gain_steps[16] = { 36 | 0, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 37 | }; 38 | 39 | const int r820t2_vga_gain_steps[16] = { 40 | 0, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 41 | }; 42 | 43 | 44 | /* initial freq @ 128MHz -> ~5MHz IF due to xtal mismatch */ 45 | static const uint8_t r82xx_init_array[R820T2_NUM_REGS] = 46 | { 47 | 0x00, 0x00, 0x00, 0x00, 0x00, /* 00 to 04 */ 48 | /* 05 */ 0x90, // 0x90 LNA manual gain mode, init to 0 49 | /* 06 */ 0x80, 50 | /* 07 */ 0x60, 51 | /* 08 */ 0x80, // Image Gain Adjustment 52 | /* 09 */ 0x40, // 40 Image Phase Adjustment 53 | /* 0A */ 0xA0, // A8 Channel filter [0..3]: 0 = widest, f = narrowest - Optimal. Don't touch! 54 | /* 0B */ 0x6F, // 0F High pass filter - Optimal. Don't touch! 55 | /* 0C */ 0x40, // 0x480x40 VGA control by code, init at 0 56 | /* 0D */ 0x63, // LNA AGC settings: [0..3]: Lower threshold; [4..7]: High threshold 57 | /* 0E */ 0x75, 58 | /* 0F */ 0xF8, // F8 Filter Widest, LDO_5V OFF, clk out OFF, 59 | /* 10 */ 0x7C, 60 | /* 11 */ 0x83, 61 | /* 12 */ 0x80, 62 | /* 13 */ 0x00, 63 | /* 14 */ 0x0F, 64 | /* 15 */ 0x00, 65 | /* 16 */ 0xC0, 66 | /* 17 */ 0x30, 67 | /* 18 */ 0x48, 68 | /* 19 */ 0xCC, 69 | /* 1A */ 0x62, //0x60 70 | /* 1B */ 0x00, 71 | /* 1C */ 0x54, 72 | /* 1D */ 0xAE, 73 | /* 1E */ 0x0A, 74 | /* 1F */ 0xC0 75 | }; 76 | 77 | 78 | 79 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 80 | 81 | /* 82 | * Tuner frequency ranges 83 | * Kanged & modified from airspy firmware to include freq for scanning table 84 | * "Copyright (C) 2013 Mauro Carvalho Chehab" 85 | * https://stuff.mit.edu/afs/sipb/contrib/linux/drivers/media/tuners/r820t.c 86 | */ 87 | struct r820t_freq_range 88 | { 89 | uint16_t freq; 90 | uint8_t open_d; 91 | uint8_t rf_mux_ploy; 92 | uint8_t tf_c; 93 | }; 94 | 95 | /* Tuner frequency ranges 96 | "Copyright (C) 2013 Mauro Carvalho Chehab" 97 | https://stuff.mit.edu/afs/sipb/contrib/linux/drivers/media/tuners/r820t.c 98 | part of freq_ranges() 99 | */ 100 | const struct r820t_freq_range freq_ranges[] = 101 | { 102 | { 103 | /* 0 MHz */ 0, 104 | /* .open_d = */ 0x08, /* low */ 105 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 106 | /* .tf_c = */ 0xdf, /* R27[7:0] band2,band0 */ 107 | }, { 108 | /* 50 MHz */ 50, 109 | /* .open_d = */ 0x08, /* low */ 110 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 111 | /* .tf_c = */ 0xbe, /* R27[7:0] band4,band1 */ 112 | }, { 113 | /* 55 MHz */ 55, 114 | /* .open_d = */ 0x08, /* low */ 115 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 116 | /* .tf_c = */ 0x8b, /* R27[7:0] band7,band4 */ 117 | }, { 118 | /* 60 MHz */ 60, 119 | /* .open_d = */ 0x08, /* low */ 120 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 121 | /* .tf_c = */ 0x7b, /* R27[7:0] band8,band4 */ 122 | }, { 123 | /* 65 MHz */ 65, 124 | /* .open_d = */ 0x08, /* low */ 125 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 126 | /* .tf_c = */ 0x69, /* R27[7:0] band9,band6 */ 127 | }, { 128 | /* 70 MHz */ 70, 129 | /* .open_d = */ 0x08, /* low */ 130 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 131 | /* .tf_c = */ 0x58, /* R27[7:0] band10,band7 */ 132 | }, { 133 | /* 75 MHz */ 75, 134 | /* .open_d = */ 0x00, /* high */ 135 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 136 | /* .tf_c = */ 0x44, /* R27[7:0] band11,band11 */ 137 | }, { 138 | /* 80 MHz */ 80, 139 | /* .open_d = */ 0x00, /* high */ 140 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 141 | /* .tf_c = */ 0x44, /* R27[7:0] band11,band11 */ 142 | }, { 143 | /* 90 MHz */ 90, 144 | /* .open_d = */ 0x00, /* high */ 145 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 146 | /* .tf_c = */ 0x34, /* R27[7:0] band12,band11 */ 147 | }, { 148 | /* 100 MHz */ 100, 149 | /* .open_d = */ 0x00, /* high */ 150 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 151 | /* .tf_c = */ 0x34, /* R27[7:0] band12,band11 */ 152 | }, { 153 | /* 110 MHz */ 110, 154 | /* .open_d = */ 0x00, /* high */ 155 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 156 | /* .tf_c = */ 0x24, /* R27[7:0] band13,band11 */ 157 | }, { 158 | /* 120 MHz */ 120, 159 | /* .open_d = */ 0x00, /* high */ 160 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 161 | /* .tf_c = */ 0x24, /* R27[7:0] band13,band11 */ 162 | }, { 163 | /* 140 MHz */ 140, 164 | /* .open_d = */ 0x00, /* high */ 165 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 166 | /* .tf_c = */ 0x14, /* R27[7:0] band14,band11 */ 167 | }, { 168 | /* 180 MHz */ 180, 169 | /* .open_d = */ 0x00, /* high */ 170 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 171 | /* .tf_c = */ 0x13, /* R27[7:0] band14,band12 */ 172 | }, { 173 | /* 220 MHz */ 220, 174 | /* .open_d = */ 0x00, /* high */ 175 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 176 | /* .tf_c = */ 0x13, /* R27[7:0] band14,band12 */ 177 | }, { 178 | /* 250 MHz */ 250, 179 | /* .open_d = */ 0x00, /* high */ 180 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 181 | /* .tf_c = */ 0x11, /* R27[7:0] highest,highest */ 182 | }, { 183 | /* 280 MHz */ 280, 184 | /* .open_d = */ 0x00, /* high */ 185 | /* .rf_mux_ploy = */ 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */ 186 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 187 | }, { 188 | /* 310 MHz */ 310, 189 | /* .open_d = */ 0x00, /* high */ 190 | /* .rf_mux_ploy = */ 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 191 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 192 | }, { 193 | /* 450 MHz */ 450, 194 | /* .open_d = */ 0x00, /* high */ 195 | /* .rf_mux_ploy = */ 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */ 196 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 197 | }, { 198 | /* 588 MHz */ 588, 199 | /* .open_d = */ 0x00, /* high */ 200 | /* .rf_mux_ploy = */ 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 201 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 202 | }, { 203 | /* 650 MHz */ 650, 204 | /* .open_d = */ 0x00, /* high */ 205 | /* .rf_mux_ploy = */ 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */ 206 | /* .tf_c = */ 0x00, /* R27[7:0] highest,highest */ 207 | } 208 | }; 209 | 210 | /* 211 | * local vars 212 | */ 213 | uint8_t r820t_regs[R820T2_NUM_REGS]; 214 | uint32_t r_freq; 215 | uint32_t r_xtal; 216 | uint32_t r_ifreq; 217 | 218 | 219 | // Send a block of data to the R820T2 via I2C 220 | void R820T2_i2c_write(uint8_t reg, uint8_t *data, uint8_t sz) 221 | { 222 | if (sz <= R820T2_NUM_REGS) 223 | /* Configure slave address, nbytes, reload and generate start */ 224 | SendI2cbytes(R820T2_ADDRESS, reg, data, sz); 225 | } 226 | 227 | /* 228 | * Write single R820T2 reg via I2C 229 | */ 230 | void R820T2_i2c_write_reg(uint8_t reg, uint8_t data) 231 | { 232 | if(reg>=R820T2_NUM_REGS) return; 233 | r820t_regs[reg] = data; 234 | SendI2cbyte(R820T2_ADDRESS, reg, r820t_regs[reg]); 235 | } 236 | 237 | 238 | // Write single R820T2 reg via I2C with mask vs cached 239 | 240 | void R820T2_i2c_write_cache_mask(uint8_t reg, uint8_t data, uint8_t mask) 241 | { 242 | data = (data & mask) | (r820t_regs[reg] & ~mask); 243 | r820t_regs[reg] = data; 244 | SendI2cbyte(R820T2_ADDRESS, reg, r820t_regs[reg]); 245 | } 246 | 247 | // Nibble-level bit reverse table 248 | const uint8_t bitrevnibble[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, 249 | 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf }; 250 | 251 | 252 | // get all regs up to & including desired reg 253 | void R820T2_i2c_read_raw(uint8_t *data, uint8_t sz) 254 | { 255 | ReadI2cbytes(R820T2_ADDRESS, 0, data, sz); // Get block of data 256 | for (int i =0; i > 4]; // bit reverse 259 | } 260 | } 261 | 262 | /* 263 | * Read R820T2 reg - uncached 264 | */ 265 | uint8_t R820T2_i2c_read_reg_uncached(uint8_t reg) 266 | { 267 | uint8_t sz = reg+1; 268 | uint8_t *data = r820t_regs; 269 | /* get all regs up to & including desired reg */ 270 | R820T2_i2c_read_raw(data, sz); 271 | return r820t_regs[reg]; 272 | } 273 | 274 | /* 275 | * Read R820T2 reg - cached 276 | */ 277 | uint8_t R820T2_i2c_read_reg_cached(uint8_t reg) 278 | { 279 | /* return desired */ 280 | return r820t_regs[reg]; 281 | } 282 | 283 | /* 284 | * r820t tuning logic 285 | */ 286 | #ifdef OPTIM_SET_MUX 287 | int r820t_set_mux_freq_idx = -1; /* Default set to invalid value in order to force set_mux */ 288 | #endif 289 | 290 | /* 291 | * Update Tracking Filter 292 | * 293 | * "inspired by Mauro Carvalho Chehab set_mux technique" 294 | * https://stuff.mit.edu/afs/sipb/contrib/linux/drivers/media/tuners/r820t.c 295 | * part of r820t_set_mux() (set tracking filter) 296 | */ 297 | static void R820T2_set_tf(uint32_t freq) 298 | { 299 | const struct r820t_freq_range *range; 300 | unsigned int i; 301 | // Get the proper frequency range in MHz instead of Hz 302 | freq = (uint32_t)((uint64_t)freq * 4295 >> 32); 303 | 304 | // Scan array for proper range 305 | for(i=0;iopen_d, 0x08); // Open Drain 312 | R820T2_i2c_write_cache_mask(0x1a, range->rf_mux_ploy, 0xc3); // RF_MUX,Polymux 313 | R820T2_i2c_write_reg(0x1b, range->tf_c); // TF Band 314 | 315 | /* XTAL CAP & Drive */ 316 | R820T2_i2c_write_cache_mask(0x10, 0x00, 0x0b); // Internal xtal no cap, bit3 = 0 ? 317 | R820T2_i2c_write_cache_mask(0x08, 0x80, 0xff); // Mixer buffer power on, high current, Image Gain Adjustment min 318 | R820T2_i2c_write_cache_mask(0x09, 0x00, 0xff); // IF Filter power on, high current, Image Gain Adjustment min 319 | } 320 | 321 | /* 322 | * Update LO PLL 323 | */ 324 | //#define _PLLDEBUG_ // if debugtrace required 325 | void R820T2_set_pll(uint32_t freq) 326 | { 327 | const uint32_t vco_min = 1770000000; 328 | const uint32_t vco_max = 3900000000; 329 | uint32_t pll_ref = (r_xtal >> 1); 330 | uint32_t pll_ref_2x = r_xtal; 331 | 332 | uint32_t vco_exact; 333 | uint32_t vco_frac; 334 | uint32_t con_frac; 335 | uint32_t div_num; 336 | uint32_t n_sdm; 337 | uint16_t sdm; 338 | uint8_t ni; 339 | uint8_t si; 340 | uint8_t nint; 341 | uint8_t tmp; 342 | 343 | /* Calculate vco output divider */ 344 | for (div_num = 0; div_num < 5; div_num++) 345 | { 346 | vco_exact = freq << (div_num + 1); 347 | if (vco_exact >= vco_min && vco_exact <= vco_max) 348 | { 349 | break; 350 | } 351 | } 352 | 353 | /* Calculate the integer PLL feedback divider */ 354 | vco_exact = freq << (div_num + 1); 355 | nint = (uint8_t)((vco_exact + (pll_ref >> 16)) / pll_ref_2x); 356 | vco_frac = vco_exact - pll_ref_2x * nint; 357 | 358 | nint -= 13; 359 | ni = (nint >> 2); 360 | si = nint - (ni << 2); 361 | 362 | R820T2_i2c_write_cache_mask( 0x10, 0x10, 0x10); // REF /2????? 363 | /* Set the vco output divider */ 364 | R820T2_i2c_write_cache_mask(0x10, (uint8_t)(div_num << 5), 0xe0); 365 | #ifdef _PLLDEBUG_ 366 | DbgPrintf("\nR820T2 vco output divider = %d", div_num); 367 | #endif 368 | /* Set the PLL Feedback integer divider */ 369 | tmp = (uint8_t)(ni + (si << 6)); 370 | R820T2_i2c_write_reg(0x14, tmp); 371 | #ifdef _PLLDEBUG_ 372 | DbgPrintf("\nR820T2 PLL Feedback integer divider = %d", tmp); 373 | #endif 374 | /* Update Fractional PLL */ 375 | if (vco_frac == 0) 376 | { 377 | #ifdef _PLLDEBUG_ 378 | DbgPrintf("\nR820T2 Disable frac pll"); 379 | #endif 380 | /* Disable frac pll */ 381 | R820T2_i2c_write_cache_mask(0x12, 0x08, 0x08); 382 | } 383 | else 384 | { 385 | #ifdef _PLLDEBUG_ 386 | DbgPrintf("\nR820T2 Compute the Sigma-Delta Modulator"); 387 | #endif 388 | /* Compute the Sigma-Delta Modulator */ 389 | vco_frac += pll_ref >> 16; 390 | sdm = 0; 391 | for (n_sdm = 0; n_sdm < 16; n_sdm++) 392 | { 393 | con_frac = pll_ref >> n_sdm; 394 | if (vco_frac >= con_frac) 395 | { 396 | sdm |= (uint16_t)(0x8000 >> n_sdm); 397 | vco_frac -= con_frac; 398 | if (vco_frac == 0) 399 | break; 400 | } 401 | } 402 | #ifdef _PLLDEBUG_ 403 | DbgPrintf("\nR820T2 smd = %ld", sdm); 404 | #endif 405 | uint32_t actual_freq = (((nint << 16) + sdm) * (uint64_t) pll_ref_2x) >> (div_num + 1 + 16); 406 | uint32_t delta = freq - actual_freq; 407 | #ifdef _PLLDEBUG_ 408 | if (actual_freq != freq) 409 | { 410 | DbgPrintf("\nTunning delta: %d Hz", delta); 411 | } 412 | #endif 413 | 414 | /* Update Sigma-Delta Modulator */ 415 | R820T2_i2c_write_reg(0x15, (uint8_t)(sdm & 0xff)); 416 | R820T2_i2c_write_reg(0x16, (uint8_t)(sdm >> 8)); 417 | 418 | /* Enable frac pll */ 419 | R820T2_i2c_write_cache_mask(0x12, 0x00, 0x08); 420 | } 421 | 422 | int i; 423 | uint8_t data[4]; 424 | for (i = 0; i < 2; i++) 425 | { 426 | SleepEx(1,false); 427 | /* Check if PLL has locked */ 428 | R820T2_i2c_read_raw(data, 3); 429 | if (data[2] & 0x40) 430 | break; 431 | 432 | if (!i) { 433 | /* Didn't lock. Increase VCO current */ 434 | R820T2_i2c_write_cache_mask(0x12, 0x60, 0xe0); 435 | } 436 | } 437 | 438 | if (data[2] & 0x40) 439 | { 440 | #ifdef _PLLDEBUG_ 441 | DbgPrintf("\nR820T2 Pll set reg2 = %x\n", data[2]); 442 | #endif 443 | return; 444 | } 445 | #ifdef _PLLDEBUG_ 446 | DbgPrintf("\nR820T2 Pll has lock at frequency %d kHz\n", freq); 447 | #endif 448 | /* set pll autotune = 8kHz ??? */ 449 | R820T2_i2c_write_cache_mask( 0x1a, 0x08, 0x08); 450 | 451 | return; 452 | } 453 | 454 | /* 455 | * Update Tracking Filter and LO to frequency 456 | */ 457 | void R820T2_set_freq(uint32_t freq) 458 | { 459 | uint32_t lo_freq = freq + r_ifreq; 460 | 461 | R820T2_set_tf(freq); 462 | R820T2_set_pll(lo_freq); 463 | r_freq = freq; 464 | } 465 | 466 | /* 467 | * Update LNA Gain 468 | */ 469 | void R820T2_set_lna_gain(uint8_t gain_index) 470 | { 471 | R820T2_i2c_write_cache_mask(0x05, gain_index, 0x0f); 472 | } 473 | 474 | /* 475 | * Update Mixer Gain 476 | */ 477 | void R820T2_set_mixer_gain(uint8_t gain_index) 478 | { 479 | R820T2_i2c_write_cache_mask(0x07, gain_index, 0x0f); 480 | } 481 | 482 | /* 483 | * Update VGA Gain 484 | */ 485 | void R820T2_set_vga_gain(uint8_t gain_index) 486 | { 487 | R820T2_i2c_write_cache_mask(0x0c, gain_index, 0x0f); 488 | } 489 | 490 | /* 491 | * Enable/Disable LNA AGC 492 | */ 493 | void R820T2_set_lna_agc(uint8_t value) 494 | { 495 | value = value != 0 ? 0x00 : 0x10; 496 | R820T2_i2c_write_cache_mask(0x05, value, 0x10); 497 | } 498 | 499 | /* 500 | * Enable/Disable Mixer AGC 501 | */ 502 | void R820T2_set_mixer_agc(uint8_t value) 503 | { 504 | value = value != 0 ? 0x10 : 0x00; 505 | R820T2_i2c_write_cache_mask(0x07, value, 0x10); 506 | } 507 | 508 | /* 509 | * Set IF Bandwidth 510 | */ 511 | void R820T2_set_if_bandwidth(uint8_t bw) 512 | { 513 | const uint8_t modes[] = { 0xE0, 0x80, 0x60, 0x00 }; 514 | uint8_t a = 0xB0 | (0x0F-(bw & 0x0F)); 515 | uint8_t b = 0x0F | modes[(bw & 0x3) >> 4]; 516 | R820T2_i2c_write_reg(0x0A, a); 517 | R820T2_i2c_write_reg(0x0B, b); 518 | } 519 | 520 | /* 521 | * Calibrate 522 | * Kanged from airspy firmware 523 | * "inspired by Mauro Carvalho Chehab calibration technique" 524 | * https://stuff.mit.edu/afs/sipb/contrib/linux/drivers/media/tuners/r820t.c 525 | * 526 | */ 527 | int32_t R820T2_calibrate(void) 528 | { 529 | int32_t i, cal_code; 530 | 531 | for (i = 0; i < 5; i++) // 5 try 532 | { 533 | // Set filt_cap 534 | R820T2_i2c_write_cache_mask(0x0b, 0x08, 0x60); 535 | 536 | // set cali clk =on 537 | R820T2_i2c_write_cache_mask(0x0f, 0x04, 0x04); 538 | 539 | // X'tal cap 0pF for PLL 540 | R820T2_i2c_write_cache_mask(0x10, 0x00, 0x03); 541 | 542 | // freq used for calibration 543 | R820T2_set_pll(CALIBRATION_LO); 544 | 545 | // Start Trigger 546 | R820T2_i2c_write_cache_mask(0x0b, 0x10, 0x10); 547 | 548 | Sleep(2); // 2ms 549 | 550 | // Stop Trigger 551 | R820T2_i2c_write_cache_mask(0x0b, 0x00, 0x10); 552 | 553 | /* set cali clk =off */ 554 | R820T2_i2c_write_cache_mask(0x0f, 0x00, 0x04); 555 | 556 | /* Check if calibration worked */ 557 | cal_code = R820T2_i2c_read_reg_uncached(0x04) & 0x0f; 558 | if (cal_code && cal_code != 0x0f) 559 | { 560 | // DbgPrintf("\nR820T2 calibrated step %d\n",i); 561 | return 0; 562 | } 563 | } 564 | DbgPrintf("\nR820T2 calibration failed\n"); 565 | return -1; 566 | } 567 | 568 | /* 569 | * Initialize the R820T 570 | */ 571 | void R820T2_init(void) 572 | { 573 | r_xtal = R820T_FREQ; 574 | r_ifreq = IFR820T; 575 | r_freq = 101800000; 576 | uint8_t data[R820T2_NUM_REGS]; 577 | DbgPrintf("\nR820T init"); 578 | memset(data, 0, sizeof(data)); 579 | 580 | memcpy(r820t_regs, r82xx_init_array, R820T2_NUM_REGS); 581 | // initialize the device 582 | R820T2_i2c_write(R820T2_WRITE_START,(uint8_t *) &r82xx_init_array[R820T2_WRITE_START], R820T2_NUM_REGS - R820T2_WRITE_START); 583 | 584 | /* Calibrate */ 585 | R820T2_calibrate(); 586 | 587 | /* set freq after calibrate */ 588 | R820T2_set_freq(r_freq); 589 | 590 | } 591 | 592 | void R820T2_set_stdby(void) 593 | { 594 | uint8_t data[R820T2_NUM_REGS]; 595 | memset(data, 0, sizeof(data)); 596 | memcpy(r820t_regs, data, R820T2_NUM_REGS); 597 | DbgPrintf("\nR820T2_set_stdby"); 598 | } 599 | 600 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/i2c_r820t2.h: -------------------------------------------------------------------------------- 1 | // Oscar Steila 2017 2 | #ifndef __r820t2__ 3 | #define __r820t2__ 4 | 5 | #include 6 | #include 7 | #include 8 | #include "ExtIO_sddc.h" // i2c Dbgprintf 9 | 10 | #define R820T2_ADDRESS ((0x1A)<<1) // 0011010+RW - 0x34 (w), 0x35 (r) 11 | #define IFR820T 7000000 12 | 13 | 14 | 15 | extern uint32_t r_freq; 16 | extern uint32_t r_xtal; 17 | extern uint32_t r_ifreq; 18 | extern const int r820t2_lna_gain_steps[16]; 19 | extern const int r820t2_mixer_gain_steps[16]; 20 | extern const int r820t2_vga_gain_steps[16]; 21 | 22 | void R820T2_init(void); 23 | void R820T2_set_stdby(void); 24 | void R820T2_i2c_write_reg(uint8_t reg, uint8_t data); 25 | void R820T2_i2c_read_raw(uint8_t *data, uint8_t sz); 26 | uint8_t R820T2_i2c_read_reg_uncached(uint8_t reg); 27 | uint8_t R820T2_i2c_read_reg_cached(uint8_t reg); 28 | void R820T2_set_freq(uint32_t freq); 29 | void R820T2_set_lna_gain(uint8_t gain_index); 30 | void R820T2_set_mixer_gain(uint8_t gain_index); 31 | void R820T2_set_vga_gain(uint8_t gain_index); 32 | void R820T2_set_lna_agc(uint8_t value); 33 | void R820T2_set_mixer_agc(uint8_t value); 34 | void R820T2_set_if_bandwidth(uint8_t bw); 35 | 36 | 37 | #endif 38 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/i2c_si5351.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * i2c_si5351.c 3 | * 4 | * Created on: Jan 17, 2017 5 | * Author: ik1xpv 6 | */ 7 | 8 | #include "i2c_si5351.h" 9 | 10 | // thanks to: Hans Summers, 2015 11 | // Website: http://www.hanssummers.com 12 | // 13 | 14 | 15 | uint8_t Si5351_init() 16 | { 17 | uint8_t r; 18 | // uint8_t data[10]; 19 | // Set crystal load capacitance 20 | r = SendI2cbyte(SI5351_ADDR, SI5351_CRYSTAL_LOAD, SI5351_CRYSTAL_LOAD_6PF | 0b00010010); 21 | 22 | SendI2cbyte(SI5351_ADDR, SI_CLK0_CONTROL, 0x80); // clocks off 23 | SendI2cbyte(SI5351_ADDR, SI_CLK1_CONTROL, 0x80); 24 | SendI2cbyte(SI5351_ADDR, SI_CLK2_CONTROL, 0x80); 25 | 26 | // ReadI2cbytes(SI5351_ADDR, SI_CLK0_CONTROL, data, 3); 27 | // DbgPrintf("\n\nSI_CLK1_CONTROL = %x %x %x \n", data[0], data[1], data[2]); 28 | DbgPrintf("\nSi5351_init()"); 29 | return r; 30 | } 31 | 32 | 33 | 34 | double fa,fb; 35 | 36 | //#define _PLLDEBUG_ 37 | // 38 | // Set up specified PLL with mult, num and denom 39 | // mult is 15..90 40 | // num is 0..1,048,575 (0xFFFFF) 41 | // denom is 0..1,048,575 (0xFFFFF) 42 | // 43 | void setupPLL(uint8_t pll, uint8_t mult, uint32_t num, uint32_t denom) 44 | { 45 | uint32_t P1; // PLL config register P1 46 | uint32_t P2; // PLL config register P2 47 | uint32_t P3; // PLL config register P3 48 | 49 | uint8_t data[8]; 50 | 51 | double x = 27000000.0; 52 | // the actual multiplier is mult + num / denom 53 | 54 | fa = x * ((double) mult + (double)num / (double)denom); 55 | #ifdef _PLLDEBUG_ 56 | DbgPrintf("pll = %d , mult = %d , num = %d , denom = %d\n", pll, mult, num, denom ); 57 | DbgPrintf("pll target %e \n", fa); 58 | #endif 59 | 60 | P1 = (uint32_t)(128 * ((float)num / (float)denom)); 61 | P1 = (uint32_t)(128 * (uint32_t)(mult) + P1 - 512); 62 | P2 = (uint32_t)(128 * ((float)num / (float)denom)); 63 | P2 = (uint32_t)(128 * num - denom * P2); 64 | P3 = denom; 65 | 66 | data[0] = (P3 & 0x0000FF00) >> 8; 67 | data[1] = (P3 & 0x000000FF); 68 | data[2] = (P1 & 0x00030000) >> 16; 69 | data[3] = (P1 & 0x0000FF00) >> 8; 70 | data[4] = (P1 & 0x000000FF); 71 | data[5] = ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16); 72 | data[6] = (P2 & 0x0000FF00) >> 8; 73 | data[7] = (P2 & 0x000000FF); 74 | 75 | SendI2cbytes(SI5351_ADDR, pll, data, sizeof(data)); 76 | } 77 | 78 | // 79 | // Set up MultiSynth with integer divider and R divider 80 | // R divider is the bit value which is OR'ed onto the appropriate register, it is a #define in si5351a.h 81 | // 82 | void setupMultisynth(uint8_t synth, uint32_t divider, uint8_t rDiv) 83 | { 84 | uint32_t P1; // Synth config register P1 85 | uint32_t P2; // Synth config register P2 86 | uint32_t P3; // Synth config register P3 87 | 88 | uint8_t data[8]; 89 | #ifdef _PLLDEBUG_ 90 | DbgPrintf("setupMultisynth synth = %d divider = %d rDiv= %d \n", synth, divider, rDiv); 91 | DbgPrintf("output expected f = %e\n", fa / divider); 92 | #endif 93 | P1 = 128 * divider - 512; 94 | P2 = 0; // P2 = 0, P3 = 1 forces an integer value for the divider 95 | P3 = 1; 96 | 97 | data[0] = (P3 & 0x0000FF00) >> 8; 98 | data[1] = (P3 & 0x000000FF); 99 | data[2] = ((P1 & 0x00030000) >> 16) | rDiv ; 100 | data[3] = (P1 & 0x0000FF00) >> 8 ; 101 | data[4] = (P1 & 0x000000FF); 102 | data[5] = ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16); 103 | data[6] = (P2 & 0x0000FF00) >> 8; 104 | data[7] = (P2 & 0x000000FF); 105 | 106 | SendI2cbytes(SI5351_ADDR, synth, data, sizeof(data)); 107 | } 108 | 109 | // 110 | // Switches off Si5351a output 111 | // Example: si5351aOutputOff(SI_CLK0_CONTROL); 112 | // will switch off output CLK0 113 | // 114 | uint8_t si5351aOutputOff(uint8_t clk) 115 | { 116 | return SendI2cbyte(SI5351_ADDR, clk, 0x80); // Refer to SiLabs AN619 to see bit values - 0x80 turns off the output stage 117 | } 118 | 119 | // 120 | // Set CLK0 output ON and to the specified frequency 121 | // Frequency is in the range 1MHz to 150MHz 122 | // Example: si5351aSetFrequency(10000000); 123 | // will set output CLK0 to 10MHz 124 | // 125 | // This example sets up PLL A 126 | // and MultiSynth 0 127 | // and produces the output on CLK0 128 | // 129 | 130 | 131 | void si5351aSetFrequency(uint32_t freq, uint32_t freq2) 132 | { 133 | uint32_t frequency; 134 | uint32_t pllFreq; 135 | uint32_t xtalFreq = SI5351_FREQ; 136 | uint32_t l; 137 | double f; 138 | uint8_t mult; 139 | uint32_t num; 140 | uint32_t denom; 141 | uint32_t divider; 142 | uint32_t rdiv; 143 | 144 | double corr = 0.9999314; 145 | 146 | DbgPrintf("\nsi5351 SetFreq ADC sampling:%d R820T reference:%d", freq, freq2); 147 | 148 | 149 | rdiv = SI_R_DIV_1; 150 | 151 | frequency = (uint32_t)((double) freq * corr); 152 | 153 | while (frequency < 1000000) 154 | { 155 | frequency = frequency * 2; 156 | rdiv += SI_R_DIV_2; 157 | } 158 | #ifdef _PLLDEBUG_ 159 | DbgPrintf("\nCLK0 frequency %d \n", frequency); 160 | #endif 161 | divider = 900000000UL / frequency;// Calculate the division ratio. 900,000,000 is the maximum internal 162 | // PLL frequency: 900MHz 163 | if (divider % 2) divider--; // Ensure an even integer division ratio 164 | 165 | pllFreq = divider * frequency; // Calculate the pllFrequency: the divider * desired output frequency 166 | #ifdef _PLLDEBUG_ 167 | DbgPrintf("pllA Freq %d \n", pllFreq); 168 | #endif 169 | mult = pllFreq / xtalFreq; // Determine the multiplier to get to the required pllFrequency 170 | l = pllFreq % xtalFreq; // It has three parts: 171 | f =(double) l; // mult is an integer that must be in the range 15..90 172 | f *= 1048575; // num and denom are the fractional parts, the numerator and denominator 173 | f /= xtalFreq; // each is 20 bits (range 0..1048575) 174 | num = (uint32_t) f; // the actual multiplier is mult + num / denom 175 | denom = 1048575; // For simplicity we set the denominator to the maximum 1048575 176 | // Set up PLL A with the calculated multiplication ratio 177 | setupPLL(SI_SYNTH_PLL_A, mult, num, denom); 178 | // Set up MultiSynth divider 0, with the calculated divider. 179 | // The final R division stage can divide by a power of two, from 1..128. 180 | // represented by constants SI_R_DIV1 to SI_R_DIV128 (see si5351a.h header file) 181 | // If you want to output frequencies below 1MHz, you have to use the 182 | // final R division stage 183 | setupMultisynth(SI_SYNTH_MS_0, divider, rdiv); 184 | // Reset the PLL. This causes a glitch in the output. For small changes to 185 | // the parameters, you don't need to reset the PLL, and there is no glitch 186 | SendI2cbyte((UINT8)SI5351_ADDR, (UINT8)SI_PLL_RESET, (UINT8) 0x20); //pllA 187 | // Finally switch on the CLK0 output (0x4F) 188 | // and set the MultiSynth0 input to be PLL A 189 | SendI2cbyte(SI5351_ADDR, SI_CLK0_CONTROL, 0x4F | SI_CLK_SRC_PLL_A); 190 | 191 | if (freq2 > 0) 192 | { 193 | // calculate clk2 194 | frequency = (uint32_t)((double)freq2 * corr);; 195 | rdiv = SI_R_DIV_1; 196 | xtalFreq = SI5351_FREQ; 197 | while (frequency <= 1000000) 198 | { 199 | frequency = frequency * 2; 200 | rdiv += SI_R_DIV_2; 201 | } 202 | #ifdef _PLLDEBUG_ 203 | DbgPrintf("\nCLK2 frequency %d \n", frequency); 204 | #endif 205 | divider = 900000000UL / frequency;// Calculate the division ratio. 900,000,000 is the maximum internal 206 | // PLL frequency: 900MHz 207 | if (divider % 2) divider--; // Ensure an even integer division ratio 208 | 209 | pllFreq = divider * frequency; // Calculate the pllFrequency: the divider * desired output frequency 210 | #ifdef _PLLDEBUG_ 211 | DbgPrintf("pllB Freq %d \n", pllFreq); 212 | #endif 213 | mult = pllFreq / xtalFreq; // Determine the multiplier to get to the required pllFrequency 214 | l = pllFreq % xtalFreq; // It has three parts: 215 | f = (double)l; // mult is an integer that must be in the range 15..90 216 | f *= 1048575; // num and denom are the fractional parts, the numerator and denominator 217 | f /= xtalFreq; // each is 20 bits (range 0..1048575) 218 | num = (uint32_t)f; // the actual multiplier is mult + num / denom 219 | denom = 1048575; // For simplicity we set the denominator to the maximum 1048575 220 | 221 | // Set up PLL B with the calculated multiplication ratio 222 | setupPLL(SI_SYNTH_PLL_B, mult, num, denom); 223 | // Set up MultiSynth divider 0, with the calculated divider. 224 | // The final R division stage can divide by a power of two, from 1..128. 225 | // represented by constants SI_R_DIV1 to SI_R_DIV128 (see si5351a.h header file) 226 | // If you want to output frequencies below 1MHz, you have to use the 227 | // final R division stage 228 | 229 | setupMultisynth(SI_SYNTH_MS_2, divider, rdiv); 230 | // Reset the PLL. This causes a glitch in the output. For small changes to 231 | // the parameters, you don't need to reset the PLL, and there is no glitch 232 | SendI2cbyte((UINT8)SI5351_ADDR, (UINT8)SI_PLL_RESET, (UINT8)0x80); //pllB 233 | // Finally switch on the CLK2 output (0x4C) 234 | // and set the MultiSynth0 input to be PLL A 235 | SendI2cbyte(SI5351_ADDR, SI_CLK2_CONTROL, 0x4C | SI_CLK_SRC_PLL_B); // select PLLB 236 | // calculate clk2 237 | } 238 | } 239 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/i2c_si5351.h: -------------------------------------------------------------------------------- 1 | /* 2 | * i2c_si5351.h 3 | * 4 | * Created on: Jan 17, 2017 5 | * Author: ik1xpv 6 | */ 7 | 8 | #ifndef USER_I2C_SI5351_H_ 9 | #define USER_I2C_SI5351_H_ 10 | 11 | 12 | #include 13 | #include 14 | #include 15 | #include "ExtIO_sddc.h" // i2c Dbgprintf 16 | 17 | #define SI_CLK0_CONTROL 16 // Register definitions 18 | #define SI_CLK1_CONTROL 17 19 | #define SI_CLK2_CONTROL 18 20 | #define SI_SYNTH_PLL_A 26 21 | #define SI_SYNTH_PLL_B 34 22 | #define SI_SYNTH_MS_0 42 23 | #define SI_SYNTH_MS_1 50 24 | #define SI_SYNTH_MS_2 58 25 | #define SI_PLL_RESET (0x177) 26 | 27 | #define SI_R_DIV_1 0b00000000 // R-division ratio definitions 28 | #define SI_R_DIV_2 0b00010000 29 | #define SI_R_DIV_4 0b00100000 30 | #define SI_R_DIV_8 0b00110000 31 | #define SI_R_DIV_16 0b01000000 32 | #define SI_R_DIV_32 0b01010000 33 | #define SI_R_DIV_64 0b01100000 34 | #define SI_R_DIV_128 0b01110000 35 | 36 | #define SI_CLK_SRC_PLL_A 0b00000000 37 | #define SI_CLK_SRC_PLL_B 0b00100000 38 | 39 | #define SI5351_FREQ 27000000 // Crystal frequency 40 | #define SI5351_PLL_FIXED 80000000000ULL 41 | 42 | uint8_t si5351aOutputOff(uint8_t clk); 43 | void si5351aSetFrequency(uint32_t frequencyA, uint32_t frequencyB); 44 | uint8_t Si5351_init(); 45 | 46 | /* Define definitions */ 47 | 48 | #define SI5351_ADDR (0x60 << 1 ) 49 | #define SI5351_XTAL_FREQ 25000000 50 | 51 | #define SI5351_CRYSTAL_LOAD 183 52 | #define SI5351_CRYSTAL_LOAD_MASK (3<<6) 53 | #define SI5351_CRYSTAL_LOAD_0PF (0<<6) 54 | #define SI5351_CRYSTAL_LOAD_6PF (1<<6) 55 | #define SI5351_CRYSTAL_LOAD_8PF (2<<6) 56 | #define SI5351_CRYSTAL_LOAD_10PF (3<<6) 57 | 58 | #define SI5351_PLL_INPUT_SOURCE 15 59 | #define SI5351_CLKIN_DIV_MASK (3<<6) 60 | #define SI5351_CLKIN_DIV_1 (0<<6) 61 | #define SI5351_CLKIN_DIV_2 (1<<6) 62 | #define SI5351_CLKIN_DIV_4 (2<<6) 63 | #define SI5351_CLKIN_DIV_8 (3<<6) 64 | #define SI5351_PLLB_SOURCE (1<<3) 65 | #define SI5351_PLLA_SOURCE (1<<2) 66 | 67 | /* 68 | low jtter noise freq 69 | 70 | VCO = 864 MHz = 27 MHz * 32 71 | 72 MHz = 864 MHz / 12 72 | f/4 = 18MHz 73 | 74 | VCO = 810 MHz = 27 MHz * 30 75 | 81 MHz = 810 MHz / 10 76 | 77 | */ 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | #endif /* USER_I2C_SI5351_H_ */ 87 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/rfddc.cpp: -------------------------------------------------------------------------------- 1 | // Oscar Steila 2017 2 | #include "rfddc.h" 3 | extern bool gR820Ton; 4 | 5 | fftwf_complex intimefft[EVENODD][NVIA][FFTXBUF + 1][FFTN]; 6 | fftwf_complex outfreqfft[EVENODD][NVIA][FFTXBUF + 1][FFTN]; 7 | fftwf_complex infreqfft[EVENODD][NVIA][FFTXBUF + 1][D_FFTN]; 8 | fftwf_complex outtimefft[EVENODD][NVIA][FFTXBUF + 1][D_FFTN]; 9 | float wnd[FFTN]; 10 | fftwf_complex outtime[FFTXBUF + 1][D_FFTN]; 11 | fftwf_plan ptime2freq[EVENODD][NVIA][FFTXBUF + 1]; // fftw plan buffers per thread 12 | fftwf_plan pfreq2time[EVENODD][NVIA][FFTXBUF + 1]; // fftw plan buffers per thread 13 | short ins[FRAMEN + FFTN]; 14 | fftwf_complex Htfilter[D_FFTN]; // lpb filter 15 | 16 | 17 | std::atomic isdying(false); 18 | std::atomic dataready0(false); 19 | std::atomic dataready1(false); 20 | std::atomic evenodd(false); 21 | std::atomic gtunebin(0); 22 | 23 | float htfilter129[129] = // ht 129 sample 0.45 use FFTN == 256 24 | { 25 | -0.000000000016F, 0.000000000136F, -0.000000000407F, 0.000000000650F, -0.000000000000F, -0.000000003822F, 0.000000015349F, -0.000000041847F, 26 | 0.000000092529F, -0.000000175271F, 0.000000289472F, -0.000000414201F, 0.000000492207F, -0.000000412804F, 0.000000000000F, 0.000000984140F, 27 | -0.000002808295F, 0.000005700312F, -0.000009727295F, 0.000014630037F, -0.000019631495F, 0.000023260842F, -0.000023257435F, 0.000016636264F, 28 | -0.000000000000F, -0.000029835803F, 0.000074884845F, -0.000134756870F, 0.000205307121F, -0.000277435990F, 0.000336400930F, -0.000362052401F, 29 | 0.000330379676F, -0.000216626387F, 0.000000000000F, 0.000330333735F, -0.000768672126F, 0.001286699274F, -0.001829294596F, 0.002313723926F, 30 | -0.002633567416F, 0.002668288956F, -0.002298599502F, 0.001426776350F, -0.000000000000F, -0.001966261013F, 0.004368542866F, -0.007003365658F, 31 | 0.009566569761F, -0.011666658002F, 0.012853137483F, -0.012658740589F, 0.010652113943F, -0.006495452691F, 0.000000000000F, 0.008828344586F, 32 | -0.019760642636F, 0.032339520267F, -0.045899922116F, 0.059615877543F, -0.072569586046F, 0.083835852339F, -0.092572422387F, 0.098105509581F, 33 | 0.899999999992F, 0.098105509581F, -0.092572422387F, 0.083835852339F, -0.072569586046F, 0.059615877543F, -0.045899922116F, 0.032339520267F, 34 | -0.019760642636F, 0.008828344586F, 0.000000000000F, -0.006495452691F, 0.010652113943F, -0.012658740589F, 0.012853137483F, -0.011666658002F, 35 | 0.009566569761F, -0.007003365658F, 0.004368542866F, -0.001966261013F, -0.000000000000F, 0.001426776350F, -0.002298599502F, 0.002668288956F, 36 | -0.002633567416F, 0.002313723926F, -0.001829294596F, 0.001286699274F, -0.000768672126F, 0.000330333735F, 0.000000000000F, -0.000216626387F, 37 | 0.000330379676F, -0.000362052401F, 0.000336400930F, -0.000277435990F, 0.000205307121F, -0.000134756870F, 0.000074884845F, -0.000029835803F, 38 | -0.000000000000F, 0.000016636264F, -0.000023257435F, 0.000023260842F, -0.000019631495F, 0.000014630037F, -0.000009727295F, 0.000005700312F, 39 | -0.000002808295F, 0.000000984140F, 0.000000000000F, -0.000000412804F, 0.000000492207F, -0.000000414201F, 0.000000289472F, -0.000000175271F, 40 | 0.000000092529F, -0.000000041847F, 0.000000015349F, -0.000000003822F, -0.000000000000F, 0.000000000650F, -0.000000000407F, 0.000000000136F, 41 | -0.000000000016F 42 | }; 43 | 44 | float htfilter65[65] = // ht 65 sample 0.42 use FFTN == 128 45 | { 46 | 0.000000005437F, 0.000000019750F, -0.000000383468F, 0.000001783791F, -0.000004979907F, 0.000009464401F, -0.000011107482F, 0.000000000000F, 47 | 0.000038683041F, -0.000117318195F, 0.000230422153F, -0.000335041261F, 0.000338311654F, -0.000109045756F, -0.000472156508F, 0.001424216585F, 48 | -0.002563423888F, 0.003439472384F, -0.003373566972F, 0.001645103700F, 0.002178940892F, -0.007853031243F, 0.014149915970F, -0.018818313088F, 49 | 0.018925432801F, -0.011586254959F, -0.005078424150F, 0.031048382651F, -0.063912978779F, 0.099037750433F, -0.130444706443F, 0.152212824175F, 50 | 0.840000004559F, 0.152212824175F, -0.130444706443F, 0.099037750433F, -0.063912978779F, 0.031048382651F, -0.005078424150F, -0.011586254959F, 51 | 0.018925432801F, -0.018818313088F, 0.014149915970F, -0.007853031243F, 0.002178940892F, 0.001645103700F, -0.003373566972F, 0.003439472384F, 52 | -0.002563423888F, 0.001424216585F, -0.000472156508F, -0.000109045756F, 0.000338311654F, -0.000335041261F, 0.000230422153F, -0.000117318195F, 53 | 0.000038683041F, 0.000000000000F, -0.000011107482F, 0.000009464401F, -0.000004979907F, 0.000001783791F, -0.000000383468F, 0.000000019750F, 54 | 0.000000005437F 55 | }; 56 | 57 | 58 | float htfilter33[33] = // ht 33 sample 0.42 use FFTN == 64 59 | { 60 | -0.000052388424F, 0.000213327781F, -0.000397867753F, 0.000305829080F, 0.000573604033F, -0.002725960948F, 0.006150113658F, -0.009841958818F, 61 | 0.011536069359F, -0.008016130355F, -0.003898905405F, 0.025933065625F, -0.057057848021F, 0.092983818405F, -0.126867797105F, 0.151163480843F, 62 | 0.839999096090F, 0.151163480843F, -0.126867797105F, 0.092983818405F, -0.057057848021F, 0.025933065625F, -0.003898905405F, -0.008016130355F, 63 | 0.011536069359F, -0.009841958818F, 0.006150113658F, -0.002725960948F, 0.000573604033F, 0.000305829080F, -0.000397867753F, 0.000213327781F, 64 | -0.000052388424F 65 | }; 66 | 67 | 68 | void f_thread0() 69 | { 70 | while (!isdying) 71 | { 72 | if (dataready0) 73 | { 74 | int e = evenodd; 75 | int me = e ^ 1; 76 | for (int m = 1; m < (FFTXBUF + 1); m++) 77 | { 78 | for (int w = 0, h = 0; w < FFTN / 16; w++) 79 | { 80 | intimefft[e][0][m][h][0] = ins[m*FFTN + h] * wnd[h++]; 81 | intimefft[e][0][m][h][0] = ins[m*FFTN + h] * wnd[h++]; 82 | intimefft[e][0][m][h][0] = ins[m*FFTN + h] * wnd[h++]; 83 | intimefft[e][0][m][h][0] = ins[m*FFTN + h] * wnd[h++]; 84 | intimefft[e][0][m][h][0] = ins[m*FFTN + h] * wnd[h++]; 85 | intimefft[e][0][m][h][0] = ins[m*FFTN + h] * wnd[h++]; 86 | intimefft[e][0][m][h][0] = ins[m*FFTN + h] * wnd[h++]; 87 | intimefft[e][0][m][h][0] = ins[m*FFTN + h] * wnd[h++]; 88 | } 89 | fftwf_execute(ptime2freq[e][0][m]); 90 | fftwf_execute(pfreq2time[e][0][m]); 91 | } 92 | for (int h = D_FFTN2; h < D_FFTN; ) // 1/2 D_FFTN copy to new frame interleaving 93 | { 94 | outtimefft[e][0][0][h][0] = outtimefft[me][0][FFTXBUF][h][0]; 95 | outtimefft[e][0][0][h][1] = outtimefft[me][0][FFTXBUF][h++][1]; 96 | outtimefft[e][0][0][h][0] = outtimefft[me][0][FFTXBUF][h][0]; 97 | outtimefft[e][0][0][h][1] = outtimefft[me][0][FFTXBUF][h++][1]; 98 | outtimefft[e][0][0][h][0] = outtimefft[me][0][FFTXBUF][h][0]; 99 | outtimefft[e][0][0][h][1] = outtimefft[me][0][FFTXBUF][h++][1]; 100 | outtimefft[e][0][0][h][0] = outtimefft[me][0][FFTXBUF][h][0]; 101 | outtimefft[e][0][0][h][1] = outtimefft[me][0][FFTXBUF][h++][1]; 102 | } 103 | fftwf_complex * pin1 = &outtimefft[me][0][0][D_FFTN2]; 104 | fftwf_complex * pin2 = &outtimefft[me][1][0][0]; 105 | fftwf_complex * pout = &outtime[0][0]; 106 | if (gR820Ton == false) 107 | { 108 | for (int m = 0, k = 0; m < (FFTXBUF * D_FFTN) / 16; m++) 109 | { 110 | pout[k][0] = pin1[k][0] + pin2[k][0]; 111 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 112 | pout[k][0] = pin1[k][0] + pin2[k][0]; 113 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 114 | pout[k][0] = pin1[k][0] + pin2[k][0]; 115 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 116 | pout[k][0] = pin1[k][0] + pin2[k][0]; 117 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 118 | pout[k][0] = pin1[k][0] + pin2[k][0]; 119 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 120 | pout[k][0] = pin1[k][0] + pin2[k][0]; 121 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 122 | pout[k][0] = pin1[k][0] + pin2[k][0]; 123 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 124 | pout[k][0] = pin1[k][0] + pin2[k][0]; 125 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 126 | } 127 | } 128 | else // reverse IQ spectrum 129 | { 130 | for (int m = 0, k = 0; m < (FFTXBUF * D_FFTN) / 16; m++) 131 | { 132 | pout[k][0] = pin1[k][0] + pin2[k][0]; 133 | pout[k][1] = - pin1[k][1] - pin2[k++][1]; 134 | pout[k][0] = pin1[k][0] + pin2[k][0]; 135 | pout[k][1] = - pin1[k][1] - pin2[k++][1]; 136 | pout[k][0] = pin1[k][0] + pin2[k][0]; 137 | pout[k][1] = - pin1[k][1] - pin2[k++][1]; 138 | pout[k][0] = pin1[k][0] + pin2[k][0]; 139 | pout[k][1] = - pin1[k][1] - pin2[k++][1]; 140 | pout[k][0] = pin1[k][0] + pin2[k][0]; 141 | pout[k][1] = - pin1[k][1] - pin2[k++][1]; 142 | pout[k][0] = pin1[k][0] + pin2[k][0]; 143 | pout[k][1] = - pin1[k][1] - pin2[k++][1]; 144 | pout[k][0] = pin1[k][0] + pin2[k][0]; 145 | pout[k][1] = - pin1[k][1] - pin2[k++][1]; 146 | pout[k][0] = pin1[k][0] + pin2[k][0]; 147 | pout[k][1] = - pin1[k][1] - pin2[k++][1]; 148 | } 149 | } 150 | dataready0 = false; 151 | } 152 | 153 | std::this_thread::yield(); 154 | } 155 | }; 156 | void f_thread1() 157 | { 158 | while (!isdying) 159 | { 160 | if (dataready1) 161 | { 162 | int e = evenodd; 163 | int me = e ^ 1; 164 | for (int m = 0; m < FFTXBUF; m++) 165 | { 166 | for (int w = 0, h = 0; w < FFTN / 16; w++) 167 | { 168 | intimefft[e][1][m][h][0] = ins[m*FFTN + FFTN2 + h] * wnd[h++]; 169 | intimefft[e][1][m][h][0] = ins[m*FFTN + FFTN2 + h] * wnd[h++]; 170 | intimefft[e][1][m][h][0] = ins[m*FFTN + FFTN2 + h] * wnd[h++]; 171 | intimefft[e][1][m][h][0] = ins[m*FFTN + FFTN2 + h] * wnd[h++]; 172 | intimefft[e][1][m][h][0] = ins[m*FFTN + FFTN2 + h] * wnd[h++]; 173 | intimefft[e][1][m][h][0] = ins[m*FFTN + FFTN2 + h] * wnd[h++]; 174 | intimefft[e][1][m][h][0] = ins[m*FFTN + FFTN2 + h] * wnd[h++]; 175 | intimefft[e][1][m][h][0] = ins[m*FFTN + FFTN2 + h] * wnd[h++]; 176 | } 177 | fftwf_execute(ptime2freq[e][1][m]); 178 | fftwf_execute(pfreq2time[e][1][m]); 179 | } 180 | fftwf_complex * pin1 = &outtimefft[me][0][FFTXBUF / 2][D_FFTN2]; 181 | fftwf_complex * pin2 = &outtimefft[me][1][FFTXBUF / 2][0]; 182 | fftwf_complex * pout = &outtime[FFTXBUF / 2][0]; 183 | if (gR820Ton == false) 184 | { 185 | for (int m = 0, k = 0; m < (FFTXBUF * D_FFTN) / 16; m++) 186 | { 187 | pout[k][0] = pin1[k][0] + pin2[k][0]; 188 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 189 | pout[k][0] = pin1[k][0] + pin2[k][0]; 190 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 191 | pout[k][0] = pin1[k][0] + pin2[k][0]; 192 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 193 | pout[k][0] = pin1[k][0] + pin2[k][0]; 194 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 195 | pout[k][0] = pin1[k][0] + pin2[k][0]; 196 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 197 | pout[k][0] = pin1[k][0] + pin2[k][0]; 198 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 199 | pout[k][0] = pin1[k][0] + pin2[k][0]; 200 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 201 | pout[k][0] = pin1[k][0] + pin2[k][0]; 202 | pout[k][1] = pin1[k][1] + pin2[k++][1]; 203 | } 204 | } 205 | else // reverse IQ spectrum 206 | { 207 | for (int m = 0, k = 0; m < (FFTXBUF * D_FFTN) / 16; m++) 208 | { 209 | pout[k][0] = pin1[k][0] + pin2[k][0]; 210 | pout[k][1] = -pin1[k][1] - pin2[k++][1]; 211 | pout[k][0] = pin1[k][0] + pin2[k][0]; 212 | pout[k][1] = -pin1[k][1] - pin2[k++][1]; 213 | pout[k][0] = pin1[k][0] + pin2[k][0]; 214 | pout[k][1] = -pin1[k][1] - pin2[k++][1]; 215 | pout[k][0] = pin1[k][0] + pin2[k][0]; 216 | pout[k][1] = -pin1[k][1] - pin2[k++][1]; 217 | pout[k][0] = pin1[k][0] + pin2[k][0]; 218 | pout[k][1] = -pin1[k][1] - pin2[k++][1]; 219 | pout[k][0] = pin1[k][0] + pin2[k][0]; 220 | pout[k][1] = -pin1[k][1] - pin2[k++][1]; 221 | pout[k][0] = pin1[k][0] + pin2[k][0]; 222 | pout[k][1] = -pin1[k][1] - pin2[k++][1]; 223 | pout[k][0] = pin1[k][0] + pin2[k][0]; 224 | pout[k][1] = -pin1[k][1] - pin2[k++][1]; 225 | } 226 | } 227 | dataready1 = false; 228 | } 229 | 230 | std::this_thread::yield(); 231 | } 232 | }; 233 | 234 | 235 | rfddc::rfddc() : 236 | t0(f_thread0), 237 | t1(f_thread1), 238 | g0(t0), 239 | g1(t1) 240 | { 241 | 242 | }; 243 | 244 | 245 | void rfddc::initp() 246 | { 247 | // init setup 248 | 249 | for (int f = 0; f < NVIA; f++) 250 | { 251 | for (int m = 0; m < FFTXBUF + 1; m++) 252 | { 253 | for (int e = 0; e < EVENODD; e++) 254 | { 255 | ptime2freq[e][f][m] = fftwf_plan_dft_1d(FFTN, intimefft[e][f][m], outfreqfft[e][f][m], FFTW_FORWARD, FFTW_MEASURE); 256 | pfreq2time[e][f][m] = fftwf_plan_dft_1d(D_FFTN, infreqfft[e][f][m], outtimefft[e][f][m], FFTW_BACKWARD, FFTW_MEASURE); 257 | } 258 | } 259 | } 260 | //init window 261 | int N = FFTN - 1; 262 | float pi = (float)4 * (float)atan(1.0); 263 | for (int n = 0; n < FFTN2; n++) { 264 | wnd[2 * FFTN2 - n - 1] = wnd[n] = (float) .149e-6;// ((.5 - .5*cos(2 * pi*n / N)))*(1.49e-8); // 1/(32736*FFTN); // hANN 265 | } 266 | memset(intimefft, 0, sizeof(intimefft)); 267 | memset(infreqfft, 0, sizeof(infreqfft)); 268 | memset(outfreqfft, 0, sizeof(outfreqfft)); 269 | memset(outtimefft, 0, sizeof(outtimefft)); 270 | { 271 | fftwf_complex htintime[D_FFTN]; 272 | fftwf_plan ptime2Ht; // fftw plan 273 | 274 | ptime2Ht = fftwf_plan_dft_1d(D_FFTN, htintime, Htfilter, FFTW_FORWARD, FFTW_ESTIMATE); 275 | memset(htintime, 0, sizeof(htintime)); 276 | for (int t = 0; t < D_FFTN / 2; t++) 277 | { 278 | switch (D_FFTN) 279 | { 280 | case 64: 281 | htintime[t][0] = htfilter33[t]; 282 | break; 283 | case 128: 284 | htintime[t][0] = htfilter65[t]; 285 | break; 286 | default: 287 | htintime[t][0] = htfilter129[t]; 288 | break; 289 | } 290 | htintime[t][1] = 0.0F; // htintime[t][1] * mwnd[t]; 291 | } 292 | fftwf_execute(ptime2Ht); 293 | } 294 | }; 295 | 296 | rfddc::~rfddc() 297 | { 298 | isdying = true; // fluss all threads 299 | }; 300 | 301 | 302 | int rfddc::arun(short *bufin) 303 | { 304 | evenodd = (!evenodd); // phase oddeven 305 | int e = evenodd; 306 | int v = !evenodd; 307 | int j; 308 | 309 | int tunebin = gtunebin; 310 | 311 | 312 | // start threads 313 | 314 | memcpy(ins, &ins[FRAMEN], sizeof(short)*FFTN); // save last FFTN block 315 | memcpy(&ins[FFTN], bufin, sizeof(short)*FRAMEN); 316 | 317 | dataready0 = true; 318 | dataready1 = true; 319 | 320 | // Tuning and decimation in frequency 321 | 322 | memset(&infreqfft[v][0][0][0][0], 0, sizeof(infreqfft)/2); 323 | for (int f = 0; f < NVIA; f++) 324 | { 325 | for (int m = 0; m < FFTXBUF + 1; m++) 326 | { 327 | if ((tunebin % 2 != 0) && (f != 0)) 328 | { 329 | for (int k = 0; k < D_FFTN2; k++) 330 | { 331 | j = tunebin + k; 332 | if (j >= FFTN) 333 | j -= FFTN; 334 | if (j < 0) 335 | j += FFTN; 336 | infreqfft[v][f][m][k][0] = outfreqfft[v][f][m][j][0] * Htfilter[k][0] - outfreqfft[v][f][m][j][1] * Htfilter[k][1]; 337 | infreqfft[v][f][m][k][1] = outfreqfft[v][f][m][j][1] * Htfilter[k][0] + outfreqfft[v][f][m][j][0] * Htfilter[k][1]; 338 | } 339 | for (int k = D_FFTN2; k < D_FFTN; k++) 340 | { 341 | j = tunebin - D_FFTN + k; 342 | if (j < 0) 343 | j += FFTN; 344 | if (j >= FFTN) 345 | j -= FFTN; 346 | infreqfft[v][f][m][k][0] = outfreqfft[v][f][m][j][0] * Htfilter[k][0] - outfreqfft[v][f][m][j][1] * Htfilter[k][1]; 347 | infreqfft[v][f][m][k][1] = outfreqfft[v][f][m][j][1] * Htfilter[k][0] + outfreqfft[v][f][m][j][0] * Htfilter[k][1]; 348 | } 349 | 350 | } 351 | else 352 | // invert phase of every interleaved frame if tunebin is odd 353 | { 354 | for (int k = 0; k < D_FFTN2; k++) 355 | { 356 | j = tunebin + k; 357 | if (j >= FFTN) 358 | j -= FFTN; 359 | if (j < 0) 360 | j += FFTN; 361 | infreqfft[v][f][m][k][0] = -(outfreqfft[v][f][m][j][0] * Htfilter[k][0] - outfreqfft[v][f][m][j][1] * Htfilter[k][1]); 362 | infreqfft[v][f][m][k][1] = -(outfreqfft[v][f][m][j][1] * Htfilter[k][0] + outfreqfft[v][f][m][j][0] * Htfilter[k][1]); 363 | } 364 | 365 | for (int k = D_FFTN2; k < D_FFTN; k++) 366 | { 367 | j = tunebin - D_FFTN + k; 368 | if (j < 0) 369 | j += FFTN; 370 | if (j >= FFTN) 371 | j -= FFTN; 372 | infreqfft[v][f][m][k][0] = -(outfreqfft[v][f][m][j][0] * Htfilter[k][0] - outfreqfft[v][f][m][j][1] * Htfilter[k][1]); 373 | infreqfft[v][f][m][k][1] = -(outfreqfft[v][f][m][j][1] * Htfilter[k][0] + outfreqfft[v][f][m][j][0] * Htfilter[k][1]); 374 | } 375 | 376 | } 377 | } 378 | } 379 | while ( (dataready0) || (dataready1) ) 380 | { 381 | std::this_thread::yield(); 382 | } 383 | return 0; 384 | }; 385 | -------------------------------------------------------------------------------- /ExtIO_sddc/ExtIO_sddc/rfddc.h: -------------------------------------------------------------------------------- 1 | #pragma once 2 | #pragma warning(disable : 4996) 3 | 4 | // RF DDC globals 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include "fftw3.h" 10 | 11 | 12 | #define FRAMEN (65536) 13 | #define FFTN (1024) 14 | #define FFTN2 (FFTN/2) 15 | #define FFTDSN (FFTN / DSN) 16 | #define FFTXBUF (FRAMEN/FFTN) 17 | #define NVIA (2) 18 | #define EVENODD (2) 19 | 20 | #define D_FFTN (256) // 256, 128, 64 21 | #define D_FFTN2 (D_FFTN/2) 22 | 23 | #define IFLEN (D_FFTN*FFTXBUF) 24 | 25 | extern fftwf_complex outtime[FFTXBUF + 1][D_FFTN]; 26 | extern short ins[FRAMEN + FFTN]; 27 | extern std::atomic gtunebin; 28 | extern std::atomic isdying; 29 | extern std::atomic dataready0; 30 | extern std::atomic dataready1; 31 | 32 | class thread_guard 33 | { 34 | std::thread& t; 35 | public: 36 | explicit thread_guard(std::thread& t_) : 37 | t(t_) 38 | {} 39 | ~thread_guard() 40 | { 41 | if (t.joinable()) 42 | { 43 | t.join(); 44 | } 45 | } 46 | thread_guard(thread_guard const&) = delete; 47 | thread_guard& operator=(thread_guard const&) = delete; 48 | }; 49 | 50 | 51 | class rfddc 52 | { 53 | public: 54 | rfddc(); 55 | ~rfddc(); 56 | void initp(); 57 | int arun(short *bufin); 58 | void tune(int bin); 59 | private: 60 | std::thread t0; // initializartion order is important 61 | std::thread t1; 62 | thread_guard g0; 63 | thread_guard g1; 64 | }; 65 | 66 | -------------------------------------------------------------------------------- /ExtIO_sddc/library/inc/CyAPI.h: -------------------------------------------------------------------------------- 1 | /* 2 | ## Cypress CyAPI C++ library header file (CyAPI.h) 3 | ## ======================================================= 4 | ## 5 | ## Copyright Cypress Semiconductor Corporation, 2009-2012, 6 | ## All Rights Reserved 7 | ## UNPUBLISHED, LICENSED SOFTWARE. 8 | ## 9 | ## CONFIDENTIAL AND PROPRIETARY INFORMATION 10 | ## WHICH IS THE PROPERTY OF CYPRESS. 11 | ## 12 | ## Use of this file is governed 13 | ## by the license agreement included in the file 14 | ## 15 | ## /license/license.rtf 16 | ## 17 | ## where is the Cypress software 18 | ## install root directory path. 19 | ## 20 | ## ======================================================= 21 | */ 22 | 23 | #ifndef CyUSBH 24 | #define CyUSBH 25 | 26 | #include "cyusb30_def.h" 27 | 28 | /* Data straucture for the Vendor request and data */ 29 | typedef struct vendorCmdData 30 | { 31 | UCHAR *buf; /* Pointer to the data */ 32 | UCHAR opCode; /* Vendor request code */ 33 | UINT addr; /* Read/Write address */ 34 | long size; /* Size of the read/write */ 35 | bool isRead; /* Read or write */ 36 | } vendorCmdData ; 37 | 38 | #ifndef __USB200_H__ 39 | #define __USB200_H__ 40 | #pragma pack(push,1) 41 | typedef struct _USB_DEVICE_DESCRIPTOR { 42 | UCHAR bLength; 43 | UCHAR bDescriptorType; 44 | USHORT bcdUSB; 45 | UCHAR bDeviceClass; 46 | UCHAR bDeviceSubClass; 47 | UCHAR bDeviceProtocol; 48 | UCHAR bMaxPacketSize0; 49 | USHORT idVendor; 50 | USHORT idProduct; 51 | USHORT bcdDevice; 52 | UCHAR iManufacturer; 53 | UCHAR iProduct; 54 | UCHAR iSerialNumber; 55 | UCHAR bNumConfigurations; 56 | } USB_DEVICE_DESCRIPTOR, *PUSB_DEVICE_DESCRIPTOR; 57 | 58 | typedef struct _USB_ENDPOINT_DESCRIPTOR { 59 | UCHAR bLength; 60 | UCHAR bDescriptorType; 61 | UCHAR bEndpointAddress; 62 | UCHAR bmAttributes; 63 | USHORT wMaxPacketSize; 64 | UCHAR bInterval; 65 | } USB_ENDPOINT_DESCRIPTOR, *PUSB_ENDPOINT_DESCRIPTOR; 66 | 67 | typedef struct _USB_CONFIGURATION_DESCRIPTOR { 68 | UCHAR bLength; 69 | UCHAR bDescriptorType; 70 | USHORT wTotalLength; 71 | UCHAR bNumInterfaces; 72 | UCHAR bConfigurationValue; 73 | UCHAR iConfiguration; 74 | UCHAR bmAttributes; 75 | UCHAR MaxPower; 76 | } USB_CONFIGURATION_DESCRIPTOR, *PUSB_CONFIGURATION_DESCRIPTOR; 77 | 78 | typedef struct _USB_INTERFACE_DESCRIPTOR { 79 | UCHAR bLength; 80 | UCHAR bDescriptorType; 81 | UCHAR bInterfaceNumber; 82 | UCHAR bAlternateSetting; 83 | UCHAR bNumEndpoints; 84 | UCHAR bInterfaceClass; 85 | UCHAR bInterfaceSubClass; 86 | UCHAR bInterfaceProtocol; 87 | UCHAR iInterface; 88 | } USB_INTERFACE_DESCRIPTOR, *PUSB_INTERFACE_DESCRIPTOR; 89 | 90 | typedef struct _USB_STRING_DESCRIPTOR { 91 | UCHAR bLength; 92 | UCHAR bDescriptorType; 93 | WCHAR bString[1]; 94 | } USB_STRING_DESCRIPTOR, *PUSB_STRING_DESCRIPTOR; 95 | 96 | typedef struct _USB_COMMON_DESCRIPTOR { 97 | UCHAR bLength; 98 | UCHAR bDescriptorType; 99 | } USB_COMMON_DESCRIPTOR, *PUSB_COMMON_DESCRIPTOR; 100 | #pragma pack(pop) 101 | #endif 102 | 103 | /*******************************************************************************/ 104 | class CCyIsoPktInfo { 105 | public: 106 | LONG Status; 107 | LONG Length; 108 | }; 109 | 110 | /*******************************************************************************/ 111 | 112 | 113 | /* {AE18AA60-7F6A-11d4-97DD-00010229B959} */ 114 | static GUID CYUSBDRV_GUID = {0xae18aa60, 0x7f6a, 0x11d4, 0x97, 0xdd, 0x0, 0x1, 0x2, 0x29, 0xb9, 0x59}; 115 | 116 | typedef enum {TGT_DEVICE, TGT_INTFC, TGT_ENDPT, TGT_OTHER } CTL_XFER_TGT_TYPE; 117 | typedef enum {REQ_STD, REQ_CLASS, REQ_VENDOR } CTL_XFER_REQ_TYPE; 118 | typedef enum {DIR_TO_DEVICE, DIR_FROM_DEVICE } CTL_XFER_DIR_TYPE; 119 | typedef enum {XMODE_BUFFERED, XMODE_DIRECT } XFER_MODE_TYPE; 120 | 121 | const int MAX_ENDPTS = 32; 122 | const int MAX_INTERFACES = 255; 123 | const int USB_STRING_MAXLEN = 256; 124 | 125 | #define BUFSIZE_UPORT 2048 //4096 - CDT 130492 126 | typedef enum { RAM = 1, I2CE2PROM, SPIFLASH } FX3_FWDWNLOAD_MEDIA_TYPE ; 127 | typedef enum { SUCCESS = 0, FAILED, INVALID_MEDIA_TYPE, INVALID_FWSIGNATURE, DEVICE_CREATE_FAILED, INCORRECT_IMAGE_LENGTH, INVALID_FILE, SPILASH_ERASE_FAILED, CORRUPT_FIRMWARE_IMAGE_FILE,I2CE2PROM_UNKNOWN_I2C_SIZE } FX3_FWDWNLOAD_ERROR_CODE; 128 | 129 | #define CYWB_BL_4_BYTES_COPY(destination,source) {memcpy((void *)(destination), (void *)(source), 4);} 130 | 131 | /******************************************************************************** 132 | * 133 | * The CCyEndPoint ABSTRACT Class 134 | * 135 | ********************************************************************************/ 136 | class CCyUSBEndPoint 137 | { 138 | protected: 139 | bool WaitForIO(OVERLAPPED *ovLapStatus); 140 | 141 | virtual PUCHAR BeginDirectXfer(PUCHAR buf, LONG bufLen, OVERLAPPED *ov); 142 | virtual PUCHAR BeginBufferedXfer(PUCHAR buf, LONG bufLen, OVERLAPPED *ov); 143 | 144 | public: 145 | 146 | CCyUSBEndPoint(void); 147 | CCyUSBEndPoint(CCyUSBEndPoint& ept); 148 | CCyUSBEndPoint(HANDLE h, PUSB_ENDPOINT_DESCRIPTOR pEndPtDescriptor); 149 | CCyUSBEndPoint(HANDLE hDev, PUSB_ENDPOINT_DESCRIPTOR pEndPtDescriptor,USB_SUPERSPEED_ENDPOINT_COMPANION_DESCRIPTOR* SSEndPtDescriptor); 150 | 151 | HANDLE hDevice; 152 | 153 | /* The fields of an EndPoint Descriptor */ 154 | UCHAR DscLen; 155 | UCHAR DscType; 156 | UCHAR Address; 157 | UCHAR Attributes; 158 | USHORT MaxPktSize; 159 | USHORT PktsPerFrame; 160 | UCHAR Interval; 161 | /* This are the fields for Super speed endpoint */ 162 | UCHAR ssdscLen; 163 | UCHAR ssdscType; 164 | UCHAR ssmaxburst; /* Maximum number of packets endpoint can send in one burst */ 165 | UCHAR ssbmAttribute; /* store endpoint attribute like for bulk it will be number of streams */ 166 | USHORT ssbytesperinterval; 167 | 168 | /* Other fields */ 169 | ULONG TimeOut; 170 | ULONG UsbdStatus; 171 | ULONG NtStatus; 172 | 173 | DWORD bytesWritten; 174 | DWORD LastError; 175 | bool bIn; 176 | 177 | XFER_MODE_TYPE XferMode; 178 | 179 | bool XferData(PUCHAR buf, LONG &len, CCyIsoPktInfo* pktInfos = NULL); 180 | bool XferData(PUCHAR buf, LONG &bufLen, CCyIsoPktInfo* pktInfos, bool pktMode); 181 | virtual PUCHAR BeginDataXfer(PUCHAR buf, LONG len, OVERLAPPED *ov) = 0; 182 | virtual bool FinishDataXfer(PUCHAR buf, LONG &len, OVERLAPPED *ov, PUCHAR pXmitBuf, CCyIsoPktInfo* pktInfos = NULL); 183 | bool WaitForXfer(OVERLAPPED *ov, ULONG tOut); 184 | ULONG GetXferSize(void); 185 | void SetXferSize(ULONG xfer); 186 | 187 | bool Reset(void); 188 | bool Abort(void); 189 | }; 190 | 191 | 192 | /******************************************************************************** 193 | * 194 | * The Control Endpoint Class 195 | * 196 | ********************************************************************************/ 197 | class CCyControlEndPoint : public CCyUSBEndPoint 198 | { 199 | public: 200 | CCyControlEndPoint(void); 201 | CCyControlEndPoint(CCyControlEndPoint& ept); 202 | CCyControlEndPoint(HANDLE h, PUSB_ENDPOINT_DESCRIPTOR pEndPtDescriptor); 203 | 204 | CTL_XFER_TGT_TYPE Target; 205 | CTL_XFER_REQ_TYPE ReqType; 206 | CTL_XFER_DIR_TYPE Direction; 207 | 208 | UCHAR ReqCode; 209 | WORD Value; 210 | WORD Index; 211 | 212 | bool Read(PUCHAR buf, LONG &len); 213 | bool Write(PUCHAR buf, LONG &len); 214 | PUCHAR BeginDataXfer(PUCHAR buf, LONG len, OVERLAPPED *ov); 215 | }; 216 | 217 | 218 | /******************************************************************************** 219 | * 220 | * The Isoc Endpoint Class 221 | * 222 | ********************************************************************************/ 223 | class CCyIsocEndPoint : public CCyUSBEndPoint 224 | { 225 | 226 | protected: 227 | virtual PUCHAR BeginDirectXfer(PUCHAR buf, LONG bufLen, OVERLAPPED *ov); 228 | virtual PUCHAR BeginBufferedXfer(PUCHAR buf, LONG bufLen, OVERLAPPED *ov); 229 | 230 | public: 231 | CCyIsocEndPoint(void); 232 | CCyIsocEndPoint(HANDLE h, PUSB_ENDPOINT_DESCRIPTOR pEndPtDescriptor); 233 | CCyIsocEndPoint(HANDLE h, PUSB_ENDPOINT_DESCRIPTOR pEndPtDescriptor,USB_SUPERSPEED_ENDPOINT_COMPANION_DESCRIPTOR* SSEndPtDescriptor); 234 | 235 | PUCHAR BeginDataXfer(PUCHAR buf, LONG len, OVERLAPPED *ov); 236 | CCyIsoPktInfo* CreatePktInfos(LONG bufLen, int &packets); 237 | }; 238 | 239 | 240 | /******************************************************************************** 241 | * 242 | * The Bulk Endpoint Class 243 | * 244 | ********************************************************************************/ 245 | class CCyBulkEndPoint : public CCyUSBEndPoint 246 | { 247 | public: 248 | CCyBulkEndPoint(void); 249 | CCyBulkEndPoint(HANDLE h, PUSB_ENDPOINT_DESCRIPTOR pEndPtDescriptor); 250 | CCyBulkEndPoint(HANDLE h, PUSB_ENDPOINT_DESCRIPTOR pEndPtDescriptor,USB_SUPERSPEED_ENDPOINT_COMPANION_DESCRIPTOR* SSEndPtDescriptor); 251 | 252 | PUCHAR BeginDataXfer(PUCHAR buf, LONG len, OVERLAPPED *ov); 253 | }; 254 | 255 | 256 | /******************************************************************************** 257 | * 258 | * The Interrupt Endpoint Class 259 | * 260 | ********************************************************************************/ 261 | class CCyInterruptEndPoint : public CCyUSBEndPoint 262 | { 263 | public: 264 | CCyInterruptEndPoint(void); 265 | CCyInterruptEndPoint(HANDLE h, PUSB_ENDPOINT_DESCRIPTOR pEndPtDescriptor); 266 | CCyInterruptEndPoint(HANDLE h, PUSB_ENDPOINT_DESCRIPTOR pEndPtDescriptor,USB_SUPERSPEED_ENDPOINT_COMPANION_DESCRIPTOR* SSEndPtDescriptor); 267 | 268 | PUCHAR BeginDataXfer(PUCHAR buf, LONG len, OVERLAPPED *ov); 269 | }; 270 | 271 | 272 | /******************************************************************************** 273 | * 274 | * The Interface Class 275 | * 276 | ********************************************************************************/ 277 | class CCyUSBInterface 278 | { 279 | public: 280 | CCyUSBEndPoint *EndPoints[MAX_ENDPTS]; /* Holds pointers to all the interface's endpoints, 281 | plus a pointer to the Control endpoint zero */ 282 | UCHAR bLength; 283 | UCHAR bDescriptorType; 284 | UCHAR bInterfaceNumber; 285 | UCHAR bAlternateSetting; 286 | UCHAR bNumEndpoints; /* Not counting the control endpoint */ 287 | UCHAR bInterfaceClass; 288 | UCHAR bInterfaceSubClass; 289 | UCHAR bInterfaceProtocol; 290 | UCHAR iInterface; 291 | 292 | UCHAR bAltSettings; 293 | USHORT wTotalLength; /* Needed in case Intfc has additional (non-endpt) descriptors */ 294 | 295 | CCyUSBInterface(HANDLE handle, PUSB_INTERFACE_DESCRIPTOR pIntfcDescriptor,UCHAR usb30Dummy); 296 | CCyUSBInterface(HANDLE h, PUSB_INTERFACE_DESCRIPTOR pIntfcDescriptor); 297 | CCyUSBInterface(CCyUSBInterface& ifc); /* Copy Constructor */ 298 | ~CCyUSBInterface(void); 299 | 300 | }; 301 | 302 | 303 | /******************************************************************************** 304 | * 305 | * The Config Class 306 | * 307 | ********************************************************************************/ 308 | class CCyUSBConfig 309 | { 310 | public: 311 | CCyUSBInterface *Interfaces[MAX_INTERFACES]; 312 | 313 | UCHAR bLength; 314 | UCHAR bDescriptorType; 315 | USHORT wTotalLength; 316 | UCHAR bNumInterfaces; 317 | UCHAR bConfigurationValue; 318 | UCHAR iConfiguration; 319 | UCHAR bmAttributes; 320 | UCHAR MaxPower; 321 | 322 | UCHAR AltInterfaces; 323 | 324 | CCyUSBConfig(void); 325 | CCyUSBConfig(CCyUSBConfig& cfg); /* Copy Constructor */ 326 | CCyUSBConfig(HANDLE h, PUSB_CONFIGURATION_DESCRIPTOR pConfigDescr); 327 | CCyUSBConfig(HANDLE h, PUSB_CONFIGURATION_DESCRIPTOR pConfigDescr,UCHAR usb30Dummy); 328 | ~CCyUSBConfig(void); 329 | }; 330 | 331 | 332 | /******************************************************************************** 333 | * 334 | * The Bos USB20 Extesnion Class 335 | * 336 | ********************************************************************************/ 337 | class CCyBosUSB20Extesnion 338 | { 339 | public: 340 | UCHAR bLength; /* Descriptor length */ 341 | UCHAR bDescriptorType; /* Descriptor Type */ 342 | UCHAR bDevCapabilityType; /* Device capability type */ 343 | UINT bmAttribute; /* Bitmap encoding for supprted feature and Link power managment supprted if set */ 344 | 345 | CCyBosUSB20Extesnion(void); 346 | CCyBosUSB20Extesnion(HANDLE h,PUSB_BOS_USB20_DEVICE_EXTENSION BosUsb20ExtDesc); 347 | }; 348 | 349 | 350 | /******************************************************************************** 351 | * 352 | * The Bos SuperSpeed Capability Class 353 | * 354 | ********************************************************************************/ 355 | class CCyBosSuperSpeedCapability 356 | { 357 | public: 358 | UCHAR bLength; 359 | UCHAR bDescriptorType; 360 | UCHAR bDevCapabilityType; 361 | UCHAR bmAttribute; 362 | USHORT SpeedsSuported; 363 | UCHAR bFunctionalitySupporte; 364 | UCHAR bU1DevExitLat; 365 | USHORT bU2DevExitLat; 366 | 367 | CCyBosSuperSpeedCapability(void); 368 | CCyBosSuperSpeedCapability(HANDLE h,PUSB_BOS_SS_DEVICE_CAPABILITY pUSB_SuperSpeedUsb); 369 | 370 | }; 371 | 372 | 373 | /******************************************************************************** 374 | * 375 | * The Bos Container ID Class 376 | * 377 | ********************************************************************************/ 378 | class CCyBosContainerID 379 | { 380 | public: 381 | UCHAR bLength; /* Descriptor length */ 382 | UCHAR bDescriptorType; /* Descriptor Type */ 383 | UCHAR bDevCapabilityType; /* Device capability type */ 384 | UCHAR bReserved; /* no use */ 385 | UCHAR ContainerID[USB_BOS_CAPABILITY_TYPE_CONTAINER_ID_SIZE]; /* UUID */ 386 | 387 | CCyBosContainerID(void); 388 | CCyBosContainerID(HANDLE h,PUSB_BOS_CONTAINER_ID pContainerID); 389 | }; 390 | 391 | 392 | /******************************************************************************** 393 | * 394 | * The USB BOS Class 395 | * 396 | ********************************************************************************/ 397 | class CCyUSBBOS 398 | { 399 | public: 400 | 401 | CCyBosContainerID *pContainer_ID; 402 | CCyBosUSB20Extesnion *pUSB20_DeviceExt; 403 | CCyBosSuperSpeedCapability *pSS_DeviceCap; 404 | 405 | UCHAR bLength; /* Descriptor length */ 406 | UCHAR bDescriptorType; /* Descriptor Type */ 407 | USHORT wTotalLength; /* Total length of descriptor ( icluding device capabilty */ 408 | UCHAR bNumDeviceCaps; /* Number of device capability descriptors in BOS */ 409 | 410 | CCyUSBBOS(void); 411 | CCyUSBBOS(HANDLE h,PUSB_BOS_DESCRIPTOR pBosDescrData); 412 | ~CCyUSBBOS(); 413 | }; 414 | 415 | /********************************************************************************* 416 | * 417 | * The USB Device Class - This is the main class that contains members of all the 418 | * other classes. 419 | * 420 | * To use the library, create an instance of this Class and call it's Open method. 421 | * 422 | *********************************************************************************/ 423 | class CCyUSBDevice 424 | { 425 | /* The public members are accessible (i.e. corruptible) by the user of the library 426 | * Algorithms of the class don't rely on any public members. Instead, they use the 427 | * private members of the class for their calculations. */ 428 | 429 | public: 430 | 431 | CCyUSBDevice(HANDLE hnd = NULL, GUID guid = CYUSBDRV_GUID, BOOL bOpen = true); 432 | ~CCyUSBDevice(void); 433 | 434 | CCyUSBEndPoint **EndPoints; /* Shortcut to USBCfgs[CfgNum]->Interfaces[IntfcIndex]->Endpoints */ 435 | CCyUSBEndPoint *EndPointOf(UCHAR addr); 436 | 437 | CCyUSBBOS *UsbBos; 438 | CCyIsocEndPoint *IsocInEndPt; 439 | CCyIsocEndPoint *IsocOutEndPt; 440 | CCyBulkEndPoint *BulkInEndPt; 441 | CCyBulkEndPoint *BulkOutEndPt; 442 | CCyControlEndPoint *ControlEndPt; 443 | CCyInterruptEndPoint *InterruptInEndPt; 444 | CCyInterruptEndPoint *InterruptOutEndPt; 445 | 446 | 447 | USHORT StrLangID; 448 | ULONG LastError; 449 | ULONG UsbdStatus; 450 | ULONG NtStatus; 451 | ULONG DriverVersion; 452 | ULONG USBDIVersion; 453 | char DeviceName[USB_STRING_MAXLEN]; 454 | char FriendlyName[USB_STRING_MAXLEN]; 455 | wchar_t Manufacturer[USB_STRING_MAXLEN]; 456 | wchar_t Product[USB_STRING_MAXLEN]; 457 | wchar_t SerialNumber[USB_STRING_MAXLEN]; 458 | 459 | CHAR DevPath[USB_STRING_MAXLEN]; 460 | 461 | USHORT BcdUSB; 462 | USHORT VendorID; 463 | USHORT ProductID; 464 | UCHAR USBAddress; 465 | UCHAR DevClass; 466 | UCHAR DevSubClass; 467 | UCHAR DevProtocol; 468 | INT MaxPacketSize; 469 | USHORT BcdDevice; 470 | 471 | UCHAR ConfigValue; 472 | UCHAR ConfigAttrib; 473 | UCHAR MaxPower; 474 | 475 | UCHAR IntfcClass; 476 | UCHAR IntfcSubClass; 477 | UCHAR IntfcProtocol; 478 | bool bHighSpeed; 479 | bool bSuperSpeed; 480 | 481 | DWORD BytesXfered; 482 | 483 | UCHAR DeviceCount(void); 484 | UCHAR ConfigCount(void); 485 | UCHAR IntfcCount(void); 486 | UCHAR AltIntfcCount(void); 487 | UCHAR EndPointCount(void); 488 | 489 | void SetConfig(UCHAR cfg); 490 | UCHAR Config(void) { return CfgNum; } /* Normally 0 */ 491 | UCHAR Interface(void) { return IntfcNum; } /* Usually 0 */ 492 | 493 | /* No SetInterface method since only 1 intfc per device (per Windows) */ 494 | UCHAR AltIntfc(void); 495 | bool SetAltIntfc(UCHAR alt); 496 | 497 | GUID DriverGUID(void) { return DrvGuid; } 498 | HANDLE DeviceHandle(void) { return hDevice; } 499 | void UsbdStatusString(ULONG stat, PCHAR s); 500 | bool CreateHandle(UCHAR dev); 501 | void DestroyHandle(); 502 | 503 | bool Open(UCHAR dev); 504 | void Close(void); 505 | bool Reset(void); 506 | bool ReConnect(void); 507 | bool Suspend(void); 508 | bool Resume(void); 509 | bool IsOpen(void) { return (hDevice != INVALID_HANDLE_VALUE); } 510 | 511 | UCHAR PowerState(void); 512 | 513 | bool GetBosDescriptor(PUSB_BOS_DESCRIPTOR descr); 514 | bool GetBosUSB20DeviceExtensionDescriptor(PUSB_BOS_USB20_DEVICE_EXTENSION descr); 515 | bool GetBosContainedIDDescriptor(PUSB_BOS_CONTAINER_ID descr); 516 | bool GetBosSSCapabilityDescriptor(PUSB_BOS_SS_DEVICE_CAPABILITY descr); 517 | 518 | void GetDeviceDescriptor(PUSB_DEVICE_DESCRIPTOR descr); 519 | void GetConfigDescriptor(PUSB_CONFIGURATION_DESCRIPTOR descr); 520 | void GetIntfcDescriptor(PUSB_INTERFACE_DESCRIPTOR descr); 521 | CCyUSBConfig GetUSBConfig(int index); 522 | 523 | private: 524 | 525 | USB_DEVICE_DESCRIPTOR USBDeviceDescriptor; 526 | PUSB_CONFIGURATION_DESCRIPTOR USBConfigDescriptors[2]; 527 | PUSB_BOS_DESCRIPTOR pUsbBosDescriptor; 528 | 529 | CCyUSBConfig *USBCfgs[2]; 530 | 531 | HANDLE hWnd; 532 | HANDLE hDevice; 533 | HANDLE hDevNotification; 534 | HANDLE hHndNotification; 535 | 536 | GUID DrvGuid; 537 | 538 | UCHAR Devices; 539 | UCHAR Interfaces; 540 | UCHAR AltInterfaces; 541 | UCHAR Configs; 542 | 543 | UCHAR DevNum; 544 | UCHAR CfgNum; 545 | UCHAR IntfcNum; /* The current selected interface's bInterfaceNumber */ 546 | UCHAR IntfcIndex; /* The entry in the Config's interfaces table matching to IntfcNum and AltSetting */ 547 | 548 | bool GetInternalBosDescriptor(); 549 | void GetDevDescriptor(void); 550 | void GetCfgDescriptor(int descIndex); 551 | void GetString(wchar_t *s, UCHAR sIndex); 552 | void SetStringDescrLanguage(void); 553 | void SetAltIntfcParams(UCHAR alt); 554 | bool IoControl(ULONG cmd, PUCHAR buf, ULONG len); 555 | 556 | void SetEndPointPtrs(void); 557 | void GetDeviceName(void); 558 | void GetFriendlyName(void); 559 | void GetDriverVer(void); 560 | void GetUSBDIVer(void); 561 | void GetSpeed(void); 562 | void GetUSBAddress(void); 563 | //void CloseEndPtHandles(void); 564 | 565 | bool RegisterForPnpEvents(HANDLE h); 566 | }; 567 | 568 | 569 | /******************************************************************************** 570 | * 571 | * The FX3 Device Class 572 | * 573 | ********************************************************************************/ 574 | class CCyFX3Device: public CCyUSBDevice 575 | { 576 | public: 577 | CCyFX3Device(void); 578 | ~CCyFX3Device(void); 579 | bool IsBootLoaderRunning(); 580 | FX3_FWDWNLOAD_ERROR_CODE DownloadFw(char *fileName, FX3_FWDWNLOAD_MEDIA_TYPE enMediaType); 581 | 582 | private: 583 | 584 | bool Ep0VendorCommand(vendorCmdData cmdData); 585 | bool SetProgramEntry(UCHAR opCode,UINT start_addr); 586 | 587 | bool DownloadBufferToDevice(UINT start_addr, USHORT count, UCHAR *data_buf, UCHAR opCode); 588 | bool UploadBufferFromDevice(UINT start_addr, USHORT count, UCHAR *data_buf, UCHAR opCode); 589 | 590 | FX3_FWDWNLOAD_ERROR_CODE DownloadFwToRam(PUCHAR buffer_p, UINT fw_size, UCHAR opCode); 591 | FX3_FWDWNLOAD_ERROR_CODE DownloadUserIMGtoI2CE2PROM(PUCHAR buffer_p, UINT fw_size, UCHAR opCode); 592 | FX3_FWDWNLOAD_ERROR_CODE DownloadUserIMGtoSPIFLASH(PUCHAR buffer_p, UINT fw_size, UCHAR opCode); 593 | 594 | FX3_FWDWNLOAD_ERROR_CODE EraseSectorOfSPIFlash(UINT SectorNumber, UCHAR opCode); 595 | bool WriteToSPIFlash(PUCHAR Buf, UINT buflen, UINT ByteAddress, UCHAR opCode); 596 | }; 597 | 598 | /********************************************************************************/ 599 | 600 | #endif -------------------------------------------------------------------------------- /ExtIO_sddc/library/inc/CyUSB30_def.h: -------------------------------------------------------------------------------- 1 | /* 2 | ## Cypress CyAPI C++ library USB3.0 defination header file (CyUSB30_def.h) 3 | ## ======================================================= 4 | ## 5 | ## Copyright Cypress Semiconductor Corporation, 2009-2012, 6 | ## All Rights Reserved 7 | ## UNPUBLISHED, LICENSED SOFTWARE. 8 | ## 9 | ## CONFIDENTIAL AND PROPRIETARY INFORMATION 10 | ## WHICH IS THE PROPERTY OF CYPRESS. 11 | ## 12 | ## Use of this file is governed 13 | ## by the license agreement included in the file 14 | ## 15 | ## /license/license.rtf 16 | ## 17 | ## where is the Cypress software 18 | ## install root directory path. 19 | ## 20 | ## ======================================================= 21 | */ 22 | #ifndef _CYUSB30_H 23 | #define _CYUSB30_H 24 | 25 | //#pragma pack(1) 26 | #pragma pack(push, 1) 27 | // USB3.0 specific constant defination 28 | #define BCDUSBJJMASK 0xFF00 //(0xJJMN JJ - Major version,M Minor version, N sub-minor vesion) 29 | #define USB30MAJORVER 0x0300 30 | #define USB20MAJORVER 0x0200 31 | 32 | #define USB_BOS_DESCRIPTOR_TYPE 0x0F 33 | #define USB_DEVICE_CAPABILITY 0x10 34 | #define USB_SUPERSPEED_ENDPOINT_COMPANION 0x30 35 | #define USB_BOS_CAPABILITY_TYPE_Wireless_USB 0x01 36 | #define USB_BOS_CAPABILITY_TYPE_USB20_EXT 0x02 37 | #define USB_BOS_CAPABILITY_TYPE_SUPERSPEED_USB 0x03 38 | #define USB_BOS_CAPABILITY_TYPE_CONTAINER_ID 0x04 39 | #define USB_BOS_CAPABILITY_TYPE_CONTAINER_ID_SIZE 0x10 40 | 41 | #define USB_BOS_DEVICE_CAPABILITY_TYPE_INDEX 0x2 42 | //constant defination 43 | typedef struct _USB_BOS_DESCRIPTOR 44 | { 45 | UCHAR bLength;/* Descriptor length*/ 46 | UCHAR bDescriptorType;/* Descriptor Type */ 47 | USHORT wTotalLength;/* Total length of descriptor ( icluding device capability*/ 48 | UCHAR bNumDeviceCaps;/* Number of device capability descriptors in BOS */ 49 | }USB_BOS_DESCRIPTOR,*PUSB_BOS_DESCRIPTOR; 50 | 51 | typedef struct _USB_BOS_USB20_DEVICE_EXTENSION 52 | { 53 | UCHAR bLength;/* Descriptor length*/ 54 | UCHAR bDescriptorType;/* Descriptor Type */ 55 | UCHAR bDevCapabilityType;/* Device capability type*/ 56 | UINT bmAttribute;// Bitmap encoding for supprted feature and Link power managment supprted if set 57 | }USB_BOS_USB20_DEVICE_EXTENSION,*PUSB_BOS_USB20_DEVICE_EXTENSION; 58 | 59 | typedef struct _USB_BOS_SS_DEVICE_CAPABILITY 60 | { 61 | UCHAR bLength;/* Descriptor length*/ 62 | UCHAR bDescriptorType;/* Descriptor Type */ 63 | UCHAR bDevCapabilityType;/* Device capability type*/ 64 | UCHAR bmAttribute;// Bitmap encoding for supprted feature and Link power managment supprted if set 65 | USHORT wSpeedsSuported;//low speed supported if set,full speed supported if set,high speed supported if set,super speed supported if set,15:4 nt used 66 | UCHAR bFunctionalitySupporte; 67 | UCHAR bU1DevExitLat;//U1 device exit latency 68 | USHORT bU2DevExitLat;//U2 device exit latency 69 | }USB_BOS_SS_DEVICE_CAPABILITY,*PUSB_BOS_SS_DEVICE_CAPABILITY; 70 | 71 | typedef struct _USB_BOS_CONTAINER_ID 72 | { 73 | UCHAR bLength;/* Descriptor length*/ 74 | UCHAR bDescriptorType;/* Descriptor Type */ 75 | UCHAR bDevCapabilityType;/* Device capability type*/ 76 | UCHAR bReserved; // no use 77 | UCHAR ContainerID[USB_BOS_CAPABILITY_TYPE_CONTAINER_ID_SIZE];/* UUID */ 78 | }USB_BOS_CONTAINER_ID,*PUSB_BOS_CONTAINER_ID; 79 | 80 | typedef struct _USB_SUPERSPEED_ENDPOINT_COMPANION_DESCRIPTOR 81 | { 82 | UCHAR bLength; 83 | UCHAR bDescriptorType; 84 | UCHAR bMaxBurst; 85 | UCHAR bmAttributes; 86 | USHORT bBytesPerInterval; 87 | }USB_SUPERSPEED_ENDPOINT_COMPANION_DESCRIPTOR,*PUSB_SUPERSPEED_ENDPOINT_COMPANION_DESCRIPTOR; 88 | #pragma pack(pop) 89 | #endif /*_CYUSB30_H*/ 90 | 91 | -------------------------------------------------------------------------------- /ExtIO_sddc/library/inc/UsbdStatus.h: -------------------------------------------------------------------------------- 1 | 2 | // Note: see usbdi.h in the DDK for the USBD_STATUS source definitions 3 | typedef LONG USBD_STATUS; 4 | #define USBD_STATUS(Status) ((ULONG)(Status) & 0x0FFFFFFFL) 5 | #define USBD_STATE(Status) ((ULONG)(Status) & 0xF0000000L) 6 | 7 | // HC status codes (Note: both error and stall bit are set) 8 | #define USBD_STATUS_SUCCESS ((USBD_STATUS)0x00000000L) 9 | #define USBD_STATUS_PENDING ((USBD_STATUS)0x40000000L) 10 | #define USBD_STATUS_HALTED ((USBD_STATUS)0xC0000000L) 11 | #define USBD_STATUS_ERROR ((USBD_STATUS)0x80000000L) 12 | 13 | #define USBD_STATUS_CRC ((USBD_STATUS)0xC0000001L) 14 | #define USBD_STATUS_BTSTUFF ((USBD_STATUS)0xC0000002L) 15 | #define USBD_STATUS_DATA_TOGGLE_MISMATCH ((USBD_STATUS)0xC0000003L) 16 | #define USBD_STATUS_STALL_PID ((USBD_STATUS)0xC0000004L) 17 | #define USBD_STATUS_DEV_NOT_RESPONDING ((USBD_STATUS)0xC0000005L) 18 | #define USBD_STATUS_PID_CHECK_FAILURE ((USBD_STATUS)0xC0000006L) 19 | #define USBD_STATUS_UNEXPECTED_PID ((USBD_STATUS)0xC0000007L) 20 | #define USBD_STATUS_DATA_OVERRUN ((USBD_STATUS)0xC0000008L) 21 | #define USBD_STATUS_DATA_UNDERRUN ((USBD_STATUS)0xC0000009L) 22 | #define USBD_STATUS_RESERVED1 ((USBD_STATUS)0xC000000AL) 23 | #define USBD_STATUS_RESERVED2 ((USBD_STATUS)0xC000000BL) 24 | #define USBD_STATUS_BUFFER_OVERRUN ((USBD_STATUS)0xC000000CL) 25 | #define USBD_STATUS_BUFFER_UNDERRUN ((USBD_STATUS)0xC000000DL) 26 | #define USBD_STATUS_NOT_ACCESSED ((USBD_STATUS)0xC000000FL) 27 | #define USBD_STATUS_FIFO ((USBD_STATUS)0xC0000010L) 28 | 29 | #define USBD_STATUS_ENDPOINT_HALTED ((USBD_STATUS)0xC0000030L) 30 | #define USBD_STATUS_NO_MEMORY ((USBD_STATUS)0x80000100L) 31 | #define USBD_STATUS_INVALID_URB_FUNCTION ((USBD_STATUS)0x80000200L) 32 | #define USBD_STATUS_INVALID_PARAMETER ((USBD_STATUS)0x80000300L) 33 | #define USBD_STATUS_ERROR_BUSY ((USBD_STATUS)0x80000400L) 34 | #define USBD_STATUS_REQUEST_FAILED ((USBD_STATUS)0x80000500L) 35 | #define USBD_STATUS_INVALID_PIPE_HANDLE ((USBD_STATUS)0x80000600L) 36 | #define USBD_STATUS_NO_BANDWIDTH ((USBD_STATUS)0x80000700L) 37 | #define USBD_STATUS_INTERNAL_HC_ERROR ((USBD_STATUS)0x80000800L) 38 | #define USBD_STATUS_ERROR_SHORT_TRANSFER ((USBD_STATUS)0x80000900L) 39 | #define USBD_STATUS_BAD_START_FRAME ((USBD_STATUS)0xC0000A00L) 40 | #define USBD_STATUS_ISOCH_REQUEST_FAILED ((USBD_STATUS)0xC0000B00L) 41 | #define USBD_STATUS_FRAME_CONTROL_OWNED ((USBD_STATUS)0xC0000C00L) 42 | #define USBD_STATUS_FRAME_CONTROL_NOT_OWNED ((USBD_STATUS)0xC0000D00L) 43 | #define USBD_STATUS_CANCELED ((USBD_STATUS)0x00010000L) 44 | #define USBD_STATUS_CANCELING ((USBD_STATUS)0x00020000L) 45 | 46 | 47 | -------------------------------------------------------------------------------- /ExtIO_sddc/library/inc/VersionNo.h: -------------------------------------------------------------------------------- 1 | /* 2 | ## Cypress CyAPI C++ library version number header file (VersionNo.h) 3 | ## ======================================================= 4 | ## 5 | ## Copyright Cypress Semiconductor Corporation, 2009-2012, 6 | ## All Rights Reserved 7 | ## UNPUBLISHED, LICENSED SOFTWARE. 8 | ## 9 | ## CONFIDENTIAL AND PROPRIETARY INFORMATION 10 | ## WHICH IS THE PROPERTY OF CYPRESS. 11 | ## 12 | ## Use of this file is governed 13 | ## by the license agreement included in the file 14 | ## 15 | ## /license/license.rtf 16 | ## 17 | ## where is the Cypress software 18 | ## install root directory path. 19 | ## 20 | ## ======================================================= 21 | */ 22 | #define FILEVER 1,2,1,0 23 | #define PRODUCTVER 1,2,1,0 24 | #define STRFILEVER "1, 2, 1, 0" 25 | #define STRPRODUCTVER "1, 2, 1, 0" 26 | #define STRFILEVER_ASSENBLY "1.2.1.0" 27 | -------------------------------------------------------------------------------- /ExtIO_sddc/library/inc/cyioctl.h: -------------------------------------------------------------------------------- 1 | /* 2 | ## Cypress CyAPI C++ library IOCTL defination header file (cyioctl.h) 3 | ## ======================================================= 4 | ## 5 | ## Copyright Cypress Semiconductor Corporation, 2009-2012, 6 | ## All Rights Reserved 7 | ## UNPUBLISHED, LICENSED SOFTWARE. 8 | ## 9 | ## CONFIDENTIAL AND PROPRIETARY INFORMATION 10 | ## WHICH IS THE PROPERTY OF CYPRESS. 11 | ## 12 | ## Use of this file is governed 13 | ## by the license agreement included in the file 14 | ## 15 | ## /license/license.rtf 16 | ## 17 | ## where is the Cypress software 18 | ## install root directory path. 19 | ## 20 | ## ======================================================= 21 | */ 22 | #ifndef __IOCTL_H__ 23 | #define __IOCTL_H__ 24 | 25 | 26 | #ifndef DRIVER 27 | 28 | #ifndef CTL_CODE 29 | #include 30 | #endif 31 | 32 | #ifndef BM_REQUEST_TYPE 33 | #include "usb200.h" 34 | #endif 35 | 36 | #include 37 | 38 | #define DIR_HOST_TO_DEVICE 0 39 | #define DIR_DEVICE_TO_HOST 1 40 | 41 | #define DEVICE_SPEED_UNKNOWN 0x00000000 42 | #define DEVICE_SPEED_LOW_FULL 0x00000001 43 | #define DEVICE_SPEED_HIGH 0x00000002 44 | #define DEVICE_SPEED_SUPER 0x00000004 45 | 46 | typedef struct _WORD_SPLIT { 47 | UCHAR lowByte; 48 | UCHAR hiByte; 49 | } WORD_SPLIT, *PWORD_SPLIT; 50 | 51 | typedef struct _BM_REQ_TYPE { 52 | UCHAR Recipient:2; 53 | UCHAR Reserved:3; 54 | UCHAR Type:2; 55 | UCHAR Direction:1; 56 | } BM_REQ_TYPE, *PBM_REQ_TYPE; 57 | 58 | typedef struct _SETUP_PACKET { 59 | 60 | union { 61 | BM_REQ_TYPE bmReqType; 62 | UCHAR bmRequest; 63 | }; 64 | 65 | UCHAR bRequest; 66 | 67 | union { 68 | WORD_SPLIT wVal; 69 | USHORT wValue; 70 | }; 71 | 72 | union { 73 | WORD_SPLIT wIndx; 74 | USHORT wIndex; 75 | }; 76 | 77 | union { 78 | WORD_SPLIT wLen; 79 | USHORT wLength; 80 | }; 81 | 82 | ULONG ulTimeOut; 83 | 84 | } SETUP_PACKET, *PSETUP_PACKET; 85 | 86 | #define USB_ISO_ID 0x4945 87 | #define USB_ISO_CMD_ASAP 0x8000 88 | #define USB_ISO_CMD_CURRENT_FRAME 0x8001 89 | #define USB_ISO_CMD_SET_FRAME 0x8002 90 | 91 | typedef struct _ISO_ADV_PARAMS { 92 | 93 | USHORT isoId; 94 | USHORT isoCmd; 95 | 96 | ULONG ulParam1; 97 | ULONG ulParam2; 98 | 99 | } ISO_ADV_PARAMS, *PISO_ADV_PARAMS; 100 | 101 | typedef struct _ISO_PACKET_INFO { 102 | ULONG Status; 103 | ULONG Length; 104 | } ISO_PACKET_INFO, *PISO_PACKET_INFO; 105 | 106 | 107 | typedef struct _SINGLE_TRANSFER { 108 | union { 109 | SETUP_PACKET SetupPacket; 110 | ISO_ADV_PARAMS IsoParams; 111 | }; 112 | 113 | UCHAR reserved; 114 | 115 | UCHAR ucEndpointAddress; 116 | ULONG NtStatus; 117 | ULONG UsbdStatus; 118 | ULONG IsoPacketOffset; 119 | ULONG IsoPacketLength; 120 | ULONG BufferOffset; 121 | ULONG BufferLength; 122 | } SINGLE_TRANSFER, *PSINGLE_TRANSFER; 123 | 124 | #endif // #ifndef DRIVER 125 | 126 | typedef struct _SET_TRANSFER_SIZE_INFO { 127 | UCHAR EndpointAddress; 128 | ULONG TransferSize; 129 | } SET_TRANSFER_SIZE_INFO, *PSET_TRANSFER_SIZE_INFO; 130 | 131 | 132 | // 133 | // Macro to extract function out of the device io control code 134 | // 135 | #ifdef WIN_98_DDK 136 | #define DEVICE_TYPE_FROM_CTL_CODE(ctrlCode) (((ULONG)(ctrlCode & 0xffff0000)) >> 16) 137 | #endif 138 | #define FUNCTION_FROM_CTL_CODE(ctrlCode) (((ULONG)(ctrlCode & 0x00003FFC)) >> 2) 139 | #define ACCESS_FROM_CTL_CODE(ctrlCode) (((ULONG)(ctrlCode & 0x000C0000)) >> 14) 140 | //#define METHOD_FROM_CTL_CODE(ctrlCode) (((ULONG)(ctrlCode & 0x00000003))) 141 | 142 | 143 | #define IOCTL_ADAPT_INDEX 0x0000 144 | 145 | // Get the driver version 146 | #define IOCTL_ADAPT_GET_DRIVER_VERSION CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX, METHOD_BUFFERED, FILE_ANY_ACCESS) 147 | 148 | // Get the current USBDI version 149 | #define IOCTL_ADAPT_GET_USBDI_VERSION CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+1, METHOD_BUFFERED, FILE_ANY_ACCESS) 150 | 151 | // Get the current device alt interface settings from driver 152 | #define IOCTL_ADAPT_GET_ALT_INTERFACE_SETTING CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+2, METHOD_BUFFERED, FILE_ANY_ACCESS) 153 | 154 | // Set the device interface and alt interface setting 155 | #define IOCTL_ADAPT_SELECT_INTERFACE CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+3, METHOD_BUFFERED, FILE_ANY_ACCESS) 156 | 157 | // Get device address from driver 158 | #define IOCTL_ADAPT_GET_ADDRESS CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+4, METHOD_BUFFERED, FILE_ANY_ACCESS) 159 | 160 | // Get number of endpoints for current interface and alt interface setting from driver 161 | #define IOCTL_ADAPT_GET_NUMBER_ENDPOINTS CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+5, METHOD_BUFFERED, FILE_ANY_ACCESS) 162 | 163 | // Get the current device power state 164 | #define IOCTL_ADAPT_GET_DEVICE_POWER_STATE CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+6, METHOD_BUFFERED, FILE_ANY_ACCESS) 165 | 166 | // Set the device power state 167 | #define IOCTL_ADAPT_SET_DEVICE_POWER_STATE CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+7, METHOD_BUFFERED, FILE_ANY_ACCESS) 168 | 169 | // Send a raw packet to endpoint 0 170 | #define IOCTL_ADAPT_SEND_EP0_CONTROL_TRANSFER CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+8, METHOD_BUFFERED, FILE_ANY_ACCESS) 171 | 172 | // Send/receive data to/from nonep0 173 | #define IOCTL_ADAPT_SEND_NON_EP0_TRANSFER CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+9, METHOD_BUFFERED, FILE_ANY_ACCESS) 174 | 175 | // Simulate a disconnect/reconnect 176 | #define IOCTL_ADAPT_CYCLE_PORT CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+10, METHOD_BUFFERED, FILE_ANY_ACCESS) 177 | 178 | // Reset the pipe 179 | #define IOCTL_ADAPT_RESET_PIPE CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+11, METHOD_BUFFERED, FILE_ANY_ACCESS) 180 | 181 | // Reset the device 182 | #define IOCTL_ADAPT_RESET_PARENT_PORT CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+12, METHOD_BUFFERED, FILE_ANY_ACCESS) 183 | 184 | // Get the current transfer size of an endpoint (in number of bytes) 185 | #define IOCTL_ADAPT_GET_TRANSFER_SIZE CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+13, METHOD_BUFFERED, FILE_ANY_ACCESS) 186 | 187 | // Set the transfer size of an endpoint (in number of bytes) 188 | #define IOCTL_ADAPT_SET_TRANSFER_SIZE CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+14, METHOD_BUFFERED, FILE_ANY_ACCESS) 189 | 190 | // Return the name of the device 191 | #define IOCTL_ADAPT_GET_DEVICE_NAME CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+15, METHOD_BUFFERED, FILE_ANY_ACCESS) 192 | 193 | // Return the "Friendly Name" of the device 194 | #define IOCTL_ADAPT_GET_FRIENDLY_NAME CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+16, METHOD_BUFFERED, FILE_ANY_ACCESS) 195 | 196 | // Abort all outstanding transfers on the pipe 197 | #define IOCTL_ADAPT_ABORT_PIPE CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+17, METHOD_BUFFERED, FILE_ANY_ACCESS) 198 | 199 | // Send/receive data to/from nonep0 w/ direct buffer acccess (no buffering) 200 | #define IOCTL_ADAPT_SEND_NON_EP0_DIRECT CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+18, METHOD_NEITHER, FILE_ANY_ACCESS) 201 | 202 | // Return device speed 203 | #define IOCTL_ADAPT_GET_DEVICE_SPEED CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+19, METHOD_BUFFERED, FILE_ANY_ACCESS) 204 | 205 | // Get the current USB frame number 206 | #define IOCTL_ADAPT_GET_CURRENT_FRAME CTL_CODE(FILE_DEVICE_UNKNOWN, IOCTL_ADAPT_INDEX+20, METHOD_BUFFERED, FILE_ANY_ACCESS) 207 | 208 | #define NUMBER_OF_ADAPT_IOCTLS 21 // Last IOCTL_ADAPT_INDEX + 1 209 | 210 | 211 | #include 212 | 213 | #endif // __IOCTL_H__ 214 | -------------------------------------------------------------------------------- /ExtIO_sddc/library/inc/usb100.h: -------------------------------------------------------------------------------- 1 | #ifndef __USB100_H__ 2 | #define __USB100_H__ 3 | 4 | 5 | #include 6 | 7 | 8 | //bmRequest.Dir 9 | #define BMREQUEST_HOST_TO_DEVICE 0 10 | #define BMREQUEST_DEVICE_TO_HOST 1 11 | 12 | //bmRequest.Type 13 | #define BMREQUEST_STANDARD 0 14 | #define BMREQUEST_CLASS 1 15 | #define BMREQUEST_VENDOR 2 16 | 17 | //bmRequest.Recipient 18 | #define BMREQUEST_TO_DEVICE 0 19 | #define BMREQUEST_TO_INTERFACE 1 20 | #define BMREQUEST_TO_ENDPOINT 2 21 | #define BMREQUEST_TO_OTHER 3 22 | 23 | 24 | #define MAXIMUM_USB_STRING_LENGTH 255 25 | 26 | // values for the bits returned by the USB GET_STATUS command 27 | #define USB_GETSTATUS_SELF_POWERED 0x01 28 | #define USB_GETSTATUS_REMOTE_WAKEUP_ENABLED 0x02 29 | 30 | 31 | #define USB_DEVICE_DESCRIPTOR_TYPE 0x01 32 | #define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 33 | #define USB_STRING_DESCRIPTOR_TYPE 0x03 34 | #define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 35 | #define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 36 | 37 | // descriptor types defined by DWG documents 38 | #define USB_RESERVED_DESCRIPTOR_TYPE 0x06 39 | #define USB_CONFIG_POWER_DESCRIPTOR_TYPE 0x07 40 | #define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 0x08 41 | 42 | #define USB_DESCRIPTOR_MAKE_TYPE_AND_INDEX(d, i) ((USHORT)((USHORT)d<<8 | i)) 43 | 44 | // 45 | // Values for bmAttributes field of an 46 | // endpoint descriptor 47 | // 48 | 49 | #define USB_ENDPOINT_TYPE_MASK 0x03 50 | 51 | #define USB_ENDPOINT_TYPE_CONTROL 0x00 52 | #define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 53 | #define USB_ENDPOINT_TYPE_BULK 0x02 54 | #define USB_ENDPOINT_TYPE_INTERRUPT 0x03 55 | 56 | 57 | // 58 | // definitions for bits in the bmAttributes field of a 59 | // configuration descriptor. 60 | // 61 | #define USB_CONFIG_POWERED_MASK 0xc0 62 | 63 | #define USB_CONFIG_BUS_POWERED 0x80 64 | #define USB_CONFIG_SELF_POWERED 0x40 65 | #define USB_CONFIG_REMOTE_WAKEUP 0x20 66 | 67 | // 68 | // Endpoint direction bit, stored in address 69 | // 70 | 71 | #define USB_ENDPOINT_DIRECTION_MASK 0x80 72 | 73 | // test direction bit in the bEndpointAddress field of 74 | // an endpoint descriptor. 75 | #define USB_ENDPOINT_DIRECTION_OUT(addr) (!((addr) & USB_ENDPOINT_DIRECTION_MASK)) 76 | #define USB_ENDPOINT_DIRECTION_IN(addr) ((addr) & USB_ENDPOINT_DIRECTION_MASK) 77 | 78 | // 79 | // USB defined request codes 80 | // see chapter 9 of the USB 1.0 specifcation for 81 | // more information. 82 | // 83 | 84 | // These are the correct values based on the USB 1.0 85 | // specification 86 | 87 | #define USB_REQUEST_GET_STATUS 0x00 88 | #define USB_REQUEST_CLEAR_FEATURE 0x01 89 | 90 | #define USB_REQUEST_SET_FEATURE 0x03 91 | 92 | #define USB_REQUEST_SET_ADDRESS 0x05 93 | #define USB_REQUEST_GET_DESCRIPTOR 0x06 94 | #define USB_REQUEST_SET_DESCRIPTOR 0x07 95 | #define USB_REQUEST_GET_CONFIGURATION 0x08 96 | #define USB_REQUEST_SET_CONFIGURATION 0x09 97 | #define USB_REQUEST_GET_INTERFACE 0x0A 98 | #define USB_REQUEST_SET_INTERFACE 0x0B 99 | #define USB_REQUEST_SYNC_FRAME 0x0C 100 | 101 | 102 | // 103 | // defined USB device classes 104 | // 105 | 106 | 107 | #define USB_DEVICE_CLASS_RESERVED 0x00 108 | #define USB_DEVICE_CLASS_AUDIO 0x01 109 | #define USB_DEVICE_CLASS_COMMUNICATIONS 0x02 110 | #define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03 111 | #define USB_DEVICE_CLASS_MONITOR 0x04 112 | #define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05 113 | #define USB_DEVICE_CLASS_POWER 0x06 114 | #define USB_DEVICE_CLASS_PRINTER 0x07 115 | #define USB_DEVICE_CLASS_STORAGE 0x08 116 | #define USB_DEVICE_CLASS_HUB 0x09 117 | #define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF 118 | 119 | // 120 | // USB Core defined Feature selectors 121 | // 122 | 123 | #define USB_FEATURE_ENDPOINT_STALL 0x0000 124 | #define USB_FEATURE_REMOTE_WAKEUP 0x0001 125 | 126 | // 127 | // USB DWG defined Feature selectors 128 | // 129 | 130 | #define USB_FEATURE_INTERFACE_POWER_D0 0x0002 131 | #define USB_FEATURE_INTERFACE_POWER_D1 0x0003 132 | #define USB_FEATURE_INTERFACE_POWER_D2 0x0004 133 | #define USB_FEATURE_INTERFACE_POWER_D3 0x0005 134 | 135 | typedef struct _USB_DEVICE_DESCRIPTOR { 136 | UCHAR bLength; 137 | UCHAR bDescriptorType; 138 | USHORT bcdUSB; 139 | UCHAR bDeviceClass; 140 | UCHAR bDeviceSubClass; 141 | UCHAR bDeviceProtocol; 142 | UCHAR bMaxPacketSize0; 143 | USHORT idVendor; 144 | USHORT idProduct; 145 | USHORT bcdDevice; 146 | UCHAR iManufacturer; 147 | UCHAR iProduct; 148 | UCHAR iSerialNumber; 149 | UCHAR bNumConfigurations; 150 | } USB_DEVICE_DESCRIPTOR, *PUSB_DEVICE_DESCRIPTOR; 151 | 152 | typedef struct _USB_ENDPOINT_DESCRIPTOR { 153 | UCHAR bLength; 154 | UCHAR bDescriptorType; 155 | UCHAR bEndpointAddress; 156 | UCHAR bmAttributes; 157 | USHORT wMaxPacketSize; 158 | UCHAR bInterval; 159 | } USB_ENDPOINT_DESCRIPTOR, *PUSB_ENDPOINT_DESCRIPTOR; 160 | 161 | typedef struct _USB_CONFIGURATION_DESCRIPTOR { 162 | UCHAR bLength; 163 | UCHAR bDescriptorType; 164 | USHORT wTotalLength; 165 | UCHAR bNumInterfaces; 166 | UCHAR bConfigurationValue; 167 | UCHAR iConfiguration; 168 | UCHAR bmAttributes; 169 | UCHAR MaxPower; 170 | } USB_CONFIGURATION_DESCRIPTOR, *PUSB_CONFIGURATION_DESCRIPTOR; 171 | 172 | typedef struct _USB_INTERFACE_DESCRIPTOR { 173 | UCHAR bLength; 174 | UCHAR bDescriptorType; 175 | UCHAR bInterfaceNumber; 176 | UCHAR bAlternateSetting; 177 | UCHAR bNumEndpoints; 178 | UCHAR bInterfaceClass; 179 | UCHAR bInterfaceSubClass; 180 | UCHAR bInterfaceProtocol; 181 | UCHAR iInterface; 182 | } USB_INTERFACE_DESCRIPTOR, *PUSB_INTERFACE_DESCRIPTOR; 183 | 184 | typedef struct _USB_STRING_DESCRIPTOR { 185 | UCHAR bLength; 186 | UCHAR bDescriptorType; 187 | WCHAR bString[1]; 188 | } USB_STRING_DESCRIPTOR, *PUSB_STRING_DESCRIPTOR; 189 | 190 | typedef struct _USB_COMMON_DESCRIPTOR { 191 | UCHAR bLength; 192 | UCHAR bDescriptorType; 193 | } USB_COMMON_DESCRIPTOR, *PUSB_COMMON_DESCRIPTOR; 194 | 195 | 196 | // 197 | // Standard USB HUB definitions 198 | // 199 | // See Chapter 11 USB core specification 200 | // 201 | 202 | typedef struct _USB_HUB_DESCRIPTOR { 203 | UCHAR bDescriptorLength; // Length of this descriptor 204 | UCHAR bDescriptorType; // Hub configuration type 205 | UCHAR bNumberOfPorts; // number of ports on this hub 206 | USHORT wHubCharacteristics; // Hub Charateristics 207 | UCHAR bPowerOnToPowerGood; // port power on till power good in 2ms 208 | UCHAR bHubControlCurrent; // max current in mA 209 | // 210 | // room for 255 ports power control and removable bitmask 211 | UCHAR bRemoveAndPowerMask[64]; 212 | } USB_HUB_DESCRIPTOR, *PUSB_HUB_DESCRIPTOR; 213 | 214 | 215 | // 216 | // Structures defined by various DWG feature documents 217 | // 218 | 219 | 220 | // 221 | // See DWG USB Feature Specification: Interface Power Management 222 | // 223 | 224 | #define USB_SUPPORT_D0_COMMAND 0x01 225 | #define USB_SUPPORT_D1_COMMAND 0x02 226 | #define USB_SUPPORT_D2_COMMAND 0x04 227 | #define USB_SUPPORT_D3_COMMAND 0x08 228 | 229 | #define USB_SUPPORT_D1_WAKEUP 0x10 230 | #define USB_SUPPORT_D2_WAKEUP 0x20 231 | 232 | 233 | typedef struct _USB_CONFIGURATION_POWER_DESCRIPTOR { 234 | UCHAR bLength; 235 | UCHAR bDescriptorType; 236 | UCHAR SelfPowerConsumedD0[3]; 237 | UCHAR bPowerSummaryId; 238 | UCHAR bBusPowerSavingD1; 239 | UCHAR bSelfPowerSavingD1; 240 | UCHAR bBusPowerSavingD2; 241 | UCHAR bSelfPowerSavingD2; 242 | UCHAR bBusPowerSavingD3; 243 | UCHAR bSelfPowerSavingD3; 244 | USHORT TransitionTimeFromD1; 245 | USHORT TransitionTimeFromD2; 246 | USHORT TransitionTimeFromD3; 247 | } USB_CONFIGURATION_POWER_DESCRIPTOR, *PUSB_CONFIGURATION_POWER_DESCRIPTOR; 248 | 249 | 250 | typedef struct _USB_INTERFACE_POWER_DESCRIPTOR { 251 | UCHAR bLength; 252 | UCHAR bDescriptorType; 253 | UCHAR bmCapabilitiesFlags; 254 | UCHAR bBusPowerSavingD1; 255 | UCHAR bSelfPowerSavingD1; 256 | UCHAR bBusPowerSavingD2; 257 | UCHAR bSelfPowerSavingD2; 258 | UCHAR bBusPowerSavingD3; 259 | UCHAR bSelfPowerSavingD3; 260 | USHORT TransitionTimeFromD1; 261 | USHORT TransitionTimeFromD2; 262 | USHORT TransitionTimeFromD3; 263 | } USB_INTERFACE_POWER_DESCRIPTOR, *PUSB_INTERFACE_POWER_DESCRIPTOR; 264 | 265 | 266 | #include 267 | 268 | 269 | #endif /* __USB100_H__ */ 270 | 271 | -------------------------------------------------------------------------------- /ExtIO_sddc/library/inc/usb200.h: -------------------------------------------------------------------------------- 1 | #ifndef __USB200_H__ 2 | #define __USB200_H__ 3 | 4 | #include "usb100.h" 5 | 6 | 7 | #include 8 | 9 | typedef enum _USB_DEVICE_SPEED { 10 | UsbLowSpeed = 0, 11 | UsbFullSpeed, 12 | UsbHighSpeed 13 | } USB_DEVICE_SPEED; 14 | 15 | typedef enum _USB_DEVICE_TYPE { 16 | Usb11Device = 0, 17 | Usb20Device 18 | } USB_DEVICE_TYPE; 19 | 20 | // standard definiions for the port status 21 | // word of the HUB port register 22 | 23 | #define USB_PORT_STATUS_CONNECT 0x0001 24 | #define USB_PORT_STATUS_ENABLE 0x0002 25 | #define USB_PORT_STATUS_SUSPEND 0x0004 26 | #define USB_PORT_STATUS_OVER_CURRENT 0x0008 27 | #define USB_PORT_STATUS_RESET 0x0010 28 | #define USB_PORT_STATUS_POWER 0x0100 29 | #define USB_PORT_STATUS_LOW_SPEED 0x0200 30 | #define USB_PORT_STATUS_HIGH_SPEED 0x0400 31 | 32 | typedef union _BM_REQUEST_TYPE { 33 | struct _BM { 34 | UCHAR Recipient:2; 35 | UCHAR Reserved:3; 36 | UCHAR Type:2; 37 | UCHAR Dir:1; 38 | }; 39 | UCHAR B; 40 | } BM_REQUEST_TYPE, *PBM_REQUEST_TYPE; 41 | 42 | typedef struct _USB_DEFAULT_PIPE_SETUP_PACKET { 43 | BM_REQUEST_TYPE bmRequestType; 44 | UCHAR bRequest; 45 | 46 | union _wValue { 47 | struct { 48 | UCHAR LowByte; 49 | UCHAR HiByte; 50 | }; 51 | USHORT W; 52 | } wValue; 53 | 54 | union _wIndex { 55 | struct { 56 | UCHAR LowByte; 57 | UCHAR HiByte; 58 | }; 59 | USHORT W; 60 | } wIndex; 61 | USHORT wLength; 62 | } USB_DEFAULT_PIPE_SETUP_PACKET, *PUSB_DEFAULT_PIPE_SETUP_PACKET; 63 | 64 | // setup packet is eight bytes -- defined by spec 65 | C_ASSERT(sizeof(USB_DEFAULT_PIPE_SETUP_PACKET) == 8); 66 | 67 | 68 | #define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 0x06 69 | 70 | typedef struct _USB_DEVICE_QUALIFIER_DESCRIPTOR { 71 | UCHAR bLength; 72 | UCHAR bDescriptorType; 73 | USHORT bcdUSB; 74 | UCHAR bDeviceClass; 75 | UCHAR bDeviceSubClass; 76 | UCHAR bDeviceProtocol; 77 | UCHAR bMaxPacketSize0; 78 | UCHAR bNumConfigurations; 79 | UCHAR bReserved; 80 | } USB_DEVICE_QUALIFIER_DESCRIPTOR, *PUSB_DEVICE_QUALIFIER_DESCRIPTOR; 81 | 82 | 83 | typedef union _USB_HIGH_SPEED_MAXPACKET { 84 | struct _MP { 85 | USHORT MaxPacket:11; /* 0..10 */ 86 | USHORT HSmux:2; /* 11..12 */ 87 | USHORT Reserved:3; /* 13..15 */ 88 | }; 89 | USHORT us; 90 | } USB_HIGH_SPEED_MAXPACKET, *PUSB_HIGH_SPEED_MAXPACKET; 91 | 92 | #define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 0x0B 93 | 94 | typedef struct _USB_INTERFACE_ASSOCIATION_DESCRIPTOR { 95 | 96 | UCHAR bLength; 97 | UCHAR bDescriptorType; 98 | UCHAR bFirstInterface; 99 | UCHAR bInterfaceCount; 100 | UCHAR bFunctionClass; 101 | UCHAR bFunctionSubClass; 102 | UCHAR bFunctionProtocol; 103 | UCHAR iFunction; 104 | 105 | } USB_INTERFACE_ASSOCIATION_DESCRIPTOR, *PUSB_INTERFACE_ASSOCIATION_DESCRIPTOR; 106 | 107 | 108 | #include 109 | 110 | #endif __USB200_H__ 111 | 112 | -------------------------------------------------------------------------------- /ExtIO_sddc/library/lib/librariesReadme.txt: -------------------------------------------------------------------------------- 1 | 2 | // libraries 3 | 4 | CyAPI.lib 5 | libfftw3f-3.def 6 | libfftw3f-3.dll 7 | libfftw3f-3.exp 8 | libfftw3f-3.lib 9 | SetupAPI.Lib // required by CyAPI.lib 10 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_GPIFII_SM/BBRF103_SM.cyfx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_GPIFII_SM/cyfxgpif2config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Project Name: BBRF103_SM.cyfx 3 | * Time : 06/22/2017 10:02:07 4 | * Device Type: FX3 5 | * Project Type: GPIF2 6 | * 7 | * 8 | * 9 | * 10 | * This is a generated file and should not be modified 11 | * This file need to be included only once in the firmware 12 | * This file is generated by Gpif2 designer tool version - 1.0.1198.2 13 | * 14 | */ 15 | 16 | #ifndef _INCLUDED_BBRF103_GPIFII_SM_ 17 | #define _INCLUDED_BBRF103_GPIFII_SM_ 18 | #include "cyu3types.h" 19 | #include "cyu3gpif.h" 20 | 21 | /* Summary 22 | Number of states in the state machine 23 | */ 24 | #define CY_NUMBER_OF_STATES 9 25 | 26 | /* Summary 27 | Mapping of user defined state names to state indices 28 | */ 29 | #define RESET 0 30 | #define TH0_RD 2 31 | #define TH0_RD_LD 1 32 | #define TH1_RD_LD 3 33 | #define TH1_RD 5 34 | #define TH1_BUSY 6 35 | #define TH1_WAIT 7 36 | #define TH0_BUSY 4 37 | #define TH0_WAIT 8 38 | 39 | 40 | /* Summary 41 | Initial value of early outputs from the state machine. 42 | */ 43 | #define ALPHA_RESET 0x4 44 | 45 | 46 | /* Summary 47 | Transition function values used in the state machine. 48 | */ 49 | uint16_t CyFxGpifTransition[] = { 50 | 0x0000, 0xAAAA, 0x5555, 0xFFFF 51 | }; 52 | 53 | /* Summary 54 | Table containing the transition information for various states. 55 | This table has to be stored in the WAVEFORM Registers. 56 | This array consists of non-replicated waveform descriptors and acts as a 57 | waveform table. 58 | */ 59 | CyU3PGpifWaveData CyFxGpifWavedata[] = { 60 | {{0x1E739A01,0x20000104,0x80000080},{0x00000000,0x00000000,0x00000000}}, 61 | {{0x1E739402,0x20000100,0x80000040},{0x3E739C04,0x00000000,0x80000100}}, 62 | {{0x1E739A03,0x24000104,0x80000080},{0x00000000,0x00000000,0x00000000}}, 63 | {{0x1E739405,0x24000100,0x80000040},{0x3E739C06,0x00000000,0x80000100}}, 64 | {{0x1E739A08,0x00000100,0x80000000},{0x00000000,0x00000000,0x00000000}}, 65 | {{0x1E739A07,0x04000100,0x80000000},{0x00000000,0x00000000,0x00000000}} 66 | }; 67 | 68 | /* Summary 69 | Table that maps state indices to the descriptor table indices. 70 | */ 71 | uint8_t CyFxGpifWavedataPosition[] = { 72 | 0,1,2,3,4,0,5,2,0 73 | }; 74 | 75 | /* Summary 76 | GPIF II configuration register values. 77 | */ 78 | uint32_t CyFxGpifRegValue[] = { 79 | 0x80008300, /* CY_U3P_PIB_GPIF_CONFIG */ 80 | 0x00000067, /* CY_U3P_PIB_GPIF_BUS_CONFIG */ 81 | 0x00000000, /* CY_U3P_PIB_GPIF_BUS_CONFIG2 */ 82 | 0x00000046, /* CY_U3P_PIB_GPIF_AD_CONFIG */ 83 | 0x00000000, /* CY_U3P_PIB_GPIF_STATUS */ 84 | 0x00000000, /* CY_U3P_PIB_GPIF_INTR */ 85 | 0x00000002, /* CY_U3P_PIB_GPIF_INTR_MASK */ 86 | 0x00000082, /* CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */ 87 | 0x00000782, /* CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */ 88 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */ 89 | 0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */ 90 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */ 91 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */ 92 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 93 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 94 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 95 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 96 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 97 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 98 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 99 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 100 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 101 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 102 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 103 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 104 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 105 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 106 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 107 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 108 | 0x00000006, /* CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */ 109 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */ 110 | 0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */ 111 | 0x0000010A, /* CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */ 112 | 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */ 113 | 0x0000FFFF, /* CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */ 114 | 0x00000000, /* CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */ 115 | 0x0000FFFF, /* CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */ 116 | 0x00000109, /* CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */ 117 | 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COUNT_RESET */ 118 | 0x00000FFE, /* CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */ 119 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */ 120 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_MASK */ 121 | 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_VALUE */ 122 | 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_MASK */ 123 | 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */ 124 | 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_MASK */ 125 | 0x00000000, /* CY_U3P_PIB_GPIF_DATA_CTRL */ 126 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 127 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 128 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 129 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 130 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 131 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 132 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 133 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 134 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 135 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 136 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 137 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 138 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 139 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 140 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 141 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 142 | 0x80010400, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 143 | 0x80010401, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 144 | 0x80010402, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 145 | 0x80010403, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 146 | 0x00000000, /* CY_U3P_PIB_GPIF_LAMBDA_STAT */ 147 | 0x00000000, /* CY_U3P_PIB_GPIF_ALPHA_STAT */ 148 | 0x00000000, /* CY_U3P_PIB_GPIF_BETA_STAT */ 149 | 0x00040000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */ 150 | 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */ 151 | 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */ 152 | 0x00000000, /* CY_U3P_PIB_GPIF_CRC_CONFIG */ 153 | 0x00000000, /* CY_U3P_PIB_GPIF_CRC_DATA */ 154 | 0xFFFFFFC1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */ 155 | }; 156 | 157 | /* Summary 158 | This structure holds all the configuration inputs for the GPIF II. 159 | */ 160 | const CyU3PGpifConfig_t CyFxGpifConfig = { 161 | (uint16_t)(sizeof(CyFxGpifWavedataPosition)/sizeof(uint8_t)), 162 | CyFxGpifWavedata, 163 | CyFxGpifWavedataPosition, 164 | (uint16_t)(sizeof(CyFxGpifTransition)/sizeof(uint16_t)), 165 | CyFxGpifTransition, 166 | (uint16_t)(sizeof(CyFxGpifRegValue)/sizeof(uint32_t)), 167 | CyFxGpifRegValue 168 | }; 169 | 170 | #endif /* _INCLUDED_BBRF103_GPIFII_SM_ */ 171 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_GPIFII_SM/projectfiles/gpif2model.xml: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | False 6 | False 7 | False 8 | False 9 | False 10 | Slave 11 | Synchronous 12 | External 13 | Positive 14 | LittleEndian 15 | Bit16 16 | 0 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | RESET 31 | True 32 | 0 33 | 34 | 35 | TH0_RD 36 | True 37 | 0 38 | 39 | Socket 40 | Thread0 41 | True 42 | True 43 | 44 | 45 | 46 | 47 | TH0_RD_LD 48 | True 49 | 0 50 | 51 | Up 52 | 0 53 | 4094 54 | Disable 55 | 1 56 | Mask 57 | 58 | 59 | Socket 60 | Thread0 61 | True 62 | True 63 | 64 | 65 | 66 | TH1_RD_LD 67 | True 68 | 0 69 | 70 | Socket 71 | Thread1 72 | True 73 | True 74 | 75 | 76 | Up 77 | 0 78 | 4094 79 | Disable 80 | 1 81 | Mask 82 | 83 | 84 | 85 | TH1_RD 86 | True 87 | 0 88 | 89 | Socket 90 | Thread1 91 | True 92 | True 93 | 94 | 95 | 96 | 97 | TH1_BUSY 98 | True 99 | 0 100 | 101 | 102 | 103 | TH1_WAIT 104 | True 105 | 0 106 | 107 | 108 | TH0_BUSY 109 | True 110 | 0 111 | 112 | 113 | 114 | TH0_WAIT 115 | True 116 | 0 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_GPIFII_SM/projectfiles/gpif2timingsimulation.xml: -------------------------------------------------------------------------------- 1 |  2 | 3 | 100 4 | 1024 5 | 0 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_GPIFII_SM/projectfiles/gpif2view.xml: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | 5 | 522 6 | 128.446666666667 7 | 83 8 | 70 9 | STATE1 10 | TH0_RD 11 | 1 12 | False 13 | 00000000-0000-0000-0000-000000000000 14 | 15 | 16 | 248 17 | 145 18 | 83 19 | 70 20 | STATE5 21 | TH0_RD_LD 22 | 1 23 | False 24 | 00000000-0000-0000-0000-000000000000 25 | 26 | 27 | 552 28 | 348.723333333333 29 | 83 30 | 70 31 | STATE0 32 | TH1_RD_LD 33 | 1 34 | False 35 | 00000000-0000-0000-0000-000000000000 36 | 37 | 38 | 286 39 | 381.723333333333 40 | 83 41 | 70 42 | STATE2 43 | TH1_RD 44 | 1 45 | False 46 | 00000000-0000-0000-0000-000000000000 47 | 48 | 49 | 733 50 | 412.723333333333 51 | 83 52 | 70 53 | STATE3 54 | TH1_BUSY 55 | 1 56 | False 57 | 00000000-0000-0000-0000-000000000000 58 | 59 | 60 | 128 61 | 326.723333333333 62 | 83 63 | 70 64 | STATE4 65 | TH0_BUSY 66 | 1 67 | False 68 | 00000000-0000-0000-0000-000000000000 69 | 70 | 71 | 619 72 | 520.723333333333 73 | 83 74 | 70 75 | STATE6 76 | TH1_WAIT 77 | 1 78 | False 79 | 00000000-0000-0000-0000-000000000000 80 | 81 | 82 | 32 83 | 179.723333333333 84 | 83 85 | 70 86 | STATE7 87 | TH0_WAIT 88 | 1 89 | False 90 | 00000000-0000-0000-0000-000000000000 91 | 92 | 93 | 29 94 | 18.4466666666667 95 | 83 96 | 70 97 | STARTSTATE1 98 | RESET 99 | 1 100 | False 101 | 00000000-0000-0000-0000-000000000000 102 | 103 | 104 | 105 | 106 | TRANSITION14 107 | DMA_RDY_TH0 108 | STATE7 109 | STATE5 110 | Connector 111 | Connector 112 | None 113 | Arrow 114 | 0 115 | 116 | 117 | TRANSITION13 118 | LOGIC_ONE 119 | STATE4 120 | STATE7 121 | Connector 122 | Connector 123 | None 124 | Arrow 125 | 0 126 | 127 | 128 | TRANSITION12 129 | !DMA_RDY_TH0 130 | STATE5 131 | STATE4 132 | Connector 133 | Connector 134 | None 135 | Arrow 136 | 0 137 | 138 | 139 | TRANSITION11 140 | DMA_RDY_TH1 141 | STATE6 142 | STATE0 143 | Connector 144 | Connector 145 | None 146 | Arrow 147 | 0 148 | 149 | 150 | TRANSITION10 151 | LOGIC_ONE 152 | STATE3 153 | STATE6 154 | Connector 155 | Connector 156 | None 157 | Arrow 158 | 0 159 | 160 | 161 | TRANSITION9 162 | !DMA_RDY_TH1 163 | STATE0 164 | STATE3 165 | Connector 166 | Connector 167 | None 168 | Arrow 169 | 0 170 | 171 | 172 | TRANSITION2 173 | DATA_CNT_HIT 174 | STATE2 175 | STATE5 176 | Connector 177 | Connector 178 | None 179 | Arrow 180 | 0 181 | 182 | 183 | TRANSITION1 184 | DMA_RDY_TH1 185 | STATE0 186 | STATE2 187 | Connector 188 | Connector 189 | None 190 | Arrow 191 | 0 192 | 193 | 194 | TRANSITION0 195 | DATA_CNT_HIT 196 | STATE1 197 | STATE0 198 | Connector 199 | Connector 200 | None 201 | Arrow 202 | 0 203 | 204 | 205 | TRANSITION8 206 | DMA_RDY_TH0 207 | STATE5 208 | STATE1 209 | Connector 210 | Connector 211 | None 212 | Arrow 213 | 0 214 | 215 | 216 | TRANSITION7 217 | LOGIC_ONE 218 | STARTSTATE1 219 | STATE5 220 | Connector 221 | Connector 222 | None 223 | Arrow 224 | 0 225 | 226 | 227 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | SDRx3B 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | ?name? 14 | 15 | 16 | 17 | org.eclipse.cdt.make.core.append_environment 18 | true 19 | 20 | 21 | org.eclipse.cdt.make.core.autoBuildTarget 22 | all 23 | 24 | 25 | org.eclipse.cdt.make.core.buildArguments 26 | 27 | 28 | 29 | org.eclipse.cdt.make.core.buildCommand 30 | cs-make 31 | 32 | 33 | org.eclipse.cdt.make.core.buildLocation 34 | ${workspace_loc:/GpifToUsb/Debug} 35 | 36 | 37 | org.eclipse.cdt.make.core.cleanBuildTarget 38 | clean 39 | 40 | 41 | org.eclipse.cdt.make.core.contents 42 | org.eclipse.cdt.make.core.activeConfigSettings 43 | 44 | 45 | org.eclipse.cdt.make.core.enableAutoBuild 46 | false 47 | 48 | 49 | org.eclipse.cdt.make.core.enableCleanBuild 50 | true 51 | 52 | 53 | org.eclipse.cdt.make.core.enableFullBuild 54 | true 55 | 56 | 57 | org.eclipse.cdt.make.core.fullBuildTarget 58 | all 59 | 60 | 61 | org.eclipse.cdt.make.core.stopOnError 62 | true 63 | 64 | 65 | org.eclipse.cdt.make.core.useDefaultBuildCmd 66 | true 67 | 68 | 69 | 70 | 71 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 72 | 73 | 74 | 75 | 76 | 77 | org.eclipse.cdt.core.cnature 78 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 79 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 80 | 81 | 82 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/cyfx_gcc_startup.S: -------------------------------------------------------------------------------- 1 | # Copyright Cypress Semiconductor Corporation, 2010-2011, 2 | # All Rights Reserved 3 | # UNPUBLISHED, LICENSED SOFTWARE. 4 | # 5 | # CONFIDENTIAL AND PROPRIETARY INFORMATION 6 | # WHICH IS THE PROPERTY OF CYPRESS. 7 | # 8 | # Use of this file is governed 9 | # by the license agreement included in the file 10 | # 11 | # /license/license.txt 12 | # 13 | # where is the Cypress software 14 | # installation root directory path. 15 | # 16 | 17 | # Cypress FX3 Firmware Startup code 18 | 19 | 20 | .section .text 21 | .code 32 22 | 23 | .global jump 24 | jump: 25 | bx R0 26 | 27 | .global CyU3PToolChainInit 28 | CyU3PToolChainInit: 29 | 30 | # clear the BSS area 31 | __main: 32 | mov R0, #0 33 | ldr R1, =_bss_start 34 | ldr R2, =_bss_end 35 | 1: cmp R1, R2 36 | strlo R0, [R1], #4 37 | blo 1b 38 | 39 | b main 40 | 41 | 42 | .global __user_initial_stackheap 43 | __user_initial_stackheap: 44 | 45 | # The tool chain is not expected to place the stack. 46 | # No heap is expected to be used by USB 3.0 platform drivers. 47 | # Place them as required by the user code 48 | .if INTER == TRUE 49 | bx lr 50 | .else 51 | mov pc, lr 52 | .endif 53 | 54 | .end 55 | 56 | # [] 57 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/cyfxbulkdscr.c: -------------------------------------------------------------------------------- 1 | /* 2 | ## Cypress USB 3.0 Platform header file (cyfxbulkdscr.c) 3 | ## =========================== 4 | ## 5 | ## Copyright Cypress Semiconductor Corporation, 2010-2011, 6 | ## All Rights Reserved 7 | ## UNPUBLISHED, LICENSED SOFTWARE. 8 | ## 9 | ## CONFIDENTIAL AND PROPRIETARY INFORMATION 10 | ## WHICH IS THE PROPERTY OF CYPRESS. 11 | ## 12 | ## Use of this file is governed 13 | ## by the license agreement included in the file 14 | ## 15 | ## /license/license.txt 16 | ## 17 | ## where is the Cypress software 18 | ## installation root directory path. 19 | ## 20 | ## =========================== 21 | */ 22 | 23 | #include "sdrx3.h" 24 | 25 | /* Standard device descriptor for USB 3.0 */ 26 | const uint8_t CyFxUSB30DeviceDscr[] __attribute__ ((aligned (32))) = 27 | { 28 | 0x12, /* Descriptor size */ 29 | CY_U3P_USB_DEVICE_DESCR, /* Device descriptor type */ 30 | 0x00,0x03, /* USB 3.0 */ 31 | 0x00, /* Device class */ 32 | 0x00, /* Device sub-class */ 33 | 0x00, /* Device protocol */ 34 | 0x09, /* Maxpacket size for EP0 : 2^9 */ 35 | 0xB4,0x04, /* Vendor ID */ 36 | 0xF1,0x00, /* Product ID */ 37 | 0x00,0x00, /* Device release number */ 38 | 0x01, /* Manufacture string index */ 39 | 0x02, /* Product string index */ 40 | 0x00, /* Serial number string index */ 41 | 0x01 /* Number of configurations */ 42 | }; 43 | 44 | /* Standard device descriptor for USB 2.0 */ 45 | const uint8_t CyFxUSB20DeviceDscr[] __attribute__ ((aligned (32))) = 46 | { 47 | 0x12, /* Descriptor size */ 48 | CY_U3P_USB_DEVICE_DESCR, /* Device descriptor type */ 49 | 0x10,0x02, /* USB 2.10 */ 50 | 0x00, /* Device class */ 51 | 0x00, /* Device sub-class */ 52 | 0x00, /* Device protocol */ 53 | 0x40, /* Maxpacket size for EP0 : 64 bytes */ 54 | 0xB4,0x04, /* Vendor ID */ 55 | 0xF1,0x00, /* Product ID */ 56 | 0x00,0x00, /* Device release number */ 57 | 0x01, /* Manufacture string index */ 58 | 0x02, /* Product string index */ 59 | 0x00, /* Serial number string index */ 60 | 0x01 /* Number of configurations */ 61 | }; 62 | 63 | /* Binary device object store descriptor */ 64 | const uint8_t CyFxUSBBOSDscr[] __attribute__ ((aligned (32))) = 65 | { 66 | 0x05, /* Descriptor size */ 67 | CY_U3P_BOS_DESCR, /* Device descriptor type */ 68 | 0x16,0x00, /* Length of this descriptor and all sub descriptors */ 69 | 0x02, /* Number of device capability descriptors */ 70 | 71 | /* USB 2.0 extension */ 72 | 0x07, /* Descriptor size */ 73 | CY_U3P_DEVICE_CAPB_DESCR, /* Device capability type descriptor */ 74 | CY_U3P_USB2_EXTN_CAPB_TYPE, /* USB 2.0 extension capability type */ 75 | 0x02,0x00,0x00,0x00, /* Supported device level features: LPM support */ 76 | 77 | /* SuperSpeed device capability */ 78 | 0x0A, /* Descriptor size */ 79 | CY_U3P_DEVICE_CAPB_DESCR, /* Device capability type descriptor */ 80 | CY_U3P_SS_USB_CAPB_TYPE, /* SuperSpeed device capability type */ 81 | 0x00, /* Supported device level features */ 82 | 0x0E,0x00, /* Speeds supported by the device : SS, HS and FS */ 83 | 0x03, /* Functionality support */ 84 | 0x0A, /* U1 Device Exit latency */ 85 | 0xFF,0x07 /* U2 Device Exit latency */ 86 | }; 87 | 88 | /* Standard device qualifier descriptor */ 89 | const uint8_t CyFxUSBDeviceQualDscr[] __attribute__ ((aligned (32))) = 90 | { 91 | 0x0A, /* Descriptor size */ 92 | CY_U3P_USB_DEVQUAL_DESCR, /* Device qualifier descriptor type */ 93 | 0x00,0x02, /* USB 2.0 */ 94 | 0x00, /* Device class */ 95 | 0x00, /* Device sub-class */ 96 | 0x00, /* Device protocol */ 97 | 0x40, /* Maxpacket size for EP0 : 64 bytes */ 98 | 0x01, /* Number of configurations */ 99 | 0x00 /* Reserved */ 100 | }; 101 | 102 | /* Standard super speed configuration descriptor */ 103 | const uint8_t CyFxUSBSSConfigDscr[] __attribute__ ((aligned (32))) = 104 | { 105 | /* Configuration descriptor */ 106 | 0x09, /* Descriptor size */ 107 | CY_U3P_USB_CONFIG_DESCR, /* Configuration descriptor type */ 108 | 0x1F,0x00, /* Length of this descriptor and all sub descriptors */ 109 | 0x01, /* Number of interfaces */ 110 | 0x01, /* Configuration number */ 111 | 0x00, /* COnfiguration string index */ 112 | 0x80, /* Config characteristics - Bus powered */ 113 | 0x7D, /* Max power consumption of device (in 8mA unit) : 800mA */ 114 | 115 | /* Interface descriptor */ 116 | 0x09, /* Descriptor size */ 117 | CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */ 118 | 0x00, /* Interface number */ 119 | 0x00, /* Alternate setting number */ 120 | 0x01, /* Number of end points */ 121 | 0xFF, /* Interface class */ 122 | 0x00, /* Interface sub class */ 123 | 0x00, /* Interface protocol code */ 124 | 0x00, /* Interface descriptor string index */ 125 | 126 | /* Endpoint descriptor for consumer EP */ 127 | 0x07, /* Descriptor size */ 128 | CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */ 129 | CY_FX_EP_CONSUMER, /* Endpoint address and description */ 130 | CY_U3P_USB_EP_BULK, /* Bulk endpoint type */ 131 | 0x00,0x04, /* Max packet size = 1024 bytes */ 132 | 0x00, /* Servicing interval for data transfers : 0 for Bulk */ 133 | 134 | /* Super speed endpoint companion descriptor for consumer EP */ 135 | 0x06, /* Descriptor size */ 136 | CY_U3P_SS_EP_COMPN_DESCR, /* SS endpoint companion descriptor type */ 137 | (CY_FX_EP_BURST_LENGTH - 1), /* Max no. of packets in a burst(0-15) - 0: burst 1 packet at a time */ 138 | 0x00, /* Max streams for bulk EP = 0 (No streams) */ 139 | 0x00,0x00 /* Service interval for the EP : 0 for bulk */ 140 | }; 141 | 142 | /* Standard high speed configuration descriptor */ 143 | const uint8_t CyFxUSBHSConfigDscr[] __attribute__ ((aligned (32))) = 144 | { 145 | /* Configuration descriptor */ 146 | 0x09, /* Descriptor size */ 147 | CY_U3P_USB_CONFIG_DESCR, /* Configuration descriptor type */ 148 | 0x19,0x00, /* Length of this descriptor and all sub descriptors */ 149 | 0x01, /* Number of interfaces */ 150 | 0x01, /* Configuration number */ 151 | 0x00, /* COnfiguration string index */ 152 | 0x80, /* Config characteristics - bus powered */ 153 | 0x32, /* Max power consumption of device (in 2mA unit) : 100mA */ 154 | 155 | /* Interface descriptor */ 156 | 0x09, /* Descriptor size */ 157 | CY_U3P_USB_INTRFC_DESCR, /* Interface Descriptor type */ 158 | 0x00, /* Interface number */ 159 | 0x00, /* Alternate setting number */ 160 | 0x01, /* Number of endpoints */ 161 | 0xFF, /* Interface class */ 162 | 0x00, /* Interface sub class */ 163 | 0x00, /* Interface protocol code */ 164 | 0x00, /* Interface descriptor string index */ 165 | 166 | /* Endpoint descriptor for consumer EP */ 167 | 0x07, /* Descriptor size */ 168 | CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */ 169 | CY_FX_EP_CONSUMER, /* Endpoint address and description */ 170 | CY_U3P_USB_EP_BULK, /* Bulk endpoint type */ 171 | 0x00,0x02, /* Max packet size = 512 bytes */ 172 | 0x00 /* Servicing interval for data transfers : 0 for bulk */ 173 | }; 174 | 175 | /* Standard full speed configuration descriptor */ 176 | const uint8_t CyFxUSBFSConfigDscr[] __attribute__ ((aligned (32))) = 177 | { 178 | /* Configuration descriptor */ 179 | 0x09, /* Descriptor size */ 180 | CY_U3P_USB_CONFIG_DESCR, /* Configuration descriptor type */ 181 | 0x19,0x00, /* Length of this descriptor and all sub descriptors */ 182 | 0x01, /* Number of interfaces */ 183 | 0x01, /* Configuration number */ 184 | 0x00, /* COnfiguration string index */ 185 | 0x80, /* Config characteristics - bus powered */ 186 | 0x32, /* Max power consumption of device (in 2mA unit) : 100mA */ 187 | 188 | /* Interface descriptor */ 189 | 0x09, /* Descriptor size */ 190 | CY_U3P_USB_INTRFC_DESCR, /* Interface descriptor type */ 191 | 0x00, /* Interface number */ 192 | 0x00, /* Alternate setting number */ 193 | 0x01, /* Number of endpoints */ 194 | 0xFF, /* Interface class */ 195 | 0x00, /* Interface sub class */ 196 | 0x00, /* Interface protocol code */ 197 | 0x00, /* Interface descriptor string index */ 198 | 199 | /* Endpoint descriptor for consumer EP */ 200 | 0x07, /* Descriptor size */ 201 | CY_U3P_USB_ENDPNT_DESCR, /* Endpoint descriptor type */ 202 | CY_FX_EP_CONSUMER, /* Endpoint address and description */ 203 | CY_U3P_USB_EP_BULK, /* Bulk endpoint type */ 204 | 0x40,0x00, /* Max packet size = 64 bytes */ 205 | 0x00 /* Servicing interval for data transfers : 0 for bulk */ 206 | }; 207 | 208 | /* Standard language ID string descriptor */ 209 | const uint8_t CyFxUSBStringLangIDDscr[] __attribute__ ((aligned (32))) = 210 | { 211 | 0x04, /* Descriptor size */ 212 | CY_U3P_USB_STRING_DESCR, /* Device descriptor type */ 213 | 0x09,0x04 /* Language ID supported */ 214 | }; 215 | 216 | /* Standard manufacturer string descriptor */ 217 | const uint8_t CyFxUSBManufactureDscr[] __attribute__ ((aligned (32))) = 218 | { 219 | 0x10, /* Descriptor size */ 220 | CY_U3P_USB_STRING_DESCR, /* Device descriptor type */ 221 | 'C',0x00, 222 | 'y',0x00, 223 | 'p',0x00, 224 | 'r',0x00, 225 | 'e',0x00, 226 | 's',0x00, 227 | 's',0x00 228 | }; 229 | 230 | /* Standard product string descriptor */ 231 | const uint8_t CyFxUSBProductDscr[] __attribute__ ((aligned (32))) = 232 | { 233 | 0x08, /* Descriptor size */ 234 | CY_U3P_USB_STRING_DESCR, /* Device descriptor type */ 235 | 'F',0x00, 236 | 'X',0x00, 237 | '3',0x00 238 | }; 239 | 240 | /* Microsoft OS Descriptor. */ 241 | const uint8_t CyFxUsbOSDscr[] __attribute__ ((aligned (32))) = 242 | { 243 | 0x0E, 244 | CY_U3P_USB_STRING_DESCR, 245 | 'O', 0x00, 246 | 'S', 0x00, 247 | ' ', 0x00, 248 | 'D', 0x00, 249 | 'e', 0x00, 250 | 's', 0x00, 251 | 'c', 0x00 252 | }; 253 | 254 | /* Place this buffer as the last buffer so that no other variable / code shares 255 | * the same cache line. Do not add any other variables / arrays in this file. 256 | * This will lead to variables sharing the same cache line. */ 257 | const uint8_t CyFxUsbDscrAlignBuffer[32] __attribute__ ((aligned (32))); 258 | 259 | /* [ ] */ 260 | 261 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/cyfxgpif2config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Project Name: BBRF103_SM.cyfx 3 | * Time : 06/22/2017 10:02:07 4 | * Device Type: FX3 5 | * Project Type: GPIF2 6 | * 7 | * 8 | * 9 | * 10 | * This is a generated file and should not be modified 11 | * This file need to be included only once in the firmware 12 | * This file is generated by Gpif2 designer tool version - 1.0.1198.2 13 | * 14 | */ 15 | 16 | #ifndef _INCLUDED_BBRF103_GPIFII_SM_ 17 | #define _INCLUDED_BBRF103_GPIFII_SM_ 18 | #include "cyu3types.h" 19 | #include "cyu3gpif.h" 20 | 21 | /* Summary 22 | Number of states in the state machine 23 | */ 24 | #define CY_NUMBER_OF_STATES 9 25 | 26 | /* Summary 27 | Mapping of user defined state names to state indices 28 | */ 29 | #define RESET 0 30 | #define TH0_RD 2 31 | #define TH0_RD_LD 1 32 | #define TH1_RD_LD 3 33 | #define TH1_RD 5 34 | #define TH1_BUSY 6 35 | #define TH1_WAIT 7 36 | #define TH0_BUSY 4 37 | #define TH0_WAIT 8 38 | 39 | 40 | /* Summary 41 | Initial value of early outputs from the state machine. 42 | */ 43 | #define ALPHA_RESET 0x4 44 | 45 | 46 | /* Summary 47 | Transition function values used in the state machine. 48 | */ 49 | uint16_t CyFxGpifTransition[] = { 50 | 0x0000, 0xAAAA, 0x5555, 0xFFFF 51 | }; 52 | 53 | /* Summary 54 | Table containing the transition information for various states. 55 | This table has to be stored in the WAVEFORM Registers. 56 | This array consists of non-replicated waveform descriptors and acts as a 57 | waveform table. 58 | */ 59 | CyU3PGpifWaveData CyFxGpifWavedata[] = { 60 | {{0x1E739A01,0x20000104,0x80000080},{0x00000000,0x00000000,0x00000000}}, 61 | {{0x1E739402,0x20000100,0x80000040},{0x3E739C04,0x00000000,0x80000100}}, 62 | {{0x1E739A03,0x24000104,0x80000080},{0x00000000,0x00000000,0x00000000}}, 63 | {{0x1E739405,0x24000100,0x80000040},{0x3E739C06,0x00000000,0x80000100}}, 64 | {{0x1E739A08,0x00000100,0x80000000},{0x00000000,0x00000000,0x00000000}}, 65 | {{0x1E739A07,0x04000100,0x80000000},{0x00000000,0x00000000,0x00000000}} 66 | }; 67 | 68 | /* Summary 69 | Table that maps state indices to the descriptor table indices. 70 | */ 71 | uint8_t CyFxGpifWavedataPosition[] = { 72 | 0,1,2,3,4,0,5,2,0 73 | }; 74 | 75 | /* Summary 76 | GPIF II configuration register values. 77 | */ 78 | uint32_t CyFxGpifRegValue[] = { 79 | 0x80008300, /* CY_U3P_PIB_GPIF_CONFIG */ 80 | 0x00000067, /* CY_U3P_PIB_GPIF_BUS_CONFIG */ 81 | 0x00000000, /* CY_U3P_PIB_GPIF_BUS_CONFIG2 */ 82 | 0x00000046, /* CY_U3P_PIB_GPIF_AD_CONFIG */ 83 | 0x00000000, /* CY_U3P_PIB_GPIF_STATUS */ 84 | 0x00000000, /* CY_U3P_PIB_GPIF_INTR */ 85 | 0x00000002, /* CY_U3P_PIB_GPIF_INTR_MASK */ 86 | 0x00000082, /* CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */ 87 | 0x00000782, /* CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */ 88 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */ 89 | 0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */ 90 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */ 91 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */ 92 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 93 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 94 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 95 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 96 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 97 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 98 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 99 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 100 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 101 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 102 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 103 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 104 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 105 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 106 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 107 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */ 108 | 0x00000006, /* CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */ 109 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */ 110 | 0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */ 111 | 0x0000010A, /* CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */ 112 | 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */ 113 | 0x0000FFFF, /* CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */ 114 | 0x00000000, /* CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */ 115 | 0x0000FFFF, /* CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */ 116 | 0x00000109, /* CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */ 117 | 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COUNT_RESET */ 118 | 0x00000FFE, /* CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */ 119 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */ 120 | 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_MASK */ 121 | 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_VALUE */ 122 | 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_MASK */ 123 | 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */ 124 | 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_MASK */ 125 | 0x00000000, /* CY_U3P_PIB_GPIF_DATA_CTRL */ 126 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 127 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 128 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 129 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */ 130 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 131 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 132 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 133 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */ 134 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 135 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 136 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 137 | 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */ 138 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 139 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 140 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 141 | 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */ 142 | 0x80010400, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 143 | 0x80010401, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 144 | 0x80010402, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 145 | 0x80010403, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */ 146 | 0x00000000, /* CY_U3P_PIB_GPIF_LAMBDA_STAT */ 147 | 0x00000000, /* CY_U3P_PIB_GPIF_ALPHA_STAT */ 148 | 0x00000000, /* CY_U3P_PIB_GPIF_BETA_STAT */ 149 | 0x00040000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */ 150 | 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */ 151 | 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */ 152 | 0x00000000, /* CY_U3P_PIB_GPIF_CRC_CONFIG */ 153 | 0x00000000, /* CY_U3P_PIB_GPIF_CRC_DATA */ 154 | 0xFFFFFFC1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */ 155 | }; 156 | 157 | /* Summary 158 | This structure holds all the configuration inputs for the GPIF II. 159 | */ 160 | const CyU3PGpifConfig_t CyFxGpifConfig = { 161 | (uint16_t)(sizeof(CyFxGpifWavedataPosition)/sizeof(uint8_t)), 162 | CyFxGpifWavedata, 163 | CyFxGpifWavedataPosition, 164 | (uint16_t)(sizeof(CyFxGpifTransition)/sizeof(uint16_t)), 165 | CyFxGpifTransition, 166 | (uint16_t)(sizeof(CyFxGpifRegValue)/sizeof(uint32_t)), 167 | CyFxGpifRegValue 168 | }; 169 | 170 | #endif /* _INCLUDED_BBRF103_GPIFII_SM_ */ 171 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/cyfxtx.c: -------------------------------------------------------------------------------- 1 | /* 2 | ## Cypress USB 3.0 Platform source file (cyfxtx.c) 3 | ## =========================== 4 | ## 5 | ## Copyright Cypress Semiconductor Corporation, 2010-2011, 6 | ## All Rights Reserved 7 | ## UNPUBLISHED, LICENSED SOFTWARE. 8 | ## 9 | ## CONFIDENTIAL AND PROPRIETARY INFORMATION 10 | ## WHICH IS THE PROPERTY OF CYPRESS. 11 | ## 12 | ## Use of this file is governed 13 | ## by the license agreement included in the file 14 | ## 15 | ## /license/license.txt 16 | ## 17 | ## where is the Cypress software 18 | ## installation root directory path. 19 | ## 20 | ## =========================== 21 | */ 22 | 23 | /* This file defines the porting required for the ThreadX RTOS. 24 | * This file shall be provided in source form and must be compiled 25 | * with the application source code 26 | */ 27 | 28 | #include 29 | #include 30 | 31 | /* 32 | The MEM heap is a Memory byte pool which is used to allocate OS objects 33 | such as thread stacks and memory for message queues. The Cypress FX3 34 | libraries require a Mem heap size of at least 32 KB. 35 | */ 36 | #define CY_U3P_MEM_HEAP_BASE ((uint8_t *)0x40038000) 37 | #define CY_U3P_MEM_HEAP_SIZE (0x8000) 38 | 39 | /* The last 32 KB of RAM is reserved for 2-stage boot operation. This value can be changed to 40 | 0x40080000 if 2-stage boot is not used by the application. */ 41 | #define CY_U3P_SYS_MEM_TOP (0x40078000) 42 | 43 | /* 44 | The buffer heap is used to obtain data buffers for DMA transfers in or out of 45 | the FX3 device. The reference implementation of the buffer allocator makes use 46 | of a reserved area in the SYSTEM RAM and ensures that all allocated DMA buffers 47 | are aligned to cache lines. 48 | */ 49 | #define CY_U3P_BUFFER_HEAP_BASE (((uint32_t)(CY_U3P_MEM_HEAP_BASE) + (CY_U3P_MEM_HEAP_SIZE))) 50 | #define CY_U3P_BUFFER_HEAP_SIZE ((CY_U3P_SYS_MEM_TOP) - (CY_U3P_BUFFER_HEAP_BASE)) 51 | 52 | #define CY_U3P_BUFFER_ALLOC_TIMEOUT (10) 53 | #define CY_U3P_MEM_ALLOC_TIMEOUT (10) 54 | 55 | #define CY_U3P_MAX(a,b) (((a) > (b)) ? (a) : (b)) 56 | #define CY_U3P_MIN(a,b) (((a) < (b)) ? (a) : (b)) 57 | 58 | CyBool_t glMemPoolInit = CyFalse; 59 | CyU3PBytePool glMemBytePool; 60 | CyU3PDmaBufMgr_t glBufferManager = {{0}, 0, 0, 0, 0, 0}; 61 | 62 | /* These functions are exception handlers. These are default 63 | * implementations and the application firmware can have a 64 | * re-implementation. All these exceptions are not currently 65 | * handled and are mapped to while (1) */ 66 | 67 | /* This function is the undefined instruction handler. This 68 | * occurs when the CPU encounters an undefined instruction. */ 69 | void 70 | CyU3PUndefinedHandler ( 71 | void) 72 | { 73 | for (;;); 74 | } 75 | 76 | /* This function is the instruction prefetch error handler. This 77 | * occurs when the CPU encounters an instruction prefetch error. 78 | * Since there are no virtual memory use case, this is an unknown 79 | * memory access error. This is a fatal error. */ 80 | void 81 | CyU3PPrefetchHandler ( 82 | void) 83 | { 84 | for (;;); 85 | } 86 | 87 | /* This function is the data abort error handler. This occurs when 88 | * the CPU encounters an data prefetch error. Since there are no 89 | * virtual memory use case, this is an unknown memory access error. 90 | * This is a fatal error. */ 91 | void 92 | CyU3PAbortHandler ( 93 | void) 94 | { 95 | for (;;); 96 | } 97 | 98 | /* This function is expected to be invoked by the RTOS kernel after 99 | * initialization. No explicit call to this function must be made. 100 | */ 101 | void 102 | tx_application_define ( 103 | void *unusedMem) 104 | { 105 | (void) unusedMem; 106 | CyU3PApplicationDefine (); 107 | } 108 | 109 | /* This function initializes the custom heap for OS specific dynamic memory allocation. 110 | * The function should not be explicitly invoked. This function is called from the 111 | * API library. Modify this function depending upon the heap requirement of 112 | * application code. The minimum required value is specified by the predefined macro. 113 | * Any value less than specified can cause the drivers to stop functioning. 114 | * The function creates a global byte pool. 115 | */ 116 | void 117 | CyU3PMemInit ( 118 | void) 119 | { 120 | if (!glMemPoolInit) 121 | { 122 | glMemPoolInit = CyTrue; 123 | CyU3PBytePoolCreate (&glMemBytePool, CY_U3P_MEM_HEAP_BASE, CY_U3P_MEM_HEAP_SIZE); 124 | } 125 | } 126 | 127 | void * 128 | CyU3PMemAlloc ( 129 | uint32_t size) 130 | { 131 | void *ret_p; 132 | uint32_t status; 133 | 134 | /* Cannot wait in interrupt context */ 135 | if (CyU3PThreadIdentify ()) 136 | { 137 | status = CyU3PByteAlloc (&glMemBytePool, (void **)&ret_p, size, CY_U3P_MEM_ALLOC_TIMEOUT); 138 | } 139 | else 140 | { 141 | status = CyU3PByteAlloc (&glMemBytePool, (void **)&ret_p, size, CYU3P_NO_WAIT); 142 | } 143 | 144 | if(status == CY_U3P_SUCCESS) 145 | { 146 | return ret_p; 147 | } 148 | 149 | return (NULL); 150 | } 151 | 152 | void 153 | CyU3PMemFree ( 154 | void *mem_p) 155 | { 156 | CyU3PByteFree (mem_p); 157 | } 158 | 159 | void 160 | CyU3PMemSet ( 161 | uint8_t *ptr, 162 | uint8_t data, 163 | uint32_t count) 164 | { 165 | /* Loop unrolling for faster operation */ 166 | while (count >> 3) 167 | { 168 | ptr[0] = data; 169 | ptr[1] = data; 170 | ptr[2] = data; 171 | ptr[3] = data; 172 | ptr[4] = data; 173 | ptr[5] = data; 174 | ptr[6] = data; 175 | ptr[7] = data; 176 | 177 | count -= 8; 178 | ptr += 8; 179 | } 180 | 181 | while (count--) 182 | { 183 | *ptr = data; 184 | ptr++; 185 | } 186 | } 187 | 188 | void 189 | CyU3PMemCopy ( 190 | uint8_t *dest, 191 | uint8_t *src, 192 | uint32_t count) 193 | { 194 | /* Loop unrolling for faster operation */ 195 | while (count >> 3) 196 | { 197 | dest[0] = src[0]; 198 | dest[1] = src[1]; 199 | dest[2] = src[2]; 200 | dest[3] = src[3]; 201 | dest[4] = src[4]; 202 | dest[5] = src[5]; 203 | dest[6] = src[6]; 204 | dest[7] = src[7]; 205 | 206 | count -= 8; 207 | dest += 8; 208 | src += 8; 209 | } 210 | 211 | while (count--) 212 | { 213 | *dest = *src; 214 | dest++; 215 | src++; 216 | } 217 | } 218 | 219 | int32_t 220 | CyU3PMemCmp ( 221 | const void* s1, 222 | const void* s2, 223 | uint32_t n) 224 | { 225 | const uint8_t *ptr1 = s1, *ptr2 = s2; 226 | 227 | while(n--) 228 | { 229 | if(*ptr1 != *ptr2) 230 | { 231 | return *ptr1 - *ptr2; 232 | } 233 | 234 | ptr1++; 235 | ptr2++; 236 | } 237 | return 0; 238 | } 239 | 240 | /* This function shall be invoked by the API library 241 | * and should not be explicitly invoked. 242 | * If other buffer sizes are required by the application code, this function must 243 | * be modified to create other block pools. 244 | */ 245 | void 246 | CyU3PDmaBufferInit ( 247 | void) 248 | { 249 | uint32_t status, size; 250 | uint32_t tmp; 251 | 252 | /* If buffer manager has already been initialized, just return. */ 253 | if ((glBufferManager.startAddr != 0) && (glBufferManager.regionSize != 0)) 254 | { 255 | return; 256 | } 257 | 258 | /* Create a mutex variable for safe allocation. */ 259 | status = CyU3PMutexCreate (&glBufferManager.lock, CYU3P_NO_INHERIT); 260 | if (status != CY_U3P_SUCCESS) 261 | { 262 | return; 263 | } 264 | 265 | /* No threads are running at this point in time. There is no need to 266 | get the mutex. */ 267 | 268 | /* Allocate the memory buffer to be used to track memory status. 269 | We need one bit per 32 bytes of memory buffer space. Since a 32 270 | bit array is being used, round up to the necessary number of 271 | 32 bit words. */ 272 | size = ((CY_U3P_BUFFER_HEAP_SIZE / 32) + 31) / 32; 273 | glBufferManager.usedStatus = (uint32_t *)CyU3PMemAlloc (size * 4); 274 | if (glBufferManager.usedStatus == 0) 275 | { 276 | CyU3PMutexDestroy (&glBufferManager.lock); 277 | return; 278 | } 279 | 280 | /* Initially mark all memory as available. If there are any status bits 281 | beyond the valid memory range, mark these as unavailable. */ 282 | CyU3PMemSet ((uint8_t *)glBufferManager.usedStatus, 0, (size * 4)); 283 | if ((CY_U3P_BUFFER_HEAP_SIZE / 32) & 31) 284 | { 285 | tmp = 32 - ((CY_U3P_BUFFER_HEAP_SIZE / 32) & 31); 286 | glBufferManager.usedStatus[size - 1] = ~((1 << tmp) - 1); 287 | } 288 | 289 | /* Initialize the start address and region size variables. */ 290 | glBufferManager.startAddr = CY_U3P_BUFFER_HEAP_BASE; 291 | glBufferManager.regionSize = CY_U3P_BUFFER_HEAP_SIZE; 292 | glBufferManager.statusSize = size; 293 | glBufferManager.searchPos = 0; 294 | } 295 | 296 | /* This function shall be invoked by the API library 297 | * and should not be explicitly invoked. 298 | */ 299 | void 300 | CyU3PDmaBufferDeInit ( 301 | void) 302 | { 303 | uint32_t status; 304 | 305 | /* Get the mutex lock. */ 306 | if (CyU3PThreadIdentify ()) 307 | { 308 | status = CyU3PMutexGet (&glBufferManager.lock, CYU3P_WAIT_FOREVER); 309 | } 310 | else 311 | { 312 | status = CyU3PMutexGet (&glBufferManager.lock, CYU3P_NO_WAIT); 313 | } 314 | 315 | if (status != CY_U3P_SUCCESS) 316 | { 317 | return; 318 | } 319 | 320 | /* Free memory and zero out variables. */ 321 | CyU3PMemFree (glBufferManager.usedStatus); 322 | glBufferManager.usedStatus = 0; 323 | glBufferManager.startAddr = 0; 324 | glBufferManager.regionSize = 0; 325 | glBufferManager.statusSize = 0; 326 | 327 | /* Free up and destroy the mutex variable. */ 328 | CyU3PMutexPut (&glBufferManager.lock); 329 | CyU3PMutexDestroy (&glBufferManager.lock); 330 | } 331 | 332 | /* Helper function for the DMA buffer manager. Used to set/clear 333 | a set of status bits from the alloc/free functions. */ 334 | static void 335 | CyU3PDmaBufMgrSetStatus ( 336 | uint32_t startPos, 337 | uint32_t numBits, 338 | CyBool_t value) 339 | { 340 | uint32_t wordnum = (startPos >> 5); 341 | uint32_t startbit, endbit, mask; 342 | 343 | startbit = (startPos & 31); 344 | endbit = CY_U3P_MIN (32, startbit + numBits); 345 | 346 | /* Compute a mask that has a 1 at all bit positions to be altered. */ 347 | mask = (endbit == 32) ? 0xFFFFFFFFU : ((uint32_t)(1 << endbit) - 1); 348 | mask -= ((1 << startbit) - 1); 349 | 350 | /* Repeatedly go through the array and update each 32 bit word as required. */ 351 | while (numBits) 352 | { 353 | if (value) 354 | { 355 | glBufferManager.usedStatus[wordnum] |= mask; 356 | } 357 | else 358 | { 359 | glBufferManager.usedStatus[wordnum] &= ~mask; 360 | } 361 | 362 | wordnum++; 363 | numBits -= (endbit - startbit); 364 | if (numBits >= 32) 365 | { 366 | startbit = 0; 367 | endbit = 32; 368 | mask = 0xFFFFFFFFU; 369 | } 370 | else 371 | { 372 | startbit = 0; 373 | endbit = numBits; 374 | mask = ((uint32_t)(1 << numBits) - 1); 375 | } 376 | } 377 | } 378 | 379 | /* This function shall be invoked from the DMA module for buffer allocation */ 380 | void * 381 | CyU3PDmaBufferAlloc ( 382 | uint16_t size) 383 | { 384 | uint32_t tmp; 385 | uint32_t wordnum, bitnum; 386 | uint32_t count, start = 0; 387 | void *ptr = 0; 388 | 389 | /* Get the lock for the buffer manager. */ 390 | if (CyU3PThreadIdentify ()) 391 | { 392 | tmp = CyU3PMutexGet (&glBufferManager.lock, CY_U3P_BUFFER_ALLOC_TIMEOUT); 393 | } 394 | else 395 | { 396 | tmp = CyU3PMutexGet (&glBufferManager.lock, CYU3P_NO_WAIT); 397 | } 398 | 399 | if (tmp != CY_U3P_SUCCESS) 400 | { 401 | return ptr; 402 | } 403 | 404 | /* Make sure the buffer manager has been initialized. */ 405 | if ((glBufferManager.startAddr == 0) || (glBufferManager.regionSize == 0)) 406 | { 407 | CyU3PMutexPut (&glBufferManager.lock); 408 | return ptr; 409 | } 410 | 411 | /* Find the number of 32 byte chunks required. The minimum size that can be handled is 412 | 64 bytes. */ 413 | size = (size <= 32) ? 2 : (size + 31) / 32; 414 | 415 | /* Search through the status array to find the first block that fits the need. */ 416 | wordnum = glBufferManager.searchPos; 417 | bitnum = 0; 418 | count = 0; 419 | tmp = 0; 420 | 421 | /* Stop searching once we have checked all of the words. */ 422 | while (tmp < glBufferManager.statusSize) 423 | { 424 | if ((glBufferManager.usedStatus[wordnum] & (1 << bitnum)) == 0) 425 | { 426 | if (count == 0) 427 | { 428 | start = (wordnum << 5) + bitnum + 1; 429 | } 430 | count++; 431 | if (count == (size + 1)) 432 | { 433 | /* The last bit corresponding to the allocated memory is left as zero. 434 | This allows us to identify the end of the allocated block while freeing 435 | the memory. We need to search for one additional zero while allocating 436 | to account for this hack. */ 437 | glBufferManager.searchPos = wordnum; 438 | break; 439 | } 440 | } 441 | else 442 | { 443 | count = 0; 444 | } 445 | 446 | bitnum++; 447 | if (bitnum == 32) 448 | { 449 | bitnum = 0; 450 | wordnum++; 451 | tmp++; 452 | if (wordnum == glBufferManager.statusSize) 453 | { 454 | /* Wrap back to the top of the array. */ 455 | wordnum = 0; 456 | count = 0; 457 | } 458 | } 459 | } 460 | 461 | if (count == (size + 1)) 462 | { 463 | /* Mark the memory region identified as occupied and return the pointer. */ 464 | CyU3PDmaBufMgrSetStatus (start, size - 1, CyTrue); 465 | ptr = (void *)(glBufferManager.startAddr + (start << 5)); 466 | } 467 | 468 | CyU3PMutexPut (&glBufferManager.lock); 469 | return (ptr); 470 | } 471 | 472 | /* This function shall be invoked from the DMA module for buffer de-allocation */ 473 | int 474 | CyU3PDmaBufferFree ( 475 | void *buffer) 476 | { 477 | uint32_t status, start, count; 478 | uint32_t wordnum, bitnum; 479 | int retVal = -1; 480 | 481 | /* Get the lock for the buffer manager. */ 482 | if (CyU3PThreadIdentify ()) 483 | { 484 | status = CyU3PMutexGet (&glBufferManager.lock, CY_U3P_BUFFER_ALLOC_TIMEOUT); 485 | } 486 | else 487 | { 488 | status = CyU3PMutexGet (&glBufferManager.lock, CYU3P_NO_WAIT); 489 | } 490 | 491 | if (status != CY_U3P_SUCCESS) 492 | { 493 | return retVal; 494 | } 495 | 496 | /* If the buffer address is within the range specified, count the number of consecutive ones and 497 | clear them. */ 498 | start = (uint32_t)buffer; 499 | if ((start > glBufferManager.startAddr) && (start < (glBufferManager.startAddr + glBufferManager.regionSize))) 500 | { 501 | start = ((start - glBufferManager.startAddr) >> 5); 502 | 503 | wordnum = (start >> 5); 504 | bitnum = (start & 0x1F); 505 | count = 0; 506 | 507 | while ((wordnum < glBufferManager.statusSize) && ((glBufferManager.usedStatus[wordnum] & (1 << bitnum)) != 0)) 508 | { 509 | count++; 510 | bitnum++; 511 | if (bitnum == 32) 512 | { 513 | bitnum = 0; 514 | wordnum++; 515 | } 516 | } 517 | 518 | CyU3PDmaBufMgrSetStatus (start, count, CyFalse); 519 | 520 | /* Start the next buffer search at the top of the heap. This can help reduce fragmentation in cases where 521 | most of the heap is allocated and then freed as a whole. */ 522 | glBufferManager.searchPos = 0; 523 | retVal = 0; 524 | } 525 | 526 | /* Free the lock before we go. */ 527 | CyU3PMutexPut (&glBufferManager.lock); 528 | return retVal; 529 | } 530 | 531 | void 532 | CyU3PFreeHeaps ( 533 | void) 534 | { 535 | /* Free up the mem and buffer heaps. */ 536 | CyU3PDmaBufferDeInit (); 537 | CyU3PBytePoolDestroy (&glMemBytePool); 538 | glMemPoolInit = CyFalse; 539 | } 540 | 541 | /* [ ] */ 542 | 543 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/i2cmodule.c: -------------------------------------------------------------------------------- 1 | /* 2 | * i2cmodule.c 3 | * 4 | * Created on: Mar 14, 2017 5 | * Author: Oscar 6 | */ 7 | 8 | #include "cyu3system.h" 9 | #include "cyu3os.h" 10 | #include "cyu3dma.h" 11 | #include "cyu3error.h" 12 | #include "cyu3usb.h" 13 | #include "cyu3i2c.h" 14 | #include "i2cmodule.h" 15 | 16 | CyU3PReturnStatus_t 17 | CyFxI2cInit () 18 | { 19 | CyU3PI2cConfig_t i2cConfig; 20 | CyU3PReturnStatus_t status = CY_U3P_SUCCESS; 21 | 22 | /* Initialize and configure the I2C master module. */ 23 | status = CyU3PI2cInit (); 24 | if (status != CY_U3P_SUCCESS) 25 | { 26 | return status; 27 | } 28 | 29 | /* Start the I2C master block. The bit rate is set at 100KHz. 30 | * The data transfer is done via DMA. */ 31 | CyU3PMemSet ((uint8_t *)&i2cConfig, 0, sizeof(i2cConfig)); 32 | i2cConfig.bitRate = CY_FX_USBI2C_I2C_BITRATE; 33 | i2cConfig.busTimeout = 0xFFFFFFFF; 34 | i2cConfig.dmaTimeout = 0xFFFF; 35 | i2cConfig.isDma = CyFalse; 36 | 37 | status = CyU3PI2cSetConfig (&i2cConfig, NULL); 38 | return status; 39 | } 40 | 41 | /* I2C read / write for application. */ 42 | CyU3PReturnStatus_t 43 | CyFxUsbI2cTransfer ( 44 | uint8_t byteAddress, 45 | uint8_t devAddr, 46 | uint8_t byteCount, 47 | uint8_t *buffer, 48 | CyBool_t isRead) 49 | { 50 | CyU3PI2cPreamble_t preamble; 51 | CyU3PReturnStatus_t status = CY_U3P_SUCCESS; 52 | 53 | if (byteCount == 0) 54 | { 55 | return CY_U3P_SUCCESS; 56 | } 57 | 58 | if (isRead) 59 | { 60 | /* Update the preamble information. */ 61 | preamble.length = 3; 62 | preamble.buffer[0] = devAddr; 63 | preamble.buffer[1] = byteAddress; 64 | preamble.buffer[2] = (devAddr | 0x01); 65 | preamble.ctrlMask = 0x0002; // stop position 66 | 67 | status = CyU3PI2cReceiveBytes (&preamble, buffer, byteCount, 0); 68 | if (status != CY_U3P_SUCCESS) 69 | { 70 | return status; 71 | } 72 | } 73 | else /* Write */ 74 | { 75 | /* Update the preamble information. */ 76 | preamble.length = 2; 77 | preamble.buffer[0] = devAddr; 78 | preamble.buffer[1] = byteAddress; 79 | preamble.ctrlMask = 0x0000; 80 | status = CyU3PI2cTransmitBytes (&preamble, buffer, byteCount, 0); 81 | return status; 82 | } 83 | 84 | return CY_U3P_SUCCESS; 85 | } 86 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/i2cmodule.h: -------------------------------------------------------------------------------- 1 | #ifndef _INCLUDED_I2CMODULE_H_ 2 | #define _INCLUDED_I2CMODULE_H_ 3 | 4 | #include "cyu3types.h" 5 | #include "cyu3usbconst.h" 6 | 7 | /* I2C Data rate */ 8 | #define I2C_ACTIVE 9 | #define CY_FX_USBI2C_I2C_BITRATE (400000) 10 | 11 | CyU3PReturnStatus_t 12 | CyFxI2cInit(); 13 | 14 | CyU3PReturnStatus_t 15 | CyFxUsbI2cTransfer ( 16 | uint8_t byteAddress, 17 | uint8_t devAddr, 18 | uint8_t byteCount, 19 | uint8_t *buffer, 20 | CyBool_t isRead); 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/makefile: -------------------------------------------------------------------------------- 1 | ## Copyright Cypress Semiconductor Corporation, 2010-2011, 2 | ## All Rights Reserved 3 | ## UNPUBLISHED, LICENSED SOFTWARE. 4 | ## 5 | ## CONFIDENTIAL AND PROPRIETARY INFORMATION 6 | ## WHICH IS THE PROPERTY OF CYPRESS. 7 | ## 8 | ## Use of this file is governed 9 | ## by the license agreement included in the file 10 | ## 11 | ## /license/license.txt 12 | ## 13 | ## where is the Cypress software 14 | ## installation root directory path. 15 | ## 16 | 17 | FX3FWROOT=../.. 18 | FX3PFWROOT=../../u3p_firmware 19 | 20 | all:compile 21 | 22 | include $(FX3FWROOT)/common/fx3_build_config.mak 23 | CCFLAGS += $(CYCFLAGS) 24 | 25 | MODULE = cyfxgpiftousb 26 | 27 | SOURCE += $(MODULE).c 28 | SOURCE += cyfxbulkdscr.c 29 | 30 | C_OBJECT=$(SOURCE:%.c=./%.o) 31 | A_OBJECT=$(SOURCE_ASM:%.S=./%.o) 32 | 33 | EXES = $(MODULE).$(EXEEXT) 34 | 35 | $(MODULE).$(EXEEXT): $(A_OBJECT) $(C_OBJECT) 36 | $(LINK) 37 | 38 | $(C_OBJECT) : %.o : %.c cyfxgpiftousb.h 39 | $(COMPILE) 40 | 41 | $(A_OBJECT) : %.o : %.S 42 | $(ASSEMBLE) 43 | 44 | clean: 45 | rm -f ./$(MODULE).$(EXEEXT) 46 | rm -f ./$(MODULE).map 47 | rm -f ./*.o 48 | 49 | compile: $(C_OBJECT) $(A_OBJECT) $(EXES) 50 | 51 | #[]# 52 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/readme.txt: -------------------------------------------------------------------------------- 1 | BBRF103 source code 2 | Oscar Steila ik1xpv 2017 3 | 4 | It is a modification of 5 | 6 | CYPRESS SEMICONDUCTOR CORPORATION FX3 SDK 7 | USB BULK SOURCE SINK EXAMPLE 8 | 9 | See SDK License 10 | 11 | Files: \BBRF103_SRC\ 12 | 13 | * cyfx_gcc_startup.S : Start-up code for the ARM-9 core on the FX3 device. 14 | This assembly source file follows the syntax for the GNU assembler. 15 | 16 | * cyfxbulksrcsink.h : Constant definitions for the bulk source 17 | application. The USB connection speed, numbers and properties of the 18 | endpoints etc. can be selected through definitions in this file. 19 | 20 | * cyfxbulkdscr.c : C source file containing the USB descriptors that 21 | are used by this firmware example. VID and PID is defined in this file. 22 | 23 | * cyfxtx.c : ThreadX RTOS wrappers and utility functions required 24 | by the FX3 API library. 25 | 26 | * sdrx3.c,sdrx3.h : Main C source file that implements the bulk source 27 | example. 28 | 29 | * cyfxgpif2config.h : GIPF state machine generated by GIPFII 30 | (project in directory BBRF103_GPIFII_SM) 31 | 32 | * i2cmodule.c, h : I2C module 33 | 34 | * makefile : GNU make compliant build script for compiling this 35 | example. 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /FX3Firmware/BBRF103_SRC/sdrx3.h: -------------------------------------------------------------------------------- 1 | /* 2 | ## Cypress USB 3.0 Platform header file (cyfxbulksrcsink.h) 3 | ## =========================== 4 | ## 5 | ## Copyright Cypress Semiconductor Corporation, 2010-2011, 6 | ## All Rights Reserved 7 | ## UNPUBLISHED, LICENSED SOFTWARE. 8 | ## 9 | ## CONFIDENTIAL AND PROPRIETARY INFORMATION 10 | ## WHICH IS THE PROPERTY OF CYPRESS. 11 | ## 12 | ## Use of this file is governed 13 | ## by the license agreement included in the file 14 | ## 15 | ## /license/license.txt 16 | ## 17 | ## where is the Cypress software 18 | ## installation root directory path. 19 | ## 20 | ## =========================== 21 | */ 22 | 23 | /* This file contains the constants used by the bulk source sink application example */ 24 | 25 | #ifndef _INCLUDED_SDRx3_H_ 26 | #define _INCLUDED_SDRx3_H_ 27 | 28 | #include "cyu3types.h" 29 | #include "cyu3usbconst.h" 30 | #include "cyu3externcstart.h" 31 | 32 | #define CY_FX_BULKSRCSINK_DMA_BUF_COUNT (6) /* Bulk channel buffer count */ 33 | #define CY_FX_BULKSRCSINK_DMA_TX_SIZE (0) /* DMA transfer size is set to infinite */ 34 | #define CY_FX_BULKSRCSINK_THREAD_STACK (0x1000) /* Bulk loop application thread stack size */ 35 | #define CY_FX_BULKSRCSINK_THREAD_PRIORITY (8) /* Bulk loop application thread priority */ 36 | 37 | 38 | /* Endpoint and socket definitions for the bulk source sink application */ 39 | 40 | /* To change the producer and consumer EP enter the appropriate EP numbers for the #defines. 41 | * In the case of IN endpoints enter EP number along with the direction bit. 42 | * For eg. EP 6 IN endpoint is 0x86 43 | * and EP 6 OUT endpoint is 0x06. 44 | * To change sockets mention the appropriate socket number in the #defines. */ 45 | 46 | /* Note: For USB 2.0 the endpoints and corresponding sockets are one-to-one mapped 47 | i.e. EP 1 is mapped to UIB socket 1 and EP 2 to socket 2 so on */ 48 | 49 | #define CY_FX_EP_PRODUCER 0x01 /* EP 1 OUT */ 50 | #define CY_FX_EP_CONSUMER 0x81 /* EP 1 IN */ 51 | 52 | #define CY_FX_EP_PRODUCER_SOCKET CY_U3P_UIB_SOCKET_PROD_1 /* Socket 1 is producer */ 53 | #define CY_FX_EP_CONSUMER_SOCKET CY_U3P_UIB_SOCKET_CONS_1 /* Socket 1 is consumer */ 54 | 55 | /* Used with FX3 Silicon. */ 56 | #define CY_FX_PRODUCER_PPORT_SOCKET CY_U3P_PIB_SOCKET_0 /* P-port Socket 0 is producer */ 57 | #define CY_FX_CONSUMER_PPORT_SOCKET CY_U3P_PIB_SOCKET_3 /* P-port Socket 3 is consumer */ 58 | 59 | /* Burst mode definitions: Only for super speed operation. The maximum burst mode 60 | * supported is limited by the USB hosts available. The maximum value for this is 16 61 | * and the minimum (no-burst) is 1. */ 62 | 63 | #define CY_FX_EP_BURST_LENGTH (8) /* Super speed burst length in packets. */ 64 | 65 | #define CY_FX_VND_REQ1 (uint8_t)(0x05) /* Vendor request */ 66 | 67 | /* USB vendor request to read the 8 byte firmware ID. This will return content 68 | * of glFirmwareID array. */ 69 | #define CY_FX_RQT_ID_CHECK (0xB0) 70 | 71 | /* USB vendor request to write to I2C connected. The EEPROM page size is 72 | * fixed to 64 bytes. The I2C EEPROM address is provided in the value field. The 73 | * memory address to start writing is provided in the index field of the request. 74 | * The maximum allowed request length is 4KB. */ 75 | 76 | #define CY_FX_RQT_I2C_WRITE (0xBA) 77 | #define CY_FX_RQT_I2C_READ (0xBB) 78 | #define CY_FX_RQT_GPIO_WRITE (0xBC) 79 | #define CY_FX_RQT_GPIO_PWM (0xBD) 80 | 81 | typedef struct pwmxio_t 82 | { 83 | uint32_t dutycicle; /* The actual bytes starting */ 84 | } pwmxio_t; 85 | 86 | typedef struct outxio_t 87 | { 88 | uint8_t buffer[15]; /* The actual bytes starting */ 89 | } outxio_t; 90 | 91 | typedef struct i2cxio_t 92 | { 93 | uint8_t i2caddr; /* The i2c device address */ 94 | uint8_t regaddr; /* The device register address */ 95 | uint8_t isRead; /* (0) False value WRITE, (1) True value Read */ 96 | uint8_t lencount; /* byte count < 12 */ 97 | uint8_t databyte[12]; 98 | } i2cxio_t; 99 | 100 | 101 | 102 | #define OUTXIO0 (1) // LED_OVERLOAD GPIO21 bit position 103 | #define OUTXIO1 (2) // LED_MODEA GPIO22 104 | #define OUTXIO2 (4) // LED_MODEB GPIO22 105 | 106 | #define OUTXIO3 (8) // SEL0 GPIO26 107 | #define OUTXIO4 (16) // SEL1 GPIO27 108 | 109 | #define OUTXIO5 (32) // SHDWN GPIO28 110 | #define OUTXIO6 (64) // DITH GPIO29 111 | 112 | #define CY_FX_PWM_PERIOD (201600 - 1) /* PWM time period. */ 113 | #define CY_FX_PWM_25P_THRESHOLD (50400 - 1) /* PWM threshold value for 25% duty cycle. */ 114 | 115 | #define LED_OVERLOAD (21) 116 | #define LED_MODEA (22) 117 | #define LED_MODEB (23) 118 | 119 | #define OUTXIO (0) 120 | #define I2CXIO (1) 121 | #define PWMXIO (2) 122 | 123 | 124 | 125 | /* Extern definitions for the USB Descriptors */ 126 | extern const uint8_t CyFxUSB20DeviceDscr[]; 127 | extern const uint8_t CyFxUSB30DeviceDscr[]; 128 | extern const uint8_t CyFxUSBDeviceQualDscr[]; 129 | extern const uint8_t CyFxUSBFSConfigDscr[]; 130 | extern const uint8_t CyFxUSBHSConfigDscr[]; 131 | extern const uint8_t CyFxUSBBOSDscr[]; 132 | extern const uint8_t CyFxUSBSSConfigDscr[]; 133 | extern const uint8_t CyFxUSBStringLangIDDscr[]; 134 | extern const uint8_t CyFxUSBManufactureDscr[]; 135 | extern const uint8_t CyFxUSBProductDscr[]; 136 | 137 | #include 138 | 139 | #endif /* _INCLUDED_CYFXBULKSRCSINK_H_ */ 140 | 141 | /*[]*/ 142 | -------------------------------------------------------------------------------- /FX3Firmware/readme.txt: -------------------------------------------------------------------------------- 1 | BBRF103 source code 2 | Oscar Steila ik1xpv 2017 3 | 4 | It is a modification of 5 | 6 | CYPRESS SEMICONDUCTOR CORPORATION FX3 SDK 7 | USB BULK SOURCE SINK EXAMPLE 8 | 9 | See SDK License 10 | 11 | Files: \BBRF103_SRC\ 12 | 13 | * cyfx_gcc_startup.S : Start-up code for the ARM-9 core on the FX3 device. 14 | This assembly source file follows the syntax for the GNU assembler. 15 | 16 | * cyfxbulksrcsink.h : Constant definitions for the bulk source 17 | application. The USB connection speed, numbers and properties of the 18 | endpoints etc. can be selected through definitions in this file. 19 | 20 | * cyfxbulkdscr.c : C source file containing the USB descriptors that 21 | are used by this firmware example. VID and PID is defined in this file. 22 | 23 | * cyfxtx.c : ThreadX RTOS wrappers and utility functions required 24 | by the FX3 API library. 25 | 26 | * sdrx3.c,sdrx3.h : Main C source file that implements the bulk source 27 | example. 28 | 29 | * cyfxgpif2config.h : GIPF state machine generated by GIPFII 30 | (project in directory BBRF103_GPIFII_SM) 31 | 32 | * i2cmodule.c, h : I2C module 33 | 34 | * makefile : GNU make compliant build script for compiling this 35 | example. 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /HARDWARE/BBRF103TopPCBview.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ik1xpv/BBRF103/443ce80aafdcd5b524f8caa6b1429b11dca53158/HARDWARE/BBRF103TopPCBview.pdf -------------------------------------------------------------------------------- /HARDWARE/BBRF103_scheme.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ik1xpv/BBRF103/443ce80aafdcd5b524f8caa6b1429b11dca53158/HARDWARE/BBRF103_scheme.pdf -------------------------------------------------------------------------------- /HARDWARE/BBRF103bottomPCBview.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ik1xpv/BBRF103/443ce80aafdcd5b524f8caa6b1429b11dca53158/HARDWARE/BBRF103bottomPCBview.pdf -------------------------------------------------------------------------------- /HARDWARE/BLOCKscheme01.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ik1xpv/BBRF103/443ce80aafdcd5b524f8caa6b1429b11dca53158/HARDWARE/BLOCKscheme01.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # BBRF103 2 | 3 | see http://www.steila.com/blog/ 4 | 5 | /HARDWARE/ hardware scheme, pcb , bloc diagram 6 | 7 | /FX3Firmware/ FX3 firmware source code and eclipse SDK proj files and GPIFII project 8 | 9 | /ExtIO_sddc/ ExtIO_sddc.dll source and VS proj files 10 | --------------------------------------------------------------------------------