├── .gitignore ├── A2Sim.JPG ├── A2_SP_16.pdf ├── A2_SP_16_Slides.pdf ├── README.md ├── asic_hardware ├── Makefile ├── hdl_sources.list ├── par │ ├── MAL_TOP.io │ ├── mal_top.globals │ └── mal_top_par.tcl ├── synth │ ├── mal_top_synth.tcl │ └── orpsoc_top_synth.tcl └── verilog │ └── orpsoc │ ├── MAL_TOP.v │ ├── arbiter │ ├── arbiter_bytebus.v │ ├── arbiter_dbus.v │ └── arbiter_ibus.v │ ├── clkgen │ ├── clkgen.v │ ├── clkgen_fpga.v │ └── clkgen_sim.v │ ├── dbg_if │ ├── dbg_cpu.v │ ├── dbg_cpu_defines.v │ ├── dbg_cpu_registers.v │ ├── dbg_crc32_d1.v │ ├── dbg_defines.v │ ├── dbg_if.v │ ├── dbg_register.v │ ├── dbg_wb.v │ └── dbg_wb_defines.v │ ├── jtag_tap │ ├── README │ ├── jtag_tap.v │ └── tap_defines.v │ ├── or1200 │ ├── or1200_alu.v │ ├── or1200_amultp2_32x32.v │ ├── or1200_cfgr.v │ ├── or1200_cpu.v │ ├── or1200_ctrl.v │ ├── or1200_dc_fsm.v │ ├── or1200_dc_ram.v │ ├── or1200_dc_tag.v │ ├── or1200_dc_top.v │ ├── or1200_defines - Copy.v │ ├── or1200_defines.v │ ├── or1200_dmmu_tlb.v │ ├── or1200_dmmu_top.v │ ├── or1200_dpram.v │ ├── or1200_dpram_256x32.v │ ├── or1200_dpram_32x32.v │ ├── or1200_du.v │ ├── or1200_except.v │ ├── or1200_fpu.v │ ├── or1200_fpu_addsub.v │ ├── or1200_fpu_arith.v │ ├── or1200_fpu_div.v │ ├── or1200_fpu_fcmp.v │ ├── or1200_fpu_intfloat_conv.v │ ├── or1200_fpu_intfloat_conv_except.v │ ├── or1200_fpu_mul.v │ ├── or1200_fpu_post_norm_addsub.v │ ├── or1200_fpu_post_norm_div.v │ ├── or1200_fpu_post_norm_intfloat_conv.v │ ├── or1200_fpu_post_norm_mul.v │ ├── or1200_fpu_pre_norm_addsub.v │ ├── or1200_fpu_pre_norm_div.v │ ├── or1200_fpu_pre_norm_mul.v │ ├── or1200_freeze.v │ ├── or1200_genpc.v │ ├── or1200_gmultp2_32x32.v │ ├── or1200_ic_fsm.v │ ├── or1200_ic_ram.v │ ├── or1200_ic_tag.v │ ├── or1200_ic_top.v │ ├── or1200_if.v │ ├── or1200_immu_tlb.v │ ├── or1200_immu_top.v │ ├── or1200_iwb_biu.v │ ├── or1200_lsu.v │ ├── or1200_mem2reg.v │ ├── or1200_mult_mac.v │ ├── or1200_operandmuxes.v │ ├── or1200_pic.v │ ├── or1200_pm.v │ ├── or1200_qmem_top.v │ ├── or1200_reg2mem.v │ ├── or1200_rf.v │ ├── or1200_rfram_generic.v │ ├── or1200_sb.v │ ├── or1200_sb_fifo.v │ ├── or1200_spram.v │ ├── or1200_spram_1024x32.v │ ├── or1200_spram_1024x32_bw.v │ ├── or1200_spram_1024x8.v │ ├── or1200_spram_128x32.v │ ├── or1200_spram_2048x32.v │ ├── or1200_spram_2048x32_bw.v │ ├── or1200_spram_2048x8.v │ ├── or1200_spram_256x21.v │ ├── or1200_spram_32_bw.v │ ├── or1200_spram_32x24.v │ ├── or1200_spram_512x20.v │ ├── or1200_spram_64x14.v │ ├── or1200_spram_64x22.v │ ├── or1200_spram_64x24.v │ ├── or1200_sprs.v │ ├── or1200_top.v │ ├── or1200_tpram_32x32.v │ ├── or1200_tt.v │ ├── or1200_wb_biu.v │ ├── or1200_wbmux.v │ └── or1200_xcv_ram32x8d.v │ ├── ram_wb │ ├── ram_wb.v │ ├── ram_wb_b3.v │ ├── sram.vmem │ └── timescale.v │ ├── ram_wb_sc │ ├── mem_scan.v │ ├── mem_tieoffs.v │ ├── ram_wb.v │ └── ram_wb_sram.v │ ├── top │ ├── orpsoc-defines.v │ ├── orpsoc-params.v │ ├── orpsoc_top.v │ ├── orpsoc_top_sc.v │ ├── synthesis-defines.v │ └── timescale.v │ └── uart16550 │ ├── raminfr.v │ ├── uart_debug_if.v │ ├── uart_defines.v │ ├── uart_receiver.v │ ├── uart_regs.v │ ├── uart_rfifo.v │ ├── uart_sync_flops.v │ ├── uart_tfifo.v │ ├── uart_top.v │ ├── uart_transmitter.v │ └── uart_wb.v ├── chipDesign ├── apr │ ├── MAL_TOP.conf │ ├── MAL_TOP.io │ └── MAL_TOP.tcl ├── netlist │ ├── charge_pump_schmitt.src.net │ └── charge_pump_schmitt_no_IO.src.net ├── synth │ ├── common │ │ ├── avoid_case_sensitive.sh │ │ ├── common.tcl │ │ ├── namingrules.tcl │ │ └── namingrules_old.tcl │ ├── orpsoc_top.tcl │ └── orpsoc_top_read_verilog.tcl └── verilog │ ├── MAL_TOP.v │ ├── mem_wrapper │ ├── mem_scan.v │ └── mem_tieoffs.v │ ├── ram_wb │ └── ram_wb_sram.v │ └── readme.md ├── fpga_hardware ├── Makefile ├── a2.mpf ├── backend │ └── ml509.ucf ├── bsdlFiles │ ├── xc5vlx110t_ff1136.bsd │ ├── xc95144xl.bsd │ ├── xccace.bsd │ └── xcf32p.bsd ├── buildSupport │ ├── orpsoc_top.prj │ └── orpsoc_top.xst ├── cores │ ├── adv_debug_sys │ │ ├── Doc │ │ │ ├── or1k_debug_sys_manual.pdf │ │ │ └── src │ │ │ │ ├── block_diag_or1ksim.odg │ │ │ │ ├── block_diag_sim_rtl.odg │ │ │ │ ├── block_diag_sim_vpi.odg │ │ │ │ ├── debug_sys_blk_diag.odg │ │ │ │ ├── debug_sys_blk_diag_altera.odg │ │ │ │ └── or1k_debug_sys_manual.odt │ │ ├── Hardware │ │ │ ├── actel_ujtag │ │ │ │ ├── doc │ │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ │ ├── actel_ujtag.pdf │ │ │ │ │ ├── gpl-2.0.txt │ │ │ │ │ └── src │ │ │ │ │ │ └── actel_ujtag.odt │ │ │ │ └── rtl │ │ │ │ │ └── verilog │ │ │ │ │ └── actel_ujtag.v │ │ │ ├── adv_dbg_if │ │ │ │ ├── bench │ │ │ │ │ ├── README_testbench.txt │ │ │ │ │ ├── full_system │ │ │ │ │ │ ├── adv_dbg_tb.v │ │ │ │ │ │ ├── onchip_ram_top.v │ │ │ │ │ │ ├── wave.do │ │ │ │ │ │ ├── xsv_fpga_defines.v │ │ │ │ │ │ └── xsv_fpga_top.v │ │ │ │ │ ├── jtag_serial_port │ │ │ │ │ │ ├── adv_dbg_jsp_tb.v │ │ │ │ │ │ └── wave.do │ │ │ │ │ └── simulated_system │ │ │ │ │ │ ├── adv_dbg_tb.v │ │ │ │ │ │ ├── cpu_behavioral.v │ │ │ │ │ │ ├── timescale.v │ │ │ │ │ │ ├── wave.do │ │ │ │ │ │ ├── wb_model_defines.v │ │ │ │ │ │ └── wb_slave_behavioral.v │ │ │ │ ├── doc │ │ │ │ │ ├── AdvancedDebugInterface.pdf │ │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ │ ├── gpl-2.0.txt │ │ │ │ │ └── src │ │ │ │ │ │ ├── AdvancedDebugInterface.odt │ │ │ │ │ │ ├── generic_submodule.odg │ │ │ │ │ │ ├── jsp_submodule.odg │ │ │ │ │ │ ├── system_block_diagram.odg │ │ │ │ │ │ └── top_level_module.odg │ │ │ │ └── rtl │ │ │ │ │ └── verilog │ │ │ │ │ ├── adbg_crc32.v │ │ │ │ │ ├── adbg_defines.v │ │ │ │ │ ├── adbg_jsp_biu.v │ │ │ │ │ ├── adbg_jsp_module.v │ │ │ │ │ ├── adbg_or1k_biu.v │ │ │ │ │ ├── adbg_or1k_defines.v │ │ │ │ │ ├── adbg_or1k_module.v │ │ │ │ │ ├── adbg_or1k_status_reg.v │ │ │ │ │ ├── adbg_top.v │ │ │ │ │ ├── adbg_wb_biu.v │ │ │ │ │ ├── adbg_wb_defines.v │ │ │ │ │ ├── adbg_wb_module.v │ │ │ │ │ ├── bytefifo.v │ │ │ │ │ ├── syncflop.v │ │ │ │ │ └── syncreg.v │ │ │ ├── altera_virtual_jtag │ │ │ │ ├── doc │ │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ │ ├── altera_virtual_jtag.pdf │ │ │ │ │ ├── gpl-2.0.txt │ │ │ │ │ └── src │ │ │ │ │ │ └── altera_virtual_jtag.odt │ │ │ │ └── rtl │ │ │ │ │ └── vhdl │ │ │ │ │ └── altera_virtual_jtag.vhd │ │ │ ├── jtag │ │ │ │ ├── BSDL │ │ │ │ │ └── opencores_tap.bsd │ │ │ │ ├── cells │ │ │ │ │ └── rtl │ │ │ │ │ │ └── verilog │ │ │ │ │ │ ├── BiDirectionalCell.v │ │ │ │ │ │ ├── ControlCell.v │ │ │ │ │ │ ├── InputCell.v │ │ │ │ │ │ └── OutputCell.v │ │ │ │ └── tap │ │ │ │ │ ├── doc │ │ │ │ │ ├── gpl-2.0.txt │ │ │ │ │ ├── jtag.pdf │ │ │ │ │ └── src │ │ │ │ │ │ ├── jtag.odt │ │ │ │ │ │ ├── oc_jtag_sys_diag.odg │ │ │ │ │ │ └── system_block_diagram.odg │ │ │ │ │ └── rtl │ │ │ │ │ └── verilog │ │ │ │ │ ├── tap_defines.v │ │ │ │ │ ├── tap_top.v │ │ │ │ │ └── timescale.v │ │ │ └── xilinx_internal_jtag │ │ │ │ ├── doc │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ ├── gpl-2.0.txt │ │ │ │ ├── src │ │ │ │ │ ├── xilinx_bscan_waveform.odg │ │ │ │ │ └── xilinx_internal_jtag.odt │ │ │ │ └── xilinx_internal_jtag.pdf │ │ │ │ └── rtl │ │ │ │ └── verilog │ │ │ │ ├── xilinx_internal_jtag.v │ │ │ │ └── xilinx_internal_jtag_options.v │ │ ├── Patches │ │ │ ├── GDB6.8 │ │ │ │ └── gdb-6.8-bz436037-reg-no-longer-active.patch │ │ │ └── OR1200v1 │ │ │ │ └── or1200v1_hwbkpt.patch │ │ └── Software │ │ │ ├── AdvancedWatchpointControl │ │ │ ├── .classpath │ │ │ ├── .project │ │ │ ├── AdvancedWatchpointControl.jar │ │ │ ├── Makefile │ │ │ ├── README │ │ │ ├── bin │ │ │ │ └── advancedWatchpointControl │ │ │ │ │ └── .keepme │ │ │ ├── doc │ │ │ │ ├── AdvancedWatchpointControl.pdf │ │ │ │ ├── EPL-v1.0.txt │ │ │ │ ├── License_FDL-1.2.txt │ │ │ │ ├── gpl-2.0.txt │ │ │ │ └── src │ │ │ │ │ ├── AdvancedWatchpointControl.odt │ │ │ │ │ ├── awc_block_diagram.odg │ │ │ │ │ ├── awc_ui_controlgroup.png │ │ │ │ │ ├── awc_ui_countersubgroup.png │ │ │ │ │ ├── awc_ui_full.png │ │ │ │ │ ├── awc_ui_serverconnection.png │ │ │ │ │ └── awc_ui_wpsubgroup.png │ │ │ ├── manifest │ │ │ ├── src │ │ │ │ └── advancedWatchpointControl │ │ │ │ │ ├── AdvancedWatchpointControl.java │ │ │ │ │ ├── LogMessageObserver.java │ │ │ │ │ ├── NetworkStatusObserver.java │ │ │ │ │ ├── ReadRegisterTransaction.java │ │ │ │ │ ├── RegisterObserver.java │ │ │ │ │ ├── TargetRunningTransaction.java │ │ │ │ │ ├── TargetTransaction.java │ │ │ │ │ ├── WriteRegisterTransaction.java │ │ │ │ │ ├── guiControlGroup.java │ │ │ │ │ ├── guiCountRegsGroup.java │ │ │ │ │ ├── guiDCRGroup.java │ │ │ │ │ ├── guiServerGroup.java │ │ │ │ │ ├── mainControl.java │ │ │ │ │ ├── networkSystem.java │ │ │ │ │ ├── registerInterpreter.java │ │ │ │ │ ├── rspCoder.java │ │ │ │ │ ├── targetDebugRegisterSet.java │ │ │ │ │ └── targetTransactor.java │ │ │ └── swt.jar │ │ │ └── adv_jtag_bridge │ │ │ ├── Makefile │ │ │ ├── README │ │ │ ├── adv_dbg_commands.c │ │ │ ├── adv_dbg_commands.h │ │ │ ├── adv_jtag_bridge.c │ │ │ ├── adv_jtag_bridge.h │ │ │ ├── altera_virtual_jtag.h │ │ │ ├── bsdl.c │ │ │ ├── bsdl.h │ │ │ ├── bsdl_parse.c │ │ │ ├── bsdl_parse.h │ │ │ ├── cable_common.c │ │ │ ├── cable_common.h │ │ │ ├── cable_ft2232.c │ │ │ ├── cable_ft2232.h │ │ │ ├── cable_ft245.c │ │ │ ├── cable_ft245.h │ │ │ ├── cable_parallel.c │ │ │ ├── cable_parallel.h │ │ │ ├── cable_sim.c │ │ │ ├── cable_sim.h │ │ │ ├── cable_usbblaster.c │ │ │ ├── cable_usbblaster.h │ │ │ ├── cable_usbblaster_ftdi.c │ │ │ ├── cable_xpc_dlc9.c │ │ │ ├── cable_xpc_dlc9.h │ │ │ ├── chain_commands.c │ │ │ ├── chain_commands.h │ │ │ ├── dbg_api.c │ │ │ ├── dbg_api.h │ │ │ ├── doc │ │ │ ├── License_FDL-1.2.txt │ │ │ ├── adv_jtag_bridge.pdf │ │ │ ├── gpl-2.0.txt │ │ │ └── src │ │ │ │ ├── adv_jtag_bridge.odt │ │ │ │ └── ajb_block_diagram.odg │ │ │ ├── errcodes.c │ │ │ ├── errcodes.h │ │ │ ├── except.h │ │ │ ├── gdb-6.8-bz436037-reg-no-longer-active.patch │ │ │ ├── hardware_monitor.c │ │ │ ├── hardware_monitor.h │ │ │ ├── hwp_server.c │ │ │ ├── hwp_server.h │ │ │ ├── jsp_server.c │ │ │ ├── jsp_server.h │ │ │ ├── legacy_dbg_commands.c │ │ │ ├── legacy_dbg_commands.h │ │ │ ├── opencores_tap.h │ │ │ ├── or32_selftest.c │ │ │ ├── or32_selftest.h │ │ │ ├── rsp-server.c │ │ │ ├── rsp-server.h │ │ │ ├── sim_lib │ │ │ ├── Makefile │ │ │ ├── icarus │ │ │ │ └── Makefile │ │ │ ├── modelsim_linux_x86 │ │ │ │ └── Makefile │ │ │ ├── modelsim_win32 │ │ │ │ ├── Makefile │ │ │ │ └── jp-io-vpi.dll │ │ │ └── src │ │ │ │ └── jp-io-vpi.c │ │ │ ├── sim_rtl │ │ │ ├── dbg_comm.v │ │ │ └── dbg_comm_vpi.v │ │ │ ├── spr-defs.h │ │ │ ├── utilities.c │ │ │ └── utilities.h │ ├── arbiter │ │ ├── arbiter_bytebus.v │ │ ├── arbiter_dbus.v │ │ └── arbiter_ibus.v │ ├── bench │ │ ├── or1200_monitor.v │ │ ├── or1200_monitor_defines.v │ │ ├── orpsoc-testbench-defines.v │ │ ├── orpsoc_testbench.v │ │ ├── synthesis-defines.v │ │ ├── test-defines.v │ │ ├── uart_decoder.v │ │ └── wiredelay.v │ ├── clkgen │ │ ├── clkgen.v │ │ ├── clkgen_fpga.v │ │ └── clkgen_sim.v │ ├── dbg_if │ │ ├── dbg_cpu.v │ │ ├── dbg_cpu_defines.v │ │ ├── dbg_cpu_registers.v │ │ ├── dbg_crc32_d1.v │ │ ├── dbg_defines.v │ │ ├── dbg_if.v │ │ ├── dbg_register.v │ │ ├── dbg_wb.v │ │ └── dbg_wb_defines.v │ ├── jtag_tap │ │ ├── README │ │ ├── jtag_tap.v │ │ └── tap_defines.v │ ├── or1200 │ │ ├── or1200_alu.v │ │ ├── or1200_amultp2_32x32.v │ │ ├── or1200_cfgr.v │ │ ├── or1200_cpu.v │ │ ├── or1200_ctrl.v │ │ ├── or1200_dc_fsm.v │ │ ├── or1200_dc_ram.v │ │ ├── or1200_dc_tag.v │ │ ├── or1200_dc_top.v │ │ ├── or1200_defines - Copy.v │ │ ├── or1200_defines.v │ │ ├── or1200_dmmu_tlb.v │ │ ├── or1200_dmmu_top.v │ │ ├── or1200_dpram.v │ │ ├── or1200_dpram_256x32.v │ │ ├── or1200_dpram_32x32.v │ │ ├── or1200_du.v │ │ ├── or1200_except.v │ │ ├── or1200_fpu.v │ │ ├── or1200_fpu_addsub.v │ │ ├── or1200_fpu_arith.v │ │ ├── or1200_fpu_div.v │ │ ├── or1200_fpu_fcmp.v │ │ ├── or1200_fpu_intfloat_conv.v │ │ ├── or1200_fpu_intfloat_conv_except.v │ │ ├── or1200_fpu_mul.v │ │ ├── or1200_fpu_post_norm_addsub.v │ │ ├── or1200_fpu_post_norm_div.v │ │ ├── or1200_fpu_post_norm_intfloat_conv.v │ │ ├── or1200_fpu_post_norm_mul.v │ │ ├── or1200_fpu_pre_norm_addsub.v │ │ ├── or1200_fpu_pre_norm_div.v │ │ ├── or1200_fpu_pre_norm_mul.v │ │ ├── or1200_freeze.v │ │ ├── or1200_genpc.v │ │ ├── or1200_gmultp2_32x32.v │ │ ├── or1200_ic_fsm.v │ │ ├── or1200_ic_ram.v │ │ ├── or1200_ic_tag.v │ │ ├── or1200_ic_top.v │ │ ├── or1200_if.v │ │ ├── or1200_immu_tlb.v │ │ ├── or1200_immu_top.v │ │ ├── or1200_iwb_biu.v │ │ ├── or1200_lsu.v │ │ ├── or1200_mem2reg.v │ │ ├── or1200_mult_mac.v │ │ ├── or1200_operandmuxes.v │ │ ├── or1200_pic.v │ │ ├── or1200_pm.v │ │ ├── or1200_qmem_top.v │ │ ├── or1200_reg2mem.v │ │ ├── or1200_rf.v │ │ ├── or1200_rfram_generic.v │ │ ├── or1200_sb.v │ │ ├── or1200_sb_fifo.v │ │ ├── or1200_spram.v │ │ ├── or1200_spram_1024x32.v │ │ ├── or1200_spram_1024x32_bw.v │ │ ├── or1200_spram_1024x8.v │ │ ├── or1200_spram_128x32.v │ │ ├── or1200_spram_2048x32.v │ │ ├── or1200_spram_2048x32_bw.v │ │ ├── or1200_spram_2048x8.v │ │ ├── or1200_spram_256x21.v │ │ ├── or1200_spram_32_bw.v │ │ ├── or1200_spram_32x24.v │ │ ├── or1200_spram_512x20.v │ │ ├── or1200_spram_64x14.v │ │ ├── or1200_spram_64x22.v │ │ ├── or1200_spram_64x24.v │ │ ├── or1200_sprs.v │ │ ├── or1200_top.v │ │ ├── or1200_tpram_32x32.v │ │ ├── or1200_tt.v │ │ ├── or1200_wb_biu.v │ │ ├── or1200_wbmux.v │ │ └── or1200_xcv_ram32x8d.v │ ├── ram_wb │ │ ├── ram_wb.v │ │ ├── ram_wb_b3.v │ │ ├── sram.vmem │ │ └── timescale.v │ ├── top │ │ ├── orpsoc-defines.v │ │ ├── orpsoc-params.v │ │ ├── orpsoc_top.v │ │ ├── synthesis-defines.v │ │ └── timescale.v │ └── uart16550 │ │ ├── bench │ │ ├── verilog │ │ │ ├── readme.txt │ │ │ ├── test_cases │ │ │ │ └── uart_int.v │ │ │ ├── uart_device.v │ │ │ ├── uart_device_utilities.v │ │ │ ├── uart_log.v │ │ │ ├── uart_test.v │ │ │ ├── uart_testbench.v │ │ │ ├── uart_testbench_defines.v │ │ │ ├── uart_testbench_utilities.v │ │ │ ├── uart_wb_utilities.v │ │ │ ├── vapi.log │ │ │ ├── wb_mast.v │ │ │ ├── wb_master_model.v │ │ │ └── wb_model_defines.v │ │ └── vhdl │ │ │ └── .keepme │ │ ├── doc │ │ ├── CHANGES.txt │ │ ├── UART_spec.pdf │ │ └── src │ │ │ └── UART_spec.doc │ │ ├── fv │ │ └── .keepme │ │ ├── lint │ │ ├── bin │ │ │ └── .keepme │ │ ├── log │ │ │ └── .keepme │ │ ├── out │ │ │ └── .keepme │ │ └── run │ │ │ └── .keepme │ │ ├── rtl │ │ ├── verilog-backup │ │ │ ├── timescale.v │ │ │ ├── uart_defines.v │ │ │ ├── uart_fifo.v │ │ │ ├── uart_receiver.v │ │ │ ├── uart_regs.v │ │ │ ├── uart_top.v │ │ │ ├── uart_transmitter.v │ │ │ └── uart_wb.v │ │ ├── verilog │ │ │ ├── raminfr.v │ │ │ ├── uart_debug_if.v │ │ │ ├── uart_defines.v │ │ │ ├── uart_receiver.v │ │ │ ├── uart_regs.v │ │ │ ├── uart_rfifo.v │ │ │ ├── uart_sync_flops.v │ │ │ ├── uart_tfifo.v │ │ │ ├── uart_top.v │ │ │ ├── uart_transmitter.v │ │ │ └── uart_wb.v │ │ └── vhdl │ │ │ └── .keepme │ │ ├── sim │ │ ├── gate_sim │ │ │ ├── bin │ │ │ │ └── .keepme │ │ │ ├── log │ │ │ │ └── .keepme │ │ │ ├── out │ │ │ │ └── .keepme │ │ │ ├── run │ │ │ │ └── .keepme │ │ │ └── src │ │ │ │ └── .keepme │ │ └── rtl_sim │ │ │ ├── bin │ │ │ ├── nc.scr │ │ │ └── sim.tcl │ │ │ ├── log │ │ │ ├── .keepme │ │ │ ├── uart_interrupts_report.log │ │ │ └── uart_interrupts_verbose.log │ │ │ ├── out │ │ │ └── .keepme │ │ │ ├── run │ │ │ ├── run_signalscan │ │ │ ├── run_sim │ │ │ └── run_sim.scr │ │ │ └── src │ │ │ └── .keepme │ │ └── syn │ │ ├── bin │ │ └── .keepme │ │ ├── log │ │ └── .keepme │ │ ├── out │ │ └── .keepme │ │ ├── run │ │ └── .keepme │ │ └── src │ │ └── .keepme ├── glbl.v └── runVSIM.sh ├── software ├── bareBench │ ├── FFT │ │ ├── Makefile │ │ ├── ddc.h │ │ ├── ddcmath.h │ │ ├── fftmisc.c │ │ ├── fourier.h │ │ ├── fourierf.c │ │ └── main.c │ ├── bareBench.h │ ├── basicmath │ │ ├── Makefile │ │ ├── basicmath_small.c │ │ ├── cubic.c │ │ ├── isqrt.c │ │ ├── pi.h │ │ ├── rad2deg.c │ │ ├── round.h │ │ ├── snipmath.h │ │ └── sniptype.h │ ├── dijkstra │ │ ├── Makefile │ │ ├── dijkstra_large.c │ │ ├── input.dat │ │ └── input.h │ ├── jpeg │ │ ├── input_large.jpg │ │ ├── input_large.ppm │ │ ├── input_small.jpg │ │ ├── input_small.ppm │ │ ├── jpeg-6a │ │ │ ├── Makefile │ │ │ ├── Makefile.new │ │ │ ├── README │ │ │ ├── ansi2knr.1 │ │ │ ├── ansi2knr.c │ │ │ ├── cderror.h │ │ │ ├── cdjpeg.c │ │ │ ├── cdjpeg.h │ │ │ ├── cjpeg.1 │ │ │ ├── cjpeg.S │ │ │ ├── cjpeg.c │ │ │ ├── cjpeg.vmem │ │ │ ├── ckconfig.c │ │ │ ├── coderules.doc │ │ │ ├── configure │ │ │ ├── djpeg.1 │ │ │ ├── djpeg.c │ │ │ ├── example.c │ │ │ ├── filelist.doc │ │ │ ├── install.doc │ │ │ ├── jcapimin.c │ │ │ ├── jcapistd.c │ │ │ ├── jccoefct.c │ │ │ ├── jccolor.c │ │ │ ├── jcdctmgr.c │ │ │ ├── jchuff.c │ │ │ ├── jchuff.h │ │ │ ├── jcinit.c │ │ │ ├── jcmainct.c │ │ │ ├── jcmarker.c │ │ │ ├── jcmaster.c │ │ │ ├── jcomapi.c │ │ │ ├── jconfig.bcc │ │ │ ├── jconfig.cfg │ │ │ ├── jconfig.dj │ │ │ ├── jconfig.doc │ │ │ ├── jconfig.h │ │ │ ├── jconfig.manx │ │ │ ├── jconfig.mc6 │ │ │ ├── jconfig.sas │ │ │ ├── jconfig.st │ │ │ ├── jconfig.vms │ │ │ ├── jconfig.wat │ │ │ ├── jcparam.c │ │ │ ├── jcphuff.c │ │ │ ├── jcprepct.c │ │ │ ├── jcsample.c │ │ │ ├── jctrans.c │ │ │ ├── jdapimin.c │ │ │ ├── jdapistd.c │ │ │ ├── jdatadst.c │ │ │ ├── jdatasrc.c │ │ │ ├── jdcoefct.c │ │ │ ├── jdcolor.c │ │ │ ├── jdct.h │ │ │ ├── jddctmgr.c │ │ │ ├── jdhuff.c │ │ │ ├── jdhuff.h │ │ │ ├── jdinput.c │ │ │ ├── jdmainct.c │ │ │ ├── jdmarker.c │ │ │ ├── jdmaster.c │ │ │ ├── jdmerge.c │ │ │ ├── jdphuff.c │ │ │ ├── jdpostct.c │ │ │ ├── jdsample.c │ │ │ ├── jdtrans.c │ │ │ ├── jerror.c │ │ │ ├── jerror.h │ │ │ ├── jfdctflt.c │ │ │ ├── jfdctfst.c │ │ │ ├── jfdctint.c │ │ │ ├── jidctflt.c │ │ │ ├── jidctfst.c │ │ │ ├── jidctint.c │ │ │ ├── jidctred.c │ │ │ ├── jinclude.h │ │ │ ├── jmemansi.c │ │ │ ├── jmemdos.c │ │ │ ├── jmemdosa.asm │ │ │ ├── jmemmac.c │ │ │ ├── jmemmgr.c │ │ │ ├── jmemname.c │ │ │ ├── jmemnobs.c │ │ │ ├── jmemsys.h │ │ │ ├── jmorecfg.h │ │ │ ├── jpegint.h │ │ │ ├── jpeglib.h │ │ │ ├── jpegtran.1 │ │ │ ├── jpegtran.c │ │ │ ├── jquant1.c │ │ │ ├── jquant2.c │ │ │ ├── jutils.c │ │ │ ├── jversion.h │ │ │ ├── libjpeg.doc │ │ │ ├── makcjpeg.st │ │ │ ├── makdjpeg.st │ │ │ ├── makefile.ansi │ │ │ ├── makefile.bcc │ │ │ ├── makefile.cfg │ │ │ ├── makefile.dj │ │ │ ├── makefile.manx │ │ │ ├── makefile.mc6 │ │ │ ├── makefile.mms │ │ │ ├── makefile.sas │ │ │ ├── makefile.unix │ │ │ ├── makefile.vms │ │ │ ├── makefile.wat │ │ │ ├── makljpeg.st │ │ │ ├── maktjpeg.st │ │ │ ├── makvms.opt │ │ │ ├── rdbmp.c │ │ │ ├── rdcolmap.c │ │ │ ├── rdgif.c │ │ │ ├── rdjpgcom.1 │ │ │ ├── rdjpgcom.c │ │ │ ├── rdppm.c │ │ │ ├── rdrle.c │ │ │ ├── rdswitch.c │ │ │ ├── rdtarga.c │ │ │ ├── structure.doc │ │ │ ├── testimg.gif │ │ │ ├── testimg.jpg │ │ │ ├── testimg.ppm │ │ │ ├── testimgp.jpg │ │ │ ├── testorig.jpg │ │ │ ├── testprog.jpg │ │ │ ├── usage.doc │ │ │ ├── wizard.doc │ │ │ ├── wrbmp.c │ │ │ ├── wrgif.c │ │ │ ├── wrjpgcom.1 │ │ │ ├── wrjpgcom.c │ │ │ ├── wrppm.c │ │ │ ├── wrrle.c │ │ │ └── wrtarga.c │ │ ├── runme_large.sh │ │ └── runme_small.sh │ ├── sha │ │ ├── Makefile │ │ ├── input.h │ │ ├── sha.c │ │ ├── sha.h │ │ └── sha_driver.c │ └── stringsearch │ │ ├── Makefile │ │ ├── bmhasrch.c │ │ ├── bmhisrch.c │ │ ├── bmhsrch.c │ │ ├── pbmsrch_large.c │ │ └── search.h ├── ml509DRAM.S ├── ml509SRAM.S ├── picojpeg │ ├── Makefile │ ├── bintoc.c │ ├── michigan.jpg │ ├── picojpeg.c │ ├── picojpeg.h │ └── picojpegtest.c └── utils │ ├── Makefile │ ├── bin2c.c │ ├── bin2flimg.c │ ├── bin2hex.c │ ├── bin2srec.c │ └── bin2vmem.c └── triggerSoftware ├── Makefile ├── README.md ├── commonFuncs.h ├── histogram.gp ├── idle.c ├── makeHists.sh ├── math_user.c └── spr_defs.h /.gitignore: -------------------------------------------------------------------------------- 1 | *.DS_Store 2 | *.rpt 3 | *.nl.v 4 | *.sdc 5 | asic_hardware/synth/.pbs* 6 | asic_hardware/synth/.st* 7 | -------------------------------------------------------------------------------- /A2Sim.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/A2Sim.JPG -------------------------------------------------------------------------------- /A2_SP_16.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/A2_SP_16.pdf -------------------------------------------------------------------------------- /A2_SP_16_Slides.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/A2_SP_16_Slides.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # A2 2 | 3 | ## Using simulation to determine victim wire toggle rates 4 | 5 | Comment-out debug options in fpga_hardware\cores\top\orpsoc-defines.v 6 | For example, you should have 7 | 8 | `// define ADV_DEBUG` 9 | `// define JTAG_DEBUG` 10 | 11 | Then make sure the clock generator is the simple one required for simulation (without needing vendor-specific libraries), see `fpga_hardware\cores\clkgen\` 12 | 13 | Open `ModelSim` GUI program 14 | Open the project file `a2.mpf` 15 | Compile all project files (may need to add a `work` library) 16 | Close `ModelSim` 17 | `sh runVSIM.sh` 18 | then type `run -all` to start simulation 19 | The simulation will create a compressed VCD file in the same directory it is run from (e.g., a2.vcd.gz) 20 | To edit what signals the VCD tracks or the name of the VCD file edit `fpga_hardware\cores\bench\orpsoc_testbench.v` 21 | 22 | See `A2Sim.jpg` for an example of a successful simulation. Note that the simulation will not stop on its own as the program being simulated never stops. 23 | 24 | This runs simulation from the command line, but it is also possible to run the simulation from inside ModelSim's GUI. 25 | 26 | ## Build an FPGA bitstream 27 | 28 | The provided scripts assume that you are using Xilinx ISE and the path to the command line tools has been added to your system's `PATH` variable. 29 | 30 | Select (via uncommenting) the appropriate debug option in `fpga_hardware\cores\top\orpsoc-defines.v`. If you don't know which debug option to select, you will need to read-up on the two debugging options as well as look at how I have them implemented in the source files. The easiest path forward is to give up on debugging using JTAG and hope that your programs runs well enough to output text to the serial console :). 31 | 32 | Then make sure the clock generator is the more complex one that takes advantage of FPGA primitives, see `fpga_hardware\cores\clkgen\`. 33 | 34 | `make all` 35 | 36 | ## Changing the program loaded into memory 37 | 38 | Now that you have simulated the provided program or built and run an FPGA implementation of the default program, you may want to simulate/run your own programs. In order to do that, you will need to write (in C or assembly), compile (using the OR1K gcc toolchain and newlib), and convert the resulting binary into a vmem file suitable for loading directly loading to memory. 39 | 40 | Here are the basic steps of the compile and conversion process: 41 | * Compile your program using the [OR1K toolchain](http://opencores.org/or1k/OpenRISC_GNU_tool_chain) 42 | * Convert the resulting binary file to a bin file using `or1k-elf-objdump -O binary` 43 | * Convert the bin file to a vmem file using the `bin2vmem` utility in `software/utils` 44 | * Rename the resulting sram file `sram.vmem` and replace the file in `fpga_hardware/cores/ram_wb` 45 | * If you get illegal instruction exceptions (0x700), you may need to move `sram.vmem` to `fpga_hardware/` 46 | -------------------------------------------------------------------------------- /asic_hardware/Makefile: -------------------------------------------------------------------------------- 1 | include hdl_sources.list 2 | 3 | SYNTH_CC. = genus 4 | SYNTH_FLAGS = -legacy_ui -files 5 | 6 | .PHONY: synth clean 7 | 8 | synth: $(HDL_SOURCES) 9 | genus -legacy_ui -files ./synth/cadence.tcl 10 | 11 | clean: 12 | rm -Rf /synth/fv 13 | rm -Rf /synth/synth_reports 14 | rm genus.* 15 | rm /synth/genus.* 16 | -------------------------------------------------------------------------------- /asic_hardware/par/MAL_TOP.io: -------------------------------------------------------------------------------- 1 | ############################################################### 2 | # Generated by: Cadence Encounter 10.13-s209_1 3 | # OS: Linux x86_64(Host ID vlsipool-f02.eecs.umich.edu) 4 | # Generated on: Sat Mar 3 03:07:43 2012 5 | # Design: top_wpad 6 | # Command: saveIoFile -locations top_wpad.save.io 7 | ############################################################### 8 | 9 | (globals 10 | version = 3 11 | io_order = default 12 | ) 13 | (iopad 14 | (right 15 | (locals row_name=rightRow space=10 ring_number=1) 16 | (inst name="PAD_POWER_VDD1" offset=30 place_status=fixed) 17 | (inst name="PAD_u1_digout" place_status=fixed) 18 | (inst name="PAD_POWER_VSS1" place_status=fixed) 19 | (inst name="PAD_POWER_DVDD1" place_status=fixed) 20 | (inst name="PAD_POWER_DVSS1" place_status=fixed) 21 | (inst name="PAD_u0_digout" place_status=fixed) 22 | (inst name="PAD_u0_digin" place_status=fixed) 23 | (inst name="PAD_u1_digin" place_status=fixed) 24 | (inst name="PAD_u2_digin" place_status=fixed) 25 | (inst name="PAD_u3_digin" place_status=fixed) 26 | ) 27 | ) 28 | # (topright 29 | # (inst name="PADRING_CORNER_TR" orientation=R0 ) 30 | # ) 31 | # (bottomright 32 | # (inst name="PADRING_CORNER_BR" orientation=MY ) 33 | # ) 34 | -------------------------------------------------------------------------------- /asic_hardware/verilog/orpsoc/jtag_tap/README: -------------------------------------------------------------------------------- 1 | JTAG TAP RTL 2 | 3 | See the project's page on OpenCores for more information: 4 | http://opencores.org/project,jtag 5 | 6 | -------------------------------------------------------------------------------- /asic_hardware/verilog/orpsoc/ram_wb_sc/mem_scan.v: -------------------------------------------------------------------------------- 1 | module mem_scan( 2 | // Control inputs from scan 3 | scan_mem_sel, mem_use_scan, mem_trigger, mem_scan_reset_n, 4 | // Input from Memory 5 | Q, 6 | // Outputs to the memory 7 | mem_addr, mem_d, mem_bwen_n, mem_cen_n, 8 | 9 | // Inputs from the scan 10 | scan_addr, scan_d, scan_wen_n, scan_cen_n, 11 | // Output to the scan 12 | scan_q, 13 | 14 | // Inputs from the core 15 | A, D, BWE_n, CE_n, 16 | CLK); 17 | 18 | parameter addrbits=16; 19 | parameter dqbits=32; 20 | 21 | input scan_mem_sel; 22 | 23 | input [addrbits-1:0] A; 24 | input [addrbits-1:0] scan_addr; 25 | output [addrbits-1:0] mem_addr; 26 | 27 | input [dqbits-1:0] D; 28 | input [dqbits-1:0] scan_d; 29 | output [dqbits-1:0] mem_d; 30 | 31 | input BWE_n; 32 | input scan_wen_n; 33 | output mem_bwen_n; 34 | 35 | input CE_n; 36 | input scan_cen_n; 37 | output mem_cen_n; 38 | 39 | input [dqbits-1:0] Q; 40 | output reg [dqbits-1:0] scan_q; 41 | 42 | input mem_use_scan; 43 | input mem_trigger; 44 | input CLK; 45 | input mem_scan_reset_n; 46 | 47 | assign mem_addr = mem_use_scan ? scan_addr : A; 48 | assign mem_d = mem_use_scan ? scan_d : D; 49 | assign mem_bwen_n = mem_use_scan ? {dqbits{scan_wen_n}} : BWE_n; 50 | reg access_ce; 51 | reg access_ce_last; 52 | assign mem_cen_n = mem_use_scan ? ~(~scan_cen_n & access_ce) : CE_n; 53 | 54 | reg [3:0] mem_trigger_sync; 55 | always @(posedge CLK or negedge mem_scan_reset_n) 56 | begin 57 | if(!mem_scan_reset_n) 58 | begin 59 | /*AUTORESET*/ 60 | // Beginning of autoreset for uninitialized flops 61 | access_ce <= 1'h0; 62 | access_ce_last <= 1'h0; 63 | mem_trigger_sync <= 4'h0; 64 | scan_q <= {dqbits{1'b0}}; 65 | // End of automatics 66 | end 67 | else 68 | begin 69 | mem_trigger_sync <= {mem_trigger_sync[2:0], mem_trigger}; 70 | access_ce <= (mem_trigger_sync[3] ^ mem_trigger_sync[2]) & scan_mem_sel; 71 | access_ce_last <= access_ce & ~scan_cen_n; 72 | if(access_ce_last) begin 73 | scan_q <= Q; 74 | end 75 | end 76 | end 77 | 78 | endmodule 79 | 80 | -------------------------------------------------------------------------------- /asic_hardware/verilog/orpsoc/ram_wb_sc/mem_tieoffs.v: -------------------------------------------------------------------------------- 1 | 2 | // RAM block for the main memory 3 | module sram_32Kx32_wrapper ( 4 | // Outputs 5 | Q, 6 | // Inputs 7 | CLK, CE_n, BWE_n, A, D, 8 | 9 | // Scan chain test inputs 10 | scan_mem_sel, mem_use_scan, mem_trigger, mem_scan_reset_n, 11 | scan_addr, scan_d, scan_wen_n, scan_cen_n,scan_q, clk_scan, scan_EMA 12 | ); 13 | 14 | input CLK; 15 | input clk_scan; 16 | input [14:0] A; 17 | input [31:0] D; 18 | 19 | input BWE_n; 20 | input CE_n; 21 | input [2:0] scan_EMA; 22 | output [31:0] Q; 23 | 24 | // Scan chain test inputs/outputs 25 | input scan_mem_sel; 26 | input mem_use_scan; 27 | input mem_trigger; 28 | input mem_scan_reset_n; 29 | input [14:0] scan_addr; 30 | input [31:0] scan_d; 31 | input scan_wen_n; 32 | input scan_cen_n; 33 | output [31:0] scan_q; 34 | 35 | // Wire definition 36 | wire [14:0] mem_addr; 37 | wire [31:0] mem_d; 38 | wire mem_bwen_n; 39 | wire mem_cen_n; 40 | 41 | mem_scan #(.addrbits(15), .dqbits(32)) mem_scan_inst ( 42 | // Control inputs from scan 43 | .scan_mem_sel(scan_mem_sel), .mem_use_scan(mem_use_scan), 44 | .mem_trigger(mem_trigger), .mem_scan_reset_n(mem_scan_reset_n), 45 | // Input from Memory 46 | .Q(Q), 47 | // Outputs to the memory 48 | .mem_addr(mem_addr), .mem_d(mem_d), 49 | .mem_bwen_n(mem_bwen_n), .mem_cen_n(mem_cen_n), 50 | // Inputs from the scan 51 | .scan_addr(scan_addr), .scan_d(scan_d), 52 | .scan_wen_n(scan_wen_n), .scan_cen_n(scan_cen_n), 53 | // Output to the scan 54 | .scan_q(scan_q), 55 | // Inputs from the core 56 | .A(A), .D(D), .BWE_n(BWE_n), .CE_n(CE_n), 57 | .CLK(clk_scan)); 58 | 59 | wire clk_mem = mem_use_scan ? clk_scan : CLK; 60 | 61 | sram_32Kx32 mem_block_32K_32 ( 62 | .Q(Q), 63 | .CLK(clk_mem), 64 | .CEN(mem_cen_n), 65 | .WEN(mem_bwen_n), 66 | .A(mem_addr), 67 | .D(mem_d), 68 | .EMA(scan_EMA), 69 | .RETN(1'b1)); 70 | 71 | 72 | endmodule // sram_32Kx32_wrapper 73 | 74 | -------------------------------------------------------------------------------- /asic_hardware/verilog/orpsoc/top/synthesis-defines.v: -------------------------------------------------------------------------------- 1 | // `define SYNTHESIS 2 | // `define XILINX 3 | 4 | -------------------------------------------------------------------------------- /chipDesign/apr/MAL_TOP.io: -------------------------------------------------------------------------------- 1 | ############################################################### 2 | # Generated by: Cadence Encounter 10.13-s209_1 3 | # OS: Linux x86_64(Host ID vlsipool-f02.eecs.umich.edu) 4 | # Generated on: Sat Mar 3 03:07:43 2012 5 | # Design: top_wpad 6 | # Command: saveIoFile -locations top_wpad.save.io 7 | ############################################################### 8 | 9 | (globals 10 | version = 3 11 | io_order = default 12 | ) 13 | (iopad 14 | (right 15 | (locals row_name=leftRow space=15 ring_number=1) 16 | (inst name="PAD_u3_digin" offset=0 place_status=fixed) 17 | (inst name="PAD_u4_digin" place_status=fixed) 18 | (inst name="PAD_u5_digin" place_status=fixed) 19 | (inst name="PAD_u6_digin" place_status=fixed) 20 | (inst name="PAD_u7_digin" place_status=fixed) 21 | (inst name="PAD_u1_digout" place_status=fixed) 22 | (inst name="PAD_POWER_VSS1" place_status=fixed) 23 | (inst name="PAD_POWER_VDD1" place_status=fixed) 24 | (inst name="PAD_u4_digout" place_status=fixed) 25 | (inst name="PAD_POWER_DVDD1" place_status=fixed) 26 | (inst name="PAD_POWER_DVSS1" place_status=fixed) 27 | (inst name="PAD_u0_digin" place_status=fixed) 28 | (inst name="PAD_u1_digin" place_status=fixed) 29 | (inst name="PAD_u2_digin" place_status=fixed) 30 | (inst name="PAD_u0_digout" place_status=fixed) 31 | (inst name="PAD_ANA1" place_status=fixed) 32 | (inst name="PAD_POWER_VDD2" place_status=fixed) 33 | (inst name="PAD_POWER_AVSS" place_status=fixed) 34 | (inst name="PAD_POWER_AVDD" place_status=fixed) 35 | (inst name="PAD_u3_digout" place_status=fixed) 36 | ) 37 | # (topright 38 | # (inst name="PADRING_CORNER_TR" orientation=R0 ) 39 | # ) 40 | # (bottomright 41 | # (inst name="PADRING_CORNER_BR" orientation=MY ) 42 | # ) 43 | -------------------------------------------------------------------------------- /chipDesign/netlist/charge_pump_schmitt.src.net: -------------------------------------------------------------------------------- 1 | ************************************************************************ 2 | * auCdl Netlist: 3 | * 4 | * Library Name: MAL_BLOCK 5 | * Top Cell Name: charge_pump_schmitt 6 | * View Name: schematic 7 | * Netlisted on: May 29 02:49:52 2015 8 | ************************************************************************ 9 | 10 | *.EQUATION 11 | *.SCALE METER 12 | *.MEGA 13 | .PARAM 14 | 15 | 16 | 17 | ************************************************************************ 18 | * Library Name: MAL_BLOCK 19 | * Cell Name: charge_pump_schmitt 20 | * View Name: schematic 21 | ************************************************************************ 22 | 23 | .SUBCKT charge_pump_schmitt OUT Signal VDD VSS 24 | *.PININFO Signal:I OUT:O VDD:B VSS:B 25 | MM11 vcap VSS VSS VSS nch l=200n w=550.0n m=1 26 | MM0 net8 Signal vcap VSS nch l=100n w=120.0n m=1 27 | MM15 net8 Signal VDD VDD pch_hvt l=100n w=120.0n m=1 28 | MM10 VSS OUT net17 VDD pch l=100n w=120.0n m=1 29 | *MM14 VDD net8 VDD VDD pch_hvt l=100n w=120.0n m=1 30 | MM1 net028 vcap VSS VSS nch_25ud18 l=260n w=400n m=1 31 | MM4 OUT vcap net028 VSS nch_25ud18 l=260n w=400n m=1 32 | MM9 VSS vcap VSS VSS nch_25ud18 l=600n w=510.0n m=5 33 | MM7 VDD OUT net028 VSS nch_hvt l=200n w=120.0n m=1 34 | MM5 net17 vcap VDD VDD pch_25ud18 l=260.0n w=400n m=1 35 | MM6 OUT vcap net17 VDD pch_25ud18 l=260.0n w=400n m=1 36 | .ENDS 37 | 38 | -------------------------------------------------------------------------------- /chipDesign/netlist/charge_pump_schmitt_no_IO.src.net: -------------------------------------------------------------------------------- 1 | ************************************************************************ 2 | * auCdl Netlist: 3 | * 4 | * Library Name: QQ 5 | * Top Cell Name: charge_pump_schmitt_no_IO 6 | * View Name: schematic 7 | * Netlisted on: May 28 02:13:53 2015 8 | ************************************************************************ 9 | 10 | *.EQUATION 11 | *.SCALE METER 12 | *.MEGA 13 | .PARAM 14 | 15 | 16 | 17 | ************************************************************************ 18 | * Library Name: QQ 19 | * Cell Name: charge_pump_schmitt_no_IO 20 | * View Name: schematic 21 | ************************************************************************ 22 | 23 | .SUBCKT charge_pump_schmitt_no_IO OUT Signal VDD VSS 24 | *.PININFO Signal:I OUT:O VDD:B VSS:B 25 | MM6 net033 vcap VSS VSS nch_hvt l=120.0n w=120.0n m=1 26 | MM5 OUT vcap net033 VSS nch_hvt l=120.0n w=120.0n m=1 27 | *MM14 VDD net04 VDD VDD pch_hvt l=60n w=120.0n m=1 28 | MM21 VSS OUT net09 VDD pch_hvt l=100n w=500n m=1 29 | MM3 net04 Signal VDD VDD pch_hvt l=100n w=120.0n m=1 30 | MM1 VSS vcap VSS VSS nch l=200n w=300n m=6 31 | MM10 vcap VSS VSS VSS nch l=200n w=530.0n m=1 32 | MM0 net04 Signal vcap VSS nch l=250.0n w=200n m=1 33 | MM7 VDD OUT net033 VSS nch_hvt l=200n w=120.0n m=1 34 | MM2 net09 vcap VDD VDD pch l=60n w=120.0n m=1 35 | MM4 OUT vcap net09 VDD pch l=60n w=120.0n m=1 36 | MM8 VSS vcap VSS VDD pch l=200n w=300n m=6 37 | .ENDS 38 | 39 | -------------------------------------------------------------------------------- /chipDesign/synth/common/avoid_case_sensitive.sh: -------------------------------------------------------------------------------- 1 | 2 | sed -i -e 's/\/netsm_\1/g' *.v 3 | sed -i -e 's/\/netlg_\1/g' *.v 4 | 5 | 6 | -------------------------------------------------------------------------------- /chipDesign/synth/common/common.tcl: -------------------------------------------------------------------------------- 1 | # common.tcl setup library files 2 | 3 | set SYNOPSYS [get_unix_variable SYNOPSYS] 4 | #set lib_root /afs/eecs.umich.edu/kits/ARM/TSMC_65lp/arm_2013q1/TS25LB021-FB-00000-r0p0-00rel0/arm/tsmc/cln65lp/sc9_base_hvt/r0p0 5 | set lib_root /afs/eecs.umich.edu/kits/ARM/TSMC_65gp/arm_2010q1/rvt_sc-adv10-v21_2008q2v1/aci/sc-ad10/synopsys 6 | 7 | set search_path [list "." "../../verilog/top" "../../sram" "../../rf" ${SYNOPSYS}/libraries/syn ${lib_root} /afs/eecs.umich.edu/kits/ARM/TSMC_65gp/arm_2010q1/tpdn65lpnv2_140b/digital/Front_End/timing_power_noise/NLDM/tpdn65lpnv2_140b ] 8 | 9 | #set link_library "* scadv10_cln65gp_lvt_tt_1p0v_25c.db" 10 | #set target_library "scadv10_cln65gp_lvt_tt_1p0v_25c.db " 11 | 12 | set synthetic_library [list "dw_foundation.sldb"] 13 | 14 | set link_library "* scadv10_cln65gp_rvt_tt_1p0v_25c.db tpdn65lpnv2tc.db sram_32Kx32_tt_1p0v_25c_syn.db rf_32x32_tt_1p0v_25c_syn.db" 15 | 16 | set target_library "scadv10_cln65gp_rvt_tt_1p0v_25c.db tpdn65lpnv2tc.db" 17 | 18 | #set hdlin_report_inferred_modules true 19 | 20 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /chipDesign/synth/common/namingrules.tcl: -------------------------------------------------------------------------------- 1 | # This script renames nets into legal verilog names. 2 | # Source at the beginning of your main script: 3 | # source -verbose "../../tcl/naming_rules.syn.tcl" 4 | 5 | define_name_rules umich_naming_rules -allowed {a-zA-Z0-9_} \ 6 | -max_length 256 -reserved_words \ 7 | [list "always" "and" "assign" "begin" "buf" "bufif0" "bufif1" "case" "casex" \ 8 | "casez" "cmos" "deassign" "default" "defparam" "disable" "edge" "else" \ 9 | "end" "endcase" "endfunction" "endmodule" "endprimitive" "endspecify" \ 10 | "endtable" "endtask" "event" "for" "force" "forever" "fork" "function" \ 11 | "highz0" "highz1" "if" "initial" "inout" "input" "integer" "join" \ 12 | "large" "macromodule" "medium" "module" "nand" "negedge" "nmos" "nor" \ 13 | "not" "notif0" "notif1" "or" "output" "pmos" "posedge" "primitive" \ 14 | "pull0" "pull1" "pulldown" "pullup" "rcmos" "reg" "release" "repeat" \ 15 | "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalered" "small" \ 16 | "specify" "specparam" "strong0" "strong1" "supply0" "supply1" "table" \ 17 | "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" \ 18 | "trior" "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" \ 19 | "xnor" "xor" "abs" "access" "after" "alias" "all" "and" "architecture" \ 20 | "array" "assert" "attribute" "begin" "block" "body" "buffer" "bus" \ 21 | "case" "component" "configuration" "constant" "disconnect" "downto" \ 22 | "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" \ 23 | "generic" "guarded" "if" "in" "inout" "is" "label" "library" "linkage" \ 24 | "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" \ 25 | "open" "or" "others" "out" "package" "port" "procedure" "process" \ 26 | "range" "record" "register" "rem" "report" "return" "select" "severity" \ 27 | "signal" "subtype" "then" "to" "transport" "type" "units" "until" "use" \ 28 | "variable" "wait" "when" "while" "with" "xor"] \ 29 | -case_insensitive \ 30 | -first_restricted "_" \ 31 | -map {{{"*cell*","U"}, {"*-return","RET"}}} \ 32 | -collapse_name_space \ 33 | -equal_ports_nets \ 34 | -inout_ports_equal_nets 35 | 36 | change_names -rules umich_naming_rules -verbose -hierarchy 37 | 38 | 39 | -------------------------------------------------------------------------------- /chipDesign/synth/orpsoc_top.tcl: -------------------------------------------------------------------------------- 1 | # OpenRISC Synthesis Script 2 | # Written by Mojtaba Ebrahimi 3 | 4 | source -verbose "./common/common.tcl" 5 | 6 | set base_dir "../../fpga_hardware/cores/or1200" 7 | set top_level "orpsoc_top" 8 | 9 | source -verbose "./orpsoc_top_read_verilog.tcl" 10 | 11 | link 12 | 13 | set clk_period 3 14 | set clk_uncertainty 0.3 15 | set clk_transition 0.1 16 | set clk_latency 0.05 17 | 18 | set clk_port "sys_clk_in_p" 19 | set clk_name "CLK" 20 | create_clock -name $clk_name -period $clk_period $clk_port 21 | 22 | set typical_input_delay 0.00 23 | set typical_output_delay 0.200 24 | set typical_wire_load 0.2 25 | 26 | #set_operating_conditions tt28_1.00V_25C -library C32_SC_12_CORE_LSL 27 | set_wire_load_model -name ZeroWireload 28 | #set_wire_load_mode enclosed 29 | 30 | set_clock_latency $clk_latency [all_clocks] 31 | set_clock_transition $clk_transition [all_clocks] 32 | set_clock_uncertainty -setup 0.1 [all_clocks] 33 | set_clock_uncertainty -hold $clk_uncertainty [all_clocks] 34 | set_ideal_network [get_ports sys_clk_in_p] 35 | 36 | set_max_transition 0.100 $top_level 37 | set_max_fanout 20 $top_level 38 | 39 | set_driving_cell -lib_cell BUFX1BA10TR [all_inputs] 40 | set_driving_cell -lib_cell BUFX4BA10TR [find port $clk_port] 41 | 42 | #set_input_delay $typical_input_delay -clock $clk_name [all_inputs] 43 | #remove_input_delay -clock $clk_name [find port $clk_port] 44 | set_output_delay $typical_output_delay -clock $clk_name [all_outputs] 45 | 46 | set_load $typical_wire_load [all_outputs] 47 | 48 | set_fix_hold [all_clocks] 49 | 50 | report_ideal_network 51 | 52 | 53 | #ensure no net connect to multiple ports 54 | set_fix_multiple_port_nets -all -buffer_constants 55 | check_design 56 | 57 | uniquify -dont_skip_empty_designs 58 | #ungroup -all -flatten 59 | 60 | compile -map_effort high 61 | #compile_ultra 62 | compile -inc -only_design_rule 63 | 64 | source -verbose "./common/namingrules.tcl" 65 | 66 | # Generate structural verilog netlist 67 | write -hierarchy -format verilog -output "${top_level}.nl.v" 68 | 69 | # Generate Standard Delay Format (SDF) file 70 | write_sdf -context verilog "${top_level}.dc.sdf" 71 | 72 | # Write SDC 73 | write_sdc -nosplit -version 1.3 "${top_level}.sdc" 74 | 75 | # Write DDC 76 | write_file -format ddc -hierarchy -output "${top_level}.ddc" 77 | 78 | ##### Create report (timing, cells, etc...) 79 | set rpt_file "${top_level}.dc.rpt" 80 | set maxpaths 20 81 | check_design > $rpt_file 82 | report_area >> ${rpt_file} 83 | report_resources -hierarchy > ${rpt_file} 84 | #report_power -hier -analysis_effort medium >> ${rpt_file} 85 | report_design >> ${rpt_file} 86 | report_cell >> ${rpt_file} 87 | report_port -verbose >> ${rpt_file} 88 | #report_compile_options >> ${rpt_file} 89 | report_constraint -all_violators -verbose >> ${rpt_file} 90 | report_timing -path full -delay max -max_paths $maxpaths -nworst 10 >> ${rpt_file} 91 | report_timing -path full -delay min -max_paths $maxpaths -nworst 10 >> ${rpt_file} 92 | report_timing_requirements >> ${rpt_file} 93 | 94 | 95 | report_timing -from { or1200_top0/or1200_cpu/or1200_ctrl/ex_branch_op_reg_0_/Q } -to { or1200_top0/or1200_cpu/or1200_sprs/sr_reg_reg_0_/D } -nworst 20 -max_paths 20 -unique_pins >> paths.rpt 96 | -------------------------------------------------------------------------------- /chipDesign/verilog/mem_wrapper/mem_scan.v: -------------------------------------------------------------------------------- 1 | module mem_scan( 2 | // Control inputs from scan 3 | scan_mem_sel, mem_use_scan, mem_trigger, mem_scan_reset_n, 4 | // Input from Memory 5 | Q, 6 | // Outputs to the memory 7 | mem_addr, mem_d, mem_bwen_n, mem_cen_n, 8 | 9 | // Inputs from the scan 10 | scan_addr, scan_d, scan_wen_n, scan_cen_n, 11 | // Output to the scan 12 | scan_q, 13 | 14 | // Inputs from the core 15 | A, D, BWE_n, CE_n, 16 | CLK); 17 | 18 | parameter addrbits=16; 19 | parameter dqbits=32; 20 | 21 | input scan_mem_sel; 22 | 23 | input [addrbits-1:0] A; 24 | input [addrbits-1:0] scan_addr; 25 | output [addrbits-1:0] mem_addr; 26 | 27 | input [dqbits-1:0] D; 28 | input [dqbits-1:0] scan_d; 29 | output [dqbits-1:0] mem_d; 30 | 31 | input BWE_n; 32 | input scan_wen_n; 33 | output mem_bwen_n; 34 | 35 | input CE_n; 36 | input scan_cen_n; 37 | output mem_cen_n; 38 | 39 | input [dqbits-1:0] Q; 40 | output reg [dqbits-1:0] scan_q; 41 | 42 | input mem_use_scan; 43 | input mem_trigger; 44 | input CLK; 45 | input mem_scan_reset_n; 46 | 47 | assign mem_addr = mem_use_scan ? scan_addr : A; 48 | assign mem_d = mem_use_scan ? scan_d : D; 49 | assign mem_bwen_n = mem_use_scan ? {dqbits{scan_wen_n}} : BWE_n; 50 | reg access_ce; 51 | reg access_ce_last; 52 | assign mem_cen_n = mem_use_scan ? ~(~scan_cen_n & access_ce) : CE_n; 53 | 54 | reg [3:0] mem_trigger_sync; 55 | always @(posedge CLK or negedge mem_scan_reset_n) 56 | begin 57 | if(!mem_scan_reset_n) 58 | begin 59 | /*AUTORESET*/ 60 | // Beginning of autoreset for uninitialized flops 61 | access_ce <= 1'h0; 62 | access_ce_last <= 1'h0; 63 | mem_trigger_sync <= 4'h0; 64 | scan_q <= {dqbits{1'b0}}; 65 | // End of automatics 66 | end 67 | else 68 | begin 69 | mem_trigger_sync <= {mem_trigger_sync[2:0], mem_trigger}; 70 | access_ce <= (mem_trigger_sync[3] ^ mem_trigger_sync[2]) & scan_mem_sel; 71 | access_ce_last <= access_ce & ~scan_cen_n; 72 | if(access_ce_last) begin 73 | scan_q <= Q; 74 | end 75 | end 76 | end 77 | 78 | endmodule 79 | 80 | -------------------------------------------------------------------------------- /chipDesign/verilog/mem_wrapper/mem_tieoffs.v: -------------------------------------------------------------------------------- 1 | 2 | // RAM block for the main memory 3 | module sram_32Kx32_wrapper ( 4 | // Outputs 5 | Q, 6 | // Inputs 7 | CLK, CE_n, BWE_n, A, D, 8 | 9 | // Scan chain test inputs 10 | scan_mem_sel, mem_use_scan, mem_trigger, mem_scan_reset_n, 11 | scan_addr, scan_d, scan_wen_n, scan_cen_n,scan_q, clk_scan, scan_EMA 12 | ); 13 | 14 | input CLK; 15 | input clk_scan; 16 | input [14:0] A; 17 | input [31:0] D; 18 | 19 | input BWE_n; 20 | input CE_n; 21 | input [2:0] scan_EMA; 22 | output [31:0] Q; 23 | 24 | // Scan chain test inputs/outputs 25 | input scan_mem_sel; 26 | input mem_use_scan; 27 | input mem_trigger; 28 | input mem_scan_reset_n; 29 | input [14:0] scan_addr; 30 | input [31:0] scan_d; 31 | input scan_wen_n; 32 | input scan_cen_n; 33 | output [31:0] scan_q; 34 | 35 | // Wire definition 36 | wire [14:0] mem_addr; 37 | wire [31:0] mem_d; 38 | wire mem_bwen_n; 39 | wire mem_cen_n; 40 | 41 | mem_scan #(.addrbits(15), .dqbits(32)) mem_scan_inst ( 42 | // Control inputs from scan 43 | .scan_mem_sel(scan_mem_sel), .mem_use_scan(mem_use_scan), 44 | .mem_trigger(mem_trigger), .mem_scan_reset_n(mem_scan_reset_n), 45 | // Input from Memory 46 | .Q(Q), 47 | // Outputs to the memory 48 | .mem_addr(mem_addr), .mem_d(mem_d), 49 | .mem_bwen_n(mem_bwen_n), .mem_cen_n(mem_cen_n), 50 | // Inputs from the scan 51 | .scan_addr(scan_addr), .scan_d(scan_d), 52 | .scan_wen_n(scan_wen_n), .scan_cen_n(scan_cen_n), 53 | // Output to the scan 54 | .scan_q(scan_q), 55 | // Inputs from the core 56 | .A(A), .D(D), .BWE_n(BWE_n), .CE_n(CE_n), 57 | .CLK(clk_scan)); 58 | 59 | wire clk_mem = mem_use_scan ? clk_scan : CLK; 60 | 61 | sram_32Kx32 mem_block_32K_32 ( 62 | .Q(Q), 63 | .CLK(clk_mem), 64 | .CEN(mem_cen_n), 65 | .WEN(mem_bwen_n), 66 | .A(mem_addr), 67 | .D(mem_d), 68 | .EMA(scan_EMA), 69 | .RETN(1'b1)); 70 | 71 | 72 | endmodule // sram_32Kx32_wrapper 73 | 74 | -------------------------------------------------------------------------------- /chipDesign/verilog/readme.md: -------------------------------------------------------------------------------- 1 | The detailed implementation is a little bit different from Figure 5 in the paper because of the specific technology, but basic idea is same. 2 | 3 | The reason Cunit is commented out is the parasitic capacitanceat that node is already enough, so we don't need to explicitly add a Cunit. 4 | 5 | The transistor in parallel with Cmain is to create another leakage path because the leakage in Cmain is not enough to reset itself. 6 | -------------------------------------------------------------------------------- /fpga_hardware/backend/ml509.ucf: -------------------------------------------------------------------------------- 1 | NET sys_clk_in_n LOC="K19" | IOSTANDARD = LVDS_25 | PERIOD = 5ns; # Bank 3, Vcco=2.5V, No DCI 2 | NET sys_clk_in_p LOC="L19" | IOSTANDARD = LVDS_25 | PERIOD = 5ns; # Bank 3, Vcco=2.5V, No DCI 3 | 4 | NET rst_n_pad_i LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33 | TIG; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors 5 | 6 | NET uart0_srx_pad_i LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI 7 | NET uart0_stx_pad_o LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI 8 | 9 | ###################################################################### 10 | # 11 | # External JTAG connections on J6 pins 46, 50, 54, 58 12 | # 13 | ###################################################################### 14 | NET tck_pad_i LOC="AJ34" | CLOCK_DEDICATED_ROUTE=FALSE; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 15 | NET tdo_pad_o LOC="AM32"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 16 | NET tdi_pad_i LOC="AN34"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 17 | NET tms_pad_i LOC="AN33"; # Bank 13, Vcco=2.5V or 3.3V user selectable by J20 18 | NET jtag_gnd LOC="AM33" | PULLDOWN; 19 | NET jtag_vdd LOC="AL33" | PULLUP; 20 | 21 | ###################################################################### 22 | # 23 | # External UART connections on J6 pins 2, 4 24 | # 25 | ###################################################################### 26 | 27 | NET uart0_srx_expheader_pad_i LOC="H33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 28 | NET uart0_stx_expheader_pad_o LOC="F34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20 29 | 30 | ###################################################################### 31 | # 32 | # UCF file from ML501 PAR 33 | # 34 | ###################################################################### 35 | 36 | # Define the two clock domains as timespecs 37 | NET dcm0_clkdv TNM_NET="wb_clk_o"; 38 | TIMESPEC "TS_wb_clk_o" = PERIOD "wb_clk_o" 20 ns HIGH 50%; 39 | #NET dcm0_clk0 TNM_NET = "ssram_clk200"; 40 | INST *sys_clk_in_ibufds DIFF_TERM=TRUE; 41 | NET "clkgen0/sys_clk_in_200" TNM_NET = "sys_clk_in_200"; 42 | TIMESPEC "TSSYSCLK200" = PERIOD "sys_clk_in_200" 5 ns HIGH 50 %; 43 | # Reset timing ignore - treat as async paths 44 | 45 | -------------------------------------------------------------------------------- /fpga_hardware/buildSupport/orpsoc_top.xst: -------------------------------------------------------------------------------- 1 | run 2 | -use_new_parser yes 3 | -ifn buildSupport/orpsoc_top.prj 4 | -ifmt mixed 5 | -ofn orpsoc_top 6 | -ofmt NGC 7 | -p xc5vlx110t-3-ff1136 8 | -top orpsoc_top 9 | -opt_mode Speed 10 | -opt_level 2 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview No 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Off 28 | -verilog2001 YES 29 | -fsm_extract YES 30 | -fsm_encoding Auto 31 | -safe_implementation No 32 | -fsm_style LUT 33 | -ram_extract Yes 34 | -ram_style Auto 35 | -rom_extract Yes 36 | -mux_style Auto 37 | -decoder_extract YES 38 | -priority_extract Yes 39 | -shreg_extract YES 40 | -shift_extract YES 41 | -xor_collapse YES 42 | -rom_style Auto 43 | -auto_bram_packing Yes 44 | -mux_extract Yes 45 | -resource_sharing YES 46 | -async_to_sync NO 47 | -use_dsp48 Auto 48 | -iobuf YES 49 | -max_fanout 100000 50 | -bufg 32 51 | -register_duplication YES 52 | -register_balancing Yes 53 | -move_first_stage YES 54 | -move_last_stage YES 55 | -slice_packing YES 56 | -optimize_primitives Yes 57 | -use_clock_enable Auto 58 | -use_sync_set Auto 59 | -use_sync_reset Auto 60 | -iob Auto 61 | -equivalent_register_removal YES 62 | -slice_utilization_ratio_maxmargin 5 63 | -vlgincdir { "cores/dbg_if" "cores/jtag_tap" "cores/or1200" "cores/top" "cores/uart16550/rtl/verilog" "cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/" "cores/adv_debug_sys/Hardware/xilinx_internal_jtag/rtl/verilog"} 64 | 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-------------------------------------------------------------------------------- 1 | README_testbench.txt 2 | Advanced Debug Module (adv_dbg_if) 3 | Nathan Yawn, nathan.yawn@opencores.org 4 | 5 | Three testbenches are supplied with the advanced debug interface. The first 6 | uses behavioral simulation of a wishbone bus with a memory attached, and 7 | another behavioral simulation of an OR1200 CPU. This testbench performs 8 | and tests bus / memory operations, and performs a few CPU operations, The 9 | top-level module is in adv_dbg_tb.v. Other than the behavioral models, it 10 | instantiates an adv_dbg_if (found in ../rtl/verilog/), and a JTAG TAP 11 | ("jtag" module, not included with this module). Note that the TAP 12 | written by Igor Mohor will not work correctly; use the version distributed 13 | with the Advanced Debug System (written by Nathan Yawn). 14 | 15 | The second testbench includes an actual wishbone/OR1200 system. Its 16 | top-level entity is xsv_fpga_top. It instantiates a wb_conbus, an OR1200, 17 | an onchipram, a jtag TAP, and a UART16550, along with an adv_dbg_if. The 18 | testbench is also instantiated here, and is used to drive the inputs to 19 | the JTAG TAP. This testbench is less polished, but includes a functional 20 | test of the single-step capability of the CPU. 21 | 22 | The third testbench is used to test the JTAG serial port function. Its 23 | top-level entity is adv_dbg_jsp_tb. This testbench instantiates only 24 | a JTAG TAP and and adv_dbg_if. The CPU module of the adv_dbg_if should 25 | not be enabled for this testbench. The WB initiator output of the WB 26 | module is connected point-to-point to the WB target interface of the JTAG 27 | Serial Port (JSP) module. The WB interface is used to drive the WB side 28 | of the JSP. 29 | 30 | All testbenches were written for use in ModelSim (version 6.4). A 31 | wave.do file is also included for each testbench, which will display a 32 | useful collection of signals in the ModelSim wave view. 33 | 34 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/AdvancedDebugInterface.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/AdvancedDebugInterface.pdf -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/AdvancedDebugInterface.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/AdvancedDebugInterface.odt -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/generic_submodule.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/generic_submodule.odg -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/jsp_submodule.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/jsp_submodule.odg -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/system_block_diagram.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/system_block_diagram.odg -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/top_level_module.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/doc/src/top_level_module.odg -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/altera_virtual_jtag/doc/altera_virtual_jtag.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/altera_virtual_jtag/doc/altera_virtual_jtag.pdf -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/altera_virtual_jtag/doc/src/altera_virtual_jtag.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/altera_virtual_jtag/doc/src/altera_virtual_jtag.odt -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/jtag/BSDL/opencores_tap.bsd: -------------------------------------------------------------------------------- 1 | -- This is a minimal BSDL file describing the particulars 2 | -- of the OpenCores standard / native TAP. It is designed 3 | -- only to be used by the adv_jtag_bridge program. This 4 | -- file almost certainly lacks key entries and attributes 5 | -- required by other JTAG / BSDL systems. 6 | -- 7 | -- by Nathan Yawn (nathan.yawn@opencores.org) 8 | -- Copyright: This file is released into the public domain. 9 | -- 10 | 11 | 12 | entity OC_TAP is 13 | 14 | 15 | attribute INSTRUCTION_LENGTH of OC_TAP : entity is 4; 16 | 17 | 18 | attribute INSTRUCTION_OPCODE of OC_TAP : entity is 19 | "EXTEST (0000)," & 20 | "SAMPLE_PRELOAD (0001)," & 21 | "IDCODE (0010)," & 22 | "MBIST (1001)," & 23 | "DEBUG (1000)," & 24 | "BYPASS (1111),"; 25 | 26 | 27 | attribute IDCODE_REGISTER of OC_TAP : entity is 28 | "0001" & -- version 29 | "0100100101010001" & -- part number 30 | "00011100001" & -- manufacturer (flextronics) 31 | "1"; -- required by 1149.1 32 | 33 | 34 | end OC_TAP; 35 | 36 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/jtag/cells/rtl/verilog/BiDirectionalCell.v: -------------------------------------------------------------------------------- 1 | /********************************************************************************** 2 | * * 3 | * BiDirectional Cell: * 4 | * * 5 | * FromCore: Value that comes from on-chip logic and goes to pin * 6 | * ToCore: Value that is read-in from the pin and goes to core * 7 | * FromPreviousBSCell: Value from previous boundary scan cell * 8 | * ToNextBSCell: Value for next boundary scan cell * 9 | * CaptureDR, ShiftDR, UpdateDR: TAP states * 10 | * extest: Instruction Register Command * 11 | * TCK: Test Clock * 12 | * BiDirPin: Bidirectional pin connected to this BS cell * 13 | * FromOutputEnable: This pin comes from core or ControlCell * 14 | * * 15 | * Signal that is connected to BiDirPin comes from core or BS chain. Tristate * 16 | * control is generated in core or BS chain (ControlCell). * 17 | * * 18 | **********************************************************************************/ 19 | 20 | module BiDirectionalCell( FromCore, ToCore, FromPreviousBSCell, CaptureDR, ShiftDR, UpdateDR, extest, TCK, ToNextBSCell, FromOutputEnable, BiDirPin); 21 | input FromCore; 22 | input FromPreviousBSCell; 23 | input CaptureDR; 24 | input ShiftDR; 25 | input UpdateDR; 26 | input extest; 27 | input TCK; 28 | input FromOutputEnable; 29 | 30 | reg Latch; 31 | 32 | output ToNextBSCell; 33 | reg ToNextBSCell; 34 | 35 | output BiDirPin; 36 | output ToCore; 37 | 38 | reg ShiftedControl; 39 | 40 | wire SelectedInput = CaptureDR? BiDirPin : FromPreviousBSCell; 41 | 42 | always @ (posedge TCK) 43 | begin 44 | if(CaptureDR | ShiftDR) 45 | Latch<=SelectedInput; 46 | end 47 | 48 | always @ (negedge TCK) 49 | begin 50 | ToNextBSCell<=Latch; 51 | end 52 | 53 | always @ (negedge TCK) 54 | begin 55 | if(UpdateDR) 56 | ShiftedControl<=ToNextBSCell; 57 | end 58 | 59 | wire MuxedSignal = extest? ShiftedControl : FromCore; 60 | assign BiDirPin = FromOutputEnable? MuxedSignal : 1'bz; 61 | 62 | //BUF Buffer (.I(BiDirPin), .O(ToCore)); 63 | assign ToCore = BiDirPin; 64 | 65 | 66 | endmodule // TristateCell -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/jtag/tap/doc/jtag.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/jtag/tap/doc/jtag.pdf -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/jtag/tap/doc/src/jtag.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/jtag/tap/doc/src/jtag.odt -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/jtag/tap/doc/src/oc_jtag_sys_diag.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/jtag/tap/doc/src/oc_jtag_sys_diag.odg -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/jtag/tap/doc/src/system_block_diagram.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/jtag/tap/doc/src/system_block_diagram.odg -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/src/xilinx_bscan_waveform.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/src/xilinx_bscan_waveform.odg -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/src/xilinx_internal_jtag.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/src/xilinx_internal_jtag.odt -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/xilinx_internal_jtag.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Hardware/xilinx_internal_jtag/doc/xilinx_internal_jtag.pdf -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag_options.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | // Xilinx has a different HDL entity for the internal JTAG in each of these. 4 | // How thoughtful. 5 | 6 | //`define SPARTAN2 7 | //`define SPARTAN3 // This is also used for SPARTAN 3E devices 8 | //`define SPARTAN3A 9 | //`define VIRTEX 10 | //`define VIRTEX2 // Also used for the VIRTEX 2P 11 | //`define VIRTEX4 12 | `define VIRTEX5 -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Patches/GDB6.8/gdb-6.8-bz436037-reg-no-longer-active.patch: -------------------------------------------------------------------------------- 1 | diff -d -urpN src.0/gdb/valops.c src.1/gdb/valops.c 2 | --- src.0/gdb/valops.c 2008-07-27 04:00:03.000000000 +0200 3 | +++ src.1/gdb/valops.c 2008-07-31 15:17:42.000000000 +0200 4 | @@ -813,10 +813,18 @@ value_assign (struct value *toval, struc 5 | struct frame_info *frame; 6 | int value_reg; 7 | 8 | - /* Figure out which frame this is in currently. */ 9 | - frame = frame_find_by_id (VALUE_FRAME_ID (toval)); 10 | value_reg = VALUE_REGNUM (toval); 11 | 12 | + /* Figure out which frame this is in currently. */ 13 | + frame = frame_find_by_id (VALUE_FRAME_ID (toval)); 14 | + /* "set $reg+=1" should work on programs with no debug info, 15 | + but frame_find_by_id returns NULL here (RH bug 436037). 16 | + Use current frame, it represents CPU state in this case. 17 | + If frame_find_by_id is changed to do it internally 18 | + (it is contemplated there), remove this. */ 19 | + if (!frame) 20 | + frame = get_current_frame (); 21 | + /* Probably never happens. */ 22 | if (!frame) 23 | error (_("Value being assigned to is no longer active.")); 24 | 25 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/.classpath: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | AdvancedWatchpointControl 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.jdt.core.javabuilder 10 | 11 | 12 | 13 | 14 | 15 | org.eclipse.jem.workbench.JavaEMFNature 16 | org.eclipse.jdt.core.javanature 17 | org.eclipse.jem.beaninfo.BeanInfoNature 18 | 19 | 20 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/AdvancedWatchpointControl.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/AdvancedWatchpointControl.jar -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/Makefile: -------------------------------------------------------------------------------- 1 | 2 | JC = javac 3 | JAVA = java 4 | SRCPATH = src/advancedWatchpointControl/ 5 | DSTPATH = bin/advancedWatchpointControl/ 6 | JFLAGS = -g -d $(DSTPATH) -cp swt.jar 7 | 8 | 9 | CLASSES = \ 10 | $(SRCPATH)AdvancedWatchpointControl.java \ 11 | $(SRCPATH)ReadRegisterTransaction.java \ 12 | $(SRCPATH)registerInterpreter.java \ 13 | $(SRCPATH)guiControlGroup.java \ 14 | $(SRCPATH)RegisterObserver.java \ 15 | $(SRCPATH)guiCountRegsGroup.java \ 16 | $(SRCPATH)rspCoder.java \ 17 | $(SRCPATH)guiDCRGroup.java \ 18 | $(SRCPATH)targetDebugRegisterSet.java \ 19 | $(SRCPATH)guiServerGroup.java \ 20 | $(SRCPATH)TargetRunningTransaction.java \ 21 | $(SRCPATH)LogMessageObserver.java \ 22 | $(SRCPATH)TargetTransaction.java \ 23 | $(SRCPATH)mainControl.java \ 24 | $(SRCPATH)targetTransactor.java \ 25 | $(SRCPATH)NetworkStatusObserver.java \ 26 | $(SRCPATH)WriteRegisterTransaction.java \ 27 | $(SRCPATH)networkSystem.java 28 | 29 | default: AdvancedWatchpointControl.jar 30 | 31 | run: AdvancedWatchpointControl.jar 32 | $(JAVA) -jar AdvancedWatchpointControl.jar & 33 | 34 | AdvancedWatchpointControl.jar: $(CLASSES) 35 | $(JC) $(JFLAGS) $(CLASSES) 36 | jar cvfm AdvancedWatchpointControl.jar manifest -C bin/advancedWatchpointControl/ . 37 | 38 | clean: 39 | $(RM) $(DSTPATH)*.class 40 | $(RM) AdvancedWatchpointControl.jar 41 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/README: -------------------------------------------------------------------------------- 1 | The AdvancedWatchpointControl program is a Java-language program distributed 2 | as an Eclipse project. These instructions assume you have both the 3 | Eclipse platform and the JDT Java development plugins installed. These 4 | instructions were written for Eclipse version 3.5.2, though other versions 5 | should be similar. 6 | 7 | To build the project in Eclipse, you must first import it into your workspace. 8 | From the 'File' menu, select 'Import...'. In the Import menu, under the 9 | 'General' folder, select 'Existing Projects into Workspace', then click 'Next'. 10 | On the next screen, select 'Select root directory', then enter (or browse to) 11 | the adv_debug_sys/Software/AdvancedWatchpointControl directory. Finally, 12 | click the 'Finish' button to import the project. 13 | 14 | AdvancedWatchpointControl depends on the SWT GUI widget toolkit from the 15 | Eclipse project. This can be downloaded directly from the Eclipse project, 16 | at http://www.eclipse.org/swt/. Download the version appropriate for your 17 | operating system. 18 | 19 | There are (at least) two ways to satisfy the dependancy on SWT. As shipped, 20 | AdvancedWatchpointControl is configured to depend on a project in the 21 | workspace called org.eclipse.swt To create this project, you may import the 22 | SWT project into the workspace from the downloaded archive file in the same 23 | way you imported AdvancedWatchpointControl. 24 | 25 | In some versions of the SWT archive, there is a bug which prevents Eclipse 26 | from importing the project. If this is the case, you must work around. 27 | Extract the SWT archive, and find the swt.jar file. In Eclipse, right-click 28 | on the AdvancedWatchpointControl, and click on 'Properties.' Under the 29 | 'Projects' tab, remove the dependancy on org.eclipse.swt. Under the 30 | 'Libraries' tab, remove SWT_CONTAINER/PLATFORM. Then click the 'Add 31 | External JARs...' button. This will open the 'JAR Selection' dialog. Select 32 | the swt.jar file from the archive, and click OK. 33 | 34 | You should now be able to build AdvancedWatchpointControl, and run it as a 35 | Java application via the Eclipse GUI. 36 | 37 | If you do not have or wish to install Eclipse, a simple Makefile has been 38 | included which should be able to build AdvancedWatchpointControl as an 39 | executable JAR file. Simply type "make" in the project's root directory 40 | to build the program, which will be called AdvancedWatchpointControl.jar. 41 | Typing "make run" will build the program, then execute it. 42 | 43 | A pre-compiled executable JAR file has been included in the root directory of 44 | AdvancedWatchpointControl, called AdvancedWatchpointControl.jar. To run this 45 | file using the Sun JVM in Linux, use the command line: 46 | 47 | >java -jar AdvancedWatchpointControl.jar 48 | 49 | Other JVMs and operating systems may use different syntax. Note that the 50 | AdvancedWatchpointControl.jar file includes the SWT library, which is 51 | distributed under the terms of the Eclipse Public License v1.0. A copy of 52 | this license may be found in the doc/ subdirectory. 53 | 54 | 55 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/bin/advancedWatchpointControl/.keepme: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/bin/advancedWatchpointControl/.keepme -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/doc/AdvancedWatchpointControl.pdf: -------------------------------------------------------------------------------- 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advancedWatchpointControl.AdvancedWatchpointControl 4 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/src/advancedWatchpointControl/LogMessageObserver.java: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////// 2 | // 3 | // LogMessageObserver.java 4 | // 5 | // Copyright (C) 2010 Nathan Yawn 6 | // (nyawn@opencores.org) 7 | // 8 | // This interface is used by any class that wants to register 9 | // to receive notifications when a new log message is 10 | // created. 11 | // 12 | //////////////////////////////////////////////////////////////// 13 | // 14 | // This source file may be used and distributed without 15 | // restriction provided that this copyright statement is not 16 | // removed from the file and that any derivative work contains 17 | // the original copyright notice and the associated disclaimer. 18 | // 19 | // This source file is free software; you can redistribute it 20 | // and/or modify it under the terms of the GNU General 21 | // Public License as published by the Free Software Foundation; 22 | // either version 3.0 of the License, or (at your option) any 23 | // later version. 24 | // 25 | // This source is distributed in the hope that it will be 26 | // useful, but WITHOUT ANY WARRANTY; without even the implied 27 | // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 28 | // PURPOSE. See the GNU Lesser General Public License for more 29 | // details. 30 | // 31 | // You should have received a copy of the GNU General 32 | // Public License along with this source; if not, download it 33 | // from http://www.gnu.org/licenses/gpl.html 34 | // 35 | //////////////////////////////////////////////////////////////// 36 | package advancedWatchpointControl; 37 | 38 | public interface LogMessageObserver { 39 | public void notifyLogMessage(); 40 | } 41 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/src/advancedWatchpointControl/NetworkStatusObserver.java: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////// 2 | // 3 | // NetworkStatusObserver.java 4 | // 5 | // Copyright (C) 2010 Nathan Yawn 6 | // (nyawn@opencores.org) 7 | // 8 | // This interface is implemented by classes that wish to 9 | // register to be notified when the network status changes. 10 | // 11 | //////////////////////////////////////////////////////////////// 12 | // 13 | // This source file may be used and distributed without 14 | // restriction provided that this copyright statement is not 15 | // removed from the file and that any derivative work contains 16 | // the original copyright notice and the associated disclaimer. 17 | // 18 | // This source file is free software; you can redistribute it 19 | // and/or modify it under the terms of the GNU General 20 | // Public License as published by the Free Software Foundation; 21 | // either version 3.0 of the License, or (at your option) any 22 | // later version. 23 | // 24 | // This source is distributed in the hope that it will be 25 | // useful, but WITHOUT ANY WARRANTY; without even the implied 26 | // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 27 | // PURPOSE. See the GNU Lesser General Public License for more 28 | // details. 29 | // 30 | // You should have received a copy of the GNU General 31 | // Public License along with this source; if not, download it 32 | // from http://www.gnu.org/licenses/gpl.html 33 | // 34 | //////////////////////////////////////////////////////////////// 35 | package advancedWatchpointControl; 36 | 37 | public interface NetworkStatusObserver { 38 | public void notifyNetworkStatus(); 39 | } 40 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/src/advancedWatchpointControl/ReadRegisterTransaction.java: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////// 2 | // 3 | // ReadRegisterTransaction.java 4 | // 5 | // Copyright (C) 2010 Nathan Yawn 6 | // (nyawn@opencores.org) 7 | // 8 | // This class defines a transaction object which is passed to 9 | // the RSP coder in order to perform an RSP 'read' command. 10 | // 11 | //////////////////////////////////////////////////////////////// 12 | // 13 | // This source file may be used and distributed without 14 | // restriction provided that this copyright statement is not 15 | // removed from the file and that any derivative work contains 16 | // the original copyright notice and the associated disclaimer. 17 | // 18 | // This source file is free software; you can redistribute it 19 | // and/or modify it under the terms of the GNU General 20 | // Public License as published by the Free Software Foundation; 21 | // either version 3.0 of the License, or (at your option) any 22 | // later version. 23 | // 24 | // This source is distributed in the hope that it will be 25 | // useful, but WITHOUT ANY WARRANTY; without even the implied 26 | // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 27 | // PURPOSE. See the GNU Lesser General Public License for more 28 | // details. 29 | // 30 | // You should have received a copy of the GNU General 31 | // Public License along with this source; if not, download it 32 | // from http://www.gnu.org/licenses/gpl.html 33 | // 34 | //////////////////////////////////////////////////////////////// 35 | package advancedWatchpointControl; 36 | 37 | public class ReadRegisterTransaction implements TargetTransaction { 38 | 39 | private String packetString = null; 40 | private long dataValueRead = 0; 41 | 42 | public ReadRegisterTransaction(targetDebugRegisterSet.regType reg) { 43 | packetString = new String("p"); // 'p' is read one register 44 | int regAddr = targetDebugRegisterSet.getRegisterAddress(reg); 45 | packetString += Integer.toHexString(regAddr); 46 | } 47 | 48 | @Override 49 | public String getDataToSend() { 50 | return packetString; 51 | } 52 | 53 | @Override 54 | public boolean receivePacket(String pkt) { 55 | 56 | // A register read response has no leading header / char... 57 | // so just parse the number. 58 | long val; 59 | try { 60 | val = Long.parseLong(pkt, 16); // data comes back as a hex string 61 | } catch (Exception e) { 62 | // TODO logMessageGUI("Got invalid read data (size " + pkt.length() + "): " + pkt + ": " + e); 63 | dataValueRead = 0; 64 | return false; 65 | } 66 | 67 | dataValueRead = val; 68 | return true; 69 | } 70 | 71 | public long getDataValueRead() { 72 | return dataValueRead; 73 | } 74 | 75 | } 76 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/src/advancedWatchpointControl/RegisterObserver.java: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////// 2 | // 3 | // RegisterObserver.java 4 | // 5 | // Copyright (C) 2010 Nathan Yawn 6 | // (nyawn@opencores.org) 7 | // 8 | // This interface is implemented by (display) classes that 9 | // wish to be notified either when the register cache has 10 | // changed due to an RSP read, or when their values should be 11 | // written to the cache in preparation for an RSP write. 12 | // 13 | //////////////////////////////////////////////////////////////// 14 | // 15 | // This source file may be used and distributed without 16 | // restriction provided that this copyright statement is not 17 | // removed from the file and that any derivative work contains 18 | // the original copyright notice and the associated disclaimer. 19 | // 20 | // This source file is free software; you can redistribute it 21 | // and/or modify it under the terms of the GNU General 22 | // Public License as published by the Free Software Foundation; 23 | // either version 3.0 of the License, or (at your option) any 24 | // later version. 25 | // 26 | // This source is distributed in the hope that it will be 27 | // useful, but WITHOUT ANY WARRANTY; without even the implied 28 | // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 29 | // PURPOSE. See the GNU Lesser General Public License for more 30 | // details. 31 | // 32 | // You should have received a copy of the GNU General 33 | // Public License along with this source; if not, download it 34 | // from http://www.gnu.org/licenses/gpl.html 35 | // 36 | //////////////////////////////////////////////////////////////// 37 | package advancedWatchpointControl; 38 | 39 | public interface RegisterObserver { 40 | public enum updateDirection { GUI_TO_REGS, REGS_TO_GUI } 41 | 42 | void notifyRegisterUpdate(updateDirection dir) throws NumberFormatException; 43 | } 44 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/src/advancedWatchpointControl/TargetRunningTransaction.java: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////// 2 | // 3 | // targetDebugRegisterSet.java 4 | // 5 | // Copyright (C) 2010 Nathan Yawn 6 | // (nyawn@opencores.org) 7 | // 8 | // This class defines a transaction object which is passed 9 | // to the RSP coder in order to determine whether the target 10 | // CPU is running. 11 | // 12 | //////////////////////////////////////////////////////////////// 13 | // 14 | // This source file may be used and distributed without 15 | // restriction provided that this copyright statement is not 16 | // removed from the file and that any derivative work contains 17 | // the original copyright notice and the associated disclaimer. 18 | // 19 | // This source file is free software; you can redistribute it 20 | // and/or modify it under the terms of the GNU General 21 | // Public License as published by the Free Software Foundation; 22 | // either version 3.0 of the License, or (at your option) any 23 | // later version. 24 | // 25 | // This source is distributed in the hope that it will be 26 | // useful, but WITHOUT ANY WARRANTY; without even the implied 27 | // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 28 | // PURPOSE. See the GNU Lesser General Public License for more 29 | // details. 30 | // 31 | // You should have received a copy of the GNU General 32 | // Public License along with this source; if not, download it 33 | // from http://www.gnu.org/licenses/gpl.html 34 | // 35 | //////////////////////////////////////////////////////////////// 36 | package advancedWatchpointControl; 37 | 38 | 39 | public class TargetRunningTransaction implements TargetTransaction { 40 | 41 | private boolean isTargetRunning = false; 42 | 43 | public TargetRunningTransaction() { 44 | } 45 | 46 | @Override 47 | public String getDataToSend() { 48 | return new String("?"); 49 | } 50 | 51 | @Override 52 | public boolean receivePacket(String pkt) { 53 | 54 | // 'S##' means it's stopped, 'R' means it's running, 55 | // anything else is an error. 56 | if(pkt.charAt(0) == 'R') { 57 | // target is running, disallow accesses 58 | isTargetRunning = true; 59 | } 60 | else if(pkt.charAt(0) == 'S') { 61 | // We got a stop packet 62 | isTargetRunning = false; 63 | } 64 | else { 65 | return false; 66 | } 67 | 68 | return true; 69 | } 70 | 71 | public boolean getIsTargetRunning() { 72 | return isTargetRunning; 73 | } 74 | 75 | } 76 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/src/advancedWatchpointControl/TargetTransaction.java: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////// 2 | // 3 | // TargetTransaction.java 4 | // 5 | // Copyright (C) 2010 Nathan Yawn 6 | // (nyawn@opencores.org) 7 | // 8 | // This interface is implemented by objects which define 9 | // specific RSP transactions, such as register read and write. 10 | // 11 | //////////////////////////////////////////////////////////////// 12 | // 13 | // This source file may be used and distributed without 14 | // restriction provided that this copyright statement is not 15 | // removed from the file and that any derivative work contains 16 | // the original copyright notice and the associated disclaimer. 17 | // 18 | // This source file is free software; you can redistribute it 19 | // and/or modify it under the terms of the GNU General 20 | // Public License as published by the Free Software Foundation; 21 | // either version 3.0 of the License, or (at your option) any 22 | // later version. 23 | // 24 | // This source is distributed in the hope that it will be 25 | // useful, but WITHOUT ANY WARRANTY; without even the implied 26 | // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 27 | // PURPOSE. See the GNU Lesser General Public License for more 28 | // details. 29 | // 30 | // You should have received a copy of the GNU General 31 | // Public License along with this source; if not, download it 32 | // from http://www.gnu.org/licenses/gpl.html 33 | // 34 | //////////////////////////////////////////////////////////////// 35 | package advancedWatchpointControl; 36 | 37 | public interface TargetTransaction { 38 | 39 | // The RSP (or other encoding / sending algorithm) can 40 | // call this method to get the pre-formatted packet which should be 41 | // encoded and sent 42 | public String getDataToSend(); 43 | 44 | // This should be called by the receiving portion of the RSP 45 | // algorithm each time a new character is received from the 46 | // network and decoded. It returns true so long as it wants 47 | // another character. It 48 | public boolean receivePacket(String pkt); 49 | 50 | } 51 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/src/advancedWatchpointControl/WriteRegisterTransaction.java: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////// 2 | // 3 | // WriteRegisterTransaction.java 4 | // 5 | // Copyright (C) 2010 Nathan Yawn 6 | // (nyawn@opencores.org) 7 | // 8 | // This class defines a transaction object which is passed to 9 | // the RSP coder in order to perform a register write 10 | // transaction. 11 | // 12 | //////////////////////////////////////////////////////////////// 13 | // 14 | // This source file may be used and distributed without 15 | // restriction provided that this copyright statement is not 16 | // removed from the file and that any derivative work contains 17 | // the original copyright notice and the associated disclaimer. 18 | // 19 | // This source file is free software; you can redistribute it 20 | // and/or modify it under the terms of the GNU General 21 | // Public License as published by the Free Software Foundation; 22 | // either version 3.0 of the License, or (at your option) any 23 | // later version. 24 | // 25 | // This source is distributed in the hope that it will be 26 | // useful, but WITHOUT ANY WARRANTY; without even the implied 27 | // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 28 | // PURPOSE. See the GNU Lesser General Public License for more 29 | // details. 30 | // 31 | // You should have received a copy of the GNU General 32 | // Public License along with this source; if not, download it 33 | // from http://www.gnu.org/licenses/gpl.html 34 | // 35 | //////////////////////////////////////////////////////////////// 36 | 37 | package advancedWatchpointControl; 38 | 39 | 40 | public class WriteRegisterTransaction implements TargetTransaction { 41 | 42 | private String packetString = null; 43 | 44 | public WriteRegisterTransaction(targetDebugRegisterSet.regType reg, long val) { 45 | packetString = new String("P"); // 'P' is write one register 46 | int regAddr = targetDebugRegisterSet.getRegisterAddress(reg); 47 | 48 | packetString += Integer.toHexString(regAddr); 49 | packetString += "="; 50 | 51 | String valueStr = Long.toHexString(val); 52 | 53 | // There must be 8 bytes of 'value' 54 | if(valueStr.length() > 8) { 55 | // Use the last 8 bytes, the first 8 may just be a sign extension 56 | valueStr = valueStr.substring(valueStr.length() - 8, valueStr.length()); 57 | } 58 | 59 | int padsize = 8 - valueStr.length(); 60 | for(int i = 0; i < padsize; i++) { 61 | packetString += '0'; 62 | } 63 | 64 | packetString += valueStr; 65 | } 66 | 67 | @Override 68 | public String getDataToSend() { 69 | return packetString; 70 | } 71 | 72 | @Override 73 | public boolean receivePacket(String pkt) { 74 | 75 | // Only one valid response from a register write: "OK" 76 | if(pkt.charAt(0) == 'O' && pkt.charAt(1) == 'K') { 77 | return true; 78 | } 79 | 80 | return false; 81 | } 82 | 83 | } 84 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/src/advancedWatchpointControl/targetTransactor.java: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////// 2 | // 3 | // targetTransactor.java 4 | // 5 | // Copyright (C) 2010 Nathan Yawn 6 | // (nyawn@opencores.org) 7 | // 8 | // This class handles the top-level target transactions. 9 | // Its methods are specific transactions (read register, 10 | // is target running, etc.). It constructs an appropriate 11 | // transaction object, then gives it to the RSP algorithm 12 | // for processing. 13 | // 14 | //////////////////////////////////////////////////////////////// 15 | // 16 | // This source file may be used and distributed without 17 | // restriction provided that this copyright statement is not 18 | // removed from the file and that any derivative work contains 19 | // the original copyright notice and the associated disclaimer. 20 | // 21 | // This source file is free software; you can redistribute it 22 | // and/or modify it under the terms of the GNU General 23 | // Public License as published by the Free Software Foundation; 24 | // either version 3.0 of the License, or (at your option) any 25 | // later version. 26 | // 27 | // This source is distributed in the hope that it will be 28 | // useful, but WITHOUT ANY WARRANTY; without even the implied 29 | // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 30 | // PURPOSE. See the GNU Lesser General Public License for more 31 | // details. 32 | // 33 | // You should have received a copy of the GNU General 34 | // Public License along with this source; if not, download it 35 | // from http://www.gnu.org/licenses/gpl.html 36 | // 37 | //////////////////////////////////////////////////////////////// 38 | package advancedWatchpointControl; 39 | 40 | import java.io.IOException; 41 | 42 | public class targetTransactor { 43 | 44 | rspCoder rsp = null; 45 | 46 | public targetTransactor(rspCoder r) { 47 | rsp = r; 48 | } 49 | 50 | // Succeeds or throws an IOException. 51 | public void writeRegister(targetDebugRegisterSet.regType reg, long val) throws IOException { 52 | WriteRegisterTransaction xact = new WriteRegisterTransaction(reg, val); 53 | rsp.Transact(xact); 54 | } 55 | 56 | // Returns a valid value or throws an IOException. 57 | public long readRegister(targetDebugRegisterSet.regType reg) throws IOException { 58 | long ret; 59 | ReadRegisterTransaction xact = new ReadRegisterTransaction(reg); 60 | rsp.Transact(xact); 61 | ret = xact.getDataValueRead(); 62 | return ret; 63 | } 64 | 65 | // Returns a valid boolean indicator or throws an IOException. 66 | public boolean isTargetRunning() throws IOException { 67 | boolean ret; 68 | TargetRunningTransaction xact = new TargetRunningTransaction(); 69 | rsp.Transact(xact); 70 | ret = xact.getIsTargetRunning(); 71 | return ret; 72 | } 73 | 74 | } 75 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/swt.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/AdvancedWatchpointControl/swt.jar -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/adv_jtag_bridge.h: -------------------------------------------------------------------------------- 1 | #ifndef _ADV_JTAG_BRIDGE_H_ 2 | #define _ADV_JTAG_BRIDGE_H_ 3 | 4 | #ifndef TRUE 5 | #define TRUE 1 6 | #endif 7 | 8 | #ifndef FALSE 9 | #define FALSE 0 10 | #endif 11 | 12 | 13 | #endif /* _ADV_JTAG_BRIDGE_H_ */ 14 | 15 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/altera_virtual_jtag.h: -------------------------------------------------------------------------------- 1 | #ifndef _ALTERA_VIRTUAL_JTAG_H_ 2 | #define _ALTERA_VIRTUAL_JTAG_H_ 3 | 4 | // Contains constants relevant to the Altera Virtual JTAG 5 | // device, which are not included in the BSDL. 6 | // As of this writing, these are constant across every 7 | // device which supports virtual JTAG. 8 | 9 | // These are commands for the FPGA's IR 10 | #define ALTERA_CYCLONE_CMD_VIR 0x0E 11 | #define ALTERA_CYCLONE_CMD_VDR 0x0C 12 | 13 | // These defines are for the virtual IR (not the FPGA's) 14 | // The virtual TAP was defined in hardware to match the OpenCores native 15 | // TAP in both IR size and DEBUG command. 16 | #define ALT_VJTAG_IR_SIZE 4 17 | #define ALT_VJTAG_CMD_DEBUG 0x8 18 | 19 | #endif 20 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/bsdl.h: -------------------------------------------------------------------------------- 1 | #ifndef _BSDL_H_ 2 | #define _BSDL_H_ 3 | 4 | #include 5 | 6 | // Used by lower levels. 7 | // should not be used by higher levels (i.e. anything that calls 8 | // the API functions). 9 | struct bsdlinfo_node { 10 | char *name; 11 | uint32_t idcode; 12 | uint32_t idcode_mask; 13 | int IR_size; 14 | uint32_t cmd_debug; 15 | uint32_t cmd_user1; 16 | uint32_t cmd_idcode; 17 | struct bsdlinfo_node *next; 18 | }; 19 | 20 | typedef struct bsdlinfo_node bsdlinfo; 21 | 22 | 23 | #define IDCODE_INVALID 0xFFFFFFFF 24 | #define TAP_CMD_INVALID 0XFFFFFFFF 25 | 26 | 27 | void bsdl_init(void); 28 | void bsdl_add_directory(const char *dirname); 29 | 30 | const char * bsdl_get_name(uint32_t idcode); 31 | int bsdl_get_IR_size(uint32_t idcode); 32 | uint32_t bsdl_get_debug_cmd(uint32_t idcode); 33 | uint32_t bsdl_get_user1_cmd(uint32_t idcode); 34 | uint32_t bsdl_get_idcode_cmd(uint32_t idcode); 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/bsdl_parse.h: -------------------------------------------------------------------------------- 1 | #ifndef _BSDL_PARSE_H_ 2 | #define _BSDL_PARSE_H_ 3 | 4 | #include "bsdl.h" // need definition of bsdlinfo here 5 | 6 | 7 | bsdlinfo * parse_extract_values(char *bsdlfilename); 8 | 9 | #endif 10 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_common.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_common.c -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_common.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _CABLE_COMMON_H_ 3 | #define _CABLE_COMMON_H_ 4 | 5 | #include 6 | 7 | 8 | typedef struct { 9 | const char *name; 10 | int (*inout_func)(uint8_t, uint8_t *); 11 | int (*out_func)(uint8_t); 12 | int (*init_func)(); 13 | int (*opt_func)(int, char *); 14 | int (*bit_out_func)(uint8_t); 15 | int (*bit_inout_func)(uint8_t, uint8_t *); 16 | int (*stream_out_func)(uint32_t *, int, int); 17 | int (*stream_inout_func)(uint32_t *, uint32_t *, int, int); 18 | int (*flush_func)(); 19 | const char *opts; 20 | const char *help; 21 | } jtag_cable_t; 22 | 23 | // Defines to use in the 'packet' args of cable_write_bit() 24 | // and cable_read_write_bit(). Note that while TRST is 25 | // active low for JTAG hardware, here the TRST bit 26 | // should be set when you want the TRST wire active 27 | // (JTAG TAP to be reset). 28 | #define TRST (0x04) 29 | #define TMS (0x02) 30 | #define TDO (0x01) 31 | 32 | // These should only be used in the cable_* files. 33 | #define TCLK_BIT (0x01) 34 | #define TRST_BIT (0x02) 35 | #define TDI_BIT (0x04) 36 | #define TMS_BIT (0x08) 37 | #define TDO_BIT (0x20) 38 | 39 | // Cable subsystem / init routines 40 | void cable_setup(void); 41 | int cable_select(const char *cable); 42 | int cable_init(); 43 | int cable_parse_opt(int c, char *str); 44 | const char *cable_get_args(); 45 | void cable_print_help(); 46 | 47 | 48 | // Cable API routines 49 | int cable_write_bit(uint8_t packet); 50 | int cable_read_write_bit(uint8_t packet_out, uint8_t *bit_in); 51 | int cable_write_stream(uint32_t *stream, int len_bits, int set_last_bit); 52 | int cable_read_write_stream(uint32_t *outstream, uint32_t *instream, int len_bits, int set_last_bit); 53 | int cable_flush(void); 54 | 55 | // Common functions for lower-level drivers to use as desired 56 | int cable_common_write_bit(uint8_t packet); 57 | int cable_common_read_write_bit(uint8_t packet_out, uint8_t *bit_in); 58 | int cable_common_write_stream(uint32_t *stream, int len_bits, int set_last_bit); 59 | int cable_common_read_stream(uint32_t *outstream, uint32_t *instream, int len_bits, int set_last_bit); 60 | 61 | #endif 62 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_ft2232.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _CABLE_FT2232_H_ 3 | #define _CABLE_FT2232_H_ 4 | 5 | #include "cable_common.h" 6 | 7 | #ifndef min 8 | #define min(X,Y) ((X) < (Y) ? (X) : (Y)) 9 | #endif 10 | 11 | #define FTDX_MAXSEND 4096 12 | #define FTDX_MAXSEND_MPSSE (64 * 1024) 13 | #define FTDI_MAXRECV ( 4 * 64) 14 | 15 | #define BIT_CABLEID2_TCK 0 /* ADBUS0 */ 16 | #define BIT_CABLEID2_TDIDO 1 /* ADBUS1 */ 17 | #define BIT_CABLEID2_TDODI 2 /* ADBUS2 */ 18 | #define BIT_CABLEID2_TMS 3 /* ADBUS3 */ 19 | #define BITMASK_CABLEID2_TCK (1 << BIT_CABLEID2_TCK) 20 | #define BITMASK_CABLEID2_TDIDO (1 << BIT_CABLEID2_TDIDO) 21 | #define BITMASK_CABLEID2_TDODI (1 << BIT_CABLEID2_TDODI) 22 | #define BITMASK_CABLEID2_TMS (1 << BIT_CABLEID2_TMS) 23 | 24 | #define BIT_CABLEID2_OE 1 /* ACBUS1 */ 25 | #define BIT_CABLEID2_RXLED 2 /* ACBUS2 */ 26 | #define BIT_CABLEID2_TXLED 3 /* ACBUS3 */ 27 | #define BITMASK_CABLEID2_OE (1 << BIT_CABLEID2_OE) 28 | #define BITMASK_CABLEID2_RXLED (1 << BIT_CABLEID2_RXLED) 29 | #define BITMASK_CABLEID2_TXLED (1 << BIT_CABLEID2_TXLED) 30 | 31 | typedef struct usbconn_t usbconn_t; 32 | 33 | typedef struct { 34 | char *name; 35 | char *desc; 36 | char *driver; 37 | int32_t vid; 38 | int32_t pid; 39 | } usbconn_cable_t; 40 | 41 | typedef struct { 42 | const char *type; 43 | usbconn_t *(*connect)( const char **, int, usbconn_cable_t *); 44 | void (*free)( usbconn_t * ); 45 | int (*open)( usbconn_t * ); 46 | int (*close)( usbconn_t * ); 47 | int (*read)( usbconn_t *, uint8_t *, int ); 48 | int (*write)( usbconn_t *, uint8_t *, int, int ); 49 | } usbconn_driver_t; 50 | 51 | struct usbconn_t { 52 | usbconn_driver_t *driver; 53 | void *params; 54 | usbconn_cable_t *cable; 55 | }; 56 | 57 | typedef struct { 58 | /* USB device information */ 59 | unsigned int vid; 60 | unsigned int pid; 61 | struct ftdi_context *ftdic; 62 | char *serial; 63 | /* send and receive buffer handling */ 64 | uint32_t send_buf_len; 65 | uint32_t send_buffered; 66 | uint8_t *send_buf; 67 | uint32_t recv_buf_len; 68 | uint32_t to_recv; 69 | uint32_t recv_write_idx; 70 | uint32_t recv_read_idx; 71 | uint8_t *recv_buf; 72 | } ftdi_param_t; 73 | 74 | jtag_cable_t *cable_ftdi_get_driver(void); 75 | int cable_ftdi_init(); 76 | int cable_ftdi_write_bit(uint8_t packet); 77 | int cable_ftdi_read_write_bit(uint8_t packet_out, uint8_t *bit_in); 78 | int cable_ftdi_write_stream(uint32_t *stream, int len_bits, int set_last_bit); 79 | int cable_ftdi_read_stream(uint32_t *outstream, uint32_t *instream, int len_bits, int set_last_bit); 80 | int cable_ftdi_opt(int c, char *str); 81 | int cable_ftdi_flush(); 82 | int cable_ftdi_close(); 83 | 84 | #endif 85 | 86 | 87 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_ft245.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _CABLE_FT245_H_ 3 | #define _CABLE_FT245_H_ 4 | 5 | #include 6 | #include "cable_common.h" 7 | 8 | 9 | jtag_cable_t *cable_ft245_get_driver(void); 10 | int cable_ft245_init(); 11 | int cable_ft245_out(uint8_t value); 12 | int cable_ft245_inout(uint8_t value, uint8_t *in_bit); 13 | int cable_ft245_write_stream(uint32_t *stream, int len_bits, int set_last_bit); 14 | int cable_ft245_read_stream(uint32_t *outstream, uint32_t *instream, int len_bits, int set_last_bit); 15 | int cable_ft245_opt(int c, char *str); 16 | void cable_ft245_wait(); 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_parallel.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_parallel.c -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_parallel.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _CABLE_PARALLEL_H_ 3 | #define _CABLE_PARALLEL_H_ 4 | 5 | #include 6 | #include "cable_common.h" 7 | 8 | int cable_parallel_init(); 9 | int cable_parallel_opt(int c, char *str); 10 | void cable_parallel_phys_wait(); 11 | 12 | jtag_cable_t *cable_xpc3_get_driver(void); 13 | int cable_xpc3_inout(uint8_t value, uint8_t *inval); 14 | int cable_xpc3_out(uint8_t value); 15 | 16 | jtag_cable_t *cable_xess_get_driver(void); 17 | int cable_xess_inout(uint8_t value, uint8_t *inval); 18 | int cable_xess_out(uint8_t value); 19 | 20 | 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_sim.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_sim.c -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_sim.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _CABLE_SIM_H_ 3 | #define _CABLE_SIM_H_ 4 | 5 | #include 6 | #include "cable_common.h" 7 | 8 | jtag_cable_t *cable_rtl_get_driver(void); 9 | int cable_rtl_sim_init(); 10 | int cable_rtl_sim_out(uint8_t value); 11 | int cable_rtl_sim_inout(uint8_t value, uint8_t *inval); 12 | void cable_rtl_sim_wait(); 13 | int cable_rtl_sim_opt(int c, char *str); 14 | 15 | jtag_cable_t *cable_vpi_get_driver(void); 16 | int cable_vpi_init(); 17 | int cable_vpi_out(uint8_t value); 18 | int cable_vpi_inout(uint8_t value, uint8_t *inval); 19 | void cable_vpi_wait(); 20 | int cable_vpi_opt(int c, char *str); 21 | 22 | 23 | #endif 24 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_usbblaster.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _CABLE_USBBLASTER_H_ 3 | #define _CABLE_USBBLASTER_H_ 4 | 5 | #include 6 | #include "cable_common.h" 7 | 8 | jtag_cable_t *cable_usbblaster_get_driver(void); 9 | int cable_usbblaster_init(); 10 | int cable_usbblaster_out(uint8_t value); 11 | int cable_usbblaster_inout(uint8_t value, uint8_t *in_bit); 12 | int cable_usbblaster_write_stream(uint32_t *stream, int len_bits, int set_last_bit); 13 | int cable_usbblaster_read_stream(uint32_t *outstream, uint32_t *instream, int len_bits, int set_last_bit); 14 | int cable_usbblaster_opt(int c, char *str); 15 | void cable_usbblaster_wait(); 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/cable_xpc_dlc9.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _CABLE_XPC_DLC9_H_ 3 | #define _CABLE_XPC_DLC9_H_ 4 | 5 | #include 6 | #include "cable_common.h" 7 | 8 | jtag_cable_t *cable_xpcusb_get_driver(void); 9 | int cable_xpcusb_init(); 10 | int cable_xpcusb_out(uint8_t value); 11 | int cable_xpcusb_inout(uint8_t value, uint8_t *inval); 12 | int cable_xpcusb_opt(int c, char *str); 13 | int cable_xpcusb_read_write_bit(uint8_t packet_out, uint8_t *bit_in); 14 | 15 | 16 | #endif 17 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/chain_commands.h: -------------------------------------------------------------------------------- 1 | #ifndef _CHAIN_COMMANDS_H_ 2 | #define _CHAIN_COMMANDS_H_ 3 | 4 | #include 5 | 6 | // These two are used by both debug modules 7 | extern int current_chain; 8 | extern int desired_chain; 9 | 10 | // These are needed by the advanced debug module 11 | extern int global_DR_prefix_bits; 12 | extern int global_DR_postfix_bits; 13 | extern unsigned char global_xilinx_bscan; 14 | 15 | // Discover devices on JTAG chain 16 | int jtag_enumerate_chain(uint32_t **id_array, int *num_devices); 17 | int jtag_get_idcode(uint32_t cmd, uint32_t *idcode); 18 | 19 | // Functions to set configuration for the JTAG chain 20 | void config_set_IR_size(int size); 21 | void config_set_IR_prefix_bits(int bits); 22 | void config_set_IR_postfix_bits(int bits); 23 | void config_set_DR_prefix_bits(int bits); 24 | void config_set_DR_postfix_bits(int bits); 25 | void config_set_debug_cmd(unsigned int cmd); 26 | void config_set_alt_vjtag(unsigned char enable); 27 | void config_set_vjtag_cmd_vir(unsigned int cmd); 28 | void config_set_vjtag_cmd_vdr(unsigned int cmd); 29 | void config_set_xilinx_bscan(unsigned char enable); 30 | 31 | // Operations on the JTAG TAP 32 | int tap_reset(void); 33 | int tap_enable_debug_module(void); 34 | int tap_set_ir(int ir); 35 | int tap_set_shift_dr(void); 36 | int tap_exit_to_idle(void); 37 | 38 | // Functions to Send/receive bitstreams via JTAG 39 | // These functions are aware of other devices in the chain, and may adjust for them. 40 | int jtag_write_bit(uint8_t packet); 41 | int jtag_read_write_bit(uint8_t packet, uint8_t *in_bit); 42 | int jtag_write_stream(uint32_t *out_data, int length_bits, unsigned char set_TMS); 43 | int jtag_read_write_stream(uint32_t *out_data, uint32_t *in_data, int length_bits, 44 | unsigned char adjust, unsigned char set_TMS); 45 | 46 | int retry_do(void); 47 | void retry_ok(void); 48 | 49 | #endif 50 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/dbg_api.h: -------------------------------------------------------------------------------- 1 | #ifndef _DBG_API_H_ 2 | #define _DBG_API_H_ 3 | 4 | #include 5 | #include 6 | 7 | 8 | 9 | // API for GDB 10 | int dbg_wb_read32(uint32_t adr, uint32_t *data); 11 | int dbg_wb_write32(uint32_t adr, uint32_t data); 12 | int dbg_wb_write16(uint32_t adr, uint16_t data); 13 | int dbg_wb_write8(uint32_t adr, uint8_t data); 14 | int dbg_wb_read_block32(uint32_t adr, uint32_t *data, int len); 15 | int dbg_wb_read_block16(uint32_t adr, uint16_t *data, int len); 16 | int dbg_wb_read_block8(uint32_t adr, uint8_t *data, int len); 17 | int dbg_wb_write_block32(uint32_t adr, uint32_t *data, int len); 18 | int dbg_wb_write_block16(uint32_t adr, uint16_t *data, int len); 19 | int dbg_wb_write_block8(uint32_t adr, uint8_t *data, int len); 20 | int dbg_cpu0_read(uint32_t adr, uint32_t *data); 21 | int dbg_cpu0_read_block(uint32_t adr, uint32_t *data, int count); 22 | int dbg_cpu0_write(uint32_t adr, uint32_t data); 23 | int dbg_cpu0_write_block(uint32_t adr, uint32_t *data, int count); 24 | int dbg_cpu0_write_ctrl(uint32_t adr, uint8_t data); 25 | int dbg_cpu0_read_ctrl(uint32_t adr, uint8_t *data); 26 | //int dbg_cpu1_read(uint32_t adr, uint32_t *data); 27 | //int dbg_cpu1_write(uint32_t adr, uint32_t data); 28 | //int dbg_cpu1_write_reg(uint32_t adr, uint8_t data); 29 | //int dbg_cpu1_read_ctrl(uint32_t adr, uint8_t *data); 30 | int dbg_serial_sndrcv(unsigned int *bytes_to_send, const uint8_t *data_to_send, unsigned int *bytes_received, uint8_t *data_received); 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/doc/adv_jtag_bridge.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/doc/adv_jtag_bridge.pdf -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/doc/src/adv_jtag_bridge.odt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/doc/src/adv_jtag_bridge.odt -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/doc/src/ajb_block_diagram.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/doc/src/ajb_block_diagram.odg -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/errcodes.c: -------------------------------------------------------------------------------- 1 | /* errcodes.c - Error code to plaintext translator for the advanced JTAG bridge 2 | Copyright(C) 2008 - 2010 Nathan Yawn 3 | 4 | This program is free software; you can redistribute it and/or modify 5 | it under the terms of the GNU General Public License as published by 6 | the Free Software Foundation; either version 2 of the License, or 7 | (at your option) any later version. 8 | 9 | This program is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | GNU General Public License for more details. 13 | 14 | You should have received a copy of the GNU General Public License 15 | along with this program; if not, write to the Free Software 16 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 | */ 18 | 19 | #include 20 | #include "errcodes.h" 21 | 22 | // We can declare the error string with a fixed size, because it can't 23 | // have more than ALL of the error strings in it. Be sure to expand it 24 | // as more errors are added. Also, put a space at the end of each 25 | // error string, as there may be multiple errors. 26 | char errstr[256]; 27 | char *get_err_string(int err) 28 | { 29 | errstr[0] = '\0'; 30 | 31 | if(err & APP_ERR_COMM) 32 | strcat(errstr, "\'JTAG comm error\' "); 33 | if(err & APP_ERR_MALLOC) 34 | strcat(errstr, "\'malloc failed\' "); 35 | if(err & APP_ERR_MAX_RETRY) 36 | strcat(errstr, "\'max retries\' "); 37 | if(err & APP_ERR_CRC) 38 | strcat(errstr, "\'CRC mismatch\' "); 39 | if(err & APP_ERR_MAX_BUS_ERR) 40 | strcat(errstr, "\'max WishBone bus errors\' "); 41 | if(err & APP_ERR_CABLE_INVALID) 42 | strcat(errstr, "\'Invalid cable\' "); 43 | if(err & APP_ERR_INIT_FAILED) 44 | strcat(errstr, "\'init failed\' "); 45 | if(err & APP_ERR_BAD_PARAM) 46 | strcat(errstr, "\'bad command line parameter\' "); 47 | if(err & APP_ERR_CONNECT) 48 | strcat(errstr, "\'connection failed\' "); 49 | if(err & APP_ERR_USB) 50 | strcat(errstr, "\'USB\' "); 51 | if(err & APP_ERR_CABLENOTFOUND) 52 | strcat(errstr, "\'cable not found\' "); 53 | return errstr; 54 | } 55 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/errcodes.h: -------------------------------------------------------------------------------- 1 | #ifndef _ERRCODES_H_ 2 | #define _ERRCODES_H_ 3 | 4 | // Errors in high-level chain transactions 5 | // An error is a 32-bit bit-encoded value 6 | #define APP_ERR_NONE 0x0 7 | #define APP_ERR_COMM 0x1 8 | #define APP_ERR_MALLOC 0x2 9 | #define APP_ERR_MAX_RETRY 0x4 10 | #define APP_ERR_CRC 0x08 11 | #define APP_ERR_MAX_BUS_ERR 0x10 12 | #define APP_ERR_CABLE_INVALID 0x20 13 | #define APP_ERR_INIT_FAILED 0x40 14 | #define APP_ERR_BAD_PARAM 0x080 15 | #define APP_ERR_CONNECT 0x100 16 | #define APP_ERR_USB 0x200 17 | #define APP_ERR_CABLENOTFOUND 0x400 18 | #define APP_ERR_TEST_FAIL 0x0800 19 | 20 | char *get_err_string(int errval); 21 | 22 | #endif 23 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/except.h: -------------------------------------------------------------------------------- 1 | /* except.h -- OR1K architecture specific exceptions 2 | 3 | Copyright (C) 1999 Damjan Lampret, lampret@opencores.org 4 | Copyright (C) 2008 Embecosm Limited 5 | 6 | Contributor Jeremy Bennett 7 | 8 | This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator. 9 | 10 | This program is free software; you can redistribute it and/or modify it 11 | under the terms of the GNU General Public License as published by the Free 12 | Software Foundation; either version 3 of the License, or (at your option) 13 | any later version. 14 | 15 | This program is distributed in the hope that it will be useful, but WITHOUT 16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 | more details. 19 | 20 | You should have received a copy of the GNU General Public License along 21 | with this program. If not, see . 22 | */ 23 | 24 | /* This program is commented throughout in a fashion suitable for processing 25 | with Doxygen. */ 26 | 27 | 28 | #ifndef EXCEPT__H 29 | #define EXCEPT__H 30 | 31 | 32 | /* Package includes */ 33 | //#include "arch.h" 34 | 35 | /* Definition of OR1K exceptions */ 36 | #define EXCEPT_NONE 0x0000 37 | #define EXCEPT_RESET 0x0100 38 | #define EXCEPT_BUSERR 0x0200 39 | #define EXCEPT_DPF 0x0300 40 | #define EXCEPT_IPF 0x0400 41 | #define EXCEPT_TICK 0x0500 42 | #define EXCEPT_ALIGN 0x0600 43 | #define EXCEPT_ILLEGAL 0x0700 44 | #define EXCEPT_INT 0x0800 45 | #define EXCEPT_DTLBMISS 0x0900 46 | #define EXCEPT_ITLBMISS 0x0a00 47 | #define EXCEPT_RANGE 0x0b00 48 | #define EXCEPT_SYSCALL 0x0c00 49 | #define EXCEPT_FPE 0x0d00 50 | #define EXCEPT_TRAP 0x0e00 51 | 52 | #endif /* EXCEPT__H */ 53 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/gdb-6.8-bz436037-reg-no-longer-active.patch: -------------------------------------------------------------------------------- 1 | diff -d -urpN src.0/gdb/valops.c src.1/gdb/valops.c 2 | --- src.0/gdb/valops.c 2008-07-27 04:00:03.000000000 +0200 3 | +++ src.1/gdb/valops.c 2008-07-31 15:17:42.000000000 +0200 4 | @@ -813,10 +813,18 @@ value_assign (struct value *toval, struc 5 | struct frame_info *frame; 6 | int value_reg; 7 | 8 | - /* Figure out which frame this is in currently. */ 9 | - frame = frame_find_by_id (VALUE_FRAME_ID (toval)); 10 | value_reg = VALUE_REGNUM (toval); 11 | 12 | + /* Figure out which frame this is in currently. */ 13 | + frame = frame_find_by_id (VALUE_FRAME_ID (toval)); 14 | + /* "set $reg+=1" should work on programs with no debug info, 15 | + but frame_find_by_id returns NULL here (RH bug 436037). 16 | + Use current frame, it represents CPU state in this case. 17 | + If frame_find_by_id is changed to do it internally 18 | + (it is contemplated there), remove this. */ 19 | + if (!frame) 20 | + frame = get_current_frame (); 21 | + /* Probably never happens. */ 22 | if (!frame) 23 | error (_("Value being assigned to is no longer active.")); 24 | 25 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/hardware_monitor.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _HARDWARE_MONITOR_H_ 3 | #define _HARDWARE_MONITOR_H_ 4 | 5 | /* Communication between servers (such as the RSP server) and the target 6 | * monitor is done via 2 pipes, created using pipe(). One pipe, pipe_fds[0], 7 | * is used by the server to command the target monitor thread to stall or 8 | * unstall the CPU. This is done by sending single-letter commands; sending "S" 9 | * commands the monitor thread to stall the CPU, sending "U" commands the monitor 10 | * to unstall the CPU. 11 | * 12 | * Feedback is sent back to servers using pipe_fds[1]. When the CPU transitions 13 | * from the stalled state to the run state, an "R" is sent to all registered 14 | * servers. When the CPU goes from running to stopped, an "H" is sent to indicate 15 | * the halt state. 16 | */ 17 | 18 | /* This should be called once at initialization */ 19 | int start_monitor_thread(void); 20 | 21 | /* This is called to create a pair of shared pipes with the monitor thread. 22 | * The pipes should NOT have already been created before calling this function, 23 | * but the pipe_fds array must be already allocated. pipe_fds[0] is for 24 | * communicating server->monitor, pipe_fds[1] is for monitor->server. 25 | */ 26 | int register_with_monitor_thread(int pipe_fds[2]); 27 | 28 | /* Un-share a set of pipes with the monitor. The pipes may be closed 29 | * after this call returns. 30 | */ 31 | void unregister_with_monitor_thread(int pipe_fds[2]); 32 | 33 | 34 | #endif 35 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/hwp_server.h: -------------------------------------------------------------------------------- 1 | /* hwp_server.h -- Header for hardware watchpoint handling 2 | Copyright(C) 2010 Nathan Yawn 3 | 4 | This file is part the advanced debug unit / bridge. GDB does not 5 | have support for the OR1200's advanced hardware watchpoints. This 6 | acts as a server for a client program that can read and set them. 7 | 8 | This program is free software; you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation; either version 2 of the License, or 11 | (at your option) any later version. 12 | 13 | This program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this program; if not, write to the Free Software 20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ 21 | 22 | #ifndef _HWP_SERVER_H_ 23 | #define _HWP_SERVER_H_ 24 | 25 | 26 | void hwp_init(int portNum); 27 | int hwp_server_start(void); 28 | void hwp_server_stop(void); 29 | int hwp_get_available_watchpoint(void); 30 | void hwp_return_watchpoint(int wp); 31 | 32 | #endif 33 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/jsp_server.h: -------------------------------------------------------------------------------- 1 | /* jsp_server.h -- Header for the JTAG serial port 2 | Copyright(C) 2010 Nathan Yawn 3 | 4 | This file is part the advanced debug unit / bridge. The JSP server 5 | acts as a telnet server, to send and receive data for the JTAG Serial 6 | Port (JSP). 7 | 8 | This program is free software; you can redistribute it and/or modify 9 | it under the terms of the GNU General Public License as published by 10 | the Free Software Foundation; either version 2 of the License, or 11 | (at your option) any later version. 12 | 13 | This program is distributed in the hope that it will be useful, 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | GNU General Public License for more details. 17 | 18 | You should have received a copy of the GNU General Public License 19 | along with this program; if not, write to the Free Software 20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ 21 | 22 | #ifndef _JSP_SERVER_H_ 23 | #define _JSP_SERVER_H_ 24 | 25 | 26 | void jsp_init(int portNum); 27 | int jsp_server_start(void); 28 | void jsp_server_stop(void); 29 | 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/legacy_dbg_commands.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _LEGACY_DBG_COMMANDS_H_ 3 | #define _LEGACY_DBG_COMMANDS_H_ 4 | 5 | #define DC_SIZE 4 6 | #define DC_STATUS_SIZE 4 7 | 8 | #define DC_WISHBONE 0 9 | #define DC_CPU0 1 10 | #define DC_CPU1 2 11 | 12 | #define DI_GO 0 13 | #define DI_READ_CMD 1 14 | #define DI_WRITE_CMD 2 15 | #define DI_READ_CTRL 3 16 | #define DI_WRITE_CTRL 4 17 | 18 | 19 | // Interface to send commands to the legacy debug interface 20 | int legacy_dbg_set_chain(int chain); 21 | int legacy_dbg_command(int type, unsigned long adr, int len); 22 | int legacy_dbg_ctrl(int reset, int stall); 23 | int legacy_dbg_ctrl_read(int *reset, int *stall); 24 | int legacy_dbg_go(unsigned char *data, unsigned short len, int read); 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/opencores_tap.h: -------------------------------------------------------------------------------- 1 | #ifndef _OPENCORES_TAP_H_ 2 | #define _OPENCODER_TAP_H_ 3 | 4 | 5 | // Information on the OpenCores JTAG TAP 6 | // Included as a default, in place of a BSDL file 7 | // with the data. 8 | 9 | #define JI_SIZE (4) 10 | enum jtag_instr 11 | { 12 | JI_EXTEST = 0x0, 13 | JI_SAMPLE_PRELOAD = 0x1, 14 | JI_IDCODE = 0x2, 15 | JI_CHAIN_SELECT = 0x3, 16 | JI_INTEST = 0x4, 17 | JI_CLAMP = 0x5, 18 | JI_CLAMPZ = 0x6, 19 | JI_HIGHZ = 0x7, 20 | JI_DEBUG = 0x8, 21 | JI_BYPASS = 0xF 22 | }; 23 | 24 | #endif 25 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/or32_selftest.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _OR32_SELFTEST_H_ 3 | #define _OR32_SELFTEST_H_ 4 | 5 | // Static memory controller defines 6 | #define MC_BAR_0 0x00 7 | #define MC_AMR_0 0x04 8 | #define MC_WTR_0 0x30 9 | #define MC_RTR_0 0x34 10 | #define MC_OSR 0xe8 11 | #define MC_BAR_1 0x08 12 | #define MC_BAR_4 0x80 13 | #define MC_AMR_1 0x0c 14 | #define MC_AMR_4 0x84 15 | #define MC_CCR_1 0x24 16 | #define MC_CCR_4 0xa0 17 | #define MC_RATR 0xb0 18 | #define MC_RCDR 0xc8 19 | #define MC_RCTR 0xb4 20 | #define MC_REFCTR 0xc4 21 | #define MC_PTR 0xbc 22 | #define MC_RRDR 0xb8 23 | #define MC_RIR 0xcc 24 | #define MC_ORR 0xe4 25 | 26 | // Static flash defines 27 | #define FLASH_AMR_VAL 0xf0000000 28 | #define FLASH_WTR_VAL 0x00011009 29 | #define FLASH_RTR_VAL 0x01002009 30 | 31 | // Static SDRAM defines 32 | #define SDRAM_RATR_VAL 0x00000006 33 | #define SDRAM_RCDR_VAL 0x00000002 34 | #define SDRAM_RCTR_VAL 0x00000006 35 | #define SDRAM_REFCTR_VAL 0x00000006 36 | #define SDRAM_PTR_VAL 0x00000001 37 | #define SDRAM_RRDR_VAL 0x00000000 38 | #define SDRAM_RIR_VAL 0x000000C0 39 | 40 | // CPU defines 41 | #define CPU_OP_ADR 0 42 | #define CPU_SEL_ADR 1 43 | 44 | 45 | 46 | // None of the TC_* defines are currently used 47 | #define TC_RESET 0 48 | #define TC_BRIGHT 1 49 | #define TC_DIM 2 50 | #define TC_UNDERLINE 3 51 | #define TC_BLINK 4 52 | #define TC_REVERSE 7 53 | #define TC_HIDDEN 8 54 | 55 | #define TC_BLACK 0 56 | #define TC_RED 1 57 | #define TC_GREEN 2 58 | #define TC_YELLOW 3 59 | #define TC_BLUE 4 60 | #define TC_MAGENTA 5 61 | #define TC_CYAN 6 62 | #define TC_WHITE 7 63 | 64 | 65 | 66 | // Prototypes //////////////////////////////////////////// 67 | int dbg_test(); 68 | int stall_cpus(void); 69 | void init_mc(void); 70 | void init_sram(void); 71 | int test_sdram (void); 72 | int test_sdram_2(void); 73 | int test_sram(void); 74 | int test_or1k_cpu0(void); 75 | //int test_8051_cpu1(void); 76 | 77 | #endif // _OR32_SELFTEST_H_ 78 | 79 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/rsp-server.h: -------------------------------------------------------------------------------- 1 | /* rsp-server.c -- Remote Serial Protocol server for GDB 2 | 3 | Copyright (C) 2008 Embecosm Limited 4 | 5 | Contributor Jeremy Bennett 6 | 7 | This file was part of Or1ksim, the OpenRISC 1000 Architectural Simulator. 8 | Was actually purchased by Mom when I decided it was nice, but not affordable after two other recent pen purchases. 9 | 10 | This program is free software; you can redistribute it and/or modify it 11 | under the terms of the GNU General Public License as published by the Free 12 | Software Foundation; either version 3 of the License, or (at your option) 13 | any later version. 14 | 15 | This program is distributed in the hope that it will be useful, but WITHOUT 16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 | more details. 19 | 20 | You should have received a copy of the GNU General Public License along 21 | with this program. If not, see . 22 | */ 23 | 24 | /* This program is commented throughout in a fashion suitable for processing 25 | with Doxygen. */ 26 | 27 | 28 | #ifndef RSP_SERVER__H 29 | #define RSP_SERVER__H 30 | 31 | 32 | /* Function prototypes for external use */ 33 | void rsp_init (int portNum); 34 | int handle_rsp (void); // returns 1 normally, 0 for an unrecoverable error 35 | 36 | #endif /* RSP_SERVER__H */ 37 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | modelsim_win32: modelsim_win32/jp-io-vpi.dll 4 | 5 | modelsim_linux_x86: modelsim_linux_x86/jp-io-vpi.so 6 | 7 | icarus: icarus/jp-io-vpi.vpi 8 | 9 | 10 | 11 | modelsim_win32/jp-io-vpi.dll: src/jp-io-vpi.c 12 | cd modelsim_win32 && make 13 | 14 | modelsim_linux_x86/jp-io-vpi.so: src/jp-io-vpi.c 15 | cd modelsim_linux_x86 && make 16 | 17 | icarus/jp-io-vpi.vpi: src/jp-io-vpi.c 18 | cd icarus && make -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus/Makefile: -------------------------------------------------------------------------------- 1 | 2 | SRCDIR=../src/ 3 | 4 | 5 | 6 | default: vpi 7 | 8 | # This is for the Icarus simulator. 9 | jp-io-vpi.vpi: $(SRCDIR)jp-io-vpi.c 10 | iverilog-vpi $(SRCDIR)jp-io-vpi.c 11 | 12 | vpi: jp-io-vpi.vpi Makefile -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_linux_x86/Makefile: -------------------------------------------------------------------------------- 1 | 2 | SRCDIR=../src/ 3 | CC = gcc 4 | 5 | # The location of the ModelSim installation, used 6 | # to build the C lib for VPI. Must contain a subdir with 7 | # vpi_user.h. 8 | MODEL=/opt/modelsim 9 | 10 | 11 | 12 | default: vpi 13 | 14 | # This is for ModelSim under Linux (x86/32) 15 | # If RH v7.1 or lower, add -noinhibit-exec 16 | jp-io-vpi.so: $(SRCDIR)jp-io-vpi.c Makefile 17 | $(CC) -c -I$(MODEL)/modeltech/include $(SRCDIR)jp-io-vpi.c -o jp-io-vpi.o 18 | $(CC) -shared -Bsymbolic -o jp-io-vpi.so jp-io-vpi.o -lc 19 | 20 | vpi: jp-io-vpi.so Makefile -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_win32/Makefile: -------------------------------------------------------------------------------- 1 | 2 | SRCDIR=../src/ 3 | 4 | # The location of the ModelSim installation, used 5 | # to build the C lib for VPI. Used by MinGW, so use windows dir name, not /cygdrive/... 6 | MODEL=c:/altera/90/modelsim_ase 7 | 8 | # Different installs of Modelsim keep their libraries in different 9 | # directories (e.g. the version that comes with the Altera web version). 10 | # This directory must contain mtipli.dll 11 | MODEL_LIB=$(MODEL)/win32aloem 12 | 13 | # If building under windows, Modelsim requires that the VPI 14 | # library be compiled with MinGW, NOT cygwin GCC. The location 15 | # here is the default used by the auto-installer. 16 | MINGW_CC = c:/MinGW/bin/mingw32-gcc.exe 17 | 18 | 19 | default: vpi 20 | 21 | # This is for ModelSim under cygwin. Modelsim requires the shared lib 22 | # to be compiled with MinGW, not cygwin GCC. 23 | jp-io-vpi.dll: $(SRCDIR)jp-io-vpi.c Makefile 24 | $(MINGW_CC) -DWIN32 -c -I$(MODEL)/include $(SRCDIR)jp-io-vpi.c -o jp-io-vpi.o 25 | $(MINGW_CC) -DWIN32 -shared -Bsymbolic -o jp-io-vpi.dll jp-io-vpi.o -L$(MODEL_LIB) -lmtipli -lws2_32 26 | 27 | vpi: jp-io-vpi.dll Makefile -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_win32/jp-io-vpi.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_win32/jp-io-vpi.dll -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/src/jp-io-vpi.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/src/jp-io-vpi.c -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/utilities.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include "errcodes.h" 4 | 5 | 6 | int check_buffer_size(char **buf, int *buf_size_bytes, int requested_size_bytes) 7 | { 8 | int ret = APP_ERR_NONE; 9 | 10 | if(*buf_size_bytes >= requested_size_bytes) 11 | { 12 | return APP_ERR_NONE; 13 | } 14 | 15 | free(*buf); 16 | *buf = (char *) malloc(requested_size_bytes); 17 | if(*buf != NULL) { 18 | *buf_size_bytes = requested_size_bytes; 19 | } 20 | else { 21 | *buf_size_bytes = 0; 22 | ret = APP_ERR_MALLOC; 23 | } 24 | 25 | return ret; 26 | } 27 | -------------------------------------------------------------------------------- /fpga_hardware/cores/adv_debug_sys/Software/adv_jtag_bridge/utilities.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _UTILITIES_H_ 3 | #define _UTILITIES_H_ 4 | 5 | int check_buffer_size(char **buf, int *buf_size_bytes, int requested_size_bytes); 6 | 7 | #endif 8 | -------------------------------------------------------------------------------- /fpga_hardware/cores/bench/or1200_monitor_defines.v: -------------------------------------------------------------------------------- 1 | 2 | // 3 | // Top of TB 4 | // 5 | `define TB_TOP orpsoc_testbench 6 | 7 | // 8 | // Top of DUT 9 | // 10 | `define DUT_TOP `TB_TOP.dut 11 | 12 | // 13 | // Top of OR1200 inside test bench 14 | // 15 | `define OR1200_TOP `DUT_TOP.or1200_top0 16 | 17 | // 18 | // Define to enable lookup file generation 19 | // 20 | //`define OR1200_MONITOR_LOOKUP 21 | 22 | // 23 | // Define to enable SPR access log file generation 24 | // 25 | //`define OR1200_MONITOR_SPRS 26 | 27 | // 28 | // Enable logging of state during execution 29 | // 30 | //`define OR1200_MONITOR_EXEC_STATE 31 | 32 | // 33 | // Enable disassembly of instructions in execution state log 34 | // 35 | //`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY 36 | 37 | // 38 | // Enable verbose report l.nops (to both general log file and stdout) 39 | // 40 | `define OR1200_MONITOR_VERBOSE_NOPS 41 | 42 | // 43 | // Enable monitoring of control and execution flow (experimental) 44 | // 45 | //`define OR1200_SYSTEM_CHECKER 46 | 47 | // Can either individually enable things above, or usually have the scripts 48 | // running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to 49 | // enable them all. 50 | 51 | `ifdef PROCESSOR_MONITOR_ENABLE_LOGS 52 | `define OR1200_MONITOR_EXEC_STATE 53 | `define OR1200_MONITOR_SPRS 54 | `define OR1200_MONITOR_LOOKUP 55 | `endif 56 | 57 | // 58 | // Memory coherence checking (double check instruction in fetch stage against 59 | // what is in memory.) Useful for cache controller development. 60 | // 61 | //`define MEM_COHERENCE_CHECK 62 | 63 | // 64 | // Top of OR1200 inside test bench 65 | // 66 | `define CPU or1200 67 | `define CPU_cpu or1200_cpu 68 | `define CPU_rf or1200_rf 69 | `define CPU_except or1200_except 70 | `define CPU_ctrl or1200_ctrl 71 | `define CPU_sprs or1200_sprs 72 | `define CPU_immu_top or1200_immu_top 73 | `define CPU_immu_tlb or1200_immu_tlb 74 | `define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk 75 | 76 | 77 | `define OR1K_OPCODE_POS 31:26 78 | `define OR1K_J_BR_IMM_POS 25:0 79 | `define OR1K_RD_POS 25:21 80 | `define OR1K_RA_POS 20:16 81 | `define OR1K_RB_POS 15:11 82 | `define OR1K_ALU_OP_POS 3:0 83 | 84 | `define OR1K_SHROT_OP_POS 7:6 85 | `define OR1K_SHROTI_IMM_POS 5:0 86 | `define OR1K_SF_OP 25:21 87 | 88 | `define OR1K_XSYNC_OP_POS 25:21 89 | -------------------------------------------------------------------------------- /fpga_hardware/cores/bench/orpsoc-testbench-defines.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /fpga_hardware/cores/bench/synthesis-defines.v: -------------------------------------------------------------------------------- 1 | // Nothing in here, just providing synthesis-defines.v for files that include 2 | // it (clkgen, for one.) 3 | -------------------------------------------------------------------------------- /fpga_hardware/cores/bench/test-defines.v: -------------------------------------------------------------------------------- 1 | `define RTL_SIM 2 | `define SIMULATOR_MODELSIM 3 | `define TEST_NAME_STRING "or1200-simple" 4 | `define VCD 5 | //`define PROCESSOR_MONITOR_ENABLE_LOGS 6 | -------------------------------------------------------------------------------- /fpga_hardware/cores/bench/wiredelay.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | 4 | module wiredelay # ( 5 | parameter Delay_g = 0, 6 | parameter Delay_rd = 0 7 | ) 8 | ( 9 | inout A, 10 | inout B, 11 | input reset 12 | ); 13 | 14 | reg A_r; 15 | reg B_r; 16 | reg line_en; 17 | 18 | assign A = A_r; 19 | assign B = B_r; 20 | 21 | always @(*) begin 22 | if (!reset) begin 23 | A_r <= 1'bz; 24 | B_r <= 1'bz; 25 | line_en <= 1'b0; 26 | end else begin 27 | if (line_en) begin 28 | A_r <= #Delay_rd B; 29 | B_r <= 1'bz; 30 | end else begin 31 | B_r <= #Delay_g A; 32 | A_r <= 1'bz; 33 | end 34 | end 35 | end 36 | 37 | always @(A or B) begin 38 | if (!reset) begin 39 | line_en <= 1'b0; 40 | end else if (A !== A_r) begin 41 | line_en <= 1'b0; 42 | end else if (B_r !== B) begin 43 | line_en <= 1'b1; 44 | end else begin 45 | line_en <= line_en; 46 | end 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /fpga_hardware/cores/jtag_tap/README: -------------------------------------------------------------------------------- 1 | JTAG TAP RTL 2 | 3 | See the project's page on OpenCores for more information: 4 | http://opencores.org/project,jtag 5 | 6 | -------------------------------------------------------------------------------- /fpga_hardware/cores/top/synthesis-defines.v: -------------------------------------------------------------------------------- 1 | `define SYNTHESIS 2 | `define XILINX 3 | 4 | -------------------------------------------------------------------------------- /fpga_hardware/cores/uart16550/bench/vhdl/.keepme: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/uart16550/bench/vhdl/.keepme -------------------------------------------------------------------------------- /fpga_hardware/cores/uart16550/doc/UART_spec.pdf: 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--------------------------------------------------------------------------- 16 | 17 | TEST CASE execution summary: 18 | Number of tests PASSED=1 19 | Number of tests FAILED=1 20 | Simulation End Time: 5834521200 21 | 22 | --------------------------------------------------------------------------- 23 | 24 | -------------------------------------------------------------------------------- /fpga_hardware/cores/uart16550/sim/rtl_sim/out/.keepme: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/uart16550/sim/rtl_sim/out/.keepme -------------------------------------------------------------------------------- /fpga_hardware/cores/uart16550/sim/rtl_sim/run/run_signalscan: -------------------------------------------------------------------------------- 1 | signalscan ../out/uart/uart.trn & 2 | # -do ../out/uart/uart.do & 3 | -------------------------------------------------------------------------------- /fpga_hardware/cores/uart16550/sim/rtl_sim/run/run_sim: -------------------------------------------------------------------------------- 1 | ncverilog -f ../bin/nc.scr & 2 | -------------------------------------------------------------------------------- /fpga_hardware/cores/uart16550/sim/rtl_sim/src/.keepme: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/uart16550/sim/rtl_sim/src/.keepme -------------------------------------------------------------------------------- /fpga_hardware/cores/uart16550/syn/bin/.keepme: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/uart16550/syn/bin/.keepme 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https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/uart16550/syn/run/.keepme -------------------------------------------------------------------------------- /fpga_hardware/cores/uart16550/syn/src/.keepme: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/fpga_hardware/cores/uart16550/syn/src/.keepme -------------------------------------------------------------------------------- /fpga_hardware/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | 3 | `timescale 1 ps / 1 ps 4 | 5 | module glbl (); 6 | 7 | parameter ROC_WIDTH = 100000; 8 | parameter TOC_WIDTH = 0; 9 | 10 | //-------- STARTUP Globals -------------- 11 | wire GSR; 12 | wire GTS; 13 | wire GWE; 14 | wire PRLD; 15 | tri1 p_up_tmp; 16 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 17 | 18 | wire PROGB_GLBL; 19 | 20 | reg GSR_int; 21 | reg GTS_int; 22 | reg PRLD_int; 23 | 24 | //-------- JTAG Globals -------------- 25 | wire JTAG_TDO_GLBL; 26 | wire JTAG_TCK_GLBL; 27 | wire JTAG_TDI_GLBL; 28 | wire JTAG_TMS_GLBL; 29 | wire JTAG_TRST_GLBL; 30 | 31 | reg JTAG_CAPTURE_GLBL; 32 | reg JTAG_RESET_GLBL; 33 | reg JTAG_SHIFT_GLBL; 34 | reg JTAG_UPDATE_GLBL; 35 | reg JTAG_RUNTEST_GLBL; 36 | 37 | reg JTAG_SEL1_GLBL = 0; 38 | reg JTAG_SEL2_GLBL = 0 ; 39 | reg JTAG_SEL3_GLBL = 0; 40 | reg JTAG_SEL4_GLBL = 0; 41 | 42 | reg JTAG_USER_TDO1_GLBL = 1'bz; 43 | reg JTAG_USER_TDO2_GLBL = 1'bz; 44 | reg JTAG_USER_TDO3_GLBL = 1'bz; 45 | reg JTAG_USER_TDO4_GLBL = 1'bz; 46 | 47 | assign (weak1, weak0) GSR = GSR_int; 48 | assign (weak1, weak0) GTS = GTS_int; 49 | assign (weak1, weak0) PRLD = PRLD_int; 50 | 51 | initial begin 52 | GSR_int = 1'b1; 53 | PRLD_int = 1'b1; 54 | #(ROC_WIDTH) 55 | GSR_int = 1'b0; 56 | PRLD_int = 1'b0; 57 | end 58 | 59 | initial begin 60 | GTS_int = 1'b1; 61 | #(TOC_WIDTH) 62 | GTS_int = 1'b0; 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /fpga_hardware/runVSIM.sh: -------------------------------------------------------------------------------- 1 | vsim +notimingchecks -c -noglitch -t ps -novopt work.orpsoc_testbench 2 | #add wave -r /orpsoc_testbench/dut/xilinx_ddr2_0/xilinx_ddr2_if0/ddr2_mig0/u_ddr2_top_0/* 3 | #run -all 4 | -------------------------------------------------------------------------------- /software/bareBench/FFT/Makefile: -------------------------------------------------------------------------------- 1 | OBJ = main.o fftmisc.o fourierf.o 2 | FILE = main.c fftmisc.c fourierf.c 3 | CC = or32-elf-gcc 4 | CFLAGS = -mboard=ml509 -Os -DBARE_METAL -lnosys -lc 5 | 6 | fft: ${OBJ} Makefile 7 | $(CC) ${CFLAGS} ${OBJ} -o fft -lm 8 | or32-elf-objcopy -O binary fft fft.bin 9 | ../../utils/bin2vmem fft.bin > fft.vmem 10 | or32-elf-objdump -d fft > fft.lst 11 | fftmisc.o: fftmisc.c 12 | $(CC) ${CFLAGS} -c fftmisc.c 13 | fourierf.o: fourierf.c 14 | $(CC) ${CFLAGS} -c fourierf.c 15 | main.o: main.c ../*.h 16 | $(CC) ${CFLAGS} -c main.c 17 | 18 | clean: 19 | rm -rf *.o fft output* *.lst *.bin *.vmem *~ 20 | -------------------------------------------------------------------------------- /software/bareBench/FFT/ddc.h: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | 3 | ddc.h - Don Cross, October 1992. 4 | 5 | Generic ddclib stuff. 6 | 7 | ============================================================================*/ 8 | 9 | #ifndef __DDC_DDC_H 10 | #define __DDC_DDC_H 11 | 12 | // If you add something to DDCRET, please add the appropriate string 13 | // to the function DDCRET_String() in the file 'source\ddcret.cpp'. 14 | 15 | enum DDCRET 16 | { 17 | DDC_SUCCESS, // The operation succeded 18 | DDC_FAILURE, // The operation failed for unspecified reasons 19 | DDC_OUT_OF_MEMORY, // Operation failed due to running out of memory 20 | DDC_FILE_ERROR, // Operation encountered file I/O error 21 | DDC_INVALID_CALL, // Operation was called with invalid parameters 22 | DDC_USER_ABORT, // Operation was aborted by the user 23 | DDC_INVALID_FILE // File format does not match 24 | }; 25 | 26 | 27 | const char *DDCRET_String ( DDCRET ); // See source\ddcret.cpp 28 | 29 | 30 | #define TRUE 1 31 | #define FALSE 0 32 | 33 | typedef int dBOOLEAN; 34 | 35 | typedef unsigned char BYTE; 36 | 37 | typedef unsigned char UINT8; 38 | typedef signed char INT8; 39 | 40 | typedef unsigned short int UINT16; 41 | typedef signed short int INT16; 42 | typedef unsigned long int UINT32; 43 | typedef signed long int INT32; 44 | 45 | #ifdef __BORLANDC__ 46 | #if sizeof(UINT16) != 2 47 | #error Need to fix UINT16 and INT16 48 | #endif 49 | 50 | #if sizeof(UINT32) != 4 51 | #error Need to fix UINT32 and INT32 52 | #endif 53 | #endif 54 | 55 | #endif /* __DDC_DDC_H */ 56 | 57 | /*--- end of file ddc.h ---*/ 58 | -------------------------------------------------------------------------------- /software/bareBench/FFT/ddcmath.h: -------------------------------------------------------------------------------- 1 | /*========================================================================== 2 | 3 | ddcmath.h - Don Cross , October 1994. 4 | 5 | Contains useful math stuff. 6 | 7 | ==========================================================================*/ 8 | 9 | #ifndef __ddcmath_h 10 | #define __ddcmath_h 11 | 12 | #define DDC_PI (3.14159265358979323846) 13 | 14 | #endif /* __ddcmath_h */ 15 | 16 | /*--- end of file ddcmath.h ---*/ 17 | -------------------------------------------------------------------------------- /software/bareBench/FFT/fftmisc.c: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | 3 | fftmisc.c - Don Cross 4 | 5 | http://www.intersrv.com/~dcross/fft.html 6 | 7 | Helper routines for Fast Fourier Transform implementation. 8 | Contains common code for fft_float() and fft_double(). 9 | 10 | See also: 11 | fourierf.c 12 | fourierd.c 13 | ..\include\fourier.h 14 | 15 | Revision history: 16 | 17 | 1998 September 19 [Don Cross] 18 | Improved the efficiency of IsPowerOfTwo(). 19 | Updated coding standards. 20 | 21 | ============================================================================*/ 22 | 23 | #include 24 | #include 25 | #include 26 | 27 | #include "fourier.h" 28 | 29 | #define TRUE 1 30 | #define FALSE 0 31 | 32 | #define BITS_PER_WORD (sizeof(unsigned) * 8) 33 | 34 | 35 | int IsPowerOfTwo ( unsigned x ) 36 | { 37 | if ( x < 2 ) 38 | return FALSE; 39 | 40 | if ( x & (x-1) ) // Thanks to 'byang' for this cute trick! 41 | return FALSE; 42 | 43 | return TRUE; 44 | } 45 | 46 | 47 | unsigned NumberOfBitsNeeded ( unsigned PowerOfTwo ) 48 | { 49 | unsigned i; 50 | 51 | if ( PowerOfTwo < 2 ) 52 | { 53 | fprintf ( 54 | stderr, 55 | ">>> Error in fftmisc.c: argument %d to NumberOfBitsNeeded is too small.\n", 56 | PowerOfTwo ); 57 | 58 | exit(1); 59 | } 60 | 61 | for ( i=0; ; i++ ) 62 | { 63 | if ( PowerOfTwo & (1 << i) ) 64 | return i; 65 | } 66 | } 67 | 68 | 69 | 70 | unsigned ReverseBits ( unsigned index, unsigned NumBits ) 71 | { 72 | unsigned i, rev; 73 | 74 | for ( i=rev=0; i < NumBits; i++ ) 75 | { 76 | rev = (rev << 1) | (index & 1); 77 | index >>= 1; 78 | } 79 | 80 | return rev; 81 | } 82 | 83 | 84 | double Index_to_frequency ( unsigned NumSamples, unsigned Index ) 85 | { 86 | if ( Index >= NumSamples ) 87 | return 0.0; 88 | else if ( Index <= NumSamples/2 ) 89 | return (double)Index / (double)NumSamples; 90 | 91 | return -(double)(NumSamples-Index) / (double)NumSamples; 92 | } 93 | 94 | 95 | /*--- end of file fftmisc.c---*/ 96 | -------------------------------------------------------------------------------- /software/bareBench/FFT/fourier.h: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | 3 | fourier.h - Don Cross 4 | 5 | http://www.intersrv.com/~dcross/fft.html 6 | 7 | Contains definitions for doing Fourier transforms 8 | and inverse Fourier transforms. 9 | 10 | ============================================================================*/ 11 | 12 | #ifdef __cplusplus 13 | extern "C" { 14 | #endif 15 | 16 | /* 17 | ** fft() computes the Fourier transform or inverse transform 18 | ** of the complex inputs to produce the complex outputs. 19 | ** The number of samples must be a power of two to do the 20 | ** recursive decomposition of the FFT algorithm. 21 | ** See Chapter 12 of "Numerical Recipes in FORTRAN" by 22 | ** Press, Teukolsky, Vetterling, and Flannery, 23 | ** Cambridge University Press. 24 | ** 25 | ** Notes: If you pass ImaginaryIn = NULL, this function will "pretend" 26 | ** that it is an array of all zeroes. This is convenient for 27 | ** transforming digital samples of real number data without 28 | ** wasting memory. 29 | */ 30 | 31 | void fft_double ( 32 | unsigned NumSamples, /* must be a power of 2 */ 33 | int InverseTransform, /* 0=forward FFT, 1=inverse FFT */ 34 | double *RealIn, /* array of input's real samples */ 35 | double *ImaginaryIn, /* array of input's imag samples */ 36 | double *RealOut, /* array of output's reals */ 37 | double *ImaginaryOut ); /* array of output's imaginaries */ 38 | 39 | 40 | void fft_float ( 41 | unsigned NumSamples, /* must be a power of 2 */ 42 | int InverseTransform, /* 0=forward FFT, 1=inverse FFT */ 43 | float *RealIn, /* array of input's real samples */ 44 | float *ImaginaryIn, /* array of input's imag samples */ 45 | float *RealOut, /* array of output's reals */ 46 | float *ImaginaryOut ); /* array of output's imaginaries */ 47 | 48 | 49 | int IsPowerOfTwo ( unsigned x ); 50 | unsigned NumberOfBitsNeeded ( unsigned PowerOfTwo ); 51 | unsigned ReverseBits ( unsigned index, unsigned NumBits ); 52 | 53 | /* 54 | ** The following function returns an "abstract frequency" of a 55 | ** given index into a buffer with a given number of frequency samples. 56 | ** Multiply return value by sampling rate to get frequency expressed in Hz. 57 | */ 58 | double Index_to_frequency ( unsigned NumSamples, unsigned Index ); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | 65 | /*--- end of file fourier.h ---*/ 66 | -------------------------------------------------------------------------------- /software/bareBench/FFT/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include "../bareBench.h" 5 | 6 | int main() { 7 | unsigned MAXSIZE; 8 | unsigned MAXWAVES; 9 | unsigned i,j; 10 | int invfft=0; 11 | 12 | MAXSIZE=8; 13 | MAXWAVES=1; 14 | 15 | srand(1); 16 | 17 | float RealIn[MAXSIZE]; 18 | float ImagIn[MAXSIZE]; 19 | float RealOut[MAXSIZE]; 20 | float ImagOut[MAXSIZE]; 21 | float coeff[MAXWAVES]; 22 | float amp[MAXWAVES]; 23 | 24 | /* Makes MAXWAVES waves of random amplitude and period */ 25 | for(i=0;i 4 | 5 | int benchmark(); 6 | 7 | #define RUNS 2 8 | 9 | int main(void) 10 | { 11 | int run; 12 | 13 | // Run baseline 14 | printf("Baseline\n\r"); 15 | for(run = 0; run < RUNS; ++run) 16 | { 17 | printf("Run %d\n\r", run+1); 18 | benchmark(); 19 | } 20 | 21 | printf("Done\n\r"); 22 | return 0; 23 | } 24 | 25 | #define main(...) benchmark(__VA_ARGS__) 26 | 27 | #endif 28 | -------------------------------------------------------------------------------- /software/bareBench/basicmath/Makefile: -------------------------------------------------------------------------------- 1 | FILE1 = basicmath_small.c rad2deg.c cubic.c isqrt.c 2 | 3 | all: basicmath_small 4 | 5 | basicmath_small: ${FILE1} Makefile ../*.h 6 | or32-elf-gcc -mboard=ml509 -DBARE_METAL -Os ${FILE1} -o basicmath_small -lnosys -lc -lm 7 | or32-elf-objdump -d basicmath_small > basicmath_small.S 8 | or32-elf-objcopy -O binary basicmath_small basicmath_small.bin 9 | ../../utils/bin2vmem basicmath_small.bin > basicmath_small.vmem 10 | rm -f *.bin 11 | 12 | clean: 13 | rm -rf basicmath_small output* *.vmem *.S *~ 14 | -------------------------------------------------------------------------------- /software/bareBench/basicmath/basicmath_small.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include "snipmath.h" 3 | #include 4 | #include "../bareBench.h" 5 | 6 | /* The printf's may be removed to isolate just the math calculations */ 7 | 8 | int main(void) 9 | { 10 | double a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0; 11 | double a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0; 12 | double a3 = 1.0, b3 = -3.5, c3 = 22.0, d3 = -31.0; 13 | double a4 = 1.0, b4 = -13.7, c4 = 1.0, d4 = -35.0; 14 | double x[3]; 15 | double X; 16 | int solutions; 17 | int i; 18 | unsigned long l = 0x3fed0169L; 19 | struct int_sqrt q; 20 | 21 | /* solve soem cubic functions */ 22 | printf("********* CUBIC FUNCTIONS ***********\n\r"); 23 | /* should get 3 solutions: 2, 6 & 2.5 */ 24 | SolveCubic(a1, b1, c1, d1, &solutions, x); 25 | printf("Solutions:"); 26 | for(i=0;i0;b1--) { 48 | for(c1=5;c1<15;c1+=0.5) { 49 | for(d1=-1;d1>-11;d1--) { 50 | SolveCubic(a1, b1, c1, d1, &solutions, x); 51 | printf("Solutions:"); 52 | for(i=0;i 9 | #include 10 | #include "snipmath.h" 11 | 12 | void SolveCubic(double a, 13 | double b, 14 | double c, 15 | double d, 16 | int *solutions, 17 | double *x) 18 | { 19 | long double a1 = b/a, a2 = c/a, a3 = d/a; 20 | long double Q = (a1*a1 - 3.0*a2)/9.0; 21 | long double R = (2.0*a1*a1*a1 - 9.0*a1*a2 + 27.0*a3)/54.0; 22 | double R2_Q3 = R*R - Q*Q*Q; 23 | 24 | double theta; 25 | 26 | if (R2_Q3 <= 0) 27 | { 28 | *solutions = 3; 29 | theta = acos(R/sqrt(Q*Q*Q)); 30 | x[0] = -2.0*sqrt(Q)*cos(theta/3.0) - a1/3.0; 31 | x[1] = -2.0*sqrt(Q)*cos((theta+2.0*PI)/3.0) - a1/3.0; 32 | x[2] = -2.0*sqrt(Q)*cos((theta+4.0*PI)/3.0) - a1/3.0; 33 | } 34 | else 35 | { 36 | *solutions = 1; 37 | x[0] = pow(sqrt(R2_Q3)+fabs(R), 1/3.0); 38 | x[0] += Q/x[0]; 39 | x[0] *= (R < 0.0) ? 1 : -1; 40 | x[0] -= a1/3.0; 41 | } 42 | } 43 | 44 | #ifdef TEST 45 | 46 | int main(void) 47 | { 48 | double a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0; 49 | double a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0; 50 | double x[3]; 51 | int solutions; 52 | 53 | SolveCubic(a1, b1, c1, d1, &solutions, x); 54 | 55 | /* should get 3 solutions: 2, 6 & 2.5 */ 56 | 57 | SolveCubic(a2, b2, c2, d2, &solutions, x); 58 | 59 | /* should get 1 solution: 2.5 */ 60 | 61 | return 0; 62 | } 63 | 64 | #endif /* TEST */ 65 | -------------------------------------------------------------------------------- /software/bareBench/basicmath/isqrt.c: -------------------------------------------------------------------------------- 1 | /* +++Date last modified: 05-Jul-1997 */ 2 | 3 | #include 4 | #include "snipmath.h" 5 | 6 | #define BITSPERLONG 32 7 | 8 | #define TOP2BITS(x) ((x & (3L << (BITSPERLONG-2))) >> (BITSPERLONG-2)) 9 | 10 | 11 | /* usqrt: 12 | ENTRY x: unsigned long 13 | EXIT returns floor(sqrt(x) * pow(2, BITSPERLONG/2)) 14 | 15 | Since the square root never uses more than half the bits 16 | of the input, we use the other half of the bits to contain 17 | extra bits of precision after the binary point. 18 | 19 | EXAMPLE 20 | suppose BITSPERLONG = 32 21 | then usqrt(144) = 786432 = 12 * 65536 22 | usqrt(32) = 370727 = 5.66 * 65536 23 | 24 | NOTES 25 | (1) change BITSPERLONG to BITSPERLONG/2 if you do not want 26 | the answer scaled. Indeed, if you want n bits of 27 | precision after the binary point, use BITSPERLONG/2+n. 28 | The code assumes that BITSPERLONG is even. 29 | (2) This is really better off being written in assembly. 30 | The line marked below is really a "arithmetic shift left" 31 | on the double-long value with r in the upper half 32 | and x in the lower half. This operation is typically 33 | expressible in only one or two assembly instructions. 34 | (3) Unrolling this loop is probably not a bad idea. 35 | 36 | ALGORITHM 37 | The calculations are the base-two analogue of the square 38 | root algorithm we all learned in grammar school. Since we're 39 | in base 2, there is only one nontrivial trial multiplier. 40 | 41 | Notice that absolutely no multiplications or divisions are performed. 42 | This means it'll be fast on a wide range of processors. 43 | */ 44 | 45 | void usqrt(unsigned long x, struct int_sqrt *q) 46 | { 47 | unsigned long a = 0L; /* accumulator */ 48 | unsigned long r = 0L; /* remainder */ 49 | unsigned long e = 0L; /* trial product */ 50 | 51 | int i; 52 | 53 | for (i = 0; i < BITSPERLONG; i++) /* NOTE 1 */ 54 | { 55 | r = (r << 2) + TOP2BITS(x); x <<= 2; /* NOTE 2 */ 56 | a <<= 1; 57 | e = (a << 1) + 1; 58 | if (r >= e) 59 | { 60 | r -= e; 61 | a++; 62 | } 63 | } 64 | memcpy(q, &a, sizeof(long)); 65 | } 66 | 67 | #ifdef TEST 68 | 69 | #include 70 | #include 71 | 72 | main(void) 73 | { 74 | int i; 75 | unsigned long l = 0x3fed0169L; 76 | struct int_sqrt q; 77 | 78 | for (i = 0; i < 101; ++i) 79 | { 80 | usqrt(i, &q); 81 | printf("sqrt(%3d) = %2d, remainder = %2d\n", 82 | i, q.sqrt, q.frac); 83 | } 84 | usqrt(l, &q); 85 | printf("\nsqrt(%lX) = %X, remainder = %X\n", l, q.sqrt, q.frac); 86 | return 0; 87 | } 88 | 89 | #endif /* TEST */ 90 | -------------------------------------------------------------------------------- /software/bareBench/basicmath/pi.h: -------------------------------------------------------------------------------- 1 | /* +++Date last modified: 05-Jul-1997 */ 2 | 3 | #ifndef PI__H 4 | #define PI__H 5 | 6 | #ifndef PI 7 | #define PI (4*atan(1)) 8 | #endif 9 | 10 | #define deg2rad(d) ((d)*PI/180) 11 | #define rad2deg(r) ((r)*180/PI) 12 | 13 | #endif /* PI__H */ 14 | -------------------------------------------------------------------------------- /software/bareBench/basicmath/rad2deg.c: -------------------------------------------------------------------------------- 1 | /* +++Date last modified: 05-Jul-1997 */ 2 | 3 | /* 4 | ** RAD2DEG.C - Functions to convert between radians and degrees 5 | */ 6 | 7 | #include 8 | #include "snipmath.h" 9 | 10 | #undef rad2deg /* These are macros defined in PI.H */ 11 | #undef deg2rad 12 | 13 | double rad2deg(double rad) 14 | { 15 | return (180.0 * rad / (PI)); 16 | } 17 | 18 | double deg2rad(double deg) 19 | { 20 | return (PI * deg / 180.0); 21 | } 22 | 23 | #ifdef TEST 24 | 25 | #include 26 | 27 | main() 28 | { 29 | double X; 30 | 31 | for (X = 0.0; X <= 360.0; X += 45.0) 32 | printf("%3.0f degrees = %.12f radians\n", X, deg2rad(X)); 33 | puts(""); 34 | for (X = 0.0; X <= (2 * PI + 1e-6); X += (PI / 6)) 35 | printf("%.12f radians = %3.0f degrees\n", X, rad2deg(X)); 36 | return 0; 37 | } 38 | 39 | #endif /* TEST */ 40 | -------------------------------------------------------------------------------- /software/bareBench/basicmath/round.h: -------------------------------------------------------------------------------- 1 | /* +++Date last modified: 05-Jul-1997 */ 2 | 3 | /* 4 | ** rounding macros by Dave Knapp, Thad Smith, Jon Strayer, & Bob Stout 5 | */ 6 | 7 | #ifndef ROUND__H 8 | #define ROUND__H 9 | 10 | #include 11 | 12 | #if defined(__cplusplus) && __cplusplus 13 | 14 | /* 15 | ** Safe C++ inline versions 16 | */ 17 | 18 | /* round to integer */ 19 | 20 | inline int iround(double x) 21 | { 22 | return (int)floor(x + 0.5); 23 | } 24 | 25 | /* round number n to d decimal points */ 26 | 27 | inline double fround(double n, unsigned d) 28 | { 29 | return floor(n * pow(10., d) + .5) / pow(10., d); 30 | } 31 | 32 | #else 33 | 34 | /* 35 | ** NOTE: These C macro versions are unsafe since arguments are referenced 36 | ** more than once. 37 | ** 38 | ** Avoid using these with expression arguments to be safe. 39 | */ 40 | 41 | /* 42 | ** round to integer 43 | */ 44 | 45 | #define iround(x) floor((x) + 0.5) 46 | 47 | /* 48 | ** round number n to d decimal points 49 | */ 50 | 51 | #define fround(n,d) (floor((n)*pow(10.,(d))+.5)/pow(10.,(d))) 52 | 53 | #endif 54 | 55 | #endif /* ROUND__H */ 56 | -------------------------------------------------------------------------------- /software/bareBench/basicmath/snipmath.h: -------------------------------------------------------------------------------- 1 | /* +++Date last modified: 05-Jul-1997 */ 2 | 3 | /* 4 | ** SNIPMATH.H - Header file for SNIPPETS math functions and macros 5 | */ 6 | 7 | #ifndef SNIPMATH__H 8 | #define SNIPMATH__H 9 | 10 | #include 11 | #include "sniptype.h" 12 | #include "round.h" 13 | 14 | /* 15 | ** Callable library functions begin here 16 | */ 17 | 18 | void SetBCDLen(int n); /* Bcdl.C */ 19 | long BCDtoLong(char *BCDNum); /* Bcdl.C */ 20 | void LongtoBCD(long num, char BCDNum[]); /* Bcdl.C */ 21 | double bcd_to_double(void *buf, size_t len, /* Bcdd.C */ 22 | int digits); 23 | int double_to_bcd(double arg, char *buf, /* Bcdd.C */ 24 | size_t length, size_t digits ); 25 | DWORD ncomb1 (int n, int m); /* Combin.C */ 26 | DWORD ncomb2 (int n, int m); /* Combin.C */ 27 | void SolveCubic(double a, double b, double c, /* Cubic.C */ 28 | double d, int *solutions, 29 | double *x); 30 | DWORD dbl2ulong(double t); /* Dbl2Long.C */ 31 | long dbl2long(double t); /* Dbl2Long.C */ 32 | double dround(double x); /* Dblround.C */ 33 | 34 | /* Use #defines for Permutations and Combinations -- Factoryl.C */ 35 | 36 | #define log10P(n,r) (log10factorial(n)-log10factorial((n)-(r))) 37 | #define log10C(n,r) (log10P((n),(r))-log10factorial(r)) 38 | 39 | double log10factorial(double N); /* Factoryl.C */ 40 | 41 | double fibo(unsigned short term); /* Fibo.C */ 42 | double frandom(int n); /* Frand.C */ 43 | double ipow(double x, int n); /* Ipow.C */ 44 | int ispow2(int x); /* Ispow2.C */ 45 | long double ldfloor(long double a); /* Ldfloor.C */ 46 | int initlogscale(long dmax, long rmax); /* Logscale.C */ 47 | long logscale(long d); /* Logscale.C */ 48 | 49 | float MSBINToIEEE(float f); /* Msb2Ieee.C */ 50 | float IEEEToMSBIN(float f); /* Msb2Ieee.C */ 51 | int perm_index (char pit[], int size); /* Perm_Idx.C */ 52 | int round_div(int n, int d); /* Rnd_Div.C */ 53 | long round_ldiv(long n, long d); /* Rnd_Div.C */ 54 | double rad2deg(double rad); /* Rad2Deg.C */ 55 | double deg2rad(double deg); /* Rad2Deg.C */ 56 | 57 | #include "pi.h" 58 | #ifndef PHI 59 | #define PHI ((1.0+sqrt(5.0))/2.0) /* the golden number */ 60 | #define INV_PHI (1.0/PHI) /* the golden ratio */ 61 | #endif 62 | 63 | /* 64 | ** File: ISQRT.C 65 | */ 66 | 67 | struct int_sqrt { 68 | unsigned sqrt, 69 | frac; 70 | }; 71 | 72 | void usqrt(unsigned long x, struct int_sqrt *q); 73 | 74 | 75 | #endif /* SNIPMATH__H */ 76 | -------------------------------------------------------------------------------- /software/bareBench/basicmath/sniptype.h: -------------------------------------------------------------------------------- 1 | /* +++Date last modified: 05-Jul-1997 */ 2 | 3 | /* 4 | ** SNIPTYPE.H - Include file for SNIPPETS data types and commonly used macros 5 | */ 6 | 7 | #ifndef SNIPTYPE__H 8 | #define SNIPTYPE__H 9 | 10 | #include /* For free() */ 11 | #include /* For NULL & strlen() */ 12 | 13 | typedef enum {Error_ = -1, Success_, False_ = 0, True_} Boolean_T; 14 | 15 | /*#if !defined(WIN32) && !defined(_WIN32) && !defined(__NT__) \ 16 | && !defined(_WINDOWS) 17 | #if !defined(OS2)*/ 18 | typedef unsigned char BYTE; 19 | typedef unsigned long DWORD; 20 | /* #endif*/ 21 | typedef unsigned short WORD; 22 | /*#else 23 | #define WIN32_LEAN_AND_MEAN 24 | #define NOGDI 25 | #define NOSERVICE 26 | #undef INC_OLE1 27 | #undef INC_OLE2 28 | #include 29 | #define HUGE 30 | #endif*/ 31 | 32 | #define NUL '\0' 33 | #define LAST_CHAR(s) (((char *)s)[strlen(s) - 1]) 34 | #define TOBOOL(x) (!(!(x))) 35 | #define FREE(p) (free(p),(p)=NULL) 36 | 37 | #endif /* SNIPTYPE__H */ 38 | -------------------------------------------------------------------------------- /software/bareBench/dijkstra/Makefile: -------------------------------------------------------------------------------- 1 | all: dijkstra_large 2 | 3 | dijkstra_large: dijkstra_large.c Makefile 4 | or32-elf-gcc -mboard=ml509 -Os -DBARE_METAL dijkstra_large.c -o dijkstra_large -lnosys -lc 5 | or32-elf-objdump -d dijkstra_large > dijkstra.S 6 | or32-elf-objcopy -O binary dijkstra_large dijkstra.bin 7 | ../../utils/bin2vmem dijkstra.bin > dijkstra.vmem 8 | rm -f *.bin 9 | clean: 10 | rm -rf dijkstra_large dijkstra_small output* *.vmem *.S *~ 11 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/input_large.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/input_large.jpg -------------------------------------------------------------------------------- /software/bareBench/jpeg/input_large.ppm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/input_large.ppm -------------------------------------------------------------------------------- /software/bareBench/jpeg/input_small.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/input_small.jpg -------------------------------------------------------------------------------- /software/bareBench/jpeg/input_small.ppm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/input_small.ppm -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/ansi2knr.1: -------------------------------------------------------------------------------- 1 | .TH ANSI2KNR 1 "19 Jan 1996" 2 | .SH NAME 3 | ansi2knr \- convert ANSI C to Kernighan & Ritchie C 4 | .SH SYNOPSIS 5 | .I ansi2knr 6 | [--varargs] input_file [output_file] 7 | .SH DESCRIPTION 8 | If no output_file is supplied, output goes to stdout. 9 | .br 10 | There are no error messages. 11 | .sp 12 | .I ansi2knr 13 | recognizes function definitions by seeing a non-keyword identifier at the left 14 | margin, followed by a left parenthesis, with a right parenthesis as the last 15 | character on the line, and with a left brace as the first token on the 16 | following line (ignoring possible intervening comments). It will recognize a 17 | multi-line header provided that no intervening line ends with a left or right 18 | brace or a semicolon. These algorithms ignore whitespace and comments, except 19 | that the function name must be the first thing on the line. 20 | .sp 21 | The following constructs will confuse it: 22 | .br 23 | - Any other construct that starts at the left margin and follows the 24 | above syntax (such as a macro or function call). 25 | .br 26 | - Some macros that tinker with the syntax of the function header. 27 | .sp 28 | The --varargs switch is obsolete, and is recognized only for 29 | backwards compatibility. The present version of 30 | .I ansi2knr 31 | will always attempt to convert a ... argument to va_alist and va_dcl. 32 | .SH AUTHOR 33 | L. Peter Deutsch wrote the original ansi2knr and 34 | continues to maintain the current version; most of the code in the current 35 | version is his work. ansi2knr also includes contributions by Francois 36 | Pinard and Jim Avera . 37 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jchuff.h: -------------------------------------------------------------------------------- 1 | /* 2 | * jchuff.h 3 | * 4 | * Copyright (C) 1991-1996, Thomas G. Lane. 5 | * This file is part of the Independent JPEG Group's software. 6 | * For conditions of distribution and use, see the accompanying README file. 7 | * 8 | * This file contains declarations for Huffman entropy encoding routines 9 | * that are shared between the sequential encoder (jchuff.c) and the 10 | * progressive encoder (jcphuff.c). No other modules need to see these. 11 | */ 12 | 13 | /* Derived data constructed for each Huffman table */ 14 | 15 | typedef struct { 16 | unsigned int ehufco[256]; /* code for each symbol */ 17 | char ehufsi[256]; /* length of code for each symbol */ 18 | /* If no code has been allocated for a symbol S, ehufsi[S] contains 0 */ 19 | } c_derived_tbl; 20 | 21 | /* Short forms of external names for systems with brain-damaged linkers. */ 22 | 23 | #ifdef NEED_SHORT_EXTERNAL_NAMES 24 | #define jpeg_make_c_derived_tbl jMkCDerived 25 | #define jpeg_gen_optimal_table jGenOptTbl 26 | #endif /* NEED_SHORT_EXTERNAL_NAMES */ 27 | 28 | /* Expand a Huffman table definition into the derived format */ 29 | EXTERN(void) jpeg_make_c_derived_tbl 30 | JPP((j_compress_ptr cinfo, JHUFF_TBL * htbl, c_derived_tbl ** pdtbl)); 31 | 32 | /* Generate an optimal table definition given the specified counts */ 33 | EXTERN(void) jpeg_gen_optimal_table 34 | JPP((j_compress_ptr cinfo, JHUFF_TBL * htbl, long freq[])); 35 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jcinit.c: -------------------------------------------------------------------------------- 1 | /* 2 | * jcinit.c 3 | * 4 | * Copyright (C) 1991-1996, Thomas G. Lane. 5 | * This file is part of the Independent JPEG Group's software. 6 | * For conditions of distribution and use, see the accompanying README file. 7 | * 8 | * This file contains initialization logic for the JPEG compressor. 9 | * This routine is in charge of selecting the modules to be executed and 10 | * making an initialization call to each one. 11 | * 12 | * Logically, this code belongs in jcmaster.c. It's split out because 13 | * linking this routine implies linking the entire compression library. 14 | * For a transcoding-only application, we want to be able to use jcmaster.c 15 | * without linking in the whole library. 16 | */ 17 | 18 | #define JPEG_INTERNALS 19 | #include "jinclude.h" 20 | #include "jpeglib.h" 21 | 22 | 23 | /* 24 | * Master selection of compression modules. 25 | * This is done once at the start of processing an image. We determine 26 | * which modules will be used and give them appropriate initialization calls. 27 | */ 28 | 29 | GLOBAL(void) 30 | jinit_compress_master (j_compress_ptr cinfo) 31 | { 32 | /* Initialize master control (includes parameter checking/processing) */ 33 | jinit_c_master_control(cinfo, FALSE /* full compression */); 34 | 35 | /* Preprocessing */ 36 | if (! cinfo->raw_data_in) { 37 | jinit_color_converter(cinfo); 38 | jinit_downsampler(cinfo); 39 | jinit_c_prep_controller(cinfo, FALSE /* never need full buffer here */); 40 | } 41 | /* Forward DCT */ 42 | jinit_forward_dct(cinfo); 43 | /* Entropy encoding: either Huffman or arithmetic coding. */ 44 | if (cinfo->arith_code) { 45 | ERREXIT(cinfo, JERR_ARITH_NOTIMPL); 46 | } else { 47 | if (cinfo->progressive_mode) { 48 | #ifdef C_PROGRESSIVE_SUPPORTED 49 | jinit_phuff_encoder(cinfo); 50 | #else 51 | ERREXIT(cinfo, JERR_NOT_COMPILED); 52 | #endif 53 | } else 54 | jinit_huff_encoder(cinfo); 55 | } 56 | 57 | /* Need a full-image coefficient buffer in any multi-pass mode. */ 58 | jinit_c_coef_controller(cinfo, 59 | (cinfo->num_scans > 1 || cinfo->optimize_coding)); 60 | jinit_c_main_controller(cinfo, FALSE /* never need full buffer here */); 61 | 62 | jinit_marker_writer(cinfo); 63 | 64 | /* We can now tell the memory manager to allocate virtual arrays. */ 65 | (*cinfo->mem->realize_virt_arrays) ((j_common_ptr) cinfo); 66 | 67 | /* Write the datastream header (SOI) immediately. 68 | * Frame and scan headers are postponed till later. 69 | * This lets application insert special markers after the SOI. 70 | */ 71 | (*cinfo->marker->write_file_header) (cinfo); 72 | } 73 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jcomapi.c: -------------------------------------------------------------------------------- 1 | /* 2 | * jcomapi.c 3 | * 4 | * Copyright (C) 1994-1996, Thomas G. Lane. 5 | * This file is part of the Independent JPEG Group's software. 6 | * For conditions of distribution and use, see the accompanying README file. 7 | * 8 | * This file contains application interface routines that are used for both 9 | * compression and decompression. 10 | */ 11 | 12 | #define JPEG_INTERNALS 13 | #include "jinclude.h" 14 | #include "jpeglib.h" 15 | 16 | 17 | /* 18 | * Abort processing of a JPEG compression or decompression operation, 19 | * but don't destroy the object itself. 20 | * 21 | * For this, we merely clean up all the nonpermanent memory pools. 22 | * Note that temp files (virtual arrays) are not allowed to belong to 23 | * the permanent pool, so we will be able to close all temp files here. 24 | * Closing a data source or destination, if necessary, is the application's 25 | * responsibility. 26 | */ 27 | 28 | GLOBAL(void) 29 | jpeg_abort (j_common_ptr cinfo) 30 | { 31 | int pool; 32 | 33 | /* Releasing pools in reverse order might help avoid fragmentation 34 | * with some (brain-damaged) malloc libraries. 35 | */ 36 | for (pool = JPOOL_NUMPOOLS-1; pool > JPOOL_PERMANENT; pool--) { 37 | (*cinfo->mem->free_pool) (cinfo, pool); 38 | } 39 | 40 | /* Reset overall state for possible reuse of object */ 41 | cinfo->global_state = (cinfo->is_decompressor ? DSTATE_START : CSTATE_START); 42 | } 43 | 44 | 45 | /* 46 | * Destruction of a JPEG object. 47 | * 48 | * Everything gets deallocated except the master jpeg_compress_struct itself 49 | * and the error manager struct. Both of these are supplied by the application 50 | * and must be freed, if necessary, by the application. (Often they are on 51 | * the stack and so don't need to be freed anyway.) 52 | * Closing a data source or destination, if necessary, is the application's 53 | * responsibility. 54 | */ 55 | 56 | GLOBAL(void) 57 | jpeg_destroy (j_common_ptr cinfo) 58 | { 59 | /* We need only tell the memory manager to release everything. */ 60 | /* NB: mem pointer is NULL if memory mgr failed to initialize. */ 61 | if (cinfo->mem != NULL) 62 | (*cinfo->mem->self_destruct) (cinfo); 63 | cinfo->mem = NULL; /* be safe if jpeg_destroy is called twice */ 64 | cinfo->global_state = 0; /* mark it destroyed */ 65 | } 66 | 67 | 68 | /* 69 | * Convenience routines for allocating quantization and Huffman tables. 70 | * (Would jutils.c be a more reasonable place to put these?) 71 | */ 72 | 73 | GLOBAL(JQUANT_TBL *) 74 | jpeg_alloc_quant_table (j_common_ptr cinfo) 75 | { 76 | JQUANT_TBL *tbl; 77 | 78 | tbl = (JQUANT_TBL *) 79 | (*cinfo->mem->alloc_small) (cinfo, JPOOL_PERMANENT, SIZEOF(JQUANT_TBL)); 80 | tbl->sent_table = FALSE; /* make sure this is false in any new table */ 81 | return tbl; 82 | } 83 | 84 | 85 | GLOBAL(JHUFF_TBL *) 86 | jpeg_alloc_huff_table (j_common_ptr cinfo) 87 | { 88 | JHUFF_TBL *tbl; 89 | 90 | tbl = (JHUFF_TBL *) 91 | (*cinfo->mem->alloc_small) (cinfo, JPOOL_PERMANENT, SIZEOF(JHUFF_TBL)); 92 | tbl->sent_table = FALSE; /* make sure this is false in any new table */ 93 | return tbl; 94 | } 95 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.bcc: -------------------------------------------------------------------------------- 1 | /* jconfig.bcc --- jconfig.h for Borland C (Turbo C) on MS-DOS or OS/2. */ 2 | /* see jconfig.doc for explanations */ 3 | 4 | #define HAVE_PROTOTYPES 5 | #define HAVE_UNSIGNED_CHAR 6 | #define HAVE_UNSIGNED_SHORT 7 | /* #define void char */ 8 | /* #define const */ 9 | #undef CHAR_IS_UNSIGNED 10 | #define HAVE_STDDEF_H 11 | #define HAVE_STDLIB_H 12 | #undef NEED_BSD_STRINGS 13 | #undef NEED_SYS_TYPES_H 14 | #ifdef __MSDOS__ 15 | #define NEED_FAR_POINTERS /* for small or medium memory model */ 16 | #endif 17 | #undef NEED_SHORT_EXTERNAL_NAMES 18 | #undef INCOMPLETE_TYPES_BROKEN /* this assumes you have -w-stu in CFLAGS */ 19 | 20 | #ifdef JPEG_INTERNALS 21 | 22 | #undef RIGHT_SHIFT_IS_UNSIGNED 23 | 24 | #ifdef __MSDOS__ 25 | #define USE_MSDOS_MEMMGR /* Define this if you use jmemdos.c */ 26 | #define MAX_ALLOC_CHUNK 65520L /* Maximum request to malloc() */ 27 | #define USE_FMEM /* Borland has _fmemcpy() and _fmemset() */ 28 | #endif 29 | 30 | #endif /* JPEG_INTERNALS */ 31 | 32 | #ifdef JPEG_CJPEG_DJPEG 33 | 34 | #define BMP_SUPPORTED /* BMP image file format */ 35 | #define GIF_SUPPORTED /* GIF image file format */ 36 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 37 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 38 | #define TARGA_SUPPORTED /* Targa image file format */ 39 | 40 | #define TWO_FILE_COMMANDLINE 41 | #define USE_SETMODE /* Borland has setmode() */ 42 | #ifdef __MSDOS__ 43 | #define NEED_SIGNAL_CATCHER /* Define this if you use jmemdos.c */ 44 | #endif 45 | #undef DONT_USE_B_MODE 46 | #undef PROGRESS_REPORT /* optional */ 47 | 48 | #endif /* JPEG_CJPEG_DJPEG */ 49 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.cfg: -------------------------------------------------------------------------------- 1 | /* jconfig.cfg --- source file edited by configure script */ 2 | /* see jconfig.doc for explanations */ 3 | 4 | #undef HAVE_PROTOTYPES 5 | #undef HAVE_UNSIGNED_CHAR 6 | #undef HAVE_UNSIGNED_SHORT 7 | #undef void 8 | #undef const 9 | #undef CHAR_IS_UNSIGNED 10 | #undef HAVE_STDDEF_H 11 | #undef HAVE_STDLIB_H 12 | #undef NEED_BSD_STRINGS 13 | #undef NEED_SYS_TYPES_H 14 | #undef NEED_FAR_POINTERS 15 | #undef NEED_SHORT_EXTERNAL_NAMES 16 | /* Define this if you get warnings about undefined structures. */ 17 | #undef INCOMPLETE_TYPES_BROKEN 18 | 19 | #ifdef JPEG_INTERNALS 20 | 21 | #undef RIGHT_SHIFT_IS_UNSIGNED 22 | #undef INLINE 23 | /* These are for configuring the JPEG memory manager. */ 24 | #undef DEFAULT_MAX_MEM 25 | #undef NO_MKTEMP 26 | 27 | #endif /* JPEG_INTERNALS */ 28 | 29 | #ifdef JPEG_CJPEG_DJPEG 30 | 31 | #define BMP_SUPPORTED /* BMP image file format */ 32 | #define GIF_SUPPORTED /* GIF image file format */ 33 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 34 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 35 | #define TARGA_SUPPORTED /* Targa image file format */ 36 | 37 | #undef TWO_FILE_COMMANDLINE 38 | #undef NEED_SIGNAL_CATCHER 39 | #undef DONT_USE_B_MODE 40 | 41 | /* Define this if you want percent-done progress reports from cjpeg/djpeg. */ 42 | #undef PROGRESS_REPORT 43 | 44 | #endif /* JPEG_CJPEG_DJPEG */ 45 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.dj: -------------------------------------------------------------------------------- 1 | /* jconfig.dj --- jconfig.h for DJGPP (Delorie's GNU C port) on MS-DOS. */ 2 | /* see jconfig.doc for explanations */ 3 | 4 | #define HAVE_PROTOTYPES 5 | #define HAVE_UNSIGNED_CHAR 6 | #define HAVE_UNSIGNED_SHORT 7 | /* #define void char */ 8 | /* #define const */ 9 | #undef CHAR_IS_UNSIGNED 10 | #define HAVE_STDDEF_H 11 | #define HAVE_STDLIB_H 12 | #undef NEED_BSD_STRINGS 13 | #undef NEED_SYS_TYPES_H 14 | #undef NEED_FAR_POINTERS /* DJGPP uses flat 32-bit addressing */ 15 | #undef NEED_SHORT_EXTERNAL_NAMES 16 | #undef INCOMPLETE_TYPES_BROKEN 17 | 18 | #ifdef JPEG_INTERNALS 19 | 20 | #undef RIGHT_SHIFT_IS_UNSIGNED 21 | 22 | #endif /* JPEG_INTERNALS */ 23 | 24 | #ifdef JPEG_CJPEG_DJPEG 25 | 26 | #define BMP_SUPPORTED /* BMP image file format */ 27 | #define GIF_SUPPORTED /* GIF image file format */ 28 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 29 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 30 | #define TARGA_SUPPORTED /* Targa image file format */ 31 | 32 | #undef TWO_FILE_COMMANDLINE /* optional */ 33 | #define USE_SETMODE /* Needed to make one-file style work in DJGPP */ 34 | #undef NEED_SIGNAL_CATCHER /* Define this if you use jmemname.c */ 35 | #undef DONT_USE_B_MODE 36 | #undef PROGRESS_REPORT /* optional */ 37 | 38 | #endif /* JPEG_CJPEG_DJPEG */ 39 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.h: -------------------------------------------------------------------------------- 1 | /* jconfig.h. Generated automatically by configure. */ 2 | /* jconfig.cfg --- source file edited by configure script */ 3 | /* see jconfig.doc for explanations */ 4 | 5 | #define HAVE_PROTOTYPES 6 | #define HAVE_UNSIGNED_CHAR 7 | #define HAVE_UNSIGNED_SHORT 8 | #undef void 9 | #undef const 10 | #undef CHAR_IS_UNSIGNED 11 | #define HAVE_STDDEF_H 12 | #define HAVE_STDLIB_H 13 | #undef NEED_BSD_STRINGS 14 | #undef NEED_SYS_TYPES_H 15 | #undef NEED_FAR_POINTERS 16 | #undef NEED_SHORT_EXTERNAL_NAMES 17 | /* Define this if you get warnings about undefined structures. */ 18 | #undef INCOMPLETE_TYPES_BROKEN 19 | 20 | #ifdef JPEG_INTERNALS 21 | 22 | #undef RIGHT_SHIFT_IS_UNSIGNED 23 | #define INLINE inline 24 | /* These are for configuring the JPEG memory manager. */ 25 | #undef DEFAULT_MAX_MEM 26 | #undef NO_MKTEMP 27 | 28 | #endif /* JPEG_INTERNALS */ 29 | 30 | #ifdef JPEG_CJPEG_DJPEG 31 | 32 | #define BMP_SUPPORTED /* BMP image file format */ 33 | #define GIF_SUPPORTED /* GIF image file format */ 34 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 35 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 36 | #define TARGA_SUPPORTED /* Targa image file format */ 37 | 38 | #undef TWO_FILE_COMMANDLINE 39 | #undef NEED_SIGNAL_CATCHER 40 | #undef DONT_USE_B_MODE 41 | 42 | /* Define this if you want percent-done progress reports from cjpeg/djpeg. */ 43 | #undef PROGRESS_REPORT 44 | 45 | #endif /* JPEG_CJPEG_DJPEG */ 46 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.manx: -------------------------------------------------------------------------------- 1 | /* jconfig.manx --- jconfig.h for Amiga systems using Manx Aztec C ver 5.x. */ 2 | /* see jconfig.doc for explanations */ 3 | 4 | #define HAVE_PROTOTYPES 5 | #define HAVE_UNSIGNED_CHAR 6 | #define HAVE_UNSIGNED_SHORT 7 | /* #define void char */ 8 | /* #define const */ 9 | #undef CHAR_IS_UNSIGNED 10 | #define HAVE_STDDEF_H 11 | #define HAVE_STDLIB_H 12 | #undef NEED_BSD_STRINGS 13 | #undef NEED_SYS_TYPES_H 14 | #undef NEED_FAR_POINTERS 15 | #undef NEED_SHORT_EXTERNAL_NAMES 16 | #undef INCOMPLETE_TYPES_BROKEN 17 | 18 | #ifdef JPEG_INTERNALS 19 | 20 | #undef RIGHT_SHIFT_IS_UNSIGNED 21 | 22 | #define TEMP_DIRECTORY "JPEGTMP:" /* recommended setting for Amiga */ 23 | 24 | #define SHORTxSHORT_32 /* produces better DCT code with Aztec C */ 25 | 26 | #endif /* JPEG_INTERNALS */ 27 | 28 | #ifdef JPEG_CJPEG_DJPEG 29 | 30 | #define BMP_SUPPORTED /* BMP image file format */ 31 | #define GIF_SUPPORTED /* GIF image file format */ 32 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 33 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 34 | #define TARGA_SUPPORTED /* Targa image file format */ 35 | 36 | #define TWO_FILE_COMMANDLINE 37 | #define NEED_SIGNAL_CATCHER 38 | #undef DONT_USE_B_MODE 39 | #undef PROGRESS_REPORT /* optional */ 40 | 41 | #define signal_catcher _abort /* hack for Aztec C naming requirements */ 42 | 43 | #endif /* JPEG_CJPEG_DJPEG */ 44 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.mc6: -------------------------------------------------------------------------------- 1 | /* jconfig.mc6 --- jconfig.h for Microsoft C on MS-DOS, version 6.00A & up. */ 2 | /* see jconfig.doc for explanations */ 3 | 4 | #define HAVE_PROTOTYPES 5 | #define HAVE_UNSIGNED_CHAR 6 | #define HAVE_UNSIGNED_SHORT 7 | /* #define void char */ 8 | /* #define const */ 9 | #undef CHAR_IS_UNSIGNED 10 | #define HAVE_STDDEF_H 11 | #define HAVE_STDLIB_H 12 | #undef NEED_BSD_STRINGS 13 | #undef NEED_SYS_TYPES_H 14 | #define NEED_FAR_POINTERS /* for small or medium memory model */ 15 | #undef NEED_SHORT_EXTERNAL_NAMES 16 | #undef INCOMPLETE_TYPES_BROKEN 17 | 18 | #ifdef JPEG_INTERNALS 19 | 20 | #undef RIGHT_SHIFT_IS_UNSIGNED 21 | 22 | #define USE_MSDOS_MEMMGR /* Define this if you use jmemdos.c */ 23 | 24 | #define MAX_ALLOC_CHUNK 65520L /* Maximum request to malloc() */ 25 | 26 | #define USE_FMEM /* Microsoft has _fmemcpy() and _fmemset() */ 27 | 28 | #define NEED_FHEAPMIN /* far heap management routines are broken */ 29 | 30 | #define SHORTxLCONST_32 /* enable compiler-specific DCT optimization */ 31 | /* Note: the above define is known to improve the code with Microsoft C 6.00A. 32 | * I do not know whether it is good for later compiler versions. 33 | * Please report any info on this point to jpeg-info@uunet.uu.net. 34 | */ 35 | 36 | #endif /* JPEG_INTERNALS */ 37 | 38 | #ifdef JPEG_CJPEG_DJPEG 39 | 40 | #define BMP_SUPPORTED /* BMP image file format */ 41 | #define GIF_SUPPORTED /* GIF image file format */ 42 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 43 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 44 | #define TARGA_SUPPORTED /* Targa image file format */ 45 | 46 | #define TWO_FILE_COMMANDLINE 47 | #define USE_SETMODE /* Microsoft has setmode() */ 48 | #define NEED_SIGNAL_CATCHER /* Define this if you use jmemdos.c */ 49 | #undef DONT_USE_B_MODE 50 | #undef PROGRESS_REPORT /* optional */ 51 | 52 | #endif /* JPEG_CJPEG_DJPEG */ 53 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.sas: -------------------------------------------------------------------------------- 1 | /* jconfig.sas --- jconfig.h for Amiga systems using SAS C 6.0 and up. */ 2 | /* see jconfig.doc for explanations */ 3 | 4 | #define HAVE_PROTOTYPES 5 | #define HAVE_UNSIGNED_CHAR 6 | #define HAVE_UNSIGNED_SHORT 7 | /* #define void char */ 8 | /* #define const */ 9 | #undef CHAR_IS_UNSIGNED 10 | #define HAVE_STDDEF_H 11 | #define HAVE_STDLIB_H 12 | #undef NEED_BSD_STRINGS 13 | #undef NEED_SYS_TYPES_H 14 | #undef NEED_FAR_POINTERS 15 | #undef NEED_SHORT_EXTERNAL_NAMES 16 | #undef INCOMPLETE_TYPES_BROKEN 17 | 18 | #ifdef JPEG_INTERNALS 19 | 20 | #undef RIGHT_SHIFT_IS_UNSIGNED 21 | 22 | #define TEMP_DIRECTORY "JPEGTMP:" /* recommended setting for Amiga */ 23 | 24 | #define NO_MKTEMP /* SAS C doesn't have mktemp() */ 25 | 26 | #define SHORTxSHORT_32 /* produces better DCT code with SAS C */ 27 | 28 | #endif /* JPEG_INTERNALS */ 29 | 30 | #ifdef JPEG_CJPEG_DJPEG 31 | 32 | #define BMP_SUPPORTED /* BMP image file format */ 33 | #define GIF_SUPPORTED /* GIF image file format */ 34 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 35 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 36 | #define TARGA_SUPPORTED /* Targa image file format */ 37 | 38 | #define TWO_FILE_COMMANDLINE 39 | #define NEED_SIGNAL_CATCHER 40 | #undef DONT_USE_B_MODE 41 | #undef PROGRESS_REPORT /* optional */ 42 | 43 | #endif /* JPEG_CJPEG_DJPEG */ 44 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.st: -------------------------------------------------------------------------------- 1 | /* jconfig.st --- jconfig.h for Atari ST/STE/TT using Pure C or Turbo C. */ 2 | /* see jconfig.doc for explanations */ 3 | 4 | #define HAVE_PROTOTYPES 5 | #define HAVE_UNSIGNED_CHAR 6 | #define HAVE_UNSIGNED_SHORT 7 | /* #define void char */ 8 | /* #define const */ 9 | #undef CHAR_IS_UNSIGNED 10 | #define HAVE_STDDEF_H 11 | #define HAVE_STDLIB_H 12 | #undef NEED_BSD_STRINGS 13 | #undef NEED_SYS_TYPES_H 14 | #undef NEED_FAR_POINTERS 15 | #undef NEED_SHORT_EXTERNAL_NAMES 16 | #define INCOMPLETE_TYPES_BROKEN /* suppress undefined-structure warnings */ 17 | 18 | #ifdef JPEG_INTERNALS 19 | 20 | #undef RIGHT_SHIFT_IS_UNSIGNED 21 | 22 | #define ALIGN_TYPE long /* apparently double is a weird size? */ 23 | 24 | #endif /* JPEG_INTERNALS */ 25 | 26 | #ifdef JPEG_CJPEG_DJPEG 27 | 28 | #define BMP_SUPPORTED /* BMP image file format */ 29 | #define GIF_SUPPORTED /* GIF image file format */ 30 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 31 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 32 | #define TARGA_SUPPORTED /* Targa image file format */ 33 | 34 | #define TWO_FILE_COMMANDLINE /* optional -- undef if you like Unix style */ 35 | /* Note: if you undef TWO_FILE_COMMANDLINE, you may need to define 36 | * USE_SETMODE. Some Atari compilers require it, some do not. 37 | */ 38 | #define NEED_SIGNAL_CATCHER /* needed if you use jmemname.c */ 39 | #undef DONT_USE_B_MODE 40 | #undef PROGRESS_REPORT /* optional */ 41 | 42 | #endif /* JPEG_CJPEG_DJPEG */ 43 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.vms: -------------------------------------------------------------------------------- 1 | /* jconfig.vms --- jconfig.h for use on Digital VMS. */ 2 | /* see jconfig.doc for explanations */ 3 | 4 | #define HAVE_PROTOTYPES 5 | #define HAVE_UNSIGNED_CHAR 6 | #define HAVE_UNSIGNED_SHORT 7 | /* #define void char */ 8 | /* #define const */ 9 | #undef CHAR_IS_UNSIGNED 10 | #define HAVE_STDDEF_H 11 | #define HAVE_STDLIB_H 12 | #undef NEED_BSD_STRINGS 13 | #undef NEED_SYS_TYPES_H 14 | #undef NEED_FAR_POINTERS 15 | #undef NEED_SHORT_EXTERNAL_NAMES 16 | #undef INCOMPLETE_TYPES_BROKEN 17 | 18 | #ifdef JPEG_INTERNALS 19 | 20 | #undef RIGHT_SHIFT_IS_UNSIGNED 21 | 22 | #endif /* JPEG_INTERNALS */ 23 | 24 | #ifdef JPEG_CJPEG_DJPEG 25 | 26 | #define BMP_SUPPORTED /* BMP image file format */ 27 | #define GIF_SUPPORTED /* GIF image file format */ 28 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 29 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 30 | #define TARGA_SUPPORTED /* Targa image file format */ 31 | 32 | #define TWO_FILE_COMMANDLINE /* Needed on VMS */ 33 | #undef NEED_SIGNAL_CATCHER 34 | #undef DONT_USE_B_MODE 35 | #undef PROGRESS_REPORT /* optional */ 36 | 37 | #endif /* JPEG_CJPEG_DJPEG */ 38 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jconfig.wat: -------------------------------------------------------------------------------- 1 | /* jconfig.wat --- jconfig.h for Watcom C/C++ on MS-DOS or OS/2. */ 2 | /* see jconfig.doc for explanations */ 3 | 4 | #define HAVE_PROTOTYPES 5 | #define HAVE_UNSIGNED_CHAR 6 | #define HAVE_UNSIGNED_SHORT 7 | /* #define void char */ 8 | /* #define const */ 9 | #define CHAR_IS_UNSIGNED 10 | #define HAVE_STDDEF_H 11 | #define HAVE_STDLIB_H 12 | #undef NEED_BSD_STRINGS 13 | #undef NEED_SYS_TYPES_H 14 | #undef NEED_FAR_POINTERS /* Watcom uses flat 32-bit addressing */ 15 | #undef NEED_SHORT_EXTERNAL_NAMES 16 | #undef INCOMPLETE_TYPES_BROKEN 17 | 18 | #ifdef JPEG_INTERNALS 19 | 20 | #undef RIGHT_SHIFT_IS_UNSIGNED 21 | 22 | #endif /* JPEG_INTERNALS */ 23 | 24 | #ifdef JPEG_CJPEG_DJPEG 25 | 26 | #define BMP_SUPPORTED /* BMP image file format */ 27 | #define GIF_SUPPORTED /* GIF image file format */ 28 | #define PPM_SUPPORTED /* PBMPLUS PPM/PGM image file format */ 29 | #undef RLE_SUPPORTED /* Utah RLE image file format */ 30 | #define TARGA_SUPPORTED /* Targa image file format */ 31 | 32 | #undef TWO_FILE_COMMANDLINE /* optional */ 33 | #define USE_SETMODE /* Needed to make one-file style work in Watcom */ 34 | #undef NEED_SIGNAL_CATCHER /* Define this if you use jmemname.c */ 35 | #undef DONT_USE_B_MODE 36 | #undef PROGRESS_REPORT /* optional */ 37 | 38 | #endif /* JPEG_CJPEG_DJPEG */ 39 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/jversion.h: -------------------------------------------------------------------------------- 1 | /* 2 | * jversion.h 3 | * 4 | * Copyright (C) 1991-1996, Thomas G. Lane. 5 | * This file is part of the Independent JPEG Group's software. 6 | * For conditions of distribution and use, see the accompanying README file. 7 | * 8 | * This file contains software version identification. 9 | */ 10 | 11 | 12 | #define JVERSION "6a 7-Feb-96" 13 | 14 | #define JCOPYRIGHT "Copyright (C) 1996, Thomas G. Lane" 15 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/makcjpeg.st: -------------------------------------------------------------------------------- 1 | ; Project file for Independent JPEG Group's software 2 | ; 3 | ; This project file is for Atari ST/STE/TT systems using Pure C or Turbo C. 4 | ; Thanks to Frank Moehle (Frank.Moehle@arbi.informatik.uni-oldenburg.de) 5 | ; and to Dr. B. Setzepfandt (bernd@gina.uni-muenster.de). 6 | ; 7 | ; To use this file, rename it to CJPEG.PRJ. 8 | ; If you are using Turbo C, change filenames beginning with "PC..." to "TC..." 9 | ; Read installation instructions before trying to make the program! 10 | ; 11 | ; 12 | ; * * * Output file * * * 13 | cjpeg.ttp 14 | ; 15 | ; * * * COMPILER OPTIONS * * * 16 | .C[-P] ; absolute calls 17 | .C[-M] ; and no string merging, folks 18 | .C[-w-cln] ; no "constant is long" warnings 19 | .C[-w-par] ; no "parameter xxxx unused" 20 | .C[-w-rch] ; no "unreachable code" 21 | .C[-wsig] ; warn if significant digits may be lost 22 | = 23 | ; * * * * List of modules * * * * 24 | PCSTART.O 25 | cjpeg.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h,jversion.h) 26 | cdjpeg.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 27 | rdswitch.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 28 | rdppm.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 29 | rdgif.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 30 | rdtarga.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 31 | rdbmp.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 32 | rdrle.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 33 | LIBJPEG.LIB ; built by LIBJPEG.PRJ 34 | PCFLTLIB.LIB ; floating point library 35 | ; the float library can be omitted if you've turned off DCT_FLOAT_SUPPORTED 36 | PCSTDLIB.LIB ; standard library 37 | PCEXTLIB.LIB ; extended library 38 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/makdjpeg.st: -------------------------------------------------------------------------------- 1 | ; Project file for Independent JPEG Group's software 2 | ; 3 | ; This project file is for Atari ST/STE/TT systems using Pure C or Turbo C. 4 | ; Thanks to Frank Moehle (Frank.Moehle@arbi.informatik.uni-oldenburg.de) 5 | ; and to Dr. B. Setzepfandt (bernd@gina.uni-muenster.de). 6 | ; 7 | ; To use this file, rename it to DJPEG.PRJ. 8 | ; If you are using Turbo C, change filenames beginning with "PC..." to "TC..." 9 | ; Read installation instructions before trying to make the program! 10 | ; 11 | ; 12 | ; * * * Output file * * * 13 | djpeg.ttp 14 | ; 15 | ; * * * COMPILER OPTIONS * * * 16 | .C[-P] ; absolute calls 17 | .C[-M] ; and no string merging, folks 18 | .C[-w-cln] ; no "constant is long" warnings 19 | .C[-w-par] ; no "parameter xxxx unused" 20 | .C[-w-rch] ; no "unreachable code" 21 | .C[-wsig] ; warn if significant digits may be lost 22 | = 23 | ; * * * * List of modules * * * * 24 | PCSTART.O 25 | djpeg.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h,jversion.h) 26 | cdjpeg.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 27 | rdcolmap.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 28 | wrppm.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 29 | wrgif.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 30 | wrtarga.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 31 | wrbmp.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 32 | wrrle.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 33 | LIBJPEG.LIB ; built by LIBJPEG.PRJ 34 | PCFLTLIB.LIB ; floating point library 35 | ; the float library can be omitted if you've turned off DCT_FLOAT_SUPPORTED 36 | PCSTDLIB.LIB ; standard library 37 | PCEXTLIB.LIB ; extended library 38 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/maktjpeg.st: -------------------------------------------------------------------------------- 1 | ; Project file for Independent JPEG Group's software 2 | ; 3 | ; This project file is for Atari ST/STE/TT systems using Pure C or Turbo C. 4 | ; Thanks to Frank Moehle (Frank.Moehle@arbi.informatik.uni-oldenburg.de) 5 | ; and to Dr. B. Setzepfandt (bernd@gina.uni-muenster.de). 6 | ; 7 | ; To use this file, rename it to JPEGTRAN.PRJ. 8 | ; If you are using Turbo C, change filenames beginning with "PC..." to "TC..." 9 | ; Read installation instructions before trying to make the program! 10 | ; 11 | ; 12 | ; * * * Output file * * * 13 | jpegtran.ttp 14 | ; 15 | ; * * * COMPILER OPTIONS * * * 16 | .C[-P] ; absolute calls 17 | .C[-M] ; and no string merging, folks 18 | .C[-w-cln] ; no "constant is long" warnings 19 | .C[-w-par] ; no "parameter xxxx unused" 20 | .C[-w-rch] ; no "unreachable code" 21 | .C[-wsig] ; warn if significant digits may be lost 22 | = 23 | ; * * * * List of modules * * * * 24 | PCSTART.O 25 | jpegtran.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h,jversion.h) 26 | cdjpeg.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 27 | rdswitch.c (cdjpeg.h,jinclude.h,jconfig.h,jpeglib.h,jmorecfg.h,jerror.h,cderror.h) 28 | LIBJPEG.LIB ; built by LIBJPEG.PRJ 29 | PCSTDLIB.LIB ; standard library 30 | PCEXTLIB.LIB ; extended library 31 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/makvms.opt: -------------------------------------------------------------------------------- 1 | ! A pointer to the VAX/VMS C Run-Time Shareable Library. 2 | ! This file is needed by makefile.mms and makefile.vms, 3 | ! but only for the older VAX C compiler. DEC C does not need it. 4 | Sys$Library:VAXCRTL.EXE /Share 5 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/rdjpgcom.1: -------------------------------------------------------------------------------- 1 | .TH RDJPGCOM 1 "15 June 1995" 2 | .SH NAME 3 | rdjpgcom \- display text comments from a JPEG file 4 | .SH SYNOPSIS 5 | .B rdjpgcom 6 | [ 7 | .B \-verbose 8 | ] 9 | [ 10 | .I filename 11 | ] 12 | .LP 13 | .SH DESCRIPTION 14 | .LP 15 | .B rdjpgcom 16 | reads the named JPEG/JFIF file, or the standard input if no file is named, 17 | and prints any text comments found in the file on the standard output. 18 | .PP 19 | The JPEG standard allows "comment" (COM) blocks to occur within a JPEG file. 20 | Although the standard doesn't actually define what COM blocks are for, they 21 | are widely used to hold user-supplied text strings. This lets you add 22 | annotations, titles, index terms, etc to your JPEG files, and later retrieve 23 | them as text. COM blocks do not interfere with the image stored in the JPEG 24 | file. The maximum size of a COM block is 64K, but you can have as many of 25 | them as you like in one JPEG file. 26 | .SH OPTIONS 27 | .TP 28 | .B \-verbose 29 | Causes 30 | .B rdjpgcom 31 | to also display the JPEG image dimensions. 32 | .PP 33 | Switch names may be abbreviated, and are not case sensitive. 34 | .SH HINTS 35 | .B rdjpgcom 36 | does not depend on the IJG JPEG library. Its source code is intended as an 37 | illustration of the minimum amount of code required to parse a JPEG file 38 | header correctly. 39 | .SH SEE ALSO 40 | .BR cjpeg (1), 41 | .BR djpeg (1), 42 | .BR jpegtran (1), 43 | .BR wrjpgcom (1) 44 | .SH AUTHOR 45 | Independent JPEG Group 46 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/testimg.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/jpeg-6a/testimg.gif -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/testimg.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/jpeg-6a/testimg.jpg -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/testimg.ppm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/jpeg-6a/testimg.ppm -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/testimgp.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/jpeg-6a/testimgp.jpg -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/testorig.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/jpeg-6a/testorig.jpg -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/testprog.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/impedimentToProgress/A2/8e758631a2670bf9feff7de78dc3a8327b94c324/software/bareBench/jpeg/jpeg-6a/testprog.jpg -------------------------------------------------------------------------------- /software/bareBench/jpeg/jpeg-6a/wrjpgcom.1: -------------------------------------------------------------------------------- 1 | .TH WRJPGCOM 1 "15 June 1995" 2 | .SH NAME 3 | wrjpgcom \- insert text comments into a JPEG file 4 | .SH SYNOPSIS 5 | .B wrjpgcom 6 | [ 7 | .B \-replace 8 | ] 9 | [ 10 | .BI \-comment " text" 11 | ] 12 | [ 13 | .BI \-cfile " name" 14 | ] 15 | [ 16 | .I filename 17 | ] 18 | .LP 19 | .SH DESCRIPTION 20 | .LP 21 | .B wrjpgcom 22 | reads the named JPEG/JFIF file, or the standard input if no file is named, 23 | and generates a new JPEG/JFIF file on standard output. A comment block is 24 | added to the file. 25 | .PP 26 | The JPEG standard allows "comment" (COM) blocks to occur within a JPEG file. 27 | Although the standard doesn't actually define what COM blocks are for, they 28 | are widely used to hold user-supplied text strings. This lets you add 29 | annotations, titles, index terms, etc to your JPEG files, and later retrieve 30 | them as text. COM blocks do not interfere with the image stored in the JPEG 31 | file. The maximum size of a COM block is 64K, but you can have as many of 32 | them as you like in one JPEG file. 33 | .PP 34 | .B wrjpgcom 35 | adds a COM block, containing text you provide, to a JPEG file. 36 | Ordinarily, the COM block is added after any existing COM blocks; but you 37 | can delete the old COM blocks if you wish. 38 | .SH OPTIONS 39 | Switch names may be abbreviated, and are not case sensitive. 40 | .TP 41 | .B \-replace 42 | Delete any existing COM blocks from the file. 43 | .TP 44 | .BI \-comment " text" 45 | Supply text for new COM block on command line. 46 | .TP 47 | .BI \-cfile " name" 48 | Read text for new COM block from named file. 49 | .PP 50 | If you have only one line of comment text to add, you can provide it on the 51 | command line with 52 | .BR \-comment . 53 | The comment text must be surrounded with quotes so that it is treated as a 54 | single argument. Longer comments can be read from a text file. 55 | .PP 56 | If you give neither 57 | .B \-comment 58 | nor 59 | .BR \-cfile , 60 | then 61 | .B wrjpgcom 62 | will read the comment text from standard input. (In this case an input image 63 | file name MUST be supplied, so that the source JPEG file comes from somewhere 64 | else.) You can enter multiple lines, up to 64KB worth. Type an end-of-file 65 | indicator (usually control-D) to terminate the comment text entry. 66 | .PP 67 | .B wrjpgcom 68 | will not add a COM block if the provided comment string is empty. Therefore 69 | \fB\-replace \-comment ""\fR can be used to delete all COM blocks from a file. 70 | .SH EXAMPLES 71 | .LP 72 | Add a short comment to in.jpg, producing out.jpg: 73 | .IP 74 | .B wrjpgcom \-c 75 | \fI"View of my back yard" in.jpg 76 | .B > 77 | .I out.jpg 78 | .PP 79 | Attach a long comment previously stored in comment.txt: 80 | .IP 81 | .B wrjpgcom 82 | .I in.jpg 83 | .B < 84 | .I comment.txt 85 | .B > 86 | .I out.jpg 87 | .PP 88 | or equivalently 89 | .IP 90 | .B wrjpgcom 91 | .B -cfile 92 | .I comment.txt 93 | .B < 94 | .I in.jpg 95 | .B > 96 | .I out.jpg 97 | .SH SEE ALSO 98 | .BR cjpeg (1), 99 | .BR djpeg (1), 100 | .BR jpegtran (1), 101 | .BR rdjpgcom (1) 102 | .SH AUTHOR 103 | Independent JPEG Group 104 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/runme_large.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | jpeg-6a/cjpeg -dct int -progressive -opt -outfile output_large_encode.jpeg input_large.ppm 3 | jpeg-6a/djpeg -dct int -ppm -outfile output_large_decode.ppm input_large.jpg 4 | -------------------------------------------------------------------------------- /software/bareBench/jpeg/runme_small.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | jpeg-6a/cjpeg -dct int -progressive -opt -outfile output_small_encode.jpeg input_small.ppm 3 | jpeg-6a/djpeg -dct int -ppm -outfile output_small_decode.ppm input_small.jpg 4 | -------------------------------------------------------------------------------- /software/bareBench/sha/Makefile: -------------------------------------------------------------------------------- 1 | # By default, the code is compiled for a "big endian" machine. 2 | # To compile on a "little endian" machine set the LITTLE_ENDIAN flag. 3 | # To make smaller object code, but run a little slower, don't use UNROLL_LOOPS. 4 | # To use NIST's modified SHA of 7/11/94, define USE_MODIFIED_SHA 5 | 6 | CC = or32-elf-gcc 7 | CFLAGS = -DBARE_METAL -mboard=ml509 -O3 -lnosys -lc 8 | 9 | sha: *.c Makefile ../*.h *.h 10 | $(CC) $(CFLAGS) -o sha sha_driver.c sha.c 11 | or32-elf-objdump -d sha > sha.S 12 | or32-elf-objcopy -O binary sha sha.bin 13 | ../../utils/bin2vmem sha.bin > sha.vmem 14 | rm -f *.bin 15 | 16 | clean: 17 | rm -rf *.o sha output* *.vmem *.S *~ 18 | -------------------------------------------------------------------------------- /software/bareBench/sha/input.h: -------------------------------------------------------------------------------- 1 | char inputString[] = "VonnegutsCommencementAddressatMITLadiesandgentlemenoftheclassof97Wearsunscreen."; 2 | -------------------------------------------------------------------------------- /software/bareBench/sha/sha.h: -------------------------------------------------------------------------------- 1 | #ifndef SHA_H 2 | #define SHA_H 3 | 4 | /* NIST Secure Hash Algorithm */ 5 | /* heavily modified from Peter C. Gutmann's implementation */ 6 | 7 | /* Useful defines & typedefs */ 8 | 9 | typedef unsigned char BYTE; 10 | typedef unsigned long LONG; 11 | 12 | #define SHA_BLOCKSIZE 64 13 | #define SHA_DIGESTSIZE 20 14 | 15 | typedef struct { 16 | LONG digest[5]; /* message digest */ 17 | LONG count_lo, count_hi; /* 64-bit bit count */ 18 | LONG data[16]; /* SHA data buffer */ 19 | } SHA_INFO; 20 | 21 | void sha_init(SHA_INFO *); 22 | void sha_update(SHA_INFO *, BYTE *, int); 23 | void sha_final(SHA_INFO *); 24 | 25 | void sha_stream(SHA_INFO *, char *); 26 | void sha_print(SHA_INFO *); 27 | 28 | #endif /* SHA_H */ 29 | -------------------------------------------------------------------------------- /software/bareBench/sha/sha_driver.c: -------------------------------------------------------------------------------- 1 | /* NIST Secure Hash Algorithm */ 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include "../bareBench.h" 8 | #include "sha.h" 9 | #include "input.h" 10 | 11 | int main() 12 | { 13 | SHA_INFO sha_info; 14 | 15 | sha_stream(&sha_info, inputString); 16 | sha_print(&sha_info); 17 | 18 | return(0); 19 | } 20 | -------------------------------------------------------------------------------- /software/bareBench/stringsearch/Makefile: -------------------------------------------------------------------------------- 1 | FILE2 = bmhasrch.c bmhisrch.c bmhsrch.c pbmsrch_large.c 2 | 3 | all: search_large 4 | 5 | search_large: ${FILE2} Makefile ../*.h 6 | or32-elf-gcc -DBARE_METAL -mboard=ml509 ${FILE2} -Os -o search_large -lnosys -lc 7 | or32-elf-objdump -d search_large > search.S 8 | or32-elf-objcopy -O binary search_large search.bin 9 | ../../utils/bin2vmem search.bin > search.vmem 10 | rm -f *.bin 11 | 12 | clean: 13 | rm -rf search_large output* *.vmem *.S *~ 14 | -------------------------------------------------------------------------------- /software/bareBench/stringsearch/bmhsrch.c: -------------------------------------------------------------------------------- 1 | /* +++Date last modified: 05-Jul-1997 */ 2 | 3 | /* 4 | ** Case-sensitive Boyer-Moore-Horspool pattern match 5 | ** 6 | ** public domain by Raymond Gardner 7/92 7 | ** 8 | ** limitation: pattern length + string length must be less than 32767 9 | ** 10 | ** 10/21/93 rdg Fixed bug found by Jeff Dunlop 11 | */ 12 | #include /* rdg 10/93 */ 13 | #include 14 | #include 15 | typedef unsigned char uchar; 16 | 17 | 18 | #define LARGE 32767 19 | 20 | static int patlen; 21 | static int skip[UCHAR_MAX+1]; /* rdg 10/93 */ 22 | static int skip2; 23 | static uchar *pat; 24 | 25 | void bmh_init(const char *pattern) 26 | { 27 | int i, lastpatchar; 28 | 29 | pat = (uchar *)pattern; 30 | patlen = strlen(pattern); 31 | for (i = 0; i <= UCHAR_MAX; ++i) /* rdg 10/93 */ 32 | skip[i] = patlen; 33 | for (i = 0; i < patlen; ++i) 34 | skip[pat[i]] = patlen - i - 1; 35 | lastpatchar = pat[patlen - 1]; 36 | skip[lastpatchar] = LARGE; 37 | skip2 = patlen; /* Horspool's fixed second shift */ 38 | for (i = 0; i < patlen - 1; ++i) 39 | { 40 | if (pat[i] == lastpatchar) 41 | skip2 = patlen - i - 1; 42 | } 43 | } 44 | 45 | char *bmh_search(const char *string, const int stringlen) 46 | { 47 | int i, j; 48 | char *s; 49 | 50 | i = patlen - 1 - stringlen; 51 | if (i >= 0) 52 | return NULL; 53 | string += stringlen; 54 | for ( ;; ) 55 | { 56 | while ( (i += skip[((uchar *)string)[i]]) < 0 ) 57 | ; /* mighty fast inner loop */ 58 | if (i < (LARGE - stringlen)) 59 | return NULL; 60 | i -= LARGE; 61 | j = patlen - 1; 62 | s = (char *)string + (i - j); 63 | while (--j >= 0 && s[j] == pat[j]) 64 | ; 65 | if ( j < 0 ) /* rdg 10/93 */ 66 | return s; /* rdg 10/93 */ 67 | if ( (i += skip2) >= 0 ) /* rdg 10/93 */ 68 | return NULL; /* rdg 10/93 */ 69 | } 70 | } 71 | -------------------------------------------------------------------------------- /software/bareBench/stringsearch/search.h: -------------------------------------------------------------------------------- 1 | /* +++Date last modified: 05-Jul-1997 */ 2 | 3 | /* 4 | ** SNIPPETS string searching functions 5 | */ 6 | 7 | void init_search(const char *string); /* Pbmsrch.C */ 8 | char *strsearch(const char *string); /* Pbmsrch.C */ 9 | void bmh_init(const char *pattern); /* Bmhsrch.C */ 10 | char *bmh_search(const char *string, /* Bmhsrch.C */ 11 | const int stringlen); 12 | void bmhi_init(const char *pattern); /* Bhmisrch.C */ 13 | char *bmhi_search(const char *string, /* Bhmisrch.C */ 14 | const int stringlen); 15 | void bmha_init(const char *pattern); /* Bmhasrch.C */ 16 | char *bmha_search(const char *string, /* Bmhasrch.C */ 17 | const int stringlen); 18 | -------------------------------------------------------------------------------- /software/ml509DRAM.S: -------------------------------------------------------------------------------- 1 | #include "or1k-asm.h" 2 | 3 | /* 4 | * Define symbols to be used during startup - file is linked at compile time 5 | * 6 | */ 7 | .weak _board_mem_base 8 | .weak _board_mem_size 9 | .weak _board_clk_freq 10 | 11 | _board_mem_base: .long 0x0 12 | _board_mem_size: .long 0x08000000 13 | 14 | _board_clk_freq: .long 50000000 15 | 16 | /* Peripheral information - Set base to 0 if not present*/ 17 | .weak _board_uart_base 18 | .weak _board_uart_baud 19 | .weak _board_uart_IRQ 20 | 21 | _board_uart_base: .long 0x90000000 22 | _board_uart_baud: .long 115200 23 | _board_uart_IRQ: .long 2 24 | 25 | .weak _board_exit 26 | _board_exit: 27 | l.j _board_exit 28 | l.nop 0x1 29 | 30 | .global _board_init_early 31 | _board_init_early: 32 | OR1K_DELAYED_NOP(l.jr r9) 33 | 34 | .weak _board_init 35 | _board_init: 36 | OR1K_DELAYED_NOP(l.jr r9) 37 | -------------------------------------------------------------------------------- /software/ml509SRAM.S: -------------------------------------------------------------------------------- 1 | #include "or1k-asm.h" 2 | 3 | /* 4 | * Define symbols to be used during startup - file is linked at compile time 5 | * 6 | */ 7 | .weak _board_mem_base 8 | .weak _board_mem_size 9 | .weak _board_clk_freq 10 | 11 | _board_mem_base: .long 0x0 12 | _board_mem_size: .long 0x20000 13 | 14 | _board_clk_freq: .long 50000000 15 | 16 | /* Peripheral information - Set base to 0 if not present*/ 17 | .weak _board_uart_base 18 | .weak _board_uart_baud 19 | .weak _board_uart_IRQ 20 | 21 | _board_uart_base: .long 0x90000000 22 | _board_uart_baud: .long 115200 23 | _board_uart_IRQ: .long 2 24 | 25 | .weak _board_exit 26 | _board_exit: 27 | l.j _board_exit 28 | l.nop 0x1 29 | 30 | .global _board_init_early 31 | _board_init_early: 32 | OR1K_DELAYED_NOP(l.jr r9) 33 | 34 | .weak _board_init 35 | _board_init: 36 | OR1K_DELAYED_NOP(l.jr r9) 37 | -------------------------------------------------------------------------------- /software/picojpeg/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all : picojpegtest 3 | 4 | jpegdata.h : bintoc.c 5 | gcc -O2 bintoc.c -o bintoc 6 | ./bintoc 7 | 8 | clean : 9 | rm -rf host 10 | rm -rf out.bmp 11 | rm -rf bintoc 12 | rm -rf jpegdata.h 13 | rm -f *.bin 14 | rm -f *.bc 15 | rm -f *.o 16 | rm -f *.elf 17 | rm -f *.list 18 | rm -f picojpegtest 19 | rm -f picojpegtest.S 20 | rm -f *.vmem 21 | rm -f *~ 22 | 23 | ARMGNU = or32-elf 24 | COPS = -Wall -Os -mboard=ml509 25 | 26 | picojpegtest : Makefile picojpegtest.c picojpeg.h jpegdata.h 27 | $(ARMGNU)-gcc $(COPS) picojpeg.c picojpegtest.c -o picojpegtest -lnosys -lc 28 | $(ARMGNU)-objdump -d picojpegtest > picojpegtest.S 29 | $(ARMGNU)-objcopy -O binary picojpegtest picojpegtest.bin 30 | ../utils/bin2vmem picojpegtest.bin > picojpeg.vmem 31 | rm -f picojpegtest.bin 32 | -------------------------------------------------------------------------------- /software/picojpeg/bintoc.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | #include 4 | #include 5 | 6 | FILE *fpin,*fpout; 7 | 8 | unsigned int dlen; 9 | unsigned char data[100000]; 10 | 11 | int main ( void ) 12 | { 13 | unsigned int ra; 14 | 15 | fpin=fopen("michigan.jpg","rb"); 16 | if(fpin==NULL) return(1); 17 | dlen=fread(data,1,sizeof(data),fpin); 18 | fclose(fpin); 19 | printf("%u bytes read\n",dlen); 20 | fpout=fopen("jpegdata.h","wt"); 21 | if(fpout==NULL) return(1); 22 | fprintf(fpout,"\n"); 23 | fprintf(fpout,"\n"); 24 | fprintf(fpout,"const unsigned char jpegdata[]=\n"); 25 | fprintf(fpout,"{\n"); 26 | for(ra=0;ra 2 | #include "picojpeg.h" 3 | #include "jpegdata.h" 4 | 5 | unsigned int doff; 6 | 7 | unsigned char pjpeg_need_bytes_callback(unsigned char* pBuf, unsigned char buf_size, unsigned char *pBytes_actually_read, void *pCallback_data) 8 | { 9 | unsigned int ra; 10 | // uint n; 11 | // pCallback_data; 12 | 13 | // n = min(g_nInFileSize - g_nInFileOfs, buf_size); 14 | //if (n && (fread(pBuf, 1, n, g_pInFile) != n)) 15 | //return PJPG_STREAM_READ_ERROR; 16 | //*pBytes_actually_read = (unsigned char)(n); 17 | //g_nInFileOfs += n; 18 | 19 | //memcpy(pBuf,&jpegdata[doff],buf_size); 20 | for(ra=0;ra 47 | 48 | int main(void) 49 | { 50 | 51 | int c, i = 0; 52 | 53 | printf("#ifdef HAVE_CONFIG_H\n"); 54 | printf("# include \"config.h\"\n"); 55 | printf("#endif\n\n"); 56 | printf("#ifdef EMBED\n"); 57 | 58 | printf("unsigned char flash_data[] = {\n"); 59 | 60 | while((c = getchar()) != EOF) { 61 | printf("0x%.2x, ", c); 62 | if(!(i % 32)) 63 | printf("\n"); 64 | i++; 65 | } 66 | 67 | printf(" };\n"); 68 | printf("#endif\n"); 69 | return(0); 70 | } 71 | -------------------------------------------------------------------------------- /triggerSoftware/Makefile: -------------------------------------------------------------------------------- 1 | UTILS = ../hardware/software/utils 2 | GCC = or1k-elf 3 | BOARD = ml509SRAM 4 | 5 | all: idle math_user 6 | 7 | idle: idle.c Makefile 8 | $(GCC)-gcc -Wall -mboard=$(BOARD) -Os -mhard-div -mhard-mul -o idle.or32 idle.c -Wl,--wrap,__uart_init 9 | $(GCC)-objdump -d idle.or32 > idle.s 10 | $(GCC)-objcopy -O binary idle.or32 idle.bin 11 | $(UTILS)/bin2vmem idle.bin > idle.vmem 12 | rm -f idle.bin 13 | 14 | math_user: math_user.c Makefile 15 | $(GCC)-gcc -Wall -mboard=$(BOARD) -Os -mhard-div -mhard-mul -o math_user.or32 math_user.c -Wl,--wrap,__uart_init 16 | $(GCC)-objdump -d math_user.or32 > math_user.s 17 | $(GCC)-objcopy -O binary math_user.or32 math_user.bin 18 | $(UTILS)/bin2vmem math_user.bin > math_user.vmem 19 | rm -f math_user.bin 20 | 21 | clean: 22 | rm -f *.or32 23 | rm -f *.s 24 | rm -f *.vmem 25 | rm -f *~ 26 | -------------------------------------------------------------------------------- /triggerSoftware/README.md: -------------------------------------------------------------------------------- 1 | ## Trigger Program 2 | 3 | We implement several triggers as a part of A2. To select which trigger 4 | you want to use, go to `math_user.c` and comment/uncomment the 5 | appropriate lines in `main()`. There are two versions of most trigger 6 | code sequences: inline assembly and pure C. 7 | 8 | ## Idle Program 9 | 10 | Just a simple empty loop to show the background toggle rate of the 11 | processor's wires. 12 | 13 | ## Building 14 | 15 | `make all` builds both idle and trigger binaries 16 | `make idle` builds the idle binary 17 | `make math_user` builds the trigger binary 18 | `make clean` removes all files that building produces 19 | 20 | # Creating a Toggle Video 21 | 22 | Requires: You will need to simulate the processor and pass the 23 | resulting VCD file to a program that divides the simulation time into 24 | bins and reports the toggle rate for each wire in the VCD for each 25 | time bin. Fortunately, I wrote an example program that does this as 26 | part of my VCD processing library: 27 | [Process VCD](https://github.com/impedimentToProgress/ProcessVCD). 28 | 29 | To create a histogram for a single bin, see `histogram.gp` in this repo. 30 | 31 | To create a video for all bins, run `makeHists.sh` in this repo. 32 | -------------------------------------------------------------------------------- /triggerSoftware/commonFuncs.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include "spr_defs.h" 3 | 4 | #define setSPR(spr, data) asm volatile( \ 5 | "l.mtspr r0, %0, %1 \n\t" \ 6 | : \ 7 | : "r"(data), "i"(spr) \ 8 | ); 9 | 10 | #define getSPR(spr) ({ \ 11 | uint32_t x; \ 12 | asm volatile( \ 13 | "l.mfspr %0, r0, %1 \n\t" \ 14 | : "=r" (x) \ 15 | : "i" (spr) \ 16 | ); \ 17 | x; \ 18 | }) 19 | 20 | #define setFabricConfigAddress(val) setSPR(SP_FABRIC_ADDRESS, val) 21 | #define setFabricConfigData(val) setSPR(SP_FABRIC_DATA, val) 22 | #define strobeFabricConfig() setSPR(SP_FABRIC_STROBE, 1); setSPR(SP_FABRIC_STROBE, 0) 23 | #define enableFabric() setFabricConfigAddress(0); setFabricConfigData(1); strobeFabricConfig() 24 | #define disableFabric() setFabricConfigAddress(0); setFabricConfigData(0); strobeFabricConfig() 25 | 26 | #define getExceptions() getSPR(SP_EXCEPTION_COUNT) 27 | #define getAssertionViolations() getSPR(SP_ASSERTION_VIOLATIONS) 28 | #define getAttackEnables() getSPR(SP_ATTACK_ENABLES) 29 | #define setAttackEnables(val) setSPR(SP_ATTACK_ENABLES, (val)) 30 | -------------------------------------------------------------------------------- /triggerSoftware/histogram.gp: -------------------------------------------------------------------------------- 1 | set terminal png enhanced 20; 2 | set size 1.0,1.0; 3 | set output 'histogram.png'; 4 | set grid xtics ytics; 5 | set xlabel 'Toggle Rate'; 6 | set ylabel "Proportion of Wires"; 7 | unset key; 8 | set yrange [0.0:0.03] 9 | set xrange [0:0.25] 10 | 11 | set arrow from .17,0 to .17,.03 nohead lt 0 lw 5 lc rgb "red" 12 | #set arrow from .12,0 to .12,.03 nohead lt 0 lw 5 lc rgb "red" 13 | 14 | plot 'histogram.txt' using 3:4 with boxes lc rgb "grey" linetype 1 linewidth 4 title 'Base' ,\ 15 | 'div.txt' using 3:4 with boxes lc rgb "red" linetype 1 linewidth 4 title 'Base' ; 16 | -------------------------------------------------------------------------------- /triggerSoftware/idle.c: -------------------------------------------------------------------------------- 1 | #include "spr_defs.h" 2 | #include "commonFuncs.h" 3 | 4 | // No UART on the fabricated chip, only in simulation 5 | void __wrap___uart_init() 6 | { 7 | ; 8 | } 9 | 10 | 11 | int main(void) 12 | { 13 | // Go to user mode, with exceptions enabled 14 | // Toggle SR[1] 15 | unsigned int sr = getSPR(SPR_SR); 16 | sr = (sr | 0x4 | 0x2) & 0xfffffffe; 17 | setSPR(SPR_SR, sr) 18 | 19 | while(1) 20 | ; 21 | 22 | return 0; 23 | } 24 | -------------------------------------------------------------------------------- /triggerSoftware/makeHists.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Convert a bunch of histograms into a bunch of png images 4 | for i in {1..450}; do cp hist_"$i".txt histogram.txt; gnuplot histogram.gp; mv histogram.png hist_"$i".png; done; 5 | 6 | # Combine the png images into a video 7 | 8 | # Version that is small and good quality 9 | ffmpeg -v quiet -i hist_%d.png -c:v libx264 -preset medium -qp 0 -r 30 -y histogram.mkv 10 | 11 | # Version that work well enough in PowerPoint 12 | ffmpeg -v quiet -i hist_%d.png -f lavfi -i aevalsrc=0 -shortest -c:v mpeg1video -qscale:v 2 -c:a libmp3lame -r 30 -y histogram.mpg 13 | 14 | # Remove temporary files 15 | for i in {1..450}; do rm hist_"$i".png; done; 16 | rm histogram.txt 17 | --------------------------------------------------------------------------------