├── .DS_Store ├── .gitignore ├── CODEOWNERS ├── CODEOWNERS~ ├── README.md └── main ├── .DS_Store ├── Devcloud_Access_Instructions ├── LoginScript │ ├── README.md │ └── devcloudLoginToolSetup.sh ├── LoginScriptGif.gif └── README.md ├── FAQ └── README.md ├── FPGA_devcloud_sitemap └── sitemap.MD ├── GitHub_Usage ├── Developer_GitHub_Devcloud_Instructions.md └── User_GitHub_Devcloud_Instructions.md ├── HandsFree ├── .DS_Store ├── Devkits │ ├── .DS_Store │ ├── DE1-SoC │ │ ├── Example Projects │ │ │ └── BlankProject │ │ │ │ └── blankProj.qar │ │ └── RemoteConsoleDE1SoC │ │ │ ├── launch.tcl │ │ │ ├── setup.tcl │ │ │ ├── setup_temp.tcl │ │ │ ├── source │ │ │ ├── console.tcl │ │ │ ├── console_procs.tcl │ │ │ ├── gui_board.tcl │ │ │ ├── gui_board_procs.tcl │ │ │ ├── gui_server.tcl │ │ │ ├── gui_server_procs.tcl │ │ │ ├── main.tcl │ │ │ └── main_procs.tcl │ │ │ └── widgets │ │ │ ├── A.png │ │ │ ├── B.png │ │ │ ├── Board_Layout.png │ │ │ ├── Board_Slide.png │ │ │ ├── Board_Slide.pptx │ │ │ ├── C.png │ │ │ ├── D.png │ │ │ ├── DE1SoC.png │ │ │ ├── E.png │ │ │ ├── F.png │ │ │ ├── G.png │ │ │ ├── H.png │ │ │ ├── LEDG.png │ │ │ ├── LEDR.png │ │ │ ├── Layout.png │ │ │ ├── PB.png │ │ │ └── SW.png │ ├── DE10-Lite │ │ ├── .DS_Store │ │ ├── Example_Projects │ │ │ ├── BlankProject │ │ │ │ ├── BlankProject.qar │ │ │ │ └── README.md │ │ │ ├── BlankProjectKitIO │ │ │ │ └── blankProject.qar │ │ │ ├── Calculator │ │ │ │ ├── Calculator.qar │ │ │ │ ├── Calculator_RemoteLab.pdf │ │ │ │ └── README.md │ │ │ ├── Intro_to_Quartus │ │ │ │ ├── BlankProject.qar │ │ │ │ ├── In_System_Memory_Content_Editor.pdf │ │ │ │ ├── IntroLab_RemoteBoard_Manual.pdf │ │ │ │ ├── Intro_Lecture_Slides_Remote.pdf │ │ │ │ ├── knight_rider.v │ │ │ │ ├── mux_2_to_1.v │ │ │ │ └── switch_to_led.v │ │ │ ├── KnightRider7Segment │ │ │ │ ├── KnightRider7segment.qar │ │ │ │ └── README.md │ │ │ ├── KnightRiderKitIO │ │ │ │ ├── KnightRiderKitIO.qar │ │ │ │ └── KnightRiderKitIO.qarlog │ │ │ ├── LogicSolver │ │ │ │ ├── Digital_Trainer_HandsFree_Edition.docx │ │ │ │ ├── LogicSolverHandsFree.qar │ │ │ │ └── README.md │ │ │ ├── OR2x1 │ │ │ │ ├── OR2x1.qar │ │ │ │ └── README.md │ │ │ ├── Parity10b │ │ │ │ ├── Parity10b.qar │ │ │ │ └── README.md │ │ │ └── VHDL_counter │ │ │ │ └── counter_VHDL.qar │ │ ├── RemoteConsoleDE10Lite.zip │ │ ├── RemoteConsoleDE10Lite │ │ │ ├── .DS_Store │ │ │ ├── launch.tcl │ │ │ ├── setup.tcl │ │ │ ├── source │ │ │ │ ├── console.tcl │ │ │ │ ├── console_procs.tcl │ │ │ │ ├── gui_board.tcl │ │ │ │ ├── gui_board_procs.tcl │ │ │ │ ├── gui_server.tcl │ │ │ │ ├── gui_server_procs.tcl │ │ │ │ ├── main.tcl │ │ │ │ └── main_procs.tcl │ │ │ └── widgets │ │ │ │ ├── DE10Lite.png │ │ │ │ ├── SWs.png │ │ │ │ ├── a.png │ │ │ │ ├── b.png │ │ │ │ ├── c.png │ │ │ │ ├── circle.png │ │ │ │ ├── d.png │ │ │ │ ├── e.png │ │ │ │ ├── f.png │ │ │ │ ├── g.png │ │ │ │ ├── h.png │ │ │ │ └── led.png │ │ ├── RemoteConsoleDE10LiteKitIO.zip │ │ └── RemoteConsoleDE10LiteKitIO │ │ │ ├── launch.tcl │ │ │ ├── run_GUI.bat │ │ │ ├── setup.tcl │ │ │ ├── source │ │ │ ├── console.tcl │ │ │ ├── console_procs.tcl │ │ │ ├── gui_board.tcl │ │ │ ├── gui_board_procs.tcl │ │ │ ├── gui_server.tcl │ │ │ ├── gui_server_procs.tcl │ │ │ ├── main.tcl │ │ │ └── main_procs.tcl │ │ │ └── widgets │ │ │ ├── DE10Lite.png │ │ │ ├── SWs.png │ │ │ ├── a.png │ │ │ ├── b.png │ │ │ ├── c.png │ │ │ ├── circle.png │ │ │ ├── d.png │ │ │ ├── e.png │ │ │ ├── f.png │ │ │ ├── g.png │ │ │ ├── h.png │ │ │ └── led.png │ └── DE2-115 │ │ ├── Example_Projects │ │ ├── BlankProject │ │ │ └── BlankProject_DE2115.qar │ │ ├── KnightRider_DE2-115 │ │ │ └── KnightRider_DE2-115.qar │ │ ├── Multiplier_VHDL │ │ │ └── DE2_115_Multiplier_VHDL.qar │ │ ├── OR2x1 │ │ │ └── OR2x1_DE2115.qar │ │ └── Parity10b │ │ │ └── Parity10b_DE2115.qar │ │ └── RemoteConsoleDE2115.zip ├── README.md ├── Remote_Console_Guide │ ├── .DS_Store │ ├── BlankProject1.PNG │ ├── DE2115_HEADER.PNG │ ├── Example_Kit_Connection.PNG │ ├── IT_Diagram.png │ ├── Login_Page.PNG │ ├── Make_Task1.PNG │ ├── Make_Task2.PNG │ └── Module_Hierarchy.png ├── Simulator │ └── DESim │ │ └── Readme.md ├── jtag_server_setup.sh └── run_GUI.bat ├── Overview └── FCCM_2020_FPGA_Cloud_Services.pdf ├── ProfessorResources └── FPGA_Professor_Resources_July_2021.pdf ├── QuickStartGuides ├── EmbeddedNios_DE_board_Quickstart │ ├── CustomComponents │ │ ├── DE_hello_world_PWM.c │ │ ├── PWM_generator.v │ │ └── reg32_avalon_interface.v │ ├── EmbeddedNios_DE_board_Quickstart.pdf │ └── NiosDevcloud.zip ├── Externally_Hosted_Training │ ├── UF_Dr_Greg_Stitt │ │ └── README.md │ └── uMass_Lowell_Dr_Yan_Luo │ │ └── README.md ├── HLS_Lab │ ├── HighLevelDesign-HLS-Lecture_Slides.pptx │ └── hls_lab_manual_source_files.zip ├── OneAPI_Program_PAC_Quickstart │ ├── Arria 10 │ │ ├── A10_oneapi_batch.sh │ │ ├── README.md │ │ └── download-file-list.txt │ └── Stratix 10 │ │ ├── README.md │ │ ├── S10_oneapi_batch.sh │ │ └── download-file-list.txt ├── OpenCL_Program_PAC_Quickstart │ ├── Arria 10 │ │ ├── A10_v1.2.1_opencl_batch.sh │ │ ├── A10_v1.2_opencl_batch.sh │ │ ├── README.md │ │ └── debug.log │ └── Stratix 10 │ │ ├── README.md │ │ └── S10_opencl_batch.sh ├── RTL_AFU_Program_PAC_Quickstart │ ├── Arria10 │ │ ├── A10_v1.2.1_rtl_batch.sh │ │ ├── A10_v1.2_rtl_batch.sh │ │ └── README.md │ └── Stratix10 │ │ ├── README.md │ │ └── S10_rtl_batch.sh ├── RTL_DE_board_Quickstart │ ├── README.md │ ├── RTL_Quickstart_source_files.zip │ └── RTL__DE_board_Quickstart.pdf ├── T2S │ ├── Disclaimer.txt │ ├── README.md │ └── tutorials │ │ └── fpga │ │ ├── 2d-convolution │ │ ├── README.md │ │ ├── basic │ │ │ ├── figures │ │ │ │ └── formula.png │ │ │ ├── main.cpp │ │ │ └── run.sh │ │ ├── io │ │ │ ├── main.cpp │ │ │ └── run.sh │ │ ├── new-basic │ │ │ ├── figures │ │ │ │ ├── dataflow.png │ │ │ │ ├── formula.png │ │ │ │ └── systolic-array.png │ │ │ ├── main.cpp │ │ │ └── run.sh │ │ ├── stt │ │ │ ├── figures │ │ │ │ ├── conv.gif │ │ │ │ └── tiling.pptx │ │ │ ├── main.cpp │ │ │ └── run.sh │ │ ├── tiling-vec │ │ │ ├── main.cpp │ │ │ └── run.sh │ │ └── util.h │ │ ├── capsule │ │ ├── README.md │ │ ├── basic │ │ │ ├── figures │ │ │ │ ├── capsule-formula.png │ │ │ │ ├── capsule-full-formula.png │ │ │ │ ├── conv-formula.png │ │ │ │ ├── dataflow.gif │ │ │ │ └── report.png │ │ │ └── main.cpp │ │ ├── buffer │ │ │ ├── figures │ │ │ │ └── profile.png │ │ │ └── main.cpp │ │ ├── ionet │ │ │ ├── figures │ │ │ │ ├── ionet.png │ │ │ │ ├── profile-code.png │ │ │ │ └── profile-time.png │ │ │ └── main.cpp │ │ ├── reorder │ │ │ ├── figures │ │ │ │ ├── profile-code.png │ │ │ │ ├── profile-time.png │ │ │ │ ├── report.png │ │ │ │ └── synthesis.png │ │ │ └── main.cpp │ │ ├── scaleup │ │ │ ├── figures │ │ │ │ ├── profile-code.png │ │ │ │ └── profile-time.png │ │ │ └── main.cpp │ │ └── vectorize │ │ │ ├── figures │ │ │ └── profile.png │ │ │ └── main.cpp │ │ ├── lu │ │ ├── README.md │ │ ├── basic │ │ │ ├── figures │ │ │ │ ├── lu-array.png │ │ │ │ ├── lu-cal-L.png │ │ │ │ ├── lu-demo.gif │ │ │ │ ├── lu-example.png │ │ │ │ ├── lu-formula.png │ │ │ │ ├── lu-row-op.png │ │ │ │ └── lu.pptx │ │ │ ├── main.cpp │ │ │ ├── profile │ │ │ │ ├── lu-basic-exec.png │ │ │ │ ├── lu-basic-freq.png │ │ │ │ └── lu-basic-profile.png │ │ │ ├── report │ │ │ │ ├── lu-basic-II.png │ │ │ │ ├── lu-basic-details.png │ │ │ │ └── lu-basic-store-dep.png │ │ │ └── run.sh │ │ ├── batch │ │ │ ├── main.cpp │ │ │ ├── profile │ │ │ │ ├── Ostall0.png │ │ │ │ ├── Ostall1.png │ │ │ │ ├── exec-time.png │ │ │ │ └── loader.png │ │ │ └── run.sh │ │ ├── host.cpp │ │ ├── io │ │ │ ├── figures │ │ │ │ └── lu-io.png │ │ │ ├── main.cpp │ │ │ ├── profile │ │ │ │ ├── exec-time.png │ │ │ │ └── stall.png │ │ │ ├── report │ │ │ │ └── lu-io-II.png │ │ │ └── run.sh │ │ └── vectorize │ │ │ ├── main.cpp │ │ │ ├── profile │ │ │ ├── Ostall.png │ │ │ ├── bandwidth.png │ │ │ └── exec-time.png │ │ │ └── run.sh │ │ ├── matrix-multiply │ │ ├── README.md │ │ ├── basic │ │ │ ├── figures │ │ │ │ ├── cik=aikbkj.png │ │ │ │ ├── matrix-multiply-UREs.png │ │ │ │ ├── matrix-multiply-dataflow.png │ │ │ │ ├── matrix-multiply-dataflow.pptx │ │ │ │ ├── matrix-multiply-spec-part1.png │ │ │ │ └── matrix-multiply-spec-part2.png │ │ │ └── main.cpp │ │ ├── control-signals │ │ │ └── main.cpp │ │ ├── final │ │ │ └── figures │ │ │ │ ├── matrix-multiply-final-design-animation.gif │ │ │ │ └── matrix-multiply-final-design-animation.pptx │ │ ├── host-files │ │ │ ├── README.md │ │ │ ├── host-opt-output.cpp │ │ │ └── host.cpp │ │ ├── isolate │ │ │ ├── figures │ │ │ │ ├── isolate-all-8-8-16-32-32-32-8-8-8-dynamic-profile-part1.png │ │ │ │ ├── isolate-all-8-8-16-32-32-32-8-8-8-dynamic-profile-part3.png │ │ │ │ ├── isolate-all-8-8-16-32-32-32-8-8-8-dynamic-profile-part4.png │ │ │ │ ├── isolate-all-8-8-16-32-32-32-8-8-8-execution-time.png │ │ │ │ ├── isolate-all-dynamic-profile-part1.png │ │ │ │ ├── isolate-all-dynamic-profile-part2.png │ │ │ │ ├── isolate-all-fmax-II.png │ │ │ │ ├── isolate-drainer-array-and-drainer-code.png │ │ │ │ ├── isolate-drainer-deserializer-fmax-II.png │ │ │ │ ├── isolate-drainer-drainer-code.png │ │ │ │ ├── isolate-drainer-fmax-II.png │ │ │ │ ├── isolate-drainer-loop-analysis.png │ │ │ │ ├── isolate-drainer-systolic-array-fmax-II.png │ │ │ │ └── isolate.pptx │ │ │ ├── isolate-drainer-deserializer.cpp │ │ │ ├── isolate-drainer.cpp │ │ │ └── isolate-full-IO.cpp │ │ ├── opt-input │ │ │ ├── figures │ │ │ │ ├── buffer-scatter.pptx │ │ │ │ ├── buffer.gif │ │ │ │ ├── dynamic-profiler-part1.png │ │ │ │ ├── dynamic-profiler-part2.png │ │ │ │ ├── dynamic-profiler-part3.png │ │ │ │ ├── dynamic-profiler-part4.png │ │ │ │ ├── exec-time.png │ │ │ │ ├── freq.png │ │ │ │ └── spec.png │ │ │ └── main.cpp │ │ ├── opt-output │ │ │ ├── figures │ │ │ │ ├── collector-stalls.png │ │ │ │ └── drainer-stalls.png │ │ │ └── main.cpp │ │ ├── reorder │ │ │ ├── figures │ │ │ │ ├── code.png │ │ │ │ ├── fmax-II-report.png │ │ │ │ ├── issue.png │ │ │ │ ├── loop-analysis-mem-dependence.png │ │ │ │ ├── reorder.png │ │ │ │ └── reorder.pptx │ │ │ └── main.cpp │ │ ├── run.sh │ │ ├── sizes.h │ │ ├── stt-vectorize │ │ │ ├── figures │ │ │ │ ├── code.png │ │ │ │ ├── fmax-II-report.png │ │ │ │ ├── loop-analysis-BB10.png │ │ │ │ └── stt-vectorize.pptx │ │ │ └── main.cpp │ │ └── tiling │ │ │ ├── figures │ │ │ ├── issues.png │ │ │ ├── tiling-spec-part1.png │ │ │ ├── tiling-spec-part2.png │ │ │ ├── tiling.gif │ │ │ └── tiling.pptx │ │ │ └── main.cpp │ │ └── pairhmm │ │ ├── README.md │ │ ├── buffer │ │ ├── figures │ │ │ └── profile.png │ │ └── main.cpp │ │ ├── ionet │ │ ├── figures │ │ │ ├── ionet.png │ │ │ └── profile-code.png │ │ └── main.cpp │ │ ├── preprocess │ │ ├── figures │ │ │ └── profile.png │ │ └── main.cpp │ │ ├── reorder │ │ ├── figures │ │ │ ├── profile.png │ │ │ └── report.png │ │ └── main.cpp │ │ ├── scaleup │ │ ├── figures │ │ │ ├── profile-1.png │ │ │ ├── profile.png │ │ │ └── synthesis.png │ │ └── main.cpp │ │ └── tiling │ │ ├── figures │ │ ├── dataflow.gif │ │ ├── report.png │ │ └── tiled.png │ │ └── main.cpp ├── TestYourKnowledge │ ├── TestYourKnowledge_Calculator │ │ ├── TestYourKnowledge_Calculator.docx │ │ ├── TestYourKnowledge_Calculator.pdf │ │ └── addit.qar │ ├── TestYourKnowledge_KnightRiderOnSteroids │ │ └── KROS_description.docx │ ├── TestYourKnowledge_KnightRiderROM │ │ ├── TestYourKnowledge_KnightRiderROM.docx │ │ ├── TestYourKnowledge_KnightRiderROM.pdf │ │ └── knight_rider.qar │ ├── TestYourKnowledge_KnightRiderRotaryEncoder │ │ ├── Archive │ │ │ ├── TestYourKnowledge_KnightRiderRotaryEncoder.pdf │ │ │ ├── rotary_encoder_project.qar │ │ │ └── rotary_encoder_project_solution.qar │ │ ├── KnightRider_RotaryEncoder.zip │ │ ├── TestYourKnowledge_RotaryEncoder.docx │ │ ├── TestYourKnowledge_RotaryEncoder.pdf │ │ └── rotary_encoder_project.qarlog │ └── TestYourKnowledge_PWM │ │ ├── PlatformDesignerCustomComponentPWM.docx │ │ └── PlatformDesignerCustomComponentPWM.pdf ├── Workshop_Devcloud_Access │ ├── Devcloud_Overview_Lab_Manual.pdf │ └── Intel_FPGA_Cloud_Services.pdf ├── Workshop_Embedded_Nios_DE10_Lite │ ├── DE10_Lite_qsys_workshop.zip │ ├── Embedded-Lecture_Slides.pdf │ └── embedded_nios.pdf ├── Workshop_Embedded_Nios_HOL │ ├── EmbeddedNiosHOL.zip │ ├── Embedded_Lecture_Slides_HOL.pdf │ └── Embedded_Nios_Design_HOL_Lab_Manual.docx ├── Workshop_FlexKR_DE10_Lite │ ├── FlexKR.qar │ └── FlexKR_Lab_Manual.pdf ├── Workshop_Intro_DE0_CycloneIII │ ├── Intro_Lecture_Slides_DE0_CycloneIII.pdf │ ├── Intro_to_FPGA_DE0_CycloneIII.pdf │ ├── de0_pins.tcl │ ├── knight_rider.v │ ├── mux_2_to_1.v │ └── switch_to_led.v ├── Workshop_Intro_DE10_Lite │ ├── DE10_Lite_files.zip │ ├── Design Files │ │ ├── .knight_rider.v.swp │ │ ├── DE0_CV_pins.tcl │ │ ├── DE10_Lite_pins.tcl │ │ ├── DE10_Lite_pins.zip │ │ ├── knight_rider.v │ │ ├── mux_2_to_1.v │ │ ├── mux_snippet_case.v │ │ ├── mux_snippet_continuous.v │ │ ├── mux_snippet_if.v │ │ └── switch_to_led.v │ └── Intro_to_FPGA.pdf ├── Workshop_Intro_DE1_SoC_Labsland │ ├── DE1_SOC_pins.tcl │ ├── IntroLab_RemoteBoard_Labsland.pdf │ ├── Intro_Lecture_Slides_Labsland.pdf │ ├── knight_rider.v │ ├── mux_2_to_1.v │ └── switch_to_led.v ├── Workshop_Intro_Remote │ ├── IntroLab_RemoteBoard.pdf │ ├── Intro_Lecture_Slides_Remote.pdf │ ├── knight_rider.v │ ├── mux_2_to_1.v │ └── switch_to_led.v ├── Workshop_Simulation_Debug_DE10_Lite │ ├── DE10LITE_Workshop_DebuggingTools.zip │ ├── Simulation-Lab_Manual.pdf │ └── Simulation-Lecture_Slides.pptx ├── Workshop_Simulation_Debug_Remote │ ├── Lab_1 │ │ ├── Simulation_Example.qar │ │ ├── tb_counter.v │ │ └── tb_counter.v~ │ ├── Lab_2 │ │ ├── Example_ISSP_SignalTap_CVGXStarter.qar │ │ └── Example_ISSP_SignalTap_DE1SoC.qar │ ├── Simulation-Lab_3101_Manual.pdf │ ├── Simulation-Lecture_Slides.pdf │ └── Solution │ │ ├── Example_ISSP_SignalTap_solution.v │ │ ├── Example_ISSP_SignalTap_solution.v~ │ │ └── tb_counter_solution.v ├── Workshop_System_Verilog │ ├── Labs-Part2.zip │ ├── SystemVerilog HDVL_Lab_Manual.docx │ ├── SystemVerilog HDVL_Lab_Manual_2.docx │ ├── System_Verilog_Training_Part_1.pptx │ ├── System_Verilog_Training_Part_2.pptx │ └── labs.zip ├── Workshop_System_Verilog_Assertions │ ├── SV_assertions.zip │ ├── SystemVerilog_HDVL_Lab_Assertions.docx │ └── System_Verilog_Assertions.pptx └── Workshop_System_Verilog_Code_Coverage │ ├── SV_assertions.zip │ ├── SystemVerilog_HDVL_Lab_Assertions_Code_Coverage.docx │ └── System_Verilog_Coverage.pptx └── figures ├── 100_succesful.png ├── A10_OpenCL_devcloud_login_menu ├── JTAG_password.png ├── add_server_JTAG.png ├── authentication_ssh.png ├── basic_ssh_settings.png ├── browse_driver_software.png ├── browse_for_sshkey.png ├── configure_JTAG.png ├── connection.png ├── convert-to-private-key.png ├── devcloud_information.png ├── devcloud_to_local_board.png ├── device_manager.png ├── download_programmer.png ├── download_programmer_intel.png ├── extra_tab.png ├── figuresLink.txt ├── graphics_usage.png ├── hardware_setup.png ├── host_key_verification_terminate.png ├── host_key_verification_update.png ├── launching_x2go.png ├── list_of_jtag_servers.png ├── localhost_user_session.png ├── lspci_grep.png ├── mobaxterm_edition.png ├── mobaxterm_filemanagment.png ├── mobaxterm_new_session.png ├── mobaxterm_ssh.png ├── mobaxterm_terminal.png ├── mobaxterm_window.png ├── open_terminal.png ├── packages_icon.png ├── preparation.png ├── programmer.png ├── putty_private_key_files.png ├── quartus_fontsize.png ├── quartus_options.png ├── run_admin.png ├── socat.png ├── ssh_key_access.png ├── step1.png ├── step2.png ├── transferring_files.png ├── type-in-localhost-information.png ├── winscp_advanced.png ├── winscp_download.png ├── winscp_open_window.png ├── x2go_change_font.png ├── x2go_desktop.png ├── x2go_fontsize.png ├── x2go_launch_puffy.png ├── x2go_loading.png ├── x2go_session_preferences.png ├── x2go_session_size.png └── x2go_terminal_window.png /.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/.DS_Store -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | *.un~ 3 | *.sh~ 4 | main/QuickStartGuides/OpenCL_Program_PAC_QuickStart/Arria10/README.md 5 | -------------------------------------------------------------------------------- /CODEOWNERS: -------------------------------------------------------------------------------- 1 | /main/QuickStartGuides/T2S @ronghongbo 2 | -------------------------------------------------------------------------------- /CODEOWNERS~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/CODEOWNERS~ -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # DISCONTINUATION OF PROJECT # 2 | This project will no longer be maintained by Intel. 3 | Intel has ceased development and contributions including, but not limited to, maintenance, bug fixes, new releases, or updates, to this project. 4 | Intel no longer accepts patches to this project. 5 | If you have an ongoing need to use this project, are interested in independently developing it, or would like to maintain patches for the open source software community, please create your own fork of this project. 6 | 7 | intel-fpga-devcloud 8 | 9 |
10 | FPGA DESIGN DEVELOPMENT AND WORKLOADS FOR HARDWARE ACCELERATION 11 |
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13 | Develop programmable solutions and validate your workloads on leading FPGA hardware with tools optimized for Intel technology. Use this cloud solution in the classroom to support acceleration engineering curriculum. 14 |
15 | 16 |
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18 | 19 | Website 20 | 21 | | 22 | 23 | Devcloud Access Instructions 24 | 25 | | 26 | 27 | Quickstart Guides 28 | 29 | | 30 | 31 | 32 | 33 | 34 | 35 | FAQ 36 | 37 | | 38 | 39 | Contact Us 40 | 41 |

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43 | 44 | ------ 45 | 46 |
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Welcome to the Intel FPGA Devcloud GitHub! 48 | 49 |

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51 | 52 | For instructions on how to connect to the Devcloud, click on **[Devcloud Access Instructions](https://github.com/intel/FPGA-Devcloud/tree/master/main/Devcloud_Access_Instructions#devcloud-access-instructions)**. 53 | 54 | For access to quick, hands-on guides that will get you started on key features of Intel FPGA Devcloud technology, click on [**Quickstart Guides**](https://github.com/intel/FPGA-Devcloud/tree/master/main/QuickStartGuides#Contents). 55 | 56 | For answers to commonly asked questions, click [**FAQ**](https://github.com/intel/FPGA-Devcloud/tree/master/main/FAQ#faq). 57 | 58 | ------ 59 | -------------------------------------------------------------------------------- /main/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/.DS_Store -------------------------------------------------------------------------------- /main/Devcloud_Access_Instructions/LoginScript/README.md: -------------------------------------------------------------------------------- 1 | #### Login Script 2 | 3 | ---- 4 | 5 |                     Refer to the [**Devcloud Access Instructions**](https://github.com/intel/FPGA-Devcloud/tree/feature/main/Devcloud_Access_Instructions#52-login-script) for more information on the Login Script. -------------------------------------------------------------------------------- /main/Devcloud_Access_Instructions/LoginScriptGif.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/Devcloud_Access_Instructions/LoginScriptGif.gif -------------------------------------------------------------------------------- /main/FAQ/README.md: -------------------------------------------------------------------------------- 1 | intel-fpga-devcloud 2 | 3 |
4 | FPGA DESIGN DEVELOPMENT AND WORKLOADS FOR HARDWARE ACCELERATION 5 |
6 |
7 | Develop programmable solutions and validate your workloads on leading FPGA hardware with tools optimized for Intel technology. Use this cloud solution in the classroom to support acceleration engineering curriculum. 8 |
9 | 10 |
11 |

12 | 13 | Website 14 | 15 | | 16 | 17 | Devcloud Access Instructions 18 | 19 | | 20 | 21 | Quickstart Guides 22 | 23 | | 24 | 25 | 26 | 27 | 28 | 29 | FAQ 30 | 31 | | 32 | 33 | Contact Us 34 | 35 |

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37 | 38 | i -------------------------------------------------------------------------------- /main/HandsFree/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/.DS_Store -------------------------------------------------------------------------------- /main/HandsFree/Devkits/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/.DS_Store -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE1-SoC/Example Projects/BlankProject/blankProj.qar: -------------------------------------------------------------------------------- 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to be adapted for Linux 15 | } 16 | variable launch_location [file normalize [info script]] 17 | open "|$env(QUARTUS_ROOTDIR)bin64/quartus_sh --script ${launch_location}/../source/main.tcl" -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE1-SoC/RemoteConsoleDE1SoC/source/gui_server.tcl: -------------------------------------------------------------------------------- 1 | ##### Figure out path to this script's location 2 | variable gui_server_location [file normalize [info script]] 3 | 4 | ##### Flush pipe after any stdout puts command 5 | fconfigure stdout -buffering line 6 | 7 | ##### Do not block pipe when using gets command 8 | fconfigure stdin -blocking 0 9 | 10 | ##### Get global variables 11 | source "${gui_server_location}/../../setup.tcl" 12 | 13 | ##### Get GUI procedures 14 | source "${gui_server_location}/../gui_server_procs.tcl" 15 | 16 | ##### Initialize the board connect window 17 | init_top_window "Board Connect" 18 | 19 | ##### Initialize the board connect parameters 20 | lassign [initial_credentials] ips credential_fh ip_address password sof_file mode pws 21 | 22 | set password_old $password 23 | set ip_address_old $ip_address 24 | 25 | ##### Add widgets and place into a widget grid 26 | grid [label .ip_lab -text "IPv4" -background white -font {Courier -17} ] -padx 10 -pady 6 -column 1 -row 1 -columnspan 1 -sticky "snew" 27 | grid [ ttk::combobox .ip_address -textvariable ip_address -values $ips -background white \ 28 | -font {Courier -17 } -foreground black -justify left -state normal -width 15] -padx 10 -pady 6 -column 2 -row 1 -columnspan 2 -sticky "snew" 29 | grid [label .pw_lab -text "Password" -background white -font {Courier -17} -justify right] -padx 10 -pady 6 -column 1 -row 2 -columnspan 1 -sticky "snew" 30 | grid [entry .pw_ent -background white -foreground black -relief ridge -width 17 \ 31 | -font {Courier -17} -textvariable password -justify left -state normal -state normal ] -padx 10 -pady 6 -column 2 -row 2 -columnspan 2 -sticky "snew" 32 | grid [label .sof_lab -text "SOF File" -background white -font {Courier -17} ] -padx 10 -pady 6 -column 1 -row 3 -columnspan 1 -sticky "snew" 33 | grid [entry .sof_ent -background white -foreground black -relief ridge -width 17 \ 34 | -font {Courier -17} -textvariable sof_file -justify left -state disabled ] -padx 10 -pady 6 -column 2 -row 3 -columnspan 2 -sticky "snew" 35 | # grid [ ttk::combobox .sof_entry -textvariable sof_file -values "" -background white \ 36 | -font {Courier -17 } -foreground black -justify left -state disabled -width 15] -padx 10 -pady 6 -column 2 -row 3 -columnspan 2 -sticky "snew" 37 | grid [button .link_button -text "Link" -height 1 -width 12 \ 38 | -command {set mode [link_press $ips $credential_fh $ip_address $password $sof_file $pws] } -state disabled ] -padx 10 -pady 6 -column 3 -row 5 -columnspan 1 39 | grid [button .rm_ips_button -text "Clear IPv4s" -height 1 -width 12 \ 40 | -command {lassign [remove_ips] ips credential_fh ip_address password sof_file mode pws; .ip_address configure -values $ips} -state normal ] -padx 10 -pady 6 -column 1 -row 5 -columnspan 1 41 | grid [button .sof_select_button -text "Select .sof" -height 1 -width 12 \ 42 | -command {set sof_file [tk_getOpenFile]; .sof_ent xview moveto 1.0; .sof_ent icursor end} -state normal ] -padx 10 -pady 6 -column 2 -row 5 -columnspan 1 43 | grid [text .msg -background white -height 3 -width 30 -foreground green -relief ridge \ 44 | -borderwidth 3 -font {Courier -17} -state disabled -wrap word -yscrollcommand {.scroll set} ] -padx 10 -pady 10 -column 1 -row 4 -columnspan 3 45 | grid [scrollbar .scroll -command {.msg yview}] -padx 10 -pady 2 -column 4 -row 4 -columnspan 1 46 | 47 | ##### Initialize the message window 48 | status_message "Initializing..." 49 | 50 | ##### Spawn the periodic coroutine 51 | spawn "periodic_function 1" 52 | -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE1-SoC/RemoteConsoleDE1SoC/source/main.tcl: -------------------------------------------------------------------------------- 1 | ##### Figure out path to this script's location 2 | variable main_location [file normalize [info script]] 3 | 4 | set exit_flag 0 5 | set console_script "${main_location}/../console.tcl" 6 | set gui_server_connect_script "${main_location}/../gui_server.tcl" 7 | set gui_board_path "${main_location}/../gui_board.tcl" 8 | 9 | ##### Source global variables 10 | source "${main_location}/../../setup.tcl" 11 | 12 | ##### Source main procedures 13 | source "${main_location}/../main_procs.tcl" 14 | 15 | ##### Connect, program and link device, and return pipe name 16 | lassign [connect_pgm_link $main_location $console_script $gui_server_connect_script $cfg_part $ign_part $prog_regex ] sys_cons_pipe device 17 | 18 | if { $sys_cons_pipe == 1 } { 19 | 20 | exit 21 | 22 | } 23 | 24 | ##### Launch board GUI and tell system console to begin sending transactions 25 | set gui_board_pipe [launch_board_gui $gui_board_path $sys_cons_pipe $device] 26 | if { $gui_board_pipe == 1 } { 27 | 28 | exit 29 | 30 | } 31 | 32 | ##### Enter run loop 33 | run_remote_console $gui_board_pipe $sys_cons_pipe -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE1-SoC/RemoteConsoleDE1SoC/widgets/A.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE1-SoC/RemoteConsoleDE1SoC/widgets/A.png -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE1-SoC/RemoteConsoleDE1SoC/widgets/B.png: -------------------------------------------------------------------------------- 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Use this .qar file to try any other projects outside of those given in the examples. This project is also the starting point for the [Intro to Quartus](https://github.com/intel/FPGA-Devcloud/blob/master/main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/Intro_to_Quartus_Remote_Lab.pdf) project. Like the rest of the Remote Console Example Projects, don't forget to instantiate your User Design at the Top level! 4 | -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/BlankProjectKitIO/blankProject.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/BlankProjectKitIO/blankProject.qar -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Calculator/Calculator.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/Calculator/Calculator.qar -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Calculator/Calculator_RemoteLab.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/Calculator/Calculator_RemoteLab.pdf -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Calculator/README.md: -------------------------------------------------------------------------------- 1 | # Calculator 2 | 3 | This is a lab to test your knowledge in assembling a small FPGA calculator project on the DE10- Lite remote development kit. The circuit adds the values of two counters (0-98) that are enabled with push button (KEY) switches. The two addends and the sum are displayed on the seven segment displays. Since the sum can overflow to a 3rd hundreds place digit and there are only 6 seven segment displays, the hundreds position should be represented by lighting up all 10 LEDs simultaneously. 4 | 5 | ![image](https://user-images.githubusercontent.com/67120855/91607435-e279ca80-e941-11ea-9e38-858bb4421963.png) 6 | 7 | For further instructions on this lab, download the Calculator_RemoteLab.pdf to continue. -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/BlankProject.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/BlankProject.qar -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/In_System_Memory_Content_Editor.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/In_System_Memory_Content_Editor.pdf -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/IntroLab_RemoteBoard_Manual.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/IntroLab_RemoteBoard_Manual.pdf -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/Intro_Lecture_Slides_Remote.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/Intro_Lecture_Slides_Remote.pdf -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/mux_2_to_1.v: -------------------------------------------------------------------------------- 1 | module mux_2_to_1 (SW, LEDR); //Create module mux_2_to_1 2 | 3 | input [9:0]SW; //Input Declarations: 10 slide switches 4 | output[9:0]LEDR; //Output Declarations: 10 red LED lights 5 | 6 | wire S; //Declare the Select signal 7 | wire [2:0] X, Y, M; //Declare the inputs and outputs to the MUX 8 | 9 | assign S = SW[9]; //Assigning input switches to internal signals 10 | assign X = SW[2:0]; 11 | assign Y = SW[5:3]; 12 | 13 | assign LEDR[8:6] = M; //Assigning internal signals to output LEDs 14 | assign LEDR[9] = SW[9]; 15 | assign LEDR[2:0] = SW[2:0]; 16 | assign LEDR[5:3] = SW[5:3]; 17 | 18 | assign M = (S == 0) ? X : Y; //Mux Select Function 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/switch_to_led.v: -------------------------------------------------------------------------------- 1 | module switch_to_led(SW, LEDR); //create module Switch_to_LED 2 | 3 | input [9:0] SW; // input declarations: 10 switches 4 | output [9:0] LEDR; // output declarations: 10 red LEDs 5 | assign LEDR = SW; // connect switches to LEDs 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/KnightRider7Segment/KnightRider7segment.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/KnightRider7Segment/KnightRider7segment.qar -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/KnightRider7Segment/README.md: -------------------------------------------------------------------------------- 1 | # KnightRider7Segment 2 | 3 | If you have not previously worked on the part 5 of the [Intro to Quartus](https://github.com/intel/FPGA-Devcloud/blob/master/main/HandsFree/Devkits/DE10-Lite/Example_Projects/Intro_to_Quartus/Intro_to_Quartus_Remote_Lab.pdf) lab, you can use this project as an example of how the program is supposed to run. Compared to the Intro to Quartus lab, you do not have to do any coding for this project. Once you download the project, compile to look at the LED sequence and the 7 segment display(s) count. 4 | 5 | ![image](https://user-images.githubusercontent.com/67120855/91612037-89fafb00-e94a-11ea-9607-4ee09bfe1eef.png) 6 | 7 | ## KnightRider Background 8 | 9 | Perhaps some of you have heard of or watched a TV show called Knight Rider that aired from 1982 to 1986 and starred David Hasselhoff.The premise of the show was David Hasselhoff was a high-tech crime fighter (at least high technology for 1982) and drove around an intelligent car named “KITT”. The KITT car was a 1982 Pontiac Trans-Am sports car with all sorts of cool gadgets. The interesting gadget of interest for this lab were the headlights of KITT which consisted of a horizontal bar of lights that sequence done at a time from left to right and back again at the rate of about 1/10th of a second per light. In this project you will see sequential logic and flip-flops. Let’s quickly review how flip-flops work. 10 | 11 | Flip-flops are basic storage elements in digital electronics. In their simplest form, they have 3 pins: D, Q, and Clock. The diagram of voltage versus time (often referred to as a waveform) for a flip-flop is shown below. Flip-flops capture the value of the “D” pin when the clock pin (the one with the triangle at its input transitions from low to high). This value of D then shows up at the Q output of the flip-flop a very short time later. The figure below is a flip-flop diagram. 12 | 13 | ![image](https://user-images.githubusercontent.com/67120855/91610798-ed375e00-e947-11ea-83af-13489c9aef21.png) 14 | 15 | When you connect several flip-flops together serially you get what is known as a shift register. That circuit serves as the basis for the Knight Rider LED circuit that we will study in this lab. Note how we clock in a 1 for a single cycle and it “shifts” through the circuit. If that “1” is driving an LED each successive LED will light up for 1/10 of a second. The figure below is a shift register diagram. 16 | 17 | ![image](https://user-images.githubusercontent.com/67120855/91610972-3daebb80-e948-11ea-8b5d-fd8e71512da6.png) -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/KnightRiderKitIO/KnightRiderKitIO.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/KnightRiderKitIO/KnightRiderKitIO.qar -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/KnightRiderKitIO/KnightRiderKitIO.qarlog: -------------------------------------------------------------------------------- 1 | 2 | 3 | ******* Archived project restoration attempt on Wed Aug 11 10:24:06 2021 4 | Source archive file: C:/Users/tsheaves/OneDrive - Intel Corporation/Documents/GitHub/FPGA-Devcloud/main/HandsFree/Devkits/DE10-Lite/Example_Projects/KnightRiderKitIO/KnightRiderKitIO.qar 5 | Archive was extracted into C:/Users/tsheaves/OneDrive - Intel Corporation/Documents/Desktop/KnightRider/ 6 | - successfully. 7 | -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/LogicSolver/Digital_Trainer_HandsFree_Edition.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/LogicSolver/Digital_Trainer_HandsFree_Edition.docx -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/LogicSolver/LogicSolverHandsFree.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/LogicSolver/LogicSolverHandsFree.qar -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/LogicSolver/README.md: -------------------------------------------------------------------------------- 1 | # Digital Logic Trainer: Remote Console Edition 2 | 3 | The purpose of the Digital Trainer project is to test the student’s knowledge of logic gates through a series of quizzes on logic gates ran on an FPGA development board. An FPGA is a type of computer chip that can be programmed to implement a variety of applications. Normally, this project is pre-programmed on a board, the student is able to powers up the board with the USB cable and try out a series of quizzes on how well they know Digital Logic. Without a board, the quizzes can still be run with the Remote Console board. 4 | 5 | In order to do the Remote Console edition of the lab, Quartus should have previously be installed. If not yet installed, you can download Quartus [here](https://fpgasoftware.intel.com/20.1/?edition=lite&platform=windows). 6 | 7 | ## 1. Remote Console Usage 8 | 9 | Download and unarchive the LogicSolverHandsFree.qar file. Compile your program and launch the Remote Console GUI. Follow the picture below for instructions to operate. 10 | 11 | **Note:** If you have already unarchived and need to rerun, go to the LogicSolverHandsFree_restored folder > quartus > double click RemoteLab.qpf and recompile. 12 | 13 | ![image](https://user-images.githubusercontent.com/67120855/89055049-66c73680-d31f-11ea-8f4b-aeba3b605b74.png) 14 | 15 | ​ 16 | 17 | ## **2. Using the Digital Trainer** 18 | 19 | There are 10 challenges programmed into the board. It is your job to decide what the logic function of each challenge is (the challenge number is displayed on the right of the display) by flipping the input switches and observing the output LED (the light on the left of the board). A switch that is flipped “up” is a 1, and a switch flipped “down” is a 0. Likewise, an LED on is while an LED off is a 0. The number on the left indicates whether the function is two input (2In, thus using only the two rightmost switches, or 3In, using the three rightmost switches). You can flip between the different challenges using the buttons on the board: to advance to the next challenge press the rightmost button, or press the button to the left to advance to the previous challenge. Try to circle the correct function for each sequence! 20 | 21 | | Sequence Number | Number of Inputs | Logic Function | 22 | | :-------------: | :--------------: | :---------------------------------: | 23 | | 1 | 2 | AND OR NAND NOR XOR | 24 | | 2 | 2 | AND OR NAND NOR XOR | 25 | | 3 | 2 | AND OR NAND NOR XOR | 26 | | 4 | 2 | AND OR NAND NOR XOR | 27 | | 5 | 2 | AND OR NAND NOR XOR | 28 | | 6 | 3 | AND OR NAND NOR XOR | 29 | | 7 | 3 | AND OR NAND NOR XOR | 30 | | 8 | 3 | AND OR NAND NOR XOR | 31 | | 9 | 3 | AND OR NAND NOR XOR | 32 | | 10 | 3 | AND OR NAND NOR XOR | 33 | 34 | ​To get the table above in excel format, click on LogicSolverChoice.xlsh at the top of this page. 35 | -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/OR2x1/OR2x1.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/OR2x1/OR2x1.qar -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/OR2x1/README.md: -------------------------------------------------------------------------------- 1 | # OR2x1 2 | 3 | This is a simple project that shows the OR digital logic gate functionality. Play around with switch 0 and 1 and see when LEDR 0 turns on. No coding required. 4 | 5 | ![How Logic Gates Work in Digital Electronics | EAGLE | Blog](https://www.autodesk.com/products/eagle/blog/wp-content/uploads/2017/05/Or-gate-en.svg_.png) -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Parity10b/Parity10b.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/Parity10b/Parity10b.qar -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/Parity10b/README.md: -------------------------------------------------------------------------------- 1 | # Parity10b 2 | 3 | Parity10b is a simple project that counts the amount of switches that are on and if it totals to an odd numbers, turns LEDR0 on. No extra coding is required for this project. 4 | 5 | ![image](https://user-images.githubusercontent.com/67120855/91616553-e9113d80-e953-11ea-8f1d-1864f9c2b0ac.png) 6 | 7 | -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/Example_Projects/VHDL_counter/counter_VHDL.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/Example_Projects/VHDL_counter/counter_VHDL.qar -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10Lite.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10Lite.zip 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# Needs to be adapted for Linux 10 | } 11 | variable launch_location [file normalize [info script]] 12 | open "|$env(QUARTUS_ROOTDIR)bin64/quartus_sh --script ${launch_location}/../source/main.tcl" -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10Lite/source/gui_server.tcl: -------------------------------------------------------------------------------- 1 | ##### Figure out path to this script's location 2 | variable gui_server_location [file normalize [info script]] 3 | 4 | ##### Flush pipe after any stdout puts command 5 | fconfigure stdout -buffering line 6 | 7 | ##### Do not block pipe when using gets command 8 | fconfigure stdin -blocking 0 9 | 10 | ##### Get global variables 11 | source "${gui_server_location}/../../setup.tcl" 12 | 13 | ##### Get GUI procedures 14 | source "${gui_server_location}/../gui_server_procs.tcl" 15 | 16 | ##### Initialize the board connect window 17 | init_top_window "Board Connect" 18 | 19 | ##### Initialize the board connect parameters 20 | lassign [initial_credentials] ips credential_fh ip_address password sof_file mode pws 21 | 22 | set password_old $password 23 | set ip_address_old $ip_address 24 | 25 | ##### Add widgets and place into a widget grid 26 | grid [label .ip_lab -text "IPv4" -background white -font {Courier -17} ] -padx 10 -pady 6 -column 1 -row 1 -columnspan 1 -sticky "snew" 27 | grid [ ttk::combobox .ip_address -textvariable ip_address -values $ips -background white \ 28 | -font {Courier -17 } -foreground black -justify left -state normal -width 15] -padx 10 -pady 6 -column 2 -row 1 -columnspan 2 -sticky "snew" 29 | grid [label .pw_lab -text "Password" -background white -font {Courier -17} -justify right] -padx 10 -pady 6 -column 1 -row 2 -columnspan 1 -sticky "snew" 30 | grid [entry .pw_ent -background white -foreground black -relief ridge -width 17 \ 31 | -font {Courier -17} -textvariable password -justify left -state normal -state normal ] -padx 10 -pady 6 -column 2 -row 2 -columnspan 2 -sticky "snew" 32 | grid [label .sof_lab -text "SOF File" -background white -font {Courier -17} ] -padx 10 -pady 6 -column 1 -row 3 -columnspan 1 -sticky "snew" 33 | grid [entry .sof_ent -background white -foreground black -relief ridge -width 17 \ 34 | -font {Courier -17} -textvariable sof_file -justify left -state disabled ] -padx 10 -pady 6 -column 2 -row 3 -columnspan 2 -sticky "snew" 35 | # grid [ ttk::combobox .sof_entry -textvariable sof_file -values "" -background white \ 36 | -font {Courier -17 } -foreground black -justify left -state disabled -width 15] -padx 10 -pady 6 -column 2 -row 3 -columnspan 2 -sticky "snew" 37 | grid [button .link_button -text "Link" -height 1 -width 12 \ 38 | -command {set mode [link_press $ips $credential_fh $ip_address $password $sof_file $pws] } -state disabled ] -padx 10 -pady 6 -column 3 -row 5 -columnspan 1 39 | grid [button .rm_ips_button -text "Clear IPv4s" -height 1 -width 12 \ 40 | -command {lassign [remove_ips] ips credential_fh ip_address password sof_file mode pws; .ip_address configure -values $ips} -state normal ] -padx 10 -pady 6 -column 1 -row 5 -columnspan 1 41 | grid [button .sof_select_button -text "Select .sof" -height 1 -width 12 \ 42 | -command {set sof_file [tk_getOpenFile]; .sof_ent xview moveto 1.0; .sof_ent icursor end} -state normal ] -padx 10 -pady 6 -column 2 -row 5 -columnspan 1 43 | grid [text .msg -background white -height 3 -width 30 -foreground green -relief ridge \ 44 | -borderwidth 3 -font {Courier -17} -state disabled -wrap word -yscrollcommand {.scroll set} ] -padx 10 -pady 10 -column 1 -row 4 -columnspan 3 45 | grid [scrollbar .scroll -command {.msg yview}] -padx 10 -pady 2 -column 4 -row 4 -columnspan 1 46 | 47 | ##### Initialize the message window 48 | status_message "Initializing..." 49 | 50 | ##### Spawn the periodic coroutine 51 | spawn "periodic_function 1" 52 | -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10Lite/source/main.tcl: -------------------------------------------------------------------------------- 1 | ##### Figure out path to this script's location 2 | variable main_location [file normalize [info script]] 3 | 4 | set console_script "${main_location}/../console.tcl" 5 | set gui_server_connect_script "${main_location}/../gui_server.tcl" 6 | set gui_board_path "${main_location}/../gui_board.tcl" 7 | 8 | ##### Source global variables 9 | source "${main_location}/../../setup.tcl" 10 | 11 | ##### Source main procedures 12 | source "${main_location}/../main_procs.tcl" 13 | 14 | ##### Connect, program and link device, and return pipe name 15 | lassign [connect_pgm_link $main_location $console_script $gui_server_connect_script] sys_cons_pipe device 16 | 17 | if { $sys_cons_pipe == 1 } { 18 | 19 | exit 20 | 21 | } 22 | 23 | ##### Launch board GUI and tell system console to begin sending transactions 24 | set gui_board_pipe [launch_board_gui $gui_board_path $sys_cons_pipe $device] 25 | if { $gui_board_pipe == 1 } { 26 | 27 | exit 28 | 29 | } 30 | 31 | ##### Enter run loop 32 | run_remote_console $gui_board_pipe $sys_cons_pipe -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10Lite/widgets/DE10Lite.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10Lite/widgets/DE10Lite.png -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10Lite/widgets/SWs.png: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | # Stop all Quartus Shell tasks (protects against zombie processes stacking) 2 | if { [catch { exec taskkill /IM "quartus_sh.exe" /F } ] != 0} { 3 | # Do nothing 4 | # Needs to be adapted for Linux 5 | } 6 | # Stop all System Console tasks (protects against zombie processes stacking) 7 | if { [catch { exec taskkill /IM "system-console.exe" /F } ] != 0} { 8 | # Do nothing 9 | # Needs to be adapted for Linux 10 | } 11 | variable launch_location [file normalize [info script]] 12 | open "|$env(QUARTUS_ROOTDIR)bin64/quartus_sh --script ${launch_location}/../source/main.tcl" -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10LiteKitIO/run_GUI.bat: -------------------------------------------------------------------------------- 1 | set path_to_main=C:/Users/tsheaves/Documents/RemoteConsoleDE10Lite/Source/main.tcl 2 | set quartus_bin=C:/intelFPGA_lite/19.1/quartus/bin64 3 | START /min /WAIT C:/Windows/System32/taskkill /IM "system-console.exe" /F 4 | START /min /WAIT C:/Windows/System32/taskkill /IM "quartus_sh.exe" /F 5 | START /min %quartus_bin%/quartus_sh --script "%path_to_main%" -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10LiteKitIO/source/gui_server.tcl: -------------------------------------------------------------------------------- 1 | ##### Figure out path to this script's location 2 | variable gui_server_location [file normalize [info script]] 3 | 4 | ##### Flush pipe after any stdout puts command 5 | fconfigure stdout -buffering line 6 | 7 | ##### Do not block pipe when using gets command 8 | fconfigure stdin -blocking 0 9 | 10 | ##### Get global variables 11 | source "${gui_server_location}/../../setup.tcl" 12 | 13 | ##### Get GUI procedures 14 | source "${gui_server_location}/../gui_server_procs.tcl" 15 | 16 | ##### Initialize the board connect window 17 | init_top_window "Board Connect" 18 | 19 | ##### Initialize the board connect parameters 20 | lassign [initial_credentials] ips credential_fh ip_address password sof_file mode pws 21 | 22 | set password_old $password 23 | set ip_address_old $ip_address 24 | 25 | ##### Add widgets and place into a widget grid 26 | grid [label .ip_lab -text "IPv4" -background white -font {Courier -17} ] -padx 10 -pady 6 -column 1 -row 1 -columnspan 1 -sticky "snew" 27 | grid [ ttk::combobox .ip_address -textvariable ip_address -values $ips -background white \ 28 | -font {Courier -17 } -foreground black -justify left -state normal -width 15] -padx 10 -pady 6 -column 2 -row 1 -columnspan 2 -sticky "snew" 29 | grid [label .pw_lab -text "Password" -background white -font {Courier -17} -justify right] -padx 10 -pady 6 -column 1 -row 2 -columnspan 1 -sticky "snew" 30 | grid [entry .pw_ent -background white -foreground black -relief ridge -width 17 \ 31 | -font {Courier -17} -textvariable password -justify left -state normal -state normal ] -padx 10 -pady 6 -column 2 -row 2 -columnspan 2 -sticky "snew" 32 | grid [label .sof_lab -text "SOF File" -background white -font {Courier -17} ] -padx 10 -pady 6 -column 1 -row 3 -columnspan 1 -sticky "snew" 33 | grid [entry .sof_ent -background white -foreground black -relief ridge -width 17 \ 34 | -font {Courier -17} -textvariable sof_file -justify left -state disabled ] -padx 10 -pady 6 -column 2 -row 3 -columnspan 2 -sticky "snew" 35 | grid [label .pgm_label -text "Program Device?" -background white -font {Courier -17}] -padx 5 -pady 6 -column 1 -row 4 -columnspan 2 -sticky "snew" 36 | grid [checkbutton .chk_pgm -background white -foreground black -variable pgm_device] -padx 1 -pady 6 -column 3 -row 4 -columnspan 1 -sticky "snew" 37 | 38 | 39 | grid [text .msg -background white -height 3 -width 30 -foreground green -relief ridge \ 40 | -borderwidth 3 -font {Courier -17} -state disabled -wrap word -yscrollcommand {.scroll set} ] -padx 10 -pady 10 -column 1 -row 5 -columnspan 3 41 | grid [scrollbar .scroll -command {.msg yview}] -padx 10 -pady 2 -column 4 -row 5 -columnspan 1 42 | 43 | # grid [ ttk::combobox .sof_entry -textvariable sof_file -values "" -background white \ 44 | -font {Courier -17 } -foreground black -justify left -state disabled -width 15] -padx 10 -pady 6 -column 2 -row 3 -columnspan 2 -sticky "snew" 45 | grid [button .link_button -text "Link" -height 1 -width 12 \ 46 | -command {set mode [link_press $ips $credential_fh $ip_address $password $sof_file $pws $pgm_device] } -state disabled ] -padx 10 -pady 6 -column 3 -row 6 -columnspan 1 47 | grid [button .rm_ips_button -text "Clear IPv4s" -height 1 -width 12 \ 48 | -command {lassign [remove_ips] ips credential_fh ip_address password sof_file mode pws; .ip_address configure -values $ips} -state normal ] -padx 10 -pady 6 -column 1 -row 6 -columnspan 1 49 | grid [button .sof_select_button -text "Select .sof" -height 1 -width 12 \ 50 | -command {set sof_file [tk_getOpenFile]; .sof_ent xview moveto 1.0; .sof_ent icursor end} -state normal ] -padx 10 -pady 6 -column 2 -row 6 -columnspan 1 51 | 52 | ##### Initialize the message window 53 | status_message "Initializing..." 54 | 55 | ##### Spawn the periodic coroutine 56 | spawn "periodic_function 1" 57 | -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10LiteKitIO/source/main.tcl: -------------------------------------------------------------------------------- 1 | ##### Figure out path to this script's location 2 | variable main_location [file normalize [info script]] 3 | 4 | set console_script "${main_location}/../console.tcl" 5 | set gui_server_connect_script "${main_location}/../gui_server.tcl" 6 | set gui_board_path "${main_location}/../gui_board.tcl" 7 | 8 | ##### Source global variables 9 | source "${main_location}/../../setup.tcl" 10 | 11 | ##### Source main procedures 12 | source "${main_location}/../main_procs.tcl" 13 | 14 | ##### Connect, program and link device, and return pipe name 15 | lassign [connect_pgm_link $main_location $console_script $gui_server_connect_script] sys_cons_pipe device 16 | 17 | if { $sys_cons_pipe == 1 } { 18 | 19 | exit 20 | 21 | } 22 | 23 | ##### Launch board GUI and tell system console to begin sending transactions 24 | set gui_board_pipe [launch_board_gui $gui_board_path $sys_cons_pipe $device] 25 | if { $gui_board_pipe == 1 } { 26 | 27 | exit 28 | 29 | } 30 | 31 | ##### Enter run loop 32 | run_remote_console $gui_board_pipe $sys_cons_pipe -------------------------------------------------------------------------------- /main/HandsFree/Devkits/DE10-Lite/RemoteConsoleDE10LiteKitIO/widgets/DE10Lite.png: -------------------------------------------------------------------------------- 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#include 2 | #include 3 | #include "altera_avalon_pio_regs.h" 4 | #include "system.h" 5 | 6 | int main() 7 | { 8 | int switch_datain; 9 | int custom32; 10 | int i,j; 11 | alt_putstr("Hello from Nios II!\n"); 12 | alt_putstr("When you press Push Button 0,1 the switching on of the LEDs is done by software\n"); 13 | alt_putstr("But, Switching on/off of LED 2 by SW 2 is done by hardware\n"); 14 | /* Event loop never exits. Read the PB, display on the LED */ 15 | 16 | printf("Value is %x\n", custom32); 17 | while (1) 18 | { 19 | //Gets the data from the pb, recall that a 0 means the button is pressed 20 | switch_datain = ~IORD_ALTERA_AVALON_PIO_DATA(BUTTON_BASE); 21 | //Mask the bits so the leftmost LEDs are off (we only care about LED3-0) 22 | switch_datain &= (0b0000000011); 23 | //Send the data to the LED 24 | IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE,switch_datain); 25 | for(i=1; i<=20;i++){ 26 | usleep(50000); 27 | // for(j=0; j<=500000; j++); 28 | IOWR_ALTERA_AVALON_PIO_DATA(REG_32_AVALON_INTERFACE_0_BASE, i*12.5); 29 | } 30 | } 31 | return 0; 32 | } 33 | -------------------------------------------------------------------------------- /main/QuickStartGuides/EmbeddedNios_DE_board_Quickstart/CustomComponents/PWM_generator.v: -------------------------------------------------------------------------------- 1 | module PWM_generator (PWM_ontime, PWM_out , clk , reset); 2 | 3 | input clk, reset; // Port type declared 4 | input [7:0] PWM_ontime; // 8-bit PWM input 5 | 6 | output reg PWM_out; // 1 bit PWM output 7 | wire [7:0] counter_out; // 8-bit counter 8 | 9 | 10 | always @ (posedge clk) 11 | begin 12 | if (PWM_ontime > counter_out) 13 | PWM_out <= 1; 14 | else 15 | PWM_out <= 0; 16 | end 17 | counter counter_inst( 18 | .clk (clk), 19 | .counter_out (counter_out), 20 | .reset(reset) 21 | ); 22 | 23 | endmodule 24 | 25 | module counter(counter_out,clk,reset); 26 | 27 | output [7:0] counter_out; 28 | input clk, reset; 29 | reg [7:0] counter_out; 30 | always @(posedge clk) 31 | if (reset) 32 | counter_out <= 8'b0; 33 | else 34 | counter_out <= counter_out + 1; 35 | endmodule -------------------------------------------------------------------------------- /main/QuickStartGuides/EmbeddedNios_DE_board_Quickstart/CustomComponents/reg32_avalon_interface.v: -------------------------------------------------------------------------------- 1 | module reg32 (clk, resetn, D, byteenable, Q); 2 | input clk, resetn; 3 | input [3:0] byteenable; 4 | input [31:0] D; 5 | output reg [31:0] Q; 6 | 7 | always @(posedge clk) 8 | if (!resetn) 9 | Q <= 32'b0; 10 | else 11 | 12 | begin 13 | // Enable writing to each byte separately 14 | if (byteenable[0]) Q[7:0] <= D[7:0]; 15 | if (byteenable[1]) Q[15:8] <= D[15:8]; 16 | if (byteenable[2]) Q[23:16] <= D[23:16]; 17 | if (byteenable[3]) Q[31:24] <= D[31:24]; 18 | end 19 | 20 | endmodule 21 | 22 | module reg32_avalon_interface (clk, resetn, writedata, readdata, write, read, 23 | byteenable, chipselect, Q_export); 24 | 25 | // signals for connecting to the Avalon fabric 26 | input clk, resetn, read, write, chipselect; 27 | input [3:0] byteenable; 28 | input [31:0] writedata; 29 | output [31:0] readdata; 30 | // signal for exporting register contents outside of the embedded system 31 | output [31:0] Q_export; 32 | wire [3:0] local_byteenable; 33 | wire [31:0] to_reg, from_reg; 34 | 35 | assign to_reg = writedata; 36 | assign local_byteenable = (chipselect & write) ? byteenable : 4'd0; 37 | 38 | reg32 U1 ( .clk(clk), .resetn(resetn), .D(to_reg), 39 | .byteenable(local_byteenable), .Q(from_reg) ); 40 | 41 | assign readdata = from_reg; 42 | assign Q_export = from_reg; 43 | endmodule -------------------------------------------------------------------------------- /main/QuickStartGuides/EmbeddedNios_DE_board_Quickstart/EmbeddedNios_DE_board_Quickstart.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/EmbeddedNios_DE_board_Quickstart/EmbeddedNios_DE_board_Quickstart.pdf -------------------------------------------------------------------------------- /main/QuickStartGuides/EmbeddedNios_DE_board_Quickstart/NiosDevcloud.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/EmbeddedNios_DE_board_Quickstart/NiosDevcloud.zip -------------------------------------------------------------------------------- /main/QuickStartGuides/Externally_Hosted_Training/UF_Dr_Greg_Stitt/README.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | # University of Florida: Sponsored Intel FPGA Devcloud Training 4 | 5 | 6 | 7 | ## 1 Introduction 8 | 9 | We are pleased to be partnering with Dr Greg Stitt at the University of Florida for FPGA devcloud based coursework on Intel PAC Cards. Dr Stitt's coursework includes generation of RTL AFUs with other courses being developed. Videos and lab exercises are available for self-paced training. Check this site often as new courses are being developed. 10 | 11 | https://github.com/ARC-Lab-UF/intel-training-modules 12 | 13 | 14 | 15 | ## 2 Document Revision History 16 | 17 | List the revision history for the application note. 18 | 19 | | Name | Date | Changes | 20 | | ------------ | --------- | --------------- | 21 | | Larry Landis | 5/12/2020 | Initial Release | 22 | 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Externally_Hosted_Training/uMass_Lowell_Dr_Yan_Luo/README.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | # University of Massachusetts Lowell: Intel FPGA Devcloud Training 4 | 5 | 6 | 7 | ## 1 Introduction 8 | 9 | We are pleased to be partnering with Dr Yan Luo at uMass Lowell for FPGA devcloud based Heterogeneous Computing coursework. This course introduces heterogeneous computing architecture and the design and optimization of applications that best utilize the resources on such platforms. The course topics include heterogeneous computer architecture, offloading architecture/API, operating systems for heterogeneous resources, GPU/FPGA acceleration, OpenCL programming framework, performance optimization, and software development. Labs are included to practice design methodology and tools. 10 | 11 | https://github.com/acanets/eece-6540-labs 12 | 13 | 14 | 15 | ## 2 Document Revision History 16 | 17 | List the revision history for the application note. 18 | 19 | | Name | Date | Changes | 20 | | ------------ | --------- | --------------- | 21 | | Larry Landis | 5/20/2020 | Initial Release | 22 | 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /main/QuickStartGuides/HLS_Lab/HighLevelDesign-HLS-Lecture_Slides.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/HLS_Lab/HighLevelDesign-HLS-Lecture_Slides.pptx -------------------------------------------------------------------------------- /main/QuickStartGuides/HLS_Lab/hls_lab_manual_source_files.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/HLS_Lab/hls_lab_manual_source_files.zip -------------------------------------------------------------------------------- /main/QuickStartGuides/OneAPI_Program_PAC_Quickstart/Arria 10/A10_oneapi_batch.sh: -------------------------------------------------------------------------------- 1 | # Copyright 2020 Intel Corporation 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated 4 | # documentation files (the "Software"), to deal in the Software without restriction, including without limitation 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, 6 | # and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 7 | # The above copyright notice and this permission notice shall be included in all copies or substantial portions 8 | # of the Software. 9 | # 10 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 11 | # TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 12 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 13 | # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 14 | # DEALINGS IN THE SOFTWARE. 15 | 16 | ########################################################################################################### 17 | # The following flow assumes A10_ONEAPI directory doesn't exist and sample design hasn't been copied over 18 | # **Adjust commands to your own needs.** 19 | ########################################################################################################### 20 | 21 | # Initial Setup 22 | source /data/intel_fpga/devcloudLoginToolSetup.sh 23 | tools_setup -t A10OAPI 24 | # Job will exit if directory already exists; no overwrite. No error message. 25 | [ ! -d ~/A10_ONEAPI/vector-add ] && mkdir -p ~/A10_ONEAPI/vector-add || exit 0 26 | 27 | # Copy Over sample design 28 | cd ~/A10_ONEAPI/vector-add 29 | wget -N https://raw.githubusercontent.com/intel/FPGA-Devcloud/master/main/QuickStartGuides/OneAPI_Program_PAC_Quickstart/Arria%2010/download-file-list.txt 30 | wget -i download-file-list.txt 31 | mkdir src 32 | mv *.cpp *.hpp src/ 33 | 34 | # Running project in Emulation mode 35 | printf "\\n%s\\n" "Running in Emulation Mode:" 36 | make run_emu -f Makefile.fpga 37 | error_check 38 | 39 | # Running project in FPGA Hardware Mode (this takes approximately 1 hour) 40 | printf "\\n%s\\n" "Running in FPGA Hardware Mode:" 41 | make run_hw -f Makefile.fpga 42 | error_check 43 | -------------------------------------------------------------------------------- /main/QuickStartGuides/OneAPI_Program_PAC_Quickstart/Arria 10/download-file-list.txt: -------------------------------------------------------------------------------- 1 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/src/dpc_common.hpp 2 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/src/vector-add-buffers.cpp 3 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/src/vector-add-usm.cpp 4 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/License.txt 5 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/Makefile 6 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/Makefile.fpga 7 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/Makefile.win 8 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/Makefile.win.fpga 9 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/README.md 10 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/sample.json 11 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/vector-add-usm.vcxproj 12 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/vector-add.sln -------------------------------------------------------------------------------- /main/QuickStartGuides/OneAPI_Program_PAC_Quickstart/Stratix 10/S10_oneapi_batch.sh: -------------------------------------------------------------------------------- 1 | # Copyright 2020 Intel Corporation 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated 4 | # documentation files (the "Software"), to deal in the Software without restriction, including without limitation 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, 6 | # and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 7 | # The above copyright notice and this permission notice shall be included in all copies or substantial portions 8 | # of the Software. 9 | # 10 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 11 | # TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 12 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 13 | # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 14 | # DEALINGS IN THE SOFTWARE. 15 | 16 | ########################################################################################################### 17 | # The following flow assumes S10_ONEAPI directory doesn't exist and sample design hasn't been copied over 18 | # **Adjust commands to your own needs.** 19 | ########################################################################################################### 20 | 21 | # Initial Setup 22 | source /data/intel_fpga/devcloudLoginToolSetup.sh 23 | tools_setup -t S10OAPI 24 | # Job will exit if directory already exists; no overwrite. No error message. 25 | [ ! -d ~/S10_ONEAPI/vector-add ] && mkdir -p ~/S10_ONEAPI/vector-add || exit 0 26 | 27 | # Copy Over sample design 28 | cd ~/S10_ONEAPI/vector-add 29 | wget -N https://raw.githubusercontent.com/intel/FPGA-Devcloud/master/main/QuickStartGuides/OneAPI_Program_PAC_Quickstart/Stratix%2010/download-file-list.txt 30 | wget -i download-file-list.txt 31 | mkdir src 32 | mv *.cpp *.hpp src/ 33 | 34 | # Running project in Emulation mode 35 | printf "\\n%s\\n" "Running in Emulation Mode:" 36 | make run_emu -f Makefile.fpga 37 | error_check 38 | 39 | # Running project in FPGA Hardware Mode (this takes approximately 1 hour) 40 | printf "\\n%s\\n" "Running in FPGA Hardware Mode:" 41 | make run_hw -f Makefile.fpga 42 | error_check 43 | -------------------------------------------------------------------------------- /main/QuickStartGuides/OneAPI_Program_PAC_Quickstart/Stratix 10/download-file-list.txt: -------------------------------------------------------------------------------- 1 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/src/dpc_common.hpp 2 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/src/vector-add-buffers.cpp 3 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/src/vector-add-usm.cpp 4 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/License.txt 5 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/Makefile 6 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/Makefile.fpga 7 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/Makefile.win 8 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/Makefile.win.fpga 9 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/README.md 10 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/sample.json 11 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/vector-add-usm.vcxproj 12 | https://raw.githubusercontent.com/intel/BaseKit-code-samples/master/DPC%2B%2BCompiler/vector-add/vector-add.sln -------------------------------------------------------------------------------- /main/QuickStartGuides/OpenCL_Program_PAC_Quickstart/Arria 10/A10_v1.2.1_opencl_batch.sh: -------------------------------------------------------------------------------- 1 | # Copyright 2020 Intel Corporation 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated 4 | # documentation files (the "Software"), to deal in the Software without restriction, including without limitation 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, 6 | # and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 7 | # The above copyright notice and this permission notice shall be included in all copies or substantial portions 8 | # of the Software. 9 | # 10 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 11 | # TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 12 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 13 | # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 14 | # DEALINGS IN THE SOFTWARE. 15 | 16 | ############################################################################################################# 17 | # The following flow assumes A10_OPENCL_AFU directory doesn't exist and sample design hasn't been copied over 18 | # Arria 10 Devstack version 1.2.1 19 | # **Adjust commands to your own needs.** 20 | ############################################################################################################# 21 | 22 | # Initial Setup 23 | source /data/intel_fpga/devcloudLoginToolSetup.sh 24 | tools_setup -t A10DS 25 | # Job will exit if directory already exists; no overwrite. No error message. 26 | [ ! -d ~/A10_OPENCL_AFU/v1.2.1 ] && mkdir -p ~/A10_OPENCL_AFU/v1.2.1 || exit 0 27 | 28 | # Copy Over sample design 29 | cp -r /opt/intelFPGA_pro/quartus_19.2.0b57/hld/examples_aoc/hello_world A10_OPENCL_AFU/v1.2.1 30 | cp -r /opt/intelFPGA_pro/quartus_19.2.0b57/hld/examples_aoc/common A10_OPENCL_AFU/v1.2.1 31 | cd A10_OPENCL_AFU/v1.2.1 32 | 33 | # Check Arria 10 PAC card connectivity 34 | aocl diagnose 35 | error_check 36 | 37 | # Running project in Emulation mode 38 | cd hello_world 39 | printf "\\n%s\\n" "Running in Emulation Mode:" 40 | aoc -march=emulator -v device/hello_world.cl -o bin/hello_world_emulation.aocx 41 | # Creating symbolic link to emulation .aocx 42 | ln -sf hello_world_emulation.aocx bin/hello_world.aocx 43 | make 44 | # Run host code for version 1.2.1 45 | ./bin/host -emulator 46 | error_check 47 | 48 | # Running project in FPGA Hardware Mode (this takes approximately 1 hour) 49 | printf "\\n%s\\n" "Running in FPGA Hardware Mode:" 50 | aoc device/hello_world.cl -o bin/hello_world_fpga.aocx -board=pac_a10 51 | # Relink to hardware .aocx 52 | ln -sf hello_world_fpga.aocx bin/hello_world.aocx 53 | # Availavility of Acceleration cards 54 | aoc -list-boards 55 | error_check 56 | # Get device name 57 | aocl diagnose 58 | error_check 59 | 60 | # Converting to an unsigned .aocx file 61 | cd bin 62 | printf "\\n%s\\n" "Converting to unsigned .aocx:" 63 | printf "Y\\nY\\n" | source $AOCL_BOARD_PACKAGE_ROOT/linux64/libexec/sign_aocx.sh -H openssl_manager -i hello_world_fpga.aocx -r NULL -k NULL -o hello_world_fpga_unsigned.aocx 64 | error_check 65 | # Programmming PAC Card 66 | aocl program acl0 hello_world_fpga_unsigned.aocx 67 | ./host 68 | error_check 69 | -------------------------------------------------------------------------------- /main/QuickStartGuides/OpenCL_Program_PAC_Quickstart/Arria 10/A10_v1.2_opencl_batch.sh: -------------------------------------------------------------------------------- 1 | # Copyright 2020 Intel Corporation 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated 4 | # documentation files (the "Software"), to deal in the Software without restriction, including without limitation 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, 6 | # and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 7 | # The above copyright notice and this permission notice shall be included in all copies or substantial portions 8 | # of the Software. 9 | # 10 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 11 | # TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 12 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 13 | # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 14 | # DEALINGS IN THE SOFTWARE. 15 | 16 | ########################################################################################################### 17 | # The following flow assumes A10_OPENCL_AFU directory doesn't exist and sample design hasn't been copied over 18 | # Arria 10 Devstack version 1.2 19 | # **Adjust commands to your own needs.** 20 | ########################################################################################################### 21 | 22 | # Initial Setup 23 | source /data/intel_fpga/devcloudLoginToolSetup.sh 24 | tools_setup -t A10DS 25 | # Job will exit if directory already exists; no overwrite. No error message. 26 | [ ! -d ~/A10_OPENCL_AFU/v1.2 ] && mkdir -p ~/A10_OPENCL_AFU/v1.2 || exit 0 27 | 28 | # Copy Over sample design 29 | cp $OPAE_PLATFORM_ROOT/opencl/exm_opencl_hello_world_x64_linux.tgz A10_OPENCL_AFU/v1.2 30 | cd A10_OPENCL_AFU/v1.2 31 | printf "\\n%s\\n" "Extracting tarfiles:" 32 | tar xvf exm_opencl_hello_world_x64_linux.tgz 33 | 34 | # Check Arria 10 PAC card connectivity 35 | aocl diagnose 36 | error_check 37 | 38 | # Running project in Emulation mode 39 | cd hello_world 40 | printf "\\n%s\\n" "Running in Emulation Mode:" 41 | aoc -march=emulator -v device/hello_world.cl -o bin/hello_world_emulation.aocx 42 | # Creating symbolic link to emulation .aocx 43 | ln -sf hello_world_emulation.aocx bin/hello_world.aocx 44 | make 45 | # Run host code for version 1.2 46 | CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./bin/host 47 | error_check 48 | 49 | # Running project in FPGA Hardware Mode (this takes approximately 1 hour) 50 | printf "\\n%s\\n" "Running in FPGA Hardware Mode:" 51 | aoc device/hello_world.cl -o bin/hello_world_fpga.aocx -board=pac_a10 52 | # Relink to hardware .aocx 53 | ln -sf hello_world_fpga.aocx bin/hello_world.aocx 54 | # Availavility of Acceleration cards 55 | aoc -list-boards 56 | error_check 57 | # Get device name 58 | aocl diagnose 59 | error_check 60 | # Programmming PAC Card 61 | aocl program acl0 bin/hello_world.aocx 62 | ./bin/host 63 | error_check 64 | -------------------------------------------------------------------------------- /main/QuickStartGuides/OpenCL_Program_PAC_Quickstart/Arria 10/debug.log: -------------------------------------------------------------------------------- 1 | [0406/163750.665:ERROR:registration_protocol_win.cc(130)] TransactNamedPipe: The pipe has been ended. (0x6D) 2 | -------------------------------------------------------------------------------- /main/QuickStartGuides/OpenCL_Program_PAC_Quickstart/Stratix 10/S10_opencl_batch.sh: -------------------------------------------------------------------------------- 1 | # Copyright 2020 Intel Corporation 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated 4 | # documentation files (the "Software"), to deal in the Software without restriction, including without limitation 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, 6 | # and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 7 | # The above copyright notice and this permission notice shall be included in all copies or substantial portions 8 | # of the Software. 9 | # 10 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 11 | # TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 12 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 13 | # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 14 | # DEALINGS IN THE SOFTWARE. 15 | 16 | ########################################################################################################### 17 | # The following flow assumes S10_OPENCL_AFU directory doesn't exist and sample design hasn't been copied over 18 | # **Adjust commands to your own needs.** 19 | ########################################################################################################### 20 | 21 | # Initial Setup 22 | source /data/intel_fpga/devcloudLoginToolSetup.sh 23 | tools_setup -t S10DS 24 | # Job will exit if directory already exists; no overwrite. No error message. 25 | [ ! -d ~/S10_OPENCL_AFU ] && mkdir -p ~/S10_OPENCL_AFU || exit 0 26 | 27 | # Copy Over sample design 28 | cp $OPAE_PLATFORM_ROOT/opencl/exm_opencl_hello_world_x64_linux.tgz S10_OPENCL_AFU 29 | cd S10_OPENCL_AFU 30 | printf "\\n%s\\n" "Extracting tarfiles:" 31 | tar xvf exm_opencl_hello_world_x64_linux.tgz 32 | 33 | # Check Stratix 10 PAC card connectivity 34 | aocl diagnose 35 | error_check 36 | 37 | #Compile for emulation 38 | cd hello_world 39 | printf "\\n%s\\n" "Running in Emulation Mode:" 40 | aoc -march=emulator -legacy-emulator device/hello_world.cl -o bin/hello_world_emulation.aocx 41 | # Creating symbolic link to emulation .aocx 42 | ln -sf hello_world_emulation.aocx bin/hello_world.aocx 43 | # Compile host software 44 | make 45 | # Run in emulation mode 46 | CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./bin/host 47 | error_check 48 | 49 | # Compile for FPGA hardware (this takes approximately 1 hour) 50 | printf "\\n%s\\n" "Running in FPGA Hardware Mode:" 51 | aoc device/hello_world.cl -o bin/hello_world_fpga.aocx -board=pac_s10_dc 52 | # Relink to hardware .aocx 53 | ln -sf hello_world_fpga.aocx bin/hello_world.aocx 54 | # Program PAC Card 55 | aocl program acl0 bin/hello_world.aocx 56 | # Run host code 57 | ./bin/host 58 | error_check 59 | -------------------------------------------------------------------------------- /main/QuickStartGuides/RTL_AFU_Program_PAC_Quickstart/Arria10/A10_v1.2.1_rtl_batch.sh: -------------------------------------------------------------------------------- 1 | # Copyright 2020 Intel Corporation 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated 4 | # documentation files (the "Software"), to deal in the Software without restriction, including without limitation 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, 6 | # and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 7 | # The above copyright notice and this permission notice shall be included in all copies or substantial portions 8 | # of the Software. 9 | # 10 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 11 | # TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 12 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 13 | # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 14 | # DEALINGS IN THE SOFTWARE. 15 | 16 | ########################################################################################################## 17 | # The following flow assumes A10_RTL_AFU directory doesn't exist and sample design hasn't been copied over 18 | # Arria 10 Devstack version 1.2.1 19 | # **Adjust commands to your own needs.** 20 | ########################################################################################################## 21 | 22 | # Initial Setup 23 | source /data/intel_fpga/devcloudLoginToolSetup.sh 24 | tools_setup -t A10DS 25 | # Job will exit if directory already exists; no overwrite. No error message. 26 | [ ! -d ~/A10_RTL_AFU/v1.2.1 ] && mkdir -p ~/A10_RTL_AFU/v1.2.1 || exit 0 27 | 28 | # Copy Over sample design 29 | cp -r $OPAE_PLATFORM_ROOT/hw/samples/dma_afu A10_RTL_AFU/v1.2.1 30 | 31 | # Compile RTL code into FPGA bitstream 32 | cd A10_RTL_AFU/v1.2.1/dma_afu 33 | printf "\\n%s\\n" "Compiling FPGA bitstream:" 34 | afu_synth_setup --source hw/rtl/filelist.txt build_synth 35 | # Run compilation command (this takes approximately 40 minutes) 36 | cd build_synth 37 | $OPAE_PLATFORM_ROOT/bin/run.sh 38 | error_check 39 | 40 | # Convert .gbs file to an unsigned .gbs 41 | printf "\\n%s\\n" "Converting to unsigned .gbs:" 42 | printf "Y\\nY\\n" | PACSign PR -t UPDATE -H openssl_manager -i dma_afu.gbs -o dma_afu_compile_unsigned.gbs 43 | error_check 44 | 45 | # Availavility of PCI Accelerator cards 46 | printf "\\n%s\\n" "Accelerator Cards:" 47 | lspci | grep accel 48 | 49 | # Download bitstream into PAC Card 50 | printf "\\n%s\\n" "Downloading bitstream:" 51 | fpgasupdate dma_afu_compile_unsigned.gbs 52 | error_check 53 | # Compile host software (this takes approximately 10 minutes) 54 | cd ../sw 55 | make clean 56 | make 57 | ./fpga_dma_test 0 58 | error_check 59 | -------------------------------------------------------------------------------- /main/QuickStartGuides/RTL_AFU_Program_PAC_Quickstart/Arria10/A10_v1.2_rtl_batch.sh: -------------------------------------------------------------------------------- 1 | # Copyright 2020 Intel Corporation 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated 4 | # documentation files (the "Software"), to deal in the Software without restriction, including without limitation 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, 6 | # and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 7 | # The above copyright notice and this permission notice shall be included in all copies or substantial portions 8 | # of the Software. 9 | # 10 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 11 | # TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 12 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 13 | # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 14 | # DEALINGS IN THE SOFTWARE. 15 | 16 | ########################################################################################################## 17 | # The following flow assumes A10_RTL_AFU directory doesn't exist and sample design hasn't been copied over 18 | # Arria 10 Devstack version 1.2 19 | # **Adjust commands to your own needs.** 20 | ########################################################################################################## 21 | 22 | # Initial Setup 23 | source /data/intel_fpga/devcloudLoginToolSetup.sh 24 | tools_setup -t A10DS 25 | # Job will exit if directory already exists; no overwrite. No error message. 26 | [ ! -d ~/A10_RTL_AFU/v1.2 ] && mkdir -p ~/A10_RTL_AFU/v1.2 || exit 0 27 | 28 | # Copy Over sample design 29 | cp -r $OPAE_PLATFORM_ROOT/hw/samples/dma_afu A10_RTL_AFU/v1.2 30 | 31 | # Compile RTL code into FPGA bitstream 32 | cd A10_RTL_AFU/v1.2/dma_afu 33 | printf "\\n%s\\n" "Compiling FPGA bitstream:" 34 | afu_synth_setup --source hw/rtl/filelist.txt build_synth 35 | # Run compilation command (this takes approximately 40 minutes) 36 | cd build_synth 37 | $OPAE_PLATFORM_ROOT/bin/run.sh 38 | error_check 39 | 40 | # Availavility of PCI Accelerator cards 41 | lspci | grep accel 42 | 43 | # Download bitstream into PAC Card 44 | printf "\\n%s\\n" "Downloading bitstream:" 45 | fpgaconf -B 0x3b dma_afu.gbs 46 | error_check 47 | # Compile host software (this takes approximately 10 minutes) 48 | cd ../sw 49 | make clean 50 | make 51 | ./fpga_dma_test 0 52 | error_check 53 | -------------------------------------------------------------------------------- /main/QuickStartGuides/RTL_AFU_Program_PAC_Quickstart/Stratix10/S10_rtl_batch.sh: -------------------------------------------------------------------------------- 1 | # Copyright 2020 Intel Corporation 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated 4 | # documentation files (the "Software"), to deal in the Software without restriction, including without limitation 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, 6 | # and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 7 | # The above copyright notice and this permission notice shall be included in all copies or substantial portions 8 | # of the Software. 9 | # 10 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 11 | # TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 12 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 13 | # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 14 | # DEALINGS IN THE SOFTWARE. 15 | 16 | ########################################################################################################## 17 | # The following flow assumes S10_RTL_AFU directory doesn't exist and sample design hasn't been copied over 18 | # **Adjust commands to your own needs.** 19 | ########################################################################################################## 20 | 21 | # Initial Setup 22 | source /data/intel_fpga/devcloudLoginToolSetup.sh 23 | tools_setup -t S10DS 24 | # Job will exit if directory already exists; no overwrite. No error message. 25 | [ ! -d ~/S10_RTL_AFU ] && mkdir -p ~/S10_RTL_AFU || exit 0 26 | 27 | # Copy Over sample design 28 | cp -r $OPAE_PLATFORM_ROOT/hw/samples/dma_afu S10_RTL_AFU 29 | 30 | # Compile RTL code into FPGA bitstream 31 | cd S10_RTL_AFU/dma_afu 32 | printf "\\n%s\\n" "Compiling FPGA bitstream:" 33 | afu_synth_setup --source hw/rtl/filelist.txt build_synth 34 | # Run compilation command (this takes approximately 1 hour) 35 | cd build_synth 36 | $OPAE_PLATFORM_ROOT/bin/run.sh 37 | error_check 38 | 39 | # Availavility of PCI Accelerator cards 40 | lspci | grep accel 41 | 42 | # Download bitstream into PAC Card 43 | printf "\\n%s\\n" "Downloading bitstream:" 44 | fpgasupdate dma_afu_S10.gbs 3b:00.0 45 | error_check 46 | # Compile host software 47 | cd ../sw 48 | make clean 49 | make 50 | ./fpga_dma_test -s 104857600 -p 1048576 -r mtom 51 | error_check 52 | -------------------------------------------------------------------------------- /main/QuickStartGuides/RTL_DE_board_Quickstart/RTL_Quickstart_source_files.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/RTL_DE_board_Quickstart/RTL_Quickstart_source_files.zip -------------------------------------------------------------------------------- /main/QuickStartGuides/RTL_DE_board_Quickstart/RTL__DE_board_Quickstart.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/RTL_DE_board_Quickstart/RTL__DE_board_Quickstart.pdf -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/Disclaimer.txt: -------------------------------------------------------------------------------- 1 | The software, tutorial and any accompanying documentation (“Materials”) are provided “as is” with no warranties of any kind, whether written, oral, implied or statutory, including warranties of merchantability or fitness for a particular purpose, non-infringement or arising from course of dealing or usage in trade. 2 | 3 | These Materials contain the general insights and opinions of Intel Corporation (“Intel”). The information in these Materials are provided for information only and are not to be relied upon for any other purpose than educational. Intel makes no representations or warranties regarding the accuracy or completeness of the information in this Material. Intel accepts no duty to update this Material based on more current information. Intel is not liable for any damages, direct or indirect, consequential or otherwise, that may arise, directly or indirectly, from the use or misuse of the information in this Material. 4 | 5 | -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/README.md: -------------------------------------------------------------------------------- 1 | # Using T2S on FPGA DevCloud 2 | 3 | T2S enables software programmers to build systolic arrays on Intel FPGAs for both productivity and performance. A binary of the tool, together with a set of tutorials, is freely available on Intel FPGA DevCloud. DevCloud provides a well-maintained software and hardware environment, making it really convenient for programmers. 4 | 5 | ## Create a DevCloud account 6 | 7 | + Register at [DevCloud](https://software.intel.com/content/www/us/en/develop/tools/devcloud/fpga.html). In "Which software tools do you intend to use with your project?", please check "Other", and indicate "T2S" in the describe box. 8 | + Follow the instructions of an approval email to set up your connection to DevCloud. 9 | 10 | ## Log in 11 | 12 | + log into a compute node: 13 | 14 | ``` 15 | devcloud_login 16 | ``` 17 | 18 | + Choose 19 | 20 | ``` 21 | 6) Enter Specific Node Number 22 | Choose a node with Arria 10 Release 1.2.1, or with Stratix 10. 23 | ``` 24 | 25 | ## Use tutorials 26 | 27 | + Create a directory. 28 | This directory will contain all temporary files (e.g. OpenCL files, bitstreams) generated when running any command in a tutorial. For example, 29 | ``` 30 | mkdir tutorials 31 | ``` 32 | + Set up environment 33 | 34 | ``` 35 | cd tutorials 36 | source /data/t2s/setenv.sh 37 | ``` 38 | 39 | + Play with a tutorial. 40 | 41 | + [Tutorial 1: Matrix multiply](tutorials/fpga/matrix-multiply/README.md) 42 | + [Tutorial 2: Capsule kernel](tutorials/fpga/capsule/README.md) 43 | + [Tutorial 3: PairHMM](tutorials/fpga/pairhmm/README.md) 44 | + [Tutorial 4: LU decomposition](tutorials/fpga/lu/README.md) 45 | + [Tutorial 5: Convolution](tutorials/fpga/2d-convolution/README.md) 46 | 47 | 48 | Usually, each tutorial starts from a simplest design, and evolves into a more sophisticated design step by step, every step addressing a visible performance bottleneck. Some tutorials might have been tried on A10 or S10 but not both. 49 | 50 | 51 | ## Contact us 52 | 53 | We would love to hear your feedback. Please feel free to contact us: Hongbo Rong (hongbo.rong@intel.com), Mingzhe Zhang (zhangmz1210@mail.ustc.edu.cn), and Xiaochen Hao (xiaochen.hao@intel.com). -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/2d-convolution/basic/figures/formula.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/T2S/tutorials/fpga/2d-convolution/basic/figures/formula.png -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/2d-convolution/basic/run.sh: -------------------------------------------------------------------------------- 1 | set -x 2 | THIS_TUTORIAL_PATH="$( cd "$(dirname $(realpath "$BASH_SOURCE") )" >/dev/null 2>&1 ; pwd -P )" # The path to this script 3 | 4 | # Purge any previously generated files 5 | rm -rf $CODE_STORE_DIR/a.* $CODE_STORE_DIR/a 6 | 7 | # Compile and run 8 | if [ $1 = "emulator" ]; then 9 | g++ $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS -o $CODE_STORE_DIR/a.out 10 | env INTEL_FPGA_OCL_PLATFORM_NAME="$EMULATOR_PLATFORM_NAME" CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 CL_CONFIG_CHANNEL_DEPTH_EMULATION_MODE=strict BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-march=emulator -board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 11 | else 12 | g++ $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS $AOCL_LIBS -o $CODE_STORE_DIR/a.out 13 | env INTEL_FPGA_OCL_PLATFORM_NAME="$HW_RUN_PLATFORM_NAME" BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 14 | fi 15 | -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/2d-convolution/io/run.sh: -------------------------------------------------------------------------------- 1 | set -x 2 | THIS_TUTORIAL_PATH="$( cd "$(dirname $(realpath "$BASH_SOURCE") )" >/dev/null 2>&1 ; pwd -P )" # The path to this script 3 | 4 | # Purge any previously generated files 5 | rm -rf $CODE_STORE_DIR/a.* $CODE_STORE_DIR/a 6 | 7 | # Compile and run 8 | if [ $1 = "emulator" ]; then 9 | g++ -DVERBOSE_DEBUG $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS -o $CODE_STORE_DIR/a.out 10 | env PRAGMAUNROLL=1 INTEL_FPGA_OCL_PLATFORM_NAME="$EMULATOR_PLATFORM_NAME" CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 CL_CONFIG_CHANNEL_DEPTH_EMULATION_MODE=strict BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-march=emulator -board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 11 | else 12 | g++ -DVERBOSE_DEBUG $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS $AOCL_LIBS -o $CODE_STORE_DIR/a.out 13 | env INTEL_FPGA_OCL_PLATFORM_NAME="$HW_RUN_PLATFORM_NAME" BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 14 | fi 15 | -------------------------------------------------------------------------------- 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CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 CL_CONFIG_CHANNEL_DEPTH_EMULATION_MODE=strict BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-march=emulator -board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 11 | else 12 | g++ -DVERBOSE_DEBUG $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS $AOCL_LIBS -o $CODE_STORE_DIR/a.out 13 | env INTEL_FPGA_OCL_PLATFORM_NAME="$HW_RUN_PLATFORM_NAME" BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 14 | fi 15 | -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/2d-convolution/stt/figures/conv.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/T2S/tutorials/fpga/2d-convolution/stt/figures/conv.gif -------------------------------------------------------------------------------- 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INTEL_FPGA_OCL_PLATFORM_NAME="$EMULATOR_PLATFORM_NAME" CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 CL_CONFIG_CHANNEL_DEPTH_EMULATION_MODE=strict BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-march=emulator -board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 11 | else 12 | g++ -DVERBOSE_DEBUG $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS $AOCL_LIBS -o $CODE_STORE_DIR/a.out 13 | env INTEL_FPGA_OCL_PLATFORM_NAME="$HW_RUN_PLATFORM_NAME" BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 14 | fi 15 | -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/2d-convolution/tiling-vec/run.sh: -------------------------------------------------------------------------------- 1 | set -x 2 | THIS_TUTORIAL_PATH="$( cd "$(dirname $(realpath "$BASH_SOURCE") )" >/dev/null 2>&1 ; pwd -P )" # The path to this script 3 | 4 | # Purge any previously generated files 5 | rm -rf $CODE_STORE_DIR/a.* $CODE_STORE_DIR/a 6 | 7 | # Compile and run 8 | if [ $1 = "emulator" ]; then 9 | g++ -DVERBOSE_DEBUG $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS -o $CODE_STORE_DIR/a.out 10 | env PRAGMAUNROLL=1 INTEL_FPGA_OCL_PLATFORM_NAME="$EMULATOR_PLATFORM_NAME" CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 CL_CONFIG_CHANNEL_DEPTH_EMULATION_MODE=strict BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-march=emulator -board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 11 | else 12 | g++ -DVERBOSE_DEBUG $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS $AOCL_LIBS -o $CODE_STORE_DIR/a.out 13 | env INTEL_FPGA_OCL_PLATFORM_NAME="$HW_RUN_PLATFORM_NAME" BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 14 | fi 15 | -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/capsule/basic/figures/capsule-formula.png: -------------------------------------------------------------------------------- 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)" # The path to this script 3 | 4 | # Purge any previously generated files 5 | rm -rf $CODE_STORE_DIR/a.* $CODE_STORE_DIR/a 6 | 7 | # Compile and run 8 | if [ $1 = "emulator" ]; then 9 | g++ $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS -o $CODE_STORE_DIR/a.out 10 | env INTEL_FPGA_OCL_PLATFORM_NAME="$EMULATOR_PLATFORM_NAME" CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 CL_CONFIG_CHANNEL_DEPTH_EMULATION_MODE=strict BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-march=emulator -board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 11 | else 12 | g++ $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS $AOCL_LIBS -o $CODE_STORE_DIR/a.out 13 | env INTEL_FPGA_OCL_PLATFORM_NAME="$HW_RUN_PLATFORM_NAME" BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 14 | fi 15 | -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/lu/batch/profile/Ostall0.png: -------------------------------------------------------------------------------- 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INTEL_FPGA_OCL_PLATFORM_NAME="$EMULATOR_PLATFORM_NAME" CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 CL_CONFIG_CHANNEL_DEPTH_EMULATION_MODE=strict BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-march=emulator -board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 11 | else 12 | g++ $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS $AOCL_LIBS -o $CODE_STORE_DIR/a.out 13 | env INTEL_FPGA_OCL_PLATFORM_NAME="$HW_RUN_PLATFORM_NAME" BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 14 | fi 15 | -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/lu/io/figures/lu-io.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/T2S/tutorials/fpga/lu/io/figures/lu-io.png -------------------------------------------------------------------------------- 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else 12 | g++ $THIS_TUTORIAL_PATH/../host.cpp -g -DSIZE=8 -DBB=1 -DB=1 -DLINUX -DALTERA_CL -fPIC -I$INTELFPGAOCLSDKROOT/examples_aoc/common/inc $INTELFPGAOCLSDKROOT/examples_aoc/common/src/AOCLUtils/opencl.cpp $INTELFPGAOCLSDKROOT/examples_aoc/common/src/AOCLUtils/options.cpp -I$INTELFPGAOCLSDKROOT/host/include $AOCL_LIBS -lelf -o host.out 13 | env BITSTREAM="bitstream/lu-io.aocx" ./host.out 14 | fi 15 | -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/lu/vectorize/profile/Ostall.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/T2S/tutorials/fpga/lu/vectorize/profile/Ostall.png -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/lu/vectorize/profile/bandwidth.png: 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The path to this script 3 | 4 | # Purge any previously generated files 5 | rm -rf $CODE_STORE_DIR/a.* $CODE_STORE_DIR/a 6 | 7 | # Compile and run 8 | if [ $1 = "emulator" ]; then 9 | g++ $THIS_TUTORIAL_PATH/main.cpp $CXX_FLAGS -o $CODE_STORE_DIR/a.out 10 | env INTEL_FPGA_OCL_PLATFORM_NAME="$EMULATOR_PLATFORM_NAME" CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 CL_CONFIG_CHANNEL_DEPTH_EMULATION_MODE=strict BITSTREAM=$CODE_STORE_DIR/a.aocx AOC_OPTION="-march=emulator -board=$FPGA_BOARD" $CODE_STORE_DIR/a.out 11 | else 12 | g++ $THIS_TUTORIAL_PATH/../host.cpp -g -DSIZE=8 -DBB=16 -DB=32768 -DLINUX -DALTERA_CL -fPIC -I$INTELFPGAOCLSDKROOT/examples_aoc/common/inc $INTELFPGAOCLSDKROOT/examples_aoc/common/src/AOCLUtils/opencl.cpp $INTELFPGAOCLSDKROOT/examples_aoc/common/src/AOCLUtils/options.cpp -I$INTELFPGAOCLSDKROOT/host/include $AOCL_LIBS -lelf -o host.out 13 | env BITSTREAM="bitstream/lu-vec.aocx" ./host.out 14 | fi 15 | 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-------------------------------------------------------------------------------- 1 | // The only header file needed for including T2S. 2 | #include "Halide.h" 3 | 4 | // For printing output 5 | #include 6 | 7 | // For validation of results. 8 | #include 9 | 10 | using namespace Halide; 11 | using namespace std; 12 | 13 | // Input matrices: A(K, I) and B(J, K). Following Halide's convention, they are in column-major format. 14 | #define I 1024 15 | #define J 1024 16 | #define K 256 17 | 18 | // Input parameters: a and b are 2D float32 matrices. 19 | #define TYPE Float(32) 20 | ImageParam a("a", TYPE, 2); 21 | ImageParam b("b", TYPE, 2); 22 | 23 | // Implementation of the compute. 24 | Func matrix_multiply() { 25 | // Loop variables 26 | Var k("k"), j("j"), i("i"); 27 | 28 | // UREs. All are recursive functions, and need signatures to be declared. An exception is c, the function 29 | // for the final results, which is not really a recursive Func, and declaring its place is enough. 30 | Func A("A", TYPE, {k, j, i}, Place::Device), // Name (optional), return type, arguments and Place. 31 | B("B", TYPE, {k, j, i}, Place::Device), 32 | C("C", TYPE, {k, j, i}, Place::Device), 33 | c("c", Place::Device); 34 | 35 | // Recursively compute. 36 | A(k, j, i) = select(j == 0, a(k, i), A(k, j - 1, i)); 37 | B(k, j, i) = select(i == 0, b(j, k), B(k, j, i - 1)); 38 | C(k, j, i) = select(k == 0, 0, C(k - 1, j, i)) + A(k, j, i) * B(k, j, i); 39 | 40 | // Take the final output 41 | c(j, i) = select(k == K - 1, C(k, j, i)); 42 | 43 | // Put all the UREs inside the same loop nest. Now the first URE (A) represents all the UREs. 44 | A.merge_ures(B, C, c); 45 | 46 | // Explicitly set the loop bounds 47 | A.set_bounds(k, 0, K, j, 0, J, i, 0, I); 48 | 49 | 50 | // Return the (unique) output func. Compiler will be able to find other functions from it. 51 | return c; 52 | } 53 | 54 | int main() { 55 | // Step 1: Set input. Random data here for example: 56 | Buffer ina(K, I), inb(J, K); 57 | for (size_t i = 0; i < I; i++) { 58 | for (size_t k = 0; k < K; k++) { 59 | ina(k, i) = k + i; 60 | } 61 | } 62 | for (size_t k = 0; k < K; k++) { 63 | for (size_t j = 0; j < J; j++) { 64 | inb(j, k) = j - k; 65 | } 66 | } 67 | // Set the input parameter a/b as the actual input ina/inb. 68 | a.set(ina); 69 | b.set(inb); 70 | 71 | // Step 2: Run 72 | Target target = get_host_target(); // Get the CPU host 73 | target.set_feature(Target::IntelFPGA); // To execute on an Intel FPGA device attached to the host. 74 | Func mm = matrix_multiply(); // Get the compute. 75 | 76 | #ifdef COMPILE_ONLY 77 | mm.compile_jit(target); 78 | #else 79 | // Invoke the T2S compiler to compile and offload the compute to the FPGA. Copy the result back to the host. 80 | Buffer result(J, I); 81 | mm.realize(result, target); 82 | result.copy_to_host(); 83 | 84 | // Step 3: Validate the results 85 | for (size_t i = 0; i < I; i++) { 86 | for (size_t j = 0; j < J; j++) { 87 | float golden = 0.0f; 88 | for (size_t k = 0; k < K; k++) { 89 | golden += ina(k, i) * inb(j, k); 90 | } 91 | assert(fabs(golden - result(j, i)) < 0.005*fabs(golden)); 92 | } 93 | } 94 | #endif 95 | cout << "Success!\n"; 96 | return 0; 97 | } 98 | 99 | 100 | 101 | -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/matrix-multiply/final/figures/matrix-multiply-final-design-animation.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/T2S/tutorials/fpga/matrix-multiply/final/figures/matrix-multiply-final-design-animation.gif -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/matrix-multiply/final/figures/matrix-multiply-final-design-animation.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/T2S/tutorials/fpga/matrix-multiply/final/figures/matrix-multiply-final-design-animation.pptx -------------------------------------------------------------------------------- /main/QuickStartGuides/T2S/tutorials/fpga/matrix-multiply/host-files/README.md: -------------------------------------------------------------------------------- 1 | These host files are to work around a bug in Halide OpenCL runtime when running on DevCloud. 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KKK 2 11 | 12 | // Testing purpose only: help define the sizes of test inputs 13 | // matrix a: 64 * 64 14 | // matrix b: 64 * 64 15 | #define OUTERMOST_I 8 16 | #define OUTERMOST_J 8 17 | #define OUTERMOST_K 8 18 | #endif 19 | 20 | 21 | #ifdef SMALL 22 | #define II 4 23 | #define JJ 4 24 | #define KK 256 25 | #define III 2 26 | #define JJJ 4 27 | #define KKK 4 28 | 29 | // Testing purpose only: help define the sizes of test inputs 30 | // matrix a: 2K * 4K 31 | // matrix b: 4K * 2K 32 | #define OUTERMOST_I 256 33 | #define OUTERMOST_J 128 34 | #define OUTERMOST_K 4 35 | #endif 36 | 37 | #ifdef MEDIUM 38 | #define II 32 39 | #define JJ 32 40 | #define KK 32 41 | #define III 8 42 | #define JJJ 8 43 | #define KKK 8 44 | 45 | // Testing purpose only: help define the sizes of test inputs 46 | // matrix a: 2K * 4K 47 | // matrix b: 4K * 2K 48 | #define OUTERMOST_I 8 49 | #define OUTERMOST_J 8 50 | #define OUTERMOST_K 16 51 | #endif 52 | 53 | #ifdef LARGE 54 | #define II 32 55 | #define JJ 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set_location_assignment PIN_C1 -to LEDG[6] 5 | set_location_assignment PIN_E1 -to LEDG[5] 6 | set_location_assignment PIN_F2 -to LEDG[4] 7 | set_location_assignment PIN_H1 -to LEDG[3] 8 | set_location_assignment PIN_J3 -to LEDG[2] 9 | set_location_assignment PIN_J2 -to LEDG[1] 10 | set_location_assignment PIN_J1 -to LEDG[0] 11 | set_location_assignment PIN_D2 -to SW[9] 12 | set_location_assignment PIN_E4 -to SW[8] 13 | set_location_assignment PIN_E3 -to SW[7] 14 | set_location_assignment PIN_H7 -to SW[6] 15 | set_location_assignment PIN_J7 -to SW[5] 16 | set_location_assignment PIN_G5 -to SW[4] 17 | set_location_assignment PIN_G4 -to SW[3] 18 | set_location_assignment PIN_H6 -to SW[2] 19 | set_location_assignment PIN_H5 -to SW[1] 20 | set_location_assignment PIN_J6 -to SW[0] 21 | set_location_assignment PIN_G21 -to CLOCK_50 22 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE0_CycloneIII/knight_rider.v: -------------------------------------------------------------------------------- 1 | module knight_rider( input wire CLOCK_50, 2 | output wire [9:0] LEDR 3 | ); 4 | wire slow_clock; 5 | reg [3:0] count; 6 | reg count_up; 7 | 8 | clock_divider u0 (.fast_clock(CLOCK_50),.slow_clock(slow_clock)); 9 | 10 | always @ (posedge slow_clock) begin 11 | if (count_up) 12 | count <= count + 1'b1 13 | else 14 | count <= count - 1'b1; 15 | end 16 | 17 | always @ (posedge slow_clock) begin 18 | if (count == 9) 19 | count_up <= 1'b0; 20 | else if (count == 0) 21 | count_up <= 1'b1; 22 | else 23 | count_up <= count_up; 24 | end 25 | 26 | assign LEDR[9:0] = (1'b1 << count); 27 | 28 | endmodule 29 | 30 | module clock_divider( input fast_clock, output slow_clock); 31 | parameter COUNTER_SIZE = 5; 32 | parameter COUNTER_MAX_COUNT = (2 ** COUNTER_SIZE) - 1; 33 | reg [COUNTER_SIZE-1:0] count; 34 | 35 | always @(posedge fast_clock) begin 36 | if(count==COUNTER_MAX_COUNT) 37 | count <= 0; 38 | else 39 | count<=count + 1'b1; 40 | end 41 | 42 | assign slow_clock = count[COUNTER_SIZE-1]; 43 | 44 | endmodule 45 | 46 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE0_CycloneIII/mux_2_to_1.v: -------------------------------------------------------------------------------- 1 | module mux_2_to_1 (SW, LEDR); //Create module mux_2_to_1 2 | input [9:0]SW; //Input Declarations: 10 slide switches 3 | output[9:0]LEDR; //Output Declarations: 10 red LED lights 4 | wire S; //Declare the Select signal 5 | wire [2:0] X, Y, M; //Declare the inputs and outputs to the MUX 6 | assign S = SW[9]; //Assigning input switches to internal signals 7 | assign X = SW[2:0]; 8 | assign Y = SW[5:3]; 9 | assign LEDR[8:6] = M; //Assigning internal signals to output LEDs 10 | assign LEDR[9] = SW[9]; 11 | assign LEDR[2:0] = SW[2:0]; 12 | assign LEDR[5:3] = SW[5:3]; 13 | assign M = (S == 0) ? X : Y; //MuxSelect Function 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE0_CycloneIII/switch_to_led.v: -------------------------------------------------------------------------------- 1 | module switch_to_led(SW, LEDR); //create module switch_to_led 2 | input [9:0] SW; // input declarations: 10 switches 3 | output [9:0] LEDR; // output declarations: 10 red LEDs 4 | assign LEDR = SW; // connect switches to LEDs 5 | endmodule 6 | 7 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/DE10_Lite_files.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Intro_DE10_Lite/DE10_Lite_files.zip -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/.knight_rider.v.swp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/.knight_rider.v.swp -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/DE0_CV_pins.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_AA2 -to LEDR[0] 2 | set_location_assignment PIN_AA1 -to LEDR[1] 3 | set_location_assignment PIN_Y2 -to LEDR[2] 4 | set_location_assignment PIN_Y3 -to LEDR[3] 5 | set_location_assignment PIN_N2 -to LEDR[4] 6 | set_location_assignment PIN_N1 -to LEDR[5] 7 | set_location_assignment PIN_U2 -to LEDR[6] 8 | set_location_assignment PIN_U1 -to LEDR[7] 9 | set_location_assignment PIN_L2 -to LEDR[8] 10 | set_location_assignment PIN_L1 -to LEDR[9] 11 | set_location_assignment PIN_U13 -to SW[0] 12 | set_location_assignment PIN_V13 -to SW[1] 13 | set_location_assignment PIN_T13 -to SW[2] 14 | set_location_assignment PIN_T12 -to SW[3] 15 | set_location_assignment PIN_AA15 -to SW[4] 16 | set_location_assignment PIN_AB15 -to SW[5] 17 | set_location_assignment PIN_AA14 -to SW[6] 18 | set_location_assignment PIN_AA13 -to SW[7] 19 | set_location_assignment PIN_AB13 -to SW[8] 20 | set_location_assignment PIN_AB12 -to SW[9] -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/DE10_Lite_pins.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_A8 -to LEDR[0] 2 | set_location_assignment PIN_A9 -to LEDR[1] 3 | set_location_assignment PIN_A10 -to LEDR[2] 4 | set_location_assignment PIN_B10 -to LEDR[3] 5 | set_location_assignment PIN_D13 -to LEDR[4] 6 | set_location_assignment PIN_C13 -to LEDR[5] 7 | set_location_assignment PIN_E14 -to LEDR[6] 8 | set_location_assignment PIN_D14 -to LEDR[7] 9 | set_location_assignment PIN_A11 -to LEDR[8] 10 | set_location_assignment PIN_B11 -to LEDR[9] 11 | set_location_assignment PIN_C10 -to SW[0] 12 | set_location_assignment PIN_C11 -to SW[1] 13 | set_location_assignment PIN_D12 -to SW[2] 14 | set_location_assignment PIN_C12 -to SW[3] 15 | set_location_assignment PIN_A12 -to SW[4] 16 | set_location_assignment PIN_B12 -to SW[5] 17 | set_location_assignment PIN_A13 -to SW[6] 18 | set_location_assignment PIN_A14 -to SW[7] 19 | set_location_assignment PIN_B14 -to SW[8] 20 | set_location_assignment PIN_F15 -to SW[9] -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/DE10_Lite_pins.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/DE10_Lite_pins.zip -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/knight_rider.v: -------------------------------------------------------------------------------- 1 | module knight_rider( 2 | input wire CLOCK_50, 3 | output wire [9:0] LEDR 4 | ); 5 | wire slow_clock; 6 | 7 | reg [3:0] count; 8 | reg count_up; 9 | 10 | clock_divider u0 (.fast_clock(CLOCK_50),.slow_clock(slow_clock)); 11 | 12 | always @ (posedge slow_clock) 13 | begin 14 | if (count_up) 15 | count <= count + 1'b1 16 | else 17 | count <= count - 1'b1; 18 | end 19 | 20 | always @ (posedge clk) 21 | begin 22 | if (count == 9) 23 | count_up <= 1'b0; 24 | else if (count == 0) 25 | count_up <= 1'b1; 26 | else 27 | count_up <= count_up; 28 | end 29 | 30 | assign LEDR[9:0] = (1'b1 << count); 31 | 32 | endmodule 33 | 34 | 35 | module clock_divider( 36 | input fast_clock, 37 | output slow_clock 38 | ); 39 | 40 | parameter COUNTER_SIZE = 5; 41 | parameter COUNTER_MAX_COUNT = (2 ** COUNTER_SIZE) - 1; 42 | 43 | reg [COUNTER_SIZE-1:0] count; 44 | 45 | always @(posedge fast_clock) 46 | begin 47 | if(count==COUNTER_MAX_COUNT) 48 | count <= 0; 49 | else 50 | count<=count + 1'b1; 51 | end 52 | 53 | assign slow_clock = count[COUNTER_SIZE-1]; 54 | 55 | endmodule -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/mux_2_to_1.v: -------------------------------------------------------------------------------- 1 | module mux_2_to_1 (SW, LEDR);//Create module mux_2_to_1 2 | 3 | input [9:0]SW; //Input Declarations: 10 slide switches 4 | output[9:0]LEDR; //Output Declarations: 10 red LED lights 5 | 6 | wire S; //Declare the Select signal 7 | wire [2:0] X, Y, M; //Declare the inputs and outputs to the MUX 8 | 9 | assign S = SW[9]; //Assigning input switches to internal signals 10 | assign X = SW[2:0]; 11 | assign Y = SW[5:3]; 12 | 13 | assign LEDR[8:6] = M; //Assigning internal signals to output LEDs 14 | assign LEDR[9] = SW[9]; 15 | assign LEDR[2:0] = SW[2:0]; 16 | assign LEDR[5:3] = SW[5:3]; 17 | 18 | assign M = (S == 0) ? X : Y; //Mux Select Function 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/mux_snippet_case.v: -------------------------------------------------------------------------------- 1 | always @ (S or X or Y) begin case (S): 2 | 1’b0: M <= X; 3 | 1’b1: M <= Y; 4 | endcase end 5 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/mux_snippet_continuous.v: -------------------------------------------------------------------------------- 1 | assign M = (S==1) ? Y : X; // if S then M = Y else M = X; AlL signals are of type wire. -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/mux_snippet_if.v: -------------------------------------------------------------------------------- 1 | always @ (S or X or Y) begin // If any of the signals S, X or Y 2 | // change state, execute this code. 3 | // Note that signals to the left of an 4 | // equal sign in an always block 5 | // need to be declared of type reg so 6 | // declare M as: 7 | // output reg [2:0] M; 8 | if(S == 1) 9 | M <= Y; //Note the non-blocking operator ‘<=’ 10 | else 11 | M <= X; 12 | end 13 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Design Files/switch_to_led.v: -------------------------------------------------------------------------------- 1 | module switch_to_led(SW, LEDR); //create module Switch_to_LED 2 | 3 | input [9:0] SW; // input declarations: 10 switches 4 | output [9:0] LEDR; // output declarations: 10 red LEDs 5 | assign LEDR = SW; // connect switches to LEDs 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE10_Lite/Intro_to_FPGA.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Intro_DE10_Lite/Intro_to_FPGA.pdf -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE1_SoC_Labsland/DE1_SOC_pins.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_Y21 -to LEDR[9] 2 | set_location_assignment PIN_W21 -to LEDR[8] 3 | set_location_assignment PIN_W20 -to LEDR[7] 4 | set_location_assignment PIN_Y19 -to LEDR[6] 5 | set_location_assignment PIN_W19 -to LEDR[5] 6 | set_location_assignment PIN_W17 -to LEDR[4] 7 | set_location_assignment PIN_V18 -to LEDR[3] 8 | set_location_assignment PIN_V17 -to LEDR[2] 9 | set_location_assignment PIN_W16 -to LEDR[1] 10 | set_location_assignment PIN_V16 -to LEDR[0] 11 | set_location_assignment PIN_AF16 -to SW[9] 12 | set_location_assignment PIN_AE16 -to SW[8] 13 | set_location_assignment PIN_AG16 -to SW[7] 14 | set_location_assignment PIN_AH17 -to SW[6] 15 | set_location_assignment PIN_AH18 -to SW[5] 16 | set_location_assignment PIN_AJ16 -to SW[4] 17 | set_location_assignment PIN_AJ17 -to SW[3] 18 | set_location_assignment PIN_AJ19 -to SW[2] 19 | set_location_assignment PIN_AK19 -to SW[1] 20 | set_location_assignment PIN_AK18 -to SW[0] 21 | set_location_assignment PIN_AF14 -to CLOCK_50 22 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE1_SoC_Labsland/IntroLab_RemoteBoard_Labsland.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Intro_DE1_SoC_Labsland/IntroLab_RemoteBoard_Labsland.pdf -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE1_SoC_Labsland/Intro_Lecture_Slides_Labsland.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Intro_DE1_SoC_Labsland/Intro_Lecture_Slides_Labsland.pdf -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE1_SoC_Labsland/knight_rider.v: -------------------------------------------------------------------------------- 1 | module knight_rider( input wire CLOCK_50, 2 | output wire [9:0] LEDR 3 | ); 4 | wire slow_clock; 5 | reg [3:0] count; 6 | reg count_up; 7 | 8 | clock_divider u0 (.fast_clock(CLOCK_50),.slow_clock(slow_clock)); 9 | 10 | always @ (posedge slow_clock) begin 11 | if (count_up) 12 | count <= count + 1'b1 13 | else 14 | count <= count - 1'b1; 15 | end 16 | 17 | always @ (posedge slow_clock) begin 18 | if (count == 9) 19 | count_up <= 1'b0; 20 | else if (count == 0) 21 | count_up <= 1'b1; 22 | else 23 | count_up <= count_up; 24 | end 25 | 26 | assign LEDR[9:0] = (1'b1 << count); 27 | 28 | endmodule 29 | 30 | module clock_divider( input fast_clock, output slow_clock); 31 | parameter COUNTER_SIZE = 5; 32 | parameter COUNTER_MAX_COUNT = (2 ** COUNTER_SIZE) - 1; 33 | reg [COUNTER_SIZE-1:0] count; 34 | 35 | always @(posedge fast_clock) begin 36 | if(count==COUNTER_MAX_COUNT) 37 | count <= 0; 38 | else 39 | count<=count + 1'b1; 40 | end 41 | 42 | assign slow_clock = count[COUNTER_SIZE-1]; 43 | 44 | endmodule 45 | 46 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE1_SoC_Labsland/mux_2_to_1.v: -------------------------------------------------------------------------------- 1 | module mux_2_to_1 (SW, LEDR); //Create module mux_2_to_1 2 | input [9:0]SW; //Input Declarations: 10 slide switches 3 | output[9:0]LEDR; //Output Declarations: 10 red LED lights 4 | wire S; //Declare the Select signal 5 | wire [2:0] X, Y, M; //Declare the inputs and outputs to the MUX 6 | assign S = SW[9]; //Assigning input switches to internal signals 7 | assign X = SW[2:0]; 8 | assign Y = SW[5:3]; 9 | assign LEDR[8:6] = M; //Assigning internal signals to output LEDs 10 | assign LEDR[9] = SW[9]; 11 | assign LEDR[2:0] = SW[2:0]; 12 | assign LEDR[5:3] = SW[5:3]; 13 | assign M = (S == 0) ? X : Y; //MuxSelect Function 14 | endmodule 15 | 16 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_DE1_SoC_Labsland/switch_to_led.v: -------------------------------------------------------------------------------- 1 | module switch_to_led(SW, LEDR); //create module switch_to_led 2 | input [9:0] SW; // input declarations: 10 switches 3 | output [9:0] LEDR; // output declarations: 10 red LEDs 4 | assign LEDR = SW; // connect switches to LEDs 5 | endmodule 6 | 7 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_Remote/IntroLab_RemoteBoard.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Intro_Remote/IntroLab_RemoteBoard.pdf -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_Remote/Intro_Lecture_Slides_Remote.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Intro_Remote/Intro_Lecture_Slides_Remote.pdf -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_Remote/knight_rider.v: -------------------------------------------------------------------------------- 1 | module knight_rider( input wire CLOCK_50, 2 | input resetn, 3 | output wire [9:0] LEDR); 4 | wire slow_clock; 5 | reg [3:0] count; 6 | reg count_up; 7 | clock_divider u0(.fast_clock(CLOCK_50),.slow_clock(slow_clock)); 8 | always @ (posedge slow_clock or negedge resetn) 9 | begin 10 | if (~resetn) 11 | count <= 0; 12 | else if (count_up) 13 | count <= count +1'b1; 14 | else 15 | count <= count - 1'b1; 16 | end 17 | always @ (posedge slow_clock) 18 | begin 19 | if (count==9) 20 | count_up <= 1'b0; 21 | else if (count==0) 22 | count_up <= 1'b1; 23 | else 24 | count_up <= count_up; 25 | end 26 | assign LEDR[9:0] = (1'b1 << count); 27 | endmodule 28 | 29 | module clock_divider( input fast_clock, 30 | output slow_clock); 31 | parameter COUNTER_SIZE = 5; 32 | parameter COUNTER_MAX_COUNT = (2 ** COUNTER_SIZE) -1 33 | reg [COUNTER_SIZE-1:0] count; 34 | always @(posedge fast_clock) 35 | begin 36 | if(count==COUNTER_MAX_COUNT) 37 | count <= 0; 38 | else 39 | count<=count+1'b1; 40 | end 41 | assign slow_clock = count[COUNTER_SIZE-1]; 42 | endmodule 43 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_Remote/mux_2_to_1.v: -------------------------------------------------------------------------------- 1 | module mux_2_to_1(SW, LEDR); //Create module mux_2_to_1 2 | input [9:0] SW; //Input Declarations:10 slides switches 3 | output [9:0] LEDR; //Output Declarations:10 red LED lights 4 | 5 | wire S; //Declare The Selected signal 6 | wire [2:0] X,Y,M; //Declare inputs and outputs to the MUX 7 | 8 | assign S=SW[9]; //Assign input SW to internal signals 9 | assign X=SW[2:0]; 10 | assign Y=SW[5:3]; 11 | 12 | assign LEDR[8:6]=M; //Assign internal signal to output LEDs 13 | assign LEDR[9]=SW[9]; 14 | assign LEDR[2:0]=SW[2:0]; 15 | assign LEDR[5:3]=SW[5:3]; 16 | 17 | assign M=(S==0) ? X:Y; //MUXSelect Function 18 | endmodule 19 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Intro_Remote/switch_to_led.v: -------------------------------------------------------------------------------- 1 | module switch_to_led(SW, LEDR); //create module Switch_to_LED 2 | input [9:0] SW; // input declarations: 10 switches 3 | output [9:0] LEDR; // output declarations: 10 red LEDs 4 | assign LEDR = SW; // connect switches to LEDs 5 | endmodule 6 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Simulation_Debug_DE10_Lite/DE10LITE_Workshop_DebuggingTools.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Simulation_Debug_DE10_Lite/DE10LITE_Workshop_DebuggingTools.zip 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different time intervals to check the functionality of testbench */ 16 | 17 | 18 | #1000 $finish; //$finish to finish simulation or $stop to stop simulation. 19 | 20 | end 21 | 22 | always #10 clock = ~clock; //50 MHz Clock (20 ns clock period), many ways to write the clock 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Lab_1/tb_counter.v~: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps //Time precision 2 | 3 | module testbench(); 4 | 5 | //declare inputs as reg and connect to top module 6 | //declare outputs as wire and connect to top module 7 | 8 | //Instantiation of top module 9 | top t1( .refclk() , .reset_pll() ,.reset_count(), .check() , .Count_up() , .Count_down() ); 10 | 11 | initial 12 | begin 13 | //Initialize inputs as 0 14 | 15 | /* Set inputs as 1,0 after different time intervals to check the functionality of testbench */ 16 | 17 | 18 | #1000 $finish; //$finish to finish simulation or $stop to stop simulation. 19 | 20 | end 21 | 22 | always #10 clock = ~clock; //50 MHz Clock (20 ns clock period), many ways to write the clock 23 | 24 | endmodule -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Lab_2/Example_ISSP_SignalTap_CVGXStarter.qar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/FPGA-Devcloud/70168c8db033fdc7ea442af2c0308cb2c4be0220/main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Lab_2/Example_ISSP_SignalTap_CVGXStarter.qar -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Lab_2/Example_ISSP_SignalTap_DE1SoC.qar: -------------------------------------------------------------------------------- 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| end 21 | 22 | else 23 | begin 24 | 25 | delay <= delay +1; //increment delay each cycle 26 | if ((delay == 24'b100000000000000000000000) && (Ones_Counter <= 4'b1001) ) 27 | begin 28 | Ones_Counter <= Ones_Counter + 1; //increment ones_counter once delay reached its value & increment tens_counter 29 | if(Ones_Counter == 4'b1001) 30 | begin 31 | Tens_Counter<= Tens_Counter +1; 32 | end 33 | end 34 | 35 | else if(Ones_Counter > 4'b1001) //Rollover to zero 36 | Ones_Counter <= 4'b0000; 37 | 38 | else if(Tens_Counter > 4'b1001) //Rollover to zero 39 | Tens_Counter <=4'b0000; 40 | 41 | end 42 | 43 | 44 | case(Ones_Counter) //Seven Segment decoder 45 | 4'b0000: Ones_Display <= 7'b1000000; // "0" 46 | 4'b0001: Ones_Display <= 7'b1111001; // "1" 47 | 4'b0010: Ones_Display <= 7'b0100100; // "2" 48 | 4'b0011: Ones_Display <= 7'b0110000; // "3" 49 | 4'b0100: Ones_Display <= 7'b0011001; // "4" 50 | 4'b0101: Ones_Display <= 7'b0010010; // "5" 51 | 4'b0110: Ones_Display <= 7'b0000010; // "6" 52 | 4'b0111: Ones_Display <= 7'b1111000; // "7" 53 | 4'b1000: Ones_Display <= 7'b0000000; // "8" 54 | 4'b1001: Ones_Display <= 7'b0010000; // "9" 55 | default: Ones_Display <= 7'b1000000; // "0" 56 | endcase 57 | 58 | 59 | 60 | case(Tens_Counter) //Seven Segment Decoder 61 | 4'b0000: Tens_Display <= 7'b1000000; // "0" 62 | 4'b0001: Tens_Display <= 7'b1111001; // "1" 63 | 4'b0010: Tens_Display <= 7'b0100100; // "2" 64 | 4'b0011: Tens_Display <= 7'b0110000; // "3" 65 | 4'b0100: Tens_Display <= 7'b0011001; // "4" 66 | 4'b0101: Tens_Display <= 7'b0010010; // "5" 67 | 4'b0110: Tens_Display <= 7'b0000010; // "6" 68 | 4'b0111: Tens_Display <= 7'b1111000; // "7" 69 | 4'b1000: Tens_Display <= 7'b0000000; // "8" 70 | 4'b1001: Tens_Display <= 7'b0010000; // "9" 71 | default: Tens_Display <= 7'b1000000; // "0" 72 | endcase 73 | end 74 | 75 | 76 | 77 | endmodule 78 | 79 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Solution/Example_ISSP_SignalTap_solution.v~: -------------------------------------------------------------------------------- 1 | module Counter ( 2 | input clock, 3 | input reset, 4 | output reg [6:0] Ones_Display, 5 | output reg [6:0] Tens_Display 6 | ); 7 | 8 | reg [23:0] delay; //Delay variable for the counter values to get displayed on the seven segment (Like clock divider) 9 | reg [3:0] Ones_Counter = 4'b0; //counter_ones variable 10 | reg [3:0] Tens_Counter = 4'b0; //counter_tens variable 11 | 12 | 13 | always @(posedge clock) 14 | begin 15 | if(reset == 1'b0) //if reset set variables to 0 16 | begin 17 | Ones_Counter <= 0; 18 | delay <=0; 19 | Tens_Counter <=0; 20 | end 21 | 22 | else 23 | begin 24 | 25 | delay <= delay +1; //increment delay each cycle 26 | if ((delay == 24'b100000000000000000000000) && (Ones_Counter <= 4'b1001) ) 27 | begin 28 | Ones_Counter <= Ones_Counter + 1; //increment ones_counter once delay reached its value & increment tens_counter 29 | if(Ones_Counter == 4'b1001) 30 | begin 31 | Tens_Counter<= Tens_Counter +1; 32 | end 33 | end 34 | 35 | else if(Ones_Counter > 4'b1001) //Rollover to zero 36 | Ones_Counter <= 4'b0000; 37 | 38 | else if(Tens_Counter > 4'b1001) //Rollover to zero 39 | Tens_Counter <=4'b0000; 40 | 41 | end 42 | 43 | 44 | case(Ones_Counter) //Seven Segment decoder 45 | 4'b0000: Ones_Display <= 7'b1000000; // "0" 46 | 4'b0001: Ones_Display <= 7'b1111001; // "1" 47 | 4'b0010: Ones_Display <= 7'b0100100; // "2" 48 | 4'b0011: Ones_Display <= 7'b0110000; // "3" 49 | 4'b0100: Ones_Display <= 7'b0011001; // "4" 50 | 4'b0101: Ones_Display <= 7'b0010010; // "5" 51 | 4'b0110: Ones_Display <= 7'b0000010; // "6" 52 | 4'b0111: Ones_Display <= 7'b1111000; // "7" 53 | 4'b1000: Ones_Display <= 7'b0000000; // "8" 54 | 4'b1001: Ones_Display <= 7'b0010000; // "9" 55 | default: Ones_Display <= 7'b1000000; // "0" 56 | endcase 57 | 58 | 59 | 60 | case(Tens_Counter) //Seven Segment Decoder 61 | 4'b0000: Tens_Display <= 7'b1000000; // "0" 62 | 4'b0001: Tens_Display <= 7'b1111001; // "1" 63 | 4'b0010: Tens_Display <= 7'b0100100; // "2" 64 | 4'b0011: Tens_Display <= 7'b0110000; // "3" 65 | 4'b0100: Tens_Display <= 7'b0011001; // "4" 66 | 4'b0101: Tens_Display <= 7'b0010010; // "5" 67 | 4'b0110: Tens_Display <= 7'b0000010; // "6" 68 | 4'b0111: Tens_Display <= 7'b1111000; // "7" 69 | 4'b1000: Tens_Display <= 7'b0000000; // "8" 70 | 4'b1001: Tens_Display <= 7'b0010000; // "9" 71 | default: Tens_Display <= 7'b1000000; // "0" 72 | endcase 73 | end 74 | 75 | 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_Simulation_Debug_Remote/Solution/tb_counter_solution.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | 3 | module tb_counter(); 4 | 5 | reg clock,reset_pll,reset_count,counter_direction; 6 | wire [3:0] count_up , count_down; 7 | 8 | 9 | top_counter DUT ( .refclk(clock) , 10 | .reset_pll(reset_pll) , 11 | .reset_count(reset_count), 12 | .counter_direction(counter_direction), 13 | .count_up(count_up), 14 | .count_down(count_down) ); 15 | 16 | initial 17 | begin 18 | clock = 0; 19 | reset_pll =1; 20 | reset_count=1; 21 | counter_direction =0; 22 | 23 | #10 reset_pll=0; 24 | #30 reset_count=0; 25 | #10 counter_direction=1; 26 | #30 counter_direction=0; 27 | #10 counter_direction=1; 28 | #30 counter_direction=0; 29 | #10 counter_direction=1; 30 | #30 counter_direction=0; 31 | 32 | 33 | #1000 $stop; 34 | 35 | end 36 | 37 | always #10 clock = ~clock; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /main/QuickStartGuides/Workshop_System_Verilog/Labs-Part2.zip: -------------------------------------------------------------------------------- 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