├── LICENSE ├── README.md ├── README.txt ├── aib_lib ├── aibcr3_lib │ └── rtl │ │ ├── aibcr3_2to4dec.v │ │ ├── aibcr3_aliasd.v │ │ ├── aibcr3_aliasv.v │ │ ├── aibcr3_anaio_esd.v │ │ ├── aibcr3_analog.v │ │ ├── aibcr3_avmm1.v │ │ ├── aibcr3_avmm2.v │ │ ├── aibcr3_buffx1.v │ │ ├── aibcr3_buffx1_top.v │ │ ├── aibcr3_clkmux2.v │ │ ├── aibcr3_clktree.v │ │ ├── aibcr3_clktree_avmm.v │ │ ├── aibcr3_clktree_avmm_mimic.v │ │ ├── aibcr3_clktree_avmm_pcs.v │ │ ├── aibcr3_clktree_mimic.v │ │ ├── aibcr3_clktree_pcs.v │ │ ├── aibcr3_cmos_fine_dly.v │ │ ├── aibcr3_cmos_nand_x1.v │ │ ├── aibcr3_cmos_nand_x64.v │ │ ├── aibcr3_data_buf.v │ │ ├── aibcr3_dcc_8ph_intp.v │ │ ├── aibcr3_dcc_crsdlyline.v │ │ ├── aibcr3_dcc_dll.v │ │ ├── aibcr3_dcc_dly.v │ │ ├── aibcr3_dcc_dly_rep.v │ │ ├── aibcr3_dcc_dlyline.v │ │ ├── aibcr3_dcc_dlyline64.v │ │ ├── aibcr3_dcc_gry2thm64.v │ │ ├── aibcr3_dcc_helper.v │ │ ├── aibcr3_dcc_interpolator.v │ │ ├── aibcr3_dcc_phasedet.v │ │ ├── aibcr3_dcc_top.v │ │ ├── aibcr3_dcc_top_dummy.v │ │ ├── aibcr3_digital.v │ │ ├── aibcr3_dll_8ph_intp.v │ │ ├── aibcr3_dll_custom.v │ │ ├── aibcr3_dll_dlyline64.v │ │ ├── aibcr3_dll_gry2thm64.v │ │ ├── aibcr3_dll_ibkmux.v │ │ ├── aibcr3_dll_lock_dly.v │ │ ├── aibcr3_dly_mimic.v │ │ ├── aibcr3_dlycell_dcc.v │ │ ├── aibcr3_dlycell_dcc_rep.v │ │ ├── aibcr3_dlycell_dll.v │ │ ├── aibcr3_dlycell_dll_c.v │ │ ├── aibcr3_esd.v │ │ ├── aibcr3_ff_p.v │ │ ├── aibcr3_ff_r.v │ │ ├── aibcr3_ff_rp.v │ │ ├── aibcr3_interface.v │ │ ├── aibcr3_inv_split_align.v │ │ ├── aibcr3_io_cmos_8ph_interpolator.v │ │ ├── aibcr3_io_cmos_8ph_interpolator_rep.v │ │ ├── aibcr3_io_cmos_nand_x1.v │ │ ├── aibcr3_io_cmos_nand_x128.v │ │ ├── aibcr3_io_cmos_nand_x64.v │ │ ├── aibcr3_io_ip8phs.v │ │ ├── aibcr3_io_nand_delay_line_min.v │ │ ├── aibcr3_io_nand_delay_line_min_rep.v │ │ ├── aibcr3_io_nand_x128_delay_line.v │ │ ├── aibcr3_latch.v │ │ ├── aibcr3_lvshift.v │ │ ├── aibcr3_lvshift_diff.v │ │ ├── aibcr3_lvshift_lospeed.v │ │ ├── aibcr3_nd2d0_custom.v │ │ ├── aibcr3_opio_esd.v │ │ ├── aibcr3_preclkbuf.v │ │ ├── aibcr3_quadph_code_gen.v │ │ ├── aibcr3_rambit_buf.v │ │ ├── aibcr3_red_clkmux2.v │ │ ├── aibcr3_red_clkmux3.v │ │ ├── aibcr3_red_custom_dig.v │ │ ├── aibcr3_red_custom_dig2.v │ │ ├── aibcr3_rxanlg.v │ │ ├── aibcr3_rxdat_mimic.v │ │ ├── aibcr3_rxdatapath_rx.v │ │ ├── aibcr3_rxdig.v │ │ ├── aibcr3_scan_iomux.v │ │ ├── aibcr3_signal_buf.v │ │ ├── aibcr3_split_align.v │ │ ├── aibcr3_str_align.v │ │ ├── aibcr3_str_ff.v │ │ ├── aibcr3_str_ioload.v │ │ ├── aibcr3_svt16_scdffcdn_cust.v │ │ ├── aibcr3_svt16_scdffsdn_cust.v │ │ ├── aibcr3_sync_2ff.v │ │ ├── aibcr3_sync_3ff.v │ │ ├── aibcr3_sync_ff.v │ │ ├── aibcr3_top.v │ │ ├── aibcr3_top_wrp.v │ │ ├── aibcr3_triinv_dig.v │ │ ├── aibcr3_txanlg.v │ │ ├── aibcr3_txdat_mimic.v │ │ ├── aibcr3_txdatapath_tx.v │ │ ├── aibcr3_txdig.v │ │ ├── aibcr3_ulvt16_2xarstsyncdff1_b2.v │ │ ├── aibcr3_ulvt16_dffcdn_cust.v │ │ ├── aibcr3_ulvt16_dffsdn_cust.v │ │ └── structured.v ├── aibcr3aux_lib │ └── rtl │ │ ├── aibcr3_clkbuf.v │ │ ├── aibcr3aux_actred.v │ │ ├── aibcr3aux_async.v │ │ ├── aibcr3aux_cndn_clktree.v │ │ ├── aibcr3aux_cnocdn.v │ │ ├── aibcr3aux_cnocup.v │ │ ├── aibcr3aux_cnup_clktree.v │ │ ├── aibcr3aux_inclkdly.v │ │ ├── aibcr3aux_lvshift.v │ │ ├── aibcr3aux_lvshift_1p8.v │ │ ├── aibcr3aux_osc.v │ │ ├── aibcr3aux_osc_3bcntr.v │ │ ├── aibcr3aux_osc_6bcntr.v │ │ ├── aibcr3aux_osc_ana.v │ │ ├── aibcr3aux_osc_clkgatesync.v │ │ ├── aibcr3aux_osc_clkmux.v │ │ ├── aibcr3aux_osc_dft.v │ │ ├── aibcr3aux_osc_dig.v │ │ ├── aibcr3aux_osc_div2_asyn_clr.v │ │ ├── aibcr3aux_osc_div2_syn_clr.v │ │ ├── aibcr3aux_osc_divby8.v │ │ ├── aibcr3aux_osc_dly.v │ │ ├── aibcr3aux_osc_dly_unit.v │ │ ├── aibcr3aux_osc_ff.v │ │ ├── aibcr3aux_osc_lsbuf.v │ │ ├── aibcr3aux_osc_monitor.v │ │ ├── aibcr3aux_osc_sync.v │ │ ├── aibcr3aux_osc_sync_ff.v │ │ ├── aibcr3aux_outclkdly.v │ │ ├── aibcr3aux_pasred.v │ │ ├── aibcr3aux_pasred_baldwin.v │ │ ├── aibcr3aux_top.v │ │ └── aibcr3aux_top_wrp.v ├── aibcr3pnr_lib │ └── rtl │ │ ├── aibcr3pnr_bsr_red_wrap.v │ │ ├── aibcr3pnr_dll_core.v │ │ ├── aibcr3pnr_dll_ctrl.v │ │ ├── aibcr3pnr_dll_pnr.v │ │ ├── aibcr3pnr_half_cycle_code_gen.v │ │ ├── aibcr3pnr_jtag_bscan.v │ │ ├── aibcr3pnr_redundancy.v │ │ ├── aibcr3pnr_rstsync.sv │ │ └── aibcr3pnr_self_lock_assertion.v ├── c3aibadapt │ └── rtl │ │ ├── c3aibadapt.v │ │ ├── c3aibadapt_avmm │ │ ├── c3aibadapt_avmm │ │ ├── c3aibadapt_avmm.v │ │ ├── c3aibadapt_avmm1.v │ │ ├── c3aibadapt_avmm1_async.v │ │ ├── c3aibadapt_avmm1_config.v │ │ ├── c3aibadapt_avmm1_transfer.v │ │ ├── c3aibadapt_avmm1clk_ctl.v │ │ ├── c3aibadapt_avmm2.v │ │ ├── c3aibadapt_avmm2_async.v │ │ ├── c3aibadapt_avmm2_config.v │ │ ├── c3aibadapt_avmm2_transfer.v │ │ ├── c3aibadapt_avmm2clk_ctl.v │ │ ├── c3aibadapt_avmm_async.v │ │ ├── c3aibadapt_avmm_cmdbuilder.sv │ │ ├── c3aibadapt_avmm_dec_arb.sv │ │ ├── c3aibadapt_avmm_decode.sv │ │ ├── c3aibadapt_avmm_rdfifo.v │ │ ├── c3aibadapt_avmm_usr32_exp.sv │ │ ├── c3aibadapt_avmmclk_dcg.v │ │ ├── c3aibadapt_avmmclk_gate.v │ │ ├── c3aibadapt_avmmrst_ctl.v │ │ ├── c3aibadapt_cfg_csr.v │ │ ├── c3aibadapt_cfg_rdmux.v │ │ ├── c3aibadapt_hrdrst_clkctl.v │ │ ├── c3aibadapt_hrdrst_rstctrl.v │ │ ├── c3aibadapt_hwcfg_dec.v │ │ └── c3aibadapt_usr_csr.v │ │ ├── c3aibadapt_cmn │ │ ├── c3aibadapt_cmn_async_capture_bit.v │ │ ├── c3aibadapt_cmn_async_capture_bus.v │ │ ├── c3aibadapt_cmn_clkand2.v │ │ ├── c3aibadapt_cmn_clkgate.v │ │ ├── c3aibadapt_cmn_clkgate_high.v │ │ ├── c3aibadapt_cmn_clkinv.v │ │ ├── c3aibadapt_cmn_clkmux2.v │ │ ├── c3aibadapt_cmn_clkmux2_cell.v │ │ ├── c3aibadapt_cmn_cp_comp_cntr.v │ │ ├── c3aibadapt_cmn_cp_dist.v │ │ ├── c3aibadapt_cmn_cp_dist_dw.v │ │ ├── c3aibadapt_cmn_cp_dist_pair.v │ │ ├── c3aibadapt_cmn_cp_dist_pair_dw.v │ │ ├── c3aibadapt_cmn_dft_clk_ctlr.v │ │ ├── c3aibadapt_cmn_dprio_status_sync_regs.v │ │ ├── c3aibadapt_cmn_latency_measure.v │ │ ├── c3aibadapt_cmn_occ_clkgate.v │ │ ├── c3aibadapt_cmn_occ_enable_logic.v │ │ ├── c3aibadapt_cmn_occ_gray_cntr.v │ │ ├── c3aibadapt_cmn_occ_test_ctlregs.v │ │ ├── c3aibadapt_cmn_parity_checker.v │ │ ├── c3aibadapt_cmn_parity_gen.v │ │ ├── c3aibadapt_cmn_pulse_stretch.v │ │ └── c3aibadapt_cmn_shadow_status_regs.v │ │ ├── c3aibadapt_rxchnl │ │ ├── c3aibadapt_rx_dprio.v │ │ ├── c3aibadapt_rxasync.v │ │ ├── c3aibadapt_rxasync_capture.v │ │ ├── c3aibadapt_rxasync_direct.v │ │ ├── c3aibadapt_rxasync_rsvd_capture.v │ │ ├── c3aibadapt_rxasync_rsvd_update.v │ │ ├── c3aibadapt_rxasync_update.v │ │ ├── c3aibadapt_rxchnl.v │ │ ├── c3aibadapt_rxchnl_testbus.v │ │ ├── c3aibadapt_rxclk_ctl.v │ │ ├── c3aibadapt_rxclk_gate.v │ │ ├── c3aibadapt_rxdp.v │ │ ├── c3aibadapt_rxdp_asn.v │ │ ├── c3aibadapt_rxdp_async_fifo.v │ │ ├── c3aibadapt_rxdp_cp_bond.v │ │ ├── c3aibadapt_rxdp_del_sm.v │ │ ├── c3aibadapt_rxdp_fifo.v │ │ ├── c3aibadapt_rxdp_fifo_ptr.v │ │ ├── c3aibadapt_rxdp_fifo_ram.v │ │ ├── c3aibadapt_rxdp_map.v │ │ ├── c3aibadapt_rxdp_rxeq_sm.v │ │ ├── c3aibadapt_rxdp_txeq.v │ │ ├── c3aibadapt_rxdp_txeq_sm.v │ │ └── c3aibadapt_rxrst_ctl.v │ │ ├── c3aibadapt_sr │ │ ├── c3aibadapt_fsr_in.v │ │ ├── c3aibadapt_fsr_out.v │ │ ├── c3aibadapt_sr.v │ │ ├── c3aibadapt_sr_async_capture_bit.v │ │ ├── c3aibadapt_sr_async_capture_bus.v │ │ ├── c3aibadapt_sr_in_bit.v │ │ ├── c3aibadapt_sr_out_bit.v │ │ ├── c3aibadapt_sr_sm.v │ │ ├── c3aibadapt_srclk_ctl.v │ │ ├── c3aibadapt_srrst_ctl.v │ │ ├── c3aibadapt_ssr_in.v │ │ └── c3aibadapt_ssr_out.v │ │ └── c3aibadapt_txchnl │ │ ├── c3aibadapt_async_update.v │ │ ├── c3aibadapt_hip_async_capture.v │ │ ├── c3aibadapt_hip_async_update.v │ │ ├── c3aibadapt_tx_dprio.v │ │ ├── c3aibadapt_txasync.v │ │ ├── c3aibadapt_txasync_capture.v │ │ ├── c3aibadapt_txasync_direct.v │ │ ├── c3aibadapt_txasync_rsvd_capture.v │ │ ├── c3aibadapt_txasync_rsvd_update.v │ │ ├── c3aibadapt_txasync_update.v │ │ ├── c3aibadapt_txchnl.v │ │ ├── c3aibadapt_txchnl_testbus.v │ │ ├── c3aibadapt_txclk_ctl.v │ │ ├── c3aibadapt_txclk_gate.v │ │ ├── c3aibadapt_txdp.v │ │ ├── c3aibadapt_txdp_async_fifo.v │ │ ├── c3aibadapt_txdp_cp_bond.v │ │ ├── c3aibadapt_txdp_fifo.v │ │ ├── c3aibadapt_txdp_fifo_ptr.v │ │ ├── c3aibadapt_txdp_fifo_ram.v │ │ ├── c3aibadapt_txdp_map.v │ │ ├── c3aibadapt_txdp_word_align.v │ │ └── c3aibadapt_txrst_ctl.v ├── c3aibadapt_wrap │ └── rtl │ │ ├── aib_top.v │ │ ├── aib_top_master.sv │ │ ├── c3aib_master.sv │ │ ├── c3aibadapt_wrap.v │ │ ├── c3aibadapt_wrap_top.v │ │ ├── c3routing_chnl_aib.sv │ │ └── c3routing_chnl_edge.sv ├── c3dfx │ └── rtl │ │ ├── defines │ │ ├── c3dfx.vh │ │ └── c3dfx_dv.vh │ │ ├── tap │ │ ├── dbg_test_defines.v │ │ └── dbg_test_jtagsm.v │ │ ├── tcb │ │ └── c3dfx_aibadaptwrap_tcb.sv │ │ └── tcm │ │ ├── c3dfx_tcm.sv │ │ └── c3dfx_tcm_wrap.sv └── c3lib │ └── rtl │ ├── avmm │ ├── c3_avmm_rdl_intf.sv │ ├── c3lib_avmm_pulse_cross.sv │ ├── c3lib_cfgcsr_fastslow_pulse_meta.sv │ └── c3lib_cfgcsr_slowfast_pulse_meta.sv │ ├── basic │ └── pulse_stretch │ │ └── cdclib_pulse_stretch.sv │ ├── cdc │ ├── async_fifo │ │ └── c3lib_async_fifo.sv │ ├── bit_synchronizer │ │ ├── c3lib_bitsync.sv │ │ ├── c3lib_sync2_lvt_bitsync.sv │ │ ├── c3lib_sync2_ulvt_bitsync.sv │ │ └── c3lib_sync3_ulvt_bitsync.sv │ ├── glitch_free_mux │ │ └── c3lib_gf_clkmux.sv │ ├── gray_code │ │ ├── c3lib_bintogray.sv │ │ └── c3lib_graytobin.sv │ ├── level_synchronizer │ │ └── c3lib_lvlsync.sv │ ├── reset_synchronizer │ │ └── c3lib_rstsync.sv │ └── vector_synchronizer │ │ ├── c3lib_vecsync.sv │ │ └── c3lib_vecsync_handshake.sv │ ├── ctn │ ├── clock_buf │ │ ├── c3lib_ckand2_ctn.sv │ │ ├── c3lib_ckbuf_ctn.sv │ │ └── c3lib_ckinv_ctn.sv │ ├── clock_divider │ │ ├── c3lib_ckdiv2_ctn.sv │ │ ├── c3lib_ckdiv4_ctn.sv │ │ └── c3lib_ckdiv8_ctn.sv │ ├── clock_gater │ │ ├── c3lib_ckg_async_posedge_ctn.sv │ │ ├── c3lib_ckg_negedge_ctn.sv │ │ └── c3lib_ckg_posedge_ctn.sv │ └── clock_mux │ │ ├── c3lib_mux2_ctn.sv │ │ ├── c3lib_mux3_ctn.sv │ │ └── c3lib_mux4_ctn.sv │ ├── defines │ └── c3lib_dv_defines.sv │ ├── ecc │ ├── c3lib_ecc_dec_c39_d32.sv │ ├── c3lib_ecc_dec_c88_d80.sv │ ├── c3lib_ecc_enc_d32_c39.sv │ └── c3lib_ecc_enc_d80_c88.sv │ ├── lcell │ ├── c3lib_and2_lcell.sv │ ├── c3lib_buf_lcell.sv │ ├── c3lib_dff_scan_lcell.sv │ ├── c3lib_mtieh_lcell.sv │ ├── c3lib_mtiel_lcell.sv │ ├── c3lib_mux2_lcell.sv │ ├── c3lib_nand2_lcell.sv │ ├── c3lib_or2_lcell.sv │ ├── c3lib_tie_bus_lcell.sv │ ├── c3lib_tieh_lcell.sv │ └── c3lib_tiel_lcell.sv │ └── primitives │ ├── c3lib_and2_svt_2x.sv │ ├── c3lib_and2_svt_4x.sv │ ├── c3lib_buf_svt_4x.sv │ ├── c3lib_ckbuf_lvt_4x.sv │ ├── c3lib_ckg_lvt_8x.sv │ ├── c3lib_ckinv_lvt_12x.sv │ ├── c3lib_ckinv_svt_8x.sv │ ├── c3lib_ckmux4_lvt_gate.sv │ ├── c3lib_ckmux4_ulvt_gate.sv │ ├── c3lib_dff0_reset_lvt_2x.sv │ ├── c3lib_dff0_scan_reset_svt_2x.sv │ ├── c3lib_dff0_set_lvt_2x.sv │ ├── c3lib_mtie0_ds.sv │ ├── c3lib_mtie1_ds.sv │ ├── c3lib_mux2_svt_2x.sv │ ├── c3lib_nand2_svt_2x.sv │ ├── c3lib_or2_svt_2x.sv │ ├── c3lib_sync2_reset_lvt_gate.sv │ ├── c3lib_sync2_reset_ulvt_gate.sv │ ├── c3lib_sync2_set_lvt_gate.sv │ ├── c3lib_sync2_set_ulvt_gate.sv │ ├── c3lib_sync3_reset_ulvt_gate.sv │ ├── c3lib_sync3_set_ulvt_gate.sv │ ├── c3lib_sync_metastable_behav_gate.sv │ ├── c3lib_tie0_svt_1x.sv │ └── c3lib_tie1_svt_1x.sv ├── docs ├── AIB_Intel_Specification 1_2 .pdf ├── AIB_Usage_Note_v1_2_1.pdf ├── FCCM_2019_Workshop_AIB.pdf ├── Stratix 10 Chiplet AIB Profile_v1_0_aib_bump_locations.xlsx ├── USERGUIDE.txt ├── aib_update_10_2018.pdf ├── archive │ ├── AIB_Intel_Specification 1_1.pdf │ ├── AIB_Intel_Specification_1_0_version1.pdf │ ├── AIB_Usage_Note_v1_2.pdf │ └── Stratix 10 Chiplet AIB Profile_v1_0.pdf ├── dkehlet_ocp_odsa_workshop_061019_v3.pdf └── open_source_aib_csr.xlsx ├── how2use ├── README.txt ├── sim_aib_top │ ├── Makefile │ ├── c3aibadapt_wrap.f │ ├── dut_io.sv │ ├── test.sv │ └── top.sv ├── sim_aib_top_ncsim │ ├── c3aibadapt_wrap.f │ ├── dut_io.sv │ ├── runnc │ ├── sim_input.tcl │ ├── test.sv │ └── top.sv ├── sim_dcc │ ├── Makefile │ ├── aibcr3_dcc_helper.v │ ├── c3aib_master.sv │ ├── c3aibadapt_wrap.f │ ├── c3aibadapt_wrap.v │ ├── dut_io.sv │ ├── test.sv │ └── top.sv ├── sim_mod2mod │ ├── filelist │ ├── redundancy_ctrl_sim.vh │ ├── runsim │ └── tb_top.sv ├── sim_phasecom │ ├── Makefile │ ├── c3aib_master.sv │ ├── c3aibadapt_wrap.f │ ├── c3aibadapt_wrap.v │ ├── dut_io.sv │ ├── test.sv │ └── top.sv └── sim_sl2ms_lpbk │ ├── README.txt │ ├── dut_io.sv │ ├── multidie.f │ ├── nda_drv.sv │ ├── nda_port.sv │ ├── ndut_declare.sv │ ├── ndut_default.sv │ ├── ndut_io.sv │ ├── redundancy_ctrl_sim.vh │ ├── runnc │ ├── runsim │ ├── runvsim │ ├── self_test.do │ ├── sim_input.tcl │ ├── test.sv │ ├── top.sv │ └── vlog.do ├── maib_rtl ├── aibnd_lib │ └── rtl │ │ └── block_function │ │ ├── aibnd_2ff_scan.v │ │ ├── aibnd_2to4dec.v │ │ ├── aibnd_aliasd.v │ │ ├── aibnd_aliasv.v │ │ ├── aibnd_analog.v │ │ ├── aibnd_avmm1.v │ │ ├── aibnd_avmm2.v │ │ ├── aibnd_avmm_rst_sync.v │ │ ├── aibnd_bsr_red_wrap.v │ │ ├── aibnd_buffx1.v │ │ ├── aibnd_buffx1_top.v │ │ ├── aibnd_clkbuf.v │ │ ├── aibnd_clkmux2.v │ │ ├── aibnd_clkmux2.v.hack │ │ ├── aibnd_clktree.v │ │ ├── aibnd_clktree_avmm.v │ │ ├── aibnd_clktree_avmm_mimic.v │ │ ├── aibnd_clktree_avmm_pcs.v │ │ ├── aibnd_clktree_mimic.v │ │ ├── aibnd_clktree_pcs.v │ │ ├── aibnd_cmos_fine_dly.v │ │ ├── aibnd_cmos_nand_x1.v │ │ ├── aibnd_cmos_nand_x128.v │ │ ├── aibnd_cmos_nand_x6.v │ │ ├── aibnd_cmos_nand_x64.v │ │ ├── aibnd_d8xsesdd1.v │ │ ├── aibnd_d8xsesdd2.v │ │ ├── aibnd_data_buf.v │ │ ├── aibnd_dcc_3bcnt.v │ │ ├── aibnd_dcc_4b_b2tc.v │ │ ├── aibnd_dcc_4bdncnt.v │ │ ├── aibnd_dcc_4bupcnt.v │ │ ├── aibnd_dcc_5b_b2tc.v │ │ ├── aibnd_dcc_5b_b2tc_x1.v │ │ ├── aibnd_dcc_5bdncnt.v │ │ ├── aibnd_dcc_5bupcnt.v │ │ ├── aibnd_dcc_adjust.v │ │ ├── aibnd_dcc_clkrst.v │ │ ├── aibnd_dcc_ctrl.v │ │ ├── aibnd_dcc_dll.v │ │ ├── aibnd_dcc_dly.v │ │ ├── aibnd_dcc_dly_inv.v │ │ ├── aibnd_dcc_dly_rep.v │ │ ├── aibnd_dcc_ff.v │ │ ├── aibnd_dcc_fine_dly.v │ │ ├── aibnd_dcc_fine_dly_x1.v │ │ ├── aibnd_dcc_fltr.v │ │ ├── aibnd_dcc_helper.v │ │ ├── aibnd_dcc_mux.v │ │ ├── aibnd_dcc_sense.v │ │ ├── aibnd_dcc_top.v │ │ ├── aibnd_digital.v │ │ ├── aibnd_dll_custom.v │ │ ├── aibnd_dll_phdet.v │ │ ├── aibnd_dly_mimic.v │ │ ├── aibnd_ff_r.v │ │ ├── aibnd_ff_rp.v │ │ ├── aibnd_fine_dly_inv.v │ │ ├── aibnd_fine_dly_x1.v │ │ ├── aibnd_hgy_latch.v │ │ ├── aibnd_interface.v │ │ ├── aibnd_inv.v │ │ ├── aibnd_inv_split_align.v │ │ ├── aibnd_io_dly_interpolator_rep.v │ │ ├── aibnd_io_nand_delay_line_min_rep.v │ │ ├── aibnd_jtag_bscan.v │ │ ├── aibnd_latch.v │ │ ├── aibnd_nand2.v │ │ ├── aibnd_nand_x128_delay_line.v │ │ ├── aibnd_nand_x64_delay_line.v │ │ ├── aibnd_nor2.v │ │ ├── aibnd_preclkbuf.v │ │ ├── aibnd_quadph_code_gen.v │ │ ├── aibnd_rambit_buf.v │ │ ├── aibnd_red_clkmux2.v │ │ ├── aibnd_red_clkmux3.v │ │ ├── aibnd_red_custom_dig.v │ │ ├── aibnd_red_custom_dig2.v │ │ ├── aibnd_redundancy.v │ │ ├── aibnd_rxanlg.v │ │ ├── aibnd_rxdat_mimic.v │ │ ├── aibnd_rxdatapath_rx.v │ │ ├── aibnd_rxdig.v │ │ ├── aibnd_signal_buf.v │ │ ├── aibnd_str_align.v │ │ ├── aibnd_str_align_avmm.v │ │ ├── aibnd_str_clktree.v │ │ ├── aibnd_str_clktree_mimic.v │ │ ├── aibnd_str_ff.v │ │ ├── aibnd_str_ioload.v │ │ ├── aibnd_str_preclkbuf.v │ │ ├── aibnd_sync_ff.v │ │ ├── aibnd_top.v │ │ ├── aibnd_top_wrp.v │ │ ├── aibnd_triinv_dig_str.v │ │ ├── aibnd_txanlg.v │ │ ├── aibnd_txdat_mimic.v │ │ ├── aibnd_txdatapath_tx.v │ │ └── aibnd_txdig.v ├── aibndpnr_lib │ └── rtl │ │ └── block_function │ │ ├── aibndpnr_bsr_red_wrap.v │ │ ├── aibndpnr_define.v │ │ ├── aibndpnr_dll_atech_clkgate_cgc00.v │ │ ├── aibndpnr_dll_atech_clkgate_cgc01.v │ │ ├── aibndpnr_dll_atech_clkmux.v │ │ ├── aibndpnr_dll_core.v │ │ ├── aibndpnr_dll_ctrl.v │ │ ├── aibndpnr_dll_pnr.v │ │ ├── aibndpnr_half_cycle_code_gen.v │ │ ├── aibndpnr_jtag_bscan.v │ │ ├── aibndpnr_redundancy.v │ │ ├── aibndpnr_self_lock_assertion.v │ │ └── aibndpnr_sync.v ├── cdclib │ └── rtl │ │ └── block_function │ │ ├── cdclib_async_fifo.v │ │ ├── cdclib_bintogray.v │ │ ├── cdclib_bintogray_inc2.v │ │ ├── cdclib_bintogray_inc8.v │ │ ├── cdclib_bitsync.v │ │ ├── cdclib_bitsync2.v │ │ ├── cdclib_bitsync4.v │ │ ├── cdclib_graytobin.v │ │ ├── cdclib_graytobin_inc2.v │ │ ├── cdclib_graytobin_inc8.v │ │ ├── cdclib_lvlsync.v │ │ ├── cdclib_lvlsync2.v │ │ ├── cdclib_lvlsync4.v │ │ ├── cdclib_pulse_stretch.v │ │ ├── cdclib_rst_n_sync.v │ │ ├── cdclib_rst_n_sync_core.v │ │ ├── cdclib_sync2_reset_type_l_gate.v │ │ ├── cdclib_sync2_reset_type_n_gate.v │ │ ├── cdclib_sync2_reset_type_w_gate.v │ │ ├── cdclib_sync2_set_type_l_gate.v │ │ ├── cdclib_sync2_set_type_n_gate.v │ │ ├── cdclib_sync2_set_type_w_gate.v │ │ ├── cdclib_sync4_reset_type_l_gate.v │ │ ├── cdclib_sync4_reset_type_w_gate.v │ │ ├── cdclib_sync4_set_type_l_gate.v │ │ ├── cdclib_sync4_set_type_w_gate.v │ │ ├── cdclib_vecsync.v │ │ ├── cdclib_vecsync2.v │ │ └── cdclib_vecsync4.v ├── cfg_shared │ └── rtl │ │ └── block_function │ │ ├── cfg_bead.v │ │ ├── cfg_bead_bus.v │ │ ├── cfg_cmn_clk_mux.v │ │ ├── cfg_cmn_latch.v │ │ ├── cfg_cmn_non_scan_reg.v │ │ ├── cfg_dprio_csr_reg_bit.v │ │ ├── cfg_dprio_csr_reg_nbits.v │ │ ├── cfg_dprio_csr_reg_nregs.v │ │ ├── cfg_dprio_csr_test_mux.v │ │ ├── cfg_dprio_ctrl_reg_bit.v │ │ ├── cfg_dprio_ctrl_reg_nbits.v │ │ ├── cfg_dprio_ctrl_reg_nregs.v │ │ ├── cfg_dprio_ctrl_stat_interface_top.v │ │ ├── cfg_dprio_ctrl_stat_reg_chnl.v │ │ ├── cfg_dprio_ctrl_stat_reg_top.v │ │ ├── cfg_dprio_ctrl_stat_reg_w_resvrd_chnl.v │ │ ├── cfg_dprio_ctrl_stat_reg_w_resvrd_top.v │ │ ├── cfg_dprio_dis_ctrl_cvp.v │ │ ├── cfg_dprio_readdata_mux.v │ │ ├── cfg_dprio_readdata_mux_mod.v │ │ ├── cfg_dprio_readdata_sel.v │ │ ├── cfg_dprio_shadow_status_nregs.v │ │ ├── cfg_dprio_shadow_status_regs.v │ │ ├── cfg_dprio_status_reg_nbits.v │ │ ├── cfg_dprio_status_reg_nregs.v │ │ └── cfg_dprio_status_sync_regs.v ├── hdpldadapt │ └── rtl │ │ ├── hdpldadapt.v │ │ ├── hdpldadapt_avmm │ │ ├── hdpldadapt_avmm.v │ │ ├── hdpldadapt_avmm1.v │ │ ├── hdpldadapt_avmm1_async.v │ │ ├── hdpldadapt_avmm1_config.v │ │ ├── hdpldadapt_avmm1_dprio_mapping.v │ │ ├── hdpldadapt_avmm1_transfer.v │ │ ├── hdpldadapt_avmm2.v │ │ ├── hdpldadapt_avmm2_async.v │ │ ├── hdpldadapt_avmm2_transfer.v │ │ ├── hdpldadapt_avmm_async.v │ │ ├── hdpldadapt_avmm_async_update.v │ │ ├── hdpldadapt_avmm_cmdfifo.v │ │ ├── hdpldadapt_avmm_cmn_intf.v │ │ ├── hdpldadapt_avmm_dprio_reg.v │ │ ├── hdpldadapt_avmm_rdfifo.v │ │ ├── hdpldadapt_avmmclk_ctl.v │ │ ├── hdpldadapt_avmmrst_ctl.v │ │ ├── hdpldadapt_hrdrst_clkctl.v │ │ └── hdpldadapt_hrdrst_rstctrl.v │ │ ├── hdpldadapt_cmn │ │ ├── hdpldadapt_cmn_async_capture_bit.v │ │ ├── hdpldadapt_cmn_async_capture_bus.v │ │ ├── hdpldadapt_cmn_clkand2.v │ │ ├── hdpldadapt_cmn_clkdelay.v │ │ ├── hdpldadapt_cmn_clkdelay_cell.v │ │ ├── hdpldadapt_cmn_clkdelay_map.v │ │ ├── hdpldadapt_cmn_clkgate.v │ │ ├── hdpldadapt_cmn_clkinv.v │ │ ├── hdpldadapt_cmn_clkmux2.v │ │ ├── hdpldadapt_cmn_clkmux2_cell.v │ │ ├── hdpldadapt_cmn_clkor2.v │ │ ├── hdpldadapt_cmn_cp_comp_cntr.v │ │ ├── hdpldadapt_cmn_cp_dist.v │ │ ├── hdpldadapt_cmn_cp_dist_dw.v │ │ ├── hdpldadapt_cmn_cp_dist_pair.v │ │ ├── hdpldadapt_cmn_cp_dist_pair_dw.v │ │ ├── hdpldadapt_cmn_dft_clock_controller.v │ │ ├── hdpldadapt_cmn_latency_measure.v │ │ ├── hdpldadapt_cmn_occ_clkgate.v │ │ ├── hdpldadapt_cmn_occ_enable_logic.v │ │ ├── hdpldadapt_cmn_occ_gray_code_counter.v │ │ ├── hdpldadapt_cmn_occ_test_control_register.v │ │ ├── hdpldadapt_cmn_parity_checker.v │ │ ├── hdpldadapt_cmn_parity_gen.v │ │ └── hdpldadapt_cmn_pulse_stretch.v │ │ ├── hdpldadapt_rx_chnl │ │ ├── hdpldadapt_rx_async.v │ │ ├── hdpldadapt_rx_async_capture.v │ │ ├── hdpldadapt_rx_async_direct.v │ │ ├── hdpldadapt_rx_async_reserved_capture.v │ │ ├── hdpldadapt_rx_async_reserved_update.v │ │ ├── hdpldadapt_rx_async_update.v │ │ ├── hdpldadapt_rx_chnl.v │ │ ├── hdpldadapt_rx_chnl_testbus.v │ │ ├── hdpldadapt_rx_datapath.v │ │ ├── hdpldadapt_rx_datapath_asn.v │ │ ├── hdpldadapt_rx_datapath_async_fifo.v │ │ ├── hdpldadapt_rx_datapath_cp_bond.v │ │ ├── hdpldadapt_rx_datapath_del_sm.v │ │ ├── hdpldadapt_rx_datapath_fifo.v │ │ ├── hdpldadapt_rx_datapath_fifo_pointers.v │ │ ├── hdpldadapt_rx_datapath_fifo_ram.v │ │ ├── hdpldadapt_rx_datapath_insert_sm.v │ │ ├── hdpldadapt_rx_datapath_pulse_stretch.v │ │ ├── hdpldadapt_rx_datapath_word_align.v │ │ ├── hdpldadapt_rxclk_ctl.v │ │ └── hdpldadapt_rxrst_ctl.v │ │ ├── hdpldadapt_sr │ │ ├── hdpldadapt_fsr_in.v │ │ ├── hdpldadapt_fsr_out.v │ │ ├── hdpldadapt_sr.v │ │ ├── hdpldadapt_sr_async_capture_bit.v │ │ ├── hdpldadapt_sr_async_capture_bus.v │ │ ├── hdpldadapt_sr_in_bit.v │ │ ├── hdpldadapt_sr_out_bit.v │ │ ├── hdpldadapt_sr_sm.v │ │ ├── hdpldadapt_srclk_ctl.v │ │ ├── hdpldadapt_srrst_ctl.v │ │ ├── hdpldadapt_ssr_in.v │ │ └── hdpldadapt_ssr_out.v │ │ └── hdpldadapt_tx_chnl │ │ ├── hdpldadapt_async_update.v │ │ ├── hdpldadapt_fsr_in.v │ │ ├── hdpldadapt_fsr_out.v │ │ ├── hdpldadapt_hip_async_capture.v │ │ ├── hdpldadapt_hip_async_update.v │ │ ├── hdpldadapt_sr.v │ │ ├── hdpldadapt_sr_async_capture_bit.v │ │ ├── hdpldadapt_sr_async_capture_bus.v │ │ ├── hdpldadapt_sr_in_bit.v │ │ ├── hdpldadapt_sr_out_bit.v │ │ ├── hdpldadapt_sr_sm.v │ │ ├── hdpldadapt_srclk_ctl.v │ │ ├── hdpldadapt_srrst_ctl.v │ │ ├── hdpldadapt_ssr_in.v │ │ ├── hdpldadapt_ssr_out.v │ │ ├── hdpldadapt_tx_async.v │ │ ├── hdpldadapt_tx_async_capture.v │ │ ├── hdpldadapt_tx_async_direct.v │ │ ├── hdpldadapt_tx_async_reserved_capture.v │ │ ├── hdpldadapt_tx_async_reserved_update.v │ │ ├── hdpldadapt_tx_async_update.v │ │ ├── hdpldadapt_tx_chnl.v │ │ ├── hdpldadapt_tx_chnl_testbus.v │ │ ├── hdpldadapt_tx_datapath.v │ │ ├── hdpldadapt_tx_datapath_async_fifo.v │ │ ├── hdpldadapt_tx_datapath_cp_bond.v │ │ ├── hdpldadapt_tx_datapath_dv_gen.v │ │ ├── hdpldadapt_tx_datapath_fifo.v │ │ ├── hdpldadapt_tx_datapath_fifo_pointers.v │ │ ├── hdpldadapt_tx_datapath_fifo_ram.v │ │ ├── hdpldadapt_tx_datapath_frame_gen.v │ │ ├── hdpldadapt_tx_datapath_pulse_stretch.v │ │ ├── hdpldadapt_tx_datapath_word_mark.v │ │ ├── hdpldadapt_txclk_ctl.v │ │ └── hdpldadapt_txrst_ctl.v ├── io_common_custom │ └── rtl │ │ └── block_function │ │ ├── block_function │ │ ├── io_8phs_calibrate_x48.v │ │ ├── io_clk_wkup.v │ │ ├── io_cmos_16ph_decode.v │ │ ├── io_cmos_nand_x1.v │ │ ├── io_cmos_nand_x128.v │ │ ├── io_cmos_nand_x128_decode.v │ │ ├── io_cmos_nand_x4.v │ │ ├── io_cmos_nand_x6.v │ │ ├── io_cmos_nand_x64.v │ │ ├── io_cmos_nand_x64_decode.v │ │ ├── io_delay_line_dcc.v │ │ ├── io_dll_custom.v │ │ ├── io_dll_phdet.v │ │ ├── io_dly_interpclk.v │ │ ├── io_dly_interpolator.v │ │ ├── io_dq_clkdrv.v │ │ ├── io_dqs_clkdrv.v │ │ ├── io_dqs_custom.v │ │ ├── io_filter_dec.v │ │ ├── io_interp_latch_in.v │ │ ├── io_interp_misc.v │ │ ├── io_interp_mux.v │ │ ├── io_interp_mux_match.v │ │ ├── io_interp_mux_pair.v │ │ ├── io_interp_output.v │ │ ├── io_interp_pdn.v │ │ ├── io_interpolator.v │ │ ├── io_ioereg_custom.v │ │ ├── io_ioereg_struct.v │ │ ├── io_ioereg_struct_out.v │ │ ├── io_ip16phs.v │ │ ├── io_ip8phs_3in.v │ │ ├── io_min_inter.v │ │ ├── io_min_interp_mux.v │ │ ├── io_min_ip16phs.v │ │ ├── io_min_misc.v │ │ ├── io_min_output.v │ │ ├── io_min_pdn.v │ │ ├── io_nand_delay_line_min.v │ │ ├── io_nand_x128_delay_line.v │ │ ├── io_nand_x64_delay_line.v │ │ ├── io_pa_custom.v │ │ ├── io_pa_phs_buf.v │ │ ├── io_pa_phs_gated.v │ │ ├── io_phdet_ff_ln.v │ │ ├── io_phs_check.v │ │ ├── io_phs_gated.v │ │ ├── io_phs_pair_couple_x48.v │ │ └── io_split_align.v ├── s10aib │ └── rtl │ │ ├── an.v │ │ ├── ndaibadapt_wrap.v │ │ └── s10aib.v └── soc_std_macro │ └── rtl │ └── block_function │ └── i14socnd │ ├── altr_hps_1r1w_4x2_rfifo_async │ ├── altr_hps_1r1w_4x2_rfifo_async │ ├── altr_hps_1r1w_4x2_rfifo_async_read.v │ ├── altr_hps_1r1w_4x2_rfifo_async_write.v │ ├── altr_hps_bin2gray.v │ └── altr_hps_gray2bin.v │ ├── altr_hps_1r1w_4x2_rfifo_async_read.v │ ├── altr_hps_1r1w_4x2_rfifo_async_write.v │ ├── altr_hps_and.v │ ├── altr_hps_bin2gray.v │ ├── altr_hps_bitsync.v │ ├── altr_hps_bitsync4.v │ ├── altr_hps_bitsync_generator.v │ ├── altr_hps_buf.v │ ├── altr_hps_ckand.v │ ├── altr_hps_ckand_gate.v │ ├── altr_hps_ckbuf.v │ ├── altr_hps_ckinv.v │ ├── altr_hps_ckmux21.v │ ├── altr_hps_ckmux32to1.v │ ├── altr_hps_ckmux41.v │ ├── altr_hps_cknand.v │ ├── altr_hps_cknor.v │ ├── altr_hps_ckor.v │ ├── altr_hps_ckor_gate.v │ ├── altr_hps_clkgate.v │ ├── altr_hps_clkgate_or.v │ ├── altr_hps_cyc_dly.v │ ├── altr_hps_eccsync.v │ ├── altr_hps_en_bitsync.v │ ├── altr_hps_en_bitsync4.v │ ├── altr_hps_gltchfltr.v │ ├── altr_hps_gltchfltr_vec.v │ ├── altr_hps_gray2bin.v │ ├── altr_hps_gtie_generator.v │ ├── altr_hps_gtieh.v │ ├── altr_hps_gtiel.v │ ├── altr_hps_interface_register.v │ ├── altr_hps_latch.v │ ├── altr_hps_mux21.v │ ├── altr_hps_mux41.v │ ├── altr_hps_nand3.v │ ├── altr_hps_nand4.v │ ├── altr_hps_nor2.v │ ├── altr_hps_nor3.v │ ├── altr_hps_or.v │ ├── altr_hps_rstnsync.v │ ├── altr_hps_rstnsync4.v │ ├── altr_hps_sync_clr.v │ ├── altr_hps_t2_register.v │ ├── altr_hps_te_clkgate.v │ └── soc_simulation_defines.v ├── ndsimslv ├── README.txt ├── dut_io.sv ├── multidie.f ├── nda_drv.sv ├── nda_port.sv ├── ndut_declare.sv ├── ndut_default.sv ├── ndut_io.sv ├── redundancy_ctrl_sim.vh ├── runnc ├── runsim ├── runvsim ├── self_test.do ├── sim_input.tcl ├── test.sv ├── top.sv └── vlog.do └── rtl ├── aib.v ├── aib_aliasd.v ├── aib_aux_channel.v ├── aib_bitsync.v ├── aib_bsr_red_wrap.v ├── aib_buffx1_top.v ├── aib_channel.v ├── aib_dcc.v ├── aib_io_buffer.sv ├── aib_ioring.v ├── aib_jtag_bscan.v ├── aib_mux21.v ├── aib_osc_clk.sv ├── aib_redundancy.v ├── aib_rstnsync.v ├── aib_sm.v ├── aib_sr_ms.v ├── aib_sr_sl.v ├── dll.sv └── redundancy_ctrl.vh /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/aib-phy-hardware/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: 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