├── LICENSE ├── Makefile ├── README.md ├── devicetrees ├── de10-nano-base.dtsi ├── de10-nano-fft.dtsi └── de10-nano-mandelbrot.dtsi ├── hdl_src ├── soc_system_hdmi_i2c_only.sdc ├── soc_system_hdmi_timing.sdc ├── soc_system_mandelbrot_timing.sdc ├── soc_system_timing.sdc └── top.v ├── ip ├── FFT_STadapter │ ├── FFT_STadapter_hw.tcl │ └── fft_adapter.v ├── avst_mandelbrot_engine │ ├── avst_mandelbrot_engine.v │ └── avst_mandelbrot_engine_hw.tcl ├── axi_bridge_for_acp_128 │ ├── axi_bridge_for_acp_128.v │ └── axi_bridge_for_acp_128_hw.tcl ├── chip_id_read_mm │ ├── chip_id_read_mm.v │ └── chip_id_read_mm_hw.tcl ├── conduit_adapters │ ├── conduit_remap │ │ ├── conduit_remap_hw.tcl │ │ ├── conduit_to_interrupt_hw.tcl │ │ ├── conduit_to_reset_hw.tcl │ │ ├── interrupt_to_conduit_hw.tcl │ │ └── reset_to_conduit_hw.tcl │ ├── emif_status_breakout │ │ └── emif_status_breakout_hw.tcl │ └── pll_sharing_to_pll_locked │ │ └── pll_sharing_to_pll_locked_hw.tcl ├── debounce │ └── debounce.v ├── fft_sub │ ├── FFT_sub.qsys │ └── LICENSE ├── mandelbrot_colorizer │ ├── mandelbrot_colorizer.v │ └── mandelbrot_colorizer_hw.tcl ├── mandelbrot_controller │ ├── mandelbrot_controller.v │ └── mandelbrot_controller_hw.tcl ├── mandelbrot_coord_feeder │ ├── mandelbrot_coord_feeder.v │ └── mandelbrot_coord_feeder_hw.tcl ├── mandelbrot_distributor │ ├── mandelbrot_distributor.v │ └── mandelbrot_distributor_hw.tcl ├── mandelbrot_image_feeder │ ├── mandelbrot_image_feeder.v │ └── mandelbrot_image_feeder_hw.tcl ├── mandelbrot_sub │ ├── mandelbrot_engine_subsys.qsys │ └── mandelbrot_subsys.qsys ├── power_on_reset │ ├── power_on_reset.v │ └── power_on_reset_hw.tcl └── reset_synchronizer │ ├── custom_reset_synchronizer_hw.tcl │ ├── reset_sync_block.sdc │ └── reset_sync_block.v ├── mks ├── bootscript.mk ├── default.mk ├── devicetree.mk ├── dtc.mk ├── ip.mk ├── preloader_uboot.mk ├── qsys.mk ├── quartus.mk ├── sof_rbf_license.mk └── sopc2dts.mk ├── patches └── sopc2dts │ ├── 0001-Modifications-for-dts-overlay-support.patch │ ├── 0002-Use-target-path-instead-of-phandle.patch │ └── 0003-remove-since-we-moved-to-full-path-for-overlay-terge.patch ├── scripts ├── create_qsys_de10-nano-base.tcl ├── create_qsys_de10-nano-fft.tcl ├── create_qsys_de10-nano-mandelbrot.tcl ├── create_quartus_de10-nano-base.tcl ├── create_quartus_de10-nano-fft.tcl ├── create_quartus_de10-nano-mandelbrot.tcl ├── fft.tcl ├── mmlink_setup.tcl ├── qsys_add_arduino_io.tcl ├── qsys_add_chipid_components.tcl ├── qsys_add_fft128_components.tcl ├── qsys_add_hdmi.tcl ├── qsys_add_hdmi.tcl.orig ├── qsys_add_hdmi_i2c.tcl ├── qsys_add_header_gpios.tcl ├── qsys_add_mandelbrot_components.tcl ├── qsys_add_pio_components.tcl ├── qsys_default_components.tcl ├── release.sh └── sign.sh └── utils ├── create_project.tcl ├── create_revision.tcl ├── extract_pin_assignments.tcl ├── project_remove_tag.tcl └── project_run_script.tcl /LICENSE: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | Copyright (c) 2016 Intel Corporation 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in 12 | all copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 | THE SOFTWARE. 21 | 22 | 23 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | DISCONTINUATION OF PROJECT. 2 | 3 | This project will no longer be maintained by Intel. 4 | 5 | Intel has ceased development and contributions including, but not limited to, maintenance, bug fixes, new releases, or updates, to this project. 6 | 7 | Intel no longer accepts patches to this project. 8 | 9 | If you have an ongoing need to use this project, are interested in independently developing it, or would like to maintain patches for the open source software community, please create your own fork of this project. 10 | # FPGA hardware design for the Terasic DE10-Nano\* kit 11 | 12 | ## Overview 13 | Instructions to build the FPGA design for the Terasic DE10-Nano\* Kit. 14 | 15 | This repository provides support for building a demonstration FPGA image for the [Terasic DE10-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=1046&PartNo=8) kit's development board and is intended to be used in conjunction with the [meta-de10-nano](https://github.com/01org/meta-de10-nano) layer. 16 | 17 | There are 3 FPGA projects created during the build 18 | * **de10-nano-base**: A base design with no IP requiring additional licenses 19 | * **de10-nano-fft**: An FPGA based FFT example. The FFT IP does require a license 20 | * **de10-nano-mandelbrot**: An FPGA implementation of a Mandelbrot. The output of the Mandelbrot is displayed on the HDMI output 21 | 22 | **Note:** Released builds of the FPGA images are available in the release section of the github project. 23 | 24 | **Note:** Only the release builds are tested fully. The master branch is likely to work but is not thoroughly tested. 25 | 26 | ## Build Instructions 27 | A Makefile based build is used for this project which results in the following outputs: 28 | 29 | * Compiled Intel\* Quartus\* Prime Design Software project 30 | * Generated Intel\* Quartus\* QSYS\* system 31 | * Generated and compiled devicetree overlay for the DE10-Nano\* Kit 32 | * Bootloader configuration files 33 | 34 | **Note:** The release build tar file contains all FPGA programing files as well all of the above mentioned files. 35 | 36 | ### Prerequisites: 37 | 38 | * Intel\* Quartus\* Prime Design Software Version 17.1.2 39 | * Intel\* SoCEDS\* Version 17.1 40 | 41 | ### Known Issues: 42 | * Intel\* QSYS\* build from tcl source may fail on systems without a full installation of the Intel\* Quartus\* Prime Design Software. If you encounter this issue, please use a build from one of the released tar.gz files available in the releases section. 43 | 44 | ### Build from a release archive: 45 | The release archive has a complete Intel\* Quartus\* Prime Design Software project and associtated RTL and SDC scripts. If you are familiar or prefer this flow, please refer to the Intel\* Quartus\* Prime Design documentation available [here](https://www.altera.com/products/design-software/fpga-design/quartus-prime/overview.html). 46 | 47 | #### Release archive contents: 48 | 49 | * **de10-nano-base**: Intel\* Quartus\* Prime Design project for the Terasic DE10-Nano kit 50 | * **hps_isw_handoff**: prebuilt handoff files for the HPS 51 | * **output_files**: prebuild FPGA bitstream files (sof & rbf) 52 | * **preloader**: bsp-editor generated files for the HPS bootloader 53 | * **de10-nano-fft**: Intel\* Quartus\* Prime Design project for the Terasic DE10-Nano kit 54 | * **hps_isw_handoff**: prebuilt handoff files for the HPS 55 | * **output_files**: prebuild FPGA bitstream files (sof & rbf) 56 | * **preloader**: bsp-editor generated files for the HPS bootloader 57 | * **de10-nano-mandelbrot**: Intel\* Quartus\* Prime Design project for the Terasic DE10-Nano kit 58 | * **hps_isw_handoff**: prebuilt handoff files for the HPS 59 | * **output_files**: prebuild FPGA bitstream files (sof & rbf) 60 | * **preloader**: bsp-editor generated files for the HPS bootloader 61 | * **devicetrees**: devicetree overlay source and devicetree overlay binaries for the kits 62 | * **hdl_src**: RTL and SDC source 63 | * **ip**: Custom Intel\* Quartus\* QSYS\* components 64 | * **patches**: sopc2dts patches to add **BASIC** support for devicetree overlay generation 65 | * **Makefile**: Main Makefile for building the Terasic\* DE10-Nano-SoC projects 66 | * **mks**: Makefile fragments for various build outputs of the project. These are included in the main Makefile 67 | 68 | ### Build from release archives: 69 | 70 | For building the projects from the generated Intel\* Quartus\* Prime Design project and generated Intel\* Quartus\* QSYS\* system please read the design tools documentation. 71 | 72 | ### Build from GIT: 73 | 74 | The build has only been tested on a linux host, although there are no known reasons this will not work in a Cygwin shell. 75 | 76 | Please refer to 'make help' for all build targets, to build everything, simple make all. 77 | 78 | * Clone the repository: git clone https://github.com/intel/de10-nano-hardware.git 79 | * cd de10-nano-hardware 80 | * Ensure that you have the tools listed in the prerequisits in your path! 81 | * make all 82 | 83 | ### Preloader and u-Boot generation 84 | 85 | This example uses mainline u-Boot for the Intel\* Cyclone5\* FPGA. The repository for this is available [here](http://git.denx.de/?p=u-boot.git;a=summary). The build requires the bsp-editor preloader output created by the Intel\* SoCEDS\* tools. Please follow the [readme](http://git.denx.de/?p=u-boot.git;a=blob_plain;f=doc/README.socfpga;hb=HEAD) available in the repository for generation and creation of the appropriate files should you want to build it yourself. Please note that the linux build for the Terasic\* DE10-Nano-SoC does also build the bootloader. 86 | 87 | ### Verify Release Build authenticity 88 | 89 | To verify the signature of the release build download please do the following on a linux host: 90 | 91 | * Download the release tgz and sig.tgz from the release section of the github project 92 | * Extract the sig.tgz file to get only the sig file 93 | * Save the signing chain as a pem file 94 | openssl pkcs7 -print_certs -inform der \ 95 | -in de10-nano-build_.sig \ 96 | > de10-nano-build.pem 97 | * Verify the signing certificate 98 | openssl x509 \ 99 | -in de10-nano-build.pem \ 100 | -serial -noout 101 | 102 | The result should be: 103 | serial=56000003003F7A8C8F5DD497E1000000000300 104 | 105 | * Verify the signature of the file 106 | openssl smime -verify \ 107 | -in de10-nano-build_.sig \ 108 | -inform der \ 109 | -content de10-nano-build_.tgz \ 110 | -noverify de10-nano-build.pem > /dev/null 111 | 112 | ## Additional Resources 113 | * [Discover the Terasic DE10-Nano Kit](https://signin.intel.com/logout?target=https://software.intel.com/en-us/iot/hardware/fpga/de10-nano) 114 | * [Terasic DE10-Nano Get Started Guide](https://software.intel.com/en-us/terasic-de10-nano-get-started-guide) 115 | * [Project: My First FPGA](https://software.intel.com/en-us/articles/my-first-fpga) 116 | * [Learn more about Intel® FPGAs](https://software.intel.com/en-us/iot/hardware/fpga/) 117 | -------------------------------------------------------------------------------- /devicetrees/de10-nano-base.dtsi: -------------------------------------------------------------------------------- 1 | / { 2 | fragment@0 { 3 | __overlay__ { 4 | // These are the bridges used in the design 5 | fpga-bridges = <&fpga_bridge0 &fpga_bridge1>; 6 | 7 | // I need to update SOPC2DTS to somehow include the "right" 8 | // fpga generated clocks only. for now, just add the ones needed 9 | clk_0: clk_0 { 10 | compatible = "fixed-clock"; 11 | #clock-cells; 12 | clock-frequency; 13 | clock-output-names = "clk_0-clk"; 14 | }; 15 | 16 | custom_reset_synchronizer: custom_reset_synchronizer { 17 | compatible = "fixed-clock"; 18 | #clock-cells; 19 | clock-frequency; 20 | clock-output-names = "custom_reset_synchronizer-clk"; 21 | }; 22 | 23 | // Add gpio-leds definitions 24 | leds: leds { 25 | compatible = "gpio-leds"; 26 | 27 | led_fpga0: fpga0 { 28 | label = "fpga_led0"; 29 | gpios = <&led_pio 0 0>; 30 | }; //end fpga0 (led_fpga0) 31 | 32 | led_fpga1: fpga1 { 33 | label = "fpga_led1"; 34 | gpios = <&led_pio 1 0>; 35 | }; //end fpga1 (led_fpga1) 36 | 37 | led_fpga2: fpga2 { 38 | label = "fpga_led2"; 39 | gpios = <&led_pio 2 0>; 40 | }; //end fpga2 (led_fpga2) 41 | 42 | led_fpga3: fpga3 { 43 | label = "fpga_led3"; 44 | gpios = <&led_pio 3 0>; 45 | }; //end fpga3 (led_fpga3) 46 | 47 | led_fpga4: fpga4 { 48 | label = "fpga_led4"; 49 | gpios = <&led_pio 4 0>; 50 | }; 51 | 52 | led_fpga5: fpga5 { 53 | label = "fpga_led5"; 54 | gpios = <&led_pio 5 0>; 55 | }; 56 | 57 | led_fpga6: fpga6 { 58 | label = "fpga_led6"; 59 | gpios = <&led_pio 6 0>; 60 | }; 61 | 62 | led_fpga7: fpga7 { 63 | label = "fpga_led7"; 64 | gpios = <&led_pio 7 0>; 65 | }; 66 | }; 67 | 68 | //Add gpio keys definitions 69 | keys: keys { 70 | compatible = "gpio-keys"; 71 | #address-cells = <1>; 72 | #size-cells = <0>; 73 | 74 | SW0: SW0 { 75 | label = "SW0"; 76 | gpios = <&dipsw_pio 0 1>; 77 | linux,code = <64>; 78 | debounce-interval = <50>; 79 | }; 80 | 81 | SW1: SW1 { 82 | label = "SW1"; 83 | gpios = <&dipsw_pio 1 1>; 84 | linux,code = <65>; 85 | debounce-interval = <50>; 86 | }; 87 | 88 | SW2: SW2 { 89 | label = "SW2"; 90 | gpios = <&dipsw_pio 2 1>; 91 | linux,code = <66>; 92 | debounce-interval = <50>; 93 | }; 94 | 95 | SW3: SW3 { 96 | label = "SW3"; 97 | gpios = <&dipsw_pio 3 1>; 98 | linux,code = <67>; 99 | debounce-interval = <50>; 100 | }; 101 | }; 102 | }; 103 | }; 104 | 105 | // UART for Arduino Header 106 | fragment@1 { 107 | target-path = "/soc/serial1@ffc03000"; 108 | __overlay__ { 109 | status = "okay"; 110 | }; 111 | }; 112 | 113 | // I2C for HDMI 114 | fragment@2 { 115 | target-path = "/soc/i2c@ffc06000"; 116 | __overlay__ { 117 | status = "okay"; 118 | }; 119 | }; 120 | 121 | // I2C for Arduino Header 122 | fragment@3 { 123 | target-path = "/soc/i2c@ffc07000"; 124 | __overlay__ { 125 | status = "okay"; 126 | }; 127 | }; 128 | 129 | // SPI for Arduino Header 130 | fragment@4 { 131 | target-path = "/soc/spi@fff00000"; 132 | __overlay__ { 133 | num-cs = <1>; 134 | status = "okay"; 135 | spidev@0 { 136 | /* spidev causes a WARN_ON() so spoof with DAC compat */ 137 | compatible = "rohm,dh2228fv"; 138 | reg = <0>; /* chip select */ 139 | spi-max-frequency = <1000000>; 140 | enable-dma = <1>; 141 | }; 142 | }; 143 | }; 144 | 145 | // Set Model Name to reflect FPGA version 146 | fragment@5 { 147 | target-path = "/"; 148 | __overlay__ { 149 | model = "Terasic DE10-Nano Base"; 150 | }; 151 | }; 152 | }; 153 | -------------------------------------------------------------------------------- /devicetrees/de10-nano-fft.dtsi: -------------------------------------------------------------------------------- 1 | / { 2 | fragment@0 { 3 | #address-cells = <2>; 4 | #size-cells = <1>; 5 | __overlay__ { 6 | // These are the bridges used in the design 7 | fpga-bridges = <&fpga_bridge0 &fpga_bridge1>; 8 | 9 | // I need to update SOPC2DTS to somehow include the "right" 10 | // fpga generated clocks only. for now, just add the ones needed 11 | clk_0: clk_0 { 12 | compatible = "fixed-clock"; 13 | #clock-cells; 14 | clock-frequency; 15 | clock-output-names = "clk_0-clk"; 16 | }; 17 | 18 | fft_sub_clk_0: fft_sub_clk_0 { 19 | compatible = "fixed-clock"; 20 | #clock-cells; 21 | clock-frequency; 22 | clock-output-names = "fft_sub_clk_0-clk"; 23 | }; 24 | 25 | pll_stream: pll_stream { 26 | compatible = "fixed-clock"; 27 | #clock-cells; 28 | clock-frequency; 29 | clock-output-names = "pll_stream-clk"; 30 | }; 31 | 32 | custom_reset_synchronizer: custom_reset_synchronizer { 33 | compatible = "fixed-clock"; 34 | #clock-cells; 35 | clock-frequency; 36 | clock-output-names = "custom_reset_synchronizer-clk"; 37 | }; 38 | 39 | // Add gpio-leds definitions 40 | leds: leds { 41 | compatible = "gpio-leds"; 42 | 43 | led_fpga0: fpga0 { 44 | label = "fpga_led0"; 45 | gpios = <&led_pio 0 0>; 46 | }; //end fpga0 (led_fpga0) 47 | 48 | led_fpga1: fpga1 { 49 | label = "fpga_led1"; 50 | gpios = <&led_pio 1 0>; 51 | }; //end fpga1 (led_fpga1) 52 | 53 | led_fpga2: fpga2 { 54 | label = "fpga_led2"; 55 | gpios = <&led_pio 2 0>; 56 | }; //end fpga2 (led_fpga2) 57 | 58 | led_fpga3: fpga3 { 59 | label = "fpga_led3"; 60 | gpios = <&led_pio 3 0>; 61 | }; //end fpga3 (led_fpga3) 62 | 63 | led_fpga4: fpga4 { 64 | label = "fpga_led4"; 65 | gpios = <&led_pio 4 0>; 66 | }; 67 | 68 | led_fpga5: fpga5 { 69 | label = "fpga_led5"; 70 | gpios = <&led_pio 5 0>; 71 | }; 72 | 73 | led_fpga6: fpga6 { 74 | label = "fpga_led6"; 75 | gpios = <&led_pio 6 0>; 76 | }; 77 | 78 | led_fpga7: fpga7 { 79 | label = "fpga_led7"; 80 | gpios = <&led_pio 7 0>; 81 | }; 82 | }; 83 | 84 | //Add gpio keys definitions 85 | keys: keys { 86 | compatible = "gpio-keys"; 87 | #address-cells = <1>; 88 | #size-cells = <0>; 89 | 90 | SW0: SW0 { 91 | label = "SW0"; 92 | gpios = <&dipsw_pio 0 1>; 93 | linux,code = <64>; 94 | debounce-interval = <50>; 95 | }; 96 | 97 | SW1: SW1 { 98 | label = "SW1"; 99 | gpios = <&dipsw_pio 1 1>; 100 | linux,code = <65>; 101 | debounce-interval = <50>; 102 | }; 103 | 104 | SW2: SW2 { 105 | label = "SW2"; 106 | gpios = <&dipsw_pio 2 1>; 107 | linux,code = <66>; 108 | debounce-interval = <50>; 109 | }; 110 | 111 | SW3: SW3 { 112 | label = "SW3"; 113 | gpios = <&dipsw_pio 3 1>; 114 | linux,code = <67>; 115 | debounce-interval = <50>; 116 | }; 117 | }; 118 | }; 119 | }; 120 | 121 | // UART for Arduino Header 122 | fragment@1 { 123 | target-path = "/soc/serial1@ffc03000"; 124 | __overlay__ { 125 | status = "okay"; 126 | }; 127 | }; 128 | 129 | // I2C for HDMI 130 | fragment@2 { 131 | target-path = "/soc/i2c@ffc06000"; 132 | __overlay__ { 133 | status = "okay"; 134 | }; 135 | }; 136 | 137 | // I2C for Arduino Header 138 | fragment@3 { 139 | target-path = "/soc/i2c@ffc07000"; 140 | __overlay__ { 141 | status = "okay"; 142 | }; 143 | }; 144 | 145 | // SPI for Arduino Header 146 | fragment@4 { 147 | target-path = "/soc/spi@fff00000"; 148 | __overlay__ { 149 | #address-cells = <1>; 150 | #size-cells = <1>; 151 | num-cs = <1>; 152 | status = "okay"; 153 | spidev@0 { 154 | /* spidev causes a WARN_ON() so spoof with DAC compat */ 155 | compatible = "rohm,dh2228fv"; 156 | reg = <0>; /* chip select */ 157 | spi-max-frequency = <1000000>; 158 | enable-dma = <1>; 159 | }; 160 | }; 161 | }; 162 | 163 | // Set Model Name to reflect FPGA version 164 | fragment@5 { 165 | target-path = "/"; 166 | __overlay__ { 167 | model = "Terasic DE10-Nano FFT"; 168 | }; 169 | }; 170 | 171 | // Add Framebuffer defaults 172 | fragment@6 { 173 | target-path = "/soc"; 174 | __overlay__ { 175 | #address-cells = <1>; 176 | #size-cells = <1>; 177 | framebuffer@3F000000 { 178 | compatible = "simple-framebuffer"; 179 | reg = <0x3F000000 8294400>; 180 | format = "x8r8g8b8"; 181 | width = <1024>; 182 | height = <768>; 183 | stride = <4096>; 184 | }; 185 | }; 186 | }; 187 | fragment@7 { 188 | target-path = "/chosen"; 189 | __overlay__ { 190 | stdout-path = "display0"; 191 | }; 192 | }; 193 | fragment@8 { 194 | target-path = "/aliases"; 195 | __overlay__ { 196 | display0 = "/soc/framebuffer@3F000000"; 197 | }; 198 | }; 199 | }; 200 | -------------------------------------------------------------------------------- /devicetrees/de10-nano-mandelbrot.dtsi: -------------------------------------------------------------------------------- 1 | / { 2 | fragment@0 { 3 | #address-cells = <2>; 4 | #size-cells = <1>; 5 | __overlay__ { 6 | // These are the bridges used in the design 7 | fpga-bridges = <&fpga_bridge0 &fpga_bridge1>; 8 | 9 | // I need to update SOPC2DTS to somehow include the "right" 10 | // fpga generated clocks only. for now, just add the ones needed 11 | clk_0: clk_0 { 12 | compatible = "fixed-clock"; 13 | #clock-cells; 14 | clock-frequency; 15 | clock-output-names = "clk_0-clk"; 16 | }; 17 | 18 | mandelbrot_clk: mandelbrot_clk { 19 | compatible = "fixed-clock"; 20 | #clock-cells; 21 | clock-frequency; 22 | clock-output-names = "mandelbrot_clk-clk"; 23 | }; 24 | 25 | pll_stream: pll_stream { 26 | compatible = "fixed-clock"; 27 | #clock-cells; 28 | clock-frequency; 29 | clock-output-names = "pll_stream-clk"; 30 | }; 31 | 32 | custom_reset_synchronizer: custom_reset_synchronizer { 33 | compatible = "fixed-clock"; 34 | #clock-cells; 35 | clock-frequency; 36 | clock-output-names = "custom_reset_synchronizer-clk"; 37 | }; 38 | 39 | // Add gpio-leds definitions 40 | leds: leds { 41 | compatible = "gpio-leds"; 42 | 43 | led_fpga0: fpga0 { 44 | label = "fpga_led0"; 45 | gpios = <&led_pio 0 0>; 46 | }; //end fpga0 (led_fpga0) 47 | 48 | led_fpga1: fpga1 { 49 | label = "fpga_led1"; 50 | gpios = <&led_pio 1 0>; 51 | }; //end fpga1 (led_fpga1) 52 | 53 | led_fpga2: fpga2 { 54 | label = "fpga_led2"; 55 | gpios = <&led_pio 2 0>; 56 | }; //end fpga2 (led_fpga2) 57 | 58 | led_fpga3: fpga3 { 59 | label = "fpga_led3"; 60 | gpios = <&led_pio 3 0>; 61 | }; //end fpga3 (led_fpga3) 62 | 63 | led_fpga4: fpga4 { 64 | label = "fpga_led4"; 65 | gpios = <&led_pio 4 0>; 66 | }; 67 | 68 | led_fpga5: fpga5 { 69 | label = "fpga_led5"; 70 | gpios = <&led_pio 5 0>; 71 | }; 72 | 73 | led_fpga6: fpga6 { 74 | label = "fpga_led6"; 75 | gpios = <&led_pio 6 0>; 76 | }; 77 | 78 | led_fpga7: fpga7 { 79 | label = "fpga_led7"; 80 | gpios = <&led_pio 7 0>; 81 | }; 82 | }; 83 | 84 | //Add gpio keys definitions 85 | keys: keys { 86 | compatible = "gpio-keys"; 87 | #address-cells = <1>; 88 | #size-cells = <0>; 89 | 90 | SW0: SW0 { 91 | label = "SW0"; 92 | gpios = <&dipsw_pio 0 1>; 93 | linux,code = <64>; 94 | debounce-interval = <50>; 95 | }; 96 | 97 | SW1: SW1 { 98 | label = "SW1"; 99 | gpios = <&dipsw_pio 1 1>; 100 | linux,code = <65>; 101 | debounce-interval = <50>; 102 | }; 103 | 104 | SW2: SW2 { 105 | label = "SW2"; 106 | gpios = <&dipsw_pio 2 1>; 107 | linux,code = <66>; 108 | debounce-interval = <50>; 109 | }; 110 | 111 | SW3: SW3 { 112 | label = "SW3"; 113 | gpios = <&dipsw_pio 3 1>; 114 | linux,code = <67>; 115 | debounce-interval = <50>; 116 | }; 117 | }; 118 | }; 119 | }; 120 | 121 | // UART for Arduino Header 122 | fragment@1 { 123 | target-path = "/soc/serial1@ffc03000"; 124 | __overlay__ { 125 | status = "okay"; 126 | }; 127 | }; 128 | 129 | // I2C for HDMI 130 | fragment@2 { 131 | target-path = "/soc/i2c@ffc06000"; 132 | __overlay__ { 133 | status = "okay"; 134 | }; 135 | }; 136 | 137 | // I2C for Arduino Header 138 | fragment@3 { 139 | target-path = "/soc/i2c@ffc07000"; 140 | __overlay__ { 141 | status = "okay"; 142 | }; 143 | }; 144 | 145 | // SPI for Arduino Header 146 | fragment@4 { 147 | target-path = "/soc/spi@fff00000"; 148 | __overlay__ { 149 | num-cs = <1>; 150 | status = "okay"; 151 | spidev@0 { 152 | /* spidev causes a WARN_ON() so spoof with DAC compat */ 153 | compatible = "rohm,dh2228fv"; 154 | reg = <0>; /* chip select */ 155 | spi-max-frequency = <1000000>; 156 | enable-dma = <1>; 157 | }; 158 | }; 159 | }; 160 | 161 | // Set Model Name to reflect FPGA version 162 | fragment@5 { 163 | target-path = "/"; 164 | __overlay__ { 165 | model = "Terasic DE10-Nano Mandelbrot"; 166 | }; 167 | }; 168 | 169 | // Add Framebuffer defaults 170 | fragment@6 { 171 | target-path = "/soc"; 172 | __overlay__ { 173 | #address-cells = <1>; 174 | #size-cells = <1>; 175 | framebuffer@3F000000 { 176 | compatible = "simple-framebuffer"; 177 | reg = <0x3F000000 8294400>; 178 | format = "x8r8g8b8"; 179 | width = <1024>; 180 | height = <768>; 181 | stride = <4096>; 182 | }; 183 | }; 184 | }; 185 | fragment@7 { 186 | target-path = "/chosen"; 187 | __overlay__ { 188 | stdout-path = "display0"; 189 | }; 190 | }; 191 | fragment@8 { 192 | target-path = "/aliases"; 193 | __overlay__ { 194 | display0 = "/soc/framebuffer@3F000000"; 195 | }; 196 | }; 197 | }; 198 | -------------------------------------------------------------------------------- /hdl_src/soc_system_hdmi_i2c_only.sdc: -------------------------------------------------------------------------------- 1 | # The MIT License (MIT) 2 | # Copyright (c) 2016 Intel Corporation 3 | # 4 | # Permission is hereby granted, free of charge, to any person obtaining a copy 5 | # of this software and associated documentation files (the "Software"), to deal 6 | # in the Software without restriction, including without limitation the rights 7 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | # copies of the Software, and to permit persons to whom the Software is 9 | # furnished to do so, subject to the following conditions: 10 | # 11 | # The above copyright notice and this permission notice shall be included in 12 | # all copies or substantial portions of the Software. 13 | # 14 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 | # THE SOFTWARE. 21 | 22 | #************************************************************** 23 | # Create I2C clocks 24 | #************************************************************** 25 | create_clock -period "1 MHz" [get_ports hdmi_i2c_scl] 26 | 27 | # I2C IO 28 | set_input_delay -clock [get_clocks {hdmi_i2c_scl}] 10 [get_ports {hdmi_i2c_sda}] 29 | set_output_delay -clock [get_clocks {hdmi_i2c_scl}] 10 [get_ports {hdmi_i2c_sda}] 30 | 31 | -------------------------------------------------------------------------------- /hdl_src/soc_system_hdmi_timing.sdc: -------------------------------------------------------------------------------- 1 | # The MIT License (MIT) 2 | # Copyright (c) 2016 Intel Corporation 3 | # 4 | # Permission is hereby granted, free of charge, to any person obtaining a copy 5 | # of this software and associated documentation files (the "Software"), to deal 6 | # in the Software without restriction, including without limitation the rights 7 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | # copies of the Software, and to permit persons to whom the Software is 9 | # furnished to do so, subject to the following conditions: 10 | # 11 | # The above copyright notice and this permission notice shall be included in 12 | # all copies or substantial portions of the Software. 13 | # 14 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 | # THE SOFTWARE. 21 | 22 | # create PLL output clocks, 148.5MHz and 60MHz 23 | 24 | # 148MHz VCO 25 | create_generated_clock \ 26 | -add \ 27 | -name {vco_for_148} \ 28 | -source [get_pins {soc_inst|pll_stream|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin}] \ 29 | -multiply_by 4563 \ 30 | -divide_by 512 \ 31 | -master_clock {fpga_clk1_50} \ 32 | [get_pins {soc_inst|pll_stream|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]}] 33 | 34 | # 60MHz VCO 35 | create_generated_clock \ 36 | -add \ 37 | -name {vco_for_60} \ 38 | -source [get_pins {soc_inst|pll_stream|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin}] \ 39 | -multiply_by 2151 \ 40 | -divide_by 256 \ 41 | -master_clock {fpga_clk1_50} \ 42 | [get_pins {soc_inst|pll_stream|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]}] 43 | 44 | # Create PLL output based off 148MHz VCO 45 | create_generated_clock \ 46 | -add \ 47 | -name {pll_clk_148} \ 48 | -source [get_pins {soc_inst|pll_stream|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]}] \ 49 | -multiply_by 1 \ 50 | -divide_by 3 \ 51 | -master_clock {vco_for_148} \ 52 | [get_pins {soc_inst|pll_stream|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] 53 | 54 | # Create PLL output based off 60MHz VCO 55 | create_generated_clock \ 56 | -add \ 57 | -name {pll_clk_60} \ 58 | -source [get_pins {soc_inst|pll_stream|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]}] \ 59 | -multiply_by 1 \ 60 | -divide_by 7 \ 61 | -master_clock {vco_for_60} \ 62 | [get_pins {soc_inst|pll_stream|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] 63 | 64 | # Cut paths between two clocks on the same PLL output tap 65 | set_clock_groups \ 66 | -exclusive \ 67 | -group [get_clocks {pll_clk_148}] \ 68 | -group [get_clocks {pll_clk_60}] 69 | 70 | derive_clock_uncertainty 71 | 72 | #************************************************************** 73 | # Create HDMI and I2C clocks 74 | #************************************************************** 75 | set HDMI_CLK {soc_inst|pll_stream|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} 76 | create_generated_clock -add -name {hdmi_tx_clk148} -master_clock {pll_clk_148} -source [get_pins ${HDMI_CLK}] [get_ports hdmi_tx_clk] 77 | create_clock -period "1 MHz" [get_ports hdmi_i2c_scl] 78 | 79 | set_clock_groups -exclusive -group {pll_clk_60} -group {hdmi_tx_clk148} 80 | 81 | # I2C IO 82 | set_input_delay -clock [get_clocks {hdmi_i2c_scl}] 10 [get_ports {hdmi_i2c_sda}] 83 | set_output_delay -clock [get_clocks {hdmi_i2c_scl}] 10 [get_ports {hdmi_i2c_sda}] 84 | 85 | # Video IO 86 | set HDMI_CLK_PERIOD [get_clock_info -period [get_clocks hdmi_tx_clk148]] 87 | set HDMI_TSU 1.0 88 | set HDMI_TH 0.7 89 | set HDMI_PAD 0.3 90 | set HDMI_MAX [expr ${HDMI_CLK_PERIOD} - ${HDMI_TSU} - ${HDMI_PAD}] 91 | set HDMI_MIN [expr ${HDMI_CLK_PERIOD} + ${HDMI_TH} + ${HDMI_PAD}] 92 | 93 | post_message -type info [format "HDMI_MAX = %f" ${HDMI_MAX}] 94 | post_message -type info [format "HDMI_MIN = %f" ${HDMI_MIN}] 95 | 96 | set_output_delay -clock [get_clocks hdmi_tx_clk148] -max ${HDMI_MAX} [get_ports {hdmi_tx_d[*]}] 97 | set_output_delay -clock [get_clocks hdmi_tx_clk148] -min ${HDMI_MIN} [get_ports {hdmi_tx_d[*]}] 98 | 99 | set_output_delay -clock [get_clocks hdmi_tx_clk148] -max ${HDMI_MAX} [get_ports {hdmi_tx_de}] 100 | set_output_delay -clock [get_clocks hdmi_tx_clk148] -min ${HDMI_MIN} [get_ports {hdmi_tx_de}] 101 | 102 | set_output_delay -clock [get_clocks hdmi_tx_clk148] -max ${HDMI_MAX} [get_ports {hdmi_tx_hs}] 103 | set_output_delay -clock [get_clocks hdmi_tx_clk148] -min ${HDMI_MIN} [get_ports {hdmi_tx_hs}] 104 | 105 | set_output_delay -clock [get_clocks hdmi_tx_clk148] -max ${HDMI_MAX} [get_ports {hdmi_tx_vs}] 106 | set_output_delay -clock [get_clocks hdmi_tx_clk148] -min ${HDMI_MIN} [get_ports {hdmi_tx_vs}] 107 | 108 | -------------------------------------------------------------------------------- /hdl_src/soc_system_mandelbrot_timing.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2017 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | # create PLL output clock, 70MHz 5 | 6 | # 70MHz VCO 7 | create_generated_clock \ 8 | -add \ 9 | -name {vco_for_70} \ 10 | -source [get_pins {soc_inst|pll_70m|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] \ 11 | -multiply_by 14 \ 12 | -divide_by 2 \ 13 | -master_clock {fpga_clk1_50} \ 14 | [get_pins {soc_inst|pll_70m|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] 15 | 16 | # Create PLL output based off 70MHz VCO 17 | create_generated_clock \ 18 | -add \ 19 | -name {pll_clk_70} \ 20 | -source [get_pins {soc_inst|pll_70m|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ 21 | -multiply_by 1 \ 22 | -divide_by 5 \ 23 | -master_clock {vco_for_70} \ 24 | [get_pins {soc_inst|pll_70m|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] 25 | 26 | -------------------------------------------------------------------------------- /ip/FFT_STadapter/fft_adapter.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016 Intel Corporation 2 | // SPDX-License-Identifier: MIT 3 | 4 | // fft_adapter.v 5 | 6 | // This file was auto-generated as a prototype implementation of a module 7 | // created in component editor. It ties off all outputs to ground and 8 | // ignores all inputs. It needs to be edited to make it do something 9 | // useful. 10 | // 11 | // This file will not be automatically regenerated. You should check it in 12 | // to your version control system if you want to keep it. 13 | 14 | `timescale 1 ps / 1 ps 15 | module fft_adapter #( 16 | parameter FFT_IN_WIDTH = 16, 17 | parameter FFT_OUT_WIDTH = 24, 18 | parameter SIZE_WIDTH = 11 19 | ) ( 20 | output wire asi_in0_ready, // in0.ready 21 | input wire asi_in0_valid, // .valid 22 | input wire asi_in0_startofpacket, // .startofpacket 23 | input wire asi_in0_endofpacket, // .endofpacket 24 | input wire [1:0] asi_in0_error, // .error 25 | input wire [1:0] asi_in0_empty, // .empty 26 | input wire [(2*FFT_IN_WIDTH)-1:0] asi_in0_data, // .data 27 | input wire clk, // clock.clk 28 | input wire reset, // reset.reset 29 | output wire [63:0] aso_out0_data, // out0.data 30 | input wire aso_out0_ready, // .ready 31 | output wire aso_out0_valid, // .valid 32 | output wire aso_out0_startofpacket, // .startofpacket 33 | output wire aso_out0_endofpacket, // .endofpacket 34 | output wire [1:0] aso_out0_error, // .error 35 | output wire [2:0] aso_out0_empty, // .empty 36 | input wire [2*FFT_OUT_WIDTH +SIZE_WIDTH -1:0] asi_fromfft_data, // from_fft.data 37 | output wire asi_fromfft_ready, // .ready 38 | input wire asi_fromfft_valid, // .valid 39 | input wire asi_fromfft_startofpacket, // .startofpacket 40 | input wire asi_fromfft_endofpacket, // .endofpacket 41 | input wire [1:0] asi_fromfft_error, // .error 42 | output wire [(2*FFT_IN_WIDTH) + SIZE_WIDTH :0] aso_tofft_data, // to_fft.data 43 | input wire aso_tofft_ready, // .ready 44 | output wire aso_tofft_valid, // .valid 45 | output wire aso_tofft_startofpacket, // .startofpacket 46 | output wire aso_tofft_endofpacket, // .endofpacket 47 | output wire [1:0] aso_tofft_error, // .error 48 | input wire [1:0] avs_s0_address, // csr.address 49 | input wire avs_s0_read, // .read 50 | output wire [31:0] avs_s0_readdata, // .readdata 51 | input wire avs_s0_write, // .write 52 | input wire [31:0] avs_s0_writedata // .writedata 53 | ); 54 | 55 | // TODO: Auto-generated HDL template 56 | //assign fft_ii_0_source_data = { fft_ii_0_source_real[23:0], fft_ii_0_source_imag[23:0], fft_ii_0_fftpts_out[10:0] }; 57 | wire [31:0] source_real; 58 | wire [31:0] source_imag; 59 | reg [SIZE_WIDTH-1:0] size_register; 60 | reg direction_register; 61 | 62 | //CSR registger 63 | //size register. 64 | always @ (posedge clk or posedge reset) 65 | begin 66 | if (reset) 67 | size_register <= 128; 68 | else 69 | if ((avs_s0_address ==0) && avs_s0_write) 70 | size_register <= avs_s0_writedata[SIZE_WIDTH-1:0]; 71 | end 72 | 73 | //direction register 74 | always @ (posedge clk or posedge reset) 75 | begin 76 | if (reset) 77 | direction_register <= 0; 78 | else 79 | if ((avs_s0_address ==1) && avs_s0_write) 80 | direction_register <= avs_s0_writedata[0]; 81 | end 82 | 83 | // read back path 84 | assign avs_s0_readdata = avs_s0_address[0]?{{31{1'b0}},direction_register}: {{31-SIZE_WIDTH{1'b0}}, size_register} ; 85 | 86 | 87 | //strip off the real and imaginary parts and sign extend the data. 88 | assign source_real = {{32-FFT_OUT_WIDTH{asi_fromfft_data[SIZE_WIDTH +2*FFT_OUT_WIDTH -1]}},asi_fromfft_data[SIZE_WIDTH +2*FFT_OUT_WIDTH -1:SIZE_WIDTH +FFT_OUT_WIDTH]}; 89 | assign source_imag = {{32-FFT_OUT_WIDTH{asi_fromfft_data[SIZE_WIDTH +FFT_OUT_WIDTH -1]}},asi_fromfft_data[SIZE_WIDTH +FFT_OUT_WIDTH -1:SIZE_WIDTH]}; 90 | 91 | // little endian conversion. 92 | assign aso_out0_data = {source_real[7:0],source_real[15:8],source_real[23:16],source_real[31:24], 93 | source_imag[7:0],source_imag[15:8],source_imag[23:16],source_imag[31:24]}; // out0.data 94 | 95 | // signal going out to the sgdma. 96 | assign aso_out0_empty = 3'b000; 97 | 98 | assign aso_out0_valid = asi_fromfft_valid; 99 | 100 | assign aso_out0_startofpacket = asi_fromfft_startofpacket; 101 | 102 | assign aso_out0_endofpacket = asi_fromfft_endofpacket; 103 | 104 | assign aso_out0_error = asi_fromfft_error; 105 | 106 | 107 | assign asi_fromfft_ready = aso_out0_ready; 108 | 109 | // signals going to the fft. 110 | 111 | assign asi_in0_ready = aso_tofft_ready; 112 | 113 | assign aso_tofft_valid = asi_in0_valid; 114 | 115 | // need an endian conversion as well. 116 | // assign aso_tofft_data = {asi_in0_data[7:0], asi_in0_data[15:8], asi_in0_data[23:16], asi_in0_data[31:24], size_register, direction_register}; 117 | // needed to shift the real and imaginary part for version 1.1 118 | assign aso_tofft_data = {asi_in0_data[23:16], asi_in0_data[31:24], asi_in0_data[7:0], asi_in0_data[15:8], size_register, direction_register}; 119 | 120 | assign aso_tofft_startofpacket = asi_in0_startofpacket; 121 | 122 | assign aso_tofft_endofpacket = asi_in0_endofpacket; 123 | 124 | assign aso_tofft_error = asi_in0_error; 125 | 126 | // assign aso_tofft_empty = asi_in0_empty; // fft does not need empty 127 | 128 | 129 | 130 | 131 | endmodule 132 | -------------------------------------------------------------------------------- /ip/avst_mandelbrot_engine/avst_mandelbrot_engine_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 16.1 5 | 6 | # 7 | # module avst_mandelbrot_engine 8 | # 9 | set_module_property DESCRIPTION "" 10 | set_module_property NAME avst_mandelbrot_engine 11 | set_module_property VERSION 1.0 12 | set_module_property INTERNAL false 13 | set_module_property OPAQUE_ADDRESS_MAP true 14 | set_module_property AUTHOR RSF 15 | set_module_property DISPLAY_NAME avst_mandelbrot_engine 16 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 17 | set_module_property EDITABLE false 18 | set_module_property REPORT_TO_TALKBACK false 19 | set_module_property ALLOW_GREYBOX_GENERATION false 20 | set_module_property REPORT_HIERARCHY false 21 | 22 | 23 | # 24 | # file sets 25 | # 26 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 27 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL avst_mandelbrot_engine 28 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 29 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 30 | add_fileset_file avst_mandelbrot_engine.v VERILOG PATH avst_mandelbrot_engine.v TOP_LEVEL_FILE 31 | 32 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 33 | set_fileset_property SIM_VERILOG TOP_LEVEL avst_mandelbrot_engine 34 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 35 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false 36 | add_fileset_file avst_mandelbrot_engine.v VERILOG PATH avst_mandelbrot_engine.v 37 | 38 | 39 | # 40 | # parameters 41 | # 42 | 43 | 44 | # 45 | # display items 46 | # 47 | 48 | 49 | # 50 | # connection point clock 51 | # 52 | add_interface clock clock end 53 | set_interface_property clock clockRate 0 54 | set_interface_property clock ENABLED true 55 | set_interface_property clock EXPORT_OF "" 56 | set_interface_property clock PORT_NAME_MAP "" 57 | set_interface_property clock CMSIS_SVD_VARIABLES "" 58 | set_interface_property clock SVD_ADDRESS_GROUP "" 59 | 60 | add_interface_port clock clk clk Input 1 61 | 62 | 63 | # 64 | # connection point reset 65 | # 66 | add_interface reset reset end 67 | set_interface_property reset associatedClock clock 68 | set_interface_property reset synchronousEdges DEASSERT 69 | set_interface_property reset ENABLED true 70 | set_interface_property reset EXPORT_OF "" 71 | set_interface_property reset PORT_NAME_MAP "" 72 | set_interface_property reset CMSIS_SVD_VARIABLES "" 73 | set_interface_property reset SVD_ADDRESS_GROUP "" 74 | 75 | add_interface_port reset reset reset Input 1 76 | 77 | 78 | # 79 | # connection point in_vector 80 | # 81 | add_interface in_vector avalon_streaming end 82 | set_interface_property in_vector associatedClock clock 83 | set_interface_property in_vector associatedReset reset 84 | set_interface_property in_vector dataBitsPerSymbol 8 85 | set_interface_property in_vector errorDescriptor "" 86 | set_interface_property in_vector firstSymbolInHighOrderBits true 87 | set_interface_property in_vector maxChannel 0 88 | set_interface_property in_vector readyLatency 0 89 | set_interface_property in_vector ENABLED true 90 | set_interface_property in_vector EXPORT_OF "" 91 | set_interface_property in_vector PORT_NAME_MAP "" 92 | set_interface_property in_vector CMSIS_SVD_VARIABLES "" 93 | set_interface_property in_vector SVD_ADDRESS_GROUP "" 94 | 95 | add_interface_port in_vector snk_data data Input 80 96 | add_interface_port in_vector snk_ready ready Output 1 97 | add_interface_port in_vector snk_valid valid Input 1 98 | 99 | 100 | # 101 | # connection point out_result 102 | # 103 | add_interface out_result avalon_streaming start 104 | set_interface_property out_result associatedClock clock 105 | set_interface_property out_result associatedReset reset 106 | set_interface_property out_result dataBitsPerSymbol 8 107 | set_interface_property out_result errorDescriptor "" 108 | set_interface_property out_result firstSymbolInHighOrderBits true 109 | set_interface_property out_result maxChannel 0 110 | set_interface_property out_result readyLatency 0 111 | set_interface_property out_result ENABLED true 112 | set_interface_property out_result EXPORT_OF "" 113 | set_interface_property out_result PORT_NAME_MAP "" 114 | set_interface_property out_result CMSIS_SVD_VARIABLES "" 115 | set_interface_property out_result SVD_ADDRESS_GROUP "" 116 | 117 | add_interface_port out_result src_data data Output 16 118 | add_interface_port out_result src_ready ready Input 1 119 | add_interface_port out_result src_valid valid Output 1 120 | 121 | -------------------------------------------------------------------------------- /ip/axi_bridge_for_acp_128/axi_bridge_for_acp_128.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016 Intel Corporation 2 | // SPDX-License-Identifier: MIT 3 | 4 | // 5 | // This component is a simple AXI3 pass through bridge with 128-bit data path 6 | // and 32-bit address bus. The intent of this component is to simply condition 7 | // the ARCACHE, ARPROT, ARUSER, AWCACHE, AWPROT, and AWUSER ports to drive an 8 | // acceptable pattern into the HPS F2S bridge for accesses that are targeting 9 | // the ACP port of the Cortex A9 cluster. 10 | // 11 | 12 | `timescale 1 ps / 1 ps 13 | module axi_bridge_for_acp_128 ( 14 | input wire clk, // clock.clk 15 | input wire reset, // reset.reset 16 | 17 | output wire [31:0] axm_m0_araddr, // m0.araddr 18 | output wire [1:0] axm_m0_arburst, // .arburst 19 | output wire [3:0] axm_m0_arcache, // .arcache 20 | output wire [7:0] axm_m0_arid, // .arid 21 | output wire [3:0] axm_m0_arlen, // .arlen 22 | output wire [1:0] axm_m0_arlock, // .arlock 23 | output wire [2:0] axm_m0_arprot, // .arprot 24 | input wire axm_m0_arready, // .arready 25 | output wire [2:0] axm_m0_arsize, // .arsize 26 | output wire [4:0] axm_m0_aruser, // .aruser 27 | output wire axm_m0_arvalid, // .arvalid 28 | output wire [31:0] axm_m0_awaddr, // .awaddr 29 | output wire [1:0] axm_m0_awburst, // .awburst 30 | output wire [3:0] axm_m0_awcache, // .awcache 31 | output wire [7:0] axm_m0_awid, // .awid 32 | output wire [3:0] axm_m0_awlen, // .awlen 33 | output wire [1:0] axm_m0_awlock, // .awlock 34 | output wire [2:0] axm_m0_awprot, // .awprot 35 | input wire axm_m0_awready, // .awready 36 | output wire [2:0] axm_m0_awsize, // .awsize 37 | output wire [4:0] axm_m0_awuser, // .awuser 38 | output wire axm_m0_awvalid, // .awvalid 39 | input wire [7:0] axm_m0_bid, // .bid 40 | output wire axm_m0_bready, // .bready 41 | input wire [1:0] axm_m0_bresp, // .bresp 42 | input wire axm_m0_bvalid, // .bvalid 43 | input wire [127:0] axm_m0_rdata, // .rdata 44 | input wire [7:0] axm_m0_rid, // .rid 45 | input wire axm_m0_rlast, // .rlast 46 | output wire axm_m0_rready, // .rready 47 | input wire [1:0] axm_m0_rresp, // .rresp 48 | input wire axm_m0_rvalid, // .rvalid 49 | output wire [127:0] axm_m0_wdata, // .wdata 50 | output wire [7:0] axm_m0_wid, // .wid 51 | output wire axm_m0_wlast, // .wlast 52 | input wire axm_m0_wready, // .wready 53 | output wire [15:0] axm_m0_wstrb, // .wstrb 54 | output wire axm_m0_wvalid, // .wvalid 55 | 56 | input wire [31:0] axs_s0_araddr, // s0.araddr 57 | input wire [1:0] axs_s0_arburst, // .arburst 58 | input wire [3:0] axs_s0_arcache, // .arcache 59 | input wire [7:0] axs_s0_arid, // .arid 60 | input wire [3:0] axs_s0_arlen, // .arlen 61 | input wire [1:0] axs_s0_arlock, // .arlock 62 | input wire [2:0] axs_s0_arprot, // .arprot 63 | output wire axs_s0_arready, // .arready 64 | input wire [2:0] axs_s0_arsize, // .arsize 65 | input wire [4:0] axs_s0_aruser, // .aruser 66 | input wire axs_s0_arvalid, // .arvalid 67 | input wire [31:0] axs_s0_awaddr, // .awaddr 68 | input wire [1:0] axs_s0_awburst, // .awburst 69 | input wire [3:0] axs_s0_awcache, // .awcache 70 | input wire [7:0] axs_s0_awid, // .awid 71 | input wire [3:0] axs_s0_awlen, // .awlen 72 | input wire [1:0] axs_s0_awlock, // .awlock 73 | input wire [2:0] axs_s0_awprot, // .awprot 74 | output wire axs_s0_awready, // .awready 75 | input wire [2:0] axs_s0_awsize, // .awsize 76 | input wire [4:0] axs_s0_awuser, // .awuser 77 | input wire axs_s0_awvalid, // .awvalid 78 | output wire [7:0] axs_s0_bid, // .bid 79 | input wire axs_s0_bready, // .bready 80 | output wire [1:0] axs_s0_bresp, // .bresp 81 | output wire axs_s0_bvalid, // .bvalid 82 | output wire [127:0] axs_s0_rdata, // .rdata 83 | output wire [7:0] axs_s0_rid, // .rid 84 | output wire axs_s0_rlast, // .rlast 85 | input wire axs_s0_rready, // .rready 86 | output wire [1:0] axs_s0_rresp, // .rresp 87 | output wire axs_s0_rvalid, // .rvalid 88 | input wire [127:0] axs_s0_wdata, // .wdata 89 | input wire [7:0] axs_s0_wid, // .wid 90 | input wire axs_s0_wlast, // .wlast 91 | output wire axs_s0_wready, // .wready 92 | input wire [15:0] axs_s0_wstrb, // .wstrb 93 | input wire axs_s0_wvalid // .wvalid 94 | ); 95 | 96 | assign axm_m0_araddr = axs_s0_araddr; 97 | assign axm_m0_arburst = axs_s0_arburst; 98 | assign axm_m0_arcache = 4'b1111; 99 | assign axm_m0_arid = axs_s0_arid; 100 | assign axm_m0_arlen = axs_s0_arlen; 101 | assign axm_m0_arlock = axs_s0_arlock; 102 | assign axm_m0_arprot = 3'b000; 103 | assign axm_m0_arsize = axs_s0_arsize; 104 | assign axm_m0_aruser = 5'b00001; 105 | assign axm_m0_arvalid = axs_s0_arvalid; 106 | assign axm_m0_awaddr = axs_s0_awaddr; 107 | assign axm_m0_awburst = axs_s0_awburst; 108 | assign axm_m0_awcache = 4'b1111; 109 | assign axm_m0_awid = axs_s0_awid; 110 | assign axm_m0_awlen = axs_s0_awlen; 111 | assign axm_m0_awlock = axs_s0_awlock; 112 | assign axm_m0_awprot = 3'b000; 113 | assign axm_m0_awsize = axs_s0_awsize; 114 | assign axm_m0_awuser = 5'b00001; 115 | assign axm_m0_awvalid = axs_s0_awvalid; 116 | assign axm_m0_bready = axs_s0_bready; 117 | assign axm_m0_rready = axs_s0_rready; 118 | assign axm_m0_wdata = axs_s0_wdata; 119 | assign axm_m0_wid = axs_s0_wid; 120 | assign axm_m0_wlast = axs_s0_wlast; 121 | assign axm_m0_wstrb = axs_s0_wstrb; 122 | assign axm_m0_wvalid = axs_s0_wvalid; 123 | assign axs_s0_arready = axm_m0_arready; 124 | assign axs_s0_awready = axm_m0_awready; 125 | assign axs_s0_bid = axm_m0_bid; 126 | assign axs_s0_bresp = axm_m0_bresp; 127 | assign axs_s0_bvalid = axm_m0_bvalid; 128 | assign axs_s0_rdata = axm_m0_rdata; 129 | assign axs_s0_rid = axm_m0_rid; 130 | assign axs_s0_rlast = axm_m0_rlast; 131 | assign axs_s0_rresp = axm_m0_rresp; 132 | assign axs_s0_rvalid = axm_m0_rvalid; 133 | assign axs_s0_wready = axm_m0_wready; 134 | 135 | endmodule 136 | 137 | -------------------------------------------------------------------------------- /ip/axi_bridge_for_acp_128/axi_bridge_for_acp_128_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | # axi_bridge_for_acp_128 "axi_bridge_for_acp_128" v1.0 5 | # RSF 2015.03.21.02:13:37 6 | # Simple AXI3 bridge to condition CACHE, PROT and USER ports for ACP operation. 7 | # 8 | 9 | # 10 | # request TCL package from ACDS 14.1 11 | # 12 | package require -exact qsys 14.1 13 | 14 | 15 | # 16 | # module axi_bridge_for_acp_128 17 | # 18 | set_module_property DESCRIPTION "Simple AXI3 bridge to condition CACHE, PROT and USER ports for ACP operation." 19 | set_module_property NAME axi_bridge_for_acp_128 20 | set_module_property VERSION 1.0 21 | set_module_property INTERNAL false 22 | set_module_property OPAQUE_ADDRESS_MAP true 23 | set_module_property AUTHOR RSF 24 | set_module_property DISPLAY_NAME axi_bridge_for_acp_128 25 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 26 | set_module_property EDITABLE true 27 | set_module_property REPORT_TO_TALKBACK false 28 | set_module_property ALLOW_GREYBOX_GENERATION false 29 | set_module_property REPORT_HIERARCHY false 30 | 31 | 32 | # 33 | # file sets 34 | # 35 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 36 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL axi_bridge_for_acp_128 37 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 38 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 39 | add_fileset_file axi_bridge_for_acp_128.v VERILOG PATH axi_bridge_for_acp_128.v TOP_LEVEL_FILE 40 | 41 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 42 | set_fileset_property SIM_VERILOG TOP_LEVEL axi_bridge_for_acp_128 43 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 44 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false 45 | add_fileset_file axi_bridge_for_acp_128.v VERILOG PATH axi_bridge_for_acp_128.v 46 | 47 | add_fileset SIM_VHDL SIM_VHDL "" "" 48 | set_fileset_property SIM_VHDL TOP_LEVEL axi_bridge_for_acp_128 49 | set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false 50 | set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE false 51 | add_fileset_file axi_bridge_for_acp_128.v VERILOG PATH axi_bridge_for_acp_128.v 52 | 53 | 54 | # 55 | # parameters 56 | # 57 | 58 | 59 | # 60 | # display items 61 | # 62 | 63 | 64 | # 65 | # connection point clock 66 | # 67 | add_interface clock clock end 68 | set_interface_property clock clockRate 0 69 | set_interface_property clock ENABLED true 70 | set_interface_property clock EXPORT_OF "" 71 | set_interface_property clock PORT_NAME_MAP "" 72 | set_interface_property clock CMSIS_SVD_VARIABLES "" 73 | set_interface_property clock SVD_ADDRESS_GROUP "" 74 | 75 | add_interface_port clock clk clk Input 1 76 | 77 | 78 | # 79 | # connection point reset 80 | # 81 | add_interface reset reset end 82 | set_interface_property reset associatedClock clock 83 | set_interface_property reset synchronousEdges DEASSERT 84 | set_interface_property reset ENABLED true 85 | set_interface_property reset EXPORT_OF "" 86 | set_interface_property reset PORT_NAME_MAP "" 87 | set_interface_property reset CMSIS_SVD_VARIABLES "" 88 | set_interface_property reset SVD_ADDRESS_GROUP "" 89 | 90 | add_interface_port reset reset reset Input 1 91 | 92 | 93 | # 94 | # connection point m0 95 | # 96 | add_interface m0 axi start 97 | set_interface_property m0 associatedClock clock 98 | set_interface_property m0 associatedReset reset 99 | set_interface_property m0 readIssuingCapability 16 100 | set_interface_property m0 writeIssuingCapability 16 101 | set_interface_property m0 combinedIssuingCapability 16 102 | set_interface_property m0 ENABLED true 103 | set_interface_property m0 EXPORT_OF "" 104 | set_interface_property m0 PORT_NAME_MAP "" 105 | set_interface_property m0 CMSIS_SVD_VARIABLES "" 106 | set_interface_property m0 SVD_ADDRESS_GROUP "" 107 | 108 | add_interface_port m0 axm_m0_araddr araddr Output 32 109 | add_interface_port m0 axm_m0_arburst arburst Output 2 110 | add_interface_port m0 axm_m0_arcache arcache Output 4 111 | add_interface_port m0 axm_m0_arid arid Output 8 112 | add_interface_port m0 axm_m0_arlen arlen Output 4 113 | add_interface_port m0 axm_m0_arlock arlock Output 2 114 | add_interface_port m0 axm_m0_arprot arprot Output 3 115 | add_interface_port m0 axm_m0_arready arready Input 1 116 | add_interface_port m0 axm_m0_arsize arsize Output 3 117 | add_interface_port m0 axm_m0_aruser aruser Output 5 118 | add_interface_port m0 axm_m0_arvalid arvalid Output 1 119 | add_interface_port m0 axm_m0_awaddr awaddr Output 32 120 | add_interface_port m0 axm_m0_awburst awburst Output 2 121 | add_interface_port m0 axm_m0_awcache awcache Output 4 122 | add_interface_port m0 axm_m0_awid awid Output 8 123 | add_interface_port m0 axm_m0_awlen awlen Output 4 124 | add_interface_port m0 axm_m0_awlock awlock Output 2 125 | add_interface_port m0 axm_m0_awprot awprot Output 3 126 | add_interface_port m0 axm_m0_awready awready Input 1 127 | add_interface_port m0 axm_m0_awsize awsize Output 3 128 | add_interface_port m0 axm_m0_awuser awuser Output 5 129 | add_interface_port m0 axm_m0_awvalid awvalid Output 1 130 | add_interface_port m0 axm_m0_bid bid Input 8 131 | add_interface_port m0 axm_m0_bready bready Output 1 132 | add_interface_port m0 axm_m0_bresp bresp Input 2 133 | add_interface_port m0 axm_m0_bvalid bvalid Input 1 134 | add_interface_port m0 axm_m0_rdata rdata Input 128 135 | add_interface_port m0 axm_m0_rid rid Input 8 136 | add_interface_port m0 axm_m0_rlast rlast Input 1 137 | add_interface_port m0 axm_m0_rready rready Output 1 138 | add_interface_port m0 axm_m0_rresp rresp Input 2 139 | add_interface_port m0 axm_m0_rvalid rvalid Input 1 140 | add_interface_port m0 axm_m0_wdata wdata Output 128 141 | add_interface_port m0 axm_m0_wid wid Output 8 142 | add_interface_port m0 axm_m0_wlast wlast Output 1 143 | add_interface_port m0 axm_m0_wready wready Input 1 144 | add_interface_port m0 axm_m0_wstrb wstrb Output 16 145 | add_interface_port m0 axm_m0_wvalid wvalid Output 1 146 | 147 | 148 | # 149 | # connection point s0 150 | # 151 | add_interface s0 axi end 152 | set_interface_property s0 associatedClock clock 153 | set_interface_property s0 associatedReset reset 154 | set_interface_property s0 readAcceptanceCapability 16 155 | set_interface_property s0 writeAcceptanceCapability 16 156 | set_interface_property s0 combinedAcceptanceCapability 16 157 | set_interface_property s0 readDataReorderingDepth 1 158 | set_interface_property s0 bridgesToMaster "m0" 159 | set_interface_property s0 ENABLED true 160 | set_interface_property s0 EXPORT_OF "" 161 | set_interface_property s0 PORT_NAME_MAP "" 162 | set_interface_property s0 CMSIS_SVD_VARIABLES "" 163 | set_interface_property s0 SVD_ADDRESS_GROUP "" 164 | 165 | add_interface_port s0 axs_s0_araddr araddr Input 32 166 | add_interface_port s0 axs_s0_arburst arburst Input 2 167 | add_interface_port s0 axs_s0_arcache arcache Input 4 168 | add_interface_port s0 axs_s0_arid arid Input 8 169 | add_interface_port s0 axs_s0_arlen arlen Input 4 170 | add_interface_port s0 axs_s0_arlock arlock Input 2 171 | add_interface_port s0 axs_s0_arprot arprot Input 3 172 | add_interface_port s0 axs_s0_arready arready Output 1 173 | add_interface_port s0 axs_s0_arsize arsize Input 3 174 | add_interface_port s0 axs_s0_aruser aruser Input 5 175 | add_interface_port s0 axs_s0_arvalid arvalid Input 1 176 | add_interface_port s0 axs_s0_awaddr awaddr Input 32 177 | add_interface_port s0 axs_s0_awburst awburst Input 2 178 | add_interface_port s0 axs_s0_awcache awcache Input 4 179 | add_interface_port s0 axs_s0_awid awid Input 8 180 | add_interface_port s0 axs_s0_awlen awlen Input 4 181 | add_interface_port s0 axs_s0_awlock awlock Input 2 182 | add_interface_port s0 axs_s0_awprot awprot Input 3 183 | add_interface_port s0 axs_s0_awready awready Output 1 184 | add_interface_port s0 axs_s0_awsize awsize Input 3 185 | add_interface_port s0 axs_s0_awuser awuser Input 5 186 | add_interface_port s0 axs_s0_awvalid awvalid Input 1 187 | add_interface_port s0 axs_s0_bid bid Output 8 188 | add_interface_port s0 axs_s0_bready bready Input 1 189 | add_interface_port s0 axs_s0_bresp bresp Output 2 190 | add_interface_port s0 axs_s0_bvalid bvalid Output 1 191 | add_interface_port s0 axs_s0_rdata rdata Output 128 192 | add_interface_port s0 axs_s0_rid rid Output 8 193 | add_interface_port s0 axs_s0_rlast rlast Output 1 194 | add_interface_port s0 axs_s0_rready rready Input 1 195 | add_interface_port s0 axs_s0_rresp rresp Output 2 196 | add_interface_port s0 axs_s0_rvalid rvalid Output 1 197 | add_interface_port s0 axs_s0_wdata wdata Input 128 198 | add_interface_port s0 axs_s0_wid wid Input 8 199 | add_interface_port s0 axs_s0_wlast wlast Input 1 200 | add_interface_port s0 axs_s0_wready wready Output 1 201 | add_interface_port s0 axs_s0_wstrb wstrb Input 16 202 | add_interface_port s0 axs_s0_wvalid wvalid Input 1 203 | 204 | -------------------------------------------------------------------------------- /ip/chip_id_read_mm/chip_id_read_mm.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016 Intel Corporation 2 | // SPDX-License-Identifier: MIT 3 | 4 | `timescale 1 ps / 1 ps 5 | module chip_id_read_mm ( 6 | // clocks and resets 7 | input wire clk, // clock.clk 8 | input wire reset, // reset.reset 9 | 10 | // Avalon MM slave 11 | input wire avs_s0_read, // s0.read 12 | output wire [63:0] avs_s0_readdata, // .readdata 13 | 14 | // Avalon ST sink 15 | input wire [63:0] asi_in0_data, // in0.data 16 | output wire asi_in0_ready // in0.ready 17 | ); 18 | 19 | assign avs_s0_readdata = asi_in0_data; 20 | assign asi_in0_ready = 1'b1; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /ip/chip_id_read_mm/chip_id_read_mm_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | # 5 | # chip_id_read_mm "chip_id_read_mm" v1.0 6 | # RSF 2014.03.07.09:59:24 7 | # Avalon MM slave that can read the Chip ID Avalon ST source output. 8 | # 9 | 10 | # 11 | # request TCL package from ACDS 13.1 12 | # 13 | package require -exact qsys 13.1 14 | 15 | 16 | # 17 | # module chip_id_read_mm 18 | # 19 | set_module_property DESCRIPTION "Avalon MM slave that can read the Chip ID Avalon ST source output." 20 | set_module_property NAME chip_id_read_mm 21 | set_module_property VERSION 1.0 22 | set_module_property INTERNAL false 23 | set_module_property OPAQUE_ADDRESS_MAP true 24 | set_module_property AUTHOR RSF 25 | set_module_property DISPLAY_NAME chip_id_read_mm 26 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 27 | set_module_property EDITABLE true 28 | set_module_property ANALYZE_HDL AUTO 29 | set_module_property REPORT_TO_TALKBACK false 30 | set_module_property ALLOW_GREYBOX_GENERATION false 31 | 32 | 33 | # 34 | # file sets 35 | # 36 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 37 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL chip_id_read_mm 38 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 39 | add_fileset_file chip_id_read_mm.v VERILOG PATH chip_id_read_mm.v TOP_LEVEL_FILE 40 | 41 | 42 | # 43 | # parameters 44 | # 45 | 46 | 47 | # 48 | # display items 49 | # 50 | 51 | 52 | # 53 | # connection point clock 54 | # 55 | add_interface clock clock end 56 | set_interface_property clock clockRate 0 57 | set_interface_property clock ENABLED true 58 | set_interface_property clock EXPORT_OF "" 59 | set_interface_property clock PORT_NAME_MAP "" 60 | set_interface_property clock CMSIS_SVD_VARIABLES "" 61 | set_interface_property clock SVD_ADDRESS_GROUP "" 62 | 63 | add_interface_port clock clk clk Input 1 64 | 65 | 66 | # 67 | # connection point reset 68 | # 69 | add_interface reset reset end 70 | set_interface_property reset associatedClock clock 71 | set_interface_property reset synchronousEdges DEASSERT 72 | set_interface_property reset ENABLED true 73 | set_interface_property reset EXPORT_OF "" 74 | set_interface_property reset PORT_NAME_MAP "" 75 | set_interface_property reset CMSIS_SVD_VARIABLES "" 76 | set_interface_property reset SVD_ADDRESS_GROUP "" 77 | 78 | add_interface_port reset reset reset Input 1 79 | 80 | 81 | # 82 | # connection point s0 83 | # 84 | add_interface s0 avalon end 85 | set_interface_property s0 addressUnits WORDS 86 | set_interface_property s0 associatedClock clock 87 | set_interface_property s0 associatedReset reset 88 | set_interface_property s0 bitsPerSymbol 8 89 | set_interface_property s0 burstOnBurstBoundariesOnly false 90 | set_interface_property s0 burstcountUnits WORDS 91 | set_interface_property s0 explicitAddressSpan 0 92 | set_interface_property s0 holdTime 0 93 | set_interface_property s0 linewrapBursts false 94 | set_interface_property s0 maximumPendingReadTransactions 0 95 | set_interface_property s0 readLatency 0 96 | set_interface_property s0 readWaitTime 1 97 | set_interface_property s0 setupTime 0 98 | set_interface_property s0 timingUnits Cycles 99 | set_interface_property s0 writeWaitTime 0 100 | set_interface_property s0 ENABLED true 101 | set_interface_property s0 EXPORT_OF "" 102 | set_interface_property s0 PORT_NAME_MAP "" 103 | set_interface_property s0 CMSIS_SVD_VARIABLES "" 104 | set_interface_property s0 SVD_ADDRESS_GROUP "" 105 | 106 | add_interface_port s0 avs_s0_read read Input 1 107 | add_interface_port s0 avs_s0_readdata readdata Output 64 108 | set_interface_assignment s0 embeddedsw.configuration.isFlash 0 109 | set_interface_assignment s0 embeddedsw.configuration.isMemoryDevice 0 110 | set_interface_assignment s0 embeddedsw.configuration.isNonVolatileStorage 0 111 | set_interface_assignment s0 embeddedsw.configuration.isPrintableDevice 0 112 | 113 | 114 | # 115 | # connection point in0 116 | # 117 | add_interface in0 avalon_streaming end 118 | set_interface_property in0 associatedClock clock 119 | set_interface_property in0 associatedReset reset 120 | set_interface_property in0 dataBitsPerSymbol 8 121 | set_interface_property in0 errorDescriptor "" 122 | set_interface_property in0 firstSymbolInHighOrderBits true 123 | set_interface_property in0 maxChannel 0 124 | set_interface_property in0 readyLatency 0 125 | set_interface_property in0 ENABLED true 126 | set_interface_property in0 EXPORT_OF "" 127 | set_interface_property in0 PORT_NAME_MAP "" 128 | set_interface_property in0 CMSIS_SVD_VARIABLES "" 129 | set_interface_property in0 SVD_ADDRESS_GROUP "" 130 | 131 | add_interface_port in0 asi_in0_data data Input 64 132 | add_interface_port in0 asi_in0_ready ready Output 1 133 | 134 | -------------------------------------------------------------------------------- /ip/conduit_adapters/conduit_remap/conduit_remap_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 15.1 5 | 6 | 7 | # 8 | # module conduit_remap 9 | # 10 | set_module_property DESCRIPTION "Remap one conduit role to another role." 11 | set_module_property NAME conduit_remap 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property GROUP "Reset Components/Adapters" 16 | set_module_property AUTHOR RSF 17 | set_module_property DISPLAY_NAME conduit_remap 18 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 19 | set_module_property EDITABLE false 20 | set_module_property REPORT_TO_TALKBACK false 21 | set_module_property ALLOW_GREYBOX_GENERATION false 22 | set_module_property REPORT_HIERARCHY false 23 | set_module_property ELABORATION_CALLBACK elaborate 24 | 25 | 26 | # 27 | # file sets 28 | # 29 | 30 | 31 | # 32 | # parameters 33 | # 34 | add_parameter INPUT_CONDUIT_ROLE STRING 35 | set_parameter_property INPUT_CONDUIT_ROLE DEFAULT_VALUE "input" 36 | set_parameter_property INPUT_CONDUIT_ROLE DISPLAY_NAME "Role of input_sig conduit" 37 | set_parameter_property INPUT_CONDUIT_ROLE TYPE STRING 38 | set_parameter_property INPUT_CONDUIT_ROLE UNITS None 39 | set_parameter_property INPUT_CONDUIT_ROLE GROUP "Input Conduit" 40 | set_parameter_property INPUT_CONDUIT_ROLE DESCRIPTION "Enter the role that you want to assign the input_sig conduit input." 41 | set_parameter_property INPUT_CONDUIT_ROLE HDL_PARAMETER false 42 | set_parameter_property INPUT_CONDUIT_ROLE AFFECTS_VALIDATION true 43 | set_parameter_property INPUT_CONDUIT_ROLE AFFECTS_ELABORATION true 44 | 45 | add_parameter OUTPUT_CONDUIT_ROLE STRING 46 | set_parameter_property OUTPUT_CONDUIT_ROLE DEFAULT_VALUE "output" 47 | set_parameter_property OUTPUT_CONDUIT_ROLE DISPLAY_NAME "Role of output_sig conduit" 48 | set_parameter_property OUTPUT_CONDUIT_ROLE TYPE STRING 49 | set_parameter_property OUTPUT_CONDUIT_ROLE UNITS None 50 | set_parameter_property OUTPUT_CONDUIT_ROLE GROUP "Output Conduit" 51 | set_parameter_property OUTPUT_CONDUIT_ROLE DESCRIPTION "Enter the role that you want to assign the output_sig conduit output." 52 | set_parameter_property OUTPUT_CONDUIT_ROLE HDL_PARAMETER false 53 | set_parameter_property OUTPUT_CONDUIT_ROLE AFFECTS_VALIDATION true 54 | set_parameter_property OUTPUT_CONDUIT_ROLE AFFECTS_ELABORATION true 55 | 56 | 57 | # 58 | # display items 59 | # 60 | 61 | 62 | # 63 | # connection point input_conduit 64 | # 65 | add_interface input_conduit conduit end 66 | set_interface_property input_conduit associatedClock "" 67 | set_interface_property input_conduit associatedReset "" 68 | set_interface_property input_conduit ENABLED true 69 | set_interface_property input_conduit EXPORT_OF "" 70 | set_interface_property input_conduit PORT_NAME_MAP "" 71 | set_interface_property input_conduit CMSIS_SVD_VARIABLES "" 72 | set_interface_property input_conduit SVD_ADDRESS_GROUP "" 73 | 74 | add_interface_port input_conduit input_sig input Input 1 75 | 76 | 77 | # 78 | # connection point output_conduit 79 | # 80 | add_interface output_conduit conduit end 81 | set_interface_property output_conduit associatedClock "" 82 | set_interface_property output_conduit associatedReset "" 83 | set_interface_property output_conduit ENABLED true 84 | set_interface_property output_conduit EXPORT_OF "" 85 | set_interface_property output_conduit PORT_NAME_MAP "" 86 | set_interface_property output_conduit CMSIS_SVD_VARIABLES "" 87 | set_interface_property output_conduit SVD_ADDRESS_GROUP "" 88 | 89 | add_interface_port output_conduit output_sig output Output 1 90 | set_port_property output_sig DRIVEN_BY input_sig 91 | 92 | 93 | proc elaborate {} { 94 | set_port_property input_sig ROLE [ get_parameter_value INPUT_CONDUIT_ROLE ] 95 | set_port_property output_sig ROLE [ get_parameter_value OUTPUT_CONDUIT_ROLE ] 96 | } 97 | 98 | -------------------------------------------------------------------------------- /ip/conduit_adapters/conduit_remap/conduit_to_interrupt_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 15.1 5 | 6 | 7 | # 8 | # module conduit_remap 9 | # 10 | set_module_property DESCRIPTION "Remap a conduit interface to an interrupt interface." 11 | set_module_property NAME conduit_to_interrupt 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property GROUP "Reset Components/Adapters" 16 | set_module_property AUTHOR RSF 17 | set_module_property DISPLAY_NAME conduit_to_interrupt 18 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 19 | set_module_property EDITABLE false 20 | set_module_property REPORT_TO_TALKBACK false 21 | set_module_property ALLOW_GREYBOX_GENERATION false 22 | set_module_property REPORT_HIERARCHY false 23 | set_module_property ELABORATION_CALLBACK elaborate 24 | 25 | 26 | # 27 | # file sets 28 | # 29 | 30 | 31 | # 32 | # parameters 33 | # 34 | add_parameter INPUT_CONDUIT_ROLE STRING 35 | set_parameter_property INPUT_CONDUIT_ROLE DEFAULT_VALUE "input" 36 | set_parameter_property INPUT_CONDUIT_ROLE DISPLAY_NAME "Role of input_sig conduit" 37 | set_parameter_property INPUT_CONDUIT_ROLE TYPE STRING 38 | set_parameter_property INPUT_CONDUIT_ROLE UNITS None 39 | set_parameter_property INPUT_CONDUIT_ROLE GROUP "Input Conduit" 40 | set_parameter_property INPUT_CONDUIT_ROLE DESCRIPTION "Enter the role that you want to assign the input_sig conduit input." 41 | set_parameter_property INPUT_CONDUIT_ROLE HDL_PARAMETER false 42 | set_parameter_property INPUT_CONDUIT_ROLE AFFECTS_VALIDATION true 43 | set_parameter_property INPUT_CONDUIT_ROLE AFFECTS_ELABORATION true 44 | 45 | 46 | # 47 | # display items 48 | # 49 | 50 | 51 | # 52 | # connection point input_conduit 53 | # 54 | add_interface input_conduit conduit end 55 | set_interface_property input_conduit associatedClock "" 56 | set_interface_property input_conduit associatedReset "" 57 | set_interface_property input_conduit ENABLED true 58 | set_interface_property input_conduit EXPORT_OF "" 59 | set_interface_property input_conduit PORT_NAME_MAP "" 60 | set_interface_property input_conduit CMSIS_SVD_VARIABLES "" 61 | set_interface_property input_conduit SVD_ADDRESS_GROUP "" 62 | 63 | add_interface_port input_conduit input_sig input Input 1 64 | 65 | # 66 | # connection point output_interrupt 67 | # 68 | add_interface output_interrupt interrupt end 69 | set_interface_property output_interrupt associatedAddressablePoint "" 70 | set_interface_property output_interrupt bridgedReceiverOffset "" 71 | set_interface_property output_interrupt bridgesToReceiver "" 72 | set_interface_property output_interrupt ENABLED true 73 | set_interface_property output_interrupt EXPORT_OF "" 74 | set_interface_property output_interrupt PORT_NAME_MAP "" 75 | set_interface_property output_interrupt CMSIS_SVD_VARIABLES "" 76 | set_interface_property output_interrupt SVD_ADDRESS_GROUP "" 77 | 78 | add_interface_port output_interrupt output_sig irq Output 1 79 | set_port_property output_sig DRIVEN_BY input_sig 80 | 81 | 82 | proc elaborate {} { 83 | set_port_property input_sig ROLE [ get_parameter_value INPUT_CONDUIT_ROLE ] 84 | } 85 | 86 | -------------------------------------------------------------------------------- /ip/conduit_adapters/conduit_remap/conduit_to_reset_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 15.1 5 | 6 | 7 | # 8 | # module conduit_remap 9 | # 10 | set_module_property DESCRIPTION "Remap a conduit interface to a reset interface." 11 | set_module_property NAME conduit_to_reset 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property GROUP "Reset Components/Adapters" 16 | set_module_property AUTHOR RSF 17 | set_module_property DISPLAY_NAME conduit_to_reset 18 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 19 | set_module_property EDITABLE false 20 | set_module_property REPORT_TO_TALKBACK false 21 | set_module_property ALLOW_GREYBOX_GENERATION false 22 | set_module_property REPORT_HIERARCHY false 23 | set_module_property ELABORATION_CALLBACK elaborate 24 | 25 | 26 | # 27 | # file sets 28 | # 29 | 30 | 31 | # 32 | # parameters 33 | # 34 | add_parameter INPUT_CONDUIT_ROLE STRING 35 | set_parameter_property INPUT_CONDUIT_ROLE DEFAULT_VALUE "input" 36 | set_parameter_property INPUT_CONDUIT_ROLE DISPLAY_NAME "Role of input_sig conduit" 37 | set_parameter_property INPUT_CONDUIT_ROLE TYPE STRING 38 | set_parameter_property INPUT_CONDUIT_ROLE UNITS None 39 | set_parameter_property INPUT_CONDUIT_ROLE GROUP "Input Conduit" 40 | set_parameter_property INPUT_CONDUIT_ROLE DESCRIPTION "Enter the role that you want to assign the input_sig conduit input." 41 | set_parameter_property INPUT_CONDUIT_ROLE HDL_PARAMETER false 42 | set_parameter_property INPUT_CONDUIT_ROLE AFFECTS_VALIDATION true 43 | set_parameter_property INPUT_CONDUIT_ROLE AFFECTS_ELABORATION true 44 | 45 | 46 | # 47 | # display items 48 | # 49 | 50 | 51 | # 52 | # connection point input_conduit 53 | # 54 | add_interface input_conduit conduit end 55 | set_interface_property input_conduit associatedClock "" 56 | set_interface_property input_conduit associatedReset "" 57 | set_interface_property input_conduit ENABLED true 58 | set_interface_property input_conduit EXPORT_OF "" 59 | set_interface_property input_conduit PORT_NAME_MAP "" 60 | set_interface_property input_conduit CMSIS_SVD_VARIABLES "" 61 | set_interface_property input_conduit SVD_ADDRESS_GROUP "" 62 | 63 | add_interface_port input_conduit input_sig input Input 1 64 | 65 | # 66 | # connection point output_reset 67 | # 68 | add_interface output_reset reset start 69 | set_interface_property output_reset associatedClock "" 70 | set_interface_property output_reset associatedDirectReset "" 71 | set_interface_property output_reset associatedResetSinks none 72 | set_interface_property output_reset synchronousEdges NONE 73 | set_interface_property output_reset ENABLED true 74 | set_interface_property output_reset EXPORT_OF "" 75 | set_interface_property output_reset PORT_NAME_MAP "" 76 | set_interface_property output_reset CMSIS_SVD_VARIABLES "" 77 | set_interface_property output_reset SVD_ADDRESS_GROUP "" 78 | 79 | add_interface_port output_reset output_sig reset Output 1 80 | set_port_property output_sig DRIVEN_BY input_sig 81 | 82 | 83 | proc elaborate {} { 84 | set_port_property input_sig ROLE [ get_parameter_value INPUT_CONDUIT_ROLE ] 85 | } 86 | 87 | -------------------------------------------------------------------------------- /ip/conduit_adapters/conduit_remap/interrupt_to_conduit_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 15.1 5 | 6 | 7 | # 8 | # module conduit_remap 9 | # 10 | set_module_property DESCRIPTION "Remap an interrupt interface to a conduit interface." 11 | set_module_property NAME interrupt_to_conduit 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property GROUP "Reset Components/Adapters" 16 | set_module_property AUTHOR RSF 17 | set_module_property DISPLAY_NAME interrupt_to_conduit 18 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 19 | set_module_property EDITABLE false 20 | set_module_property REPORT_TO_TALKBACK false 21 | set_module_property ALLOW_GREYBOX_GENERATION false 22 | set_module_property REPORT_HIERARCHY false 23 | set_module_property ELABORATION_CALLBACK elaborate 24 | 25 | 26 | # 27 | # file sets 28 | # 29 | 30 | 31 | # 32 | # parameters 33 | # 34 | add_parameter OUTPUT_CONDUIT_ROLE STRING 35 | set_parameter_property OUTPUT_CONDUIT_ROLE DEFAULT_VALUE "output" 36 | set_parameter_property OUTPUT_CONDUIT_ROLE DISPLAY_NAME "Role of output_sig conduit" 37 | set_parameter_property OUTPUT_CONDUIT_ROLE TYPE STRING 38 | set_parameter_property OUTPUT_CONDUIT_ROLE UNITS None 39 | set_parameter_property OUTPUT_CONDUIT_ROLE GROUP "Output Conduit" 40 | set_parameter_property OUTPUT_CONDUIT_ROLE DESCRIPTION "Enter the role that you want to assign the output_sig conduit output." 41 | set_parameter_property OUTPUT_CONDUIT_ROLE HDL_PARAMETER false 42 | set_parameter_property OUTPUT_CONDUIT_ROLE AFFECTS_VALIDATION true 43 | set_parameter_property OUTPUT_CONDUIT_ROLE AFFECTS_ELABORATION true 44 | 45 | 46 | # 47 | # display items 48 | # 49 | 50 | 51 | # 52 | # connection point input_interrupt 53 | # 54 | add_interface input_interrupt interrupt start 55 | set_interface_property input_interrupt associatedAddressablePoint "" 56 | set_interface_property input_interrupt irqScheme INDIVIDUAL_REQUESTS 57 | set_interface_property input_interrupt ENABLED true 58 | set_interface_property input_interrupt EXPORT_OF "" 59 | set_interface_property input_interrupt PORT_NAME_MAP "" 60 | set_interface_property input_interrupt CMSIS_SVD_VARIABLES "" 61 | set_interface_property input_interrupt SVD_ADDRESS_GROUP "" 62 | 63 | add_interface_port input_interrupt input_sig irq Input 1 64 | 65 | 66 | # 67 | # connection point output_conduit 68 | # 69 | add_interface output_conduit conduit end 70 | set_interface_property output_conduit associatedClock "" 71 | set_interface_property output_conduit associatedReset "" 72 | set_interface_property output_conduit ENABLED true 73 | set_interface_property output_conduit EXPORT_OF "" 74 | set_interface_property output_conduit PORT_NAME_MAP "" 75 | set_interface_property output_conduit CMSIS_SVD_VARIABLES "" 76 | set_interface_property output_conduit SVD_ADDRESS_GROUP "" 77 | 78 | add_interface_port output_conduit output_sig output Output 1 79 | set_port_property output_sig DRIVEN_BY input_sig 80 | 81 | 82 | proc elaborate {} { 83 | set_port_property output_sig ROLE [ get_parameter_value OUTPUT_CONDUIT_ROLE ] 84 | } 85 | 86 | -------------------------------------------------------------------------------- /ip/conduit_adapters/conduit_remap/reset_to_conduit_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 15.1 5 | 6 | 7 | # 8 | # module conduit_remap 9 | # 10 | set_module_property DESCRIPTION "Remap a reset interface to a conduit interface." 11 | set_module_property NAME reset_to_conduit 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property GROUP "Reset Components/Adapters" 16 | set_module_property AUTHOR RSF 17 | set_module_property DISPLAY_NAME reset_to_conduit 18 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 19 | set_module_property EDITABLE false 20 | set_module_property REPORT_TO_TALKBACK false 21 | set_module_property ALLOW_GREYBOX_GENERATION false 22 | set_module_property REPORT_HIERARCHY false 23 | set_module_property ELABORATION_CALLBACK elaborate 24 | 25 | 26 | # 27 | # file sets 28 | # 29 | 30 | 31 | # 32 | # parameters 33 | # 34 | add_parameter OUTPUT_CONDUIT_ROLE STRING 35 | set_parameter_property OUTPUT_CONDUIT_ROLE DEFAULT_VALUE "output" 36 | set_parameter_property OUTPUT_CONDUIT_ROLE DISPLAY_NAME "Role of output_sig conduit" 37 | set_parameter_property OUTPUT_CONDUIT_ROLE TYPE STRING 38 | set_parameter_property OUTPUT_CONDUIT_ROLE UNITS None 39 | set_parameter_property OUTPUT_CONDUIT_ROLE GROUP "Output Conduit" 40 | set_parameter_property OUTPUT_CONDUIT_ROLE DESCRIPTION "Enter the role that you want to assign the output_sig conduit output." 41 | set_parameter_property OUTPUT_CONDUIT_ROLE HDL_PARAMETER false 42 | set_parameter_property OUTPUT_CONDUIT_ROLE AFFECTS_VALIDATION true 43 | set_parameter_property OUTPUT_CONDUIT_ROLE AFFECTS_ELABORATION true 44 | 45 | 46 | # 47 | # display items 48 | # 49 | 50 | 51 | # 52 | # connection point input_reset 53 | # 54 | add_interface input_reset reset end 55 | set_interface_property input_reset associatedClock "" 56 | set_interface_property input_reset synchronousEdges NONE 57 | set_interface_property input_reset ENABLED true 58 | set_interface_property input_reset EXPORT_OF "" 59 | set_interface_property input_reset PORT_NAME_MAP "" 60 | set_interface_property input_reset CMSIS_SVD_VARIABLES "" 61 | set_interface_property input_reset SVD_ADDRESS_GROUP "" 62 | 63 | add_interface_port input_reset input_sig reset Input 1 64 | 65 | 66 | # 67 | # connection point output_conduit 68 | # 69 | add_interface output_conduit conduit end 70 | set_interface_property output_conduit associatedClock "" 71 | set_interface_property output_conduit associatedReset "" 72 | set_interface_property output_conduit ENABLED true 73 | set_interface_property output_conduit EXPORT_OF "" 74 | set_interface_property output_conduit PORT_NAME_MAP "" 75 | set_interface_property output_conduit CMSIS_SVD_VARIABLES "" 76 | set_interface_property output_conduit SVD_ADDRESS_GROUP "" 77 | 78 | add_interface_port output_conduit output_sig output Output 1 79 | set_port_property output_sig DRIVEN_BY input_sig 80 | 81 | 82 | proc elaborate {} { 83 | set_port_property output_sig ROLE [ get_parameter_value OUTPUT_CONDUIT_ROLE ] 84 | } 85 | 86 | -------------------------------------------------------------------------------- /ip/conduit_adapters/emif_status_breakout/emif_status_breakout_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 15.1 5 | 6 | 7 | # 8 | # module emif_status_breakout 9 | # 10 | set_module_property DESCRIPTION "Breakout the EMIF status conduit bundle into more useful interfaces." 11 | set_module_property NAME emif_status_breakout 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property GROUP "Reset Components/Adapters" 16 | set_module_property AUTHOR RSF 17 | set_module_property DISPLAY_NAME emif_status_breakout 18 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 19 | set_module_property EDITABLE false 20 | set_module_property REPORT_TO_TALKBACK false 21 | set_module_property ALLOW_GREYBOX_GENERATION false 22 | set_module_property REPORT_HIERARCHY false 23 | 24 | 25 | # 26 | # file sets 27 | # 28 | 29 | 30 | # 31 | # parameters 32 | # 33 | 34 | 35 | # 36 | # display items 37 | # 38 | 39 | 40 | # 41 | # connection point status 42 | # 43 | add_interface status conduit end 44 | set_interface_property status associatedClock "" 45 | set_interface_property status associatedReset "" 46 | set_interface_property status ENABLED true 47 | set_interface_property status EXPORT_OF "" 48 | set_interface_property status PORT_NAME_MAP "" 49 | set_interface_property status CMSIS_SVD_VARIABLES "" 50 | set_interface_property status SVD_ADDRESS_GROUP "" 51 | 52 | add_interface_port status local_cal_fail local_cal_fail Input 1 53 | add_interface_port status local_cal_success local_cal_success Input 1 54 | add_interface_port status local_init_done local_init_done Input 1 55 | 56 | 57 | # 58 | # connection point cal_fail 59 | # 60 | add_interface cal_fail reset start 61 | set_interface_property cal_fail associatedClock "" 62 | set_interface_property cal_fail associatedDirectReset "" 63 | set_interface_property cal_fail associatedResetSinks "" 64 | set_interface_property cal_fail synchronousEdges NONE 65 | set_interface_property cal_fail ENABLED true 66 | set_interface_property cal_fail EXPORT_OF "" 67 | set_interface_property cal_fail PORT_NAME_MAP "" 68 | set_interface_property cal_fail CMSIS_SVD_VARIABLES "" 69 | set_interface_property cal_fail SVD_ADDRESS_GROUP "" 70 | 71 | add_interface_port cal_fail cal_fail reset Output 1 72 | set_port_property cal_fail DRIVEN_BY local_cal_fail 73 | 74 | 75 | # 76 | # connection point cal_success 77 | # 78 | add_interface cal_success conduit end 79 | set_interface_property cal_success associatedClock "" 80 | set_interface_property cal_success associatedReset "" 81 | set_interface_property cal_success ENABLED true 82 | set_interface_property cal_success EXPORT_OF "" 83 | set_interface_property cal_success PORT_NAME_MAP "" 84 | set_interface_property cal_success CMSIS_SVD_VARIABLES "" 85 | set_interface_property cal_success SVD_ADDRESS_GROUP "" 86 | 87 | add_interface_port cal_success cal_success event_input Output 1 88 | set_port_property cal_success DRIVEN_BY local_cal_success 89 | 90 | 91 | # 92 | # connection point init_done 93 | # 94 | add_interface init_done conduit end 95 | set_interface_property init_done associatedClock "" 96 | set_interface_property init_done associatedReset "" 97 | set_interface_property init_done ENABLED true 98 | set_interface_property init_done EXPORT_OF "" 99 | set_interface_property init_done PORT_NAME_MAP "" 100 | set_interface_property init_done CMSIS_SVD_VARIABLES "" 101 | set_interface_property init_done SVD_ADDRESS_GROUP "" 102 | 103 | add_interface_port init_done init_done event_input Output 1 104 | set_port_property init_done DRIVEN_BY local_init_done 105 | 106 | -------------------------------------------------------------------------------- /ip/conduit_adapters/pll_sharing_to_pll_locked/pll_sharing_to_pll_locked_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 15.1 5 | 6 | 7 | # 8 | # module pll_sharing_to_pll_locked 9 | # 10 | set_module_property DESCRIPTION "Breakout the pll_locked conduit from the pll_sharing conduit bundle provided by the EMIF IP core." 11 | set_module_property NAME pll_sharing_to_pll_locked 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property GROUP "Reset Components/Adapters" 16 | set_module_property AUTHOR RSF 17 | set_module_property DISPLAY_NAME pll_sharing_to_pll_locked 18 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 19 | set_module_property EDITABLE false 20 | set_module_property REPORT_TO_TALKBACK false 21 | set_module_property ALLOW_GREYBOX_GENERATION false 22 | set_module_property REPORT_HIERARCHY false 23 | 24 | 25 | # 26 | # file sets 27 | # 28 | 29 | 30 | # 31 | # parameters 32 | # 33 | 34 | 35 | # 36 | # display items 37 | # 38 | 39 | 40 | # 41 | # connection point pll_sharing 42 | # 43 | add_interface pll_sharing conduit end 44 | set_interface_property pll_sharing associatedClock "" 45 | set_interface_property pll_sharing associatedReset "" 46 | set_interface_property pll_sharing ENABLED true 47 | set_interface_property pll_sharing EXPORT_OF "" 48 | set_interface_property pll_sharing PORT_NAME_MAP "" 49 | set_interface_property pll_sharing CMSIS_SVD_VARIABLES "" 50 | set_interface_property pll_sharing SVD_ADDRESS_GROUP "" 51 | 52 | add_interface_port pll_sharing afi_phy_clk afi_phy_clk Input 1 53 | add_interface_port pll_sharing pll_addr_cmd_clk pll_addr_cmd_clk Input 1 54 | add_interface_port pll_sharing pll_avl_clk pll_avl_clk Input 1 55 | add_interface_port pll_sharing pll_avl_phy_clk pll_avl_phy_clk Input 1 56 | add_interface_port pll_sharing pll_config_clk pll_config_clk Input 1 57 | add_interface_port pll_sharing pll_locked pll_locked Input 1 58 | add_interface_port pll_sharing pll_mem_clk pll_mem_clk Input 1 59 | add_interface_port pll_sharing pll_mem_phy_clk pll_mem_phy_clk Input 1 60 | add_interface_port pll_sharing pll_write_clk pll_write_clk Input 1 61 | add_interface_port pll_sharing pll_write_clk_pre_phy_clk pll_write_clk_pre_phy_clk Input 1 62 | 63 | 64 | # 65 | # connection point pll_locked 66 | # 67 | add_interface pll_locked conduit end 68 | set_interface_property pll_locked associatedClock "" 69 | set_interface_property pll_locked associatedReset "" 70 | set_interface_property pll_locked ENABLED true 71 | set_interface_property pll_locked EXPORT_OF "" 72 | set_interface_property pll_locked PORT_NAME_MAP "" 73 | set_interface_property pll_locked CMSIS_SVD_VARIABLES "" 74 | set_interface_property pll_locked SVD_ADDRESS_GROUP "" 75 | 76 | add_interface_port pll_locked pll_locked_out pll_locked Output 1 77 | set_port_property pll_locked_out DRIVEN_BY pll_locked 78 | 79 | -------------------------------------------------------------------------------- /ip/debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /ip/fft_sub/LICENSE: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | Copyright (c) 2016 Intel Corporation 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in 12 | all copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 | THE SOFTWARE. 21 | 22 | -------------------------------------------------------------------------------- /ip/mandelbrot_colorizer/mandelbrot_colorizer.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (c) 2017 Intel Corporation 3 | // 4 | // Permission is hereby granted, free of charge, to any person obtaining a copy 5 | // of this software and associated documentation files (the "Software"), to 6 | // deal in the Software without restriction, including without limitation the 7 | // rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 8 | // sell copies of the Software, and to permit persons to whom the Software is 9 | // furnished to do so, subject to the following conditions: 10 | // 11 | // The above copyright notice and this permission notice shall be included in 12 | // all copies or substantial portions of the Software. 13 | // 14 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 | // FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20 | // IN THE SOFTWARE. 21 | // 22 | 23 | `timescale 1 ps / 1 ps 24 | 25 | // This block takes a 32-bit input pixel value that represents the 16-bit value 26 | // of the iteration count discovered by the avst_mandelbrot_engine core and it 27 | // either passes it straight through, or it translates that value into a color 28 | // pixel value from a lookup table and emits that color pixel value. This core 29 | // looks at the value loaded into its max_iters register to decide if the raw 30 | // data is used or the colorized pixel data. The max_iters register is a 32-bit 31 | // register loaded via the AVMM slave interface, but only the 16 lsbs are valid. 32 | // If max_iters is set to 0, then the raw input data is passed straight through 33 | // this core, otherwise the colorized data is used. If colorized data is being 34 | // used, any input value that equals max_iters is encoded as 0x0000_0000 to 35 | // represent a black pixel color. Black pixels generally represent the value 36 | // of coordinates that reside inside the Mandelbrot set. 37 | 38 | module mandelbrot_colorizer( 39 | 40 | // clock and reset for component 41 | input wire clk, 42 | input wire reset, 43 | 44 | // avmm slave interface, sl 45 | input wire sl_read, 46 | input wire sl_write, 47 | input wire [ 3:0] sl_byteenable, 48 | input wire [ 31:0] sl_writedata, 49 | output wire [ 31:0] sl_readdata, 50 | output wire sl_waitrequest, 51 | 52 | // avst sink interface, in_pixel 53 | input wire [ 31:0] in_pixel_snk_data, 54 | input wire in_pixel_snk_valid, 55 | output wire in_pixel_snk_ready, 56 | 57 | // avst source interface, out_pixel 58 | output wire [ 31:0] out_pixel_src_data, 59 | output wire out_pixel_src_valid, 60 | input wire out_pixel_src_ready 61 | ); 62 | 63 | wire [15:0] result; 64 | wire colorize; 65 | wire [31:0] colorized_data; 66 | 67 | reg [15:0] max_iters; 68 | reg [31:0] color_data; 69 | 70 | assign result = {in_pixel_snk_data[23:16], in_pixel_snk_data[31:24]}; 71 | 72 | assign colorize = |max_iters; 73 | 74 | // 16 color table 75 | always @* begin 76 | // set color data to black, if result == max_iters then it stays black 77 | color_data <= 32'h00000000; 78 | if(result != max_iters) begin 79 | case(result[3:0]) 80 | 4'h0: color_data <= 32'h0000CC00; 81 | 4'h1: color_data <= 32'h00CC0000; 82 | 4'h2: color_data <= 32'hCC000000; 83 | 4'h3: color_data <= 32'h9900FF00; 84 | 4'h4: color_data <= 32'h99FF0000; 85 | 4'h5: color_data <= 32'hFF009900; 86 | 4'h6: color_data <= 32'h0099FF00; 87 | 4'h7: color_data <= 32'h00FF9900; 88 | 4'h8: color_data <= 32'hFF990000; 89 | 4'h9: color_data <= 32'h9900CC00; 90 | 4'hA: color_data <= 32'h99CC0000; 91 | 4'hB: color_data <= 32'hCC009900; 92 | 4'hC: color_data <= 32'h0099CC00; 93 | 4'hD: color_data <= 32'h00CC9900; 94 | 4'hE: color_data <= 32'hCC990000; 95 | 4'hF: color_data <= 32'h99009900; 96 | endcase 97 | end 98 | end 99 | 100 | assign colorized_data = (colorize == 1'b1) ? color_data : in_pixel_snk_data; 101 | 102 | altera_avalon_st_pipeline_base 103 | #( 104 | .BITS_PER_SYMBOL(32) 105 | ) st_pipe ( 106 | .clk (clk), 107 | .reset (reset), 108 | .in_ready (in_pixel_snk_ready), 109 | .in_valid (in_pixel_snk_valid), 110 | .in_data (colorized_data), 111 | .out_ready (out_pixel_src_ready), 112 | .out_valid (out_pixel_src_valid), 113 | .out_data (out_pixel_src_data) 114 | ); 115 | 116 | // avmm slave control 117 | 118 | assign sl_readdata = {16'd0, max_iters}; 119 | assign sl_waitrequest = 1'b0; 120 | 121 | always @ (posedge clk, posedge reset) begin 122 | if(reset) begin 123 | max_iters <= 16'd0; 124 | end else begin 125 | if(sl_write & sl_byteenable[0]) begin 126 | max_iters[7:0] <= sl_writedata[7:0]; 127 | end 128 | if(sl_write & sl_byteenable[1]) begin 129 | max_iters[15:8] <= sl_writedata[15:8]; 130 | end 131 | end // if 132 | end // always 133 | 134 | endmodule 135 | 136 | -------------------------------------------------------------------------------- /ip/mandelbrot_colorizer/mandelbrot_colorizer_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2017 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 16.1 5 | 6 | 7 | # 8 | # module mandelbrot_colorizer 9 | # 10 | set_module_property DESCRIPTION "" 11 | set_module_property NAME mandelbrot_colorizer 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property AUTHOR RSF 16 | set_module_property DISPLAY_NAME mandelbrot_colorizer 17 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 18 | set_module_property EDITABLE false 19 | set_module_property REPORT_TO_TALKBACK false 20 | set_module_property ALLOW_GREYBOX_GENERATION false 21 | set_module_property REPORT_HIERARCHY false 22 | 23 | 24 | # 25 | # file sets 26 | # 27 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 28 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL mandelbrot_colorizer 29 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 30 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 31 | add_fileset_file mandelbrot_colorizer.v VERILOG PATH mandelbrot_colorizer.v TOP_LEVEL_FILE 32 | 33 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 34 | set_fileset_property SIM_VERILOG TOP_LEVEL mandelbrot_colorizer 35 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 36 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true 37 | add_fileset_file mandelbrot_colorizer.v VERILOG PATH mandelbrot_colorizer.v 38 | 39 | 40 | # 41 | # parameters 42 | # 43 | 44 | 45 | # 46 | # display items 47 | # 48 | 49 | 50 | # 51 | # connection point clock 52 | # 53 | add_interface clock clock end 54 | set_interface_property clock clockRate 0 55 | set_interface_property clock ENABLED true 56 | set_interface_property clock EXPORT_OF "" 57 | set_interface_property clock PORT_NAME_MAP "" 58 | set_interface_property clock CMSIS_SVD_VARIABLES "" 59 | set_interface_property clock SVD_ADDRESS_GROUP "" 60 | 61 | add_interface_port clock clk clk Input 1 62 | 63 | 64 | # 65 | # connection point reset 66 | # 67 | add_interface reset reset end 68 | set_interface_property reset associatedClock clock 69 | set_interface_property reset synchronousEdges DEASSERT 70 | set_interface_property reset ENABLED true 71 | set_interface_property reset EXPORT_OF "" 72 | set_interface_property reset PORT_NAME_MAP "" 73 | set_interface_property reset CMSIS_SVD_VARIABLES "" 74 | set_interface_property reset SVD_ADDRESS_GROUP "" 75 | 76 | add_interface_port reset reset reset Input 1 77 | 78 | 79 | # 80 | # connection point sl 81 | # 82 | add_interface sl avalon end 83 | set_interface_property sl addressUnits WORDS 84 | set_interface_property sl associatedClock clock 85 | set_interface_property sl associatedReset reset 86 | set_interface_property sl bitsPerSymbol 8 87 | set_interface_property sl burstOnBurstBoundariesOnly false 88 | set_interface_property sl burstcountUnits WORDS 89 | set_interface_property sl explicitAddressSpan 0 90 | set_interface_property sl holdTime 0 91 | set_interface_property sl linewrapBursts false 92 | set_interface_property sl maximumPendingReadTransactions 0 93 | set_interface_property sl maximumPendingWriteTransactions 0 94 | set_interface_property sl readLatency 0 95 | set_interface_property sl readWaitTime 1 96 | set_interface_property sl setupTime 0 97 | set_interface_property sl timingUnits Cycles 98 | set_interface_property sl writeWaitTime 0 99 | set_interface_property sl ENABLED true 100 | set_interface_property sl EXPORT_OF "" 101 | set_interface_property sl PORT_NAME_MAP "" 102 | set_interface_property sl CMSIS_SVD_VARIABLES "" 103 | set_interface_property sl SVD_ADDRESS_GROUP "" 104 | 105 | add_interface_port sl sl_read read Input 1 106 | add_interface_port sl sl_write write Input 1 107 | add_interface_port sl sl_byteenable byteenable Input 4 108 | add_interface_port sl sl_writedata writedata Input 32 109 | add_interface_port sl sl_readdata readdata Output 32 110 | add_interface_port sl sl_waitrequest waitrequest Output 1 111 | set_interface_assignment sl embeddedsw.configuration.isFlash 0 112 | set_interface_assignment sl embeddedsw.configuration.isMemoryDevice 0 113 | set_interface_assignment sl embeddedsw.configuration.isNonVolatileStorage 0 114 | set_interface_assignment sl embeddedsw.configuration.isPrintableDevice 0 115 | 116 | 117 | # 118 | # connection point in_pixel 119 | # 120 | add_interface in_pixel avalon_streaming end 121 | set_interface_property in_pixel associatedClock clock 122 | set_interface_property in_pixel associatedReset reset 123 | set_interface_property in_pixel dataBitsPerSymbol 8 124 | set_interface_property in_pixel errorDescriptor "" 125 | set_interface_property in_pixel firstSymbolInHighOrderBits true 126 | set_interface_property in_pixel maxChannel 0 127 | set_interface_property in_pixel readyLatency 0 128 | set_interface_property in_pixel ENABLED true 129 | set_interface_property in_pixel EXPORT_OF "" 130 | set_interface_property in_pixel PORT_NAME_MAP "" 131 | set_interface_property in_pixel CMSIS_SVD_VARIABLES "" 132 | set_interface_property in_pixel SVD_ADDRESS_GROUP "" 133 | 134 | add_interface_port in_pixel in_pixel_snk_data data Input 32 135 | add_interface_port in_pixel in_pixel_snk_ready ready Output 1 136 | add_interface_port in_pixel in_pixel_snk_valid valid Input 1 137 | 138 | 139 | # 140 | # connection point out_pixel 141 | # 142 | add_interface out_pixel avalon_streaming start 143 | set_interface_property out_pixel associatedClock clock 144 | set_interface_property out_pixel associatedReset reset 145 | set_interface_property out_pixel dataBitsPerSymbol 8 146 | set_interface_property out_pixel errorDescriptor "" 147 | set_interface_property out_pixel firstSymbolInHighOrderBits true 148 | set_interface_property out_pixel maxChannel 0 149 | set_interface_property out_pixel readyLatency 0 150 | set_interface_property out_pixel ENABLED true 151 | set_interface_property out_pixel EXPORT_OF "" 152 | set_interface_property out_pixel PORT_NAME_MAP "" 153 | set_interface_property out_pixel CMSIS_SVD_VARIABLES "" 154 | set_interface_property out_pixel SVD_ADDRESS_GROUP "" 155 | 156 | add_interface_port out_pixel out_pixel_src_data data Output 32 157 | add_interface_port out_pixel out_pixel_src_ready ready Input 1 158 | add_interface_port out_pixel out_pixel_src_valid valid Output 1 159 | 160 | -------------------------------------------------------------------------------- /ip/mandelbrot_controller/mandelbrot_controller.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2017 Intel Corporation 2 | // SPDX-License-Identifier: MIT 3 | 4 | `timescale 1 ps / 1 ps 5 | 6 | // This core provides an AVMM slave interface to store the values required to 7 | // form an input vector to the mandelbrot_image_feeder core along with a go bit 8 | // to send the input vector and a status register that can monitor the read bits 9 | // on the AVST output pipeline stage. 10 | // 11 | // See the address map and register bit definitions in the comments below. 12 | 13 | module mandelbrot_controller( 14 | 15 | // clock and reset for component 16 | input wire clk, 17 | input wire reset, 18 | 19 | // avmm slave interface, sl 20 | input wire sl_read, 21 | input wire sl_write, 22 | input wire [ 3:0] sl_byteenable, 23 | input wire [ 3:0] sl_address, 24 | input wire [ 31:0] sl_writedata, 25 | output wire [ 31:0] sl_readdata, 26 | output wire sl_waitrequest, 27 | output wire sl_readdatavalid, 28 | 29 | // avst source interface, out_vector 30 | // this is a multi-data vector containing: 31 | // pix_map_height[15:0] @ src_data[183:168] 32 | // pix_map_width[15:0] @ src_data[167:152] 33 | // pix_buf_ptr[31:0] @ src_data[151:120] 34 | //line_count_shift[ 7:0] @ src_data[119:112] 35 | // step_dim[31:0] @ src_data[111: 80] 36 | // max_iters[15:0] @ src_data[ 79: 64] 37 | // cr[31:0] @ src_data[ 63: 32] 38 | // ci[31:0] @ src_data[ 31: 0] 39 | output wire [183:0] out_vector_src_data, 40 | output wire out_vector_src_valid, 41 | input wire out_vector_src_ready 42 | ); 43 | 44 | wire ready_i; 45 | wire ready_o; 46 | wire [183:0] in_vector; 47 | 48 | reg [ 15:0] pix_map_height; 49 | reg [ 15:0] pix_map_width; 50 | reg [ 31:0] pix_buf_ptr; 51 | reg [ 7:0] line_count_shift; 52 | reg [ 31:0] step_dim; 53 | reg [ 15:0] max_iters; 54 | reg [ 31:0] cr; 55 | reg [ 31:0] ci; 56 | 57 | reg go; 58 | reg [ 31:0] readdata; 59 | reg readdatavalid; 60 | 61 | assign in_vector = { 62 | pix_map_height, 63 | pix_map_width, 64 | pix_buf_ptr, 65 | line_count_shift, 66 | step_dim, 67 | max_iters, 68 | cr, 69 | ci 70 | }; 71 | 72 | assign ready_o = out_vector_src_ready; 73 | 74 | altera_avalon_st_pipeline_base 75 | #( 76 | .BITS_PER_SYMBOL(184) 77 | ) st_pipe ( 78 | .clk (clk), 79 | .reset (reset), 80 | .in_ready (ready_i), 81 | .in_valid (go), 82 | .in_data (in_vector), 83 | .out_ready (ready_o), 84 | .out_valid (out_vector_src_valid), 85 | .out_data (out_vector_src_data) 86 | ); 87 | 88 | // avmm slave control 89 | // 90 | // all registers are allocated as 32-bit registers in the address map but some 91 | // registers are smaller than 32-bits. 92 | // 93 | // status[ 1:0] @ 0x09 3-bit register {ready_i, ready_o, go} 94 | // control[ 0:0] @ 0x08 1-bit register {go} 95 | // pix_map_height[15:0] @ 0x07 16-bit register 96 | // pix_map_width[15:0] @ 0x06 16-bit register 97 | // pix_buf_ptr[31:0] @ 0x05 32-bit register 98 | // line_count_shift[ 7:0] @ 0x04 8-bit register only 3 lsb are valid 99 | // step_dim[31:0] @ 0x03 32-bit register 100 | // max_iters[15:0] @ 0x02 16-bit register 101 | // cr[31:0] @ 0x01 32-bit register 102 | // ci[31:0] @ 0x00 32-bit register 103 | 104 | assign sl_readdata = readdata; 105 | assign sl_waitrequest = 1'b0; 106 | assign sl_readdatavalid = readdatavalid; 107 | 108 | assign sl_waitrequest = 1'b0; 109 | 110 | always @ (posedge clk, posedge reset) begin 111 | if(reset) begin 112 | pix_map_height <= 16'd0; 113 | pix_map_width <= 16'd0; 114 | pix_buf_ptr <= 32'd0; 115 | line_count_shift <= 8'd0; 116 | step_dim <= 32'd0; 117 | max_iters <= 16'd0; 118 | cr <= 32'd0; 119 | ci <= 32'd0; 120 | 121 | go <= 1'd0; 122 | readdata <= 32'd0; 123 | readdatavalid <= 1'd0; 124 | 125 | end else begin // if(reset) 126 | readdatavalid <= 1'b0; 127 | if(sl_write) begin 128 | case(sl_address) 129 | 4'h0: begin // ci 130 | if(sl_byteenable[0]) ci[ 7:0 ] <= sl_writedata[ 7:0 ]; 131 | if(sl_byteenable[1]) ci[15:8 ] <= sl_writedata[15:8 ]; 132 | if(sl_byteenable[2]) ci[23:16] <= sl_writedata[23:16]; 133 | if(sl_byteenable[3]) ci[31:24] <= sl_writedata[31:24]; 134 | end 135 | 4'h1: begin // cr 136 | if(sl_byteenable[0]) cr[ 7:0 ] <= sl_writedata[ 7:0 ]; 137 | if(sl_byteenable[1]) cr[15:8 ] <= sl_writedata[15:8 ]; 138 | if(sl_byteenable[2]) cr[23:16] <= sl_writedata[23:16]; 139 | if(sl_byteenable[3]) cr[31:24] <= sl_writedata[31:24]; 140 | end 141 | 4'h2: begin // max_iters 142 | if(sl_byteenable[0]) max_iters[ 7:0 ] <= sl_writedata[ 7:0 ]; 143 | if(sl_byteenable[1]) max_iters[15:8 ] <= sl_writedata[15:8 ]; 144 | end 145 | 4'h3: begin // step_dim 146 | if(sl_byteenable[0]) step_dim[ 7:0 ] <= sl_writedata[ 7:0 ]; 147 | if(sl_byteenable[1]) step_dim[15:8 ] <= sl_writedata[15:8 ]; 148 | if(sl_byteenable[2]) step_dim[23:16] <= sl_writedata[23:16]; 149 | if(sl_byteenable[3]) step_dim[31:24] <= sl_writedata[31:24]; 150 | end 151 | 4'h4: begin // line_count_shift 152 | if(sl_byteenable[0]) line_count_shift[ 7:0 ] <= {5'd0, sl_writedata[ 2:0 ]}; 153 | end 154 | 4'h5: begin // pix_buf_ptr 155 | if(sl_byteenable[0]) pix_buf_ptr[ 7:0 ] <= sl_writedata[ 7:0 ]; 156 | if(sl_byteenable[1]) pix_buf_ptr[15:8 ] <= sl_writedata[15:8 ]; 157 | if(sl_byteenable[2]) pix_buf_ptr[23:16] <= sl_writedata[23:16]; 158 | if(sl_byteenable[3]) pix_buf_ptr[31:24] <= sl_writedata[31:24]; 159 | end 160 | 4'h6: begin // pix_map_width 161 | if(sl_byteenable[0]) pix_map_width[ 7:0 ] <= sl_writedata[ 7:0 ]; 162 | if(sl_byteenable[1]) pix_map_width[15:8 ] <= sl_writedata[15:8 ]; 163 | end 164 | 4'h7: begin // pix_map_height 165 | if(sl_byteenable[0]) pix_map_height[ 7:0 ] <= sl_writedata[ 7:0 ]; 166 | if(sl_byteenable[1]) pix_map_height[15:8 ] <= sl_writedata[15:8 ]; 167 | end 168 | 4'h8: begin // control 169 | if(sl_byteenable[0]) go <= sl_writedata[0]; 170 | end 171 | default:; 172 | endcase 173 | end // if(sl_write) 174 | 175 | if(sl_read) begin 176 | readdatavalid <= 1'b1; 177 | case(sl_address) 178 | 4'h0: readdata <= ci[31:0]; 179 | 4'h1: readdata <= cr[31:0]; 180 | 4'h2: readdata <= {16'd0, max_iters[15:0]}; 181 | 4'h3: readdata <= step_dim[31:0]; 182 | 4'h4: readdata <= {24'd0, line_count_shift[7:0]}; 183 | 4'h5: readdata <= pix_buf_ptr[31:0]; 184 | 4'h6: readdata <= {16'd0, pix_map_width[15:0]}; 185 | 4'h7: readdata <= {16'd0, pix_map_height[15:0]}; 186 | 4'h8: readdata <= {31'd0, go}; 187 | 4'h9: readdata <= {29'd0, ready_i, ready_o, go}; 188 | default: readdata <= 32'd0; 189 | endcase 190 | end // if(sl_read) 191 | 192 | if(go) begin 193 | if(ready_i) go <= 1'b0; 194 | end // if(go) 195 | end // else 196 | end // always 197 | 198 | endmodule 199 | 200 | -------------------------------------------------------------------------------- /ip/mandelbrot_controller/mandelbrot_controller_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2017 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 16.1 5 | 6 | 7 | # 8 | # module mandelbrot_controller 9 | # 10 | set_module_property DESCRIPTION "" 11 | set_module_property NAME mandelbrot_controller 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property AUTHOR RSF 16 | set_module_property DISPLAY_NAME mandelbrot_controller 17 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 18 | set_module_property EDITABLE false 19 | set_module_property REPORT_TO_TALKBACK false 20 | set_module_property ALLOW_GREYBOX_GENERATION false 21 | set_module_property REPORT_HIERARCHY false 22 | 23 | 24 | # 25 | # file sets 26 | # 27 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 28 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL mandelbrot_controller 29 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 30 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 31 | add_fileset_file mandelbrot_controller.v VERILOG PATH mandelbrot_controller.v TOP_LEVEL_FILE 32 | 33 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 34 | set_fileset_property SIM_VERILOG TOP_LEVEL mandelbrot_controller 35 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 36 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false 37 | add_fileset_file mandelbrot_controller.v VERILOG PATH mandelbrot_controller.v 38 | 39 | 40 | # 41 | # parameters 42 | # 43 | 44 | 45 | # 46 | # display items 47 | # 48 | 49 | 50 | # 51 | # connection point clock 52 | # 53 | add_interface clock clock end 54 | set_interface_property clock clockRate 0 55 | set_interface_property clock ENABLED true 56 | set_interface_property clock EXPORT_OF "" 57 | set_interface_property clock PORT_NAME_MAP "" 58 | set_interface_property clock CMSIS_SVD_VARIABLES "" 59 | set_interface_property clock SVD_ADDRESS_GROUP "" 60 | 61 | add_interface_port clock clk clk Input 1 62 | 63 | 64 | # 65 | # connection point reset 66 | # 67 | add_interface reset reset end 68 | set_interface_property reset associatedClock clock 69 | set_interface_property reset synchronousEdges DEASSERT 70 | set_interface_property reset ENABLED true 71 | set_interface_property reset EXPORT_OF "" 72 | set_interface_property reset PORT_NAME_MAP "" 73 | set_interface_property reset CMSIS_SVD_VARIABLES "" 74 | set_interface_property reset SVD_ADDRESS_GROUP "" 75 | 76 | add_interface_port reset reset reset Input 1 77 | 78 | 79 | # 80 | # connection point sl 81 | # 82 | add_interface sl avalon end 83 | set_interface_property sl addressUnits WORDS 84 | set_interface_property sl associatedClock clock 85 | set_interface_property sl associatedReset reset 86 | set_interface_property sl bitsPerSymbol 8 87 | set_interface_property sl burstOnBurstBoundariesOnly false 88 | set_interface_property sl burstcountUnits WORDS 89 | set_interface_property sl explicitAddressSpan 0 90 | set_interface_property sl holdTime 0 91 | set_interface_property sl linewrapBursts false 92 | set_interface_property sl maximumPendingReadTransactions 1 93 | set_interface_property sl maximumPendingWriteTransactions 0 94 | set_interface_property sl readLatency 0 95 | set_interface_property sl readWaitTime 1 96 | set_interface_property sl setupTime 0 97 | set_interface_property sl timingUnits Cycles 98 | set_interface_property sl writeWaitTime 0 99 | set_interface_property sl ENABLED true 100 | set_interface_property sl EXPORT_OF "" 101 | set_interface_property sl PORT_NAME_MAP "" 102 | set_interface_property sl CMSIS_SVD_VARIABLES "" 103 | set_interface_property sl SVD_ADDRESS_GROUP "" 104 | 105 | add_interface_port sl sl_read read Input 1 106 | add_interface_port sl sl_write write Input 1 107 | add_interface_port sl sl_byteenable byteenable Input 4 108 | add_interface_port sl sl_address address Input 4 109 | add_interface_port sl sl_writedata writedata Input 32 110 | add_interface_port sl sl_readdata readdata Output 32 111 | add_interface_port sl sl_waitrequest waitrequest Output 1 112 | add_interface_port sl sl_readdatavalid readdatavalid Output 1 113 | set_interface_assignment sl embeddedsw.configuration.isFlash 0 114 | set_interface_assignment sl embeddedsw.configuration.isMemoryDevice 0 115 | set_interface_assignment sl embeddedsw.configuration.isNonVolatileStorage 0 116 | set_interface_assignment sl embeddedsw.configuration.isPrintableDevice 0 117 | 118 | 119 | # 120 | # connection point out_vector 121 | # 122 | add_interface out_vector avalon_streaming start 123 | set_interface_property out_vector associatedClock clock 124 | set_interface_property out_vector associatedReset reset 125 | set_interface_property out_vector dataBitsPerSymbol 8 126 | set_interface_property out_vector errorDescriptor "" 127 | set_interface_property out_vector firstSymbolInHighOrderBits true 128 | set_interface_property out_vector maxChannel 0 129 | set_interface_property out_vector readyLatency 0 130 | set_interface_property out_vector ENABLED true 131 | set_interface_property out_vector EXPORT_OF "" 132 | set_interface_property out_vector PORT_NAME_MAP "" 133 | set_interface_property out_vector CMSIS_SVD_VARIABLES "" 134 | set_interface_property out_vector SVD_ADDRESS_GROUP "" 135 | 136 | add_interface_port out_vector out_vector_src_data data Output 184 137 | add_interface_port out_vector out_vector_src_valid valid Output 1 138 | add_interface_port out_vector out_vector_src_ready ready Input 1 139 | 140 | -------------------------------------------------------------------------------- /ip/mandelbrot_coord_feeder/mandelbrot_coord_feeder.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2017 Intel Corporation 2 | // SPDX-License-Identifier: MIT 3 | 4 | `timescale 1 ps / 1 ps 5 | 6 | // This core takes an input vector generated by the mandelbrot_image_feeder core 7 | // and creates an msgdma descriptor for the work load. It pushes the descriptor 8 | // into an msgdma controller and then it proceeds to process the coordinate run 9 | // length described in the input vector by passing each coordinate into an 10 | // avst_mandelbrot_engine core and retrieving the result. It then passes the 11 | // results into the data sink of the msgdma core to be written to memory. 12 | // 13 | // Optionally a mandelbrot_colorizer core can be placed between this core and 14 | // the msgdma data sink in order to apply colorization to the result values. 15 | 16 | module mandelbrot_coord_feeder( 17 | 18 | // clock and reset for component 19 | input wire clk, 20 | input wire reset, 21 | 22 | // avst sink interface, in_vector 23 | // this is a multi-data vector containing: 24 | // pix_buf_ptr[31:0] @ snk_data[151:120] 25 | // line_count[ 7:0] @ snk_data[119:112] 26 | // step_dim[31:0] @ snk_data[111: 80] 27 | // max_iters[15:0] @ snk_data[ 79: 64] 28 | // cr[31:0] @ snk_data[ 63: 32] 29 | // ci[31:0] @ snk_data[ 31: 0] 30 | input wire [151:0] in_vector_snk_data, 31 | input wire in_vector_snk_valid, 32 | output wire in_vector_snk_ready, 33 | 34 | // avst source interface, out_descriptor 35 | // this is an msgdma descriptor 36 | output wire [255:0] out_descriptor_src_data, 37 | output wire out_descriptor_src_valid, 38 | input wire out_descriptor_src_ready, 39 | 40 | // avst sink interface, in_response 41 | // this is an msgdma response 42 | input wire [255:0] in_response_snk_data, 43 | input wire in_response_snk_valid, 44 | output wire in_response_snk_ready, 45 | 46 | // avst source interface, out_vector 47 | // this is a multi-data vector containing: 48 | // max_iters[15:0] @ src_data[79:64] 49 | // cr[31:0] @ src_data[63:32] 50 | // ci[31:0] @ src_data[31:0] 51 | output wire [ 79:0] out_vector_src_data, 52 | output wire out_vector_src_valid, 53 | input wire out_vector_src_ready, 54 | 55 | // avst sink interface, in_result 56 | input wire [ 15:0] in_result_snk_data, 57 | input wire in_result_snk_valid, 58 | output wire in_result_snk_ready, 59 | 60 | // avst source interface, out_pixel 61 | output wire [ 31:0] out_pixel_src_data, 62 | output wire out_pixel_src_valid, 63 | input wire out_pixel_src_ready 64 | ); 65 | 66 | localparam STATE_IDLE = 2'b00; 67 | localparam STATE_LOAD_DESC = 2'b01; 68 | localparam STATE_FEED_COORDS = 2'b10; 69 | 70 | wire [31:0] v_ci; 71 | wire [31:0] v_cr; 72 | wire [15:0] v_max_iters; 73 | wire [31:0] v_step_dim; 74 | wire [ 7:0] v_line_count; 75 | wire [31:0] v_pix_buf_ptr; 76 | 77 | reg [31:0] ci; 78 | reg [31:0] cr; 79 | reg [15:0] max_iters; 80 | reg [31:0] step_dim; 81 | reg [ 7:0] line_count; 82 | reg [31:0] pix_buf_ptr; 83 | 84 | reg [ 1:0] state; 85 | reg [10:0] pixel_count; 86 | reg [10:0] started_count; 87 | reg [10:0] complete_count; 88 | reg holding_result; 89 | reg [15:0] result; 90 | reg [31:0] dma_length; 91 | 92 | assign { 93 | v_pix_buf_ptr, 94 | v_line_count, 95 | v_step_dim, 96 | v_max_iters, 97 | v_cr, 98 | v_ci 99 | } = { 100 | in_vector_snk_data[151:120], 101 | in_vector_snk_data[119:112], 102 | in_vector_snk_data[111: 80], 103 | in_vector_snk_data[79:64], 104 | in_vector_snk_data[63:32], 105 | in_vector_snk_data[31:0] 106 | }; 107 | 108 | // in_vector 109 | assign in_vector_snk_ready = (state == STATE_IDLE) ? 110 | (1'b1) : (1'b0); 111 | 112 | // out_descriptor 113 | assign out_descriptor_src_valid = (state == STATE_LOAD_DESC) ? 114 | (1'b1) : (1'b0); 115 | 116 | // MSGDMA WRITE MASTER DESCRIPTOR INPUT FORMAT 117 | // 118 | // THIS IS THE RAW HDL DEFINITION OF THE COMMAND DESCRIPTOR INPUT VECTOR 119 | // 120 | // descriptor_address = {snk_command_data[123:92], snk_command_data[31:0]}; 121 | // descriptor_length = snk_command_data[63:32]; 122 | // descriptor_programmable_burst_count = snk_command_data[75:68]; 123 | // descriptor_stride = snk_command_data[91:76]; 124 | // descriptor_end_on_eop_enable = snk_command_data[64]; 125 | // sw_stop_in = snk_command_data[66]; 126 | // sw_reset_in = snk_command_data[67]; 127 | // 128 | // TO VISUALIZE THIS A BIT EASIER, SOME ASCII ART 129 | // 130 | // |255--128| 131 | // These 16 bytes from bits 255 through 128 are not used, so set them to ZERO. 132 | // 133 | // |127--120|119--112|111--104|103---96|95----88|87----80|79----72|71----64| 134 | // ++++ ++++++++ ++++++++ ++++++++ ++++++++ ++++++++ ++++++++ ++++++ + 135 | // |--------address[123:92]-----------||--stride[91:76]-||---.---||| | 136 | // | || | 137 | // programmable_burst_count[75:68] --+ || | 138 | // sw_reset_in[67] --+| | 139 | // sw_stop_in[66] --+ | 140 | // end_on_eop_enable[64] --+ 141 | // 142 | // |63----56|55----48|47----40|39----32|31----24|23----16|15-----8|7------0| 143 | // ++++++++ ++++++++ ++++++++ ++++++++ ++++++++ ++++++++ ++++++++ ++++++++ 144 | // |---------length[63:32]-----------| |----------address[31:0]----------| 145 | 146 | assign out_descriptor_src_data = { 147 | {128{1'b0}}, // unused[255:128] 148 | {4{1'b0}}, // unused[127:124] 149 | {32{1'b0}}, // address[123:92] 150 | {16{1'b0}}, // stride[91:76] 151 | line_count, // programmable_burst_count[75:68] 152 | 1'b0, // sw_reset_in[67] 153 | 1'b0, // sw_stop_in[66] 154 | 1'b0, // unused[65] 155 | 1'b0, // end_on_eop_enable[64] 156 | dma_length, // length[63:32] 157 | pix_buf_ptr // address[31:0] 158 | }; 159 | 160 | // in_response 161 | assign in_response_snk_ready = 1'b1; 162 | 163 | // out_vector 164 | assign out_vector_src_valid = ((state == STATE_FEED_COORDS) && 165 | (started_count < pixel_count)) ? 166 | (1'b1) : (1'b0); 167 | 168 | assign out_vector_src_data = {max_iters, cr, ci}; 169 | 170 | // in_result 171 | assign in_result_snk_ready = ((state == STATE_FEED_COORDS) && 172 | (~holding_result)) ? 173 | (1'b1) : (1'b0); 174 | 175 | // out_pixel 176 | assign out_pixel_src_valid = ((state == STATE_FEED_COORDS) && 177 | (holding_result)) ? 178 | (1'b1) : (1'b0); 179 | 180 | assign out_pixel_src_data = {result[7:0], result[15:8], 8'h00, 8'h00}; 181 | 182 | always @ (posedge clk or posedge reset) begin 183 | if(reset) begin 184 | ci <= 32'd0; 185 | cr <= 32'd0; 186 | max_iters <= 16'd0; 187 | step_dim <= 32'd0; 188 | line_count <= 8'd0; 189 | pix_buf_ptr <= 32'd0; 190 | 191 | pixel_count <= 10'h0; 192 | started_count <= 10'h0; 193 | complete_count <= 10'h0; 194 | holding_result <= 1'b0; 195 | result <= 16'h0; 196 | dma_length <= 32'h0; 197 | state <= STATE_IDLE; 198 | 199 | end else begin 200 | 201 | case(state) 202 | STATE_IDLE: begin 203 | ci <= v_ci; 204 | cr <= v_cr; 205 | max_iters <= v_max_iters; 206 | step_dim <= v_step_dim; 207 | line_count <= v_line_count; 208 | pix_buf_ptr <= v_pix_buf_ptr; 209 | 210 | pixel_count <= {v_line_count, 3'b000}; 211 | started_count <= 10'h0; 212 | complete_count <= 10'h0; 213 | holding_result <= 1'b0; 214 | result <= 16'h0; 215 | dma_length <= {v_line_count, 5'b00000}; 216 | 217 | if(in_vector_snk_valid & in_vector_snk_ready) begin 218 | state <= STATE_LOAD_DESC; 219 | end 220 | end 221 | STATE_LOAD_DESC: begin 222 | 223 | if(out_descriptor_src_valid & out_descriptor_src_ready) begin 224 | state <= STATE_FEED_COORDS; 225 | end 226 | end 227 | STATE_FEED_COORDS: begin 228 | 229 | if(out_vector_src_valid & out_vector_src_ready) begin 230 | started_count <= started_count + 1'b1; 231 | cr <= cr + step_dim; 232 | end 233 | 234 | if(in_result_snk_valid & in_result_snk_ready) begin 235 | holding_result <= 1'b1; 236 | result <= in_result_snk_data; 237 | end 238 | 239 | if(out_pixel_src_valid & out_pixel_src_ready) begin 240 | holding_result <= 1'b0; 241 | complete_count <= complete_count + 1'b1; 242 | end 243 | 244 | if(complete_count == pixel_count) begin 245 | state <= STATE_IDLE; 246 | end 247 | end 248 | endcase 249 | 250 | end // if 251 | end // always 252 | 253 | endmodule 254 | 255 | -------------------------------------------------------------------------------- /ip/mandelbrot_coord_feeder/mandelbrot_coord_feeder_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2017 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 16.1 5 | 6 | 7 | # 8 | # module mandelbrot_coord_feeder 9 | # 10 | set_module_property DESCRIPTION "" 11 | set_module_property NAME mandelbrot_coord_feeder 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property AUTHOR RSF 16 | set_module_property DISPLAY_NAME mandelbrot_coord_feeder 17 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 18 | set_module_property EDITABLE false 19 | set_module_property REPORT_TO_TALKBACK false 20 | set_module_property ALLOW_GREYBOX_GENERATION false 21 | set_module_property REPORT_HIERARCHY false 22 | 23 | 24 | # 25 | # file sets 26 | # 27 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 28 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL mandelbrot_coord_feeder 29 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 30 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 31 | add_fileset_file mandelbrot_coord_feeder.v VERILOG PATH mandelbrot_coord_feeder.v TOP_LEVEL_FILE 32 | 33 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 34 | set_fileset_property SIM_VERILOG TOP_LEVEL mandelbrot_coord_feeder 35 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 36 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false 37 | add_fileset_file mandelbrot_coord_feeder.v VERILOG PATH mandelbrot_coord_feeder.v 38 | 39 | 40 | # 41 | # parameters 42 | # 43 | 44 | 45 | # 46 | # display items 47 | # 48 | 49 | 50 | # 51 | # connection point clock 52 | # 53 | add_interface clock clock end 54 | set_interface_property clock clockRate 0 55 | set_interface_property clock ENABLED true 56 | set_interface_property clock EXPORT_OF "" 57 | set_interface_property clock PORT_NAME_MAP "" 58 | set_interface_property clock CMSIS_SVD_VARIABLES "" 59 | set_interface_property clock SVD_ADDRESS_GROUP "" 60 | 61 | add_interface_port clock clk clk Input 1 62 | 63 | 64 | # 65 | # connection point reset 66 | # 67 | add_interface reset reset end 68 | set_interface_property reset associatedClock clock 69 | set_interface_property reset synchronousEdges DEASSERT 70 | set_interface_property reset ENABLED true 71 | set_interface_property reset EXPORT_OF "" 72 | set_interface_property reset PORT_NAME_MAP "" 73 | set_interface_property reset CMSIS_SVD_VARIABLES "" 74 | set_interface_property reset SVD_ADDRESS_GROUP "" 75 | 76 | add_interface_port reset reset reset Input 1 77 | 78 | 79 | # 80 | # connection point in_vector 81 | # 82 | add_interface in_vector avalon_streaming end 83 | set_interface_property in_vector associatedClock clock 84 | set_interface_property in_vector associatedReset reset 85 | set_interface_property in_vector dataBitsPerSymbol 8 86 | set_interface_property in_vector errorDescriptor "" 87 | set_interface_property in_vector firstSymbolInHighOrderBits true 88 | set_interface_property in_vector maxChannel 0 89 | set_interface_property in_vector readyLatency 0 90 | set_interface_property in_vector ENABLED true 91 | set_interface_property in_vector EXPORT_OF "" 92 | set_interface_property in_vector PORT_NAME_MAP "" 93 | set_interface_property in_vector CMSIS_SVD_VARIABLES "" 94 | set_interface_property in_vector SVD_ADDRESS_GROUP "" 95 | 96 | add_interface_port in_vector in_vector_snk_data data Input 152 97 | add_interface_port in_vector in_vector_snk_ready ready Output 1 98 | add_interface_port in_vector in_vector_snk_valid valid Input 1 99 | 100 | 101 | # 102 | # connection point out_descriptor 103 | # 104 | add_interface out_descriptor avalon_streaming start 105 | set_interface_property out_descriptor associatedClock clock 106 | set_interface_property out_descriptor associatedReset reset 107 | set_interface_property out_descriptor dataBitsPerSymbol 256 108 | set_interface_property out_descriptor errorDescriptor "" 109 | set_interface_property out_descriptor firstSymbolInHighOrderBits true 110 | set_interface_property out_descriptor maxChannel 0 111 | set_interface_property out_descriptor readyLatency 0 112 | set_interface_property out_descriptor ENABLED true 113 | set_interface_property out_descriptor EXPORT_OF "" 114 | set_interface_property out_descriptor PORT_NAME_MAP "" 115 | set_interface_property out_descriptor CMSIS_SVD_VARIABLES "" 116 | set_interface_property out_descriptor SVD_ADDRESS_GROUP "" 117 | 118 | add_interface_port out_descriptor out_descriptor_src_data data Output 256 119 | add_interface_port out_descriptor out_descriptor_src_ready ready Input 1 120 | add_interface_port out_descriptor out_descriptor_src_valid valid Output 1 121 | 122 | 123 | # 124 | # connection point in_response 125 | # 126 | add_interface in_response avalon_streaming end 127 | set_interface_property in_response associatedClock clock 128 | set_interface_property in_response associatedReset reset 129 | set_interface_property in_response dataBitsPerSymbol 256 130 | set_interface_property in_response errorDescriptor "" 131 | set_interface_property in_response firstSymbolInHighOrderBits true 132 | set_interface_property in_response maxChannel 0 133 | set_interface_property in_response readyLatency 0 134 | set_interface_property in_response ENABLED true 135 | set_interface_property in_response EXPORT_OF "" 136 | set_interface_property in_response PORT_NAME_MAP "" 137 | set_interface_property in_response CMSIS_SVD_VARIABLES "" 138 | set_interface_property in_response SVD_ADDRESS_GROUP "" 139 | 140 | add_interface_port in_response in_response_snk_data data Input 256 141 | add_interface_port in_response in_response_snk_ready ready Output 1 142 | add_interface_port in_response in_response_snk_valid valid Input 1 143 | 144 | 145 | # 146 | # connection point out_vector 147 | # 148 | add_interface out_vector avalon_streaming start 149 | set_interface_property out_vector associatedClock clock 150 | set_interface_property out_vector associatedReset reset 151 | set_interface_property out_vector dataBitsPerSymbol 8 152 | set_interface_property out_vector errorDescriptor "" 153 | set_interface_property out_vector firstSymbolInHighOrderBits true 154 | set_interface_property out_vector maxChannel 0 155 | set_interface_property out_vector readyLatency 0 156 | set_interface_property out_vector ENABLED true 157 | set_interface_property out_vector EXPORT_OF "" 158 | set_interface_property out_vector PORT_NAME_MAP "" 159 | set_interface_property out_vector CMSIS_SVD_VARIABLES "" 160 | set_interface_property out_vector SVD_ADDRESS_GROUP "" 161 | 162 | add_interface_port out_vector out_vector_src_data data Output 80 163 | add_interface_port out_vector out_vector_src_ready ready Input 1 164 | add_interface_port out_vector out_vector_src_valid valid Output 1 165 | 166 | 167 | # 168 | # connection point in_result 169 | # 170 | add_interface in_result avalon_streaming end 171 | set_interface_property in_result associatedClock clock 172 | set_interface_property in_result associatedReset reset 173 | set_interface_property in_result dataBitsPerSymbol 8 174 | set_interface_property in_result errorDescriptor "" 175 | set_interface_property in_result firstSymbolInHighOrderBits true 176 | set_interface_property in_result maxChannel 0 177 | set_interface_property in_result readyLatency 0 178 | set_interface_property in_result ENABLED true 179 | set_interface_property in_result EXPORT_OF "" 180 | set_interface_property in_result PORT_NAME_MAP "" 181 | set_interface_property in_result CMSIS_SVD_VARIABLES "" 182 | set_interface_property in_result SVD_ADDRESS_GROUP "" 183 | 184 | add_interface_port in_result in_result_snk_data data Input 16 185 | add_interface_port in_result in_result_snk_ready ready Output 1 186 | add_interface_port in_result in_result_snk_valid valid Input 1 187 | 188 | 189 | # 190 | # connection point out_pixel 191 | # 192 | add_interface out_pixel avalon_streaming start 193 | set_interface_property out_pixel associatedClock clock 194 | set_interface_property out_pixel associatedReset reset 195 | set_interface_property out_pixel dataBitsPerSymbol 8 196 | set_interface_property out_pixel errorDescriptor "" 197 | set_interface_property out_pixel firstSymbolInHighOrderBits true 198 | set_interface_property out_pixel maxChannel 0 199 | set_interface_property out_pixel readyLatency 0 200 | set_interface_property out_pixel ENABLED true 201 | set_interface_property out_pixel EXPORT_OF "" 202 | set_interface_property out_pixel PORT_NAME_MAP "" 203 | set_interface_property out_pixel CMSIS_SVD_VARIABLES "" 204 | set_interface_property out_pixel SVD_ADDRESS_GROUP "" 205 | 206 | add_interface_port out_pixel out_pixel_src_data data Output 32 207 | add_interface_port out_pixel out_pixel_src_ready ready Input 1 208 | add_interface_port out_pixel out_pixel_src_valid valid Output 1 209 | 210 | -------------------------------------------------------------------------------- /ip/mandelbrot_image_feeder/mandelbrot_image_feeder.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2017 Intel Corporation 2 | // SPDX-License-Identifier: MIT 3 | 4 | `timescale 1 ps / 1 ps 5 | 6 | // This core takes a input vector that describes the top left coordinate of a 7 | // Mandelbrot image to be computed along with the image geometry and output 8 | // buffer location. This core then computes each cluster of pixel workload to 9 | // be passed down to a mandelbrot_coordinate_feeder core for processing and it 10 | // sends that out of its source interface. This core computes the workloads for 11 | // the entire image defined by the input vector. 12 | 13 | module mandelbrot_image_feeder( 14 | 15 | // clock and reset for component 16 | input wire clk, 17 | input wire reset, 18 | 19 | // avst sink interface, in_vector 20 | // this is a multi-data vector containing: 21 | // pix_map_height[15:0] @ snk_data[183:168] 22 | // pix_map_width[15:0] @ snk_data[167:152] 23 | // pix_buf_ptr[31:0] @ snk_data[151:120] 24 | //line_count_shift[ 7:0] @ snk_data[119:112] 25 | // step_dim[31:0] @ snk_data[111: 80] 26 | // max_iters[15:0] @ snk_data[ 79: 64] 27 | // cr[31:0] @ snk_data[ 63: 32] 28 | // ci[31:0] @ snk_data[ 31: 0] 29 | input wire [183:0] in_vector_snk_data, 30 | input wire in_vector_snk_valid, 31 | output wire in_vector_snk_ready, 32 | 33 | // avst source interface, out_vector 34 | // this is a multi-data vector containing: 35 | // pix_buf_ptr[31:0] @ snk_data[151:120] 36 | // line_count[ 7:0] @ snk_data[119:112] 37 | // step_dim[31:0] @ snk_data[111: 80] 38 | // max_iters[15:0] @ snk_data[ 79: 64] 39 | // cr[31:0] @ snk_data[ 63: 32] 40 | // ci[31:0] @ snk_data[ 31: 0] 41 | output wire [151:0] out_vector_src_data, 42 | output wire out_vector_src_valid, 43 | input wire out_vector_src_ready 44 | ); 45 | 46 | localparam STATE_IDLE = 2'b00; 47 | localparam STATE_FEED_COORDS = 2'b01; 48 | localparam STATE_WAIT_READY = 2'b10; 49 | 50 | wire [31:0] v_ci; 51 | wire [31:0] v_cr; 52 | wire [15:0] v_max_iters; 53 | wire [31:0] v_step_dim; 54 | wire [ 7:0] v_line_count_shift; 55 | wire [31:0] v_pix_buf_ptr; 56 | wire [15:0] v_pix_map_width; 57 | wire [15:0] v_pix_map_height; 58 | 59 | reg [31:0] ci; 60 | reg [31:0] cr; 61 | reg [15:0] max_iters; 62 | reg [31:0] step_dim; 63 | reg [31:0] multi_step_dim; 64 | reg [ 7:0] line_count; 65 | reg [31:0] pix_buf_ptr; 66 | reg [15:0] pix_map_width; 67 | reg [15:0] pix_map_height; 68 | 69 | reg [ 1:0] state; 70 | reg [10:0] pixel_count; 71 | reg [15:0] cr_x_count; 72 | reg [15:0] ci_y_count; 73 | reg [31:0] dma_length; 74 | reg [31:0] leftmost_cr; 75 | 76 | assign { 77 | v_pix_map_height, 78 | v_pix_map_width, 79 | v_pix_buf_ptr, 80 | v_line_count_shift, 81 | v_step_dim, 82 | v_max_iters, 83 | v_cr, 84 | v_ci 85 | } = { 86 | in_vector_snk_data[183:168], 87 | in_vector_snk_data[167:152], 88 | in_vector_snk_data[151:120], 89 | in_vector_snk_data[119:112], 90 | in_vector_snk_data[111: 80], 91 | in_vector_snk_data[79:64], 92 | in_vector_snk_data[63:32], 93 | in_vector_snk_data[31:0] 94 | }; 95 | 96 | // in_vector 97 | assign in_vector_snk_ready = (state == STATE_IDLE) ? 98 | (1'b1) : (1'b0); 99 | 100 | // out_vector 101 | assign out_vector_src_valid = (state == STATE_FEED_COORDS) ? 102 | (1'b1) : (1'b0); 103 | 104 | assign out_vector_src_data = {pix_buf_ptr, line_count, step_dim, max_iters, cr, ci}; 105 | 106 | 107 | always @ (posedge clk or posedge reset) begin 108 | if(reset) begin 109 | ci <= 32'd0; 110 | cr <= 32'd0; 111 | max_iters <= 16'd0; 112 | step_dim <= 32'd0; 113 | multi_step_dim <= 32'd0; 114 | line_count <= 8'd0; 115 | pix_buf_ptr <= 32'd0; 116 | pix_map_width <= 16'd0; 117 | pix_map_height <= 16'd0; 118 | 119 | leftmost_cr <= 32'd0; 120 | pixel_count <= 10'h0; 121 | cr_x_count <= 16'h0; 122 | ci_y_count <= 16'h0; 123 | dma_length <= 32'h0; 124 | state <= STATE_IDLE; 125 | 126 | end else begin 127 | 128 | case(state) 129 | STATE_IDLE: begin 130 | ci <= v_ci; 131 | cr <= v_cr; 132 | max_iters <= v_max_iters; 133 | step_dim <= v_step_dim; 134 | multi_step_dim <= (v_step_dim << v_line_count_shift[2:0]) << 3; 135 | line_count <= 1'b1 << v_line_count_shift[2:0]; 136 | pix_buf_ptr <= v_pix_buf_ptr; 137 | pix_map_width <= v_pix_map_width; 138 | pix_map_height <= v_pix_map_height; 139 | 140 | leftmost_cr <= v_cr; 141 | pixel_count <= (1'b1 << v_line_count_shift[2:0]) << 3; 142 | cr_x_count <= 16'h0; 143 | ci_y_count <= 16'h0; 144 | dma_length <= (1'b1 << v_line_count_shift[2:0]) << 5; 145 | 146 | if(in_vector_snk_valid & in_vector_snk_ready) begin 147 | state <= STATE_FEED_COORDS; 148 | end 149 | end 150 | STATE_FEED_COORDS: begin 151 | 152 | if(out_vector_src_valid & out_vector_src_ready) begin 153 | 154 | if((cr_x_count + pixel_count) < pix_map_width) begin 155 | cr_x_count <= cr_x_count + pixel_count; 156 | cr <= cr + multi_step_dim; 157 | end else begin 158 | if((ci_y_count + 1'b1) < pix_map_height) begin 159 | ci_y_count <= ci_y_count + 16'd1; 160 | ci <= ci - step_dim; 161 | cr_x_count <= 16'd0; 162 | cr <= leftmost_cr; 163 | end else begin 164 | state <= STATE_WAIT_READY; 165 | end 166 | end 167 | 168 | pix_buf_ptr <= pix_buf_ptr + dma_length; 169 | end 170 | end 171 | STATE_WAIT_READY: begin 172 | 173 | if(out_vector_src_ready) begin 174 | state <= STATE_IDLE; 175 | end 176 | end 177 | endcase 178 | 179 | end // if 180 | end // always 181 | 182 | endmodule 183 | 184 | -------------------------------------------------------------------------------- /ip/mandelbrot_image_feeder/mandelbrot_image_feeder_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2017 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 16.1 5 | 6 | 7 | # 8 | # module mandelbrot_image_feeder 9 | # 10 | set_module_property DESCRIPTION "" 11 | set_module_property NAME mandelbrot_image_feeder 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property AUTHOR RSF 16 | set_module_property DISPLAY_NAME mandelbrot_image_feeder 17 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 18 | set_module_property EDITABLE false 19 | set_module_property REPORT_TO_TALKBACK false 20 | set_module_property ALLOW_GREYBOX_GENERATION false 21 | set_module_property REPORT_HIERARCHY false 22 | 23 | 24 | # 25 | # file sets 26 | # 27 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 28 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL mandelbrot_image_feeder 29 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 30 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 31 | add_fileset_file mandelbrot_image_feeder.v VERILOG PATH mandelbrot_image_feeder.v TOP_LEVEL_FILE 32 | 33 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 34 | set_fileset_property SIM_VERILOG TOP_LEVEL mandelbrot_image_feeder 35 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 36 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false 37 | add_fileset_file mandelbrot_image_feeder.v VERILOG PATH mandelbrot_image_feeder.v 38 | 39 | 40 | # 41 | # parameters 42 | # 43 | 44 | 45 | # 46 | # display items 47 | # 48 | 49 | 50 | # 51 | # connection point clock 52 | # 53 | add_interface clock clock end 54 | set_interface_property clock clockRate 0 55 | set_interface_property clock ENABLED true 56 | set_interface_property clock EXPORT_OF "" 57 | set_interface_property clock PORT_NAME_MAP "" 58 | set_interface_property clock CMSIS_SVD_VARIABLES "" 59 | set_interface_property clock SVD_ADDRESS_GROUP "" 60 | 61 | add_interface_port clock clk clk Input 1 62 | 63 | 64 | # 65 | # connection point reset 66 | # 67 | add_interface reset reset end 68 | set_interface_property reset associatedClock clock 69 | set_interface_property reset synchronousEdges DEASSERT 70 | set_interface_property reset ENABLED true 71 | set_interface_property reset EXPORT_OF "" 72 | set_interface_property reset PORT_NAME_MAP "" 73 | set_interface_property reset CMSIS_SVD_VARIABLES "" 74 | set_interface_property reset SVD_ADDRESS_GROUP "" 75 | 76 | add_interface_port reset reset reset Input 1 77 | 78 | 79 | # 80 | # connection point in_vector 81 | # 82 | add_interface in_vector avalon_streaming end 83 | set_interface_property in_vector associatedClock clock 84 | set_interface_property in_vector associatedReset reset 85 | set_interface_property in_vector dataBitsPerSymbol 8 86 | set_interface_property in_vector errorDescriptor "" 87 | set_interface_property in_vector firstSymbolInHighOrderBits true 88 | set_interface_property in_vector maxChannel 0 89 | set_interface_property in_vector readyLatency 0 90 | set_interface_property in_vector ENABLED true 91 | set_interface_property in_vector EXPORT_OF "" 92 | set_interface_property in_vector PORT_NAME_MAP "" 93 | set_interface_property in_vector CMSIS_SVD_VARIABLES "" 94 | set_interface_property in_vector SVD_ADDRESS_GROUP "" 95 | 96 | add_interface_port in_vector in_vector_snk_data data Input 184 97 | add_interface_port in_vector in_vector_snk_ready ready Output 1 98 | add_interface_port in_vector in_vector_snk_valid valid Input 1 99 | 100 | 101 | # 102 | # connection point out_vector 103 | # 104 | add_interface out_vector avalon_streaming start 105 | set_interface_property out_vector associatedClock clock 106 | set_interface_property out_vector associatedReset reset 107 | set_interface_property out_vector dataBitsPerSymbol 8 108 | set_interface_property out_vector errorDescriptor "" 109 | set_interface_property out_vector firstSymbolInHighOrderBits true 110 | set_interface_property out_vector maxChannel 0 111 | set_interface_property out_vector readyLatency 0 112 | set_interface_property out_vector ENABLED true 113 | set_interface_property out_vector EXPORT_OF "" 114 | set_interface_property out_vector PORT_NAME_MAP "" 115 | set_interface_property out_vector CMSIS_SVD_VARIABLES "" 116 | set_interface_property out_vector SVD_ADDRESS_GROUP "" 117 | 118 | add_interface_port out_vector out_vector_src_data data Output 152 119 | add_interface_port out_vector out_vector_src_ready ready Input 1 120 | add_interface_port out_vector out_vector_src_valid valid Output 1 121 | 122 | -------------------------------------------------------------------------------- /ip/mandelbrot_sub/mandelbrot_engine_subsys.qsys: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 86 | 91 | 96 | 101 | 106 | 111 | 116 | 117 | 118 | 119 | 120 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 147 | 152 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 168 | 173 | 178 | 183 | 188 | 193 | 198 | 203 | 208 | 213 | 218 | 223 | 228 | 233 | 238 | 239 | 240 | 241 | 242 | 243 | -------------------------------------------------------------------------------- /ip/power_on_reset/power_on_reset.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016 Intel Corporation 2 | // SPDX-License-Identifier: MIT 3 | 4 | /* 5 | This component produces a power on reset strobe. 6 | 7 | At power up when the FPGA enters user mode the registers of the 8 | altera_std_synchronizer core will all be set to ZERO. As the 1'b1 input 9 | propogates through the shift chain of the synchronizer the specified power on 10 | reset delay count will be measured to the number of clocks specified by the 11 | POR_COUNT parameter. 12 | 13 | This is intended to create a rather short power on reset delay, between 2 and 32 14 | clocks, so the inefficient use of a shift chain to measure this is not a 15 | significant concern. The advantage of using the altera_std_synchronizer is that 16 | it takes care of the quartus properties to preserve the registers of the shift 17 | chain and apply the SDC constraints for us. 18 | 19 | To constrain the outputs of this component in your own SDC constraints, you can 20 | locate the output registers of the component with something like this: 21 | [get_registers {*power_on_reset:*|output_reg}] 22 | 23 | */ 24 | `timescale 1 ps / 1 ps 25 | module power_on_reset #( 26 | parameter POR_COUNT = 20 // MUST BE 2 or greater 27 | ) ( 28 | input wire clk, 29 | output wire reset 30 | ); 31 | 32 | wire sync_dout; 33 | altera_std_synchronizer #( 34 | .depth (POR_COUNT) 35 | ) power_on_reset_std_sync_inst ( 36 | .clk (clk), 37 | .reset_n (1'b1), 38 | .din (1'b1), 39 | .dout (sync_dout) 40 | ); 41 | 42 | reg output_reg; 43 | initial begin 44 | output_reg <= 1'b0; 45 | end 46 | 47 | always @ (posedge clk) begin 48 | output_reg <= sync_dout; 49 | end 50 | 51 | assign reset = ~output_reg; 52 | 53 | endmodule 54 | 55 | -------------------------------------------------------------------------------- /ip/power_on_reset/power_on_reset_hw.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require -exact qsys 15.1 5 | 6 | 7 | # 8 | # module power_on_reset 9 | # 10 | set_module_property DESCRIPTION "Create a power on reset pulse." 11 | set_module_property NAME power_on_reset 12 | set_module_property VERSION 1.0 13 | set_module_property INTERNAL false 14 | set_module_property OPAQUE_ADDRESS_MAP true 15 | set_module_property GROUP "Reset Components" 16 | set_module_property AUTHOR RSF 17 | set_module_property DISPLAY_NAME power_on_reset 18 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 19 | set_module_property EDITABLE false 20 | set_module_property REPORT_TO_TALKBACK false 21 | set_module_property ALLOW_GREYBOX_GENERATION false 22 | set_module_property REPORT_HIERARCHY false 23 | set_module_property ELABORATION_CALLBACK elaborate 24 | set_module_property VALIDATION_CALLBACK validate 25 | 26 | 27 | # 28 | # file sets 29 | # 30 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 31 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL power_on_reset 32 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 33 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 34 | add_fileset_file power_on_reset.v VERILOG PATH power_on_reset.v TOP_LEVEL_FILE 35 | 36 | add_fileset SIM_VERILOG SIM_VERILOG "" "" 37 | set_fileset_property SIM_VERILOG TOP_LEVEL power_on_reset 38 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false 39 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false 40 | add_fileset_file power_on_reset.v VERILOG PATH power_on_reset.v 41 | 42 | add_fileset SIM_VHDL SIM_VHDL "" "" 43 | set_fileset_property SIM_VHDL TOP_LEVEL power_on_reset 44 | set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false 45 | set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE true 46 | add_fileset_file power_on_reset.v VERILOG PATH power_on_reset.v 47 | 48 | 49 | # 50 | # parameters 51 | # 52 | add_parameter POR_COUNT INTEGER 53 | set_parameter_property POR_COUNT DEFAULT_VALUE 20 54 | set_parameter_property POR_COUNT DISPLAY_NAME "Power On Reset Count" 55 | set_parameter_property POR_COUNT TYPE INTEGER 56 | set_parameter_property POR_COUNT GROUP "Power On Reset Duration" 57 | set_parameter_property POR_COUNT UNITS Cycles 58 | set_parameter_property POR_COUNT ALLOWED_RANGES 2:128 59 | set_parameter_property POR_COUNT DESCRIPTION "The number of clocks from power up until this reset is released, plus one clock. Minimum value is 2 and maximum value is 128." 60 | set_parameter_property POR_COUNT HDL_PARAMETER true 61 | set_parameter_property POR_COUNT AFFECTS_VALIDATION true 62 | set_parameter_property POR_COUNT AFFECTS_ELABORATION true 63 | 64 | add_parameter CLOCK_FREQ LONG 65 | set_parameter_property CLOCK_FREQ DEFAULT_VALUE 0 66 | set_parameter_property CLOCK_FREQ DISPLAY_NAME "Input clock rate" 67 | set_parameter_property CLOCK_FREQ DESCRIPTION {Input clock rate from system.} 68 | set_parameter_property CLOCK_FREQ UNITS None 69 | set_parameter_property CLOCK_FREQ DERIVED true 70 | set_parameter_property CLOCK_FREQ HDL_PARAMETER false 71 | set_parameter_property CLOCK_FREQ VISIBLE false 72 | set_parameter_property CLOCK_FREQ SYSTEM_INFO {CLOCK_RATE "clock"} 73 | set_parameter_property CLOCK_FREQ AFFECTS_VALIDATION true 74 | set_parameter_property CLOCK_FREQ AFFECTS_ELABORATION true 75 | 76 | add_parameter DURATION_TIME FLOAT 77 | set_parameter_property DURATION_TIME DEFAULT_VALUE "0.0" 78 | set_parameter_property DURATION_TIME DISPLAY_NAME "Power On Reset Duration" 79 | set_parameter_property DURATION_TIME DESCRIPTION {Calculation of the power on reset duration. Clock input must be connected to a known frequency for calculation to appear.} 80 | set_parameter_property DURATION_TIME UNITS Nanoseconds 81 | set_parameter_property DURATION_TIME GROUP "Power On Reset Duration" 82 | set_parameter_property DURATION_TIME DERIVED true 83 | set_parameter_property DURATION_TIME HDL_PARAMETER false 84 | set_parameter_property DURATION_TIME VISIBLE false 85 | 86 | add_parameter DURATION_STRING STRING 87 | set_parameter_property DURATION_STRING DEFAULT_VALUE "Unknown clock input frequency." 88 | set_parameter_property DURATION_STRING DISPLAY_NAME "Power On Reset Duration" 89 | set_parameter_property DURATION_STRING DESCRIPTION {Calculation of the power on reset duration. Clock input must be connected to a known frequency for calculation to appear.} 90 | set_parameter_property DURATION_STRING UNITS none 91 | set_parameter_property DURATION_STRING GROUP "Power On Reset Duration" 92 | set_parameter_property DURATION_STRING DERIVED true 93 | set_parameter_property DURATION_STRING HDL_PARAMETER false 94 | set_parameter_property DURATION_STRING VISIBLE false 95 | 96 | 97 | # 98 | # display items 99 | # 100 | 101 | 102 | # 103 | # connection point clock 104 | # 105 | add_interface clock clock end 106 | set_interface_property clock clockRate 0 107 | set_interface_property clock ENABLED true 108 | set_interface_property clock EXPORT_OF "" 109 | set_interface_property clock PORT_NAME_MAP "" 110 | set_interface_property clock CMSIS_SVD_VARIABLES "" 111 | set_interface_property clock SVD_ADDRESS_GROUP "" 112 | 113 | add_interface_port clock clk clk Input 1 114 | 115 | 116 | # 117 | # connection point reset 118 | # 119 | add_interface reset reset start 120 | set_interface_property reset associatedClock clock 121 | set_interface_property reset associatedDirectReset "" 122 | set_interface_property reset associatedResetSinks "" 123 | set_interface_property reset synchronousEdges DEASSERT 124 | set_interface_property reset ENABLED true 125 | set_interface_property reset EXPORT_OF "" 126 | set_interface_property reset PORT_NAME_MAP "" 127 | set_interface_property reset CMSIS_SVD_VARIABLES "" 128 | set_interface_property reset SVD_ADDRESS_GROUP "" 129 | 130 | add_interface_port reset reset reset Output 1 131 | 132 | 133 | proc elaborate {} { 134 | set clk_freq [ get_parameter_value CLOCK_FREQ ] 135 | if { $clk_freq == 0.0 } { 136 | set_parameter_value DURATION_TIME 0.0 137 | set_parameter_property DURATION_TIME VISIBLE false 138 | set_parameter_property DURATION_STRING VISIBLE true 139 | } else { 140 | set clk_period [ expr {1.0 / $clk_freq} ] 141 | set por_count [ expr {[ get_parameter_value POR_COUNT ] * 1.0} ] 142 | set por_period [ expr {$clk_period * $por_count} ] 143 | set duration [ expr {$por_period / 0.000000001} ] 144 | set round_duration [ expr {round($duration)} ] 145 | set_parameter_value DURATION_TIME $round_duration 146 | set_parameter_property DURATION_TIME VISIBLE true 147 | set_parameter_property DURATION_STRING VISIBLE false 148 | } 149 | } 150 | 151 | proc validate {} { 152 | set_module_assignment embeddedsw.CMacro.POR_COUNT [ get_parameter_value POR_COUNT ] 153 | set_module_assignment embeddedsw.CMacro.CLOCK_FREQ [ get_parameter_value CLOCK_FREQ ] 154 | } 155 | 156 | -------------------------------------------------------------------------------- /ip/reset_synchronizer/reset_sync_block.sdc: -------------------------------------------------------------------------------- 1 | #Since the synchronizer will resync the reset input we are cutting the input reset into the resync register. 2 | set_false_path -to [get_pins -compatibility_mode -nocase -nowarn *|reset_sync_block*|synchronizer_reg*] 3 | -------------------------------------------------------------------------------- /ip/reset_synchronizer/reset_sync_block.v: -------------------------------------------------------------------------------- 1 | module reset_sync_block ( 2 | clk_in, 3 | reset_in, 4 | clk_out, 5 | reset_out 6 | ); 7 | 8 | parameter SYNC_DEPTH = 3; // needs to be at least two but on new FPGAs should be at least 3 9 | parameter ADDITIONAL_DEPTH = 2; // needs to be at least two stages, increase this if recovery errors occur even with DISABLE_GLOBAL_NETWORK is set to 1 10 | parameter DISABLE_GLOBAL_NETWORK = 1; // set to 1 to prevent synchronized reset from getting promoted to global network, enable this if recovery errors occur from FFs hooked up to reset_out 11 | parameter SYNC_BOTH_EDGES = 0; // set to 1 synchronize the reset_in to both edges, set to 0 to allow reset_out to deassert asynchronously and assert synchronously 12 | 13 | input clk_in; 14 | input reset_in; 15 | output wire clk_out; 16 | output wire reset_out; 17 | 18 | wire synchronized_reset; 19 | 20 | 21 | 22 | generate 23 | if (SYNC_BOTH_EDGES == 0) // use reset_in as an asynchronous clear for reset_out but sychronize reset_out to the rising clock edge 24 | begin 25 | 26 | deassert_synchronizer the_deassert_synchronizer( 27 | .clk (clk_in), 28 | .reset_in (reset_in), 29 | .reset_out (synchronized_reset) 30 | ); 31 | defparam the_deassert_synchronizer.SYNC_DEPTH = SYNC_DEPTH; 32 | defparam the_deassert_synchronizer.ADDITIONAL_DEPTH = ADDITIONAL_DEPTH; 33 | defparam the_deassert_synchronizer.DISABLE_GLOBAL_NETWORK = DISABLE_GLOBAL_NETWORK; 34 | 35 | 36 | end 37 | else // just synchronize and pipeline reset_in and feed it back out as reset_out 38 | begin 39 | 40 | both_synchronizer the_both_synchronizer( 41 | .clk (clk_in), 42 | .reset_in (reset_in), 43 | .reset_out (synchronized_reset) 44 | ); 45 | defparam the_both_synchronizer.SYNC_DEPTH = SYNC_DEPTH; 46 | defparam the_both_synchronizer.ADDITIONAL_DEPTH = ADDITIONAL_DEPTH; 47 | defparam the_both_synchronizer.DISABLE_GLOBAL_NETWORK = DISABLE_GLOBAL_NETWORK; 48 | 49 | end 50 | endgenerate 51 | 52 | 53 | assign clk_out = clk_in; // this signal is included to make it easier to export a clock and reset to the level above it 54 | assign reset_out = synchronized_reset; 55 | 56 | endmodule 57 | 58 | 59 | 60 | 61 | module deassert_synchronizer ( 62 | clk, 63 | reset_in, 64 | reset_out 65 | ); 66 | parameter SYNC_DEPTH = 3; 67 | parameter ADDITIONAL_DEPTH = 2; 68 | parameter DISABLE_GLOBAL_NETWORK = 1; 69 | 70 | input clk; 71 | input reset_in; 72 | output wire reset_out; 73 | 74 | (* preserve *) reg [SYNC_DEPTH-1 : 0] synchronizer_reg; 75 | 76 | 77 | // shifting the 0 from the MSB down to the LSB, this will make keeping things off the global network much easier 78 | always @ (posedge clk or posedge reset_in) 79 | begin 80 | if (reset_in == 1'b1) 81 | begin 82 | synchronizer_reg <= {SYNC_DEPTH {1'b1}}; 83 | end 84 | else 85 | begin 86 | synchronizer_reg[SYNC_DEPTH-1] <= 1'b0; 87 | synchronizer_reg[SYNC_DEPTH-2:0] <= synchronizer_reg[SYNC_DEPTH-1:1]; // right shift by 1 88 | end 89 | end 90 | 91 | // need to keep the declaration of output_pipeline_reg in the same scope as the driving of reset_out 92 | generate 93 | if (DISABLE_GLOBAL_NETWORK == 0) 94 | begin 95 | reg [ADDITIONAL_DEPTH-1:0] output_pipeline_reg; 96 | 97 | // using the LSB output of the synchronizer as the asynchronous reset of the output pipeline 98 | always @ (posedge clk or posedge synchronizer_reg[0]) 99 | begin 100 | if (synchronizer_reg[0] == 1'b1) 101 | begin 102 | output_pipeline_reg <= {ADDITIONAL_DEPTH {1'b1}}; 103 | end 104 | else 105 | begin 106 | output_pipeline_reg[ADDITIONAL_DEPTH-1] <= 1'b0; // feeding the synchronizer output into this pipeline's MSB 107 | output_pipeline_reg[ADDITIONAL_DEPTH-2:0] <= output_pipeline_reg[ADDITIONAL_DEPTH-1:1]; // right shift by 1 108 | end 109 | end 110 | 111 | assign reset_out = output_pipeline_reg[0]; 112 | end 113 | else 114 | begin 115 | (* altera_attribute = "-name GLOBAL_SIGNAL OFF" *) reg [ADDITIONAL_DEPTH-1:0] output_pipeline_reg; 116 | 117 | // using the LSB output of the synchronizer as the asynchronous reset of the output pipeline 118 | always @ (posedge clk or posedge synchronizer_reg[0]) 119 | begin 120 | if (synchronizer_reg[0] == 1'b1) 121 | begin 122 | output_pipeline_reg <= {ADDITIONAL_DEPTH {1'b1}}; 123 | end 124 | else 125 | begin 126 | output_pipeline_reg[ADDITIONAL_DEPTH-1] <= 1'b0; // feeding the synchronizer output into this pipeline's MSB 127 | output_pipeline_reg[ADDITIONAL_DEPTH-2:0] <= output_pipeline_reg[ADDITIONAL_DEPTH-1:1]; // right shift by 1 128 | end 129 | end 130 | 131 | assign reset_out = output_pipeline_reg[0]; 132 | end 133 | endgenerate 134 | 135 | 136 | 137 | endmodule 138 | 139 | 140 | module both_synchronizer ( 141 | clk, 142 | reset_in, 143 | reset_out 144 | ); 145 | 146 | parameter SYNC_DEPTH = 3; 147 | parameter ADDITIONAL_DEPTH = 2; 148 | parameter DISABLE_GLOBAL_NETWORK = 1; 149 | 150 | input clk; 151 | input reset_in; 152 | output wire reset_out; 153 | 154 | (* preserve *) reg [SYNC_DEPTH-1 : 0] synchronizer_reg; 155 | 156 | 157 | always @ (posedge clk or posedge reset_in) 158 | begin 159 | if (reset_in == 1'b1) 160 | begin 161 | synchronizer_reg <= {SYNC_DEPTH {1'b1}}; 162 | end 163 | else 164 | begin 165 | synchronizer_reg[SYNC_DEPTH-1] <= 1'b0; 166 | synchronizer_reg[SYNC_DEPTH-2:0] <= synchronizer_reg[SYNC_DEPTH-1:1]; // right shift by 1 167 | end 168 | end 169 | 170 | // need to keep the declaration of output_pipeline_reg in the same scope as the driving of reset_out 171 | generate 172 | if (DISABLE_GLOBAL_NETWORK == 0) 173 | begin 174 | reg [ADDITIONAL_DEPTH-1:0] output_pipeline_reg; 175 | 176 | always @ (posedge clk) 177 | begin 178 | output_pipeline_reg[ADDITIONAL_DEPTH-1] <= synchronizer_reg[0]; // feeding the synchronizer output into this pipeline's MSB 179 | output_pipeline_reg[ADDITIONAL_DEPTH-2:0] <= output_pipeline_reg[ADDITIONAL_DEPTH-1:1]; // right shift by 1 180 | end 181 | 182 | assign reset_out = output_pipeline_reg[0]; 183 | end 184 | else 185 | begin 186 | (* altera_attribute = "-name GLOBAL_SIGNAL OFF" *) reg [ADDITIONAL_DEPTH-1:0] output_pipeline_reg; 187 | 188 | always @ (posedge clk) 189 | begin 190 | output_pipeline_reg[ADDITIONAL_DEPTH-1] <= synchronizer_reg[0]; // feeding the synchronizer output into this pipeline's MSB 191 | output_pipeline_reg[ADDITIONAL_DEPTH-2:0] <= output_pipeline_reg[ADDITIONAL_DEPTH-1:1]; // right shift by 1 192 | end 193 | 194 | assign reset_out = output_pipeline_reg[0]; 195 | end 196 | endgenerate 197 | 198 | 199 | endmodule 200 | -------------------------------------------------------------------------------- /mks/bootscript.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | ################################################ 5 | 6 | # BOOTSCRIPT_REVISION_LIST := $(filter $REVISION_LIST) 7 | 8 | BOOTSCRIPT_REVISION_LIST := $(REVISION_LIST) 9 | 10 | #define build_boot_script 11 | 12 | #HELP_TARGETS_$1 += $1.boot_script_image 13 | #$1.boot_script_image.HELP := Make boot script image for $1 14 | 15 | #.PHONY: $1.boot_script_image 16 | #$1.boot_script_image: $1/u-boot.scr 17 | # 18 | #$1/boot.script : Makefile $$(PRELOADER_STAMP_$1) 19 | # @$(MKDIR) $1 20 | # @$(RM) $$@ 21 | # @$(ECHO) "Generating $$@" 22 | # @$(ECHO) "fatload mmc 0:1 \$$$$fpgadata $$(QUARTUS_RBF_$1);" >>$$@ 23 | # @$(ECHO) "fpga load 0 \$$$$fpgadata \$$$$filesize;" >>$$@ 24 | # @$(ECHO) "set fdtimage $$(DEVICE_TREE_BLOB_$1);" >>$$@ 25 | # @$(ECHO) "set rootfsimage rootfs.img;" >>$$@ 26 | # @$(ECHO) "run bridge_enable_handoff;" >>$$@ 27 | # @$(ECHO) "setenv mmcroot /dev/ram;;" >>$$@ 28 | # @$(ECHO) "setenv mmcload '\$$$${mmcloadcmd} mmc 0:\$$$${mmcloadpart} \$$$${loadaddr} \$$$${bootimage}; \$$$${mmcloadcmd} mmc 0:\$$$${mmcloadpart} \$$$${fdtaddr} \$$$${fdtimage}; \$$$${mmcloadcmd} mmc 0:\$$$${mmcloadpart} \$$$${fpgadata} \$$$${rootfsimage}';" >>$$@ 29 | # @$(ECHO) "setenv mmcboot 'setenv bootargs console=ttyS0,115200 root=\$$$${mmcroot} rw rootwait; bootz \$$$${loadaddr} \$$$${fpgadata} \$$$${fdtaddr}';" >>$$@ 30 | # @$(ECHO) "run mmcload;" >>$$@ 31 | # @$(ECHO) "run mmcboot;" >>$$@ 32 | 33 | #$1/u-boot.scr: $1/boot.script 34 | # $$(UBOOT_MKIMAGE_$1) -A arm -O linux -T script -C none -a 0 -e 0 -n "bootscript" -d $1/boot.script $1/u-boot.scr 35 | 36 | 37 | #$$(UBOOT_MKIMAGE_$1): $$(PRELOADER_STAMP_$1) 38 | 39 | #AR_FILES += $$(UBOOT_MKIMAGE_$1) 40 | #AR_FILES += $1/u-boot.scr: $1/boot.script 41 | 42 | #endef # build_boot_script 43 | 44 | 45 | #$(foreach r, $(BOOTSCRIPT_REVISION_LIST), $(eval $(call build_boot_script,$r))) 46 | 47 | u-boot.scr: boot.script 48 | $(MKIMAGE) -A arm -O linux -T script -C none -a 0 -e 0 -n "bootscript" -d $< $@ 49 | -------------------------------------------------------------------------------- /mks/default.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | ################################################ 5 | # Tools 6 | 7 | CAT := cat 8 | CD := cd 9 | CHMOD := chmod 10 | CP := cp -rf 11 | ECHO := echo 12 | DATE := date 13 | FIND := find 14 | GREP := grep 15 | HEAD := head 16 | MKDIR := mkdir -p 17 | MV := mv 18 | RM := rm -Rf 19 | SED := sed 20 | TAR := tar 21 | TOUCH := touch 22 | WHICH := which 23 | XZ := xz 24 | MKIMAGE := mkimage 25 | CAT := cat 26 | 27 | # Preloader 28 | 29 | SBT.CREATE_SETTINGS := bsp-create-settings 30 | SBT.GENERATE := bsp-generate-files 31 | 32 | DTS.SOPC2DTS := java -jar $(PWD)/sopc2dts/sopc2dts.jar 33 | 34 | DTS.DTC := dtc/dtc 35 | 36 | # Helpful Macros 37 | SPACE := $(empty) $(empty) 38 | 39 | ifndef COMSPEC 40 | ifdef ComSpec 41 | COMSPEC = $(ComSpec) 42 | endif # ComSpec 43 | endif # COMSPEC 44 | 45 | ifdef COMSPEC # if Windows OS 46 | IS_WINDOWS_HOST := 1 47 | endif 48 | 49 | ifeq ($(IS_WINDOWS_HOST),1) 50 | ifneq ($(shell $(WHICH) cygwin1.dll 2>/dev/null),) 51 | IS_CYGWIN_HOST := 1 52 | endif 53 | endif 54 | 55 | ifneq ($(shell $(WHICH) quartus 2>/dev/null),) 56 | HAVE_QUARTUS := 1 57 | endif 58 | 59 | ifeq ($(HAVE_QUARTUS),1) 60 | HAVE_QSYS := 1 61 | endif 62 | 63 | ################################################ 64 | 65 | ################################################ 66 | # Target Stamping 67 | 68 | SOCEDS_VERSION := $(if $(wildcard $(SOCEDS_DEST_ROOT)/version.txt),$(shell $(CAT) $(SOCEDS_DEST_ROOT)/version.txt 2>/dev/null | $(GREP) Version | $(HEAD) -n1 | $(SED) -e 's,^Version[: \t=]*\([0-9.]*\).*,\1,g' 2>/dev/null)) 69 | 70 | #define get_stamp_dir 71 | #stamp$(if $(SOCEDS_VERSION),/$(SOCEDS_VERSION)) 72 | #endef 73 | 74 | define get_stamp_dir 75 | stamp 76 | endef 77 | 78 | define get_stamp_target 79 | $(get_stamp_dir)$(if $1,/$1.stamp,$(error ERROR: Arg 1 missing to $0 function)) 80 | endef 81 | 82 | define stamp_target 83 | @$(MKDIR) $(@D) 84 | @$(TOUCH) $@ 85 | endef 86 | 87 | ################################################ 88 | 89 | ################################################ 90 | # Archiving & Cleaning your QuartusII/QSys Project 91 | 92 | AR_TIMESTAMP := $(if $(SOCEDS_VERSION),$(subst .,_,$(SOCEDS_VERSION))_)$(subst $(SPACE),,$(shell $(DATE) +%m%d%Y_%k%M%S)) 93 | 94 | AR_DIR := tgz 95 | AR_FILE := $(AR_DIR)/$(basename $(firstword $(wildcard *.qpf)))_$(AR_TIMESTAMP).tar.gz 96 | 97 | AR_REGEX += \ 98 | Makefile \ 99 | *.mk 100 | 101 | AR_FILTER_OUT += %_tb.qsys 102 | ################################################################################ 103 | -------------------------------------------------------------------------------- /mks/devicetree.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | ################################################ 5 | # Device Tree 6 | 7 | #DTS_COMMON = sopc2dts_overlay.xml 8 | #DTS.CLOCKINFO ?= hps_clock_info.xml 9 | DTS.SOPC2DTS_ARGS += $(if $(DTS_COMMON),--board $(DTS_COMMON)) 10 | DTS.SOPC2DTS_ARGS += --bridge-removal all 11 | DTS.SOPC2DTS_ARGS += --bridge-ranges bridge 12 | DTS.SOPC2DTS_ARGS += --clocks 13 | DTS.SOPC2DTS_ARGS += --overlay-target "/soc/base-fpga-region" 14 | DTS.SOPC2DTS_ARGS += --pov hps_0_bridges 15 | DTS.SOPC2DTS_ARGS += --pov-type overlay 16 | DTS.SOPC2DTS_ARGS += --type dts 17 | 18 | 19 | # $(DTS.SOPC2DTS) --input $$(QSYS_SOPCINFO_$1) --output $$(DEVICE_TREE_SOURCE_$1) --firmware-name $1.rbf $$(DTS.SOPC2DTS_ARGS_$1) 2>&1 | tee logs/$$(notdir $$@).log 20 | 21 | define build_dts_revisions 22 | 23 | DTS.SOPC2DTS_ARGS_$1 += $(DTS.SOPC2DTS_ARGS) 24 | #DTS.SOPC2DTS_ARGS_$1 += $(if $$(DTS_BOARDINFO_$1),--board $$(DTS_BOARDINFO_$1)) 25 | 26 | $$(DEVICE_TREE_SOURCE_$1): $$(QSYS_SOPCINFO_$1) sopc2dts.build 27 | $(DTS.SOPC2DTS) --input $$(QSYS_SOPCINFO_$1) --output $$(DEVICE_TREE_SOURCE_$1) $$(DTS.SOPC2DTS_ARGS_$1) 2>&1 | tee logs/$$(notdir $$@).log 28 | sed -i 's/hps_0_arm_gic_0/intc/g' $$(DEVICE_TREE_SOURCE_$1) 29 | sed -i 's/h2f_user0_clock/cfg_h2f_usr0_clk/g' $$(DEVICE_TREE_SOURCE_$1) 30 | sed -i 's/h2f_user1_clock/h2f_usr1_clk/g' $$(DEVICE_TREE_SOURCE_$1) 31 | sed -i '/dts-v1/a \/include\/ "$$(DEVICE_TREE_INCLUDE_$1)"' $$(DEVICE_TREE_SOURCE_$1) 32 | sed -i '/dts-v1/a \/plugin\/\;' $$(DEVICE_TREE_SOURCE_$1) 33 | sed -i 's/\/dts-v1\/ \/plugin\/\;/\/dts-v1\/\;/' $$(DEVICE_TREE_SOURCE_$1) 34 | 35 | #HELP_TARGETS_$1 += $$(DEVICE_TREE_SOURCE_$1) 36 | #$$(DEVICE_TREE_SOURCE_$1).HELP := Generate a device tree for $1 37 | 38 | $$(DEVICE_TREE_BLOB_$1): $$(DEVICE_TREE_SOURCE_$1) devicetrees/$$(DEVICE_TREE_INCLUDE_$1) dtc.build 39 | $(DTS.DTC) -@ -I dts -O dtb -o $$(DEVICE_TREE_BLOB_$1) $$(DEVICE_TREE_SOURCE_$1) 40 | 41 | endef # build_dts_revisions 42 | 43 | $(foreach r, $(REVISION_LIST), $(eval $(call build_dts_revisions,$r))) 44 | 45 | -------------------------------------------------------------------------------- /mks/dtc.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | DTC_REPO_HASH := 0931cea3ba20d41013284c20b5a204dca002c058 5 | DTC_REPO := "http://git.kernel.org/pub/scm/utils/dtc/dtc.git" 6 | 7 | .PHONY: dtc.get 8 | dtc.get: downloads/dtc_$(DTC_REPO_HASH).tgz 9 | downloads/dtc_$(DTC_REPO_HASH).tgz: 10 | $(RM) dtc dtc_temp 11 | $(MKDIR) downloads 12 | git clone $(DTC_REPO) dtc_temp 13 | git -C dtc_temp checkout -b temp_v1.4.2 $(DTC_REPO_HASH) 14 | git -C dtc_temp archive --format=tar.gz --output ../downloads/dtc_$(DTC_REPO_HASH).tgz --prefix=dtc/ temp_v1.4.2 15 | $(RM) dtc_temp 16 | 17 | .PHONY: dtc.extract 18 | dtc.extract: $(call get_stamp_target,dtc.extract) 19 | $(call get_stamp_target,dtc.extract): downloads/dtc_$(DTC_REPO_HASH).tgz 20 | $(RM) dtc dtc_temp 21 | $(MKDIR) dtc 22 | $(TAR) -xvzf downloads/dtc_$(DTC_REPO_HASH).tgz --strip-components 1 -C dtc 23 | $(stamp_target) 24 | 25 | 26 | .PHONY: dtc.build 27 | dtc.build: $(call get_stamp_target,dtc.build) 28 | $(call get_stamp_target,dtc.build): $(call get_stamp_target,dtc.extract) 29 | $(MAKE) -C dtc 30 | $(stamp_target) 31 | 32 | -------------------------------------------------------------------------------- /mks/ip.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | SUP_COMPS_REPO_HASH := 533acace136065fc3f2dcbaaaee31fe4eda32e09 5 | SUP_COMPS_SOURCE_PACKAGE := "https://github.com/01org/supplemental-reset-components-for-qsys/tarball/$(SUP_COMPS_REPO_HASH)" 6 | 7 | PHONY: sup_comps.get 8 | sup_comps.get: downloads/sup_comps_$(SUP_COMPS_REPO_HASH).tgz 9 | downloads/sup_comps_$(SUP_COMPS_REPO_HASH).tgz: 10 | $(MKDIR) downloads 11 | wget -O $@ $(SUP_COMPS_SOURCE_PACKAGE) 12 | 13 | .PHONY: sup_comps.extract 14 | sup_comps.extract: supplemental-reset-components-for-qsys/reset_components.ipx 15 | supplemental-reset-components-for-qsys/reset_components.ipx: downloads/sup_comps_$(SUP_COMPS_REPO_HASH).tgz 16 | $(MKDIR) supplemental-reset-components-for-qsys 17 | $(TAR) -xvzf downloads/sup_comps_$(SUP_COMPS_REPO_HASH).tgz --strip-components 1 -C supplemental-reset-components-for-qsys 18 | 19 | define make_ipx_components 20 | 21 | $1/addon_components.ipx: 22 | @$(MKDIR) $1 23 | @$(ECHO) "Creating IPX file" 24 | @$(ECHO) "" > $1/addon_components.ipx 25 | @$(ECHO) " " >> $1/addon_components.ipx 26 | @$(ECHO) "" >> $1/addon_components.ipx 27 | 28 | $1/supplemental-reset-components-for-qsys.ipx: supplemental-reset-components-for-qsys/reset_components.ipx 29 | $(MKDIR) $1 30 | ip-make-ipx --source-directory=./supplemental-reset-components-for-qsys --output=$1/supplemental-reset-components-for-qsys.ipx 31 | 32 | endef 33 | 34 | $(foreach r,$(REVISION_LIST),$(eval $(call make_ipx_components,$r))) 35 | -------------------------------------------------------------------------------- /mks/preloader_uboot.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | ################################################ 5 | # Preloader 6 | 7 | QSYS_HPS_INST_NAME ?= hps_0 8 | 9 | PRELOADER_DISABLE_WATCHDOG ?= 1 10 | ifeq ($(PRELOADER_DISABLE_WATCHDOG),1) 11 | PRELOADER_EXTRA_ARGS += --set spl.boot.WATCHDOG_ENABLE false 12 | endif 13 | 14 | PRELOADER_FAT_SUPPORT ?= 1 15 | ifeq ($(PRELOADER_FAT_SUPPORT),1) 16 | PRELOADER_EXTRA_ARGS += --set spl.boot.FAT_SUPPORT true 17 | endif 18 | 19 | PRELOADER_EXTRA_ARGS += --set spl.boot.FAT_LOAD_PAYLOAD_NAME $1/u-boot.img 20 | 21 | define bsp_editor_create_revisions 22 | 23 | PRELOADER_DIR_$1 := $1/preloader 24 | 25 | HELP_TARGETS_$1 += $1.bsp_editor_gen 26 | $1.bsp_editor_gen.HELP := Generate BSP-Editor Files for $1 BSP 27 | 28 | .PHONY: $1.bsp_editor_gen 29 | $1.bsp_editor_gen: $$(PRELOADER_GEN_STAMP_$1) 30 | 31 | PRELOADER_EXTRA_ARGS_$1 += $(PRELOADER_EXTRA_ARGS) 32 | 33 | $$(PRELOADER_GEN_STAMP_$1): $$(PRELOADER_GEN_DEPS_$1) 34 | @$(MKDIR) $$(PRELOADER_DIR_$1) 35 | $(SBT.CREATE_SETTINGS) \ 36 | --type spl \ 37 | --bsp-dir $$(PRELOADER_DIR_$1) \ 38 | --preloader-settings-dir \ 39 | "$1/hps_isw_handoff/$(QSYS_BASE_NAME)_$(QSYS_HPS_INST_NAME)" \ 40 | --settings $$(PRELOADER_DIR_$1)/settings.bsp \ 41 | $$(PRELOADER_EXTRA_ARGS_$1) 42 | $$(stamp_target) 43 | 44 | endef # bsp_editor_create_revisions 45 | 46 | $(foreach r, $(REVISION_LIST), $(eval $(call bsp_editor_create_revisions,$r))) 47 | -------------------------------------------------------------------------------- /mks/qsys.mk: -------------------------------------------------------------------------------- 1 | ## Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | ################################################################################ 5 | # QSys Targets 6 | ############# 7 | 8 | # Under cygwin, ensure TMP env variable is not a cygwin style path 9 | # before calling ip-generate 10 | ifeq ($(IS_CYGWIN_HOST),1) 11 | ifneq ($(shell $(WHICH) cygpath 2>/dev/null),) 12 | SET_QSYS_GENERATE_ENV = TMP="$(shell cygpath -m "$(TMP)")" 13 | endif 14 | endif 15 | 16 | define create_qsys_targets 17 | 18 | HELP_TARGETS_$1 += $1.qsys_generate_qsys 19 | $1.qsys_generate_qsys.HELP := Create QSys for $1 revision 20 | 21 | .PHONY: $1.qsys_generate_qsys 22 | $1.qsys_generate_qsys: $(sort $$(QSYS_GEN_STAMP_$1)) 23 | 24 | $$(QSYS_GEN_STAMP_$1): $$(QSYS_GEN_DEPS_$1) 25 | $(RM) $$(QSYS_FILE_$1) 26 | $(MKDIR) $1 27 | qsys-script --cmd="source scripts/create_qsys_$1.tcl; build_qsys $1" 2>&1 | tee logs/$$(notdir $$@).log 28 | $$(stamp_target) 29 | 30 | HELP_TARGETS_$1 += $1.qsys_compile 31 | $1.qsys_compile.HELP := Generate Qsys System - $1 32 | 33 | .PHONY: $1.qsys_compile 34 | $1.qsys_compile: $$(QSYS_STAMP_$1) 35 | 36 | #so if qsys file changes, regenerate 37 | $$(QSYS_FILE_$1): $$(QSYS_GEN_STAMP_$1) 38 | 39 | $$(QSYS_STAMP_$1): $$(QSYS_FILE_$1) 40 | $(SET_QSYS_GENERATE_ENV) qsys-generate $$(QSYS_FILE_$1) --synthesis=VERILOG $(QSYS_GENERATE_ARGS) 2>&1 | tee logs/$$(notdir $$@).log 41 | $$(stamp_target) 42 | 43 | HELP_TARGETS_$1 += $1.qsys_edit 44 | $1.qsys_edit.HELP := Launch QSys GUI - $1 45 | 46 | .PHONY: $1.qsys_edit 47 | $1.qsys_edit: $$(QSYS_FILE_$1) 48 | qsys-edit $$(QSYS_FILE_$1) & 49 | 50 | $$(QSYS_SOPCINFO_$1) $1/$(QSYS_BASE_NAME)/synthesis/$(QSYS_BASE_NAME).qip: $$(QSYS_STAMP_$1) 51 | 52 | ############# 53 | # Target for pin assignments 54 | ############# 55 | 56 | $$(QSYS_PIN_ASSIGNMENTS_STAMP_$1): $$(QSYS_STAMP_$1) $$(CREATE_PROJECT_STAMP_$1) 57 | quartus_map $$(QUARTUS_QPF_$1) -c $1 58 | quartus_cdb --merge $$(QUARTUS_QPF_$1) -c $1 59 | $(MAKE) -j1 QSYS_ENABLE_PIN_ASSIGNMENTS_APPLY=1 $1.quartus_apply_tcl_pin_assignments 2>&1 | tee logs/$$(notdir $$@).log 60 | $$(stamp_target) 61 | 62 | ####### 63 | # we need to recursively call this makefile to 64 | # apply *_pin_assignments.tcl script because the 65 | # pin_assignment.tcl files may not exist yet 66 | # when makefile was originally called 67 | 68 | ifeq ($$(QSYS_ENABLE_PIN_ASSIGNMENTS_APPLY),1) 69 | 70 | QSYS_TCL_PIN_ASSIGNMENTS_$1 = $(wildcard $1/$(QSYS_BASE_NAME)/synthesis/submodules/*_pin_assignments.tcl) 71 | QSYS_TCL_PIN_ASSIGNMENTS_APPLY_TARGETS_$1 = $(patsubst %,$1_quartus_apply_tcl-%,$$(QSYS_TCL_PIN_ASSIGNMENTS_$1)) 72 | 73 | .PHONY: $1.quartus_apply_tcl_pin_assignments 74 | $1.quartus_apply_tcl_pin_assignments: $$(QSYS_TCL_PIN_ASSIGNMENTS_APPLY_TARGETS_$1) 75 | 76 | .PHONY: $$(QSYS_TCL_PIN_ASSIGNMENTS_APPLY_TARGETS_$1) 77 | $$(QSYS_TCL_PIN_ASSIGNMENTS_APPLY_TARGETS_$1): $1_quartus_apply_tcl-% : % 78 | @$(ECHO) "Applying $$<... to $(QUARTUS_QPF_$1)..." 79 | quartus_sh -t $(CURDIR)/$$< $(CURDIR)/$$(QUARTUS_QPF_$1) 2>&1 | tee logs/$$(notdir $$@).log 80 | 81 | endif # QUARTUS_ENABLE_PIN_ASSIGNMENTS_APPLY == 1 82 | ###### 83 | 84 | endef 85 | 86 | $(foreach r,$(REVISION_LIST),$(eval $(call create_qsys_targets,$r))) 87 | 88 | 89 | 90 | -------------------------------------------------------------------------------- /mks/quartus.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | ################################################################################ 5 | # Quartus Targets 6 | ############# 7 | 8 | define set_default_project_settings 9 | quartus_sh --no_banner --set -rev $1 PROJECT_OUTPUT_DIRECTORY=output_files $1/$1.qpf 2>&1 | tee -a logs/$$(notdir $$@).log 10 | quartus_sh --no_banner --set -rev $1 SMART_RECOMPILE=ON $1/$1.qpf 2>&1 | tee -a logs/$$(notdir $$@).log 11 | quartus_sh --no_banner --set -rev $1 TOP_LEVEL_ENTITY=$(TOP_LEVEL_ENTITY) $1/$1.qpf 2>&1 | tee -a logs/$$(notdir $$@).log 12 | quartus_sh --no_banner --set -rev $1 QIP_FILE=$(QSYS_BASE_NAME)/synthesis/$(QSYS_BASE_NAME).qip $1/$1.qpf 2>&1 | tee -a logs/$$(notdir $$@).log 13 | # quartus_sh --no_banner --set -rev $1 VERILOG_MACRO="$1=1" $1/$1.qpf 2>&1 | tee -a logs/$$(notdir $$@).log 14 | quartus_sh --no_banner --set -rev $1 SEARCH_PATH="../ip" $1/$1.qpf 2>&1 | tee -a logs/$$(notdir $$@).log 15 | endef 16 | 17 | define create_quartus_targets 18 | 19 | 20 | ############# 21 | # Create QuartusII Project 22 | ############# 23 | 24 | HELP_TARGETS_$1 += $1.create_project 25 | $1.create_project.HELP := Create Quartus Project for $1 26 | .PHONY: $1.create_project 27 | $1.create_project: $$(CREATE_PROJECT_STAMP_$1) 28 | 29 | $$(QUARTUS_QPF_$1): $$(CREATE_PROJECT_STAMP_$1) 30 | 31 | $$(CREATE_PROJECT_STAMP_$1): $$(CREATE_PROJECT_DEPS_$1) 32 | @$(RM) $1 33 | @$(MKDIR) $1 34 | quartus_sh --no_banner -t $$(SCRIPT_DIR)/create_project.tcl $1 -d $1 -c $1 2>&1 | tee logs/$$(notdir $$@).log 35 | quartus_sh --no_banner -t $$(SCRIPT_DIR)/create_revision.tcl $1/$1.qpf -new $1 2>&1 | tee -a logs/$$(notdir $$@).log 36 | quartus_sh --no_banner -t $$(SCRIPT_DIR)/project_run_script.tcl $1/$1.qpf -c $1 -script $(CURDIR)/$$< 2>&1 | tee -a logs/$$(notdir $$@).log 37 | $(call set_default_project_settings,$1) 38 | $(MAKE) $1/addon_components.ipx 39 | $$(stamp_target) 40 | 41 | $1/hps_isw_handoff: $$(QUARTUS_STAMP_$1) 42 | 43 | $1/$1.qsf: $$(CREATE_PROJECT_STAMP_$1) 44 | 45 | ############# 46 | # target for compilation 47 | ############# 48 | 49 | HELP_TARGETS_$1 += $1.quartus_compile 50 | $1.quartus_compile.HELP := Compile Quartus Project Revision $1 51 | 52 | .PHONY: $1.quartus_compile 53 | $1.quartus_compile: $$(QUARTUS_STAMP_$1) 54 | 55 | $$(QUARTUS_SOF_$1): $$(QUARTUS_STAMP_$1) 56 | 57 | $$(QUARTUS_JDI_$1): $$(QUARTUS_STAMP_$1) 58 | 59 | $$(QUARTUS_STAMP_$1): $$(QUARTUS_DEPS_$1) 60 | quartus_stp $$(QUARTUS_QPF_$1) -c $1 2>&1 | tee logs/$$(notdir $$@).log 61 | quartus_sh --flow compile $$(QUARTUS_QPF_$1) -c $1 2>&1 | tee -a logs/$$(notdir $$@).log 62 | $$(stamp_target) 63 | 64 | # 65 | # This converts the sof into compressed, unencrypted 66 | # raw binary format corresponding to MSEL value of 8 67 | # in the FPGAMGRREGS_STAT register. If you read the 68 | # the whole register, it should be 0x50. 69 | # 70 | # CVSoC DevBoard SW1 MSEL should be set to up,down,up,down,up,up 71 | # 72 | 73 | QUARTUS_CPF_ARGS = bitstream_compression=on 74 | 75 | $$(QUARTUS_RBF_$1): %.rbf: %.sof 76 | $(ECHO) $$(QUARTUS_RBF_$1) 77 | quartus_cpf -c -o bitstream_compression=on $$< $$@ 2>&1 | tee logs/$$(notdir $$@).log 78 | 79 | 80 | HELP_TARGETS_$1 += $1.quartus_edit 81 | $1.quartus_edit.HELP := Launch Quartus II GUI for $1 82 | 83 | .PHONY: $1.quartus_edit 84 | $1.quartus_edit: $$(CREATE_PROJECT_STAMP_$1) 85 | quartus $$(QUARTUS_QPF_$1) & 86 | 87 | endef 88 | 89 | $(foreach r,$(REVISION_LIST),$(eval $(call create_quartus_targets,$r))) 90 | 91 | 92 | 93 | ################################################################################ 94 | 95 | -------------------------------------------------------------------------------- /mks/sof_rbf_license.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | ################################################################################ 5 | 6 | 7 | define q_lic 8 | @$(ECHO) "(C) 2001-2016 Intel Corporation. All rights reserved." >> $$@ 9 | @$(ECHO) "Your use of Intel Corporation's design tools, logic functions and other" >> $$@ 10 | @$(ECHO) "software and tools, and its AMPP partner logic functions, and any output" >> $$@ 11 | @$(ECHO) "files any of the foregoing (including device programming or simulation" >> $$@ 12 | @$(ECHO) "files), and any associated documentation or information are expressly subject" >> $$@ 13 | @$(ECHO) "to the terms and conditions of the Intel Program License Subscription" >> $$@ 14 | @$(ECHO) "Agreement, Intel MegaCore Function License Agreement, or other applicable" >> $$@ 15 | @$(ECHO) "license agreement, including, without limitation, that your use is for the" >> $$@ 16 | @$(ECHO) "sole purpose of programming logic devices manufactured by Intel and sold by" >> $$@ 17 | @$(ECHO) "Intel or its authorized distributors. Please refer to the applicable" >> $$@ 18 | @$(ECHO) "agreement for further details." >> $$@ 19 | endef 20 | 21 | define gen_binary_license 22 | 23 | $$(QUARTUS_SOF_LIC_$1): $$(QUARTUS_STAMP_$1) 24 | @$(RM) $$(QUARTUS_SOF_LIC_$1) 25 | $(q_lic) $$(QUARTUS_SOF_LIC_$1) 26 | 27 | $$(QUARTUS_RBF_LIC_$1): $$(QUARTUS_STAMP_$1) 28 | @$(RM) $$(QUARTUS_RBF_LIC_$1) 29 | $(q_lic) $$(QUARTUS_RBF_LIC_$1) 30 | 31 | endef 32 | 33 | $(foreach r,$(REVISION_LIST),$(eval $(call gen_binary_license,$r))) 34 | -------------------------------------------------------------------------------- /mks/sopc2dts.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | SOPC2DTS_REPO_HASH := 33881de096d24194c7da36da1831cbbe140e3956 5 | SOPC2DTS_SOURCE_PACKAGE := "https://github.com/altera-opensource/sopc2dts/tarball/$(SOPC2DTS_REPO_HASH)" 6 | 7 | SOPC2DTS_PATCHES = $(sort $(wildcard patches/sopc2dts/*.patch)) 8 | 9 | .PHONY: sopc2dts.get 10 | sopc2dts.get: downloads/sopc2dts_$(SOPC2DTS_REPO_HASH).tgz 11 | downloads/sopc2dts_$(SOPC2DTS_REPO_HASH).tgz: 12 | $(MKDIR) downloads 13 | wget -O $@ $(SOPC2DTS_SOURCE_PACKAGE) 14 | 15 | .PHONY: sopc2dts.extract 16 | sopc2dts.extract: $(call get_stamp_target,sopc2dts.$(SOPC2DTS_REPO_HASH).extract) 17 | $(call get_stamp_target,sopc2dts.$(SOPC2DTS_REPO_HASH).extract): downloads/sopc2dts_$(SOPC2DTS_REPO_HASH).tgz $(SOPC2DTS_PATCHES) 18 | $(RM) sopc2dts 19 | $(MKDIR) sopc2dts 20 | $(TAR) -xvzf downloads/sopc2dts_$(SOPC2DTS_REPO_HASH).tgz --strip-components 1 -C sopc2dts 21 | $(stamp_target) 22 | 23 | linux.patch: $(foreach p,$(SOPC2DTS_PATCHES),$(call get_stamp_target,sopc2dts.$(SOPC2DTS_REPO_HASH).$(notdir $p))) 24 | define do_patch_sopc2dts 25 | $(call get_stamp_target,sopc2dts.$(SOPC2DTS_REPO_HASH).$(notdir $p)): $(call get_stamp_target,sopc2dts.$(SOPC2DTS_REPO_HASH).extract) 26 | patch -d sopc2dts -p1 < $1 2>&1 27 | $$(stamp_target) 28 | endef 29 | $(foreach p,$(SOPC2DTS_PATCHES),$(eval $(call do_patch_sopc2dts,$p))) 30 | 31 | .PHONY: sopc2dts.build 32 | sopc2dts.build: $(call get_stamp_target,sopc2dts.$(SOPC2DTS_REPO_HASH).sopc2dts.build) 33 | $(call get_stamp_target,sopc2dts.$(SOPC2DTS_REPO_HASH).sopc2dts.build): $(foreach p,$(SOPC2DTS_PATCHES),$(call get_stamp_target,sopc2dts.$(SOPC2DTS_REPO_HASH).$(notdir $p))) 34 | $(MAKE) -C sopc2dts 35 | $(stamp_target) 36 | -------------------------------------------------------------------------------- /patches/sopc2dts/0002-Use-target-path-instead-of-phandle.patch: -------------------------------------------------------------------------------- 1 | From 34fa7811efad7c7a16c39a9e2bcd2b633b5f2e5b Mon Sep 17 00:00:00 2001 2 | From: Dalon Westergreen 3 | Date: Tue, 9 Aug 2016 10:45:10 -0700 4 | Subject: [PATCH 2/2] Use target-path instead of phandle 5 | 6 | --- 7 | Sopc2DTS.java | 2 +- 8 | sopc2dts/generators/DTGenerator.java | 2 +- 9 | 2 files changed, 2 insertions(+), 2 deletions(-) 10 | 11 | diff --git a/Sopc2DTS.java b/Sopc2DTS.java 12 | index a120c35..57de307 100644 13 | --- a/Sopc2DTS.java 14 | +++ b/Sopc2DTS.java 15 | @@ -117,7 +117,7 @@ public class Sopc2DTS implements LogListener { 16 | vOptions.add(new CommandLineOption("no-timestamp", null, excludeTimeStamp, false, false, "Don't add a timestamp to generated files", null)); 17 | vOptions.add(new CommandLineOption("input", "i", inputFileName, true, true, "The sopcinfo file (optional in gui mode)", "sopcinfo file")); 18 | vOptions.add(new CommandLineOption("output", "o", outputFileName, true, false,"The output filename","filename")); 19 | - vOptions.add(new CommandLineOption("overlay-target",null, overlayTarget,true, false,"Target node for dt-overlay","node-label")); 20 | + vOptions.add(new CommandLineOption("overlay-target",null, overlayTarget,true, false,"Target PATH for dt-overlay","node-label")); 21 | vOptions.add(new CommandLineOption("firmware-name",null, firmwareName,true, false,"DTS overlay FPGA configuration RBF name, if not specified we assume external configuration","node-label")); 22 | vOptions.add(new CommandLineOption("pov", "p", pov, true, false,"The point of view to generate from. Defaults to the first cpu found", "component name")); 23 | vOptions.add(new CommandLineOption("pov-type", null, povType, true, false,"The point of view device type", "{cpu,pci,overlay}")); 24 | diff --git a/sopc2dts/generators/DTGenerator.java b/sopc2dts/generators/DTGenerator.java 25 | index 6564595..527ba33 100644 26 | --- a/sopc2dts/generators/DTGenerator.java 27 | +++ b/sopc2dts/generators/DTGenerator.java 28 | @@ -97,7 +97,7 @@ public abstract class DTGenerator extends AbstractSopcGenerator { 29 | } break; 30 | case OVERLAY: { 31 | DTNode fragmentNode = new DTNode("fragment@0"); 32 | - fragmentNode.addProperty(new DTProperty("target", new DTPropTargetVal(bi.getOverlayTarget()))); 33 | + fragmentNode.addProperty(new DTProperty("target-path", new DTPropTargetVal(bi.getOverlayTarget()))); 34 | sopcNode = new DTNode("__overlay__"); 35 | if(bi.getFirmwareName().equals("")) 36 | { 37 | -- 38 | 2.5.5 39 | 40 | -------------------------------------------------------------------------------- /patches/sopc2dts/0003-remove-since-we-moved-to-full-path-for-overlay-terge.patch: -------------------------------------------------------------------------------- 1 | From d3b1a3e0b97103f275c4d100c9d3c26e1062931b Mon Sep 17 00:00:00 2001 2 | From: Dalon Westergreen 3 | Date: Tue, 9 Aug 2016 17:06:34 -0700 4 | Subject: [PATCH 3/3] remove & since we moved to full path for overlay terget 5 | 6 | --- 7 | Sopc2DTS.java | 1 + 8 | sopc2dts/lib/devicetree/DTPropTargetVal.java | 2 +- 9 | 2 files changed, 2 insertions(+), 1 deletion(-) 10 | 11 | diff --git a/Sopc2DTS.java b/Sopc2DTS.java 12 | index 57de307..1766f29 100644 13 | --- a/Sopc2DTS.java 14 | +++ b/Sopc2DTS.java 15 | @@ -78,6 +78,7 @@ public class Sopc2DTS implements LogListener { 16 | protected static final String programName = "sopc2dts"; 17 | private static String programVersion = Package.getPackage("sopc2dts").getImplementationVersion();; 18 | private Vector vInfoFileNames = new Vector(); 19 | + private Vector vdtsiFileNames = new Vector(); 20 | 21 | /** 22 | * @param args 23 | diff --git a/sopc2dts/lib/devicetree/DTPropTargetVal.java b/sopc2dts/lib/devicetree/DTPropTargetVal.java 24 | index 4601f0a..b9584cc 100644 25 | --- a/sopc2dts/lib/devicetree/DTPropTargetVal.java 26 | +++ b/sopc2dts/lib/devicetree/DTPropTargetVal.java 27 | @@ -57,7 +57,7 @@ public class DTPropTargetVal extends DTPropVal { 28 | } 29 | @Override 30 | public String toString() { 31 | - return '&' + label; 32 | + return label; 33 | } 34 | 35 | } 36 | -- 37 | 2.5.5 38 | 39 | -------------------------------------------------------------------------------- /scripts/mmlink_setup.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | set project_file [ lindex $argv 0 ] 5 | set board_ip [ lindex $argv 1 ] 6 | set board_port [ lindex $argv 2 ] 7 | 8 | puts "Loading project $project_file." 9 | if { [ catch { set design_node [ design_load $project_file ] } ] } { 10 | global errorInfo 11 | puts "Failed to load $project_file. $errorInfo." 12 | exit 1 13 | } 14 | array set design_markers [ marker_get_info $design_node ] 15 | 16 | set existing_devices [ get_service_paths device ] 17 | 18 | puts "Connecting to remote device on $board_ip:$board_port." 19 | if { [ catch { set connection_node [ add_service tcp remote_system $board_ip $board_port ] } ] } { 20 | global errorInfo 21 | puts "Failed to connect to remote device. $errorInfo." 22 | } 23 | 24 | refresh_connections 25 | get_service_paths device 26 | if { [ catch { marker_get_info $connection_node } ] } { 27 | puts "System Console was unable to connect to $board_ip:$board_port successfully." 28 | exit 1 29 | } 30 | 31 | set new_devices {} 32 | foreach device [ get_service_paths device ] { 33 | if { [ lsearch $existing_devices $device ] < 0 } { 34 | set new_devices [ lappend $new_devices $device ] 35 | } 36 | } 37 | 38 | set at_least_one_device_matches_project 0 39 | puts "Found new devices:" 40 | foreach device $new_devices { 41 | puts "\t$device" 42 | array set device_markers [ marker_get_info $device ] 43 | puts "\t value of design_markers $design_markers(DESIGN_HASH)" 44 | puts "\t value of device_markers $device_markers(DESIGN_HASH)" 45 | if { $design_markers(DESIGN_HASH) == $device_markers(DESIGN_HASH) } { 46 | set at_least_one_device_matches_project 1 47 | } 48 | } 49 | if { !$at_least_one_device_matches_project } { 50 | puts "The project $project_file didn't match any of the newly discovered devices." 51 | exit 1 52 | } 53 | 54 | puts "Remote system ready." 55 | -------------------------------------------------------------------------------- /scripts/qsys_add_arduino_io.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | #HPS Modifications 5 | set_instance_parameter_value hps_0 {SPIM0_PinMuxing} {FPGA} 6 | set_instance_parameter_value hps_0 {SPIM0_Mode} {Full} 7 | set_instance_parameter_value hps_0 {UART1_PinMuxing} {FPGA} 8 | set_instance_parameter_value hps_0 {UART1_Mode} {Full} 9 | set_instance_parameter_value hps_0 {I2C3_PinMuxing} {FPGA} 10 | set_instance_parameter_value hps_0 {I2C3_Mode} {Full} 11 | 12 | #Add Components 13 | add_instance arduino_gpio altera_avalon_pio 14 | set_instance_parameter_value arduino_gpio {bitClearingEdgeCapReg} {1} 15 | set_instance_parameter_value arduino_gpio {bitModifyingOutReg} {1} 16 | set_instance_parameter_value arduino_gpio {captureEdge} {1} 17 | set_instance_parameter_value arduino_gpio {direction} {Bidir} 18 | set_instance_parameter_value arduino_gpio {edgeType} {RISING} 19 | set_instance_parameter_value arduino_gpio {generateIRQ} {1} 20 | set_instance_parameter_value arduino_gpio {irqType} {EDGE} 21 | set_instance_parameter_value arduino_gpio {resetValue} {0.0} 22 | set_instance_parameter_value arduino_gpio {simDoTestBenchWiring} {0} 23 | set_instance_parameter_value arduino_gpio {simDrivenValue} {0.0} 24 | set_instance_parameter_value arduino_gpio {width} {8} 25 | 26 | # connections and connection parameters 27 | # LW Bridge 28 | add_connection lw_mm_bridge.m0 arduino_gpio.s1 avalon 29 | set_connection_parameter_value lw_mm_bridge.m0/arduino_gpio.s1 arbitrationPriority {1} 30 | set_connection_parameter_value lw_mm_bridge.m0/arduino_gpio.s1 baseAddress {0x6000} 31 | set_connection_parameter_value lw_mm_bridge.m0/arduino_gpio.s1 defaultConnection {0} 32 | 33 | # Resets 34 | add_connection clk_0.clk_reset arduino_gpio.reset reset 35 | # Clocks 36 | add_connection clk_0.clk arduino_gpio.clk clock 37 | 38 | # IRQ 39 | add_connection hps_0.f2h_irq0 arduino_gpio.irq interrupt 40 | set_connection_parameter_value hps_0.f2h_irq0/arduino_gpio.irq irqNumber {11} 41 | 42 | # exported interfaces 43 | set_interface_property hps_0_spim0 EXPORT_OF hps_0.spim0 44 | add_interface hps_0_spim0_sclk_out clock source 45 | set_interface_property hps_0_spim0_sclk_out EXPORT_OF hps_0.spim0_sclk_out 46 | add_interface hps_0_uart1 conduit end 47 | set_interface_property hps_0_uart1 EXPORT_OF hps_0.uart1 48 | add_interface hps_0_i2c3_scl_in clock sink 49 | set_interface_property hps_0_i2c3_scl_in EXPORT_OF hps_0.i2c3_scl_in 50 | add_interface hps_0_i2c3_clk clock source 51 | set_interface_property hps_0_i2c3_clk EXPORT_OF hps_0.i2c3_clk 52 | add_interface hps_0_i2c3 conduit end 53 | set_interface_property hps_0_i2c3 EXPORT_OF hps_0.i2c3 54 | 55 | add_interface arduino_gpio conduit end 56 | set_interface_property arduino_gpio EXPORT_OF arduino_gpio.external_connection 57 | -------------------------------------------------------------------------------- /scripts/qsys_add_chipid_components.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | #Add Components 5 | add_instance altchip_id_0 altchip_id 6 | set_instance_parameter_value altchip_id_0 {ID_VALUE} {18446744073709551615} 7 | 8 | add_instance chip_id_read_mm_0 chip_id_read_mm 9 | 10 | # connections and connection parameters 11 | # LW Bridge 12 | add_connection lw_mm_bridge.m0 chip_id_read_mm_0.s0 13 | set_connection_parameter_value lw_mm_bridge.m0/chip_id_read_mm_0.s0 arbitrationPriority {1} 14 | set_connection_parameter_value lw_mm_bridge.m0/chip_id_read_mm_0.s0 baseAddress {0x7000} 15 | set_connection_parameter_value lw_mm_bridge.m0/chip_id_read_mm_0.s0 defaultConnection {0} 16 | 17 | # AvST 18 | add_connection altchip_id_0.output chip_id_read_mm_0.in0 avalon_streaming 19 | 20 | # Clocks 21 | add_connection clk_0.clk chip_id_read_mm_0.clock clock 22 | add_connection clk_0.clk altchip_id_0.clkin clock 23 | 24 | # Resets 25 | add_connection clk_0.clk_reset altchip_id_0.reset reset 26 | add_connection clk_0.clk_reset chip_id_read_mm_0.reset reset 27 | -------------------------------------------------------------------------------- /scripts/qsys_add_fft128_components.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | #Add Components 5 | add_instance fft_sub FFT_sub 6 | 7 | add_instance fft_ddr_bridge altera_address_span_extender 8 | set_instance_parameter_value fft_ddr_bridge {DATA_WIDTH} {128} 9 | set_instance_parameter_value fft_ddr_bridge {MASTER_ADDRESS_WIDTH} {32} 10 | set_instance_parameter_value fft_ddr_bridge {SLAVE_ADDRESS_WIDTH} {26} 11 | set_instance_parameter_value fft_ddr_bridge {BURSTCOUNT_WIDTH} {5} 12 | set_instance_parameter_value fft_ddr_bridge {SUB_WINDOW_COUNT} {1} 13 | set_instance_parameter_value fft_ddr_bridge {MASTER_ADDRESS_DEF} {2147483648} 14 | set_instance_parameter_value fft_ddr_bridge {MAX_PENDING_READS} {8} 15 | 16 | # MM Connectivity 17 | add_connection lw_mm_bridge.m0 fft_sub.s0 avalon 18 | set_connection_parameter_value lw_mm_bridge.m0/fft_sub.s0 arbitrationPriority {1} 19 | set_connection_parameter_value lw_mm_bridge.m0/fft_sub.s0 baseAddress {0x00080000} 20 | set_connection_parameter_value lw_mm_bridge.m0/fft_sub.s0 defaultConnection {0} 21 | 22 | add_connection fft_sub.to_ddr fft_ddr_bridge.windowed_slave avalon 23 | set_connection_parameter_value fft_sub.to_ddr/fft_ddr_bridge.windowed_slave arbitrationPriority {1} 24 | set_connection_parameter_value fft_sub.to_ddr/fft_ddr_bridge.windowed_slave baseAddress {0x0000} 25 | set_connection_parameter_value fft_sub.to_ddr/fft_ddr_bridge.windowed_slave defaultConnection {0} 26 | 27 | add_connection fft_ddr_bridge.expanded_master axi_bridge_for_acp_128_0.s0 avalon 28 | set_connection_parameter_value fft_ddr_bridge.expanded_master/axi_bridge_for_acp_128_0.s0 arbitrationPriority {1} 29 | set_connection_parameter_value fft_ddr_bridge.expanded_master/axi_bridge_for_acp_128_0.s0 baseAddress {0x0000} 30 | set_connection_parameter_value fft_ddr_bridge.expanded_master/axi_bridge_for_acp_128_0.s0 defaultConnection {0} 31 | 32 | add_connection lw_mm_bridge.m0 fft_ddr_bridge.cntl 33 | set_connection_parameter_value lw_mm_bridge.m0/fft_ddr_bridge.cntl arbitrationPriority {1} 34 | set_connection_parameter_value lw_mm_bridge.m0/fft_ddr_bridge.cntl baseAddress {0x00100000} 35 | set_connection_parameter_value lw_mm_bridge.m0/fft_ddr_bridge.cntl defaultConnection {0} 36 | 37 | # Interrupts 38 | add_connection hps_0.f2h_irq0 fft_sub.sgdma_from_fft_csr_irq interrupt 39 | set_connection_parameter_value hps_0.f2h_irq0/fft_sub.sgdma_from_fft_csr_irq irqNumber {3} 40 | 41 | add_connection hps_0.f2h_irq0 fft_sub.sgdma_to_fft_csr_irq interrupt 42 | set_connection_parameter_value hps_0.f2h_irq0/fft_sub.sgdma_to_fft_csr_irq irqNumber {4} 43 | 44 | add_connection hps_0.f2h_irq0 fft_sub.sgdma_from_ram_csr_irq interrupt 45 | set_connection_parameter_value hps_0.f2h_irq0/fft_sub.sgdma_from_ram_csr_irq irqNumber {5} 46 | 47 | # Clocks 48 | add_connection hps_0.h2f_user0_clock fft_ddr_bridge.clock clock 49 | add_connection hps_0.h2f_user0_clock fft_sub.clk clock 50 | 51 | # Resets 52 | add_connection clk_0.clk_reset fft_sub.reset reset 53 | add_connection clk_0.clk_reset fft_ddr_bridge.reset reset 54 | -------------------------------------------------------------------------------- /scripts/qsys_add_hdmi_i2c.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | # exported interfaces 5 | add_interface hps_0_i2c2 conduit end 6 | set_interface_property hps_0_i2c2 EXPORT_OF hps_0.i2c2 7 | add_interface hps_0_i2c2_clk clock source 8 | set_interface_property hps_0_i2c2_clk EXPORT_OF hps_0.i2c2_clk 9 | add_interface hps_0_i2c2_scl_in clock sink 10 | set_interface_property hps_0_i2c2_scl_in EXPORT_OF hps_0.i2c2_scl_in 11 | -------------------------------------------------------------------------------- /scripts/qsys_add_header_gpios.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | add_instance gpio_0_a altera_avalon_pio 5 | set_instance_parameter_value gpio_0_a {bitClearingEdgeCapReg} {1} 6 | set_instance_parameter_value gpio_0_a {bitModifyingOutReg} {1} 7 | set_instance_parameter_value gpio_0_a {captureEdge} {1} 8 | set_instance_parameter_value gpio_0_a {direction} {Bidir} 9 | set_instance_parameter_value gpio_0_a {edgeType} {RISING} 10 | set_instance_parameter_value gpio_0_a {generateIRQ} {0} 11 | set_instance_parameter_value gpio_0_a {irqType} {EDGE} 12 | set_instance_parameter_value gpio_0_a {resetValue} {0.0} 13 | set_instance_parameter_value gpio_0_a {simDoTestBenchWiring} {0} 14 | set_instance_parameter_value gpio_0_a {simDrivenValue} {0.0} 15 | set_instance_parameter_value gpio_0_a {width} {18} 16 | 17 | add_instance gpio_0_b altera_avalon_pio 18 | set_instance_parameter_value gpio_0_b {bitClearingEdgeCapReg} {1} 19 | set_instance_parameter_value gpio_0_b {bitModifyingOutReg} {1} 20 | set_instance_parameter_value gpio_0_b {captureEdge} {1} 21 | set_instance_parameter_value gpio_0_b {direction} {Bidir} 22 | set_instance_parameter_value gpio_0_b {edgeType} {RISING} 23 | set_instance_parameter_value gpio_0_b {generateIRQ} {0} 24 | set_instance_parameter_value gpio_0_b {irqType} {EDGE} 25 | set_instance_parameter_value gpio_0_b {resetValue} {0.0} 26 | set_instance_parameter_value gpio_0_b {simDoTestBenchWiring} {0} 27 | set_instance_parameter_value gpio_0_b {simDrivenValue} {0.0} 28 | set_instance_parameter_value gpio_0_b {width} {18} 29 | 30 | add_instance gpio_1_b altera_avalon_pio 31 | set_instance_parameter_value gpio_1_b {bitClearingEdgeCapReg} {1} 32 | set_instance_parameter_value gpio_1_b {bitModifyingOutReg} {1} 33 | set_instance_parameter_value gpio_1_b {captureEdge} {1} 34 | set_instance_parameter_value gpio_1_b {direction} {Bidir} 35 | set_instance_parameter_value gpio_1_b {edgeType} {RISING} 36 | set_instance_parameter_value gpio_1_b {generateIRQ} {0} 37 | set_instance_parameter_value gpio_1_b {irqType} {EDGE} 38 | set_instance_parameter_value gpio_1_b {resetValue} {0.0} 39 | set_instance_parameter_value gpio_1_b {simDoTestBenchWiring} {0} 40 | set_instance_parameter_value gpio_1_b {simDrivenValue} {0.0} 41 | set_instance_parameter_value gpio_1_b {width} {18} 42 | 43 | add_instance gpio_1_a altera_avalon_pio 44 | set_instance_parameter_value gpio_1_a {bitClearingEdgeCapReg} {1} 45 | set_instance_parameter_value gpio_1_a {bitModifyingOutReg} {1} 46 | set_instance_parameter_value gpio_1_a {captureEdge} {1} 47 | set_instance_parameter_value gpio_1_a {direction} {Bidir} 48 | set_instance_parameter_value gpio_1_a {edgeType} {RISING} 49 | set_instance_parameter_value gpio_1_a {generateIRQ} {0} 50 | set_instance_parameter_value gpio_1_a {irqType} {EDGE} 51 | set_instance_parameter_value gpio_1_a {resetValue} {0.0} 52 | set_instance_parameter_value gpio_1_a {simDoTestBenchWiring} {0} 53 | set_instance_parameter_value gpio_1_a {simDrivenValue} {0.0} 54 | set_instance_parameter_value gpio_1_a {width} {18} 55 | 56 | # Clocks 57 | add_connection clk_0.clk gpio_0_a.clk 58 | add_connection clk_0.clk gpio_0_b.clk 59 | add_connection clk_0.clk gpio_1_a.clk 60 | add_connection clk_0.clk gpio_1_b.clk 61 | 62 | # resets 63 | add_connection clk_0.clk_reset gpio_0_a.reset 64 | add_connection clk_0.clk_reset gpio_0_b.reset 65 | add_connection clk_0.clk_reset gpio_1_a.reset 66 | add_connection clk_0.clk_reset gpio_1_b.reset 67 | 68 | # mm connections 69 | add_connection lw_mm_bridge.m0 gpio_0_a.s1 70 | set_connection_parameter_value lw_mm_bridge.m0/gpio_0_a.s1 arbitrationPriority {1} 71 | set_connection_parameter_value lw_mm_bridge.m0/gpio_0_a.s1 baseAddress {0x00010000} 72 | set_connection_parameter_value lw_mm_bridge.m0/gpio_0_a.s1 defaultConnection {0} 73 | 74 | add_connection lw_mm_bridge.m0 gpio_0_b.s1 75 | set_connection_parameter_value lw_mm_bridge.m0/gpio_0_b.s1 arbitrationPriority {1} 76 | set_connection_parameter_value lw_mm_bridge.m0/gpio_0_b.s1 baseAddress {0x00011000} 77 | set_connection_parameter_value lw_mm_bridge.m0/gpio_0_b.s1 defaultConnection {0} 78 | 79 | add_connection lw_mm_bridge.m0 gpio_1_a.s1 80 | set_connection_parameter_value lw_mm_bridge.m0/gpio_1_a.s1 arbitrationPriority {1} 81 | set_connection_parameter_value lw_mm_bridge.m0/gpio_1_a.s1 baseAddress {0x00012000} 82 | set_connection_parameter_value lw_mm_bridge.m0/gpio_1_a.s1 defaultConnection {0} 83 | 84 | add_connection lw_mm_bridge.m0 gpio_1_b.s1 85 | set_connection_parameter_value lw_mm_bridge.m0/gpio_1_b.s1 arbitrationPriority {1} 86 | set_connection_parameter_value lw_mm_bridge.m0/gpio_1_b.s1 baseAddress {0x00013000} 87 | set_connection_parameter_value lw_mm_bridge.m0/gpio_1_b.s1 defaultConnection {0} 88 | 89 | # Exports 90 | add_interface gpio_0_a conduit end 91 | set_interface_property gpio_0_a EXPORT_OF gpio_0_a.external_connection 92 | add_interface gpio_0_b conduit end 93 | set_interface_property gpio_0_b EXPORT_OF gpio_0_b.external_connection 94 | add_interface gpio_1_a conduit end 95 | set_interface_property gpio_1_a EXPORT_OF gpio_1_a.external_connection 96 | add_interface gpio_1_b conduit end 97 | set_interface_property gpio_1_b EXPORT_OF gpio_1_b.external_connection 98 | -------------------------------------------------------------------------------- /scripts/qsys_add_pio_components.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | #Add Components 5 | add_instance led_pio altera_avalon_pio 6 | set_instance_parameter_value led_pio {bitClearingEdgeCapReg} {0} 7 | set_instance_parameter_value led_pio {bitModifyingOutReg} {0} 8 | set_instance_parameter_value led_pio {captureEdge} {0} 9 | set_instance_parameter_value led_pio {direction} {Output} 10 | set_instance_parameter_value led_pio {edgeType} {RISING} 11 | set_instance_parameter_value led_pio {generateIRQ} {0} 12 | set_instance_parameter_value led_pio {irqType} {LEVEL} 13 | set_instance_parameter_value led_pio {resetValue} {0.0} 14 | set_instance_parameter_value led_pio {simDoTestBenchWiring} {0} 15 | set_instance_parameter_value led_pio {simDrivenValue} {0.0} 16 | set_instance_parameter_value led_pio {width} {8} 17 | 18 | add_instance dipsw_pio altera_avalon_pio 19 | set_instance_parameter_value dipsw_pio {bitClearingEdgeCapReg} {1} 20 | set_instance_parameter_value dipsw_pio {bitModifyingOutReg} {0} 21 | set_instance_parameter_value dipsw_pio {captureEdge} {1} 22 | set_instance_parameter_value dipsw_pio {direction} {Input} 23 | set_instance_parameter_value dipsw_pio {edgeType} {ANY} 24 | set_instance_parameter_value dipsw_pio {generateIRQ} {1} 25 | set_instance_parameter_value dipsw_pio {irqType} {EDGE} 26 | set_instance_parameter_value dipsw_pio {resetValue} {0.0} 27 | set_instance_parameter_value dipsw_pio {simDoTestBenchWiring} {0} 28 | set_instance_parameter_value dipsw_pio {simDrivenValue} {0.0} 29 | set_instance_parameter_value dipsw_pio {width} {4} 30 | 31 | add_instance button_pio altera_avalon_pio 32 | set_instance_parameter_value button_pio {bitClearingEdgeCapReg} {1} 33 | set_instance_parameter_value button_pio {bitModifyingOutReg} {0} 34 | set_instance_parameter_value button_pio {captureEdge} {1} 35 | set_instance_parameter_value button_pio {direction} {Input} 36 | set_instance_parameter_value button_pio {edgeType} {FALLING} 37 | set_instance_parameter_value button_pio {generateIRQ} {1} 38 | set_instance_parameter_value button_pio {irqType} {EDGE} 39 | set_instance_parameter_value button_pio {resetValue} {0.0} 40 | set_instance_parameter_value button_pio {simDoTestBenchWiring} {0} 41 | set_instance_parameter_value button_pio {simDrivenValue} {0.0} 42 | set_instance_parameter_value button_pio {width} {2} 43 | 44 | # connections and connection parameters 45 | # LW Bridge 46 | add_connection lw_mm_bridge.m0 led_pio.s1 avalon 47 | set_connection_parameter_value lw_mm_bridge.m0/led_pio.s1 arbitrationPriority {1} 48 | set_connection_parameter_value lw_mm_bridge.m0/led_pio.s1 baseAddress {0x3000} 49 | set_connection_parameter_value lw_mm_bridge.m0/led_pio.s1 defaultConnection {0} 50 | 51 | add_connection lw_mm_bridge.m0 dipsw_pio.s1 avalon 52 | set_connection_parameter_value lw_mm_bridge.m0/dipsw_pio.s1 arbitrationPriority {1} 53 | set_connection_parameter_value lw_mm_bridge.m0/dipsw_pio.s1 baseAddress {0x4000} 54 | set_connection_parameter_value lw_mm_bridge.m0/dipsw_pio.s1 defaultConnection {0} 55 | 56 | add_connection lw_mm_bridge.m0 button_pio.s1 avalon 57 | set_connection_parameter_value lw_mm_bridge.m0/button_pio.s1 arbitrationPriority {1} 58 | set_connection_parameter_value lw_mm_bridge.m0/button_pio.s1 baseAddress {0x5000} 59 | set_connection_parameter_value lw_mm_bridge.m0/button_pio.s1 defaultConnection {0} 60 | 61 | # IRQ 62 | add_connection hps_0.f2h_irq0 dipsw_pio.irq interrupt 63 | set_connection_parameter_value hps_0.f2h_irq0/dipsw_pio.irq irqNumber {1} 64 | add_connection hps_0.f2h_irq0 button_pio.irq interrupt 65 | set_connection_parameter_value hps_0.f2h_irq0/button_pio.irq irqNumber {2} 66 | 67 | # Clocks 68 | add_connection clk_0.clk led_pio.clk clock 69 | add_connection clk_0.clk dipsw_pio.clk clock 70 | add_connection clk_0.clk button_pio.clk clock 71 | 72 | # Resets 73 | add_connection clk_0.clk_reset button_pio.reset reset 74 | add_connection clk_0.clk_reset dipsw_pio.reset reset 75 | add_connection clk_0.clk_reset led_pio.reset reset 76 | 77 | # exported interfaces 78 | add_interface led_pio conduit end 79 | set_interface_property led_pio EXPORT_OF led_pio.external_connection 80 | add_interface dipsw_pio conduit end 81 | set_interface_property dipsw_pio EXPORT_OF dipsw_pio.external_connection 82 | add_interface button_pio conduit end 83 | set_interface_property button_pio EXPORT_OF button_pio.external_connection 84 | -------------------------------------------------------------------------------- /scripts/release.sh: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | #!/bin/bash 5 | 6 | # OLD STAMP STAMP=$(date -u +"%m-%d-%y_%H.%M.%S") 7 | STAMP=$(date -u +"%Y%m%d_%H.%M.%S") 8 | STAMP_SHORT=$(date -u +"%Y%m%d") 9 | QUART_VER=$(head -1 $QUARTUS_ROOTDIR/version.txt) 10 | 11 | # tag master 12 | git tag -s -a RELEASE-$STAMP -m "Release Build:$STAMP QUARTUS:$QUART_VER" 13 | 14 | git checkout --orphan temp-RELEASE-BUILD-$STAMP 15 | git rm -rf --cached . 16 | 17 | for i in de10-nano-fft de10-nano-base de10-nano-mandelbrot; do 18 | git add $i/hps_isw_handoff/* 19 | git add $i/preloader/* 20 | git add $i/output_files/*.rbf 21 | git add $i/output_files/*.sof 22 | git add $i/*.qpf 23 | git add $i/*.qsf 24 | git add $i/*.qsys 25 | git add $i/*.sopcinfo 26 | git add $i/*.ipx 27 | done 28 | 29 | git add LICENSE 30 | git add README.md 31 | git add Makefile 32 | 33 | git add devicetrees/* 34 | git add mks/* 35 | git add scripts/* 36 | git add utils/* 37 | 38 | git add ip/* 39 | git add hdl_src/* 40 | git add patches/sopc2dts/* 41 | 42 | 43 | git clean -fd 44 | 45 | find ./ > $STAMP.filelist 46 | sed -i '/^\.\/\.git/d' $STAMP.filelist 47 | sed -i '/^\.\/$/d' $STAMP.filelist 48 | 49 | git add $STAMP.filelist 50 | git commit -a -s -m "Build:$STAMP QUARTUS:$QUART_VER" 51 | 52 | git tag -a tgz-RELEASE-BUILD-$STAMP -m "Build:$STAMP QUARTUS:$QUART_VER" 53 | git archive --format=tar.gz --output=de10-nano-build_$STAMP_SHORT.tgz tgz-RELEASE-BUILD-$STAMP 54 | -------------------------------------------------------------------------------- /scripts/sign.sh: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | #!/bin/bash 5 | 6 | STAMP_SHORT=$(date -u +"%Y%m%d") 7 | SIGNFILE=/tools/signfile-lin-x64-3.2.471/SignFile 8 | 9 | $SIGNFILE -vv -wf 0 -c DE10-Nano -u amr/dwesterg -p - -s cl \ 10 | -cf de10-nano-build_$STAMP_SHORT.tgz.sig \ 11 | de10-nano-build_$STAMP_SHORT.tgz 12 | 13 | openssl pkcs7 -print_certs -inform der \ 14 | -in de10-nano-build_$STAMP_SHORT.tgz.sig \ 15 | > de10-nano-build_$STAMP_SHORT.tgz.pem 16 | 17 | openssl x509 \ 18 | -in de10-nano-build_$STAMP_SHORT.tgz.pem \ 19 | -serial -noout 20 | 21 | openssl smime -verify \ 22 | -in de10-nano-build_$STAMP_SHORT.tgz.sig \ 23 | -inform der \ 24 | -content de10-nano-build_$STAMP_SHORT.tgz \ 25 | -noverify de10-nano-build_$STAMP_SHORT.tgz.pem > /dev/null 26 | -------------------------------------------------------------------------------- /utils/create_project.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require cmdline 5 | 6 | load_package project 7 | 8 | set tlist "c.arg" 9 | lappend tlist "#_unassigned_#" 10 | lappend tlist "Revision name" 11 | lappend function_opts $tlist 12 | 13 | set tlist "d.arg" 14 | lappend tlist "#_unassigned_#" 15 | lappend tlist "Directory" 16 | lappend function_opts $tlist 17 | 18 | if { [llength $::quartus(args)] == 0 } { 19 | post_message -type error "Expected arguments are -base -new " 20 | qexit -error 21 | } 22 | 23 | set project_name [lindex $::quartus(args) 0] 24 | set newargs [lreplace $::quartus(args) 0 0] 25 | array set optshash [cmdline::getFunctionOptions newargs $function_opts] 26 | 27 | set rev_name $optshash(c) 28 | if {$rev_name != "#_unassigned_#"} { 29 | post_message -type info "Revision name is $rev_name" 30 | } else { 31 | post_message -type error "Revision not set" 32 | qexit -error 33 | } 34 | 35 | set dir $optshash(d) 36 | if {$dir != "#_unassigned_#"} { 37 | set project_name "$dir/$project_name" 38 | } 39 | 40 | if { [project_exists $project_name] } { 41 | post_message -type error "Project: $project_name already exists" 42 | } else { 43 | post_message -type info "Creating Project: $project_name" 44 | project_new -revision $rev_name $project_name 45 | } 46 | 47 | if [is_project_open] { 48 | project_close 49 | 50 | } else { 51 | post_message -type error "Cannot create project $project_name" 52 | qexit -error 53 | } 54 | -------------------------------------------------------------------------------- /utils/create_revision.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | # BEGIN MAIN ---------------------------------------------------------------- 5 | 6 | package require cmdline 7 | 8 | load_package project 9 | 10 | set tlist "base.arg" 11 | lappend tlist "#_unassigned_#" 12 | lappend tlist "Revision on which to base the creation of the new revision" 13 | lappend function_opts $tlist 14 | 15 | set tlist "new.arg" 16 | lappend tlist "#_unassigned_#" 17 | lappend tlist "new revision name" 18 | 19 | lappend function_opts $tlist 20 | 21 | if { [llength $::quartus(args)] == 0 } { 22 | post_message -type error "Expected arguments are -base -new " 23 | qexit -error 24 | } 25 | 26 | set project_name [lindex $::quartus(args) 0] 27 | set newargs [lreplace $::quartus(args) 0 0] 28 | array set optshash [cmdline::getFunctionOptions newargs $function_opts] 29 | 30 | set base_name $optshash(base) 31 | if {$base_name != "#_unassigned_#"} { 32 | post_message -type info "Base Revision name is $base_name" 33 | } else { 34 | post_message -type info "Base revision not set, creating new revision" 35 | # qexit -error 36 | } 37 | 38 | if {$optshash(new) != "#_unassigned_#"} { 39 | set new_name $optshash(new) 40 | post_message -type info "New Revision name is $new_name" 41 | } else { 42 | post_message -type error "New revision must be set!" 43 | qexit -error 44 | } 45 | 46 | 47 | if { ![project_exists $project_name] } { 48 | post_message -type error "Project: $project_name does not exist" 49 | } else { 50 | post_message -type info "Opening Project: $project_name" 51 | project_open $project_name -current_revision -force 52 | } 53 | 54 | set revision_exists 0 55 | 56 | if [is_project_open] { 57 | foreach revision [get_project_revisions] { 58 | if { [string equal "$new_name" "$revision"] } { 59 | post_message -type warning "Revision $new_name already exists" 60 | #qexit 61 | #delete_revision $new_name 62 | set revision_exists 1 63 | } 64 | } 65 | if { $revision_exists} { 66 | set_current_revision -force $new_name 67 | } else { 68 | if {$base_name == "#_unassigned_#"} { 69 | create_revision -set_current $new_name 70 | } else { 71 | create_revision -based_on $base_name -set_current $new_name 72 | } 73 | } 74 | project_close 75 | 76 | } else { 77 | post_message -type error "Cannot open project $project_name" 78 | qexit -error 79 | } 80 | -------------------------------------------------------------------------------- /utils/extract_pin_assignments.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require cmdline 5 | 6 | load_package project 7 | 8 | set tlist "c.arg" 9 | lappend tlist "#_unassigned_#" 10 | lappend tlist "Revision to extract from" 11 | lappend function_opts $tlist 12 | 13 | set tlist "output.arg" 14 | lappend tlist "#_unassigned_#" 15 | lappend tlist "Output filename" 16 | lappend function_opts $tlist 17 | 18 | if { [llength $::quartus(args)] == 0 } { 19 | post_message -type error "Expected arguments are -c -output " 20 | qexit -error 21 | } 22 | 23 | set project_name [lindex $::quartus(args) 0] 24 | set newargs [lreplace $::quartus(args) 0 0] 25 | array set optshash [cmdline::getFunctionOptions newargs $function_opts] 26 | 27 | set rev_name $optshash(c) 28 | if {$rev_name != "#_unassigned_#"} { 29 | post_message -type info "Revision name is $rev_name" 30 | } else { 31 | post_message -type error "Revision not set" 32 | qexit -error 33 | } 34 | 35 | if {$optshash(output) != "#_unassigned_#"} { 36 | set output_name $optshash(output) 37 | post_message -type info "New Revision name is $output_name" 38 | } else { 39 | post_message -type error "Output filename not set" 40 | qexit -error 41 | } 42 | 43 | if { ![project_exists $project_name] } { 44 | post_message -type error "Project: $project_name does not exist" 45 | } else { 46 | post_message -type info "Opening Project: $project_name" 47 | project_open $project_name -force 48 | } 49 | 50 | if [is_project_open] { 51 | set rev_match 0 52 | foreach revision [get_project_revisions] { 53 | if { "$rev_name" == "$revision" } { 54 | set rev_match 1 55 | } 56 | } 57 | 58 | if { $rev_match } { 59 | set filename $output_name 60 | if [file exists $filename] { 61 | file rename -force $filename $filename.bac 62 | } 63 | set f [open $filename w] 64 | puts -nonewline $f "######################################\n" 65 | puts -nonewline $f "# Automatically Created Pin Assignment\n" 66 | puts -nonewline $f "# \t\tPin Assignment\n" 67 | puts -nonewline $f "######################################\n\n" 68 | foreach_in_collection assignment [get_all_assignments -name LOCATION -type instance] { 69 | puts -nonewline $f "set_location_assignment " 70 | puts -nonewline $f "[get_assignment_info $assignment -value] " 71 | puts -nonewline $f "-to [get_assignment_info $assignment -to] " 72 | puts -nonewline $f "-tag __pin_assignment_script" 73 | puts -nonewline $f "\n" 74 | } 75 | 76 | puts -nonewline $f "\n\n" 77 | puts -nonewline $f "# \t\tIO Standard Assignment\n" 78 | foreach_in_collection assignment [get_all_assignments -name IO_STANDARD -type instance] { 79 | puts -nonewline $f "set_instance_assignment " 80 | puts -nonewline $f "-name [get_assignment_info $assignment -name] " 81 | puts -nonewline $f "\"[get_assignment_info $assignment -value]\" " 82 | puts -nonewline $f "-to [get_assignment_info $assignment -to] " 83 | puts -nonewline $f "-tag __pin_assignment_script" 84 | puts -nonewline $f "\n" 85 | } 86 | puts -nonewline $f "\n" 87 | close $f 88 | 89 | } else { 90 | post_message -type error "Project: $project_name does not have revision $rev_name" 91 | } 92 | 93 | project_close 94 | 95 | } else { 96 | post_message -type error "Cannot open project $project_name" 97 | qexit -error 98 | } 99 | 100 | 101 | -------------------------------------------------------------------------------- /utils/project_remove_tag.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require cmdline 5 | 6 | load_package project 7 | 8 | set tlist "c.arg" 9 | lappend tlist "#_unassigned_#" 10 | lappend tlist "Revision name" 11 | lappend function_opts $tlist 12 | 13 | set tlist "tag.arg" 14 | lappend tlist "#_unassigned_#" 15 | lappend tlist "tag name" 16 | lappend function_opts $tlist 17 | 18 | if { [llength $::quartus(args)] == 0 } { 19 | post_message -type error "Expected arguments are -base -new " 20 | qexit -error 21 | } 22 | 23 | set project_name [lindex $::quartus(args) 0] 24 | set newargs [lreplace $::quartus(args) 0 0] 25 | array set optshash [cmdline::getFunctionOptions newargs $function_opts] 26 | 27 | set rev_name $optshash(c) 28 | if {$rev_name != "#_unassigned_#"} { 29 | post_message -type info "Revision name is $rev_name" 30 | } else { 31 | post_message -type error "Revision not set" 32 | qexit -error 33 | } 34 | 35 | set tag_name $optshash(tag) 36 | if { $tag_name == "#_unassigned_#"} { 37 | post_message -type error "Tag Name not specified" 38 | qexit -error 39 | } 40 | 41 | if { ![project_exists $project_name] } { 42 | post_message -type error "Project: $project_name doesn't exists" 43 | } else { 44 | post_message -type info "Creating Project: $project_name" 45 | project_open $project_name -current_revision 46 | } 47 | 48 | if [is_project_open] { 49 | set rev_match 0 50 | foreach revision [get_project_revisions] { 51 | if { "$rev_name" == "$revision" } { 52 | set rev_match 1 53 | } 54 | } 55 | if { $rev_match } { 56 | remove_all_instance_assignments -name * -tag $tag_name 57 | } else { 58 | post_message -type error "Revision $rev_name doesn't exist" 59 | qexit -error 60 | } 61 | 62 | project_close 63 | 64 | } else { 65 | post_message -type error "Cannot open project $project_name" 66 | qexit -error 67 | } 68 | -------------------------------------------------------------------------------- /utils/project_run_script.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Intel Corporation 2 | # SPDX-License-Identifier: MIT 3 | 4 | package require cmdline 5 | 6 | load_package project 7 | 8 | set tlist "c.arg" 9 | lappend tlist "#_unassigned_#" 10 | lappend tlist "Revision name" 11 | lappend function_opts $tlist 12 | 13 | set tlist "script.arg" 14 | lappend tlist "#_unassigned_#" 15 | lappend tlist "Script name" 16 | lappend function_opts $tlist 17 | 18 | if { [llength $::quartus(args)] == 0 } { 19 | post_message -type error "Expected arguments are -base -new " 20 | qexit -error 21 | } 22 | 23 | set project_name [lindex $::quartus(args) 0] 24 | set newargs [lreplace $::quartus(args) 0 0] 25 | array set optshash [cmdline::getFunctionOptions newargs $function_opts] 26 | 27 | set rev_name $optshash(c) 28 | if {$rev_name != "#_unassigned_#"} { 29 | post_message -type info "Revision name is $rev_name" 30 | } else { 31 | post_message -type error "Revision not set" 32 | qexit -error 33 | } 34 | 35 | set script_file $optshash(script) 36 | if { $script_file == "#_unassigned_#"} { 37 | post_message -type error "Script file not specified" 38 | qexit -error 39 | } 40 | 41 | if { ![project_exists $project_name] } { 42 | post_message -type error "Project: $project_name doesn't exists" 43 | } else { 44 | post_message -type info "Opening Project: $project_name" 45 | project_open $project_name -current_revision 46 | } 47 | 48 | if [is_project_open] { 49 | set rev_match 0 50 | foreach revision [get_project_revisions] { 51 | if { "$rev_name" == "$revision" } { 52 | set rev_match 1 53 | } 54 | } 55 | if { $rev_match } { 56 | set_current_revision $rev_name 57 | if [file exists $script_file] { 58 | source $script_file 59 | } else { 60 | post_message -type error "invalid script" 61 | qexit -error 62 | } 63 | } else { 64 | post_message -type error "Revision $rev_name doesn't exist" 65 | qexit -error 66 | } 67 | 68 | project_close 69 | 70 | } else { 71 | post_message -type error "Cannot create project $project_name" 72 | qexit -error 73 | } 74 | --------------------------------------------------------------------------------