├── LICENSE ├── README.md ├── SECURITY.md ├── contrib └── soft_noc │ ├── pr_concentrated_bus_demo │ ├── README │ ├── adder_grid_1d.qsf │ ├── adder_grid_1d.sv │ ├── adder_grid_2d.qsf │ ├── adder_grid_2d.sv │ ├── blinking_led.qpf │ ├── blinking_led.qsf │ ├── blinking_led.sdc │ ├── blinking_led.sv │ ├── blinking_led_default.qsf │ ├── blinking_led_empty.qsf │ ├── blinking_led_empty.sv │ ├── blinking_led_slow.qsf │ ├── blinking_led_slow.sv │ ├── run_compile.sh │ ├── top.sv │ └── top_counter.sv │ ├── pr_distributed_bus_demo │ ├── README │ ├── adder_grid_1d.qsf │ ├── adder_grid_1d.sv │ ├── adder_grid_2d.qsf │ ├── adder_grid_2d.sv │ ├── blinking_led.qpf │ ├── blinking_led.qsf │ ├── blinking_led.sdc │ ├── blinking_led.sv │ ├── blinking_led_default.qsf │ ├── blinking_led_empty.qsf │ ├── blinking_led_empty.sv │ ├── blinking_led_slow.qsf │ ├── blinking_led_slow.sv │ ├── run_compile.sh │ ├── tcl_gen │ │ ├── blinking_led.qsf.base │ │ ├── doit.sh │ │ └── pipe_maker.tcl │ ├── top.sv │ └── top_counter.sv │ └── pr_island_hop_mlab_demo │ ├── README │ ├── blinking_led.sv │ ├── bus_pipe.sv │ ├── fifo_control.sv │ ├── mlab_fifo.ip │ ├── run_compile.sh │ ├── soft_noc.qpf │ ├── soft_noc.qsf │ ├── soft_noc.sdc │ ├── tcl_gen │ ├── doit.sh │ ├── input.txt │ ├── pipe_maker.tcl │ ├── soft_noc.qsf.base │ ├── soft_noc_maker.tcl │ └── top_prefix.sv │ ├── top.sv │ └── top_counter.sv ├── pr_logo.gif ├── quartus-prime-partial-reconfiguration-diagram.jpg ├── ref_designs ├── README.md ├── a10_pcie_devkit_cvp │ ├── AN-784.pdf │ ├── README.md │ ├── a10_pcie_devkit_cvp.qpf │ ├── a10_pcie_devkit_cvp.qsf │ ├── a10_pcie_devkit_cvp.sdc │ ├── a10_pcie_devkit_cvp_base.dts │ ├── a10_pcie_devkit_cvp_basic_arithmetic.qsf │ ├── a10_pcie_devkit_cvp_basic_dsp.qsf │ ├── a10_pcie_devkit_cvp_ddr4_access.qsf │ ├── a10_pcie_devkit_cvp_gol.qsf │ ├── auxiliary.sdc │ ├── avalon_config.hex │ ├── basic_dsp_persona.stp │ ├── compile.sh │ ├── gen_pr_models.tcl │ ├── jtag.sdc │ ├── pr_logic_impl_template.qsf.template │ ├── software │ │ ├── installation │ │ │ ├── flash.pl │ │ │ └── flash.pof.gz │ │ └── util │ │ │ ├── Makefile │ │ │ ├── example_host_uio.c │ │ │ └── fpga-ioctl.h │ ├── source │ │ ├── basic_arithmetic_persona │ │ │ ├── basic_arithmetic.sv │ │ │ ├── basic_arithmetic_persona.sv │ │ │ ├── basic_arithmetic_persona_top.sv │ │ │ ├── basic_arithmetic_reg_blk.sv │ │ │ └── basic_arithmetic_top.sv │ │ ├── basic_dsp_persona │ │ │ ├── basic_dsp_persona.sv │ │ │ ├── basic_dsp_persona_top.sv │ │ │ ├── basic_dsp_top.sv │ │ │ └── logic_example_dsp_unsigned_27x27_atom.sv │ │ ├── common │ │ │ ├── emif_interface │ │ │ │ ├── emif_avmm_interface.qsys │ │ │ │ └── ip │ │ │ │ │ └── emif_avmm_interface │ │ │ │ │ ├── emif_avmm_interface_clock_in.ip │ │ │ │ │ ├── emif_avmm_interface_mm_bridge_0.ip │ │ │ │ │ ├── emif_avmm_interface_mm_clock_crossing_bridge.ip │ │ │ │ │ ├── emif_avmm_interface_reset_in.ip │ │ │ │ │ ├── emif_global_reset.ip │ │ │ │ │ └── pr_region_clock.ip │ │ │ ├── reg_file │ │ │ │ ├── ip │ │ │ │ │ └── reg_file │ │ │ │ │ │ ├── reg_file_clock_bridge.ip │ │ │ │ │ │ ├── reg_file_mm_bridge.ip │ │ │ │ │ │ ├── reg_file_pio_in.ip │ │ │ │ │ │ ├── reg_file_pio_out.ip │ │ │ │ │ │ └── reg_file_reset_bridge.ip │ │ │ │ └── reg_file.qsys │ │ │ └── sld_jtag_host │ │ │ │ └── ip │ │ │ │ └── sld_jtag_host.ip │ │ ├── ddr4_access_persona │ │ │ ├── ddr4_access_persona.sv │ │ │ ├── ddr4_access_persona_controller.sv │ │ │ ├── ddr4_access_persona_top.sv │ │ │ ├── ddr4_access_top.sv │ │ │ ├── ddr_wr_rd.sv │ │ │ ├── lfsr.sv │ │ │ ├── mem_access.sv │ │ │ ├── perf_cntr.sv │ │ │ └── traffic_generator.sv │ │ ├── gol_persona │ │ │ ├── block.sv │ │ │ ├── gol_block_wrapper.sv │ │ │ ├── gol_cell.sv │ │ │ ├── gol_persona.sv │ │ │ ├── gol_persona_top.sv │ │ │ ├── gol_top.sv │ │ │ └── moderator.sv │ │ └── static_region │ │ │ ├── a10_pcie_ref_design.sv │ │ │ ├── bsp_top.qsys │ │ │ ├── ddr4_status_bus.sv │ │ │ ├── design_top.qsys │ │ │ ├── global_rst_n_controller.sv │ │ │ ├── ip │ │ │ ├── bsp_top │ │ │ │ ├── ddr4_emif.ip │ │ │ │ ├── top_a10_pcie.ip │ │ │ │ └── top_dk.ip │ │ │ ├── design_top │ │ │ │ ├── alt_pr_ip.ip │ │ │ │ ├── avalon_mm_clk.ip │ │ │ │ ├── avalon_system_config.ip │ │ │ │ ├── bar2_avmm_pipeline_bridge.ip │ │ │ │ ├── ddr4_calibration_pio.ip │ │ │ │ ├── ddr4_ctlr_mm_clock_bridge.ip │ │ │ │ ├── emif_avmm_pbridge.ip │ │ │ │ ├── emif_clock.ip │ │ │ │ ├── emif_reset_n.ip │ │ │ │ ├── global_rst_n.ip │ │ │ │ ├── pcie_avmm_pbridge.ip │ │ │ │ ├── pcie_bar_2_mm_clock_crossing_bridge.ip │ │ │ │ ├── pcie_mm_clock_crossing_bridge.ip │ │ │ │ ├── pcie_rst_n.ip │ │ │ │ ├── pr_subsystem_pll_ref_clk.ip │ │ │ │ └── top_iopll.ip │ │ │ └── pr_subsystem │ │ │ │ ├── pr_subsystem_clock_bridge_0.ip │ │ │ │ ├── pr_subsystem_emif_clock_bridge.ip │ │ │ │ ├── pr_subsystem_freeze_bridge_cra.ip │ │ │ │ ├── pr_subsystem_freeze_bridge_ddr4.ip │ │ │ │ ├── pr_subsystem_pr_region_controller_0.ip │ │ │ │ ├── pr_subsystem_reset_bridge_0.ip │ │ │ │ └── pr_subsystem_sld_jtag_bridge_agent.ip │ │ │ ├── pr_logic_sim_wrapper.sv │ │ │ ├── pr_logic_wrapper.sv │ │ │ ├── pr_subsystem.qsys │ │ │ ├── synchronizer.sv │ │ │ └── tcd2um.sv │ └── verif │ │ └── design_top_sim │ │ ├── base_test.sv │ │ ├── basic_arith_sequence_lib.sv │ │ ├── basic_dsp_sequence_lib.sv │ │ ├── comp_sim.sh │ │ ├── ddr4_access_sequence_lib.sv │ │ ├── ddr4_memory_simulation.sv │ │ ├── design_top_sim_cfg_pkg.sv │ │ ├── design_top_sim_pkg.sv │ │ ├── environment.sv │ │ ├── gol_sequence_lib.sv │ │ ├── persona_base_sequence_lib.sv │ │ ├── region0_pr_sequence_lib.sv │ │ ├── region0_prblock_listener.sv │ │ ├── sb_predict.sv │ │ ├── sb_predictor_base.sv │ │ ├── scoreboard.sv │ │ ├── sim_reporting.sv │ │ ├── sim_top.sv │ │ ├── testbench.sv │ │ ├── tests │ │ ├── flat_basic_arith.sv │ │ ├── flat_basic_dsp.sv │ │ ├── simple_basic_arith.sv │ │ ├── simple_basic_dsp.sv │ │ ├── simple_ddr4_access.sv │ │ ├── simple_gol.sv │ │ ├── simple_pr_error.sv │ │ └── simple_pr_success.sv │ │ └── vkits │ │ ├── bar2_avmm │ │ ├── bar2_avalon_mm_master_bfm.sv │ │ ├── bar2_avalon_mm_monitor_bfm.sv │ │ ├── bar2_avmm_agent.sv │ │ ├── bar2_avmm_command_seq_item.sv │ │ ├── bar2_avmm_pkg.sv │ │ ├── bar2_avmm_response_seq_item.sv │ │ └── bar2_avmm_sequence_lib.sv │ │ └── bar4_avmm │ │ ├── bar4_avalon_mm_master_bfm.sv │ │ ├── bar4_avalon_mm_monitor_bfm.sv │ │ ├── bar4_avmm_agent.sv │ │ ├── bar4_avmm_command_seq_item.sv │ │ ├── bar4_avmm_pkg.sv │ │ ├── bar4_avmm_response_seq_item.sv │ │ └── bar4_avmm_sequence_lib.sv ├── a10_pcie_devkit_cvp_hpr │ ├── AN-813.pdf │ ├── README.md │ ├── a10_pcie_devkit_cvp.qpf │ ├── a10_pcie_devkit_cvp.qsf │ ├── a10_pcie_devkit_cvp.sdc │ ├── a10_pcie_devkit_cvp_base.dts │ ├── a10_pcie_devkit_cvp_basic_arithmetic.qsf │ ├── a10_pcie_devkit_cvp_basic_dsp.qsf │ ├── a10_pcie_devkit_cvp_ddr4_access.qsf │ ├── a10_pcie_devkit_cvp_gol.qsf │ ├── a10_pcie_devkit_cvp_normal_basic_arithmetic.qsf │ ├── a10_pcie_devkit_cvp_normal_basic_dsp.qsf │ ├── a10_pcie_devkit_cvp_normal_ddr4_access.qsf │ ├── a10_pcie_devkit_cvp_normal_gol.qsf │ ├── auxiliary.sdc │ ├── avalon_config.hex │ ├── basic_dsp_persona.stp │ ├── compile.sh │ ├── gen_pr_models.tcl │ ├── jtag.sdc │ ├── pr_logic_impl_template.qsf.template │ ├── software │ │ ├── installation │ │ │ ├── flash.pl │ │ │ └── flash.pof.gz │ │ └── util │ │ │ ├── Makefile │ │ │ ├── example_host_uio.c │ │ │ └── fpga-ioctl.h │ ├── source │ │ ├── basic_arithmetic_persona │ │ │ ├── basic_arithmetic.sv │ │ │ ├── basic_arithmetic_persona.sv │ │ │ ├── basic_arithmetic_persona_top.sv │ │ │ ├── basic_arithmetic_reg_blk.sv │ │ │ └── basic_arithmetic_top.sv │ │ ├── basic_dsp_persona │ │ │ ├── basic_dsp_persona.sv │ │ │ ├── basic_dsp_persona_top.sv │ │ │ ├── basic_dsp_top.sv │ │ │ └── logic_example_dsp_unsigned_27x27_atom.sv │ │ ├── common │ │ │ ├── emif_interface │ │ │ │ ├── emif_avmm_interface.qsys │ │ │ │ └── ip │ │ │ │ │ └── emif_avmm_interface │ │ │ │ │ ├── emif_avmm_interface_clock_in.ip │ │ │ │ │ ├── emif_avmm_interface_mm_bridge_0.ip │ │ │ │ │ ├── emif_avmm_interface_mm_clock_crossing_bridge.ip │ │ │ │ │ ├── emif_avmm_interface_reset_in.ip │ │ │ │ │ ├── emif_global_reset.ip │ │ │ │ │ └── pr_region_clock.ip │ │ │ ├── reg_file │ │ │ │ ├── ip │ │ │ │ │ └── reg_file │ │ │ │ │ │ ├── reg_file_clock_bridge.ip │ │ │ │ │ │ ├── reg_file_mm_bridge.ip │ │ │ │ │ │ ├── reg_file_pio_in.ip │ │ │ │ │ │ ├── reg_file_pio_out.ip │ │ │ │ │ │ └── reg_file_reset_bridge.ip │ │ │ │ └── reg_file.qsys │ │ │ ├── sld_jtag_agent │ │ │ │ └── sld_jtag_agent.ip │ │ │ └── sld_jtag_host │ │ │ │ └── sld_jtag_host.ip │ │ ├── ddr4_access_persona │ │ │ ├── ddr4_access_persona.sv │ │ │ ├── ddr4_access_persona_controller.sv │ │ │ ├── ddr4_access_persona_top.sv │ │ │ ├── ddr4_access_top.sv │ │ │ ├── ddr_wr_rd.sv │ │ │ ├── lfsr.sv │ │ │ ├── mem_access.sv │ │ │ ├── perf_cntr.sv │ │ │ └── traffic_generator.sv │ │ ├── gol_persona │ │ │ ├── block.sv │ │ │ ├── gol_block_wrapper.sv │ │ │ ├── gol_cell.sv │ │ │ ├── gol_persona.sv │ │ │ ├── gol_persona_top.sv │ │ │ ├── gol_top.sv │ │ │ └── moderator.sv │ │ ├── parent_persona │ │ │ ├── child_pr_logic_sim_wrapper_0.sv │ │ │ ├── child_pr_logic_sim_wrapper_1.sv │ │ │ ├── child_pr_logic_wrapper_0.sv │ │ │ ├── child_pr_logic_wrapper_1.sv │ │ │ ├── ip │ │ │ │ └── parent_pr_subsystem │ │ │ │ │ ├── emif_clk.ip │ │ │ │ │ ├── emif_rst_n.ip │ │ │ │ │ ├── parent_pr_child_avmm_pbridge.ip │ │ │ │ │ ├── parent_pr_emif_avmm_pbridge.ip │ │ │ │ │ ├── parent_pr_emif_avmm_pbridge_to_static.ip │ │ │ │ │ ├── parent_pr_pcie_avmm_pbridge.ip │ │ │ │ │ ├── parent_pr_subsystem_clock_in.ip │ │ │ │ │ ├── parent_pr_subsystem_freeze_bridge_cra.ip │ │ │ │ │ ├── parent_pr_subsystem_freeze_bridge_ddr4.ip │ │ │ │ │ ├── parent_pr_subsystem_id.ip │ │ │ │ │ ├── parent_pr_subsystem_pr_region_controller_0.ip │ │ │ │ │ ├── parent_pr_subsystem_reset_in.ip │ │ │ │ │ └── pr_parent_subsystem_sld_jtag_bridge_agent.ip │ │ │ ├── parent_persona_top.sv │ │ │ └── parent_pr_subsystem.qsys │ │ ├── static_region │ │ │ ├── a10_pcie_ref_design.sv │ │ │ ├── bsp_top.qsys │ │ │ ├── ddr4_status_bus.sv │ │ │ ├── design_top.qsys │ │ │ ├── global_rst_n_controller.sv │ │ │ ├── ip │ │ │ │ ├── bsp_top │ │ │ │ │ ├── ddr4_emif.ip │ │ │ │ │ ├── top_a10_pcie.ip │ │ │ │ │ └── top_dk.ip │ │ │ │ ├── design_top │ │ │ │ │ ├── alt_pr_ip.ip │ │ │ │ │ ├── avalon_mm_clk.ip │ │ │ │ │ ├── avalon_system_config.ip │ │ │ │ │ ├── bar2_avmm_pipeline_bridge.ip │ │ │ │ │ ├── ddr4_calibration_pio.ip │ │ │ │ │ ├── ddr4_ctlr_mm_clock_bridge.ip │ │ │ │ │ ├── emif_avmm_pbridge.ip │ │ │ │ │ ├── emif_clock.ip │ │ │ │ │ ├── emif_reset_n.ip │ │ │ │ │ ├── global_rst_n.ip │ │ │ │ │ ├── pcie_avmm_pbridge.ip │ │ │ │ │ ├── pcie_bar_2_mm_clock_crossing_bridge.ip │ │ │ │ │ ├── pcie_mm_clock_crossing_bridge.ip │ │ │ │ │ ├── pcie_rst_n.ip │ │ │ │ │ ├── pr_subsystem_pll_ref_clk.ip │ │ │ │ │ └── top_iopll.ip │ │ │ │ └── pr_subsystem │ │ │ │ │ ├── pr_subsystem_clock_bridge_0.ip │ │ │ │ │ ├── pr_subsystem_emif_clock_bridge.ip │ │ │ │ │ ├── pr_subsystem_freeze_bridge_cra.ip │ │ │ │ │ ├── pr_subsystem_freeze_bridge_ddr4.ip │ │ │ │ │ ├── pr_subsystem_pr_region_controller_0.ip │ │ │ │ │ ├── pr_subsystem_reset_bridge_0.ip │ │ │ │ │ └── pr_subsystem_sld_jtag_bridge_agent.ip │ │ │ ├── pr_logic_sim_wrapper.sv │ │ │ ├── pr_logic_wrapper.sv │ │ │ ├── pr_subsystem.qsys │ │ │ ├── synchronizer.sv │ │ │ └── tcd2um.sv │ │ └── templates │ │ │ └── pr_logic_template.sv │ └── verif │ │ └── design_top_sim │ │ ├── base_test.sv │ │ ├── basic_arith_sequence_lib.sv │ │ ├── basic_dsp_sequence_lib.sv │ │ ├── basic_hpr_sequence_lib.sv │ │ ├── comp_sim.sh │ │ ├── ddr4_access_sequence_lib.sv │ │ ├── ddr4_memory_simulation.sv │ │ ├── design_top_sim_cfg_pkg.sv │ │ ├── design_top_sim_pkg.sv │ │ ├── environment.sv │ │ ├── gol_sequence_lib.sv │ │ ├── persona_base_sequence_lib.sv │ │ ├── region0_pr_sequence_lib.sv │ │ ├── region0_prblock_listener.sv │ │ ├── sb_predict.sv │ │ ├── sb_predictor_base.sv │ │ ├── scoreboard.sv │ │ ├── sim_reporting.sv │ │ ├── sim_top.sv │ │ ├── testbench.sv │ │ ├── tests │ │ ├── flat_basic_arith.sv │ │ ├── flat_basic_dsp.sv │ │ ├── simple_basic_arith.sv │ │ ├── simple_basic_dsp.sv │ │ ├── simple_ddr4_access.sv │ │ ├── simple_gol.sv │ │ ├── simple_hpr_test.sv │ │ ├── simple_pr_error.sv │ │ ├── simple_pr_parent_test.sv │ │ └── simple_pr_success.sv │ │ └── vkits │ │ ├── bar2_avmm │ │ ├── bar2_avalon_mm_master_bfm.sv │ │ ├── bar2_avalon_mm_monitor_bfm.sv │ │ ├── bar2_avmm_agent.sv │ │ ├── bar2_avmm_command_seq_item.sv │ │ ├── bar2_avmm_pkg.sv │ │ ├── bar2_avmm_response_seq_item.sv │ │ └── bar2_avmm_sequence_lib.sv │ │ └── bar4_avmm │ │ ├── bar4_avalon_mm_master_bfm.sv │ │ ├── bar4_avalon_mm_monitor_bfm.sv │ │ ├── bar4_avmm_agent.sv │ │ ├── bar4_avmm_command_seq_item.sv │ │ ├── bar4_avmm_pkg.sv │ │ ├── bar4_avmm_response_seq_item.sv │ │ └── bar4_avmm_sequence_lib.sv ├── s10_pcie_devkit_hpr │ ├── AN-820.pdf │ ├── README.md │ ├── auxiliary.sdc │ ├── avalon_config.hex │ ├── basic_dsp_persona.stp │ ├── compile.sh │ ├── gen_pr_models.tcl │ ├── jtag.sdc │ ├── pr_logic_impl_template.qsf.template │ ├── quartus.ini │ ├── s10_pcie_devkit_hpr.qpf │ ├── s10_pcie_devkit_hpr.qsf │ ├── s10_pcie_devkit_hpr.sdc │ ├── s10_pcie_devkit_hpr_basic_arithmetic.qsf │ ├── s10_pcie_devkit_hpr_basic_dsp.qsf │ ├── s10_pcie_devkit_hpr_ddr4_access.qsf │ ├── s10_pcie_devkit_hpr_gol.qsf │ ├── s10_pcie_devkit_hpr_normal_basic_arithmetic.qsf │ ├── s10_pcie_devkit_hpr_normal_basic_dsp.qsf │ ├── s10_pcie_devkit_hpr_normal_ddr4_access.qsf │ ├── s10_pcie_devkit_hpr_normal_gol.qsf │ ├── software │ │ ├── installation │ │ │ ├── flash.pl │ │ │ ├── max5_116.pof │ │ │ └── system_max_s10_pcie.pof │ │ └── util │ │ │ ├── Makefile │ │ │ ├── example_host_uio.c │ │ │ └── fpga-ioctl.h │ ├── source │ │ ├── basic_arithmetic_persona │ │ │ ├── basic_arithmetic.sv │ │ │ ├── basic_arithmetic_persona.sv │ │ │ ├── basic_arithmetic_persona_top.sv │ │ │ ├── basic_arithmetic_reg_blk.sv │ │ │ └── basic_arithmetic_top.sv │ │ ├── basic_dsp_persona │ │ │ ├── basic_dsp_persona.sv │ │ │ ├── basic_dsp_persona_top.sv │ │ │ └── basic_dsp_top.sv │ │ ├── common │ │ │ ├── emif_interface │ │ │ │ ├── emif_avmm_interface.qsys │ │ │ │ └── ip │ │ │ │ │ └── emif_avmm_interface │ │ │ │ │ ├── emif_avmm_interface_clock_in.ip │ │ │ │ │ ├── emif_avmm_interface_mm_bridge_0.ip │ │ │ │ │ ├── emif_avmm_interface_mm_clock_crossing_bridge.ip │ │ │ │ │ ├── emif_avmm_interface_reset_in.ip │ │ │ │ │ ├── emif_global_reset.ip │ │ │ │ │ └── pr_region_clock.ip │ │ │ ├── reg_file │ │ │ │ ├── ip │ │ │ │ │ └── reg_file │ │ │ │ │ │ ├── reg_file_clock_bridge.ip │ │ │ │ │ │ ├── reg_file_mm_bridge.ip │ │ │ │ │ │ ├── reg_file_pio_in.ip │ │ │ │ │ │ ├── reg_file_pio_out.ip │ │ │ │ │ │ └── reg_file_reset_bridge.ip │ │ │ │ └── reg_file.qsys │ │ │ ├── sld_jtag_agent │ │ │ │ └── sld_jtag_agent.ip │ │ │ └── sld_jtag_host │ │ │ │ └── ip │ │ │ │ └── sld_jtag_host.ip │ │ ├── ddr4_access_persona │ │ │ ├── ddr4_access_persona.sv │ │ │ ├── ddr4_access_persona_controller.sv │ │ │ ├── ddr4_access_persona_top.sv │ │ │ ├── ddr4_access_top.sv │ │ │ ├── ddr_wr_rd.sv │ │ │ ├── lfsr.sv │ │ │ ├── mem_access.sv │ │ │ ├── perf_cntr.sv │ │ │ └── traffic_generator.sv │ │ ├── gol_persona │ │ │ ├── block.sv │ │ │ ├── gol_block_wrapper.sv │ │ │ ├── gol_cell.sv │ │ │ ├── gol_persona.sv │ │ │ ├── gol_persona_top.sv │ │ │ ├── gol_top.sv │ │ │ └── moderator.sv │ │ ├── parent_persona │ │ │ ├── child_pr_logic_wrapper_0.sv │ │ │ ├── child_pr_logic_wrapper_1.sv │ │ │ ├── ip │ │ │ │ └── parent_pr_subsystem │ │ │ │ │ ├── emif_clk.ip │ │ │ │ │ ├── emif_rst_n.ip │ │ │ │ │ ├── parent_pr_emif_avmm_pbridge.ip │ │ │ │ │ ├── parent_pr_pcie_avmm_pbridge.ip │ │ │ │ │ ├── parent_pr_subsystem_clock_in.ip │ │ │ │ │ ├── parent_pr_subsystem_freeze_bridge_cra.ip │ │ │ │ │ ├── parent_pr_subsystem_freeze_bridge_ddr4.ip │ │ │ │ │ ├── parent_pr_subsystem_id.ip │ │ │ │ │ ├── parent_pr_subsystem_pr_region_controller_0.ip │ │ │ │ │ ├── parent_pr_subsystem_reset_in.ip │ │ │ │ │ └── pr_parent_subsystem_sld_jtag_bridge_agent.ip │ │ │ ├── parent_persona_top.sv │ │ │ └── parent_pr_subsystem.qsys │ │ ├── static_region │ │ │ ├── bsp_top.qsys │ │ │ ├── ddr4_reset_conduit.sv │ │ │ ├── ddr4_status_bus.sv │ │ │ ├── design_top.qsys │ │ │ ├── global_rst_n_controller.sv │ │ │ ├── ip │ │ │ │ ├── bsp_top │ │ │ │ │ ├── bsp_top_emif_s10_0.ip │ │ │ │ │ └── s10_pcie.ip │ │ │ │ ├── design_top │ │ │ │ │ ├── avalon_mm_clk.ip │ │ │ │ │ ├── avalon_system_config.ip │ │ │ │ │ ├── bar4_avmm_cc_bridge.ip │ │ │ │ │ ├── bar4_avmm_pipeline_bridge_0.ip │ │ │ │ │ ├── ddr4_calibration_pio.ip │ │ │ │ │ ├── ddr4_ctlr_mm_clock_bridge.ip │ │ │ │ │ ├── ddr4_reset_request.ip │ │ │ │ │ ├── ddr4_reset_status.ip │ │ │ │ │ ├── design_top_iopll.ip │ │ │ │ │ ├── emif_avmm_bridge.ip │ │ │ │ │ ├── emif_avmm_pbridge.ip │ │ │ │ │ ├── emif_clock.ip │ │ │ │ │ ├── emif_reset_n.ip │ │ │ │ │ ├── global_rst_n.ip │ │ │ │ │ ├── pcie_avmm_pbridge.ip │ │ │ │ │ ├── pcie_mm_clock_crossing_bridge.ip │ │ │ │ │ ├── pcie_rst_n.ip │ │ │ │ │ ├── pr_subsystem_pll_ref_clk.ip │ │ │ │ │ └── s10_pr.ip │ │ │ │ └── pr_subsystem │ │ │ │ │ ├── emif_bridge.ip │ │ │ │ │ ├── emif_pipeline_bridge.ip │ │ │ │ │ ├── pr_subsystem_clock_bridge_0.ip │ │ │ │ │ ├── pr_subsystem_emif_clock_bridge.ip │ │ │ │ │ ├── pr_subsystem_freeze_bridge_cra.ip │ │ │ │ │ ├── pr_subsystem_freeze_bridge_ddr4.ip │ │ │ │ │ ├── pr_subsystem_pr_region_controller_0.ip │ │ │ │ │ ├── pr_subsystem_reset_bridge_0.ip │ │ │ │ │ └── pr_subsystem_sld_jtag_bridge_agent.ip │ │ │ ├── pr_logic_sim_wrapper.sv │ │ │ ├── pr_logic_wrapper.sv │ │ │ ├── pr_subsystem.qsys │ │ │ ├── s10_pcie_ref_design.sv │ │ │ ├── synchronizer.sv │ │ │ └── tcd2um.sv │ │ └── templates │ │ │ └── pr_logic_template.sv │ └── verif │ │ └── design_top_sim │ │ ├── base_test.sv │ │ ├── basic_arith_sequence_lib.sv │ │ ├── basic_dsp_sequence_lib.sv │ │ ├── comp_sim.sh │ │ ├── ddr4_access_sequence_lib.sv │ │ ├── ddr4_memory_simulation.sv │ │ ├── design_top_sim_cfg_pkg.sv │ │ ├── design_top_sim_pkg.sv │ │ ├── environment.sv │ │ ├── gol_sequence_lib.sv │ │ ├── persona_base_sequence_lib.sv │ │ ├── region0_pr_sequence_lib.sv │ │ ├── reset_watchdog.sv │ │ ├── reset_watchdog_if.sv │ │ ├── sb_predict.sv │ │ ├── sb_predictor_base.sv │ │ ├── scoreboard.sv │ │ ├── sim_reporting.sv │ │ ├── sim_top.sv │ │ ├── testbench.sv │ │ ├── tests │ │ ├── flat_basic_arith.sv │ │ ├── flat_basic_dsp.sv │ │ ├── simple_basic_arith.sv │ │ ├── simple_basic_dsp.sv │ │ ├── simple_ddr4_access.sv │ │ ├── simple_gol.sv │ │ ├── simple_pr_error.sv │ │ └── simple_pr_success.sv │ │ └── vkits │ │ ├── bar2_avmm │ │ ├── bar2_avalon_mm_master_bfm.sv │ │ ├── bar2_avalon_mm_monitor_bfm.sv │ │ ├── bar2_avmm_agent.sv │ │ ├── bar2_avmm_command_seq_item.sv │ │ ├── bar2_avmm_pkg.sv │ │ ├── bar2_avmm_response_seq_item.sv │ │ └── bar2_avmm_sequence_lib.sv │ │ └── bar4_avmm │ │ ├── bar4_avalon_mm_master_bfm.sv │ │ ├── bar4_avalon_mm_monitor_bfm.sv │ │ ├── bar4_avmm_agent.sv │ │ ├── bar4_avmm_command_seq_item.sv │ │ ├── bar4_avmm_pkg.sv │ │ ├── bar4_avmm_response_seq_item.sv │ │ └── bar4_avmm_sequence_lib.sv └── s10_pcie_devkit_pr │ ├── AN-819.pdf │ ├── README.md │ ├── auxiliary.sdc │ ├── avalon_config.hex │ ├── basic_dsp_persona.stp │ ├── compile.sh │ ├── gen_pr_models.tcl │ ├── jtag.sdc │ ├── pr_logic_impl_template.qsf.template │ ├── quartus.ini │ ├── s10_pcie_devkit_pr.qpf │ ├── s10_pcie_devkit_pr.qsf │ ├── s10_pcie_devkit_pr.sdc │ ├── s10_pcie_devkit_pr.stp │ ├── s10_pcie_devkit_pr_basic_arithmetic.qsf │ ├── s10_pcie_devkit_pr_basic_dsp.qsf │ ├── s10_pcie_devkit_pr_ddr4_access.qsf │ ├── s10_pcie_devkit_pr_gol.qsf │ ├── software │ ├── installation │ │ ├── flash.pl │ │ ├── max5_116.pof │ │ └── system_max_s10_pcie.pof │ └── util │ │ ├── Makefile │ │ ├── example_host_uio.c │ │ └── fpga-ioctl.h │ ├── source │ ├── basic_arithmetic_persona │ │ ├── basic_arithmetic.sv │ │ ├── basic_arithmetic_persona.sv │ │ ├── basic_arithmetic_persona_top.sv │ │ ├── basic_arithmetic_reg_blk.sv │ │ └── basic_arithmetic_top.sv │ ├── basic_dsp_persona │ │ ├── basic_dsp_persona.sv │ │ ├── basic_dsp_persona_top.sv │ │ └── basic_dsp_top.sv │ ├── common │ │ ├── emif_interface │ │ │ ├── emif_avmm_interface.qsys │ │ │ └── ip │ │ │ │ └── emif_avmm_interface │ │ │ │ ├── emif_avmm_interface_clock_in.ip │ │ │ │ ├── emif_avmm_interface_mm_bridge_0.ip │ │ │ │ ├── emif_avmm_interface_mm_clock_crossing_bridge.ip │ │ │ │ ├── emif_avmm_interface_reset_in.ip │ │ │ │ ├── emif_global_reset.ip │ │ │ │ └── pr_region_clock.ip │ │ ├── reg_file │ │ │ ├── ip │ │ │ │ └── reg_file │ │ │ │ │ ├── reg_file_clock_bridge.ip │ │ │ │ │ ├── reg_file_mm_bridge.ip │ │ │ │ │ ├── reg_file_pio_in.ip │ │ │ │ │ ├── reg_file_pio_out.ip │ │ │ │ │ └── reg_file_reset_bridge.ip │ │ │ └── reg_file.qsys │ │ └── sld_jtag_host │ │ │ └── ip │ │ │ └── sld_jtag_host.ip │ ├── ddr4_access_persona │ │ ├── ddr4_access_persona.sv │ │ ├── ddr4_access_persona_controller.sv │ │ ├── ddr4_access_persona_top.sv │ │ ├── ddr4_access_top.sv │ │ ├── ddr_wr_rd.sv │ │ ├── lfsr.sv │ │ ├── mem_access.sv │ │ ├── perf_cntr.sv │ │ └── traffic_generator.sv │ ├── gol_persona │ │ ├── block.sv │ │ ├── gol_block_wrapper.sv │ │ ├── gol_cell.sv │ │ ├── gol_persona.sv │ │ ├── gol_persona_top.sv │ │ ├── gol_top.sv │ │ └── moderator.sv │ └── static_region │ │ ├── bsp_top.qsys │ │ ├── ddr4_reset_conduit.sv │ │ ├── ddr4_status_bus.sv │ │ ├── design_top.qsys │ │ ├── global_rst_n_controller.sv │ │ ├── ip │ │ ├── bsp_top │ │ │ ├── bsp_top_emif_s10_0.ip │ │ │ └── s10_pcie.ip │ │ ├── design_top │ │ │ ├── avalon_mm_clk.ip │ │ │ ├── avalon_system_config.ip │ │ │ ├── bar4_avmm_cc_bridge.ip │ │ │ ├── bar4_avmm_pipeline_bridge_0.ip │ │ │ ├── ddr4_calibration_pio.ip │ │ │ ├── ddr4_ctlr_mm_clock_bridge.ip │ │ │ ├── ddr4_reset_request.ip │ │ │ ├── ddr4_reset_status.ip │ │ │ ├── design_top_iopll.ip │ │ │ ├── emif_avmm_bridge.ip │ │ │ ├── emif_avmm_pbridge.ip │ │ │ ├── emif_clock.ip │ │ │ ├── emif_reset_n.ip │ │ │ ├── global_rst_n.ip │ │ │ ├── pcie_avmm_pbridge.ip │ │ │ ├── pcie_mm_clock_crossing_bridge.ip │ │ │ ├── pcie_rst_n.ip │ │ │ ├── pr_subsystem_pll_ref_clk.ip │ │ │ └── s10_pr.ip │ │ └── pr_subsystem │ │ │ ├── emif_bridge.ip │ │ │ ├── emif_pipeline_bridge.ip │ │ │ ├── pr_subsystem_clock_bridge_0.ip │ │ │ ├── pr_subsystem_emif_clock_bridge.ip │ │ │ ├── pr_subsystem_freeze_bridge_cra.ip │ │ │ ├── pr_subsystem_freeze_bridge_ddr4.ip │ │ │ ├── pr_subsystem_pr_region_controller_0.ip │ │ │ ├── pr_subsystem_reset_bridge_0.ip │ │ │ └── pr_subsystem_sld_jtag_bridge_agent.ip │ │ ├── pr_logic_sim_wrapper.sv │ │ ├── pr_logic_wrapper.sv │ │ ├── pr_subsystem.qsys │ │ ├── s10_pcie_ref_design.sv │ │ ├── synchronizer.sv │ │ └── tcd2um.sv │ └── verif │ └── design_top_sim │ ├── base_test.sv │ ├── basic_arith_sequence_lib.sv │ ├── basic_dsp_sequence_lib.sv │ ├── comp_sim.sh │ ├── ddr4_access_sequence_lib.sv │ ├── ddr4_memory_simulation.sv │ ├── design_top_sim_cfg_pkg.sv │ ├── design_top_sim_pkg.sv │ ├── environment.sv │ ├── gol_sequence_lib.sv │ ├── persona_base_sequence_lib.sv │ ├── region0_pr_sequence_lib.sv │ ├── reset_watchdog.sv │ ├── reset_watchdog_if.sv │ ├── sb_predict.sv │ ├── sb_predictor_base.sv │ ├── scoreboard.sv │ ├── sim_reporting.sv │ ├── sim_top.sv │ ├── testbench.sv │ ├── tests │ ├── flat_basic_arith.sv │ ├── flat_basic_dsp.sv │ ├── simple_basic_arith.sv │ ├── simple_basic_dsp.sv │ ├── simple_ddr4_access.sv │ ├── simple_gol.sv │ ├── simple_pr_error.sv │ └── simple_pr_success.sv │ └── vkits │ ├── bar2_avmm │ ├── bar2_avalon_mm_master_bfm.sv │ ├── bar2_avalon_mm_monitor_bfm.sv │ ├── bar2_avmm_agent.sv │ ├── bar2_avmm_command_seq_item.sv │ ├── bar2_avmm_pkg.sv │ ├── bar2_avmm_response_seq_item.sv │ └── bar2_avmm_sequence_lib.sv │ └── bar4_avmm │ ├── bar4_avalon_mm_master_bfm.sv │ ├── bar4_avalon_mm_monitor_bfm.sv │ ├── bar4_avmm_agent.sv │ ├── bar4_avmm_command_seq_item.sv │ ├── bar4_avmm_pkg.sv │ ├── bar4_avmm_response_seq_item.sv │ └── bar4_avmm_sequence_lib.sv ├── scripts ├── README.md ├── jtag.sdc └── jtag_with_a10_pr_ip.sdc ├── software ├── README.md └── drivers │ ├── README.md │ ├── fpga │ ├── Makefile │ ├── README.md │ ├── altera-pr-ip-core.c │ ├── altera-pr-ip-core.h │ ├── altera-pr-ip-core_s10.c │ ├── fpga-mgr-debugfs.c │ ├── fpga-mgr-debugfs.h │ ├── fpga-mgr.c │ ├── fpga-pcie.c │ ├── fpga_region_controller.c │ ├── libfdt │ │ ├── fdt.c │ │ ├── fdt.h │ │ ├── fdt_empty_tree.c │ │ ├── fdt_ro.c │ │ ├── fdt_rw.c │ │ ├── fdt_sw.c │ │ ├── fdt_wip.c │ │ ├── libfdt.h │ │ ├── libfdt_env.h │ │ └── libfdt_internal.h │ ├── linux │ │ └── fpga │ │ │ └── fpga-mgr.h │ ├── program-fpga-jtag │ └── program-fpga-pcie │ └── fpga_pcie │ ├── Makefile │ ├── altera-pr-ip-core-a10.c │ ├── altera-pr-ip-core-s10.c │ ├── altera-pr-ip-core.h │ ├── fpga-configure.c │ ├── fpga-ioctl.h │ ├── fpga-pcie.c │ ├── fpga-pcie.h │ ├── fpga-region-controller.c │ ├── fpga-region-controller.h │ └── program-fpga-jtag ├── tutorials ├── README.md ├── a10_pcie_devkit_blinking_led │ ├── AN-797.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── jtag.sdc │ │ ├── top.sv │ │ └── top_counter.sv │ └── pr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── compile.sh │ │ ├── jtag.sdc │ │ ├── pr_ip.ip │ │ ├── top.sv │ │ └── top_counter.sv ├── a10_pcie_devkit_blinking_led_hpr │ ├── AN-806.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── jtag.sdc │ │ ├── top.sv │ │ └── top_counter.sv │ └── hpr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_child.sv │ │ ├── blinking_led_child_empty.sv │ │ ├── blinking_led_child_slow.sv │ │ ├── blinking_led_slow.sv │ │ ├── compile.sh │ │ ├── hpr_child_default.qsf │ │ ├── hpr_child_empty.qsf │ │ ├── hpr_child_slow.qsf │ │ ├── hpr_parent_slow_child_default.qsf │ │ ├── hpr_parent_slow_child_slow.qsf │ │ ├── jtag.sdc │ │ ├── pr_ip.ip │ │ ├── prpof_id_mif_gen.tcl │ │ ├── top.sv │ │ └── top_counter.sv ├── a10_pcie_devkit_blinking_led_stp │ ├── AN-845.pdf │ ├── README.md │ ├── finish │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── config_reset_release_endpoint.ip │ │ ├── jtag.sdc │ │ ├── pr_ip.ip │ │ ├── sld_agent.ip │ │ ├── sld_host.ip │ │ ├── stp_default.stp │ │ ├── stp_empty.stp │ │ ├── stp_slow.stp │ │ ├── top.sv │ │ └── top_counter.sv │ └── start │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── jtag.sdc │ │ ├── pr_ip.ip │ │ ├── top.sv │ │ └── top_counter.sv ├── a10_pcie_devkit_blinking_led_supr │ ├── AN-817.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── jtag.sdc │ │ ├── top.sv │ │ └── top_counter.sv │ └── supr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── impl_blinking_led_supr_new.qsf │ │ ├── jtag.sdc │ │ ├── pr_ip.ip │ │ ├── top.sv │ │ ├── top_counter.sv │ │ └── top_counter_fast.sv ├── a10_pcie_devkit_pr_sim │ ├── AN-1007.pdf │ ├── README.md │ ├── pr │ │ ├── and_gate.qsf │ │ ├── and_gate.sv │ │ ├── counter.qsf │ │ ├── counter.sv │ │ ├── fsm.qsf │ │ ├── fsm.sv │ │ ├── pr_sim.qpf │ │ ├── pr_wrapper.sv │ │ ├── top.qsf │ │ └── top.sv │ └── pr_sim │ │ ├── and_gate.qsf │ │ ├── and_gate.sv │ │ ├── counter.qsf │ │ ├── counter.sv │ │ ├── freeze_logic_controller.sv │ │ ├── fsm.qsf │ │ ├── fsm.sv │ │ ├── gen_pr_models.do │ │ ├── pr_sim.qpf │ │ ├── pr_sim.qsf │ │ ├── pr_sim_wrapper.sv │ │ ├── pr_wrapper.sv │ │ ├── run_pr_sim.do │ │ ├── run_pr_sim_only.do │ │ ├── top.qsf │ │ ├── top.sv │ │ ├── top_sim.sv │ │ ├── top_tb.sv │ │ └── wave.do ├── agilex5_pcie_devkit_pr_sim │ ├── AN-1007.pdf │ ├── README.md │ ├── pr │ │ ├── and_gate.qsf │ │ ├── and_gate.sv │ │ ├── counter.qsf │ │ ├── counter.sv │ │ ├── fsm.qsf │ │ ├── fsm.sv │ │ ├── pr_sim.qpf │ │ ├── pr_wrapper.sv │ │ ├── top.qsf │ │ └── top.sv │ └── pr_sim │ │ ├── and_gate.qsf │ │ ├── and_gate.sv │ │ ├── counter.qsf │ │ ├── counter.sv │ │ ├── freeze_logic_controller.sv │ │ ├── fsm.qsf │ │ ├── fsm.sv │ │ ├── gen_pr_models.do │ │ ├── pr_sim.qpf │ │ ├── pr_sim.qsf │ │ ├── pr_sim_wrapper.sv │ │ ├── pr_wrapper.sv │ │ ├── run_pr_sim.do │ │ ├── run_pr_sim_only.do │ │ ├── top.qsf │ │ ├── top.sv │ │ ├── top_sim.sv │ │ ├── top_tb.sv │ │ └── wave.do ├── agilex7_pcie_devkit_pr_sim │ ├── AN-1007.pdf │ ├── README.md │ ├── pr │ │ ├── and_gate.qsf │ │ ├── and_gate.sv │ │ ├── counter.qsf │ │ ├── counter.sv │ │ ├── fsm.qsf │ │ ├── fsm.sv │ │ ├── pr_sim.qpf │ │ ├── pr_wrapper.sv │ │ ├── top.qsf │ │ └── top.sv │ └── pr_sim │ │ ├── and_gate.qsf │ │ ├── and_gate.sv │ │ ├── counter.qsf │ │ ├── counter.sv │ │ ├── freeze_logic_controller.sv │ │ ├── fsm.qsf │ │ ├── fsm.sv │ │ ├── gen_pr_models.do │ │ ├── pr_sim.qpf │ │ ├── pr_sim.qsf │ │ ├── pr_sim_wrapper.sv │ │ ├── pr_wrapper.sv │ │ ├── run_pr_sim.do │ │ ├── run_pr_sim_only.do │ │ ├── top.qsf │ │ ├── top.sv │ │ ├── top_sim.sv │ │ ├── top_tb.sv │ │ └── wave.do ├── agilex7f_external_pr_configuration │ ├── AN-991.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv │ └── pr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── external_host_pr_ip.ip │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv ├── agilex7f_pcie_devkit_blinking_led │ ├── AN-953.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── top.sv │ │ └── top_counter.sv │ └── pr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── top.sv │ │ └── top_counter.sv ├── agilex7f_pcie_devkit_blinking_led_hpr │ ├── AN-954.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv │ └── hpr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_child.sv │ │ ├── blinking_led_child_empty.sv │ │ ├── blinking_led_child_slow.sv │ │ ├── blinking_led_slow.sv │ │ ├── hpr_child_default.qsf │ │ ├── hpr_child_empty.qsf │ │ ├── hpr_child_slow.qsf │ │ ├── hpr_parent_slow_child_default.qsf │ │ ├── hpr_parent_slow_child_slow.qsf │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv ├── agilex7f_pcie_devkit_blinking_led_stp │ ├── AN-964.pdf │ ├── README.md │ ├── finish │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── config_reset_release_endpoint.ip │ │ ├── reset_release.ip │ │ ├── sld_agent.ip │ │ ├── sld_host.ip │ │ ├── stp_default.stp │ │ ├── stp_empty.stp │ │ ├── stp_slow.stp │ │ ├── top.sv │ │ └── top_counter.sv │ └── start │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── top.sv │ │ └── top_counter.sv ├── agilex7f_pcie_devkit_blinking_led_supr │ ├── AN-987.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv │ └── supr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── impl_blinking_led_supr_new.qsf │ │ ├── reset_release.ip │ │ ├── top.sv │ │ ├── top_counter.sv │ │ └── top_counter_fast.sv ├── agilex7m_external_pr_configuration │ ├── AN-991.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv │ └── pr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── external_host_pr_ip.ip │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv ├── agilex7m_pcie_devkit_blinking_led │ ├── AN-953.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── top.sv │ │ └── top_counter.sv │ └── pr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── top.sv │ │ └── top_counter.sv ├── agilex7m_pcie_devkit_blinking_led_hpr │ ├── AN-954.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv │ └── hpr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_child.sv │ │ ├── blinking_led_child_empty.sv │ │ ├── blinking_led_child_slow.sv │ │ ├── blinking_led_slow.sv │ │ ├── hpr_child_default.qsf │ │ ├── hpr_child_empty.qsf │ │ ├── hpr_child_slow.qsf │ │ ├── hpr_parent_slow_child_default.qsf │ │ ├── hpr_parent_slow_child_slow.qsf │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv ├── agilex7m_pcie_devkit_blinking_led_stp │ ├── AN-964.pdf │ ├── README.md │ ├── finish │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── config_reset_release_endpoint.ip │ │ ├── reset_release.ip │ │ ├── sld_agent.ip │ │ ├── sld_host.ip │ │ ├── stp_default.stp │ │ ├── stp_empty.stp │ │ ├── stp_slow.stp │ │ ├── top.sv │ │ └── top_counter.sv │ └── start │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── top.sv │ │ └── top_counter.sv ├── agilex7m_pcie_devkit_blinking_led_supr │ ├── AN-987.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── reset_release.ip │ │ ├── top.sv │ │ └── top_counter.sv │ └── supr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── impl_blinking_led_supr_new.qsf │ │ ├── reset_release.ip │ │ ├── top.sv │ │ ├── top_counter.sv │ │ └── top_counter_fast.sv ├── s10_pcie_devkit_blinking_led │ ├── AN-825.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── top.sv │ │ └── top_counter.sv │ └── pr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── compile.sh │ │ ├── top.sv │ │ └── top_counter.sv ├── s10_pcie_devkit_blinking_led_hpr │ ├── AN-826.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── top.sv │ │ └── top_counter.sv │ └── hpr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_child.sv │ │ ├── blinking_led_child_empty.sv │ │ ├── blinking_led_child_slow.sv │ │ ├── blinking_led_slow.sv │ │ ├── compile.sh │ │ ├── hpr_child_default.qsf │ │ ├── hpr_child_empty.qsf │ │ ├── hpr_child_slow.qsf │ │ ├── hpr_parent_slow_child_default.qsf │ │ ├── hpr_parent_slow_child_slow.qsf │ │ ├── top.sv │ │ └── top_counter.sv ├── s10_pcie_devkit_blinking_led_stp │ ├── AN-841.pdf │ ├── README.md │ ├── finish │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── config_reset_release_endpoint.ip │ │ ├── reset_release.ip │ │ ├── sld_agent.ip │ │ ├── sld_host.ip │ │ ├── stp_default.stp │ │ ├── stp_empty.stp │ │ ├── stp_slow.stp │ │ ├── top.sv │ │ └── top_counter.sv │ └── start │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── top.sv │ │ └── top_counter.sv ├── s10_pcie_devkit_blinking_led_supr │ ├── AN-818.pdf │ ├── README.md │ ├── flat │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── top.sv │ │ └── top_counter.sv │ └── supr │ │ ├── blinking_led.qpf │ │ ├── blinking_led.qsf │ │ ├── blinking_led.sdc │ │ ├── blinking_led.sv │ │ ├── blinking_led_default.qsf │ │ ├── blinking_led_empty.qsf │ │ ├── blinking_led_empty.sv │ │ ├── blinking_led_slow.qsf │ │ ├── blinking_led_slow.sv │ │ ├── impl_blinking_led_supr_new.qsf │ │ ├── top.sv │ │ ├── top_counter.sv │ │ └── top_counter_fast.sv └── s10_pcie_devkit_pr_sim │ ├── AN-1007.pdf │ ├── README.md │ ├── pr │ ├── and_gate.qsf │ ├── and_gate.sv │ ├── counter.qsf │ ├── counter.sv │ ├── fsm.qsf │ ├── fsm.sv │ ├── pr_sim.qpf │ ├── pr_wrapper.sv │ ├── top.qsf │ └── top.sv │ └── pr_sim │ ├── and_gate.qsf │ ├── and_gate.sv │ ├── counter.qsf │ ├── counter.sv │ ├── freeze_logic_controller.sv │ ├── fsm.qsf │ ├── fsm.sv │ ├── gen_pr_models.do │ ├── pr_sim.qpf │ ├── pr_sim.qsf │ ├── pr_sim_wrapper.sv │ ├── pr_wrapper.sv │ ├── run_pr_sim.do │ ├── run_pr_sim_only.do │ ├── top.qsf │ ├── top.sv │ ├── top_sim.sv │ ├── top_tb.sv │ └── wave.do └── verification ├── README.md └── vkits ├── README.md ├── altr_cmn ├── altr_cmn_macros.sv ├── altr_verbosity_uvm_pkg.sv └── sim_reporting.sv ├── avmm ├── avmm_agent.sv ├── avmm_command_seq_item.sv ├── avmm_driver.sv ├── avmm_monitor.sv ├── avmm_pkg.sv ├── avmm_response_seq_item.sv ├── avmm_sequence_lib.sv └── avmm_sequencer.sv ├── config_stream_endpoint_pr ├── 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