├── rohd_devtools_extension ├── devtools_options.yaml ├── web │ ├── favicon.png │ ├── icons │ │ ├── Icon-192.png │ │ ├── Icon-512.png │ │ ├── Icon-maskable-192.png │ │ └── Icon-maskable-512.png │ ├── manifest.json │ └── index.html ├── lib │ ├── rohd_devtools │ │ ├── view │ │ │ ├── view.dart │ │ │ └── rohd_devtools_page.dart │ │ ├── rohd_devtools.dart │ │ ├── cubit │ │ │ ├── tree_search_term_cubit.dart │ │ │ ├── signal_search_term_cubit.dart │ │ │ ├── selected_module_cubit.dart │ │ │ ├── selected_module_state.dart │ │ │ ├── rohd_service_state.dart │ │ │ └── rohd_service_cubit.dart │ │ ├── services │ │ │ ├── signal_service.dart │ │ │ └── tree_service.dart │ │ ├── ui │ │ │ ├── signal_table_text_field.dart │ │ │ ├── module_tree_details_navbar.dart │ │ │ └── devtool_appbar.dart │ │ └── models │ │ │ ├── signal_model.dart │ │ │ └── tree_model.dart │ ├── rohd_devtools_observer.dart │ └── main.dart ├── .gitignore ├── pubspec.yaml ├── .metadata ├── README.md ├── .vscode │ └── launch.json ├── test │ └── modules │ │ └── tree_structure │ │ └── rohd_devtools_mocks.dart └── analysis_options.yaml ├── doc ├── tutorials │ ├── chapter_2 │ │ ├── assets │ │ │ └── and_gate.png │ │ ├── answers │ │ │ ├── exercise_3.dart │ │ │ ├── exercise_1.dart │ │ │ └── exercise_2.dart │ │ ├── g_constant.dart │ │ ├── c_logic_gate_part_1.dart │ │ ├── a_logic.dart │ │ ├── e_logic_gate_part_2.dart │ │ ├── d_assignment_operator.dart │ │ ├── f_logic_gate_part_3.dart │ │ └── b_logic_width.dart │ ├── chapter_8 │ │ ├── assets │ │ │ ├── oven_fsm.png │ │ │ ├── fsm_mermaid_output.png │ │ │ └── 4x4-bits-Carry-Save-Multiplier-2.png │ │ ├── 00_abstraction.md │ │ ├── answers │ │ │ └── exercise_3_pipeline.dart │ │ └── counter_interface.dart │ ├── chapter_9 │ │ ├── assets │ │ │ └── ROHD_VF_Design.png │ │ └── rohd_vf_example │ │ │ ├── pubspec.yaml │ │ │ ├── analysis_options.yaml │ │ │ └── lib │ │ │ └── counter.dart │ ├── chapter_1 │ │ └── assets │ │ │ ├── local_setup │ │ │ ├── step_1.png │ │ │ ├── step_2.png │ │ │ └── dart_package_install.png │ │ │ ├── codespaces_setup │ │ │ ├── step_1.png │ │ │ ├── step_2.png │ │ │ ├── step_3.png │ │ │ ├── step_4.png │ │ │ ├── step_5.png │ │ │ └── step_6.png │ │ │ └── docker_setup │ │ │ ├── clone_in_volume.png │ │ │ └── vscode_extension.png │ ├── chapter_3 │ │ ├── assets │ │ │ └── full_adder_circuit.png │ │ ├── answers │ │ │ ├── helper.dart │ │ │ ├── exercise.dart │ │ │ └── exercise_sv.dart │ │ └── helper.dart │ ├── chapter_4 │ │ ├── assets │ │ │ ├── ripple_carry_adder.png │ │ │ └── ripple-carry-adder-eg.png │ │ ├── answers │ │ │ ├── exercise_2.dart │ │ │ └── exercise_1.dart │ │ └── basic_generation.dart │ ├── chapter_6 │ │ ├── case.dart │ │ ├── if_block.dart │ │ └── answers │ │ │ └── exercise_1_case_answer.dart │ └── chapter_5 │ │ └── answers │ │ ├── n_bit_subtractor.dart │ │ ├── full_subtractor.dart │ │ └── full_adder.dart └── user_guide │ ├── _docs │ ├── B01-contributing.md │ ├── A03-constant.md │ ├── A09-sequentials.md │ ├── A17-external-modules.md │ ├── A18-unit-testing.md │ ├── A06-shift-operations.md │ ├── A12-non-synthesizable-signal.md │ ├── A04-assignment.md │ ├── A07-bus-ranges-and-swizzling.md │ ├── A05-logic-math-compare.md │ ├── A16-simulator.md │ └── A14-pipelines.md │ └── _get-started │ └── 03-development-recommendations.md ├── .vscode └── extensions.json ├── lib ├── src │ ├── interfaces │ │ └── interfaces.dart │ ├── exceptions │ │ ├── sim_compare │ │ │ ├── sim_compare_exceptions.dart │ │ │ └── non_supported_type_exception.dart │ │ ├── interface │ │ │ ├── interface_exceptions.dart │ │ │ ├── interface_name_exception.dart │ │ │ └── interface_type_exception.dart │ │ ├── name │ │ │ ├── name_exceptions.dart │ │ │ ├── null_reserved_name_exception.dart │ │ │ ├── empty_reserved_name_exception.dart │ │ │ ├── invalid_portname_exceptions.dart │ │ │ ├── invalid_reserved_name_exception.dart │ │ │ └── unavailable_reserved_name_exception.dart │ │ ├── conditionals │ │ │ ├── conditional_exceptions.dart │ │ │ ├── invalid_conditional_exception.dart │ │ │ ├── uninitialized_signal_exception.dart │ │ │ ├── signal_redriven_exception.dart │ │ │ ├── mapped_signal_already_assigned_exception.dart │ │ │ └── write_after_read_exception.dart │ │ ├── logic_value │ │ │ ├── logic_value_exceptions.dart │ │ │ ├── logic_value_construction_exception.dart │ │ │ ├── logic_value_conversion_exception.dart │ │ │ ├── invalid_truncation_exception.dart │ │ │ ├── value_width_mismatch_exception.dart │ │ │ ├── invalid_value_operation_exception.dart │ │ │ └── invalid_random_logic_value_exception.dart │ │ ├── logic │ │ │ ├── logic_exceptions.dart │ │ │ ├── put_exception.dart │ │ │ ├── logic_construction_exception.dart │ │ │ ├── invalid_multiplier_exception.dart │ │ │ ├── self_connecting_logic_exception.dart │ │ │ ├── unassignable_exception.dart │ │ │ └── signal_width_mismatch_exception.dart │ │ ├── module │ │ │ ├── module_exceptions.dart │ │ │ ├── port_does_not_exist_exception.dart │ │ │ ├── invalid_hierarchy_exception.dart │ │ │ ├── module_not_built_exception.dart │ │ │ ├── port_type_exception.dart │ │ │ └── port_width_mismatch_exception.dart │ │ ├── synth_exception.dart │ │ ├── simulator_exception.dart │ │ ├── rohd_exception.dart │ │ ├── exceptions.dart │ │ ├── illegal_configuration_exception.dart │ │ └── unsupported_type_exception.dart │ ├── collections │ │ └── collections.dart │ ├── synthesizers │ │ ├── systemverilog │ │ │ └── systemverilog.dart │ │ ├── utilities │ │ │ └── utilities.dart │ │ ├── synthesizers.dart │ │ ├── synth_file_contents.dart │ │ └── synthesizer.dart │ ├── modules │ │ ├── modules.dart │ │ ├── conditionals │ │ │ ├── conditionals.dart │ │ │ └── ssa.dart │ │ ├── passthrough.dart │ │ └── clkgen.dart │ ├── utilities │ │ ├── config.dart │ │ ├── timestamper.dart │ │ ├── web.dart │ │ ├── sv_cleaner.dart │ │ └── index_utilities.dart │ ├── values │ │ └── values.dart │ ├── signals │ │ ├── signals.dart │ │ ├── logic_value_changed.dart │ │ ├── port.dart │ │ └── const.dart │ ├── selection.dart │ └── external.dart └── rohd.dart ├── extension └── devtools │ └── config.yaml ├── .markdownlint-cli2.jsonc ├── tool ├── gh_actions │ ├── install_pana.sh │ ├── analyze_source.sh │ ├── install_dependencies.sh │ ├── install_iverilog.sh │ ├── pana_source.sh │ ├── devtool │ │ ├── run_devtool_test.sh │ │ └── build_web.sh │ ├── run_tests.sh │ ├── verify_formatting.sh │ ├── install_node.sh │ ├── check_tmp_test.sh │ └── generate_documentation.sh ├── gh_codespaces │ ├── run_setup.sh │ └── install_dart.sh └── generate_coverage.sh ├── SECURITY.md ├── test ├── logic_test.dart ├── sv_param_passthrough.sv ├── timestamper_test.dart ├── multimodule5_test.dart ├── example_test.dart ├── comb_sensitivity_search_test.dart ├── example_icarus_waves.vcd ├── long_chain_test.dart ├── external_test.dart ├── trace_bounce_test.dart ├── vcd_parser_test.dart ├── example_verilator_waves.vcd ├── previous_value_test.dart ├── arithmetic_shift_right_test.dart ├── multimodule3_test.dart ├── traverseable_collection_test.dart ├── duplicate_detection_set_test.dart ├── multimodule4_test.dart ├── shuffle_test.dart └── benchmark_test.dart ├── .gitignore ├── .github ├── ISSUE_TEMPLATE │ ├── config.yml │ ├── feature_request.yml │ └── bug_report.yml ├── configs │ └── mlc_config.json ├── PULL_REQUEST_TEMPLATE.md └── workflows │ └── build_devtool.yml ├── .pubignore ├── pubspec.yaml ├── .devcontainer └── devcontainer.json ├── benchmark ├── README.md ├── benchmark.dart ├── logic_value_of_benchmark.dart ├── many_submodules_benchmark.dart ├── byte_enable_benchmark.dart ├── wave_dump_benchmark.dart └── comb_guard_fanout_benchmark.dart └── LICENSE /rohd_devtools_extension/devtools_options.yaml: -------------------------------------------------------------------------------- 1 | extensions: 2 | - rohd: true -------------------------------------------------------------------------------- /rohd_devtools_extension/web/favicon.png: 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/.vscode/extensions.json: -------------------------------------------------------------------------------- 1 | { 2 | "recommendations": [ 3 | "Dart-Code.dart-code", 4 | "ms-vscode-remote.remote-containers", 5 | "DavidAnson.vscode-markdownlint" 6 | ] 7 | } 8 | -------------------------------------------------------------------------------- /lib/src/interfaces/interfaces.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'interface.dart'; 5 | export 'pair_interface.dart'; 6 | -------------------------------------------------------------------------------- /lib/src/exceptions/sim_compare/sim_compare_exceptions.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'non_supported_type_exception.dart'; 5 | -------------------------------------------------------------------------------- /extension/devtools/config.yaml: -------------------------------------------------------------------------------- 1 | name: rohd 2 | issueTracker: https://github.com/intel/rohd/issues 3 | version: 0.0.1 4 | materialIconCodePoint: '0xe1c5' 5 | requiresConnection: true # optional field - defaults to true -------------------------------------------------------------------------------- /.markdownlint-cli2.jsonc: -------------------------------------------------------------------------------- 1 | { 2 | "config": { 3 | "default": true, 4 | "MD013": false, 5 | "MD041": false, 6 | "MD033": false 7 | }, 8 | 9 | "ignores": [ 10 | "doc/api/" 11 | ] 12 | } 13 | -------------------------------------------------------------------------------- /lib/src/collections/collections.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'duplicate_detection_set.dart'; 5 | export 'traverseable_collection.dart'; 6 | -------------------------------------------------------------------------------- /lib/src/exceptions/interface/interface_exceptions.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'interface_name_exception.dart'; 5 | export 'interface_type_exception.dart'; 6 | -------------------------------------------------------------------------------- /lib/src/synthesizers/systemverilog/systemverilog.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'systemverilog_mixins.dart'; 5 | export 'systemverilog_synthesizer.dart'; 6 | -------------------------------------------------------------------------------- /lib/src/synthesizers/utilities/utilities.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'synth_assignment.dart'; 5 | export 'synth_logic.dart'; 6 | export 'synth_module_definition.dart'; 7 | export 'synth_sub_module_instantiation.dart'; 8 | -------------------------------------------------------------------------------- /lib/src/modules/modules.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'bus.dart'; 5 | export 'clkgen.dart'; 6 | export 'conditionals/conditionals.dart'; 7 | export 'gates.dart'; 8 | export 'pipeline.dart'; 9 | export 'tristate.dart'; 10 | -------------------------------------------------------------------------------- /lib/src/synthesizers/synthesizers.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'synth_builder.dart'; 5 | export 'synth_file_contents.dart'; 6 | export 'synthesis_result.dart'; 7 | export 'synthesizer.dart'; 8 | export 'systemverilog/systemverilog.dart'; 9 | -------------------------------------------------------------------------------- /tool/gh_actions/install_pana.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2025 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # install_pana.sh 7 | # GitHub Actions step: Install pana dart analysis. 8 | # 9 | # 2025 September 26 10 | # Author: Desmond A. Kirkpatrick 11 | 12 | dart pub global activate pana 13 | -------------------------------------------------------------------------------- /tool/gh_actions/analyze_source.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2022 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # analyze_source.sh 7 | # GitHub Actions step: Analyze project source. 8 | # 9 | # 2022 October 9 10 | # Author: Chykon 11 | 12 | set -euo pipefail 13 | 14 | dart analyze --fatal-infos 15 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/view/view.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // view.dart 5 | // 6 | // 2025 January 28 7 | // Author: Roberto Torres 8 | 9 | export 'rohd_devtools_page.dart'; 10 | export 'tree_structure_page.dart'; 11 | -------------------------------------------------------------------------------- /tool/gh_actions/install_dependencies.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2022-2023 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # install_dependencies.sh 7 | # GitHub Actions step: Install project dependencies. 8 | # 9 | # 2022 October 7 10 | # Author: Chykon 11 | 12 | set -euo pipefail 13 | 14 | dart pub get 15 | -------------------------------------------------------------------------------- /tool/gh_actions/install_iverilog.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2022-2023 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # install_iverilog.sh 7 | # GitHub Actions step: Install software - Icarus Verilog. 8 | # 9 | # 2022 October 9 10 | # Author: Chykon 11 | 12 | set -euo pipefail 13 | 14 | sudo apt-get install --yes iverilog 15 | -------------------------------------------------------------------------------- /lib/src/exceptions/name/name_exceptions.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'empty_reserved_name_exception.dart'; 5 | export 'invalid_portname_exceptions.dart'; 6 | export 'invalid_reserved_name_exception.dart'; 7 | export 'null_reserved_name_exception.dart'; 8 | export 'unavailable_reserved_name_exception.dart'; 9 | -------------------------------------------------------------------------------- /lib/src/modules/conditionals/conditionals.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'case.dart'; 5 | export 'combinational.dart'; 6 | export 'conditional.dart'; 7 | export 'conditional_assign.dart'; 8 | export 'conditional_group.dart'; 9 | export 'flop.dart'; 10 | export 'if.dart'; 11 | export 'sequential.dart'; 12 | -------------------------------------------------------------------------------- /tool/gh_actions/pana_source.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2025 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # pana_source.sh 7 | # GitHub Actions step: execute pana analysis on project source. 8 | # 9 | # 2025 September 26 10 | # Author: Desmond A. Kirkpatrick 11 | 12 | PATH="$PATH":"$HOME/.pub-cache/bin" 13 | 14 | pana --exit-code-threshold 0 . 15 | -------------------------------------------------------------------------------- /lib/src/exceptions/conditionals/conditional_exceptions.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'invalid_conditional_exception.dart'; 5 | export 'mapped_signal_already_assigned_exception.dart'; 6 | export 'signal_redriven_exception.dart'; 7 | export 'uninitialized_signal_exception.dart'; 8 | export 'write_after_read_exception.dart'; 9 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_3/answers/helper.dart: -------------------------------------------------------------------------------- 1 | class FSResult { 2 | int diff = 0; 3 | int borrowOut = 0; 4 | } 5 | 6 | FSResult fsTruthTable(int a, int b, int bIn) { 7 | final res = FSResult(); 8 | 9 | if (a < b + bIn) { 10 | res 11 | ..diff = (a + 2) - b - bIn 12 | ..borrowOut = 1; 13 | } else { 14 | res.diff = a - b - bIn; 15 | } 16 | 17 | return res; 18 | } 19 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic_value/logic_value_exceptions.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'invalid_truncation_exception.dart'; 5 | export 'invalid_value_operation_exception.dart'; 6 | export 'logic_value_construction_exception.dart'; 7 | export 'logic_value_conversion_exception.dart'; 8 | export 'value_width_mismatch_exception.dart'; 9 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/B01-contributing.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Contributing" 3 | permalink: /docs/contributing/ 4 | excerpt: "Contributing" 5 | last_modified_at: 2022-12-06 6 | toc: true 7 | --- 8 | 9 | ROHD is under active development. If you're interested in contributing, have feedback or a question, or found a bug, please see [CONTRIBUTING.md](https://github.com/intel/rohd/blob/main/CONTRIBUTING.md). 10 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic/logic_exceptions.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'invalid_multiplier_exception.dart'; 5 | export 'logic_construction_exception.dart'; 6 | export 'put_exception.dart'; 7 | export 'self_connecting_logic_exception.dart'; 8 | export 'signal_width_mismatch_exception.dart'; 9 | export 'unassignable_exception.dart'; 10 | -------------------------------------------------------------------------------- /tool/gh_actions/devtool/run_devtool_test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2024 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # run_devtool_test.sh 7 | # Run devtool test 8 | # 9 | # 2024 January 03 10 | # Author: Yao Jing Quek 11 | 12 | set -euo pipefail 13 | 14 | cd rohd_devtools_extension 15 | 16 | flutter pub get 17 | 18 | flutter test --platform chrome -------------------------------------------------------------------------------- /lib/src/exceptions/module/module_exceptions.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'invalid_hierarchy_exception.dart'; 5 | export 'module_not_built_exception.dart'; 6 | export 'port_does_not_exist_exception.dart'; 7 | export 'port_rules_violation_exception.dart'; 8 | export 'port_type_exception.dart'; 9 | export 'port_width_mismatch_exception.dart'; 10 | -------------------------------------------------------------------------------- /SECURITY.md: -------------------------------------------------------------------------------- 1 | # Security Policy 2 | 3 | Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation. 4 | 5 | ## Reporting a Vulnerability 6 | 7 | Please report any security vulnerabilities in this project utilizing the guidelines [here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html). 8 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_9/rohd_vf_example/pubspec.yaml: -------------------------------------------------------------------------------- 1 | name: rohd_vf_example 2 | description: A sample command-line application. 3 | version: 1.0.0 4 | # repository: https://github.com/my_org/my_repo 5 | 6 | environment: 7 | sdk: ^3.1.0 8 | 9 | # Add regular dependencies here. 10 | dependencies: 11 | rohd: ^0.4.2 12 | rohd_vf: ^0.4.1 13 | logging: ^1.0.1 14 | 15 | dev_dependencies: 16 | lints: ^2.0.0 17 | test: ^1.21.0 18 | -------------------------------------------------------------------------------- /lib/src/utilities/config.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // config.dart 5 | // A configuration file of ROHD. 6 | // 7 | // 2022 December 1 8 | // Author: Yao Jing Quek 9 | 10 | /// A utility for ROHD configuration file. 11 | class Config { 12 | /// The version of the ROHD framework. 13 | static const String version = '0.6.6'; 14 | } 15 | -------------------------------------------------------------------------------- /tool/gh_actions/run_tests.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2022-2023 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # run_tests.sh 7 | # GitHub Actions step: Run project tests. 8 | # 9 | # 2022 October 10 10 | # Author: Chykon 11 | 12 | set -euo pipefail 13 | 14 | dart test 15 | 16 | # run tests in JS (increase heap size also) 17 | export NODE_OPTIONS="--max-old-space-size=8192" 18 | dart test --platform node -------------------------------------------------------------------------------- /tool/gh_actions/devtool/build_web.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2024 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # build_web.sh 7 | # Build DevTool static web. 8 | # 9 | # 2024 January 03 10 | # Author: Yao Jing Quek 11 | 12 | set -euo pipefail 13 | 14 | cd rohd_devtools_extension 15 | 16 | flutter pub get 17 | 18 | dart run devtools_extensions build_and_copy --source=. --dest=../extension/devtools -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/rohd_devtools.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // rohd_devtools.dart 5 | // 6 | // 2025 January 28 7 | // Author: Roberto Torres 8 | 9 | export 'cubit/rohd_service_cubit.dart'; 10 | export 'cubit/selected_module_cubit.dart'; 11 | export 'cubit/signal_search_term_cubit.dart'; 12 | export 'cubit/tree_search_term_cubit.dart'; 13 | export 'view/view.dart'; 14 | -------------------------------------------------------------------------------- /test/logic_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // logic_test.dart 5 | // Unit tests for `Logic` functionality. 6 | // 7 | // 2025 July 24 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'package:test/test.dart'; 12 | 13 | void main() { 14 | test('packed simple logic returns itself', () { 15 | final logic = Logic(); 16 | expect(logic.packed, logic); 17 | }); 18 | } 19 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # NOTE: Be sure to update .pubignore as well! 2 | 3 | # Files and directories created by pub 4 | .dart_tool/ 5 | .packages 6 | pubspec.lock 7 | 8 | # Conventional directory for build outputs 9 | build/ 10 | 11 | # Directory created by dartdoc 12 | doc/api/ 13 | 14 | # Other stuff 15 | tmp_test/ 16 | *.sv 17 | *.vcd 18 | *_fsm.md 19 | .vscode/* 20 | ./devtools_options.yaml 21 | 22 | # Exceptions 23 | !.vscode/extensions.json 24 | !test/example_icarus_waves.vcd 25 | !test/example_verilator_waves.vcd 26 | !test/sv_param_passthrough.sv -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/config.yml: -------------------------------------------------------------------------------- 1 | blank_issues_enabled: true 2 | 3 | contact_links: 4 | - name: ROHD Discussions 5 | url: https://github.com/intel/rohd/discussions 6 | about: Ask questions - get answers. 7 | 8 | - name: ROHD Discord 9 | url: https://discord.com/invite/jubxF84yGw 10 | about: Instant communication... if someone is online. 11 | 12 | - name: ROHD Forum 13 | url: https://intel.github.io/rohd-website/forum/rohd-forum/ 14 | about: Public periodic meeting for users and developers to discuss topics related to ROHD. 15 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/cubit/tree_search_term_cubit.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // tree_search_term_cubit.dart 5 | // Cubit for the tree search term. 6 | // 7 | // 2025 January 28 8 | // Author: Roberto Torres 9 | 10 | import 'package:flutter_bloc/flutter_bloc.dart'; 11 | 12 | class TreeSearchTermCubit extends Cubit { 13 | TreeSearchTermCubit() : super(null); 14 | 15 | void setTerm(String term) { 16 | emit(term); 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /tool/gh_actions/verify_formatting.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2022-2023 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # verify_formatting.sh 7 | # GitHub Actions step: Verify project formatting. 8 | # 9 | # 2022 October 9 10 | # Author: Chykon 11 | 12 | set -euo pipefail 13 | 14 | if dart format --output=none --set-exit-if-changed .; then 15 | echo 'Format check passed!' 16 | else 17 | declare -r exit_code=${?} 18 | echo 'Format check failed: please format your code (use "dart format .")!' 19 | exit ${exit_code} 20 | fi 21 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/cubit/signal_search_term_cubit.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // signal_search_term_cubit.dart 5 | // Cubit for the signal search term. 6 | // 7 | // 2025 January 28 8 | // Author: Roberto Torres 9 | 10 | import 'package:flutter_bloc/flutter_bloc.dart'; 11 | 12 | class SignalSearchTermCubit extends Cubit { 13 | SignalSearchTermCubit() : super(null); 14 | 15 | void setTerm(String term) { 16 | emit(term); 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /test/sv_param_passthrough.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // sv_param_passthrough.sv 5 | // Module useful for testing parameter passthrough 6 | // 7 | // 2024 June 25 8 | // Author: Max Korbel 9 | 10 | module leaf_node #( 11 | parameter int A = 0, 12 | parameter int B = 0, 13 | parameter bit[3:0] C = 0, 14 | parameter logic D = 1'b0 15 | ) ( 16 | input logic [7:0] a, 17 | output logic [7:0] b 18 | ); 19 | 20 | assign b = a + B; 21 | 22 | endmodule : leaf_node 23 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/answers/exercise_3.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // exercise_3.dart 5 | // Answer to exercise 3. 6 | // 7 | // 2023 February 14 8 | // Author: Yao Jing Quek 9 | 10 | // ignore_for_file: avoid_print 11 | 12 | import 'package:rohd/rohd.dart'; 13 | 14 | Future main() async { 15 | final a = Const(10, width: 4); // 10 in binary is 1010 16 | final b = Logic(name: 'copy_of_const', width: a.width); 17 | 18 | b <= a; 19 | 20 | print(b.value.toInt()); 21 | } 22 | -------------------------------------------------------------------------------- /tool/gh_codespaces/run_setup.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2023 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # run_setup.sh 7 | # GitHub Codespaces setup: Setting up the development environment. 8 | # 9 | # 2023 February 5 10 | # Author: Chykon 11 | 12 | set -euo pipefail 13 | 14 | # Install Dart SDK. 15 | tool/gh_codespaces/install_dart.sh 16 | 17 | # Install Pub dependencies. 18 | tool/gh_actions/install_dependencies.sh 19 | 20 | # Install Icarus Verilog. 21 | tool/gh_actions/install_iverilog.sh 22 | 23 | # Install Node 24 | tool/gh_actions/install_node.sh -------------------------------------------------------------------------------- /lib/src/exceptions/synth_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // synth_exception.dart 5 | // Definition for exception when an error occurs in the Synthesizer stack. 6 | // 7 | // 2025 June 24 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An [Exception] thrown when an error occurs in the simulator. 13 | class SynthException extends RohdException { 14 | /// Constructs a new [Exception] for when an error occurs in the [Synthesizer] 15 | /// stack. 16 | SynthException(super.message); 17 | } 18 | -------------------------------------------------------------------------------- /lib/src/exceptions/module/port_does_not_exist_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // port_does_not_exist_exception.dart 5 | // Definition for exception when a port is not present. 6 | // 7 | // 2023 December 26 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An [Exception] thrown when a port does not exist. 13 | class PortDoesNotExistException extends RohdException { 14 | /// Constructs a new [Exception] for when a port is not present. 15 | PortDoesNotExistException(super.message); 16 | } 17 | -------------------------------------------------------------------------------- /.pubignore: -------------------------------------------------------------------------------- 1 | # NOTE: Everything (probably) from .gitignore should be in here! 2 | 3 | # Files and directories created by pub 4 | .dart_tool/ 5 | .packages 6 | pubspec.lock 7 | 8 | # Conventional directory for build outputs 9 | build/ 10 | 11 | # Directory created by dartdoc 12 | doc/api/ 13 | 14 | # Other stuff 15 | tmp_test/ 16 | *.sv 17 | *.vcd 18 | *_fsm.md 19 | .vscode/* 20 | ./devtools_options.yaml 21 | 22 | # Exceptions 23 | !.vscode/extensions.json 24 | !test/example_icarus_waves.vcd 25 | !test/example_verilator_waves.vcd 26 | !test/sv_param_passthrough.sv 27 | 28 | # Release with devtools build 29 | !extension/devtools/build 30 | -------------------------------------------------------------------------------- /pubspec.yaml: -------------------------------------------------------------------------------- 1 | name: rohd 2 | version: 0.6.6 3 | description: The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware. 4 | homepage: https://intel.github.io/rohd-website 5 | repository: https://github.com/intel/rohd 6 | issue_tracker: https://github.com/intel/rohd/issues 7 | documentation: https://intel.github.io/rohd-website/docs/sample-example/ 8 | 9 | environment: 10 | sdk: '>=3.0.0 <4.0.0' 11 | 12 | dependencies: 13 | collection: ^1.15.0 14 | logging: ^1.0.1 15 | meta: ^1.9.0 16 | test: ^1.17.3 17 | 18 | dev_dependencies: 19 | benchmark_harness: ^2.2.0 20 | yaml: ^3.1.1 21 | -------------------------------------------------------------------------------- /lib/rohd.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export 'src/exceptions/exceptions.dart'; 5 | export 'src/external.dart'; 6 | export 'src/finite_state_machine.dart'; 7 | export 'src/interfaces/interfaces.dart'; 8 | export 'src/module.dart'; 9 | export 'src/modules/modules.dart'; 10 | export 'src/selection.dart'; 11 | export 'src/signals/signals.dart'; 12 | export 'src/simulator.dart'; 13 | export 'src/swizzle.dart'; 14 | export 'src/synthesizers/synthesizers.dart'; 15 | export 'src/utilities/naming.dart'; 16 | export 'src/values/values.dart'; 17 | export 'src/wave_dumper.dart'; 18 | -------------------------------------------------------------------------------- /.github/configs/mlc_config.json: -------------------------------------------------------------------------------- 1 | { 2 | "ignorePatterns": [ 3 | { 4 | "pattern": "^https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html$" 5 | }, 6 | { 7 | "pattern":"^https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html$" 8 | }, 9 | { 10 | "pattern":"^https://stackoverflow.com" 11 | }, 12 | { 13 | "pattern":"^https://github.com" 14 | }, 15 | { 16 | "pattern":"^https://www.nandland.com" 17 | }, 18 | { 19 | "pattern":"^https://.*\\.fandom\\.com" 20 | } 21 | ] 22 | } 23 | -------------------------------------------------------------------------------- /lib/src/exceptions/module/invalid_hierarchy_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // invalid_hierarchy_exception.dart 5 | // Definition for exception when an invalid hierarchy is detected. 6 | // 7 | // 2024 April 12 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An [Exception] thrown when a constructed hierarchy is illegal. 13 | class InvalidHierarchyException extends RohdException { 14 | /// Constructs a new [Exception] for when a constructed hierarchy is illegal. 15 | InvalidHierarchyException(super.message); 16 | } 17 | -------------------------------------------------------------------------------- /lib/src/exceptions/simulator_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // simulator_exception.dart 5 | // Definition for exception when an error occurs in the simulator. 6 | // 7 | // 2024 June 11 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An [Exception] thrown when an error occurs in the simulator. 13 | class SimulatorException extends RohdException { 14 | /// Constructs a new [Exception] for when an error occurs in the simulator 15 | /// with [message] explaining why. 16 | SimulatorException(super.message); 17 | } 18 | -------------------------------------------------------------------------------- /lib/src/values/values.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2022 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | library; 5 | 6 | import 'dart:collection'; 7 | import 'dart:math' as math; 8 | 9 | import 'package:meta/meta.dart'; 10 | import 'package:rohd/rohd.dart'; 11 | import 'package:rohd/src/exceptions/logic_value/invalid_random_logic_value_exception.dart'; 12 | import 'package:rohd/src/utilities/index_utilities.dart'; 13 | import 'package:rohd/src/utilities/web.dart'; 14 | 15 | part 'logic_value.dart'; 16 | part 'small_logic_value.dart'; 17 | part 'big_logic_value.dart'; 18 | part 'filled_logic_value.dart'; 19 | part 'random_logic_value.dart'; 20 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools_observer.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // rohd_devtools_observer.dart 5 | // Bloc observer for the app. 6 | // 7 | // 2025 January 28 8 | // Author: Roberto Torres 9 | 10 | import 'package:flutter_bloc/flutter_bloc.dart'; 11 | 12 | /// [BlocObserver] observe all state changes in the application. 13 | class RohdDevToolsObserver extends BlocObserver { 14 | const RohdDevToolsObserver(); 15 | 16 | @override 17 | void onChange(BlocBase bloc, Change change) { 18 | super.onChange(bloc, change); 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /lib/src/exceptions/rohd_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // rohd_exception.dart 5 | // Base class for all ROHD exceptions 6 | // 7 | // 2022 December 30 8 | // Author: Max Korbel 9 | 10 | /// A base type of exception that ROHD-specific exceptions inherit from. 11 | abstract class RohdException implements Exception { 12 | /// A description of what this exception means. 13 | final String message; 14 | 15 | /// Creates a new exception with description [message]. 16 | RohdException(this.message); 17 | 18 | @override 19 | String toString() => message; 20 | } 21 | -------------------------------------------------------------------------------- /lib/src/exceptions/exceptions.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | export './conditionals/conditional_exceptions.dart'; 5 | export './interface/interface_exceptions.dart'; 6 | export './logic/logic_exceptions.dart'; 7 | export './logic_value/logic_value_exceptions.dart'; 8 | export './module/module_exceptions.dart'; 9 | export './name/name_exceptions.dart'; 10 | export './sim_compare/sim_compare_exceptions.dart'; 11 | export 'illegal_configuration_exception.dart'; 12 | export 'rohd_exception.dart'; 13 | export 'simulator_exception.dart'; 14 | export 'synth_exception.dart'; 15 | export 'unsupported_type_exception.dart'; 16 | -------------------------------------------------------------------------------- /test/timestamper_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // timestamper_test.dart 5 | // Tests for Timestamper. 6 | // 7 | // 2023 February 18 8 | // Author: Chykon 9 | 10 | import 'package:rohd/src/utilities/timestamper.dart'; 11 | import 'package:test/test.dart'; 12 | 13 | void main() { 14 | group('Timestamper', () { 15 | test('format must be correct', () { 16 | final regexp = RegExp( 17 | r'^\d{4}-\d{2}-\d{2} \d{2}:\d{2}:\d{2}\.\d{3} [+-]\d{2}:\d{2}$'); 18 | 19 | final timestamp = Timestamper.stamp(); 20 | 21 | expect(regexp.hasMatch(timestamp), equals(true)); 22 | }); 23 | }); 24 | } 25 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/g_constant.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // g_constant.dart 5 | // Creation of constant Logic in rohd. 6 | // 7 | // 2023 February 20 8 | // Author: Yao Jing Quek 9 | 10 | // ignore_for_file: avoid_print 11 | 12 | import 'package:rohd/rohd.dart'; 13 | import 'helper.dart'; 14 | 15 | void main() async { 16 | final a = Const(5, width: 16); 17 | // Instantiate Module and display system verilog 18 | final constantLogic = ConstantValue(a); 19 | await displaySystemVerilog(constantLogic); 20 | 21 | print('\nValue of a is: '); 22 | print(constantLogic.a.value.toInt()); 23 | } 24 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic/put_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // put_exception.dart 5 | // An exception that thrown when a signal failes to `put`. 6 | // 7 | // 2023 January 5 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that thrown when a [Logic] signal fails to `put`. 13 | class PutException extends RohdException { 14 | /// Creates an exception for when a `put` fails on a `Logic` with [context] as 15 | /// to where the 16 | PutException(String context, String message) 17 | : super('Failed to put value on signal ($context): $message'); 18 | } 19 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/c_logic_gate_part_1.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // c_logic_gate_part_1.dart 5 | // Initialize of logic gate Logic. 6 | // 7 | // 2023 February 20 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'helper.dart'; 12 | 13 | void main() async { 14 | // Create a logic for input and output 15 | final a = Logic(name: 'a'); 16 | final b = Logic(name: 'b'); 17 | final c = Logic(name: 'c'); 18 | 19 | // Instantiate Module and display system verilog 20 | final basicLogic = Part1LogicGate(a, b, c); 21 | await displaySystemVerilog(basicLogic); 22 | } 23 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/answers/exercise_1.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // exercise_1.dart 5 | // Answer to exercise 1. 6 | // 7 | // 2023 February 14 8 | // Author: Yao Jing Quek 9 | 10 | // ignore_for_file: avoid_print 11 | 12 | import 'package:rohd/rohd.dart'; 13 | 14 | Future main() async { 15 | final threeBitBus = Logic(name: 'threeBitBus'); 16 | print('answer 1: $threeBitBus'); 17 | 18 | // that you have created the correct signal? 19 | print('answer 2: Yes, threeBitBus Logic property output ' 20 | 'the name as threeBitBus. Check threeBitBus.name to see a more simple ' 21 | 'answer'); 22 | } 23 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A03-constant.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Constants" 3 | permalink: /docs/constant/ 4 | excerpt: "Constants" 5 | last_modified_at: 2022-12-06 6 | toc: true 7 | --- 8 | 9 | Constants can often be inferred by ROHD automatically, but can also be explicitly defined using [`Const`](https://intel.github.io/rohd/rohd/Const-class.html), which extends `Logic`. 10 | 11 | ```dart 12 | // a 16 bit constant with value 5 13 | var x = Const(5, width:16); 14 | ``` 15 | 16 | There is a convenience function for converting binary to an integer: 17 | 18 | ```dart 19 | // this is equvialent to and shorter than int.parse('010101', radix:2) 20 | // you can put underscores to help with readability, they are ignored 21 | bin('01_0101') 22 | ``` 23 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A09-sequentials.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Sequentials" 3 | permalink: /docs/sequentials/ 4 | excerpt: "Sequentials" 5 | last_modified_at: 2022-12-06 6 | toc: true 7 | --- 8 | 9 | ROHD has a basic [`FlipFlop`](https://intel.github.io/rohd/rohd/FlipFlop-class.html) module that can be used as a flip flop. You can use the shorthand [`flop`](https://intel.github.io/rohd/rohd/flop.html) to construct a `FlipFlop`. For more complex sequential logic, use the `Sequential` block described in the Conditionals section. 10 | 11 | Dart doesn't have a notion of certain signals being "clocks" vs. "not clocks". You can use any signal as a clock input to sequential logic, and have as many clocks of as many frequencies as you want. 12 | -------------------------------------------------------------------------------- /lib/src/exceptions/illegal_configuration_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // illegal_configuration_exception.dart 5 | // An exception thrown when something is configured in an illegal way. 6 | // 7 | // 2023 June 13 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/src/exceptions/exceptions.dart'; 11 | 12 | /// An exception that is thrown when somethins is configured in an illegal way. 13 | class IllegalConfigurationException extends RohdException { 14 | /// Creates a new [IllegalConfigurationException] with a [message] explaining 15 | /// what was illegal about it. 16 | IllegalConfigurationException(super.message); 17 | } 18 | -------------------------------------------------------------------------------- /lib/src/exceptions/conditionals/invalid_conditional_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // invalid_conditional_exception.dart 5 | // An exception thrown when a conditional is built in an invalid way. 6 | // 7 | // 2023 June 13 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that is thrown when a [Conditional] has been constructed in 13 | /// an invalid way. 14 | class InvalidConditionalException extends RohdException { 15 | /// Creates a new [InvalidConditionalException] with a [message] explaining 16 | /// why the conditional was invalid. 17 | InvalidConditionalException(super.message); 18 | } 19 | -------------------------------------------------------------------------------- /.devcontainer/devcontainer.json: -------------------------------------------------------------------------------- 1 | // For format details, see https://aka.ms/devcontainer.json. For config options, see the 2 | // README at: https://github.com/devcontainers/templates/tree/main/src/ubuntu 3 | 4 | { 5 | "image": "mcr.microsoft.com/devcontainers/base:ubuntu-22.04", 6 | 7 | "updateContentCommand": "tool/gh_codespaces/run_setup.sh", 8 | 9 | "customizations": { 10 | "codespaces": { 11 | "openFiles": [ 12 | "example/example.dart", 13 | "README.md", 14 | "CONTRIBUTING.md", 15 | "CODE_OF_CONDUCT.md" 16 | ] 17 | }, 18 | "vscode": { 19 | "extensions": [ 20 | "Dart-Code.dart-code", 21 | "DavidAnson.vscode-markdownlint" 22 | ] 23 | } 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /lib/src/exceptions/interface/interface_name_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // interface_name_exception.dart 5 | // Definition for an exception thrown when an interface has a naming issue. 6 | // 7 | // 2023 June 7 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/src/exceptions/rohd_exception.dart'; 11 | 12 | /// An [Exception] thrown when an interface has an invalid name. 13 | class InterfaceNameException extends RohdException { 14 | /// Constructs a new [Exception] for when an interface has an invalid name. 15 | InterfaceNameException(String name, String reason) 16 | : super('Interface name "$name" is invalid: $reason'); 17 | } 18 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic_value/logic_value_construction_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // logic_value_construction_exception.dart 5 | // An exception that is thrown when a signal fails to `put`. 6 | // 7 | // 2023 May 1 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that thrown when a [LogicValue] cannot be properly constructed. 13 | class LogicValueConstructionException extends RohdException { 14 | /// Creates an exception for when a construction of a `LogicValue` fails. 15 | LogicValueConstructionException(String message) 16 | : super('Failed to construct `LogicValue`: $message'); 17 | } 18 | -------------------------------------------------------------------------------- /lib/src/signals/signals.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | 4 | library; 5 | 6 | import 'dart:async'; 7 | import 'dart:math'; 8 | 9 | import 'package:collection/collection.dart'; 10 | import 'package:meta/meta.dart'; 11 | import 'package:rohd/rohd.dart'; 12 | import 'package:rohd/src/utilities/index_utilities.dart'; 13 | import 'package:rohd/src/utilities/sanitizer.dart'; 14 | import 'package:rohd/src/utilities/synchronous_propagator.dart'; 15 | 16 | export 'logic_value_changed.dart'; 17 | export 'port.dart'; 18 | 19 | part 'const.dart'; 20 | part 'logic.dart'; 21 | part 'wire.dart'; 22 | part 'wire_net.dart'; 23 | part 'logic_structure.dart'; 24 | part 'logic_array.dart'; 25 | part 'logic_net.dart'; 26 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/a_logic.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // a_logic.dart 5 | // Creation of logic in rohd. 6 | // 7 | // 2023 February 20 8 | // Author: Yao Jing Quek 9 | 10 | // ignore_for_file: avoid_print 11 | 12 | import 'package:rohd/rohd.dart'; 13 | import 'helper.dart'; 14 | 15 | void main() async { 16 | // Create a logic 17 | final unnamedSignal = Logic(); 18 | 19 | print(unnamedSignal); 20 | 21 | // 8-bit bus named 'b'. 22 | final bus = Logic(name: 'b', width: 8); 23 | 24 | // Instantiate Module and display system verilog 25 | final basicLogic = LogicInitialization(unnamedSignal, bus); 26 | await displaySystemVerilog(basicLogic); 27 | } 28 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_6/case.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | 3 | Case truthTableCase( 4 | Logic a, Logic b, Logic carryIn, Logic sum, Logic carryOut) => 5 | Case( 6 | [a, b, carryIn].swizzle(), 7 | [ 8 | CaseItem(Const(bin('000')), [sum < 0, carryOut < 0]), 9 | CaseItem(Const(bin('001')), [sum < 1, carryOut < 0]), 10 | CaseItem(Const(bin('010')), [sum < 1, carryOut < 0]), 11 | CaseItem(Const(bin('011')), [sum < 0, carryOut < 1]), 12 | CaseItem(Const(bin('100')), [sum < 1, carryOut < 1]), 13 | CaseItem(Const(bin('101')), [sum < 0, carryOut < 1]), 14 | CaseItem(Const(bin('110')), [sum < 0, carryOut < 1]) 15 | ], 16 | defaultItem: [sum < 1, carryOut < 1], 17 | ); 18 | -------------------------------------------------------------------------------- /.github/PULL_REQUEST_TEMPLATE.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | ## Description & Motivation 4 | 5 | 6 | 7 | ## Related Issue(s) 8 | 9 | 10 | 11 | ## Testing 12 | 13 | 14 | 15 | ## Backwards-compatibility 16 | 17 | > Is this a breaking change that will not be backwards-compatible? If yes, how so? 18 | 19 | 20 | 21 | ## Documentation 22 | 23 | > Does the change require any updates to documentation? If so, where? Are they included? 24 | 25 | 26 | -------------------------------------------------------------------------------- /lib/src/exceptions/interface/interface_type_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // interface_type_exception.dart 5 | // Definition for an exception thrown when an interface has a type issue. 6 | // 7 | // 2023 June 7 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An [Exception] thrown when an interface has an issue with its type. 13 | class InterfaceTypeException extends RohdException { 14 | /// Constructs a new [Exception] for when an interface has an issue with its 15 | /// type. 16 | InterfaceTypeException(Interface interface, String reason) 17 | : super('Interface "$interface" cannot be used in this context: $reason'); 18 | } 19 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic/logic_construction_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // logic_construction_exception.dart 5 | // An exception thrown when a logical signal fails to construct. 6 | // 7 | // 2023 June 1 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that thrown when a [Logic] is connecting to itself. 13 | class LogicConstructionException extends RohdException { 14 | /// A message describing why the construction failed. 15 | final String reason; 16 | 17 | /// Creates an exception when a [Logic] is trying to connect itself. 18 | LogicConstructionException(this.reason) 19 | : super('Failed to construct signal: $reason'); 20 | } 21 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic/invalid_multiplier_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // invalid_multiplier_exception.dart 5 | // An exception that thrown when a signal has an invalid width. 6 | // 7 | // 2023 January 24 8 | // Author: Akshay Wankhede 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that thrown when a [Logic] is replicated with an invalid (<1) 13 | /// multiplier. 14 | class InvalidMultiplierException extends RohdException { 15 | /// Creates an exception when a logic input/output is replicated with an 16 | /// invalid multiplier 17 | InvalidMultiplierException(int multiplier) 18 | : super('A multiplier can not be 0 or negative: $multiplier'); 19 | } 20 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/cubit/selected_module_cubit.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // selected_module_cubit.dart 5 | // Cubit for the selected module. 6 | // 7 | // 2025 January 28 8 | // Author: Roberto Torres 9 | 10 | import 'package:flutter_bloc/flutter_bloc.dart'; 11 | import 'package:equatable/equatable.dart'; 12 | import 'package:rohd_devtools_extension/rohd_devtools/models/tree_model.dart'; 13 | 14 | part 'selected_module_state.dart'; 15 | 16 | class SelectedModuleCubit extends Cubit { 17 | SelectedModuleCubit() : super(SelectedModuleInitial()); 18 | 19 | void setModule(TreeModel module) { 20 | emit(SelectedModuleLoaded(module)); 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic/self_connecting_logic_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // self_connecting_logic_exception.dart 5 | // An exception that is thrown when there is a logical signal connecting to 6 | // itself. 7 | // 8 | // 2023 May 27 9 | // Author: Sanchit Kumar 10 | 11 | import 'package:rohd/rohd.dart'; 12 | 13 | /// An exception that thrown when a [Logic] is connecting to itself. 14 | class SelfConnectingLogicException extends RohdException { 15 | /// Creates an exception when a [Logic] is trying to connect itself. 16 | SelfConnectingLogicException(Logic a, Logic b) 17 | : super('Failed to connect signal "$a" with signal "$b":' 18 | ' Self connecting logic not allowed.'); 19 | } 20 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic_value/logic_value_conversion_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // logic_value_conversion_exception.dart 5 | // An exception that is thrown when a conversion from a [LogicValue] fails 6 | // (such as to a [String]). 7 | // 8 | // 2024 December 26 9 | // Author: Desmond Kirkpatrick 10 | 11 | import 'package:rohd/rohd.dart'; 12 | 13 | /// An exception that is thrown when a [LogicValue] cannot be 14 | /// properly converted. 15 | class LogicValueConversionException extends RohdException { 16 | /// Creates an exception for when conversion of a `LogicValue` fails. 17 | LogicValueConversionException(String message) 18 | : super('Failed to convert `LogicValue`: $message'); 19 | } 20 | -------------------------------------------------------------------------------- /lib/src/exceptions/unsupported_type_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // unsupported_type_exception.dart 5 | // An exception that is thrown when an unsupported type is used. 6 | // 7 | // 2023 September 14 8 | // Author: Max Korbel supportedTypes) 16 | : super('Unsupported type ${value.runtimeType} used ($value).' 17 | ' Supported types are ${supportedTypes.join(',')}'); 18 | } 19 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/e_logic_gate_part_2.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // e_logic_gate_part_2.dart 5 | // Add assignment and mathematical & operator to create Logic Gate. 6 | // 7 | // 2023 February 20 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'helper.dart'; 12 | 13 | void andGate(Logic a, Logic b, Logic c) { 14 | c <= a & b; 15 | } 16 | 17 | void main() async { 18 | // Create a logic for input and output 19 | final a = Logic(name: 'a'); 20 | final b = Logic(name: 'b'); 21 | final c = Logic(name: 'c'); 22 | 23 | // Instantiate Module and display system verilog 24 | final basicLogic = LogicGate(a, b, c, andGate); 25 | await displaySystemVerilog(basicLogic); 26 | } 27 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A17-external-modules.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "External Modules" 3 | permalink: /docs/external-modules/ 4 | excerpt: "External Modules" 5 | last_modified_at: 2022-12-06 6 | toc: true 7 | --- 8 | 9 | ROHD can instantiate external SystemVerilog modules. The [`ExternalSystemVerilogModule`](https://intel.github.io/rohd/rohd/ExternalSystemVerilogModule-class.html) constructor requires the top level SystemVerilog module name. When ROHD generates SystemVerilog for a model containing an `ExternalSystemVerilogModule`, it will instantiate instances of the specified `definitionName`. This is useful for integration related activities. 10 | 11 | The [ROHD Cosim](https://github.com/intel/rohd-cosim) package enables SystemVerilog cosimulation with ROHD by adding cosimulation capabilities to an `ExternalSystemVerilogModule`. 12 | -------------------------------------------------------------------------------- /tool/gh_actions/install_node.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2023 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # install_node.sh 7 | # Install Node 8 | # 9 | # 2023 December 12 10 | # Author: Max Korbel 11 | 12 | 13 | set -euo pipefail 14 | 15 | # based on https://deb.nodesource.com/ to get a recent version of node 16 | 17 | sudo apt-get update && sudo apt-get install -y ca-certificates curl gnupg 18 | curl -fsSL https://deb.nodesource.com/gpgkey/nodesource-repo.gpg.key | sudo gpg --dearmor -o /etc/apt/keyrings/nodesource.gpg 19 | NODE_MAJOR=20 20 | echo "deb [signed-by=/etc/apt/keyrings/nodesource.gpg] https://deb.nodesource.com/node_$NODE_MAJOR.x nodistro main" | sudo tee /etc/apt/sources.list.d/nodesource.list 21 | sudo apt-get update && sudo apt-get install nodejs -y -------------------------------------------------------------------------------- /lib/src/exceptions/logic_value/invalid_truncation_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // invalid_truncation_exception.dart 5 | // An exception that is thrown when invalid truncation takes place. 6 | // 7 | // 2023 May 13 8 | // Author: Sanchit Kumar 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that is thrown when a [LogicValue] operation 13 | /// couldn't be performed due invalid data truncation. 14 | class InvalidTruncationException extends RohdException { 15 | /// Creates an exception when an invalid data truncation occurs 16 | /// from present type to required type. 17 | InvalidTruncationException(String message) 18 | : super("Logical operation couldn't be performed as $message"); 19 | } 20 | -------------------------------------------------------------------------------- /lib/src/synthesizers/synth_file_contents.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // synth_file_contents.dart 5 | // Definition for `SynthFileContents` 6 | // 7 | // 2025 June 24 8 | // Author: Max Korbel 9 | 10 | /// Represents contents of a file. 11 | class SynthFileContents { 12 | /// The name of the content or file. 13 | final String name; 14 | 15 | /// An (optional) description of what this represents. 16 | final String? description; 17 | 18 | /// The actual contents of the file. 19 | final String contents; 20 | 21 | /// Creates a new [SynthFileContents]. 22 | const SynthFileContents( 23 | {required this.name, required this.contents, this.description}); 24 | 25 | @override 26 | String toString() => contents; 27 | } 28 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/cubit/selected_module_state.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // selected_module_state.dart 5 | // States for the selected module cubit. 6 | // 7 | // 2025 January 28 8 | // Author: Roberto Torres 9 | 10 | part of 'selected_module_cubit.dart'; 11 | 12 | abstract class SelectedModuleState extends Equatable { 13 | const SelectedModuleState(); 14 | 15 | @override 16 | List get props => []; 17 | } 18 | 19 | class SelectedModuleInitial extends SelectedModuleState {} 20 | 21 | class SelectedModuleLoaded extends SelectedModuleState { 22 | final TreeModel module; 23 | 24 | const SelectedModuleLoaded(this.module); 25 | 26 | @override 27 | List get props => [module]; 28 | } 29 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic/unassignable_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // unassignable_exception.dart 5 | // An exception that thrown when a signal failes to `put`. 6 | // 7 | // 2024 October 24 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that thrown when a [Logic] signal fails to `put`. 13 | class UnassignableException extends RohdException { 14 | /// Creates an exception for when a [Logic] is marked as unassignable but 15 | /// something tried to assign to it. 16 | UnassignableException(Logic logic, {String? reason}) 17 | : super([ 18 | 'The signal "$logic" has been marked as unassignable.', 19 | if (reason != null) ' $reason' 20 | ].join()); 21 | } 22 | -------------------------------------------------------------------------------- /lib/src/exceptions/name/null_reserved_name_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // null_reserved_name_exception.dart 5 | // An exception that thrown when a reserved name is `null`. 6 | // 7 | // 2022 November 15 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:rohd/src/exceptions/rohd_exception.dart'; 11 | 12 | /// An exception that thrown when a reserved name is `null`. 13 | class NullReservedNameException extends RohdException { 14 | /// Display error [message] on `null` reserved name. 15 | /// 16 | /// Creates a [NullReservedNameException] with an optional error [message]. 17 | NullReservedNameException( 18 | [super.message = 'Reserved Name cannot be null ' 19 | 'if reserved name set to true']); 20 | } 21 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A18-unit-testing.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Unit Testing" 3 | permalink: /docs/unit-test/ 4 | excerpt: "Unit Testing" 5 | last_modified_at: 2024-06-11 6 | toc: true 7 | --- 8 | 9 | Dart has a great unit testing package available on pub.dev: 10 | 11 | The ROHD package has a great set of examples of how to write unit tests for ROHD `Module`s in the `test/` directory. 12 | 13 | Note that when unit testing with ROHD, it is important to reset the `Simulator` with `Simulator.reset()` between tests. For example, you could include something like the following so that the `Simulator` is always reset at the end of each of your tests: 14 | 15 | ```dart 16 | void main() { 17 | tearDown(() async { 18 | await Simulator.reset(); 19 | }); 20 | 21 | test('my first test', () async { 22 | ... 23 | ``` 24 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/services/signal_service.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // signal_service.dart 5 | // Services for signal's logic. 6 | // 7 | // 2024 January 5 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:rohd_devtools_extension/rohd_devtools/models/signal_model.dart'; 11 | 12 | abstract class SignalService { 13 | static List filterSignals( 14 | List signals, 15 | String searchTerm, 16 | ) { 17 | List filteredSignals = []; 18 | 19 | for (var signal in signals) { 20 | if (signal.name.toLowerCase().contains(searchTerm.toLowerCase())) { 21 | filteredSignals.add(signal); 22 | } 23 | } 24 | 25 | return filteredSignals; 26 | } 27 | } 28 | -------------------------------------------------------------------------------- /lib/src/exceptions/name/empty_reserved_name_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // empty_reserved_name_exception.dart 5 | // An exception that thrown when a reserved name is empty string. 6 | // 7 | // 2023 March 14 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:rohd/src/exceptions/rohd_exception.dart'; 11 | 12 | /// An exception that thrown when a reserved name is `null`. 13 | class EmptyReservedNameException extends RohdException { 14 | /// Display error [message] on empty reserved name string. 15 | /// 16 | /// Creates a [EmptyReservedNameException] with an optional error [message]. 17 | EmptyReservedNameException( 18 | [super.message = 'Reserved Name cannot be empty string ' 19 | 'if reserved name set to true']); 20 | } 21 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/d_assignment_operator.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // d_assignment_operator.dart 5 | // Demo how to the assignment operator work. 6 | // 7 | // 2023 February 20 8 | // Author: Yao Jing Quek 9 | 10 | // ignore_for_file: avoid_print 11 | 12 | import 'package:rohd/rohd.dart'; 13 | import 'helper.dart'; 14 | 15 | void assignmentOperator(Logic a, Logic b) { 16 | b <= a; 17 | } 18 | 19 | void main() async { 20 | final a = Logic(name: 'a'); 21 | final b = Logic(name: 'b'); 22 | 23 | // Instantiate Module and display system verilog 24 | final assignOperator = AssignmentOperator(a, b, assignmentOperator); 25 | await displaySystemVerilog(assignOperator); 26 | 27 | a.put(1); 28 | print('The value of b is ${assignOperator.b.value}.'); 29 | } 30 | -------------------------------------------------------------------------------- /lib/src/exceptions/conditionals/uninitialized_signal_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // uninitialized_signal_exception.dart 5 | // An exception thrown when an SSA variable is used before being initialized. 6 | // 7 | // 2023 April 17 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that is thrown when [Combinational.ssa] detects that an SSA 13 | /// signal is being used before it was initialized. 14 | class UninitializedSignalException extends RohdException { 15 | /// Creates a [UninitializedSignalException] for [signalName]. 16 | UninitializedSignalException( 17 | String signalName, 18 | ) : super('Signal "$signalName" is being used before it has been initialized' 19 | ' in this `Combinational.ssa`.'); 20 | } 21 | -------------------------------------------------------------------------------- /lib/src/signals/logic_value_changed.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // logic_value_changed.dart 5 | // Definition of an event when a signal value changes. 6 | // 7 | // 2023 May 26 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// Represents the event of a [Logic] changing value. 13 | class LogicValueChanged { 14 | /// The newly updated value of the [Logic]. 15 | final LogicValue newValue; 16 | 17 | /// The previous value of the [Logic]. 18 | final LogicValue previousValue; 19 | 20 | /// Represents the event of a [Logic] changing value from [previousValue] 21 | /// to [newValue]. 22 | const LogicValueChanged(this.newValue, this.previousValue); 23 | 24 | @override 25 | String toString() => '$previousValue --> $newValue'; 26 | } 27 | -------------------------------------------------------------------------------- /lib/src/synthesizers/synthesizer.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // synthesizer.dart 5 | // Generic definition for something that synthesizes output files 6 | // 7 | // 2021 August 26 8 | // Author: Max Korbel 9 | // 10 | 11 | import 'package:rohd/rohd.dart'; 12 | 13 | /// An object capable of converting a module into some new output format 14 | abstract class Synthesizer { 15 | /// Determines whether [module] needs a separate definition or can just be 16 | /// described in-line. 17 | bool generatesDefinition(Module module); 18 | 19 | /// Synthesizes [module] into a [SynthesisResult], given the mapping provided 20 | /// by [getInstanceTypeOfModule]. 21 | SynthesisResult synthesize( 22 | Module module, String Function(Module module) getInstanceTypeOfModule); 23 | } 24 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic_value/value_width_mismatch_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // value_width_mismatch_exception.dart 5 | // An exception that is thrown when LogicValue of different width are found. 6 | // 7 | // 2023 June 4 8 | // Author: Sanchit Kumar 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that is thrown when [LogicValue]s of different width are found. 13 | class ValueWidthMismatchException extends RohdException { 14 | /// Creates an exception when two [LogicValue] considered for the operation 15 | /// are of different width. 16 | ValueWidthMismatchException(LogicValue a, LogicValue b) 17 | : super('Width mismatch between $a (${a.width}) & $b (${b.width}): ' 18 | 'LogicValues must be of same width for this operation.'); 19 | } 20 | -------------------------------------------------------------------------------- /lib/src/exceptions/name/invalid_portname_exceptions.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // invalid_portname_exceptions.dart 5 | // An exception that thrown when a port or interface name is invalid. 6 | // 7 | // 2023 April 10 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:rohd/src/exceptions/rohd_exception.dart'; 11 | 12 | /// An exception that thrown when a port or interface name is invalid. 13 | class InvalidPortNameException extends RohdException { 14 | /// Display error [message] on invalid reserved name. 15 | /// 16 | /// Creates a [InvalidPortNameException] with an optional error [message]. 17 | InvalidPortNameException(String name) 18 | : super( 19 | 'Invalid name "$name", must be legal SystemVerilog and not collide' 20 | ' with any keywords.'); 21 | } 22 | -------------------------------------------------------------------------------- /rohd_devtools_extension/.gitignore: -------------------------------------------------------------------------------- 1 | # Miscellaneous 2 | *.class 3 | *.log 4 | *.pyc 5 | *.swp 6 | .DS_Store 7 | .atom/ 8 | .buildlog/ 9 | .history 10 | .svn/ 11 | migrate_working_dir/ 12 | 13 | # IntelliJ related 14 | *.iml 15 | *.ipr 16 | *.iws 17 | .idea/ 18 | 19 | # The .vscode folder contains launch configuration and tasks you configure in 20 | # VS Code which you may wish to be included in version control, so this line 21 | # is commented out by default. 22 | #.vscode/ 23 | 24 | # Flutter/Dart/Pub related 25 | **/doc/api/ 26 | **/ios/Flutter/.last_build_id 27 | .dart_tool/ 28 | .flutter-plugins 29 | .flutter-plugins-dependencies 30 | .pub-cache/ 31 | .pub/ 32 | /build/ 33 | 34 | # Symbolication related 35 | app.*.symbols 36 | 37 | # Obfuscation related 38 | app.*.map.json 39 | 40 | # Android Studio will place build artifacts here 41 | /android/app/debug 42 | /android/app/profile 43 | /android/app/release 44 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A06-shift-operations.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Shift Operations" 3 | permalink: /docs/shift-operations/ 4 | excerpt: "Shift Operations" 5 | last_modified_at: 2022-12-06 6 | toc: true 7 | --- 8 | 9 | Dart has [implemented the triple shift](https://github.com/dart-lang/language/blob/master/accepted/2.14/triple-shift-operator/feature-specification.md) operator (``>>>``) in the opposite way as is [implemented in SystemVerilog](https://www.nandland.com/verilog/examples/example-shift-operator-verilog.html). That is to say in Dart, ``>>>`` means *logical* shift right (fill with 0's), and ``>>`` means *arithmetic* shift right (maintaining sign). ROHD keeps consistency with Dart's implementation to avoid introducing confusion within Dart code you write (whether ROHD or plain Dart). 10 | 11 | ```dart 12 | a << b // logical shift left 13 | a >> b // arithmetic shift right 14 | a >>> b // logical shift right 15 | ``` 16 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic_value/invalid_value_operation_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // invalid_value_operation_exception.dart 5 | // An exception that is thrown when a given operation cannot be performed on 6 | // invalid LogicValue 7 | // 8 | // 2023 June 4 9 | // Author: Sanchit Kumar 10 | 11 | import 'package:rohd/rohd.dart'; 12 | 13 | /// An exception that is thrown when a given operation cannot be performed on 14 | /// invalid [LogicValue] 15 | class InvalidValueOperationException extends RohdException { 16 | /// An exception that is thrown when a given operation [op] cannot be 17 | /// performed on invalid input [a] i.e., [LogicValue.isValid] is 18 | /// `false`. 19 | InvalidValueOperationException(LogicValue a, String op) 20 | : super('$op operation cannot be performed on invalid LogicValue $a'); 21 | } 22 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/ui/signal_table_text_field.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // signal_table_text_field.dart 5 | // UI for signal table text field. 6 | // 7 | // 2024 January 5 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:flutter/material.dart'; 11 | 12 | class SignalTableTextField extends StatelessWidget { 13 | final String labelText; 14 | final ValueChanged onChanged; 15 | 16 | const SignalTableTextField({ 17 | super.key, 18 | required this.labelText, 19 | required this.onChanged, 20 | }); 21 | 22 | @override 23 | Widget build(BuildContext context) { 24 | return Expanded( 25 | child: TextField( 26 | onChanged: onChanged, 27 | decoration: InputDecoration( 28 | labelText: labelText, 29 | ), 30 | ), 31 | ); 32 | } 33 | } 34 | -------------------------------------------------------------------------------- /lib/src/exceptions/conditionals/signal_redriven_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // signal_redriven_exception.dart 5 | // An exception that thrown when a signal is 6 | // redriven multiple times. 7 | // 8 | // 2022 November 9 9 | // Author: Yao Jing Quek 10 | 11 | import 'package:rohd/rohd.dart'; 12 | 13 | /// An exception that is thrown when a [Logic] signal is 14 | /// driven multiple times. 15 | class SignalRedrivenException extends RohdException { 16 | /// Displays [signals] that are driven multiple times 17 | /// with default error [message]. 18 | /// 19 | /// Creates a [SignalRedrivenException] with an optional error [message]. 20 | SignalRedrivenException(Iterable signals, 21 | [String message = 'Sequential drove the same signal(s) multiple times: ']) 22 | : super(message + signals.toString()); 23 | } 24 | -------------------------------------------------------------------------------- /lib/src/exceptions/module/module_not_built_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // module_not_build_exception.dart 5 | // Definition for exception when module is not built 6 | // 7 | // 2022 December 30 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An [Exception] thrown when a [Module] was used in a way that required it 13 | /// to be built first, but it was not yet built. 14 | class ModuleNotBuiltException extends RohdException { 15 | /// Constructs a new [Exception] for when a [Module] should have been built 16 | /// before some action was taken. 17 | ModuleNotBuiltException(Module module, [String? additionalInformation]) 18 | : super([ 19 | 'Module $module has not yet built! Must call build() first.', 20 | additionalInformation 21 | ].nonNulls.join(' ')); 22 | } 23 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic_value/invalid_random_logic_value_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // invalid_random_logic_value_exception.dart 5 | // An exception that is thrown when LogicValue generated from Random 6 | // LogicValue is incorrect. 7 | // 8 | // 2023 May 31 9 | // Author: Yao Jing Quek 10 | 11 | import 'dart:math'; 12 | import 'package:rohd/rohd.dart'; 13 | 14 | /// An exception that is thrown when the generation of the random [LogicValue] 15 | /// from [Random] results in errors or bugs. 16 | class InvalidRandomLogicValueException extends RohdException { 17 | /// Creates an exception when the [LogicValue]'s bits generated from [Random] 18 | /// is incorrect. 19 | InvalidRandomLogicValueException(String message) 20 | : super('Generation of the random value is incorrect or errors ' 21 | 'due to $message'); 22 | } 23 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_8/00_abstraction.md: -------------------------------------------------------------------------------- 1 | # Content 2 | 3 | - [ROHD Abstraction](#rohd-abstraction) 4 | - [Interface](#interface) 5 | - [Finite State Machine](#finite-state-machine-fsm) 6 | - [Pipeline](#pipeline) 7 | 8 | ## Learning Outcome 9 | 10 | In this chapter: 11 | 12 | - You will learn how to use ROHD abstraction to speed up the development process. 13 | 14 | ## ROHD Abstraction 15 | 16 | ROHD provides several abstraction layer to accelerate the development work. As of now, ROHD provides several abstraction catalog which listed as below: 17 | 18 | ### [Interface](01_interface.md) 19 | 20 | Interface make it easier to define port connections of a module in a reusable way. 21 | 22 | ### [Finite State Machine (FSM)](02_finite_state_machine.md) 23 | 24 | An easy and fast implementation of Finite State Machine with ROHD API. 25 | 26 | ### [Pipeline](03_pipeline.md) 27 | 28 | Pipeline can be build with ROHD API in a simple and refactorable way. 29 | -------------------------------------------------------------------------------- /rohd_devtools_extension/pubspec.yaml: -------------------------------------------------------------------------------- 1 | name: rohd_devtools_extension 2 | description: "DevTool extension on ROHD." 3 | # The following line prevents the package from being accidentally published to 4 | # pub.dev using `flutter pub publish`. This is preferred for private packages. 5 | publish_to: 'none' # Remove this line if you wish to publish to pub.dev 6 | 7 | version: 1.0.0+1 8 | 9 | environment: 10 | sdk: ^3.6.0 11 | 12 | dependencies: 13 | flutter: 14 | sdk: flutter 15 | cupertino_icons: ^1.0.2 16 | rohd: 17 | path: ../../rohd 18 | # devtools_shared: ^6.0.0 19 | devtools_extensions: ^0.3.0 20 | devtools_app_shared: ^0.3.0 21 | vm_service: ^14.0.0 22 | flutter_simple_treeview: ^3.0.2 23 | equatable: ^2.0.5 24 | flutter_bloc: ^9.0.0 25 | 26 | dev_dependencies: 27 | flutter_test: 28 | sdk: flutter 29 | flutter_lints: ^3.0.1 30 | build_runner: ^2.4.7 31 | mocktail: ^1.0.2 32 | bloc_lint: ^0.1.0 33 | 34 | flutter: 35 | uses-material-design: true 36 | 37 | -------------------------------------------------------------------------------- /benchmark/README.md: -------------------------------------------------------------------------------- 1 | Benchmarking in ROHD 2 | ==================== 3 | 4 | This folder contains some benchmarking related code for estimating relative performance of certain ROHD features. It can be used to help judge the relative performance impact with and without a change in ROHD. Benchmarks can be microbenchmarks for a specific feature, larger benchmarks for estimating performance on more realistic designs, or comparison benchmarks for similar applications relative to other frameworks and simulators. 5 | 6 | To run all benchmarks, execute the below command: 7 | 8 | ```shell 9 | dart run benchmark/benchmark.dart 10 | ``` 11 | 12 | You can run this command (or specific benchmarks) before and after a change to get a feel if any performance covered by these benchmarks has been impacted. 13 | 14 | ----------------------------------------- 15 | Copyright (C) 2022-2023 Intel Corporation \ 16 | SPDX-License-Identifier: BSD-3-Clause 17 | 18 | 2022 September 28 \ 19 | Author: Max Korbel <> 20 | -------------------------------------------------------------------------------- /benchmark/benchmark.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // benchmark.dart 5 | // Runs benchmarks and prints values. 6 | // 7 | // 2022 September 28 8 | // Author: Max Korbel 9 | 10 | import 'byte_enable_benchmark.dart'; 11 | import 'comb_guard_fanout_benchmark.dart'; 12 | import 'logic_value_of_benchmark.dart'; 13 | import 'many_seq_and_comb_benchmark.dart' as many_seq_and_comb; 14 | import 'many_submodules_benchmark.dart'; 15 | import 'pipeline_benchmark.dart'; 16 | import 'ssa_driver_search_benchmark.dart'; 17 | import 'wave_dump_benchmark.dart'; 18 | 19 | void main() async { 20 | await PipelineBenchmark().report(); 21 | LogicValueOfBenchmark().report(); 22 | ByteEnableBenchmark().report(); 23 | await WaveDumpBenchmark().report(); 24 | await many_seq_and_comb.main(); 25 | await CombGuardFanoutBenchmark().report(); 26 | SsaDriverSearchBenchmark().report(); 27 | await ManySubmodulesBenchmark().report(); 28 | } 29 | -------------------------------------------------------------------------------- /lib/src/exceptions/name/invalid_reserved_name_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // invalid_reserved_name_exception.dart 5 | // An exception that thrown when a reserved name is invalid. 6 | // 7 | // 2022 October 25 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:rohd/src/exceptions/rohd_exception.dart'; 11 | 12 | /// An exception that thrown when a reserved name is invalid. 13 | class InvalidReservedNameException extends RohdException { 14 | /// An exception with an error [message] for an invalid reserved name. 15 | /// 16 | /// Creates a [InvalidReservedNameException] with an optional error [message]. 17 | InvalidReservedNameException(String name) 18 | : super('The name "$name" was reserved but does not follow' 19 | ' safe naming conventions. ' 20 | 'Generally, reserved names should be valid variable identifiers' 21 | ' in languages such as Dart and SystemVerilog.'); 22 | } 23 | -------------------------------------------------------------------------------- /lib/src/exceptions/name/unavailable_reserved_name_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // unavailable_reserved_name_exception.dart 5 | // An exception that thrown when a reserved name can't be acquired. 6 | // 7 | // 2023 November 3 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An exception that thrown when a reserved name cannot be acquired. 13 | class UnavailableReservedNameException extends RohdException { 14 | /// Constructs an error indicating that the reserved [name] could not be 15 | /// acquired. 16 | UnavailableReservedNameException(String name) 17 | : this.withMessage('Unable to use reserved name "$name" ' 18 | 'because something else already has this name.'); 19 | 20 | /// Constructs an error indicating that the reserved `name` could not be 21 | /// acquired with a [message] explaining why. 22 | UnavailableReservedNameException.withMessage(super.message); 23 | } 24 | -------------------------------------------------------------------------------- /lib/src/modules/passthrough.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // passthrough.dart 5 | // A module that does nothing but pass a signal through. 6 | // 7 | // 2021 May 7 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// A very simple noop module that just passes a signal through. 13 | class Passthrough extends Module { 14 | /// The input port. 15 | Logic get in_ => input('in'); 16 | 17 | /// The output port. 18 | Logic get out => output('out'); 19 | 20 | /// Constructs a simple pass-through module that performs no operations 21 | /// between [a] and [out]. 22 | Passthrough(Logic a, [String name = 'passthrough']) : super(name: name) { 23 | addInput('in', a, width: a.width); 24 | addOutput('out', width: a.width); 25 | _setup(); 26 | } 27 | 28 | void _setup() { 29 | final inner = Logic(name: 'inner', width: in_.width); 30 | inner <= in_; 31 | out <= inner; 32 | } 33 | } 34 | -------------------------------------------------------------------------------- /lib/src/modules/conditionals/ssa.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // ssa.dart 5 | // Definitions for usage with combinational SSA. 6 | // 7 | // 2024 December 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// A signal that represents an SSA node in [Combinational.ssa] which is 13 | /// associated with one specific [Combinational]. 14 | class SsaLogic extends Logic { 15 | /// The signal that this represents. 16 | final Logic ref; 17 | 18 | /// A unique identifier for the context of which [Combinational.ssa] it is 19 | /// associated with. 20 | final int context; 21 | 22 | /// Constructs a new SSA node referring to a signal in a specific context. 23 | SsaLogic(this.ref, this.context) 24 | : super(width: ref.width, name: ref.name, naming: Naming.mergeable); 25 | 26 | @override 27 | SsaLogic clone({String? name}) => 28 | throw UnimplementedError('Should not clone an SsaLogic'); 29 | } 30 | -------------------------------------------------------------------------------- /tool/gh_codespaces/install_dart.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2023 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # install_dart.sh 7 | # GitHub Codespaces setup: Install Dart SDK according to the instructions from https://dart.dev/get-dart#install-using-apt-get. 8 | # 9 | # 2023 February 5 10 | # Author: Chykon 11 | 12 | set -euo pipefail 13 | 14 | # Add Dart repository key. 15 | 16 | declare -r input_pubkey_file='tool/gh_codespaces/pubkeys/dart.pub' 17 | declare -r output_pubkey_file='/usr/share/keyrings/dart.gpg' 18 | 19 | sudo gpg --output ${output_pubkey_file} --dearmor ${input_pubkey_file} 20 | 21 | # Add Dart repository. 22 | 23 | declare -r dart_repository_url='https://storage.googleapis.com/download.dartlang.org/linux/debian' 24 | declare -r dart_repository_file='/etc/apt/sources.list.d/dart.list' 25 | 26 | echo "deb [signed-by=${output_pubkey_file}] ${dart_repository_url} stable main" | sudo tee ${dart_repository_file} 27 | 28 | # Install Dart. 29 | 30 | sudo apt-get update 31 | sudo apt-get install dart 32 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/main.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // main.dart 5 | // Main entry for the app. 6 | // 7 | // 2025 January 28 8 | // Author: Roberto Torres 9 | 10 | import 'package:devtools_extensions/devtools_extensions.dart'; 11 | import 'package:flutter/widgets.dart'; 12 | import 'package:flutter_bloc/flutter_bloc.dart'; 13 | import 'package:rohd_devtools_extension/rohd_devtools/view/rohd_devtools_page.dart'; 14 | 15 | import 'package:rohd_devtools_extension/rohd_devtools_observer.dart'; 16 | 17 | void main() { 18 | /// Initializing the [BlocObserver] created and calling runApp 19 | Bloc.observer = const RohdDevToolsObserver(); 20 | 21 | runApp(const RohdDevToolsApp()); 22 | } 23 | 24 | class RohdDevToolsApp extends StatelessWidget { 25 | const RohdDevToolsApp({super.key}); 26 | @override 27 | Widget build(BuildContext context) { 28 | return const DevToolsExtension( 29 | child: RohdDevToolsPage(), 30 | ); 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /tool/generate_coverage.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2022-2023 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # generate_coverage.sh 7 | # Determines code coverage by tests and generates an HTML representation. 8 | # 9 | # 2022 May 5 10 | # Author: Max Korbel 11 | 12 | ### WARNING ### 13 | # The "x" option outputs all script commands. This allows you to track 14 | # the progress of the execution, but MAY REVEAL ANY SECRETS PASSED TO THE SCRIPT! 15 | set -euxo pipefail 16 | 17 | #=============# 18 | 19 | declare -r coverage_dir='build/coverage' 20 | declare -r html_dir="${coverage_dir}/genhtml" 21 | 22 | # requires enabling "coverage": 23 | # > dart pub global activate coverage 24 | dart pub global run coverage:test_with_coverage --branch-coverage --out=${coverage_dir} 25 | 26 | # requires installing "lcov": 27 | # > sudo apt install lcov 28 | genhtml --output-directory=${html_dir} --rc lcov_branch_coverage=1 ${coverage_dir}/lcov.info 29 | 30 | printf '\n%s\n\n' "Open ${html_dir}/index.html to review code coverage results." 31 | -------------------------------------------------------------------------------- /lib/src/utilities/timestamper.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // timestamper.dart 5 | // Utility for creating uniform timestamps. 6 | // 7 | // 2023 February 18 8 | // Author: Chykon 9 | 10 | /// Utility for creating timestamps. 11 | abstract class Timestamper { 12 | /// Creates a timestamp in `YYYY-MM-DD hh:mm:ss.sss [+/-]hh:mm` format. 13 | static String stamp() { 14 | final now = DateTime.now(); 15 | 16 | return '${now.toString().substring(0, 23)} ${_getUtcOffset(now)}'; 17 | } 18 | 19 | /// Converts the timezone offset to `[+/-]hh:mm` format. 20 | static String _getUtcOffset(DateTime time) { 21 | final utcOffset = 22 | time.timeZoneOffset.abs().toString().split(':').sublist(0, 2); 23 | 24 | utcOffset.first = utcOffset.first.padLeft(2, '0'); 25 | 26 | if (time.timeZoneOffset.isNegative) { 27 | utcOffset.first = '-${utcOffset.first}'; 28 | } else { 29 | utcOffset.first = '+${utcOffset.first}'; 30 | } 31 | 32 | return utcOffset.join(':'); 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A12-non-synthesizable-signal.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Non-synthesizable signal deposition" 3 | permalink: /docs/non-synthesizable-signal/ 4 | excerpt: "Non-synthesizable signal deposition" 5 | last_modified_at: 2022-12-06 6 | toc: true 7 | --- 8 | 9 | For testbench code or other non-synthesizable code, you can use `put` or `inject` on any `Logic` to deposit a value on the signal. The two functions have similar behavior, but `inject` is shorthand for calling `put` inside of `Simulator.injectAction`, which allows the deposited change to propogate within the same `Simulator` tick. Generally, you will want to use `inject` for testbench interaction with a design if it has any sequential elements. 10 | 11 | ```dart 12 | var a = Logic(), b = Logic(width:4); 13 | 14 | // you can put an int directly on a signal 15 | a.put(0); 16 | b.inject(0xf); 17 | 18 | // you can also put a `LogicValue` onto a signal 19 | a.inject(LogicValue.x); 20 | ``` 21 | 22 | Note: changing a value directly with `put()` will propogate the value, but it will not trigger flip-flop edge detection or cosim interaction. 23 | -------------------------------------------------------------------------------- /lib/src/exceptions/module/port_type_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // port_type_exception.dart 5 | // Definition for exception when a port has the wrong type. 6 | // 7 | // 2024 May 30 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An [Exception] thrown when a port has the wrong type. 13 | class PortTypeException extends RohdException { 14 | /// Constructs a new [Exception] for when a port has the wrong type. 15 | PortTypeException(Logic port, [String additionalMessage = '']) 16 | : this.forIntendedName(port.name, additionalMessage); 17 | 18 | /// Constructs a new [Exception] for when a port with the [intendedName] has 19 | /// the wrong type. 20 | /// 21 | /// This constructor is in case the port didn't even get the right name. 22 | PortTypeException.forIntendedName(String intendedName, 23 | [String additionalMessage = '']) 24 | : super('Port $intendedName has an incompatible type.' 25 | ' $additionalMessage'); 26 | } 27 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/models/signal_model.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // signal_model.dart 5 | // Model of the signal to be tabulate on the detail table. 6 | // 7 | // 2024 January 5 8 | // Author: Yao Jing Quek 9 | 10 | class SignalModel { 11 | final String name; 12 | final String direction; 13 | final String value; 14 | final int width; 15 | 16 | SignalModel({ 17 | required this.name, 18 | required this.direction, 19 | required this.value, 20 | required this.width, 21 | }); 22 | 23 | factory SignalModel.fromMap(Map map) { 24 | return SignalModel( 25 | name: map['name'] as String, 26 | direction: map['direction'] as String, 27 | value: map['value'] as String, 28 | width: map['width'] as int, 29 | ); 30 | } 31 | 32 | Map toMap() { 33 | return { 34 | 'name': name, 35 | 'direction': direction, 36 | 'value': value, 37 | 'width': width, 38 | }; 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /tool/gh_actions/check_tmp_test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2022-2024 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # check_tmp_test.sh 7 | # GitHub Actions step: Check temporary test files. 8 | # 9 | # 2022 October 12 10 | # Author: Chykon 11 | 12 | set -euo pipefail 13 | 14 | declare -r folder_name='tmp_test' 15 | 16 | # The "tmp_test" folder after performing the tests should be empty. 17 | if [ -d "${folder_name}" ]; then 18 | output=$(find ${folder_name} | wc --lines | tee) 19 | if [ "${output}" -eq 1 ]; then 20 | echo "Success: directory \"${folder_name}\" is empty!" 21 | else 22 | echo "Failure: directory \"${folder_name}\" is not empty!" 23 | exit 1 24 | fi 25 | else 26 | echo "Failure: directory \"${folder_name}\" not found!" 27 | exit 1 28 | fi 29 | 30 | # Make sure there are no VCD files in the root directory. 31 | if [ -n "$(find . -maxdepth 1 -name '*.vcd' -print -quit)" ]; then 32 | echo "Failure: VCD files found in the root directory!" 33 | exit 1 34 | else 35 | echo "Success: no VCD files found in the root directory!" 36 | fi 37 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_6/if_block.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | 3 | If truthTableIf(Logic a, Logic b, Logic carryIn, Logic sum, Logic carryOut) => 4 | If.block([ 5 | Iff(a.eq(0) & b.eq(0) & carryIn.eq(0), [ 6 | sum < 0, 7 | carryOut < 0, 8 | ]), 9 | ElseIf(a.eq(0) & b.eq(0) & carryIn.eq(1), [ 10 | sum < 1, 11 | carryOut < 0, 12 | ]), 13 | ElseIf(a.eq(0) & b.eq(1) & carryIn.eq(0), [ 14 | sum < 1, 15 | carryOut < 0, 16 | ]), 17 | ElseIf(a.eq(0) & b.eq(1) & carryIn.eq(1), [ 18 | sum < 0, 19 | carryOut < 1, 20 | ]), 21 | ElseIf(a.eq(1) & b.eq(0) & carryIn.eq(0), [ 22 | sum < 1, 23 | carryOut < 0, 24 | ]), 25 | ElseIf(a.eq(1) & b.eq(0) & carryIn.eq(1), [ 26 | sum < 0, 27 | carryOut < 1, 28 | ]), 29 | ElseIf(a.eq(1) & b.eq(1) & carryIn.eq(0), [ 30 | sum < 0, 31 | carryOut < 1, 32 | ]), 33 | // a = 1, b = 1, cin = 1 34 | Else([ 35 | sum < 1, 36 | carryOut < 1, 37 | ]) 38 | ]); 39 | -------------------------------------------------------------------------------- /rohd_devtools_extension/.metadata: -------------------------------------------------------------------------------- 1 | # This file tracks properties of this Flutter project. 2 | # Used by Flutter tool to assess capabilities and perform upgrades etc. 3 | # 4 | # This file should be version controlled and should not be manually edited. 5 | 6 | version: 7 | revision: "17025dd88227cd9532c33fa78f5250d548d87e9a" 8 | channel: "stable" 9 | 10 | project_type: app 11 | 12 | # Tracks metadata for the flutter migrate command 13 | migration: 14 | platforms: 15 | - platform: root 16 | create_revision: 17025dd88227cd9532c33fa78f5250d548d87e9a 17 | base_revision: 17025dd88227cd9532c33fa78f5250d548d87e9a 18 | - platform: web 19 | create_revision: 17025dd88227cd9532c33fa78f5250d548d87e9a 20 | base_revision: 17025dd88227cd9532c33fa78f5250d548d87e9a 21 | 22 | # User provided section 23 | 24 | # List of Local paths (relative to this file) that should be 25 | # ignored by the migrate tool. 26 | # 27 | # Files that are not part of the templates will be ignored by default. 28 | unmanaged_files: 29 | - 'lib/main.dart' 30 | - 'ios/Runner.xcodeproj/project.pbxproj' 31 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_3/answers/exercise.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | import 'package:test/test.dart'; 3 | import 'helper.dart'; 4 | 5 | void main() async { 6 | final a = Logic(name: 'a'); 7 | final b = Logic(name: 'b'); 8 | final borrowIn = Logic(name: 'borrow_in'); 9 | 10 | final xorAB = a ^ b; 11 | final diff = xorAB ^ borrowIn; 12 | final borrowOut = (~xorAB & borrowIn) | (~a & b); 13 | 14 | test('should return 0 when a and b equal 1', () async { 15 | a.put(1); 16 | b.put(1); 17 | borrowIn.put(0); 18 | 19 | expect(diff.value.toInt(), equals(0)); 20 | }); 21 | 22 | test('should return true if results matched truth table', () async { 23 | for (var i = 0; i <= 1; i++) { 24 | for (var j = 0; j <= 1; j++) { 25 | for (var k = 0; k <= 1; k++) { 26 | a.put(i); 27 | b.put(j); 28 | borrowIn.put(k); 29 | 30 | final res = fsTruthTable(i, j, k); 31 | 32 | expect(diff.value.toInt(), res.diff); 33 | expect(borrowOut.value.toInt(), res.borrowOut); 34 | } 35 | } 36 | } 37 | }); 38 | } 39 | -------------------------------------------------------------------------------- /lib/src/exceptions/conditionals/mapped_signal_already_assigned_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // mapped_signal_already_assigned_exception.dart 5 | // An exception thrown when SSA attempts to assign multiple times on the same 6 | // signal. 7 | // 8 | // 2023 April 17 9 | // Author: Max Korbel 10 | 11 | import 'package:rohd/rohd.dart'; 12 | 13 | /// An exception that is thrown when [Combinational.ssa] is attempting to 14 | /// deduce mappings for signals but fails since a signal would be connected 15 | /// multiple times. 16 | class MappedSignalAlreadyAssignedException extends RohdException { 17 | /// Creates a [MappedSignalAlreadyAssignedException] for [signalName]. 18 | MappedSignalAlreadyAssignedException( 19 | String signalName, 20 | ) : super('Signal "$signalName" has already been assigned by `ssa`,' 21 | ' but apparently needs to be connected again.' 22 | ' This is an indication that a remapped signal was incorrectly' 23 | ' used twice in different contexts.'); 24 | } 25 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_6/answers/exercise_1_case_answer.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | 3 | Case truthTableCase( 4 | Logic a, Logic b, Logic carryIn, Logic sum, Logic carryOut) => 5 | Case( 6 | [a, b, carryIn].swizzle(), 7 | [ 8 | // Mistake 1. The width of the Const is missing, remember that the width 9 | // of the constant should exists when the value have width larger 10 | // than one. 11 | CaseItem(Const(bin('000'), width: 3), [sum < 0, carryOut < 0]), 12 | CaseItem(Const(bin('001'), width: 3), [sum < 1, carryOut < 0]), 13 | CaseItem(Const(bin('010'), width: 3), [sum < 1, carryOut < 0]), 14 | CaseItem(Const(bin('011'), width: 3), [sum < 0, carryOut < 1]), 15 | 16 | // Mistake 2: The declaration of the value is wrong here 17 | CaseItem(Const(bin('100'), width: 3), [sum < 1, carryOut < 0]), 18 | 19 | CaseItem(Const(bin('101'), width: 3), [sum < 0, carryOut < 1]), 20 | CaseItem(Const(bin('110'), width: 3), [sum < 0, carryOut < 1]) 21 | ], 22 | defaultItem: [sum < 1, carryOut < 1], 23 | ); 24 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/cubit/rohd_service_state.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // rohd_service_state.dart 5 | // States for the ROHD service cubit. 6 | // 7 | // 2025 January 28 8 | // Author: Roberto Torres 9 | 10 | part of 'rohd_service_cubit.dart'; 11 | 12 | abstract class RohdServiceState extends Equatable { 13 | const RohdServiceState(); 14 | 15 | @override 16 | List get props => []; 17 | } 18 | 19 | class RohdServiceInitial extends RohdServiceState {} 20 | 21 | class RohdServiceLoading extends RohdServiceState {} 22 | 23 | class RohdServiceLoaded extends RohdServiceState { 24 | final TreeModel? treeModel; 25 | 26 | const RohdServiceLoaded(this.treeModel); 27 | 28 | @override 29 | List get props => [treeModel]; 30 | } 31 | 32 | class RohdServiceError extends RohdServiceState { 33 | final String error; 34 | final StackTrace trace; 35 | 36 | const RohdServiceError(this.error, this.trace); 37 | 38 | @override 39 | List get props => [error, trace]; 40 | } 41 | -------------------------------------------------------------------------------- /rohd_devtools_extension/web/manifest.json: -------------------------------------------------------------------------------- 1 | { 2 | "name": "rohd_devtools_extension", 3 | "short_name": "rohd_devtools_extension", 4 | "start_url": ".", 5 | "display": "standalone", 6 | "background_color": "#0175C2", 7 | "theme_color": "#0175C2", 8 | "description": "A new Flutter project.", 9 | "orientation": "portrait-primary", 10 | "prefer_related_applications": false, 11 | "icons": [ 12 | { 13 | "src": "icons/Icon-192.png", 14 | "sizes": "192x192", 15 | "type": "image/png" 16 | }, 17 | { 18 | "src": "icons/Icon-512.png", 19 | "sizes": "512x512", 20 | "type": "image/png" 21 | }, 22 | { 23 | "src": "icons/Icon-maskable-192.png", 24 | "sizes": "192x192", 25 | "type": "image/png", 26 | "purpose": "maskable" 27 | }, 28 | { 29 | "src": "icons/Icon-maskable-512.png", 30 | "sizes": "512x512", 31 | "type": "image/png", 32 | "purpose": "maskable" 33 | } 34 | ] 35 | } 36 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/f_logic_gate_part_3.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // f_logic_gate_part_3.dart 5 | // Test and simulate the logic gate created using put(). 6 | // 7 | // 2023 February 20 8 | // Author: Yao Jing Quek 9 | 10 | // ignore_for_file: avoid_print 11 | 12 | import 'package:rohd/rohd.dart'; 13 | import 'helper.dart'; 14 | 15 | void andGate(Logic a, Logic b, Logic c) { 16 | c <= a & b; 17 | } 18 | 19 | void main() async { 20 | // Create a logic for input and output 21 | final a = Logic(name: 'a'); 22 | final b = Logic(name: 'b'); 23 | final c = Logic(name: 'c'); 24 | 25 | // Instantiate Module and display system verilog 26 | final basicLogic = LogicGate(a, b, c, andGate); 27 | await displaySystemVerilog(basicLogic); 28 | 29 | // Let build a truth table 30 | print('\nBuild Truth Table: '); 31 | for (var i = 0; i <= 1; i++) { 32 | for (var j = 0; j <= 1; j++) { 33 | a.put(i); 34 | b.put(j); 35 | print('a: $i, b: $j c: ${basicLogic.c.value.toInt()}'); 36 | } 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /lib/src/exceptions/sim_compare/non_supported_type_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // non_supported_type_exception.dart 5 | // An exception that thrown when `runtimetype` of expected 6 | // vector output from SimCompare is invalid or unsupported. 7 | // 8 | // 2022 November 17 9 | // Author: Yao Jing Quek 10 | 11 | import 'package:rohd/src/exceptions/rohd_exception.dart'; 12 | import 'package:rohd/src/utilities/simcompare.dart'; 13 | 14 | /// An exception that thrown when `runtimeType` of expected vector 15 | /// output from [SimCompare] is invalid or unsupported. 16 | class NonSupportedTypeException extends RohdException { 17 | /// Displays [vector] which have invalid or unsupported `runtimeType` 18 | /// with default error [message]. 19 | /// 20 | /// Creates a [NonSupportedTypeException] with an optional error [message]. 21 | NonSupportedTypeException(dynamic vector, 22 | [String message = 'The runtimetype of expected vector is unsupported: ']) 23 | : super('$message $vector (${vector.runtimeType})'); 24 | } 25 | -------------------------------------------------------------------------------- /rohd_devtools_extension/README.md: -------------------------------------------------------------------------------- 1 | # ROHD Devtool 2 | 3 | The ROHD Devtool provides debugging functionality for hardware designers. Initial proposals and discussions for the devtool can be found at . 4 | 5 | How to Use the ROHD Devtool: 6 | 7 | 1. Set a breakpoint on your ROHD design. 8 | 2. When the breakpoint is hit, an URL will be outputted. 9 | 3. Run the dart devtools command on your terminal. 10 | 4. A webpage will open, and you can paste the URL into the webpage. 11 | 5. Look for the tab labeled 'ROHD'. 12 | 13 | ## Contributions 14 | 15 | We welcome contributions to the development of the ROHD Devtool. Please refer to our Contributing doc for guidance on how to get started. 16 | 17 | ## Running Tests on the Devtool 18 | 19 | The ROHD Devtool runs in an iframe, which means that the --platform chrome flag is required to ensure tests are run in the browser. 20 | 21 | ```cmd 22 | flutter test --platform chrome Optional[test\modules\tree_structure\model_tree_card_test.dart] > test_output.txt 23 | ``` 24 | 25 | This command will output the test results to a text file named `test_output.txt`. 26 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A04-assignment.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Assignment" 3 | permalink: /docs/assignment/ 4 | excerpt: "Assignment" 5 | last_modified_at: 2025-7-24 6 | toc: true 7 | --- 8 | 9 | To assign one signal to the value of another signal, use the `<=` operator. This is a hardware synthesizable assignment connecting two wires together. 10 | 11 | ```dart 12 | var a = Logic(), b = Logic(); 13 | 14 | // assign `a` to always have the same value as `b` 15 | a <= b; 16 | 17 | // or, equivalently, you can use the `gets` function, which may be more convenient in some situations 18 | a.gets(b); 19 | ``` 20 | 21 | It is also possible to do a partial assignment to a signal using `assignSubset`. 22 | 23 | ```dart 24 | var a = Logic(width: 3), b = Logic(width: 2); 25 | 26 | // assign the bottom two bits of `a` to have the same value as `b` 27 | a.assignSubset(b.elements); 28 | 29 | // assign the upper bit (index 2) of `a` to be 0 30 | a.assignSubset([Const(0)], 2); 31 | ``` 32 | 33 | If you're assigning groups of bits that are already collected as a single `Logic`, consider using a [`swizzle`](https://intel.github.io/rohd-website/docs/bus-range-swizzling/). 34 | -------------------------------------------------------------------------------- /lib/src/exceptions/module/port_width_mismatch_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // port_width_mismatch_exception.dart 5 | // Definition for exception when a port has the wrong width. 6 | // 7 | // 2023 April 18 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An [Exception] thrown when a port has the wrong width. 13 | class PortWidthMismatchException extends RohdException { 14 | /// Constructs a new [Exception] for when a port has the wrong width. 15 | PortWidthMismatchException(Logic port, int expectedWidth, 16 | {String additionalMessage = ''}) 17 | : super('Port ${port.name} has the wrong width.' 18 | ' Expected $expectedWidth but found ${port.width}.' 19 | ' $additionalMessage'); 20 | 21 | /// Constructs a new [Exception] for when two ports should have been the 22 | /// same width, but were not. 23 | PortWidthMismatchException.equalWidth(Logic port1, Logic port2) 24 | : super('Expected ports $port1 and $port2 to be the same width,' 25 | ' but they are not.'); 26 | } 27 | -------------------------------------------------------------------------------- /test/multimodule5_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // multimodule5_test.dart 5 | // Unit tests for a hierarchy of multiple modules and multiple instantiation 6 | // (another type) 7 | // 8 | // 2022 November 22 9 | // Author: Max Korbel 10 | 11 | import 'package:rohd/rohd.dart'; 12 | import 'package:rohd/src/modules/passthrough.dart'; 13 | import 'package:test/test.dart'; 14 | 15 | class TopModule extends Module { 16 | TopModule(Logic inPort) { 17 | inPort = addInput('inPort', inPort); 18 | 19 | final internalNet = Logic(name: 'internalNet'); 20 | final outPort = addOutput('outPort'); 21 | 22 | Combinational([internalNet < inPort]); 23 | Combinational([outPort < internalNet]); 24 | 25 | Passthrough(internalNet); 26 | } 27 | } 28 | 29 | void main() { 30 | tearDown(() async { 31 | await Simulator.reset(); 32 | }); 33 | 34 | test('multimodules5', () async { 35 | final mod = TopModule(Logic()); 36 | await mod.build(); 37 | 38 | final sv = mod.generateSynth(); 39 | 40 | expect(sv, contains('Passthrough')); 41 | }); 42 | } 43 | -------------------------------------------------------------------------------- /tool/gh_actions/generate_documentation.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Copyright (C) 2022-2024 Intel Corporation 4 | # SPDX-License-Identifier: BSD-3-Clause 5 | # 6 | # generate_documentation.sh 7 | # GitHub Actions step: Generate project documentation. 8 | # 9 | # 2022 October 10 10 | # Author: Chykon 11 | 12 | set -euo pipefail 13 | 14 | # Output parsing is required because "dart doc" is not capable of 15 | # signaling a warning with an exit code: 16 | # https://github.com/dart-lang/dartdoc/issues/2846 17 | # https://github.com/dart-lang/dartdoc/issues/2907 18 | # https://github.com/dart-lang/dartdoc/issues/1959 19 | 20 | # Disabling --validate-links due to 21 | # https://github.com/dart-lang/dartdoc/issues/3584 22 | # https://github.com/dart-lang/dartdoc/issues/3939 23 | # output=$(dart doc --validate-links 2>&1 | tee) 24 | output=$(dart doc 2>&1 | tee) 25 | 26 | # In case of problems, the searched substring will not be found. 27 | if echo "${output}" | grep --silent -e 'no issues found' -e 'Success!'; then 28 | echo 'Documentation check passed!' 29 | else 30 | echo "${output}" 31 | echo 'Documentation failed since some issues were found' 32 | exit 1 33 | fi 34 | -------------------------------------------------------------------------------- /benchmark/logic_value_of_benchmark.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // logic_value_of_benchmark.dart 5 | // Benchmarking for concatenation of values together into one. 6 | // 7 | // 2022 December 1 8 | // Author: Max Korbel 9 | 10 | import 'dart:math'; 11 | 12 | import 'package:benchmark_harness/benchmark_harness.dart'; 13 | import 'package:rohd/rohd.dart'; 14 | 15 | class LogicValueOfBenchmark extends BenchmarkBase { 16 | late final List toOf; 17 | 18 | LogicValueOfBenchmark() : super('LogicValueOf'); 19 | 20 | @override 21 | void setup() { 22 | final rand = Random(1234); 23 | toOf = List.generate( 24 | 1000, 25 | (index) => LogicValue.ofString(([ 26 | '0' * rand.nextInt(10), 27 | '1' * rand.nextInt(10), 28 | 'x' * rand.nextInt(10), 29 | 'z' * rand.nextInt(10), 30 | ]..shuffle(rand)) 31 | .join())); 32 | } 33 | 34 | @override 35 | void run() { 36 | LogicValue.ofIterable(toOf); 37 | } 38 | } 39 | 40 | void main() { 41 | LogicValueOfBenchmark().report(); 42 | } 43 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_3/helper.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | 3 | class FAResult { 4 | int sum = 0; 5 | int cOut = 0; 6 | } 7 | 8 | FAResult faTruthTable(int a, int b, int cIn) { 9 | final res = FAResult(); 10 | if (a + b + cIn == 0) { 11 | return res 12 | ..sum = 0 13 | ..cOut = 0; 14 | } else if (a + b + cIn == 3) { 15 | return res 16 | ..sum = 1 17 | ..cOut = 1; 18 | } else if (a + b + cIn == 1) { 19 | return res 20 | ..sum = 1 21 | ..cOut = 0; 22 | } else { 23 | return res 24 | ..sum = 0 25 | ..cOut = 1; 26 | } 27 | } 28 | 29 | class FullAdderModule extends Module { 30 | FullAdderModule( 31 | Logic a, 32 | Logic b, 33 | Logic cIn, 34 | void Function( 35 | Logic a, Logic b, Logic cIn, Logic xorAB, Logic sum, Logic cOut) 36 | faOps, 37 | ) : super(name: 'full_adder') { 38 | a = addInput('a', a); 39 | b = addInput('b', b); 40 | cIn = addInput('c_in', cIn); 41 | 42 | final sum = addOutput('sum'); 43 | final cOut = addOutput('c_out'); 44 | 45 | final xorAB = Logic(name: 'xor_ab'); 46 | faOps(a, b, cIn, xorAB, sum, cOut); 47 | } 48 | } 49 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_9/rohd_vf_example/analysis_options.yaml: -------------------------------------------------------------------------------- 1 | # This file configures the static analysis results for your project (errors, 2 | # warnings, and lints). 3 | # 4 | # This enables the 'recommended' set of lints from `package:lints`. 5 | # This set helps identify many issues that may lead to problems when running 6 | # or consuming Dart code, and enforces writing Dart using a single, idiomatic 7 | # style and format. 8 | # 9 | # If you want a smaller set of lints you can change this to specify 10 | # 'package:lints/core.yaml'. These are just the most critical lints 11 | # (the recommended set includes the core lints). 12 | # The core lints are also what is used by pub.dev for scoring packages. 13 | 14 | include: package:lints/recommended.yaml 15 | 16 | # Uncomment the following section to specify additional rules. 17 | 18 | # linter: 19 | # rules: 20 | # - camel_case_types 21 | 22 | # analyzer: 23 | # exclude: 24 | # - path/to/excluded/files/** 25 | 26 | # For more information about the core and recommended set of lints, see 27 | # https://dart.dev/go/core-lints 28 | 29 | # For additional information about configuring this file, see 30 | # https://dart.dev/guides/language/analysis-options 31 | -------------------------------------------------------------------------------- /rohd_devtools_extension/.vscode/launch.json: -------------------------------------------------------------------------------- 1 | { 2 | // Use IntelliSense to learn about possible attributes. 3 | // Hover to view descriptions of existing attributes. 4 | // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 5 | "version": "0.2.0", 6 | "configurations": [ 7 | { 8 | "name": "rohd_devtools_extension", 9 | "request": "launch", 10 | "type": "dart" 11 | }, 12 | { 13 | "name": "rohd_devtools_extension (profile mode)", 14 | "request": "launch", 15 | "type": "dart", 16 | "flutterMode": "profile" 17 | }, 18 | { 19 | "name": "rohd_devtools_extension (release mode)", 20 | "request": "launch", 21 | "type": "dart", 22 | "flutterMode": "release" 23 | }, 24 | { 25 | "name": "rohd_devtools_extension + simulated environment", 26 | "program": "lib/main.dart", 27 | "request": "launch", 28 | "type": "dart", 29 | "args": [ 30 | "--dart-define=use_simulated_environment=true" 31 | ], 32 | }, 33 | ] 34 | } -------------------------------------------------------------------------------- /test/example_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // example_test.dart 5 | // Tests to make sure that the examples don't break. 6 | // 7 | // 2021 September 17 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'package:test/test.dart'; 12 | 13 | import '../example/example.dart' as counter; 14 | import '../example/fir_filter.dart' as fir_filter; 15 | import '../example/logic_array.dart' as logic_array; 16 | import '../example/oven_fsm.dart' as fsm; 17 | import '../example/tree.dart' as tree; 18 | 19 | void main() { 20 | tearDown(() async { 21 | await Simulator.reset(); 22 | }); 23 | 24 | test('counter example', () async { 25 | await counter.main(noPrint: true); 26 | }); 27 | 28 | test('tree example', () async { 29 | await tree.main(noPrint: true); 30 | }); 31 | 32 | test('fir filter example', () async { 33 | await fir_filter.main(noPrint: true); 34 | }); 35 | 36 | test('fsm example', () async { 37 | await fsm.main(noPrint: true); 38 | }); 39 | 40 | test('logic array example', () async { 41 | await logic_array.main(noPrint: true); 42 | }); 43 | } 44 | -------------------------------------------------------------------------------- /benchmark/many_submodules_benchmark.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // many_submodules_benchmark.dart 5 | // A benchmarking test for a large number of submodules. 6 | // 7 | // 2024 June 12 8 | // Author: Max Korbel 9 | 10 | import 'package:benchmark_harness/benchmark_harness.dart'; 11 | import 'package:rohd/rohd.dart'; 12 | 13 | class ManySubmodulesModule extends Module { 14 | late final Logic y; 15 | ManySubmodulesModule(Logic x, {int numSubModules = 0}) { 16 | x = addInput('x', x); 17 | y = addOutput('y'); 18 | 19 | var intermediate = x; 20 | 21 | for (var i = 0; i < numSubModules; i++) { 22 | intermediate = ManySubmodulesModule(intermediate).y; 23 | } 24 | 25 | y <= intermediate; 26 | } 27 | } 28 | 29 | class ManySubmodulesBenchmark extends AsyncBenchmarkBase { 30 | ManySubmodulesBenchmark() : super('ManySubmodules'); 31 | 32 | @override 33 | Future run() async { 34 | final dut = ManySubmodulesModule(Logic(), numSubModules: 10000); 35 | await dut.build(); 36 | dut.generateSynth(); 37 | } 38 | } 39 | 40 | Future main() async { 41 | await ManySubmodulesBenchmark().report(); 42 | } 43 | -------------------------------------------------------------------------------- /lib/src/signals/port.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // port.dart 5 | // Definition of Port. 6 | // 7 | // 2023 May 30 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'package:rohd/src/utilities/sanitizer.dart'; 12 | 13 | /// An extension of [Logic] which performs some additional validation for 14 | /// inputs and outputs of [Module]s. 15 | /// 16 | /// Useful for [Interface] definitions. 17 | @Deprecated('Use `Logic.port` instead.') 18 | class Port extends Logic { 19 | /// Constructs a [Logic] intended to be used for ports of a [Module] or 20 | /// in an [Interface]. 21 | @Deprecated('Use `Logic.port` instead.') 22 | Port(String name, [int width = 1]) 23 | : super( 24 | name: name, 25 | width: width, 26 | 27 | // make port names mergeable so we don't duplicate the ports 28 | // when calling connectIO 29 | naming: Naming.mergeable, 30 | ) { 31 | if (!Sanitizer.isSanitary(name)) { 32 | throw InvalidPortNameException(name); 33 | } 34 | } 35 | 36 | @override 37 | Logic clone({String? name}) => Port(name ?? this.name, width); 38 | } 39 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/feature_request.yml: -------------------------------------------------------------------------------- 1 | name: Feature Request 2 | description: Suggest an idea for this project. 3 | labels: enhancement 4 | 5 | body: 6 | - type: markdown 7 | attributes: 8 | value: Thank you for taking the time to suggest a new feature! 9 | 10 | - type: textarea 11 | attributes: 12 | label: Motivation 13 | description: > 14 | Is your feature request related to a problem? 15 | Please provide a clear and concise description of what the problem is. 16 | placeholder: For example, "I'm always frustrated when ..." 17 | validations: 18 | required: true 19 | 20 | - type: textarea 21 | attributes: 22 | label: Desired solution 23 | description: A clear and concise description of what you want to happen. 24 | validations: 25 | required: true 26 | 27 | - type: textarea 28 | attributes: 29 | label: Alternatives considered 30 | description: > 31 | A clear and concise description of any alternative solutions 32 | or features you've considered. 33 | 34 | - type: textarea 35 | attributes: 36 | label: Additional details 37 | description: Add any other context or screenshots about the feature request here. 38 | -------------------------------------------------------------------------------- /lib/src/signals/const.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // const.dart 5 | // Definition of signals with constant values. 6 | // 7 | // 2023 May 26 8 | // Author: Max Korbel 9 | 10 | part of 'signals.dart'; 11 | 12 | /// Represents a [Logic] that never changes value. 13 | class Const extends Logic { 14 | /// Constructs a [Const] with the specified value. 15 | /// 16 | /// [val] should be processable by [LogicValue.of]. 17 | /// 18 | /// If a [width] is provided, the [Const] will be that width. If not, and 19 | /// [val] is a [LogicValue], the [Const] will be the width of [val]. 20 | /// Otherwise, the [Const] will be 1 bit wide. 21 | Const(dynamic val, {int? width, bool fill = false}) 22 | : super( 23 | name: 'const_$val', 24 | width: width ?? (val is LogicValue ? val.width : 1), 25 | // we don't care about maintaining this node unless necessary 26 | naming: Naming.unnamed, 27 | ) { 28 | _wire.put(val, fill: fill, signalName: name); 29 | 30 | makeUnassignable(reason: '`Const` signals are unassignable.'); 31 | } 32 | 33 | @override 34 | Const clone({String? name}) => Const(value, width: width); 35 | } 36 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_4/answers/exercise_2.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | import 'package:test/test.dart'; 3 | 4 | void main() { 5 | final a = Logic(name: 'a', width: 8); 6 | final b = Logic(name: 'b', width: 8); 7 | 8 | final diff = nBitSubtractor(a, b); 9 | 10 | test('should return 5 when a is 25 and b is 20', () { 11 | a.put(25); 12 | b.put(20); 13 | expect(diff.value.toInt(), equals(5)); 14 | }); 15 | } 16 | 17 | Logic nBitSubtractor(Logic a, Logic b) { 18 | assert(a.width == b.width, 'a and b should have same width.'); 19 | 20 | Logic borrow = Const(0); 21 | final diff = []; 22 | 23 | for (var i = 0; i < a.width; i++) { 24 | final res = rippleBorrowSubtractor(a[i], b[i], borrow); 25 | 26 | borrow = res.borrow; 27 | diff.add(res.diff); 28 | } 29 | diff.add(borrow); 30 | 31 | return diff.rswizzle(); 32 | } 33 | 34 | FullSubtractorResult rippleBorrowSubtractor(Logic a, Logic b, Logic borrowIn) { 35 | final xorAB = a ^ b; 36 | 37 | final fsr = FullSubtractorResult(); 38 | fsr.diff <= xorAB ^ borrowIn; 39 | fsr.borrow <= (~xorAB & borrowIn) | (~a & b); 40 | 41 | return fsr; 42 | } 43 | 44 | class FullSubtractorResult { 45 | final diff = Logic(name: 'diff'); 46 | final borrow = Logic(name: 'borrow'); 47 | } 48 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_4/basic_generation.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | import 'package:test/test.dart'; 3 | 4 | void main() { 5 | final a = Logic(name: 'a', width: 8); 6 | final b = Logic(name: 'a', width: 8); 7 | 8 | final sum = nBitAdder(a, b); 9 | 10 | test('should return 10 when both inputs are 5', () { 11 | a.put(5); 12 | b.put(5); 13 | 14 | expect(sum.value.toInt(), equals(10)); 15 | }); 16 | } 17 | 18 | Logic nBitAdder(Logic a, Logic b) { 19 | assert(a.width == b.width, 'a and b should have same width.'); 20 | 21 | Logic carry = Const(0); 22 | final sum = []; 23 | 24 | for (var i = 0; i < a.width; i++) { 25 | final res = fullAdder(a[i], b[i], carry); 26 | carry = res.cOut; 27 | sum.add(res.sum); 28 | } 29 | 30 | sum.add(carry); 31 | 32 | return sum.rswizzle(); 33 | } 34 | 35 | class FullAdderResult { 36 | final sum = Logic(name: 'sum'); 37 | final cOut = Logic(name: 'cOut'); 38 | } 39 | 40 | // fullAdder function that has a return type of FullAdderResult 41 | FullAdderResult fullAdder(Logic a, Logic b, Logic carryIn) { 42 | final and1 = carryIn & (a ^ b); 43 | final and2 = b & a; 44 | 45 | final res = FullAdderResult(); 46 | res.sum <= (a ^ b) ^ carryIn; 47 | res.cOut <= and1 | and2; 48 | 49 | return res; 50 | } 51 | -------------------------------------------------------------------------------- /lib/src/selection.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // selection.dart 5 | // Definition for selecting a Logic from List by a given index. 6 | // 7 | // 2023 November 14 8 | // Author: Rahul Gautham Putcha 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// Allows a lists of [Logic]s to have its elemets picked 13 | /// by a [Logic] index value. 14 | extension IndexedLogic on List { 15 | /// Performs a [index] based selection on an [List] of [Logic]. 16 | /// 17 | /// Given a [List] of [Logic] say `logicList` on which we apply [selectIndex] 18 | /// and an element [index] as argument , we can select any valid element 19 | /// of type [Logic] within the `logicList` using the [index] of [Logic] type. 20 | /// 21 | /// Alternatively we can approach this with `index.selectFrom(logicList)` 22 | /// 23 | /// Example: 24 | /// ```dart 25 | /// // ordering matches closer to array indexing with `0` index-based. 26 | /// List logicList = [/* Add your Logic elements here */]; 27 | /// selected <= logicList.selectIndex(index); 28 | /// ``` 29 | /// 30 | Logic selectIndex(Logic index, {Logic? defaultValue}) => 31 | index.selectFrom(this, defaultValue: defaultValue); 32 | } 33 | -------------------------------------------------------------------------------- /test/comb_sensitivity_search_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // comb_sensitivity_search_test.dart 5 | // Unit tests related to Combinational sensitivity searching. 6 | // 7 | // 2023 January 5 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'package:test/test.dart'; 12 | 13 | class CombySubModule extends Module { 14 | Logic get b => output('b'); 15 | CombySubModule(Logic a) : super(name: 'combySubModule') { 16 | a = addInput('a', a); 17 | addOutput('b'); 18 | 19 | Combinational([b < a]); 20 | } 21 | } 22 | 23 | class ContainerModule extends Module { 24 | ContainerModule(Logic a) : super(name: 'containerModule') { 25 | a = addInput('a', a); 26 | final b = addOutput('b'); 27 | final bb = addOutput('bb'); 28 | 29 | final combySubMod = CombySubModule(a); 30 | 31 | // attach `b` output first so that the CombySubModule gets found by 32 | // the output search before the inverter for `bb` 33 | b <= combySubMod.b; 34 | 35 | bb <= ~combySubMod.b; 36 | } 37 | } 38 | 39 | void main() { 40 | test('build runs properly for comb sensitivity search', () async { 41 | final mod = ContainerModule(Logic()); 42 | await mod.build(); 43 | }); 44 | } 45 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_5/answers/n_bit_subtractor.dart: -------------------------------------------------------------------------------- 1 | // ignore_for_file: avoid_print 2 | 3 | import 'package:rohd/rohd.dart'; 4 | import 'package:test/test.dart'; 5 | import 'full_subtractor.dart'; 6 | 7 | class NBitFullSubtractor extends Module { 8 | NBitFullSubtractor(Logic a, Logic b) { 9 | a = addInput('a', a, width: a.width); 10 | b = addInput('b', b, width: b.width); 11 | 12 | final diff = addOutput('diff', width: a.width + b.width); 13 | 14 | Logic borrow = Const(0); 15 | final diffList = []; 16 | 17 | for (var i = 0; i < a.width; i++) { 18 | final res = FullSubtractor(a[i], b[i], borrow); 19 | 20 | borrow = res.fsResult.borrow; 21 | diffList.add(res.fsResult.diff); 22 | } 23 | diffList.add(borrow); 24 | 25 | diff <= diffList.rswizzle().zeroExtend(diff.width); 26 | } 27 | 28 | // getter 29 | Logic get result => output('diff'); 30 | } 31 | 32 | Future main() async { 33 | final a = Logic(name: 'a', width: 8); 34 | final b = Logic(name: 'b', width: 8); 35 | 36 | final mod = NBitFullSubtractor(a, b); 37 | await mod.build(); 38 | 39 | print(mod.generateSynth()); 40 | 41 | test('should return 1 when a is 8 and b is 7.', () { 42 | a.put(8); 43 | b.put(7); 44 | 45 | expect(mod.result.value.toInt(), 1); 46 | }); 47 | } 48 | -------------------------------------------------------------------------------- /test/example_icarus_waves.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Tue Feb 7 10:45:30 2023 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1ps 9 | $end 10 | $scope module cosim_wrapper $end 11 | $scope module external_module $end 12 | $var wire 1 ! clk $end 13 | $var wire 8 " push_data [7:0] $end 14 | $var wire 1 # push_valid $end 15 | $var reg 8 $ sampled [7:0] $end 16 | $upscope $end 17 | $upscope $end 18 | $enddefinitions $end 19 | #0 20 | $dumpvars 21 | bx $ 22 | z# 23 | bz " 24 | 0! 25 | $end 26 | #5000 27 | 1! 28 | #5002 29 | b0 " 30 | 1# 31 | #10000 32 | 0! 33 | #15000 34 | b0 $ 35 | 1! 36 | #15002 37 | b1 " 38 | 0# 39 | #20000 40 | 0! 41 | #25000 42 | 1! 43 | #25002 44 | b10 " 45 | 1# 46 | #30000 47 | 0! 48 | #35000 49 | b10 $ 50 | 1! 51 | #35002 52 | b11 " 53 | 0# 54 | #40000 55 | 0! 56 | #45000 57 | 1! 58 | #45002 59 | b100 " 60 | 1# 61 | #50000 62 | 0! 63 | #55000 64 | b100 $ 65 | 1! 66 | #55002 67 | b101 " 68 | 0# 69 | #60000 70 | 0! 71 | #65000 72 | 1! 73 | #65002 74 | b110 " 75 | 1# 76 | #70000 77 | 0! 78 | #75000 79 | b110 $ 80 | 1! 81 | #75002 82 | b111 " 83 | 0# 84 | #80000 85 | 0! 86 | #85000 87 | 1! 88 | #85002 89 | b1000 " 90 | 1# 91 | #90000 92 | 0! 93 | #95000 94 | b1000 $ 95 | 1! 96 | #95002 97 | b1001 " 98 | 0# 99 | #100000 100 | 0! 101 | #100002 102 | -------------------------------------------------------------------------------- /test/long_chain_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // long_chain_test.dart 5 | // Tests with long chains of combinational logic. 6 | // 7 | // 2022 November 8 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'package:rohd/src/modules/passthrough.dart'; 12 | import 'package:rohd/src/utilities/web.dart'; 13 | import 'package:test/test.dart'; 14 | 15 | class LongChain extends Module { 16 | final int length; 17 | 18 | Logic get chainOut => output('chainOut'); 19 | 20 | LongChain( 21 | Logic chainIn, { 22 | this.length = 23 | // for some reason, compiled to JS it hits stack limit sooner 24 | kIsWeb ? 850 : 1050, 25 | }) : super(name: 'longChain') { 26 | chainIn = addInput('chainIn', chainIn); 27 | 28 | var intermediate = chainIn; 29 | for (var i = 0; i < length; i++) { 30 | intermediate = ~Passthrough(intermediate).out; 31 | } 32 | addOutput('chainOut') <= intermediate; 33 | } 34 | } 35 | 36 | void main() { 37 | test('long chain of combinational logic and modules', () async { 38 | final chainIn = Logic(name: 'chainIn'); 39 | final chain = LongChain(chainIn); 40 | await chain.build(); 41 | 42 | chainIn.put(0); 43 | expect(chain.chainOut.value.toInt(), equals(chain.length % 2)); 44 | }); 45 | } 46 | -------------------------------------------------------------------------------- /test/external_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // external_test.dart 5 | // Unit tests for external modules 6 | // 7 | // 2022 January 7 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'package:test/test.dart'; 12 | 13 | class MyExternalModule extends ExternalSystemVerilogModule { 14 | MyExternalModule(Logic a, {int width = 2}) 15 | : super( 16 | definitionName: 'external_module_name', 17 | parameters: {'WIDTH': '$width'}) { 18 | addInput('a', a, width: width); 19 | addOutput('b', width: width); 20 | } 21 | } 22 | 23 | class TopModule extends Module { 24 | TopModule(Logic a) { 25 | a = addInput('a', a, width: a.width); 26 | MyExternalModule(a); 27 | } 28 | } 29 | 30 | void main() { 31 | test('instantiate', () async { 32 | final mod = TopModule(Logic(width: 2)); 33 | await mod.build(); 34 | final sv = mod.generateSynth(); 35 | 36 | // make sure we instantiate the external module properly 37 | expect( 38 | sv, 39 | contains( 40 | 'external_module_name #(.WIDTH(2)) external_module(.a(a),.b(b));')); 41 | 42 | // make sure we don't generate the external module SV definition 43 | expect(RegExp(r'module\s+external_module_name').hasMatch(sv), isFalse); 44 | }); 45 | } 46 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/ui/module_tree_details_navbar.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // module_tree_details_navbar.dart 5 | // UI for module tree details card navrbar. 6 | // 7 | // 2024 January 5 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:flutter/material.dart'; 11 | 12 | class ModuleTreeDetailsNavbar extends StatelessWidget { 13 | const ModuleTreeDetailsNavbar({ 14 | super.key, 15 | }); 16 | 17 | @override 18 | Widget build(BuildContext context) { 19 | return BottomNavigationBar( 20 | type: BottomNavigationBarType.fixed, 21 | backgroundColor: const Color(0x1B1B1FEE), 22 | selectedItemColor: Colors.white, 23 | unselectedItemColor: Colors.white.withOpacity(.60), 24 | selectedFontSize: 10, 25 | unselectedFontSize: 10, 26 | onTap: (value) { 27 | // Respond to item press. 28 | }, 29 | items: const [ 30 | BottomNavigationBarItem( 31 | label: 'Details', 32 | icon: Icon(Icons.info), 33 | ), 34 | BottomNavigationBarItem( 35 | label: 'Waveform', 36 | icon: Icon(Icons.cable), 37 | ), 38 | BottomNavigationBarItem( 39 | label: 'Schematic', 40 | icon: Icon(Icons.developer_board), 41 | ), 42 | ], 43 | ); 44 | } 45 | } 46 | -------------------------------------------------------------------------------- /rohd_devtools_extension/test/modules/tree_structure/rohd_devtools_mocks.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // rohd_devtools_mocks.dart 5 | // All the mocks initialization for services and providers. 6 | // 7 | // 2024 January 9 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:mocktail/mocktail.dart'; 11 | import 'package:rohd_devtools_extension/rohd_devtools/models/signal_model.dart'; 12 | import 'package:rohd_devtools_extension/rohd_devtools/models/tree_model.dart'; 13 | import 'package:rohd_devtools_extension/rohd_devtools/rohd_devtools.dart'; 14 | import 'package:rohd_devtools_extension/rohd_devtools/services/signal_service.dart'; 15 | import 'package:rohd_devtools_extension/rohd_devtools/services/tree_service.dart'; 16 | 17 | class MockTreeModel extends Mock implements TreeModel {} 18 | 19 | class MockSignalModel extends Mock implements SignalModel {} 20 | 21 | class MockTreeService extends Mock implements TreeService {} 22 | 23 | class MockSignalService extends Mock implements SignalService {} 24 | 25 | class MockRohdServiceCubit extends Mock implements RohdServiceCubit {} 26 | 27 | class MockSelectedModuleCubit extends Mock implements SelectedModuleCubit {} 28 | 29 | class MockTreeSearchTermCubit extends Mock implements TreeSearchTermCubit {} 30 | 31 | class MockSignalSearchTermCubit extends Mock implements SignalSearchTermCubit {} 32 | -------------------------------------------------------------------------------- /rohd_devtools_extension/web/index.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | rohd_devtools_extension 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | -------------------------------------------------------------------------------- /lib/src/utilities/web.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // web.dart 5 | // Utilities for running ROHD safely on the web or in JavaScript. 6 | // 7 | // 2023 December 8 8 | // Author: Max Korbel 9 | 10 | import 'dart:math'; 11 | 12 | import 'package:rohd/rohd.dart'; 13 | 14 | /// Borrowed from Flutter's implementation to determine whether Dart is 15 | /// compiled to run on the web. This is relevant for ROHD because when the 16 | /// code is compiled to JavaScript, it affects the ability for [LogicValue] 17 | /// to store different sizes of data in different implementations. 18 | /// 19 | /// See more details here: 20 | /// https://api.flutter.dev/flutter/foundation/kIsWeb-constant.html 21 | // ignore: do_not_use_environment 22 | const bool kIsWeb = bool.fromEnvironment('dart.library.js_util'); 23 | 24 | /// The number of bits in an int. 25 | // ignore: constant_identifier_names 26 | const int INT_BITS = kIsWeb ? 32 : 64; 27 | 28 | /// Calculates the `int` result of `1 << shamt` in a safe way considering 29 | /// whether it is run in JavaScript or native Dart. 30 | /// 31 | /// In JavaScript, the shift amount is `&`ed with `0x1f`, so `1 << 32 == 0`. 32 | int oneSllBy(int shamt) { 33 | if (kIsWeb) { 34 | assert(shamt <= 52, 'Loss of precision in JavaScript beyond 53 bits.'); 35 | return pow(2, shamt) as int; 36 | } else { 37 | return 1 << shamt; 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Bus ranges and swizzling" 3 | permalink: /docs/bus-range-swizzling/ 4 | excerpt: "Bus ranges and swizzling" 5 | last_modified_at: 2022-12-06 6 | toc: true 7 | --- 8 | 9 | Multi-bit busses can be accessed by single bits and ranges or composed from multiple other signals. Slicing, swizzling, etc. are also accessible on `LogicValue`s. 10 | 11 | ```dart 12 | var a = Logic(width:8), 13 | b = Logic(width:3), 14 | c = Const(7, width:5), 15 | d = Logic(), 16 | e = Logic(width: 9); 17 | 18 | 19 | // assign b to the bottom 3 bits of a 20 | b <= a.slice(2,0); 21 | 22 | // assign d to the top bit of a 23 | d <= a[7]; 24 | 25 | // construct e by swizzling bits from b, c, and d 26 | // here, the MSB is on the left, LSB is on the right 27 | e <= [d, c, b].swizzle(); 28 | 29 | // alternatively, do a reverse swizzle 30 | // (useful for lists where 0-index is actually the 0th element) 31 | // 32 | // here, the LSB is on the left, the MSB is on the right 33 | e <= [b, c, d].rswizzle(); 34 | ``` 35 | 36 | ROHD does not support assignment to a subset of a bus. That is, you *cannot* do something like `e[3] <= d`. Instead, you can use the `withSet` function to get a copy with that subset of the bus assigned to something else. This applies for both `Logic` and `LogicValue`. For example: 37 | 38 | ```dart 39 | // reassign the variable `e` to a new `Logic` where bit 3 is set to `d` 40 | e = e.withSet(3, d); 41 | ``` 42 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/ui/devtool_appbar.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // devtool_appbar.dart 5 | // UI for rohd devtool appbar. 6 | // 7 | // 2024 January 5 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:flutter/material.dart'; 11 | 12 | class DevtoolAppBar extends StatelessWidget implements PreferredSizeWidget { 13 | const DevtoolAppBar({ 14 | super.key, 15 | }); 16 | 17 | @override 18 | Widget build(BuildContext context) { 19 | return AppBar( 20 | backgroundColor: Theme.of(context).colorScheme.onPrimary, 21 | title: const Text('ROHD DevTool (Beta)'), 22 | leading: const Icon(Icons.build), 23 | actions: [ 24 | Padding( 25 | padding: const EdgeInsets.only(right: 20.0), 26 | child: MouseRegion( 27 | cursor: SystemMouseCursors.click, 28 | child: GestureDetector( 29 | onTap: () { 30 | showLicensePage(context: context); 31 | }, 32 | child: const Text( 33 | 'Licenses', 34 | style: TextStyle( 35 | fontWeight: FontWeight.bold, 36 | ), 37 | ), 38 | ), 39 | ), 40 | ), 41 | ], 42 | ); 43 | } 44 | 45 | @override 46 | Size get preferredSize => const Size.fromHeight(kToolbarHeight); 47 | } 48 | -------------------------------------------------------------------------------- /doc/user_guide/_get-started/03-development-recommendations.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Development Recommendations" 3 | permalink: /get-started/development-recommendations/ 4 | excerpt: "Development Recommendations" 5 | last_modified_at: 2023-6-19 6 | toc: true 7 | --- 8 | 9 | - The [ROHD Verification Framework](https://github.com/intel/rohd-vf) is a UVM-like framework for building testbenches for hardware modelled in ROHD. 10 | - The [ROHD Cosimulation](https://github.com/intel/rohd-cosim) package allows you to cosimulate the ROHD simulator with a variety of SystemVerilog simulators. 11 | - The [ROHD Hardware Component Library](https://github.com/intel/rohd-vf) provides a set of reusable and configurable components for design and verification. 12 | - Visual Studio Code (vscode) is a great, free IDE with excellent support for Dart. It works well on all platforms, including native Windows or Windows Subsystem for Linux (WSL) which allows you to run a native Linux kernel (e.g. Ubuntu) within Windows. You can also use vscode to develop on a remote machine with the Remote SSH extension. 13 | - vscode: 14 | - WSL: 15 | - Remote SSH: 16 | - Dart extension for vscode: 17 | 18 | Head over to the [user guide]({{ site.baseurl }}{% link _docs/A01-sample-example.md %}) to learn more about how to use ROHD. 19 | -------------------------------------------------------------------------------- /benchmark/byte_enable_benchmark.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // byte_enable_benchmark.dart 5 | // Benchmarking for simple byte enable hardware 6 | // 7 | // 2022 December 2 8 | // Author: Max Korbel 9 | 10 | import 'package:benchmark_harness/benchmark_harness.dart'; 11 | import 'package:rohd/rohd.dart'; 12 | 13 | class ByteEnableBenchmark extends BenchmarkBase { 14 | late final Logic result; 15 | late final Logic select; 16 | late final Logic original; 17 | 18 | static const int numBytes = 128; 19 | 20 | final List vectors = List.generate( 21 | numBytes, 22 | (index) => LogicValue.ofString( 23 | (index.toRadixString(2) * numBytes).substring(0, numBytes))); 24 | 25 | ByteEnableBenchmark() : super('ByteEnable'); 26 | 27 | @override 28 | void setup() { 29 | select = Logic(name: 'select', width: numBytes); 30 | original = Logic(name: 'original', width: numBytes * 8); 31 | original.put(LogicValue.ofString('0x1z10xz' * numBytes)); 32 | select.put(0); 33 | result = List.generate( 34 | numBytes, 35 | (index) => mux( 36 | select[index], 37 | original.getRange(index * 8, (index + 1) * 8), 38 | Const(0, width: 8), 39 | )).swizzle(); 40 | } 41 | 42 | @override 43 | void run() { 44 | vectors.forEach(select.put); 45 | } 46 | } 47 | 48 | void main() { 49 | ByteEnableBenchmark().report(); 50 | } 51 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/answers/exercise_2.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // exercise_2.dart 5 | // Answer to exercise 2. 6 | // 7 | // 2023 February 14 8 | // Author: Yao Jing Quek 9 | 10 | // ignore_for_file: avoid_print 11 | import 'package:rohd/rohd.dart'; 12 | import '../helper.dart'; 13 | 14 | void gate(Logic a, Logic b, Logic c) { 15 | // Note: If you're familiar with SV, you may want to read this section, 16 | // but if it's new to you, feel free to skip ahead. 17 | // We'll cover the topic more extensively in Chapters 5, 6, and 7, 18 | // where you'll have the opportunity to gain a deeper understanding. 19 | const answer = 'xor'; // 'or', 'nor', 'xor' 20 | switch (answer) { 21 | case 'or': 22 | c <= a | b; 23 | case 'nor': 24 | c <= ~(a | b); 25 | case 'xor': 26 | c <= a ^ b; 27 | } 28 | } 29 | 30 | void main() async { 31 | // Create a logic for input and output 32 | final a = Logic(name: 'a'); 33 | final b = Logic(name: 'b'); 34 | final c = Logic(name: 'c'); 35 | 36 | // Instantiate Module and display system verilog 37 | final basicLogic = LogicGate(a, b, c, gate); 38 | await displaySystemVerilog(basicLogic); 39 | 40 | // Let build a truth table 41 | print('\nBuild Truth Table: '); 42 | for (var i = 0; i <= 1; i++) { 43 | for (var j = 0; j <= 1; j++) { 44 | a.put(i); 45 | b.put(j); 46 | print('a: $i, b: $j c: ${basicLogic.c.value.toInt()}'); 47 | } 48 | } 49 | } 50 | -------------------------------------------------------------------------------- /rohd_devtools_extension/analysis_options.yaml: -------------------------------------------------------------------------------- 1 | # This file configures the analyzer, which statically analyzes Dart code to 2 | # check for errors, warnings, and lints. 3 | # 4 | # The issues identified by the analyzer are surfaced in the UI of Dart-enabled 5 | # IDEs (https://dart.dev/tools#ides-and-editors). The analyzer can also be 6 | # invoked from the command line by running `flutter analyze`. 7 | 8 | # The following line activates a set of recommended lints for Flutter apps, 9 | # packages, and plugins designed to encourage good coding practices. 10 | include: package:flutter_lints/flutter.yaml 11 | 12 | linter: 13 | # The lint rules applied to this project can be customized in the 14 | # section below to disable rules from the `package:flutter_lints/flutter.yaml` 15 | # included above or to enable additional rules. A list of all available lints 16 | # and their documentation is published at https://dart.dev/lints. 17 | # 18 | # Instead of disabling a lint rule for the entire project in the 19 | # section below, it can also be suppressed for a single line of code 20 | # or a specific dart file by using the `// ignore: name_of_lint` and 21 | # `// ignore_for_file: name_of_lint` syntax on the line or in the file 22 | # producing the lint. 23 | rules: 24 | # avoid_print: false # Uncomment to disable the `avoid_print` rule 25 | # prefer_single_quotes: true # Uncomment to enable the `prefer_single_quotes` rule 26 | 27 | # Additional information about this file can be found at 28 | # https://dart.dev/guides/language/analysis-options 29 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_4/answers/exercise_1.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | import 'package:test/test.dart'; 3 | 4 | void main() { 5 | final a = Logic(name: 'a', width: 8); 6 | final b = Logic(name: 'a', width: 8); 7 | 8 | final sum = nBitAdder(a, b); 9 | 10 | test('should return 255 when both inputs are added', () { 11 | a.put(127); 12 | b.put(128); 13 | 14 | expect(sum.value.toInt(), equals(255)); 15 | }); 16 | } 17 | 18 | Logic nBitAdder(Logic a, Logic b) { 19 | assert(a.width == b.width, 'a and b should have same width.'); 20 | 21 | final carry = Const(0); 22 | final sum = []; 23 | 24 | recursiveFullAdder(a, b, carry, sum, 0); 25 | 26 | sum.add(carry); 27 | 28 | return sum.rswizzle(); 29 | } 30 | 31 | void recursiveFullAdder(Logic a, Logic b, Logic carry, List sum, int i) { 32 | // Base Case 33 | if (i == a.width) { 34 | // if the width equals to index 0 35 | return; 36 | } else { 37 | // Recursive Case 38 | final res = fullAdder(a[i], b[i], carry); 39 | recursiveFullAdder(a, b, res.cOut, sum, i + 1); 40 | sum.add(res.sum); 41 | } 42 | } 43 | 44 | class FullAdderResult { 45 | final sum = Logic(name: 'sum'); 46 | final cOut = Logic(name: 'cOut'); 47 | } 48 | 49 | // fullAdder function that has a return type of FullAdderResult 50 | FullAdderResult fullAdder(Logic a, Logic b, Logic carryIn) { 51 | final and1 = carryIn & (a ^ b); 52 | final and2 = b & a; 53 | 54 | final res = FullAdderResult(); 55 | res.sum <= (a ^ b) ^ carryIn; 56 | res.cOut <= and1 | and2; 57 | 58 | return res; 59 | } 60 | -------------------------------------------------------------------------------- /.github/workflows/build_devtool.yml: -------------------------------------------------------------------------------- 1 | name: Build ROHD devtool 2 | on: 3 | push: 4 | branches: 5 | - main 6 | 7 | # Top-level default, no permissions 8 | permissions: {} 9 | 10 | jobs: 11 | build-devtool: 12 | name: Build Devtools 13 | permissions: 14 | contents: write 15 | pull-requests: write 16 | timeout-minutes: 30 17 | runs-on: ${{ github.repository_owner == 'intel' && 'intel-ubuntu-latest' || 'ubuntu-latest' }} 18 | steps: 19 | - uses: actions/checkout@v2 20 | 21 | - name: Setup Flutter SDK 22 | uses: flutter-actions/setup-flutter@v2 23 | with: 24 | channel: stable 25 | version: 3.29.0 26 | 27 | - name: Run Flutter Test 28 | run: tool/gh_actions/devtool/run_devtool_test.sh 29 | 30 | - name: Build Static Web 31 | run: tool/gh_actions/devtool/build_web.sh 32 | 33 | - name: Create artifact branch and commit 34 | run: | 35 | git config --global user.name "${GITHUB_ACTOR}" 36 | git config --global user.email "${GITHUB_ACTOR}@users.noreply.github.com" 37 | git fetch origin 38 | git checkout -b artifacts 39 | git pull origin main 40 | git add . 41 | git add -f extension/* 42 | git commit -m "Add build artifacts" 43 | 44 | - name: Push changes 45 | uses: ad-m/github-push-action@master 46 | with: 47 | github_token: ${{ secrets.GITHUB_TOKEN }} 48 | branch: artifacts 49 | force: true 50 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (C) 2021-2023 Intel Corporation 4 | 5 | Redistribution and use in source and binary forms, with or without 6 | modification, are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its 16 | contributors may be used to endorse or promote products derived from 17 | this software without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_2/b_logic_width.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // a_logic_width.dart 5 | // Creation logic value and width in rohd. 6 | // 7 | // 2023 February 20 8 | // Author: Yao Jing Quek 9 | 10 | // ignore_for_file: avoid_print 11 | 12 | import 'package:rohd/rohd.dart'; 13 | import 'helper.dart'; 14 | 15 | void main() async { 16 | final bus = Logic(name: 'threeBitBus', width: 3); 17 | final bigBus = Logic(name: 'bigBus', width: 65); 18 | 19 | // Instantiate Module and display system verilog 20 | final basicLogic = LogicInitialization(bus, bigBus); 21 | await displaySystemVerilog(basicLogic); 22 | 23 | // Simulation with put()! 24 | 25 | // .put() is one way to simulate a signal on a Logic signal that has been 26 | // created. 27 | // We will come back to this in later section. 28 | bus.put(1); 29 | 30 | // Obtain the value of bus. 31 | final busVal = bus.value; 32 | 33 | print('\nNote:'); 34 | 35 | // output: 3'h1. 36 | print('a) The hexadecimal string value of bus is $busVal.'); 37 | 38 | // Obtain the value of bus in Int 39 | final busValInt = bus.value.toInt(); 40 | 41 | // output: 1. 42 | print('b) The integer value of bus is $busValInt.'); 43 | 44 | // If you set your bus width larger than 64 bits. 45 | // You have to use toBigInt(). 46 | bigBus.put(BigInt.parse('9223372036854775808')); 47 | final bigBusValBigInt = bigBus.value.toBigInt(); 48 | 49 | // output: 9223372036854775808. 50 | print('c) The big integer of bus is $bigBusValBigInt.'); 51 | } 52 | -------------------------------------------------------------------------------- /lib/src/utilities/sv_cleaner.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // sv_cleaner.dart 5 | // Internal helper utilities for changing generated SV for testing purposes 6 | // only. This should NOT be used for anything else. 7 | // 8 | // 2025 November 5 9 | // Author: Max Korbel 10 | 11 | import 'package:meta/meta.dart'; 12 | 13 | @internal 14 | abstract class SvCleaner { 15 | /// Removes all swizzle bit annotation comments from a generated SystemVerilog 16 | /// string for the purpose of helping test accurate SV. 17 | /// 18 | /// This function removes comments of the form `/* ... */` that contain bit 19 | /// range annotations (like `/* 7:0 */` or `/* 15 */`) and collapses the 20 | /// remaining content to the old style single-line format without spaces. 21 | /// 22 | /// This is specifically for tests that compare generated SV strings where 23 | /// bit range annotations are not relevant to the test and would only add 24 | /// noise. 25 | @internal 26 | static String removeSwizzleAnnotationComments(String sv) => 27 | // Single regex that handles all formatting cases 28 | sv.replaceAllMapped( 29 | RegExp(r'(\{\s+|\s*/\*\s*\d+(?::\s*\d+)?\s*\*/\s*|\s+\})', 30 | multiLine: true), (match) { 31 | final matched = match.group(0)!; 32 | if (matched.contains('{')) { 33 | return '{'; 34 | } 35 | if (matched.contains('}')) { 36 | return '}'; 37 | } 38 | return ''; // Remove bit range annotations and their whitespace 39 | }); 40 | } 41 | -------------------------------------------------------------------------------- /test/trace_bounce_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // trace_bounce_test.dart 5 | // 6 | // 2022 March 4 7 | // Author: Max Korbel 8 | 9 | import 'package:rohd/rohd.dart'; 10 | import 'package:rohd/src/utilities/simcompare.dart'; 11 | import 'package:test/test.dart'; 12 | 13 | class TopModule extends Module { 14 | TopModule(Logic a) : super(name: 'topmodule') { 15 | a = addInput('a_top', a); 16 | final bundle = addOutput('bundle_top', width: 3); 17 | bundle <= SubModule(a).bundle; 18 | } 19 | } 20 | 21 | class SubModule extends Module { 22 | Logic get bundle => output('bundle'); 23 | SubModule(Logic a) : super(name: 'submodule') { 24 | a = addInput('a', a); 25 | final b = addOutput('b'); 26 | final c = addOutput('c'); 27 | final d = addOutput('d'); 28 | final e = addOutput('e'); 29 | final bundle = addOutput('bundle', width: 3); 30 | 31 | b <= a; 32 | c <= b; 33 | d <= (Logic()..gets(b)); 34 | e <= ~b; 35 | bundle <= [c, d, e].swizzle(); 36 | } 37 | } 38 | 39 | void main() { 40 | tearDown(() async { 41 | await Simulator.reset(); 42 | }); 43 | 44 | test('out depends on out', () async { 45 | final mod = TopModule(Logic()); 46 | await mod.build(); 47 | 48 | final vectors = [ 49 | Vector({'a_top': 0}, {'bundle_top': 1}), 50 | Vector({'a_top': 1}, {'bundle_top': 6}), 51 | ]; 52 | await SimCompare.checkFunctionalVector(mod, vectors); 53 | final simResult = SimCompare.iverilogVector(mod, vectors); 54 | expect(simResult, equals(true)); 55 | }); 56 | } 57 | -------------------------------------------------------------------------------- /test/vcd_parser_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // vcd_parser_test.dart 5 | // Tests for the VcdParser 6 | // 7 | // 2023 February 7 8 | // Author: Max Korbel 9 | 10 | @TestOn('vm') 11 | library; 12 | 13 | import 'dart:io'; 14 | 15 | import 'package:rohd/rohd.dart'; 16 | import 'package:rohd/src/utilities/vcd_parser.dart'; 17 | import 'package:test/test.dart'; 18 | 19 | void main() { 20 | test('VCD parser can parse Icarus Verilog generated VCD file', () { 21 | final vcdContents = 22 | File('test/example_icarus_waves.vcd').readAsStringSync(); 23 | for (var countI = 1; countI < 10; countI++) { 24 | expect( 25 | VcdParser.confirmValue( 26 | vcdContents, 27 | 'sampled', 28 | (10 * countI + 5) * 1000, 29 | LogicValue.ofInt(countI.isEven ? countI - 2 : countI - 1, 8), 30 | ), 31 | isTrue, 32 | ); 33 | } 34 | }); 35 | 36 | test('VCD parser can parse Verilator generated VCD file', () { 37 | // NOTE: this one is extra interesting since initial values matter and it 38 | // doesn't have a dumpvars section 39 | final vcdContents = 40 | File('test/example_verilator_waves.vcd').readAsStringSync(); 41 | for (var countI = 1; countI < 10; countI++) { 42 | expect( 43 | VcdParser.confirmValue( 44 | vcdContents, 45 | 'sampled', 46 | (10 * countI + 5) * 1000, 47 | LogicValue.ofInt(countI.isEven ? countI - 2 : countI - 1, 8), 48 | ), 49 | isTrue, 50 | ); 51 | } 52 | }); 53 | } 54 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A05-logic-math-compare.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Simple logical, mathematical, and comparison operations" 3 | permalink: /docs/logic-math-compare/ 4 | excerpt: "Simple logical, mathematical, and comparison operations" 5 | last_modified_at: 2025-7-24 6 | toc: true 7 | --- 8 | 9 | Logical operations on signals are very similar to those in SystemVerilog. 10 | 11 | ```dart 12 | a_bar <= ~a; // not 13 | a_and_b <= a & b; // and 14 | a_or_b <= a | b; // or 15 | a_xor_b <= a ^ b; // xor 16 | and_a <= a.and(); // unary and 17 | or_a <= a.or(); // unary or 18 | xor_a <= a.xor(); // unary xor 19 | a_pow_b <= a.pow(b);// exponent 20 | a_plus_b <= a + b; // addition 21 | a_sub_b <= a - b; // subtraction 22 | a_times_b <= a * b; // multiplication 23 | a_div_b <= a / b; // division 24 | a_mod_b <= a % b; // modulo 25 | a_eq_b <= a.eq(b) // equality NOTE: == is for Object equality of Logic's 26 | a_neq_b <= a.neq(b) // inequality NOTE: != is for Object inequality of Logic's 27 | a_lt_b <= a.lt(b) // less than NOTE: < is for conditional assignment 28 | a_lte_b <= a.lte(b) // less than or equal NOTE: <= is for assignment 29 | a_gt_b <= a.gt(b) // greater than 30 | a_gt_b <= (a > b) // greater than (alt) NOTE: careful with order of operations, > needs parentheses in this case 31 | a_gte_b <= a.gte(b) // greater than or equal 32 | a_gte_b <= (a >= b) // greater than or equal (alt) NOTE: careful with order of operations, >= needs parentheses in this case 33 | answer <= mux(selectA, a, b) // answer = selectA ? a : b 34 | ``` 35 | -------------------------------------------------------------------------------- /test/example_verilator_waves.vcd: -------------------------------------------------------------------------------- 1 | $version Generated by VerilatedVcd $end 2 | $timescale 1ps $end 3 | $scope module $end 4 | $scope module cosim_wrapper $end 5 | $scope module external_module $end 6 | $var wire 1 # clk $end 7 | $var wire 1 $ push_valid $end 8 | $var wire 8 % push_data [7:0] $end 9 | $var wire 8 & sampled [7:0] $end 10 | $upscope $end 11 | $upscope $end 12 | $upscope $end 13 | $enddefinitions $end 14 | 15 | 16 | #0 17 | 0# 18 | 0$ 19 | b00000000 % 20 | b00000000 & 21 | #1 22 | #5000 23 | 1# 24 | #5001 25 | 1$ 26 | #5002 27 | #10000 28 | 0# 29 | #10001 30 | #15000 31 | 1# 32 | #15001 33 | 0$ 34 | b00000001 % 35 | #15002 36 | #20000 37 | 0# 38 | #20001 39 | #25000 40 | 1# 41 | #25001 42 | 1$ 43 | b00000010 % 44 | #25002 45 | #30000 46 | 0# 47 | #30001 48 | #35000 49 | 1# 50 | b00000010 & 51 | #35001 52 | 0$ 53 | b00000011 % 54 | #35002 55 | #40000 56 | 0# 57 | #40001 58 | #45000 59 | 1# 60 | #45001 61 | 1$ 62 | b00000100 % 63 | #45002 64 | #50000 65 | 0# 66 | #50001 67 | #55000 68 | 1# 69 | b00000100 & 70 | #55001 71 | 0$ 72 | b00000101 % 73 | #55002 74 | #60000 75 | 0# 76 | #60001 77 | #65000 78 | 1# 79 | #65001 80 | 1$ 81 | b00000110 % 82 | #65002 83 | #70000 84 | 0# 85 | #70001 86 | #75000 87 | 1# 88 | b00000110 & 89 | #75001 90 | 0$ 91 | b00000111 % 92 | #75002 93 | #80000 94 | 0# 95 | #80001 96 | #85000 97 | 1# 98 | #85001 99 | 1$ 100 | b00001000 % 101 | #85002 102 | #90000 103 | 0# 104 | #90001 105 | #95000 106 | 1# 107 | b00001000 & 108 | #95001 109 | 0$ 110 | b00001001 % 111 | #95002 112 | #100000 113 | 0# 114 | #100001 115 | #100002 116 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_8/answers/exercise_3_pipeline.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | import 'package:test/test.dart'; 3 | 4 | class Pipeline4Stages extends Module { 5 | late final Pipeline pipeline; 6 | 7 | Logic get result => output('result'); 8 | 9 | Pipeline4Stages(Logic clk, Logic reset, Logic a) 10 | : super(name: 'pipeline_4_stages') { 11 | clk = addInput('clk', clk); 12 | reset = addInput(reset.name, reset); 13 | a = addInput(a.name, a, width: a.width); 14 | 15 | final result = addOutput('result', width: 64); 16 | 17 | pipeline = Pipeline(clk, reset: reset, resetValues: { 18 | result: Const(0) 19 | }, stages: [ 20 | ...List.generate( 21 | 4, (stage) => (p) => [p.get(a) < p.get(a) + (p.get(a) * stage)]) 22 | ]); 23 | 24 | result <= pipeline.get(a).zeroExtend(result.width); 25 | } 26 | } 27 | 28 | void main(List args) async { 29 | test('should return the the matching stage result if input is 5.', () async { 30 | final a = Logic(name: 'a', width: 8); 31 | final reset = Logic(name: 'reset'); 32 | final clk = SimpleClockGenerator(10).clk; 33 | 34 | final pipe = Pipeline4Stages(clk, reset, a); 35 | await pipe.build(); 36 | 37 | // print(pipe.generateSynth()); 38 | 39 | a.inject(5); 40 | reset.inject(1); 41 | 42 | Simulator.registerAction(10, () => reset.put(0)); 43 | 44 | WaveDumper(pipe, outputPath: 'answer_1.vcd'); 45 | 46 | Simulator.registerAction(50, () async { 47 | // stage 4 / result: 30 + (30 * 3) = 120 48 | expect(pipe.result.value.toInt(), 120); 49 | }); 50 | 51 | Simulator.setMaxSimTime(100); 52 | await Simulator.run(); 53 | }); 54 | } 55 | -------------------------------------------------------------------------------- /test/previous_value_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // previous_value_test.dart 5 | // Tests for Logic.previousValue 6 | // 7 | // 2023 June 16 8 | // Author: Max Korbel 9 | 10 | import 'dart:async'; 11 | 12 | import 'package:rohd/rohd.dart'; 13 | import 'package:test/test.dart'; 14 | 15 | void main() { 16 | tearDown(() async { 17 | await Simulator.reset(); 18 | }); 19 | 20 | test('sample on flop with listen', () async { 21 | final clk = SimpleClockGenerator(10).clk; 22 | 23 | final a = Logic()..put(0); 24 | 25 | final b = flop(clk, a); 26 | final c = flop(clk, b); 27 | 28 | Simulator.registerAction(11, () => a.put(1)); 29 | 30 | clk.posedge.listen((event) { 31 | if (Simulator.time == 25) { 32 | expect(c.previousValue!.toInt(), 0); 33 | expect(c.value.toInt(), 1); 34 | } 35 | }); 36 | 37 | Simulator.setMaxSimTime(200); 38 | await Simulator.run(); 39 | }); 40 | 41 | test('sample on flop with await', () async { 42 | final clk = SimpleClockGenerator(10).clk; 43 | 44 | final a = Logic()..put(0); 45 | 46 | final b = flop(clk, a); 47 | final c = flop(clk, b); 48 | 49 | Simulator.registerAction(11, () => a.put(1)); 50 | 51 | Future clkLoop() async { 52 | while (!Simulator.simulationHasEnded) { 53 | await clk.nextPosedge; 54 | if (Simulator.time == 25) { 55 | expect(c.previousValue!.toInt(), 0); 56 | expect(c.value.toInt(), 1); 57 | } 58 | } 59 | } 60 | 61 | unawaited(clkLoop()); 62 | 63 | Simulator.setMaxSimTime(200); 64 | await Simulator.run(); 65 | }); 66 | } 67 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A16-simulator.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "ROHD Simulator" 3 | permalink: /docs/simulator/ 4 | excerpt: "ROHD Simulator" 5 | last_modified_at: 2022-12-06 6 | toc: true 7 | --- 8 | 9 | The ROHD simulator is a static class accessible as [`Simulator`](https://intel.github.io/rohd/rohd/Simulator-class.html) which implements a simple event-based simulator. All `Logic`s in Dart have `glitch` events which propogate values to connected `Logic`s downstream. In this way, ROHD propogates values across the entire graph representation of the hardware (without any `Simulator` involvement required). The simulator has a concept of (unitless) time, and arbitrary Dart functions can be registered to occur at arbitraty times in the simulator. Asking the simulator to run causes it to iterate through all registered timestamps and execute the functions in chronological order. When these functions deposit signals on `Logic`s, it propogates values across the hardware. The simulator has a number of events surrounding execution of a timestamp tick so that things like `FlipFlop`s can know when clocks and signals are glitch-free. 10 | 11 | - To register a function at an arbitraty timestamp, use `Simulator.registerAction` 12 | - To set a maximum simulation time, use `Simulator.setMaxSimTime` 13 | - To immediately end the simulation at the end of the current timestamp, use `Simulator.endSimulation` 14 | - To run just the next timestamp, use `Simulator.tick` 15 | - To run simulator ticks until completion, use `Simulator.run` 16 | - To reset the simulator, use `Simulator.reset` 17 | - Note that this only resets the `Simulator` and not any `Module`s or `Logic` values 18 | - To add an action to the Simulator in the *current* timestep, use `Simulator.injectAction`. 19 | -------------------------------------------------------------------------------- /test/arithmetic_shift_right_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // arithmetic_shift_right_test.dart 5 | // Tests related to special circumstances around arithmetic right-shift. 6 | // 7 | // 2023 March 1 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'package:rohd/src/utilities/simcompare.dart'; 12 | import 'package:test/test.dart'; 13 | 14 | class SraUnsignedTestModule extends Module { 15 | Logic get result => output('result'); 16 | SraUnsignedTestModule(Logic toShift, Logic shiftAmount, Logic maskBit) { 17 | toShift = addInput('toShift', toShift, width: toShift.width); 18 | shiftAmount = 19 | addInput('shiftAmount', shiftAmount, width: shiftAmount.width); 20 | maskBit = addInput('maskBit', maskBit); 21 | 22 | addOutput('result', width: toShift.width); 23 | 24 | result <= (toShift >> shiftAmount) & maskBit.replicate(toShift.width); 25 | } 26 | } 27 | 28 | void main() { 29 | test('arithmetic shift right and mask', () async { 30 | final mod = 31 | SraUnsignedTestModule(Logic(width: 32), Logic(width: 32), Logic()); 32 | await mod.build(); 33 | final vectors = [ 34 | Vector({'toShift': 0xe0000000, 'shiftAmount': 4, 'maskBit': 1}, 35 | {'result': 0xfe000000}), 36 | Vector({'toShift': 0x10000000, 'shiftAmount': 4, 'maskBit': 1}, 37 | {'result': 0x01000000}), 38 | Vector({'toShift': 0xe0000000, 'shiftAmount': 4, 'maskBit': 0}, 39 | {'result': 0}), 40 | ]; 41 | await SimCompare.checkFunctionalVector(mod, vectors); 42 | final simResult = SimCompare.iverilogVector(mod, vectors); 43 | expect(simResult, equals(true)); 44 | }); 45 | } 46 | -------------------------------------------------------------------------------- /.github/ISSUE_TEMPLATE/bug_report.yml: -------------------------------------------------------------------------------- 1 | name: Bug Report 2 | description: Report a problem. 3 | labels: bug 4 | 5 | body: 6 | - type: markdown 7 | attributes: 8 | value: Thanks for taking the time to fill out this bug report! 9 | 10 | - type: textarea 11 | attributes: 12 | label: Describe the bug 13 | description: A clear and concise description of what the bug is. 14 | validations: 15 | required: true 16 | 17 | - type: textarea 18 | attributes: 19 | label: To Reproduce 20 | description: If possible, please include code that reproduces the failure. 21 | placeholder: | 22 | Steps to reproduce the behavior: 23 | 1. Use class ... for ... 24 | 2. Run a simulation with ... 25 | 3. See error 26 | 27 | - type: textarea 28 | attributes: 29 | label: Expected behavior 30 | description: A clear and concise description of what you expected to happen. 31 | 32 | - type: textarea 33 | attributes: 34 | label: Actual behavior 35 | description: What you observed instead of the expected behavior? 36 | 37 | - type: input 38 | attributes: 39 | label: "Additional: Dart SDK info" 40 | description: Please paste the output of 'dart --version'. 41 | placeholder: "> dart --version" 42 | 43 | - type: textarea 44 | attributes: 45 | label: "Additional: pubspec.yaml" 46 | description: > 47 | Please paste the contents of your 'pubspec.yaml' file and identify the 48 | version of ROHD you're using. 49 | placeholder: your 'pubspec.yaml' file here... 50 | render: yaml 51 | 52 | - type: textarea 53 | attributes: 54 | label: "Additional: Context" 55 | description: Add any other context about the problem here. 56 | -------------------------------------------------------------------------------- /test/multimodule3_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // multimodule3_test.dart 5 | // Unit tests for a hierarchy of multiple modules and 6 | // multiple instantiation (another type) 7 | // 8 | // 2021 June 30 9 | // Author: Max Korbel 10 | 11 | import 'package:rohd/rohd.dart'; 12 | import 'package:rohd/src/modules/passthrough.dart'; 13 | import 'package:rohd/src/utilities/simcompare.dart'; 14 | import 'package:test/test.dart'; 15 | 16 | // mostly all outputs 17 | class InnerModule2 extends Module { 18 | Logic get z => output('z'); 19 | InnerModule2() : super(name: 'innermodule2') { 20 | addOutput('z'); 21 | z <= Const(1); 22 | } 23 | } 24 | 25 | class InnerModule1 extends Module { 26 | Logic get y => output('y'); 27 | Logic get m => output('m'); 28 | InnerModule1() : super(name: 'innermodule1') { 29 | addOutput('m'); 30 | m <= Const(0); 31 | addOutput('y'); 32 | y <= Passthrough(InnerModule2().z).out; 33 | } 34 | } 35 | 36 | class TopModule extends Module { 37 | Logic get x => output('x'); 38 | TopModule() : super(name: 'topmod') { 39 | addOutput('x'); 40 | final im1 = InnerModule1(); 41 | x <= im1.y | im1.m; 42 | } 43 | } 44 | 45 | void main() { 46 | tearDown(() async { 47 | await Simulator.reset(); 48 | }); 49 | 50 | group('simcompare', () { 51 | test('multimodules3', () async { 52 | final ftm = TopModule(); 53 | await ftm.build(); 54 | final vectors = [ 55 | Vector({}, {'x': 1}), 56 | ]; 57 | await SimCompare.checkFunctionalVector(ftm, vectors); 58 | final simResult = SimCompare.iverilogVector(ftm, vectors); 59 | expect(simResult, equals(true)); 60 | }); 61 | }); 62 | } 63 | -------------------------------------------------------------------------------- /test/traverseable_collection_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // traverseable_collection_test.dart 5 | // Tests for `TraverseableCollection`. 6 | // 7 | // 2024 June 12 8 | // Author: Max Korbel 9 | 10 | // ignore_for_file: cascade_invocations 11 | 12 | import 'package:rohd/src/collections/traverseable_collection.dart'; 13 | import 'package:test/test.dart'; 14 | 15 | void main() { 16 | test('simple traverseable collection usage', () { 17 | final c = TraverseableCollection(); 18 | 19 | c.add(10); 20 | 21 | c.addAll([1, 2, 3]); 22 | 23 | expect(c.length, 4); 24 | 25 | final removed = c.remove(2); 26 | expect(removed, isTrue); 27 | 28 | final removedAgain = c.remove(2); 29 | expect(removedAgain, isFalse); 30 | 31 | expect(c.length, 3); 32 | 33 | expect(c[0], 10); 34 | expect(c[1], 1); 35 | expect(c[2], 3); 36 | 37 | expect(c.contains(10), isTrue); 38 | expect(c.contains(3), isTrue); 39 | 40 | for (final item in c) { 41 | expect(c.contains(item), isTrue); 42 | } 43 | 44 | expect(c.isEmpty, isFalse); 45 | 46 | c.clear(); 47 | 48 | expect(c.isEmpty, isTrue); 49 | expect(c.length, 0); 50 | }); 51 | 52 | test('unmodifiable traverseable collection cannot be changed', () { 53 | final c = TraverseableCollection(); 54 | final v = UnmodifiableTraverseableCollectionView(c); 55 | 56 | c.addAll([1, 2, 3]); 57 | 58 | expect(() => v.add(4), throwsUnsupportedError); 59 | expect(() => v.addAll([5, 6]), throwsUnsupportedError); 60 | expect(() => v.remove(1), throwsUnsupportedError); 61 | 62 | expect(v.length, 3); 63 | expect(v[0], 1); 64 | expect(v.contains(2), isTrue); 65 | }); 66 | } 67 | -------------------------------------------------------------------------------- /test/duplicate_detection_set_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // duplicate_detection_set_test.dart 5 | // Unit tests for DuplicateDetectionSet 6 | // 7 | // 2022 November 11 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:rohd/src/collections/duplicate_detection_set.dart'; 11 | import 'package:test/test.dart'; 12 | 13 | void main() { 14 | group('Add Function: ', () { 15 | test( 16 | 'should return duplicates if duplicate value exists ' 17 | 'through addAll method', () async { 18 | final testDuplicateSet = DuplicateDetectionSet()..addAll([1, 2, 1]); 19 | 20 | expect(testDuplicateSet.hasDuplicates, equals(true)); 21 | expect(testDuplicateSet.duplicates, equals({1})); 22 | }); 23 | test( 24 | 'should return duplicates if duplicate value exists through add method', 25 | () async { 26 | final testDuplicateSet = DuplicateDetectionSet() 27 | ..addAll([1, 2, 3]) 28 | ..add(1); 29 | 30 | expect(testDuplicateSet.hasDuplicates, equals(true)); 31 | expect(testDuplicateSet.duplicates, equals({1})); 32 | }); 33 | }); 34 | 35 | group('remove function: ', () { 36 | test('should return value if removed value are not duplicate', () async { 37 | final testDuplicateSet = DuplicateDetectionSet()..addAll([3, 1, 2]); 38 | expect(testDuplicateSet.remove(1), equals(true)); 39 | }); 40 | test('should return exception if removed value that are duplicate', 41 | () async { 42 | final testDuplicateSet = DuplicateDetectionSet() 43 | ..addAll([3, 1, 2, 1]); 44 | expect(() { 45 | testDuplicateSet.remove(1); 46 | }, throwsException); 47 | }); 48 | }); 49 | } 50 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_3/answers/exercise_sv.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | import 'package:test/test.dart'; 3 | import 'helper.dart'; 4 | 5 | class FullSubtractor extends Module { 6 | FullSubtractor(Logic a, Logic b, Logic borrowIn) 7 | : super(name: 'full_subtractor') { 8 | // Add Input 9 | a = addInput('a', a); 10 | b = addInput('b', b); 11 | borrowIn = addInput('borrowIn', borrowIn); 12 | 13 | // Add Output 14 | final borrowOut = addOutput('borrowOut'); 15 | final diff = addOutput('diff'); 16 | 17 | // Logic 18 | final xorAB = a ^ b; 19 | diff <= xorAB ^ borrowIn; 20 | borrowOut <= (~xorAB & borrowIn) | (~a & b); 21 | } 22 | // getter for output 23 | Logic get borrowOut => output('borrowOut'); 24 | Logic get diff => output('diff'); 25 | } 26 | 27 | void main() async { 28 | final a = Logic(name: 'a'); 29 | final b = Logic(name: 'b'); 30 | final borrowIn = Logic(name: 'borrow_in'); 31 | 32 | final fSub = FullSubtractor(a, b, borrowIn); 33 | await fSub.build(); 34 | 35 | // ignore: avoid_print 36 | print(fSub.generateSynth()); 37 | 38 | test('should return 0 when a and b equal 1', () async { 39 | a.put(1); 40 | b.put(1); 41 | borrowIn.put(0); 42 | 43 | expect(fSub.diff.value.toInt(), equals(0)); 44 | }); 45 | 46 | test('should return true if results matched truth table', () async { 47 | for (var i = 0; i <= 1; i++) { 48 | for (var j = 0; j <= 1; j++) { 49 | for (var k = 0; k <= 1; k++) { 50 | a.put(i); 51 | b.put(j); 52 | borrowIn.put(k); 53 | 54 | final res = fsTruthTable(i, j, k); 55 | 56 | expect(fSub.diff.value.toInt(), res.diff); 57 | expect(fSub.borrowOut.value.toInt(), res.borrowOut); 58 | } 59 | } 60 | } 61 | }); 62 | } 63 | -------------------------------------------------------------------------------- /test/multimodule4_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // multimodule4_test.dart 5 | // Unit tests for a hierarchy of multiple modules and multiple instantiation 6 | // (another type) 7 | // 8 | // 2021 June 30 9 | // Author: Max Korbel 10 | 11 | import 'package:rohd/rohd.dart'; 12 | import 'package:rohd/src/modules/passthrough.dart'; 13 | import 'package:test/test.dart'; 14 | 15 | // mostly all inputs 16 | class InnerModule2 extends Module { 17 | Logic get z => output('z'); 18 | InnerModule2() : super(name: 'innermodule2') { 19 | addOutput('z'); 20 | z <= Const(1); 21 | } 22 | } 23 | 24 | class InnerModule1 extends Module { 25 | InnerModule1(Logic y) : super(name: 'innermodule1') { 26 | y = addInput('y', y); 27 | final m = Logic(); 28 | m <= Passthrough(InnerModule2().z).out | y; 29 | } 30 | } 31 | 32 | class TopModule extends Module { 33 | TopModule(Logic x) : super(name: 'topmod') { 34 | x = addInput('x', x); 35 | InnerModule1(x); 36 | } 37 | } 38 | 39 | void main() { 40 | tearDown(() async { 41 | await Simulator.reset(); 42 | }); 43 | 44 | test('multimodules4', () async { 45 | final ftm = TopModule(Logic()); 46 | await ftm.build(); 47 | 48 | // find a module with 'z' output 2 levels deep 49 | assert( 50 | ftm.subModules 51 | .where((pIn1) => pIn1.subModules 52 | .where((pIn2) => pIn2.outputs.containsKey('z')) 53 | .isNotEmpty) 54 | .isNotEmpty, 55 | 'Should find a z two levels deep'); 56 | 57 | final synth = ftm.generateSynth(); 58 | 59 | // "z = 1" means it correctly traversed down from inputs 60 | assert(synth.contains('z = 1'), 61 | 'Should correctly traverse from inputs to z=1'); 62 | }); 63 | } 64 | -------------------------------------------------------------------------------- /lib/src/modules/clkgen.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // clkgen.dart 5 | // A simple clock generator (non-synthesizable) 6 | // 7 | // 2021 May 7 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// A very simple clock generator. Generates a non-synthesizable SystemVerilog 13 | /// representation. 14 | class SimpleClockGenerator extends Module with SystemVerilog { 15 | /// The number of time units between repetitions of this clock. 16 | /// 17 | /// For example, if the [clockPeriod] is 10, then the frequency is 1/10, 18 | /// and the time between positive edges of the generated clock is 10. 19 | final int clockPeriod; 20 | 21 | /// The generated clock. 22 | late final Logic clk = output('clk'); 23 | 24 | /// Constructs a very simple clock generator. Generates a non-synthesizable 25 | /// SystemVerilog representation. 26 | /// 27 | /// Set the frequency via [clockPeriod]. 28 | SimpleClockGenerator(this.clockPeriod, {super.name = 'clkgen'}) { 29 | addOutput('clk'); 30 | 31 | clk.makeUnassignable( 32 | reason: 'Generated clock from $this cannot be assigned'); 33 | 34 | clk.glitch.listen((args) { 35 | Simulator.registerAction(Simulator.time + clockPeriod ~/ 2, () { 36 | clk.put(~clk.value); 37 | }); 38 | }); 39 | clk.put(0); 40 | } 41 | 42 | @override 43 | String instantiationVerilog( 44 | String instanceType, String instanceName, Map ports) { 45 | assert(ports.length == 1, 46 | 'SimpleClockGenerator has exactly one output and no inputs.'); 47 | 48 | final clk = ports['clk']!; 49 | return ''' 50 | // $instanceName 51 | initial begin 52 | $clk = 0; 53 | forever begin 54 | #${clockPeriod ~/ 2}; 55 | $clk = ~$clk; 56 | end 57 | end 58 | '''; 59 | } 60 | } 61 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_9/rohd_vf_example/lib/counter.dart: -------------------------------------------------------------------------------- 1 | import 'package:rohd/rohd.dart'; 2 | 3 | enum CounterDirection { inward, outward, misc } 4 | 5 | /// A simple [Interface] for [MyCounter]. 6 | class MyCounterInterface extends Interface { 7 | Logic get en => port('en'); 8 | Logic get reset => port('reset'); 9 | Logic get val => port('val'); 10 | Logic get clk => port('clk'); 11 | 12 | final int width; 13 | MyCounterInterface({this.width = 8}) { 14 | setPorts( 15 | [Logic.port('en'), Logic.port('reset')], [CounterDirection.inward]); 16 | 17 | setPorts([ 18 | Logic.port('val', width), 19 | ], [ 20 | CounterDirection.outward 21 | ]); 22 | 23 | setPorts([Logic.port('clk')], [CounterDirection.misc]); 24 | } 25 | 26 | @override 27 | MyCounterInterface clone() => MyCounterInterface(width: width); 28 | } 29 | 30 | /// A simple counter which increments once per [clk] edge whenever 31 | /// [en] is high, and [reset]s to 0, with output [val]. 32 | class MyCounter extends Module { 33 | Logic get clk => input('clk'); 34 | Logic get en => input('en'); 35 | Logic get reset => input('reset'); 36 | Logic get val => output('val'); 37 | 38 | late final MyCounterInterface counterintf; 39 | 40 | MyCounter(MyCounterInterface intf) : super(name: 'counter') { 41 | counterintf = addInterfacePorts(counterintf, 42 | inputTags: {CounterDirection.inward, CounterDirection.misc}, 43 | outputTags: {CounterDirection.outward}); 44 | 45 | _buildLogic(); 46 | } 47 | 48 | void _buildLogic() { 49 | final nextVal = Logic(name: 'nextVal', width: counterintf.width); 50 | 51 | nextVal <= counterintf.val + 1; 52 | 53 | Sequential(clk, [ 54 | If(reset, then: [ 55 | counterintf.val < 0 56 | ], orElse: [ 57 | If(en, then: [counterintf.val < nextVal]) 58 | ]) 59 | ]); 60 | } 61 | } 62 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/models/tree_model.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // tree_model.dart 5 | // Model of the module tree hierarchy. 6 | // 7 | // 2024 January 5 8 | // Author: Yao Jing Quek 9 | 10 | import 'package:rohd_devtools_extension/rohd_devtools/models/signal_model.dart'; 11 | 12 | class TreeModel { 13 | final String name; 14 | final List inputs; 15 | final List outputs; 16 | final List subModules; 17 | 18 | TreeModel({ 19 | required this.name, 20 | required this.inputs, 21 | required this.outputs, 22 | required this.subModules, 23 | }); 24 | 25 | factory TreeModel.fromJson(Map json) { 26 | List inputSignalsList = []; 27 | List outputSignalsList = []; 28 | 29 | for (var inputSignal in json['inputs'].entries) { 30 | SignalModel signal = SignalModel.fromMap({ 31 | 'name': inputSignal.key, 32 | 'direction': 'Input', 33 | 'value': inputSignal.value['value'], 34 | 'width': inputSignal.value['width'], 35 | }); 36 | inputSignalsList.add(signal); 37 | } 38 | 39 | for (var outputSignal in json['outputs'].entries) { 40 | SignalModel signal = SignalModel.fromMap({ 41 | 'name': outputSignal.key, 42 | 'direction': 'Input', 43 | 'value': outputSignal.value['value'], 44 | 'width': outputSignal.value['width'], 45 | }); 46 | 47 | outputSignalsList.add(signal); 48 | } 49 | 50 | return TreeModel( 51 | name: json['name'], 52 | inputs: inputSignalsList, 53 | outputs: outputSignalsList, 54 | subModules: (json["subModules"] as List) 55 | .map((subModule) => TreeModel.fromJson(subModule)) 56 | .toList(), 57 | ); 58 | } 59 | } 60 | -------------------------------------------------------------------------------- /lib/src/exceptions/conditionals/write_after_read_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // write_after_read_exception.dart 5 | // An exception thrown when a "write after read" violation occurs. 6 | // 7 | // 2023 April 13 8 | // Author: Max Korbel 9 | 10 | import 'package:meta/meta.dart'; 11 | import 'package:rohd/src/exceptions/rohd_exception.dart'; 12 | 13 | /// An exception that is thrown when a "write after read" violation occurs. 14 | /// 15 | /// This is also sometimes called a "read before write" violation. 16 | class WriteAfterReadException extends RohdException { 17 | /// The path of things that caused the exception. 18 | final List? _path; 19 | 20 | /// Creates a [WriteAfterReadException]. 21 | WriteAfterReadException() : this._(); 22 | 23 | /// Creates a [WriteAfterReadException]. 24 | WriteAfterReadException._([this._path]) 25 | : super(_appendPath( 26 | 'Signal changed its value after being used' 27 | ' within one `Combinational` execution.' 28 | ' This can lead to a mismatch between simulation and synthesis.' 29 | ' You may be able to use `Combinational.ssa` to correct your' 30 | ' design with minimal refactoring.', 31 | _path)); 32 | 33 | /// Appends a [path] to the [message], if it exists. 34 | static String _appendPath(String message, List? path) { 35 | if (path == null || path.isEmpty) { 36 | return message; 37 | } 38 | return '$message\n${path.join('\n')}'; 39 | } 40 | 41 | /// Clones this [WriteAfterReadException] with an added [pathItem] item to the 42 | /// top of the path. 43 | @internal 44 | WriteAfterReadException cloneWithAddedPath(String pathItem) => 45 | WriteAfterReadException._([ 46 | pathItem, 47 | ...?_path, 48 | ]); 49 | } 50 | -------------------------------------------------------------------------------- /benchmark/wave_dump_benchmark.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // wave_dump_benchmark.dart 5 | // Benchmarking for wave dumping 6 | // 7 | // 2023 January 5 8 | // Author: Max Korbel 9 | 10 | import 'dart:io'; 11 | 12 | import 'package:benchmark_harness/benchmark_harness.dart'; 13 | import 'package:rohd/rohd.dart'; 14 | 15 | class _ModuleToDump extends Module { 16 | static const _numExtraOutputs = 50; 17 | 18 | _ModuleToDump(Logic d, Logic clk) { 19 | d = addInput('d', d); 20 | 21 | final q = addOutput('q'); 22 | 23 | for (var i = 0; i < _numExtraOutputs; i++) { 24 | addOutput('i$i') <= FlipFlop(clk, ~output('i$i')).q; 25 | } 26 | 27 | q <= FlipFlop(clk, d).q; 28 | } 29 | } 30 | 31 | class WaveDumpBenchmark extends AsyncBenchmarkBase { 32 | late _ModuleToDump _mod; 33 | late Logic _clk; 34 | 35 | static const _maxSimTime = 1000; 36 | 37 | static const _vcdTemporaryPath = 'tmp_test/wave_dump_benchmark.vcd'; 38 | 39 | WaveDumpBenchmark() : super('WaveDump'); 40 | 41 | @override 42 | Future setup() async { 43 | Simulator.setMaxSimTime(_maxSimTime); 44 | } 45 | 46 | @override 47 | Future teardown() async { 48 | if (File(_vcdTemporaryPath).existsSync()) { 49 | File(_vcdTemporaryPath).deleteSync(); 50 | } 51 | } 52 | 53 | @override 54 | Future run() async { 55 | _clk = SimpleClockGenerator(10).clk; 56 | _mod = _ModuleToDump(Logic(), _clk); 57 | await _mod.build(); 58 | 59 | WaveDumper(_mod, outputPath: _vcdTemporaryPath); 60 | 61 | await Simulator.run(); 62 | 63 | assert(Simulator.time == _maxSimTime, 'sim should run through end'); 64 | 65 | await Simulator.reset(); 66 | Simulator.setMaxSimTime(_maxSimTime); 67 | } 68 | } 69 | 70 | Future main() async { 71 | await WaveDumpBenchmark().report(); 72 | } 73 | -------------------------------------------------------------------------------- /lib/src/exceptions/logic/signal_width_mismatch_exception.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // port_width_mismatch_exception.dart 5 | // Definition for exception when a signal has the wrong width. 6 | // 7 | // 2023 June 2 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// An [Exception] thrown when a signal has the wrong width. 13 | class SignalWidthMismatchException extends RohdException { 14 | /// Constructs a new [Exception] for when a signal has the wrong width. 15 | SignalWidthMismatchException(Logic signal, int expectedWidth, 16 | {String additionalMessage = ''}) 17 | : super('Signal ${signal.name} has the wrong width.' 18 | ' Expected $expectedWidth but found ${signal.width}.' 19 | ' $additionalMessage'); 20 | 21 | /// Constructs a new [Exception] for when a dynamic has a wrong width. 22 | SignalWidthMismatchException.forDynamic( 23 | dynamic val, int expectedWidth, int actualWidth, 24 | {String additionalMessage = ''}) 25 | : super('Value $val has the wrong width.' 26 | ' Expected $expectedWidth but found $actualWidth.' 27 | ' $additionalMessage'); 28 | 29 | /// Constructs a new [Exception] for when a dynamic has no width or it could 30 | /// not be inferred. 31 | SignalWidthMismatchException.forNull(dynamic val) 32 | : super('Could not infer width of input $val.' 33 | ' Please provide a valid width.'); 34 | 35 | /// Constructs a new [Exception] for when a dynamic has a wrong width. 36 | SignalWidthMismatchException.forWidthOverflow(int actualWidth, int maxWidth, 37 | {String? customMessage}) 38 | : super(customMessage ?? 39 | 'Value has the wrong width.' 40 | ' Expected $actualWidth to be less than' 41 | ' or equal to $maxWidth.'); 42 | } 43 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/services/tree_service.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2024-2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // tree_service.dart 5 | // Services for tree logic. 6 | // 7 | // 2024 January 5 8 | // Author: Yao Jing Quek 9 | 10 | import 'dart:convert'; 11 | 12 | import 'package:devtools_app_shared/service.dart'; 13 | import 'package:rohd_devtools_extension/rohd_devtools/models/tree_model.dart'; 14 | 15 | class TreeService { 16 | final invokeFunc = 'ModuleTree.instance.hierarchyJSON'; 17 | final EvalOnDartLibrary rohdControllerEval; 18 | final Disposable evalDisposable; 19 | 20 | TreeService(this.rohdControllerEval, this.evalDisposable); 21 | 22 | Future evalModuleTree() async { 23 | final treeInstance = await rohdControllerEval.evalInstance( 24 | invokeFunc, 25 | isAlive: evalDisposable, 26 | ); 27 | 28 | final treeObj = jsonDecode(treeInstance.valueAsString ?? '') as Map; 29 | 30 | if (treeObj['status'] == 'fail') { 31 | print('error'); 32 | 33 | return null; 34 | } else { 35 | return TreeModel.fromJson(jsonDecode(treeInstance.valueAsString ?? "")); 36 | } 37 | } 38 | 39 | static bool isNodeOrDescendentMatching( 40 | TreeModel module, String? treeSearchTerm) { 41 | if (module.name.toLowerCase().contains(treeSearchTerm!.toLowerCase())) { 42 | return true; 43 | } 44 | 45 | for (TreeModel childModule in module.subModules) { 46 | if (isNodeOrDescendentMatching(childModule, treeSearchTerm)) { 47 | return true; 48 | } 49 | } 50 | return false; 51 | } 52 | 53 | Future refreshModuleTree() { 54 | return rohdControllerEval 55 | .evalInstance(invokeFunc, isAlive: evalDisposable) 56 | .then((treeInstance) => 57 | TreeModel.fromJson(jsonDecode(treeInstance.valueAsString ?? "{}"))); 58 | } 59 | } 60 | -------------------------------------------------------------------------------- /test/shuffle_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // shuffle_test.dart 5 | // Tests related to shuffled bits 6 | // 7 | // 2022 December 21 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | import 'package:rohd/src/modules/passthrough.dart'; 12 | import 'package:rohd/src/utilities/simcompare.dart'; 13 | import 'package:test/test.dart'; 14 | 15 | class Shuffler extends Module { 16 | final int payloadWidth; 17 | Shuffler(Logic payloadIn1, Logic payloadIn2) 18 | : payloadWidth = payloadIn1.width + payloadIn2.width { 19 | payloadIn1 = addInput('payloadIn1', payloadIn1, width: payloadIn1.width); 20 | payloadIn2 = addInput('payloadIn2', payloadIn2, width: payloadIn2.width); 21 | final payloadOut = addOutput('payloadOut', width: payloadWidth); 22 | 23 | final innerPayload1 = Logic(name: 'innerPayload1', width: payloadIn1.width) 24 | ..gets(Passthrough(payloadIn1).out); 25 | final innerPayload2 = Logic(name: 'innerPayload2', width: payloadIn2.width) 26 | ..gets(Passthrough(payloadIn2).out); 27 | 28 | payloadOut <= 29 | List.generate( 30 | payloadWidth, 31 | (index) => index.isEven 32 | ? innerPayload1[index ~/ 2] 33 | : innerPayload2[index ~/ 2], 34 | ).reversed.toList().rswizzle(); 35 | } 36 | } 37 | 38 | void main() { 39 | tearDown(() async { 40 | await Simulator.reset(); 41 | }); 42 | 43 | test('shuffle test', () async { 44 | final gtm = Shuffler(Logic(width: 8), Logic(width: 8)); 45 | await gtm.build(); 46 | final vectors = [ 47 | Vector({'payloadIn1': 0xff, 'payloadIn2': 0}, {'payloadOut': 0xaaaa}), 48 | ]; 49 | await SimCompare.checkFunctionalVector(gtm, vectors); 50 | final simResult = SimCompare.iverilogVector(gtm, vectors); 51 | expect(simResult, equals(true)); 52 | }); 53 | } 54 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_5/answers/full_subtractor.dart: -------------------------------------------------------------------------------- 1 | // ignore_for_file: avoid_print 2 | 3 | import 'package:rohd/rohd.dart'; 4 | import 'package:test/test.dart'; 5 | import '../../chapter_3/answers/helper.dart'; 6 | 7 | class FullSubtractorResult { 8 | final diff = Logic(name: 'diff'); 9 | final borrow = Logic(name: 'borrow'); 10 | } 11 | 12 | class FullSubtractor extends Module { 13 | FullSubtractor(Logic a, Logic b, Logic borrowIn) { 14 | // Declare input and output 15 | a = addInput('a', a); 16 | b = addInput('b', b); 17 | borrowIn = addInput('borrowIn', borrowIn); 18 | 19 | final diff = addOutput('diff'); 20 | final borrow = addOutput('borrow'); 21 | 22 | // Logic 23 | final xorAB = a ^ b; 24 | 25 | diff <= xorAB ^ borrowIn; 26 | borrow <= (~xorAB & borrowIn) | (~a & b); 27 | } 28 | 29 | FullSubtractorResult get fsResult { 30 | final res = FullSubtractorResult(); 31 | res.diff <= output('diff'); 32 | res.borrow <= output('borrow'); 33 | 34 | return res; 35 | } 36 | } 37 | 38 | Future main() async { 39 | final a = Logic(name: 'a'); 40 | final b = Logic(name: 'b'); 41 | final borrowIn = Logic(); 42 | 43 | final diff = FullSubtractor(a, b, borrowIn); 44 | 45 | await diff.build(); 46 | 47 | print(diff.generateSynth()); 48 | 49 | test('should return true if results matched truth table', () async { 50 | for (var i = 0; i <= 1; i++) { 51 | for (var j = 0; j <= 1; j++) { 52 | for (var k = 0; k <= 1; k++) { 53 | a.put(i); 54 | b.put(j); 55 | borrowIn.put(k); 56 | 57 | final res = fsTruthTable(i, j, k); 58 | 59 | final actualDiff = diff.fsResult.diff.value.toInt(); 60 | final actualBorrowout = diff.fsResult.borrow.value.toInt(); 61 | 62 | expect(actualDiff, res.diff); 63 | expect(actualBorrowout, res.borrowOut); 64 | } 65 | } 66 | } 67 | }); 68 | } 69 | -------------------------------------------------------------------------------- /lib/src/utilities/index_utilities.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // index_utilities.dart 5 | // Code for modifying and validating indices. 6 | // 7 | // 2023 June 1 8 | // Author: Max Korbel 9 | 10 | /// A utility class for modifying and validating indices. 11 | abstract class IndexUtilities { 12 | /// Computes a modified version of an index into an array that allows for 13 | /// negative values to wrap around from the end. 14 | /// 15 | /// Guaranteed to either return an index in `[0, width)` or else throw 16 | /// an exception. 17 | /// 18 | /// If [allowWidth], then the range is `[0, width]` instead. 19 | static int wrapIndex(int originalIndex, int width, 20 | {bool allowWidth = false}) { 21 | final modifiedIndex = 22 | (originalIndex < 0) ? width + originalIndex : originalIndex; 23 | 24 | // check that it meets indexing requirements 25 | if (modifiedIndex < 0 || 26 | modifiedIndex > width || 27 | (!allowWidth && modifiedIndex == width)) { 28 | // The suggestion in the deprecation for this constructor is not available 29 | // before 2.19, so keep it in here for now. Eventually, switch to the 30 | // new one. 31 | // ignore: deprecated_member_use 32 | throw IndexError( 33 | originalIndex, 34 | width, 35 | 'IndexOutOfRange', 36 | 'Index out of range:' 37 | ' $modifiedIndex(=$originalIndex) for width $width.', 38 | width); 39 | } 40 | 41 | return modifiedIndex; 42 | } 43 | 44 | /// Validates that the range is legal. 45 | static void validateRange(int startIndex, int endIndex, 46 | {bool allowEqual = true}) { 47 | if (endIndex < startIndex || (!allowEqual && endIndex == startIndex)) { 48 | throw RangeError('End $endIndex cannot be less than start $startIndex.'); 49 | } 50 | } 51 | } 52 | -------------------------------------------------------------------------------- /test/benchmark_test.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2022-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // benchmark_test.dart 5 | // Tests that run benchmarks to make sure they don't break. 6 | // 7 | // 2022 September 28 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/src/utilities/web.dart'; 11 | import 'package:test/test.dart'; 12 | 13 | import '../benchmark/byte_enable_benchmark.dart'; 14 | import '../benchmark/comb_guard_fanout_benchmark.dart'; 15 | import '../benchmark/logic_value_of_benchmark.dart'; 16 | import '../benchmark/many_seq_and_comb_benchmark.dart'; 17 | import '../benchmark/many_submodules_benchmark.dart'; 18 | import '../benchmark/pipeline_benchmark.dart'; 19 | import '../benchmark/ssa_driver_search_benchmark.dart'; 20 | import '../benchmark/wave_dump_benchmark.dart'; 21 | 22 | void main() { 23 | group('benchmark', () { 24 | test('pipeline', () async { 25 | await PipelineBenchmark().measure(); 26 | }); 27 | 28 | test('logic value of', () { 29 | LogicValueOfBenchmark().measure(); 30 | }); 31 | 32 | test('byte enable', () { 33 | ByteEnableBenchmark().measure(); 34 | }); 35 | 36 | if (!kIsWeb) { 37 | test('waveform', () async { 38 | await WaveDumpBenchmark().measure(); 39 | }); 40 | } 41 | 42 | group('many seq and comb', () { 43 | for (final connectionType in ManySeqAndCombCombConnectionType.values) { 44 | test(connectionType.name, () async { 45 | await ManySeqAndCombBenchmark(connectionType).measure(); 46 | }); 47 | } 48 | }); 49 | 50 | test('comb guard fanout', () async { 51 | await CombGuardFanoutBenchmark().measure(); 52 | }); 53 | 54 | test('ssa driver search', () { 55 | SsaDriverSearchBenchmark().measure(); 56 | }); 57 | 58 | test('many submodule', () async { 59 | await ManySubmodulesBenchmark().measure(); 60 | }); 61 | }); 62 | } 63 | -------------------------------------------------------------------------------- /lib/src/external.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2021-2024 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // external.dart 5 | // Definition for external modules 6 | // 7 | // 2021 May 25 8 | // Author: Max Korbel 9 | 10 | import 'package:rohd/rohd.dart'; 11 | 12 | /// Represents a [Module] whose definition exists outside of this framework 13 | /// in SystemVerilog. 14 | /// 15 | /// This is useful for interacting with SystemVerilog modules. You can add 16 | /// custom behavior for how to synthesize the generated SystemVerilog as well 17 | /// as extend functionality with behavioral models or cosimulation. 18 | abstract class ExternalSystemVerilogModule extends Module with SystemVerilog { 19 | /// A map of parameter names and values to be passed to the SystemVerilog 20 | /// module. 21 | final Map? parameters; 22 | 23 | /// Constructs an instance of an externally defined SystemVerilog module. 24 | /// 25 | /// The name of the SystemVerilog module should match [definitionName] 26 | /// exactly. The [name] will be the instance name when referred to in 27 | /// generated SystemVerilog. 28 | ExternalSystemVerilogModule({ 29 | required String definitionName, 30 | this.parameters, 31 | super.name = 'external_module', 32 | }) : super(definitionName: definitionName, reserveDefinitionName: true); 33 | 34 | @override 35 | String instantiationVerilog( 36 | String instanceType, 37 | String instanceName, 38 | Map ports, 39 | ) => 40 | SystemVerilogSynthesizer.instantiationVerilogFor( 41 | module: this, 42 | instanceType: definitionName, 43 | instanceName: instanceName, 44 | ports: ports, 45 | parameters: parameters, 46 | forceStandardInstantiation: true, 47 | ); 48 | } 49 | 50 | /// Deprecated - Use [ExternalSystemVerilogModule] instead. 51 | @Deprecated('Use ExternalSystemVerilogModule instead.') 52 | typedef ExternalModule = ExternalSystemVerilogModule; 53 | -------------------------------------------------------------------------------- /benchmark/comb_guard_fanout_benchmark.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2023 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // comb_guard_fanout_benchmark.dart 5 | // Benchmarking for many `Combinational` listeners on the same signals, leading 6 | // to many `guard`s and subscription cancels in signal listeners. 7 | // 8 | // 2023 April 21 9 | // Author: Max Korbel 10 | 11 | import 'package:benchmark_harness/benchmark_harness.dart'; 12 | import 'package:rohd/rohd.dart'; 13 | 14 | class CombGuardFanout extends Module { 15 | CombGuardFanout(Logic a, 16 | {int numStatements = 10, int numCombinationals = 100}) { 17 | a = addInput('a', a, width: 8); 18 | 19 | final sxi = [a]; 20 | 21 | for (var i = 1; i < numStatements; i++) { 22 | sxi.add(listeners(sxi[i - 1])); 23 | } 24 | 25 | for (var c = 0; c < numCombinationals; c++) { 26 | Combinational([ 27 | for (var i = 1; i < numStatements; i++) 28 | Logic(width: a.width) < sxi[i - 1], 29 | ]); 30 | } 31 | } 32 | 33 | /// Adds a bunch of listeners to a modified [a] and return it. 34 | Logic listeners( 35 | Logic a, { 36 | int fanout = 5, 37 | }) { 38 | final toReturn = a + 1; 39 | for (var i = 0; i < fanout; i++) { 40 | Logic(width: a.width) <= ~toReturn; 41 | } 42 | return toReturn; 43 | } 44 | } 45 | 46 | class CombGuardFanoutBenchmark extends AsyncBenchmarkBase { 47 | final int numPuts; 48 | CombGuardFanoutBenchmark({this.numPuts = 100}) 49 | : super('CombGuardFanoutBenchmark'); 50 | 51 | CombGuardFanout? mod; 52 | final Logic a = Logic(width: 8); 53 | 54 | @override 55 | Future setup() async { 56 | mod = CombGuardFanout(a); 57 | await mod!.build(); 58 | } 59 | 60 | @override 61 | Future run() async { 62 | for (var i = 0; i < numPuts; i++) { 63 | a.put(i); 64 | } 65 | } 66 | } 67 | 68 | Future main() async { 69 | await CombGuardFanoutBenchmark().report(); 70 | } 71 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_8/counter_interface.dart: -------------------------------------------------------------------------------- 1 | // ignore_for_file: avoid_print 2 | 3 | import 'package:rohd/rohd.dart'; 4 | 5 | enum CounterDirection { inward, outward, misc } 6 | 7 | class CounterInterface extends Interface { 8 | Logic get en => port('en'); 9 | Logic get reset => port('reset'); 10 | Logic get val => port('val'); 11 | Logic get clk => port('clk'); 12 | 13 | final int width; 14 | CounterInterface({this.width = 8}) { 15 | setPorts([ 16 | Logic.port('en'), 17 | ], [ 18 | CounterDirection.inward 19 | ]); 20 | 21 | setPorts([ 22 | Logic.port('val', width), 23 | ], [ 24 | CounterDirection.outward 25 | ]); 26 | 27 | setPorts([ 28 | Logic.port('clk'), 29 | Logic.port('reset'), 30 | ], [ 31 | CounterDirection.misc 32 | ]); 33 | } 34 | 35 | @override 36 | CounterInterface clone() => CounterInterface(width: width); 37 | } 38 | 39 | class Counter extends Module { 40 | late final CounterInterface _intf; 41 | 42 | Counter(CounterInterface intf) : super(name: 'counter') { 43 | _intf = addInterfacePorts(intf, 44 | inputTags: {CounterDirection.inward, CounterDirection.misc}, 45 | outputTags: {CounterDirection.outward}); 46 | 47 | _intf.val <= 48 | flop( 49 | _intf.clk, 50 | reset: _intf.reset, 51 | (_intf.val + 1).named('nextVal'), 52 | ); 53 | } 54 | } 55 | 56 | Future main() async { 57 | final intf = CounterInterface(); 58 | intf.clk <= SimpleClockGenerator(10).clk; 59 | intf.en.inject(0); 60 | intf.reset.inject(1); 61 | 62 | final counter = Counter(intf); 63 | 64 | await counter.build(); 65 | 66 | print(counter.generateSynth()); 67 | 68 | WaveDumper(counter, 69 | outputPath: 'doc/tutorials/chapter_8/counter_interface.vcd'); 70 | Simulator.registerAction(25, () { 71 | intf.en.put(1); 72 | intf.reset.put(0); 73 | }); 74 | 75 | Simulator.setMaxSimTime(100); 76 | 77 | await Simulator.run(); 78 | } 79 | -------------------------------------------------------------------------------- /doc/tutorials/chapter_5/answers/full_adder.dart: -------------------------------------------------------------------------------- 1 | // ignore_for_file: avoid_print 2 | 3 | import 'package:rohd/rohd.dart'; 4 | import 'package:test/test.dart'; 5 | import '../../chapter_3/helper.dart'; 6 | 7 | class FullAdderResult { 8 | final sum = Logic(name: 'sum'); 9 | final cOut = Logic(name: 'c_out'); 10 | } 11 | 12 | class FullAdder extends Module { 13 | final fullAdderresult = FullAdderResult(); 14 | 15 | // Constructor 16 | FullAdder({ 17 | required Logic a, 18 | required Logic b, 19 | required Logic carryIn, 20 | super.name = 'full_adder', 21 | }) { 22 | // Declare Input Node 23 | a = addInput('a', a, width: a.width); 24 | b = addInput('b', b, width: b.width); 25 | carryIn = addInput('carry_in', carryIn, width: carryIn.width); 26 | 27 | // Declare Output Node 28 | final carryOut = addOutput('carry_out'); 29 | final sum = addOutput('sum'); 30 | 31 | final and1 = carryIn & (a ^ b); 32 | final and2 = b & a; 33 | 34 | sum <= (a ^ b) ^ carryIn; 35 | carryOut <= and1 | and2; 36 | 37 | fullAdderresult.sum <= output('sum'); 38 | fullAdderresult.cOut <= output('carry_out'); 39 | } 40 | 41 | FullAdderResult get fullAdderRes => fullAdderresult; 42 | } 43 | 44 | void main() async { 45 | final a = Logic(name: 'a'); 46 | final b = Logic(name: 'b'); 47 | final cIn = Logic(name: 'cin'); 48 | 49 | final mod = FullAdder(a: a, b: b, carryIn: cIn); 50 | await mod.build(); 51 | 52 | print(mod.generateSynth()); 53 | 54 | test('should return true if result sum similar to truth table.', () async { 55 | for (var i = 0; i <= 1; i++) { 56 | for (var j = 0; j <= 1; j++) { 57 | for (var k = 0; k <= 1; k++) { 58 | a.put(i); 59 | b.put(j); 60 | cIn.put(k); 61 | 62 | final actual = mod.fullAdderRes.sum.value.toInt(); 63 | 64 | expect(actual, faTruthTable(i, j, k).sum, 65 | reason: 'Input of a: $i, b: $j, cIn: $k; Output: $actual'); 66 | } 67 | } 68 | } 69 | }); 70 | } 71 | -------------------------------------------------------------------------------- /doc/user_guide/_docs/A14-pipelines.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "Pipelines" 3 | permalink: /docs/pipelines/ 4 | excerpt: "Pipelines" 5 | last_modified_at: 2022-12-06 6 | toc: true 7 | --- 8 | 9 | ROHD has a built-in syntax for handling pipelines in a simple & refactorable way. The below example shows a three-stage pipeline which adds 1 three times. Note that [`Pipeline`](https://intel.github.io/rohd/rohd/Pipeline-class.html) consumes a clock and a list of stages, which are each a `List Function(PipelineStageInfo p)`, where `PipelineStageInfo` has information on the value of a given signal in that stage. The `List` the same type of procedural code that can be placed in `Combinational`. 10 | 11 | ```dart 12 | Logic a; 13 | var pipeline = Pipeline(clk, 14 | stages: [ 15 | (p) => [ 16 | // the first time `get` is called, `a` is automatically pipelined 17 | p.get(a) < p.get(a) + 1 18 | ], 19 | (p) => [ 20 | p.get(a) < p.get(a) + 1 21 | ], 22 | (p) => [ 23 | p.get(a) < p.get(a) + 1 24 | ], 25 | ] 26 | ); 27 | var b = pipeline.get(a); // the output of the pipeline 28 | ``` 29 | 30 | This pipeline is very easy to refactor. If we wanted to merge the last two stages, we could simply rewrite it as: 31 | 32 | ```dart 33 | Logic a; 34 | var pipeline = Pipeline(clk, 35 | stages: [ 36 | (p) => [ 37 | p.get(a) < p.get(a) + 1 38 | ], 39 | (p) => [ 40 | p.get(a) < p.get(a) + 1, 41 | p.get(a) < p.get(a) + 1 42 | ], 43 | ] 44 | ); 45 | var b = pipeline.get(a); 46 | ``` 47 | 48 | You can also optionally add stalls and reset values for signals in the pipeline. Any signal not accessed via the `PipelineStageInfo` object is just accessed as normal, so other logic can optionally sit outside of the pipeline object. 49 | 50 | ROHD also includes a version of `Pipeline` that supports a ready/valid protocol called [`ReadyValidPipeline`](https://intel.github.io/rohd/rohd/ReadyValidPipeline-class.html). The syntax looks the same, but has some additional parameters for readys and valids. 51 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/view/rohd_devtools_page.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // rohd_devtools_page.dart 5 | // Page view for the app. 6 | // 7 | // 2025 January 28 8 | // Author: Roberto Torres 9 | 10 | import 'package:devtools_app_shared/service.dart'; 11 | import 'package:flutter/material.dart'; 12 | import 'package:flutter_bloc/flutter_bloc.dart'; 13 | import 'package:rohd_devtools_extension/rohd_devtools/rohd_devtools.dart'; 14 | import 'package:rohd_devtools_extension/rohd_devtools/ui/devtool_appbar.dart'; 15 | 16 | class RohdDevToolsPage extends StatelessWidget { 17 | const RohdDevToolsPage({super.key}); 18 | @override 19 | Widget build(BuildContext context) { 20 | return MultiBlocProvider( 21 | providers: [ 22 | BlocProvider( 23 | create: (context) => RohdServiceCubit(), 24 | ), 25 | BlocProvider( 26 | create: (context) => TreeSearchTermCubit(), 27 | ), 28 | BlocProvider( 29 | create: (context) => SelectedModuleCubit(), 30 | ), 31 | BlocProvider( 32 | create: (context) => SignalSearchTermCubit(), 33 | ), 34 | ], 35 | child: const RohdExtensionModule(), 36 | ); 37 | } 38 | } 39 | 40 | class RohdExtensionModule extends StatefulWidget { 41 | const RohdExtensionModule({super.key}); 42 | 43 | @override 44 | State createState() => _RohdExtensionModuleState(); 45 | } 46 | 47 | class _RohdExtensionModuleState extends State { 48 | late final EvalOnDartLibrary rohdControllerEval; 49 | 50 | @override 51 | void initState() { 52 | super.initState(); 53 | } 54 | 55 | @override 56 | Widget build(BuildContext context) { 57 | final screenSize = MediaQuery.of(context).size; 58 | 59 | return Scaffold( 60 | appBar: const DevtoolAppBar(), 61 | body: TreeStructurePage( 62 | screenSize: screenSize, 63 | ), 64 | ); 65 | } 66 | } 67 | -------------------------------------------------------------------------------- /rohd_devtools_extension/lib/rohd_devtools/cubit/rohd_service_cubit.dart: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2025 Intel Corporation 2 | // SPDX-License-Identifier: BSD-3-Clause 3 | // 4 | // rohd_service_cubit.dart 5 | // Cubit for the ROHD service. 6 | // 7 | // 2025 January 28 8 | // Author: Roberto Torres 9 | 10 | import 'package:devtools_app_shared/service.dart'; 11 | import 'package:devtools_extensions/devtools_extensions.dart'; 12 | import 'package:flutter_bloc/flutter_bloc.dart'; 13 | import 'package:equatable/equatable.dart'; 14 | import 'package:rohd_devtools_extension/rohd_devtools/models/tree_model.dart'; 15 | import 'package:rohd_devtools_extension/rohd_devtools/services/tree_service.dart'; 16 | 17 | part 'rohd_service_state.dart'; 18 | 19 | class RohdServiceCubit extends Cubit { 20 | TreeService? treeService; 21 | 22 | RohdServiceCubit() : super(RohdServiceInitial()) { 23 | evalModuleTree(); 24 | } 25 | 26 | Future evalModuleTree() async { 27 | await _handleModuleTreeOperation( 28 | (treeService) => treeService.evalModuleTree()); 29 | } 30 | 31 | Future refreshModuleTree() async { 32 | await _handleModuleTreeOperation( 33 | (treeService) => treeService.refreshModuleTree()); 34 | } 35 | 36 | Future _handleModuleTreeOperation( 37 | Future Function(TreeService) operation) async { 38 | try { 39 | emit(RohdServiceLoading()); 40 | if (serviceManager.service == null) { 41 | throw Exception('ServiceManager is not initialized'); 42 | } 43 | treeService ??= TreeService( 44 | EvalOnDartLibrary( 45 | 'package:rohd/src/diagnostics/inspector_service.dart', 46 | serviceManager.service!, 47 | serviceManager: serviceManager, 48 | ), 49 | Disposable(), 50 | ); 51 | final treeModel = await operation(treeService!); 52 | emit(RohdServiceLoaded(treeModel)); 53 | } catch (error, trace) { 54 | emit(RohdServiceError(error.toString(), trace)); 55 | } 56 | } 57 | } 58 | --------------------------------------------------------------------------------