├── .github └── workflows │ └── on-pr-update.yml ├── .gitignore ├── CMakeLists.txt ├── GenXIntrinsics ├── CMakeLists.txt ├── cmake │ └── utils.cmake ├── docs │ ├── GenXLangRef.rst │ ├── GenXLangRef_region_example1.png │ ├── GenXLangRef_region_example2.png │ ├── GenXLangRef_region_example3.png │ ├── GenXLangRef_region_example4.png │ ├── LangRefIndex.rst │ ├── Makefile.sphinx │ ├── ReadMe.txt │ └── conf.py ├── include │ ├── llvm │ │ ├── CMakeLists.txt │ │ └── GenXIntrinsics │ │ │ ├── CMakeLists.txt │ │ │ ├── ConfigureVersionFile.cmake │ │ │ ├── GenXIntrOpts.h │ │ │ ├── GenXIntrinsicInst.h │ │ │ ├── GenXIntrinsics.h │ │ │ ├── GenXMetadata.h │ │ │ ├── GenXSPIRVReaderAdaptor.h │ │ │ ├── GenXSPIRVWriterAdaptor.h │ │ │ ├── GenXSimdCFLowering.h │ │ │ ├── GenXVersion.h │ │ │ ├── Intrinsic_definitions.py │ │ │ └── Intrinsics.py │ └── llvmVCWrapper │ │ ├── ADT │ │ ├── Optional.h │ │ └── StringRef.h │ │ ├── Analysis │ │ └── InstructionSimplify.h │ │ ├── IR │ │ ├── Attributes.h │ │ ├── DerivedTypes.h │ │ ├── Function.h │ │ ├── Instructions.h │ │ ├── Intrinsics.h │ │ └── Type.h │ │ └── Support │ │ └── Alignment.h ├── lib │ ├── CMakeLists.txt │ └── GenXIntrinsics │ │ ├── AdaptorsCommon.cpp │ │ ├── AdaptorsCommon.h │ │ ├── CMakeLists.txt │ │ ├── GenXIntrinsics.cpp │ │ ├── GenXMetadata.cpp │ │ ├── GenXRestoreIntrAttr.cpp │ │ ├── GenXSPIRVReaderAdaptor.cpp │ │ ├── GenXSPIRVWriterAdaptor.cpp │ │ ├── GenXSimdCFLowering.cpp │ │ ├── GenXSingleElementVectorUtil.cpp │ │ ├── GenXSingleElementVectorUtil.h │ │ └── GenXVersion.cpp ├── test │ ├── Adaptors │ │ ├── annot_mess_writer.ll │ │ ├── annotated_args_mixed_reader.ll │ │ ├── annotated_args_no_conv_reader.ll │ │ ├── annotated_args_no_conv_writer.ll │ │ ├── annotated_args_reader.ll │ │ ├── annotated_args_writer.ll │ │ ├── args_attributes_transform_reader.ll │ │ ├── args_attributes_transform_writer.ll │ │ ├── combined_args_reader.ll │ │ ├── combined_args_writer.ll │ │ ├── empty_kernel_writer.ll │ │ ├── fun_attributes_transform_reader.ll │ │ ├── image_array_reader.ll │ │ ├── image_array_writer.ll │ │ ├── media_block_reader.ll │ │ ├── media_block_writer.ll │ │ ├── no_kernels_module_reader.ll │ │ ├── no_kernels_module_writer.ll │ │ ├── no_vcfunction_reader.ll │ │ ├── non_global_ptr_reader.ll │ │ ├── old_decorated_args_reader.ll │ │ ├── opaque_ptrs │ │ │ ├── addr_conv_attribute_writer.ll │ │ │ ├── annot_mess_writer.ll │ │ │ ├── annotated_args_mixed_reader.ll │ │ │ ├── annotated_args_no_conv_reader.ll │ │ │ ├── annotated_args_no_conv_writer.ll │ │ │ ├── annotated_args_reader.ll │ │ │ ├── annotated_args_writer.ll │ │ │ ├── args_attributes_transform_reader.ll │ │ │ ├── args_attributes_transform_writer.ll │ │ │ ├── combined_args_reader.ll │ │ │ ├── combined_args_writer.ll │ │ │ ├── image_array_reader.ll │ │ │ ├── image_array_writer.ll │ │ │ ├── media_block_reader.ll │ │ │ ├── media_block_writer.ll │ │ │ ├── non_global_ptr_reader.ll │ │ │ ├── plain_args_reader.ll │ │ │ ├── plain_args_writer.ll │ │ │ ├── sev_ptr_reader.ll │ │ │ ├── sev_ptr_writer.ll │ │ │ ├── sev_signature_reader.ll │ │ │ ├── sev_signature_writer.ll │ │ │ ├── sev_struct.ll │ │ │ ├── surface_access_reader.ll │ │ │ └── surface_access_writer.ll │ │ ├── plain_args_reader.ll │ │ ├── plain_args_writer.ll │ │ ├── sev_calling_conv_reader.ll │ │ ├── sev_calling_conv_writer.ll │ │ ├── sev_ptr_reader.ll │ │ ├── sev_ptr_writer.ll │ │ ├── sev_signature_reader.ll │ │ ├── sev_signature_writer.ll │ │ ├── sev_struct.ll │ │ ├── spirv_friendly_types_reader.ll │ │ ├── surface_access_reader.ll │ │ ├── surface_access_writer.ll │ │ ├── unknown_arg_reader.ll │ │ └── unknown_arg_writer.ll │ ├── CMakeLists.txt │ ├── Plugin │ │ ├── CMakeLists.txt │ │ └── Plugin.cpp │ ├── SimdCFLowering │ │ ├── bitcast_between_wrrs.ll │ │ ├── opaque_ptrs │ │ │ ├── bitcast_between_wrrs.ll │ │ │ ├── predicate_masked_gather.ll │ │ │ ├── replicate_mask.ll │ │ │ ├── replicate_mask_masked_gather4.ll │ │ │ └── update_mask_masked_gather4.ll │ │ ├── predicate_masked_gather.ll │ │ ├── replicate_mask.ll │ │ ├── replicate_mask_masked_gather4.ll │ │ └── update_mask_masked_gather4.ll │ ├── lit.cfg.py │ └── lit.site.cfg.py.in └── unittests │ ├── CMakeLists.txt │ └── GenXIntrinsics │ ├── CMakeLists.txt │ └── GenXIntrinsicsTest.cpp ├── LICENSE.md ├── Readme.md └── SECURITY.md /.github/workflows/on-pr-update.yml: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2020-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | name: Notify 10 | on: 11 | status: 12 | pull_request_review: 13 | 14 | permissions: 15 | contents: read 16 | 17 | jobs: 18 | notify: 19 | runs-on: [self-hosted, linux, gfx] 20 | steps: 21 | - name: Get branch name if status changed 22 | if: github.event_name == 'status' 23 | env: 24 | PR_BR_NAME: ${{ github.event.branches[0].name }} 25 | run: > 26 | echo "os_branch=$PR_BR_NAME" >> $GITHUB_ENV 27 | - name: Get branch name if pr review state changed 28 | if: github.event_name == 'pull_request_review' 29 | env: 30 | PR_HEAD_REF: ${{ github.event.pull_request.head.ref }} 31 | run: > 32 | echo "os_branch=$PR_HEAD_REF" >> $GITHUB_ENV 33 | - name: Notify 34 | run: ${{ secrets.NOTIFY }} 35 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | #==============================================================================# 2 | # This file specifies intentionally untracked files that git should ignore. 3 | # See: http://www.kernel.org/pub/software/scm/git/docs/gitignore.html 4 | # 5 | # This file is intentionally different from the output of `git svn show-ignore`, 6 | # as most of those are useless. 7 | #==============================================================================# 8 | 9 | #==============================================================================# 10 | # File extensions to be ignored anywhere in the tree. 11 | #==============================================================================# 12 | # Temp files created by most text editors. 13 | *~ 14 | # Merge files created by git. 15 | *.orig 16 | # Byte compiled python modules. 17 | *.pyc 18 | # vim swap files 19 | .*.sw? 20 | .sw? 21 | #OS X specific files. 22 | .DS_store 23 | 24 | # Nested build directory 25 | /build 26 | 27 | #==============================================================================# 28 | # Explicit files to ignore (only matches one). 29 | #==============================================================================# 30 | # Various tag programs 31 | /tags 32 | /TAGS 33 | /GPATH 34 | /GRTAGS 35 | /GSYMS 36 | /GTAGS 37 | .gitusers 38 | autom4te.cache 39 | cscope.files 40 | cscope.out 41 | autoconf/aclocal.m4 42 | autoconf/autom4te.cache 43 | /compile_commands.json 44 | tags 45 | # Visual Studio built-in CMake configuration 46 | /CMakeSettings.json 47 | # CLion project configuration 48 | /.idea 49 | 50 | #==============================================================================# 51 | # Directories to ignore (do not add trailing '/'s, they skip symlinks). 52 | #==============================================================================# 53 | # Sphinx build tree, if building in-source dir. 54 | GenXIntrinsics/docs/_build 55 | GenXIntrinsics/docs/autogenerated 56 | # VS2017 and VSCode config files. 57 | .vscode 58 | .vs 59 | # clangd index 60 | .clangd 61 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2019-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | cmake_minimum_required(VERSION 3.13.4) 10 | 11 | set(LLVM_GENX_INTRINSICS_VERSION 1.0) 12 | 13 | set(LLVM_GENX_INTRINSICS_ROOT_DIR ${CMAKE_CURRENT_SOURCE_DIR}) 14 | 15 | option(LLVM_GENX_INTRINSICS_IN_TREE_INSTALL "Do install after in-tree build" FALSE) 16 | 17 | # check if we build inside llvm or not 18 | if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) 19 | get_filename_component(LLVM_CMAKE_PATH ${LLVM_DIR} ABSOLUTE BASE_DIR ${CMAKE_BINARY_DIR}) 20 | set(BUILD_EXTERNAL YES) 21 | project(LLVM_GenXIntrinsics 22 | VERSION 23 | ${LLVM_GENX_INTRINSICS_VERSION} 24 | LANGUAGES 25 | C CXX 26 | ) 27 | 28 | set(CMAKE_CXX_STANDARD_REQUIRED OFF) 29 | 30 | find_package(LLVM REQUIRED HINTS "${LLVM_CMAKE_PATH}") 31 | set(CMAKE_MODULE_PATH 32 | ${CMAKE_MODULE_PATH} 33 | ${LLVM_CMAKE_DIR} 34 | ) 35 | include(AddLLVM) 36 | include(HandleLLVMOptions) 37 | 38 | if (LLVM_PACKAGE_VERSION GREATER_EQUAL 14) 39 | set(CMAKE_CXX_STANDARD 17) 40 | else () 41 | set(CMAKE_CXX_STANDARD 14) 42 | endif() 43 | 44 | include_directories("${LLVM_INCLUDE_DIR}") 45 | link_directories("${LLVM_LIBRARY_DIR}") 46 | 47 | message(STATUS "Found LLVM: ${LLVM_VERSION}") 48 | else(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) 49 | set(BUILD_EXTERNAL NO) 50 | 51 | # LLVM_CMAKE_DIR is not set for non-standalone builds. Use LLVM_CMAKE_PATH 52 | # instead. (see clang/CMakeLists.txt) 53 | if(NOT LLVM_CMAKE_DIR) 54 | set(LLVM_CMAKE_DIR ${LLVM_CMAKE_PATH}) 55 | endif() 56 | endif(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) 57 | 58 | if(LLVM_VERSION_MAJOR VERSION_LESS 8) 59 | message(FATAL_ERROR "VC-intrinsics do not support ${LLVM_VERSION} LLVM version") 60 | endif() 61 | 62 | if (DEFINED PYTHON_EXECUTABLE) 63 | get_filename_component(PYTHON_EXECUTABLE "${PYTHON_EXECUTABLE}" ABSOLUTE) 64 | else() 65 | find_package(Python REQUIRED COMPONENTS Interpreter) 66 | if("${Python_VERSION}" VERSION_LESS 2.7) 67 | message(FATAL_ERROR "Python 2.7 or newer is required") 68 | endif() 69 | set(PYTHON_EXECUTABLE "${Python_EXECUTABLE}") 70 | endif() 71 | 72 | 73 | add_subdirectory(GenXIntrinsics) 74 | -------------------------------------------------------------------------------- /GenXIntrinsics/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2019-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | cmake_minimum_required(VERSION 3.13.4) 10 | include(GNUInstallDirs) 11 | 12 | set(GENX_INTRINSICS_MAIN_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/include) 13 | 14 | set(GENX_INTRINSICS_MAIN_DIR ${CMAKE_CURRENT_SOURCE_DIR}) 15 | 16 | if(IGC_INFRA) 17 | set(GENX_INTRINSICS_MAIN_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/include PARENT_SCOPE) 18 | endif() 19 | 20 | include(cmake/utils.cmake) 21 | 22 | # Global config. 23 | add_compile_definitions(VC_INTR_LLVM_VERSION_MAJOR=${LLVM_VERSION_MAJOR}) 24 | 25 | include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include) 26 | include_directories(${CMAKE_CURRENT_BINARY_DIR}/include) 27 | 28 | set(GENX_INTRINSICS_DESCRIPTION "GenXIntrinsicDescription.gen") 29 | 30 | add_subdirectory(include/llvm) 31 | add_subdirectory(lib) 32 | 33 | # LLVM doesn't install gtest which is required for our tests 34 | # so we cannot simply enable current unittests with prebuilt LLVM 35 | if(NOT BUILD_EXTERNAL) 36 | add_subdirectory(unittests) 37 | endif() 38 | 39 | # Experimental lit tests for intrinsic passes. Require plugin support, 40 | # so only available with LLVM dylib (for stability). 41 | if(VC_INTR_ENABLE_LIT_TESTS) 42 | if(LLVM_LINK_LLVM_DYLIB) 43 | message(STATUS "VC intrinsics lit tests are enabled") 44 | add_subdirectory(test) 45 | else() 46 | message(STATUS "VC intrinsics lit tests require dynamic LLVM, skipping") 47 | endif() 48 | endif() 49 | 50 | install(DIRECTORY include/llvm 51 | DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} 52 | COMPONENT genx-intrinsics-headers 53 | FILES_MATCHING 54 | PATTERN "*.h" 55 | ) 56 | 57 | # cmake creates too many subdirectories in build directory 58 | # and then "install(DIRECTORY" installs them even if they are empty 59 | # so generated file has to be installed separetely 60 | install(FILES ${CMAKE_CURRENT_BINARY_DIR}/include/llvm/GenXIntrinsics/${GENX_INTRINSICS_DESCRIPTION} 61 | DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/llvm/GenXIntrinsics 62 | COMPONENT genx-intrinsics-headers 63 | ) 64 | 65 | install(TARGETS LLVMGenXIntrinsics EXPORT LLVMGenXIntrinsicsTargets 66 | LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} 67 | ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} 68 | RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} 69 | INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} 70 | ) 71 | 72 | # Install Config-file only for external build 73 | if(BUILD_EXTERNAL OR LLVM_GENX_INTRINSICS_IN_TREE_INSTALL) 74 | 75 | # Legacy export. To remove when all clients switch to new name. 76 | install(EXPORT LLVMGenXIntrinsicsTargets 77 | FILE LLVMGenXIntrinsicsConfig.cmake 78 | DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/LLVMGenXIntrinsics 79 | ) 80 | 81 | set(PACKAGE_NAME VCIntrinsics${LLVM_VERSION_MAJOR}) 82 | install(EXPORT LLVMGenXIntrinsicsTargets 83 | FILE ${PACKAGE_NAME}Config.cmake 84 | DESTINATION ${CMAKE_INSTALL_LIBDIR}/cmake/${PACKAGE_NAME} 85 | ) 86 | endif() # BUILD_EXTERNAL OR LLVM_GENX_INTRINSICS_IN_TREE_INSTALL 87 | -------------------------------------------------------------------------------- /GenXIntrinsics/cmake/utils.cmake: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2020-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | # Convenience function to get list of LLVM components for 10 | # target_link_library. If LLVM was configured with llvm dylib, then 11 | # included in dylib llvm targets should be replaced with LLVM 12 | # lib. Otherwise, just return passed libraries. 13 | # ret -- name of variable with returned targets list. All other 14 | # arguments are components to process. 15 | function(vc_get_llvm_targets RET) 16 | set(TARGETS ${ARGN}) 17 | 18 | if (LLVM_LINK_LLVM_DYLIB) 19 | # Drop all components, though it is probably not right 20 | # and llvm_map_components_to_libnames should be used as filter. 21 | # However, in external build it returns empty list for "all" 22 | # so filtering is not really done. 23 | if ("${LLVM_DYLIB_COMPONENTS}" STREQUAL "all") 24 | set(TARGETS "") 25 | else() 26 | list(REMOVE_ITEM TARGETS ${LLVM_DYLIB_COMPONENTS}) 27 | endif() 28 | endif() 29 | 30 | # Expand rest of components names to target names. 31 | llvm_map_components_to_libnames(TARGETS ${TARGETS}) 32 | 33 | if (LLVM_LINK_LLVM_DYLIB) 34 | set(TARGETS ${TARGETS} LLVM) 35 | endif() 36 | 37 | set(${RET} ${TARGETS} PARENT_SCOPE) 38 | endfunction() 39 | -------------------------------------------------------------------------------- /GenXIntrinsics/docs/GenXLangRef_region_example1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/vc-intrinsics/46286b96fb9eee9fa4fcf8b8ecf74a8c01af4c1a/GenXIntrinsics/docs/GenXLangRef_region_example1.png -------------------------------------------------------------------------------- /GenXIntrinsics/docs/GenXLangRef_region_example2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/vc-intrinsics/46286b96fb9eee9fa4fcf8b8ecf74a8c01af4c1a/GenXIntrinsics/docs/GenXLangRef_region_example2.png -------------------------------------------------------------------------------- /GenXIntrinsics/docs/GenXLangRef_region_example3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/vc-intrinsics/46286b96fb9eee9fa4fcf8b8ecf74a8c01af4c1a/GenXIntrinsics/docs/GenXLangRef_region_example3.png -------------------------------------------------------------------------------- /GenXIntrinsics/docs/GenXLangRef_region_example4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/intel/vc-intrinsics/46286b96fb9eee9fa4fcf8b8ecf74a8c01af4c1a/GenXIntrinsics/docs/GenXLangRef_region_example4.png -------------------------------------------------------------------------------- /GenXIntrinsics/docs/LangRefIndex.rst: -------------------------------------------------------------------------------- 1 | .. ========================= begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2019-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | =========================== end_copyright_notice ============================= 8 | 9 | VC Intrinsics documentation (language reference) 10 | ================================================== 11 | 12 | .. toctree:: 13 | :hidden: 14 | 15 | GenXLangRef 16 | 17 | :doc:`GenXLangRef` 18 | Defines the restrictions on and additions to LLVM intermediate representation 19 | for the GenX backend for Intel HD Graphics. 20 | 21 | -------------------------------------------------------------------------------- /GenXIntrinsics/docs/Makefile.sphinx: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2019-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | # Minimal makefile for Sphinx documentation 10 | # 11 | 12 | # You can set these variables from the command line. 13 | SPHINXOPTS = 14 | SPHINXBUILD = sphinx-build 15 | SPHINXPROJ = VCIntrinsics 16 | SOURCEDIR = . 17 | BUILDDIR = _build 18 | AUTOGENDIR = _build/autogenerated 19 | 20 | # Put it first so that "make" without argument is like "make help". 21 | help: 22 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 23 | 24 | .PHONY: help Makefile.sphinx 25 | 26 | # Catch-all target: route all unknown targets to Sphinx using the new 27 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 28 | %: Makefile.sphinx autogen 29 | echo "$@" 30 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 31 | 32 | # AUTOGENSED : auto-generation of docs from source files 33 | # 1. Remove initial "/// ", and blank any line that does not have it. 34 | # 2. Change ".. include ." into ".. include autogen/.rstinc" 35 | AUTOGENSEDCXX='/^ *\/\/\/ /!s/.*//; s/^ *\/\/\/ //; s/\(\.\. include:: \)\(.*\)\.[a-z]*/\1$(AUTOGENDIR)\/\2.rstinc/' 36 | AUTOGENSEDPY='/^ *\#\#\# /!s/.*//; s/^ *\#\#\# //' 37 | autogen: 38 | @mkdir -p $(AUTOGENDIR) 39 | @rm -f $(AUTOGENDIR)/* 40 | @sed $(AUTOGENSEDPY) ../include/llvm/GenXIntrinsics/Intrinsic_definitions.py > $(AUTOGENDIR)/GenXLangRef.rstinc 41 | -------------------------------------------------------------------------------- /GenXIntrinsics/docs/ReadMe.txt: -------------------------------------------------------------------------------- 1 | 8 | 9 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvm/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2019-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | add_subdirectory(GenXIntrinsics) 10 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvm/GenXIntrinsics/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2019-2024 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | add_custom_command( 10 | OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${GENX_INTRINSICS_DESCRIPTION} 11 | COMMAND ${PYTHON_EXECUTABLE} -B 12 | ${CMAKE_CURRENT_SOURCE_DIR}/Intrinsics.py 13 | ${CMAKE_CURRENT_SOURCE_DIR}/Intrinsic_definitions.py 14 | ${CMAKE_CURRENT_BINARY_DIR}/${GENX_INTRINSICS_DESCRIPTION} 15 | DEPENDS 16 | ${CMAKE_CURRENT_SOURCE_DIR}/Intrinsics.py 17 | ${CMAKE_CURRENT_SOURCE_DIR}/Intrinsic_definitions.py 18 | COMMENT "Building ${GENX_INTRINSICS_DESCRIPTION}..." 19 | ) 20 | 21 | find_first_existing_vc_file(intrinsics_vc "${GENX_INTRINSICS_MAIN_DIR}") 22 | 23 | set(version_inc ${CMAKE_CURRENT_BINARY_DIR}/GenXVersion.inc) 24 | 25 | if(LLVM_GENX_INTRINSICS_ROOT_DIR) 26 | set(LLVM_GENX_INTRINSICS_REPO_DIR ${LLVM_GENX_INTRINSICS_ROOT_DIR}) 27 | else() 28 | set(LLVM_GENX_INTRINSICS_REPO_DIR ${GENX_INTRINSICS_MAIN_DIR}/..) 29 | endif() 30 | 31 | if(${LLVM_VERSION_MAJOR} LESS 9) 32 | find_file(FOUND_VCS GetSVN.cmake PATHS ${LLVM_CMAKE_DIR} REQUIRED NO_CMAKE_FIND_ROOT_PATH) 33 | add_custom_command( 34 | OUTPUT "${version_inc}" 35 | COMMAND 36 | ${CMAKE_COMMAND} "-DSOURCE_DIRS=${LLVM_GENX_INTRINSICS_REPO_DIR}" 37 | "-DNAMES=VCI" 38 | "-DHEADER_FILE=${version_inc}" 39 | -P "${FOUND_VCS}") 40 | else() 41 | find_file(FOUND_VCS VersionFromVCS.cmake PATHS ${LLVM_CMAKE_DIR} REQUIRED NO_CMAKE_FIND_ROOT_PATH) 42 | add_custom_command( 43 | OUTPUT "${version_inc}" 44 | COMMAND 45 | ${CMAKE_COMMAND} "-DSOURCE_DIR=${LLVM_GENX_INTRINSICS_REPO_DIR}" 46 | "-DNAME=VCI" 47 | "-DHEADER_FILE=${version_inc}" 48 | "-DVCS_SCRIPT=${FOUND_VCS}" 49 | -P "${CMAKE_CURRENT_SOURCE_DIR}/ConfigureVersionFile.cmake") 50 | endif() 51 | 52 | set_source_files_properties("${version_inc}" 53 | PROPERTIES GENERATED TRUE 54 | HEADER_FILE_ONLY TRUE) 55 | 56 | add_custom_target(GenXIntrinsicDescriptionGen 57 | DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${GENX_INTRINSICS_DESCRIPTION} 58 | ${version_inc} 59 | ) 60 | add_custom_target(GenXIntrinsicsGen) 61 | add_dependencies(GenXIntrinsicsGen GenXIntrinsicDescriptionGen) 62 | 63 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvm/GenXIntrinsics/ConfigureVersionFile.cmake: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2020-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | include(${VCS_SCRIPT}) 10 | 11 | function(generate_version_file output_file) 12 | get_source_info(${SOURCE_DIR} rev repo) 13 | file(APPEND "${output_file}.txt" "#define ${NAME}_REVISION \"${rev}\"\n") 14 | file(APPEND "${output_file}.txt" "#define ${NAME}_REPOSITORY \"${repo}\"\n") 15 | execute_process(COMMAND ${CMAKE_COMMAND} -E copy_if_different 16 | "${output_file}.txt" "${output_file}") 17 | file(REMOVE "${output_file}.txt") 18 | 19 | endfunction() 20 | 21 | generate_version_file(${HEADER_FILE}) 22 | 23 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrOpts.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | /*========================== begin_copyright_notice ============================ 10 | 11 | This file is distributed under the University of Illinois Open Source License. 12 | See LICENSE.TXT for details. 13 | 14 | ============================= end_copyright_notice ===========================*/ 15 | 16 | // This header file defines prototypes for accessor functions that expose passes 17 | // in the GenX Intrinsics transformations library. 18 | 19 | #ifndef LLVM_GENX_INTR_OPTS_H 20 | #define LLVM_GENX_INTR_OPTS_H 21 | 22 | namespace llvm { 23 | 24 | class FunctionPass; 25 | class ModulePass; 26 | class Pass; 27 | 28 | //===----------------------------------------------------------------------===// 29 | // 30 | // CMSimdCFLowering - Lower CM SIMD control flow 31 | // 32 | Pass *createCMSimdCFLoweringPass(); 33 | Pass *createISPCSimdCFLoweringPass(); 34 | 35 | //===----------------------------------------------------------------------===// 36 | // 37 | // GenXRestoreIntrAttr - Restore Intrinsics' Attributes 38 | // 39 | Pass *createGenXRestoreIntrAttrPass(); 40 | 41 | } // End llvm namespace 42 | 43 | #endif 44 | 45 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsicInst.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2019-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | //===----------------------------------------------------------------------===// 10 | // 11 | // This file defines classes that make it really easy to deal with intrinsic 12 | // functions with the isa/dyncast family of functions. In particular, this 13 | // allows you to do things like: 14 | // 15 | // if (MemCpyInst *MCI = dyn_cast(Inst)) 16 | // ... MCI->getDest() ... MCI->getSource() ... 17 | // 18 | // All intrinsic function calls are instances of the call instruction, so these 19 | // are all subclasses of the CallInst class. Note that none of these classes 20 | // has state or virtual methods, which is an important part of this gross/neat 21 | // hack working. 22 | // 23 | //===----------------------------------------------------------------------===// 24 | 25 | #ifndef GENX_INTRINSIC_INST_H 26 | #define GENX_INTRINSIC_INST_H 27 | 28 | #include "llvm/GenXIntrinsics/GenXIntrinsics.h" 29 | 30 | #include "llvm/IR/Constants.h" 31 | #include "llvm/IR/Function.h" 32 | #include "llvm/IR/IRBuilder.h" 33 | #include "llvm/IR/Instructions.h" 34 | #include "llvm/IR/Module.h" 35 | 36 | namespace llvm { 37 | /// IntrinsicInst - A useful wrapper class for inspecting calls to intrinsic 38 | /// functions. This allows the standard isa/dyncast/cast functionality to 39 | /// work with calls to intrinsic functions. 40 | class GenXIntrinsicInst : public CallInst { 41 | public: 42 | GenXIntrinsicInst() = delete; 43 | GenXIntrinsicInst(const GenXIntrinsicInst &) = delete; 44 | void operator=(const GenXIntrinsicInst &) = delete; 45 | 46 | /// getIntrinsicID - Return the intrinsic ID of this intrinsic. 47 | /// 48 | GenXIntrinsic::ID getIntrinsicID() const { 49 | return GenXIntrinsic::getGenXIntrinsicID(getCalledFunction()); 50 | } 51 | 52 | // Methods for support type inquiry through isa, cast, and dyn_cast: 53 | static bool classof(const CallInst *I); 54 | 55 | static bool classof(const Value *V) { 56 | return isa(V) && classof(cast(V)); 57 | } 58 | }; 59 | 60 | // TODO: add more classes to make our intrinsics easier to use 61 | 62 | } // namespace llvm 63 | 64 | #endif 65 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvm/GenXIntrinsics/GenXMetadata.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | //===----------------------------------------------------------------------===// 10 | // 11 | // This file defines GenX kernel metadata operand numbers and other module 12 | // metadata. 13 | // 14 | //===----------------------------------------------------------------------===// 15 | 16 | #ifndef GENX_METADATA_H 17 | #define GENX_METADATA_H 18 | 19 | namespace llvm { 20 | 21 | class MDNode; 22 | class Function; 23 | 24 | namespace genx { 25 | 26 | namespace FunctionMD { 27 | static constexpr const char GenXKernels[] = "genx.kernels"; 28 | static constexpr const char GenXByteOffset[] = "genx_byte_offset"; 29 | static constexpr const char GenXVolatile[] = "genx_volatile"; 30 | static constexpr const char CMGenXMain[] = "CMGenxMain"; 31 | static constexpr const char CMStackCall[] = "CMStackCall"; 32 | static constexpr const char CMCallable[] = "CMCallable"; 33 | static constexpr const char CMEntry[] = "CMEntry"; 34 | static constexpr const char CMFloatControl[] = "CMFloatControl"; 35 | static constexpr const char CMGenxSIMT[] = "CMGenxSIMT"; 36 | static constexpr const char CMGenxReplicateMask[] = "CMGenxReplicateMask"; 37 | static constexpr const char OCLRuntime[] = "oclrt"; 38 | static constexpr const char ReferencedIndirectly[] = "referenced-indirectly"; 39 | } // namespace FunctionMD 40 | 41 | namespace VCModuleMD { 42 | static constexpr const char VCGlobalVariable[] = "VCGlobalVariable"; 43 | static constexpr const char VCVolatile[] = "VCVolatile"; 44 | static constexpr const char VCByteOffset[] = "VCByteOffset"; 45 | static constexpr const char VCSingleElementVector[] = "VCSingleElementVector"; 46 | } // namespace VCModuleMD 47 | 48 | namespace VCFunctionMD { 49 | static constexpr const char VCFunction[] = "VCFunction"; 50 | static constexpr const char VCStackCall[] = "VCStackCall"; 51 | static constexpr const char VCCallable[] = "VCCallable"; 52 | static constexpr const char VCFCEntry[] = "VCFCEntry"; 53 | static constexpr const char VCArgumentIOKind[] = "VCArgumentIOKind"; 54 | static constexpr const char VCFloatControl[] = "VCFloatControl"; 55 | static constexpr const char VCSLMSize[] = "VCSLMSize"; 56 | static constexpr const char VCArgumentKind[] = "VCArgumentKind"; 57 | static constexpr const char VCArgumentDesc[] = "VCArgumentDesc"; 58 | static constexpr const char VCSIMTCall[] = "VCSIMTCall"; 59 | static constexpr const char VCNamedBarrierCount[] = "VCNamedBarrierCount"; 60 | static constexpr const char VCMediaBlockIO[] = "VCMediaBlockIO"; 61 | } // namespace VCFunctionMD 62 | 63 | enum KernelMDOp { 64 | FunctionRef, // Reference to Function 65 | Name, // Kernel name 66 | ArgKinds, // Reference to metadata node containing kernel arg kinds 67 | SLMSize, // SLM-size in bytes 68 | ArgOffsets, // Kernel argument offsets 69 | ArgIOKinds, // Reference to metadata node containing kernel argument 70 | // input/output kinds 71 | ArgTypeDescs, // Kernel argument type descriptors 72 | NBarrierCnt, // Named barrier count 73 | BarrierCnt // Barrier count 74 | }; 75 | 76 | MDNode *GetOldStyleKernelMD(const Function &F); 77 | 78 | } // namespace genx 79 | } // namespace llvm 80 | 81 | #endif 82 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2022 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | /// 10 | /// GenXSPIRVReaderAdaptor 11 | /// --------------------------- 12 | /// This pass converts metadata from SPIRV format to whichever used in backend 13 | 14 | #include "llvm/IR/PassManager.h" 15 | 16 | namespace llvm { 17 | class ModulePass; 18 | class PassRegistry; 19 | 20 | //----------------------------------------------------------------------------- 21 | // New PM support 22 | //----------------------------------------------------------------------------- 23 | // Reader adaptor for new PM. 24 | class GenXSPIRVReaderAdaptor final 25 | : public PassInfoMixin { 26 | 27 | public: 28 | PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 29 | static StringRef getArgString() { return "GenXSPIRVReaderAdaptor"; } 30 | }; 31 | 32 | //----------------------------------------------------------------------------- 33 | // Legacy PM support 34 | //----------------------------------------------------------------------------- 35 | void initializeGenXSPIRVReaderAdaptorLegacyPass(PassRegistry &); 36 | 37 | ModulePass *createGenXSPIRVReaderAdaptorPass(); 38 | } // namespace llvm 39 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | /// 10 | /// GenXSPIRVWriterAdaptor 11 | /// --------------------------- 12 | /// This pass converts metadata to SPIRV format from whichever used in frontend 13 | 14 | #include "llvm/IR/PassManager.h" 15 | 16 | namespace llvm { 17 | class ModulePass; 18 | class PassRegistry; 19 | 20 | //----------------------------------------------------------------------------- 21 | // New PM support 22 | //----------------------------------------------------------------------------- 23 | // Writer adaptor for new PM. 24 | class GenXSPIRVWriterAdaptor final 25 | : public PassInfoMixin { 26 | bool RewriteTypes = true; 27 | bool RewriteSingleElementVectors = true; 28 | 29 | public: 30 | GenXSPIRVWriterAdaptor(bool RewriteTypesIn, 31 | bool RewriteSingleElementVectorsIn) 32 | : RewriteTypes(RewriteTypesIn), 33 | RewriteSingleElementVectors(RewriteSingleElementVectorsIn) {} 34 | 35 | PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 36 | 37 | static StringRef getArgString() { return "GenXSPIRVWriterAdaptor"; } 38 | }; 39 | 40 | //----------------------------------------------------------------------------- 41 | // Legacy PM support 42 | //----------------------------------------------------------------------------- 43 | void initializeGenXSPIRVWriterAdaptorLegacyPass(PassRegistry &); 44 | 45 | // Create spirv writer adaptor pass. 46 | // RewriteTypes -- whether plain types with decorations should be 47 | // rewritten with native SPIRV types. Defaults to false for 48 | // compatibility reasons until backend will be able to handle new 49 | // types. 50 | ModulePass * 51 | createGenXSPIRVWriterAdaptorPass(bool RewriteTypes = false, 52 | bool RewriteSingleElementVectors = false); 53 | } // namespace llvm 54 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvm/GenXIntrinsics/GenXVersion.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | // This file declares interface functions used to aquire version info. 10 | 11 | #ifndef GENX_VERSION 12 | #define GENX_VERSION 13 | 14 | #include 15 | 16 | namespace llvm { 17 | 18 | namespace GenXIntrinsic { 19 | 20 | std::string getVCIntrinsicsRevision(); 21 | std::string getVCIntrinsicsRepository(); 22 | 23 | } // namespace GenXIntrinsic 24 | } // namespace llvm 25 | 26 | #endif 27 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/ADT/Optional.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2022 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_ADT_OPTIONAL_H 10 | #define VCINTR_ADT_OPTIONAL_H 11 | 12 | #if VC_INTR_LLVM_VERSION_MAJOR < 16 13 | #include 14 | 15 | namespace VCINTR { 16 | 17 | template using Optional = llvm::Optional; 18 | } 19 | #else 20 | #include 21 | 22 | namespace VCINTR { 23 | template using Optional = std::optional; 24 | } 25 | 26 | #endif 27 | 28 | #endif 29 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/ADT/StringRef.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2022 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_ADT_STRINGREF_H 10 | #define VCINTR_ADT_STRINGREF_H 11 | 12 | #include 13 | 14 | namespace VCINTR { 15 | 16 | namespace StringRef { 17 | 18 | inline bool starts_with(llvm::StringRef S, llvm::StringRef Prefix) { 19 | #if VC_INTR_LLVM_VERSION_MAJOR >= 16 20 | return S.starts_with(Prefix); 21 | #else 22 | return S.startswith(Prefix); 23 | #endif 24 | } 25 | 26 | } // namespace StringRef 27 | 28 | } // namespace VCINTR 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/Analysis/InstructionSimplify.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2022 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_ANALYSIS_INSTRUCTIONSIMPLIFY_H 10 | #define VCINTR_ANALYSIS_INSTRUCTIONSIMPLIFY_H 11 | 12 | #include 13 | 14 | namespace VCINTR { 15 | 16 | inline llvm::Value *SimplifyInsertElementInst(llvm::Value *Vec, 17 | llvm::Value *Elt, 18 | llvm::Value *Idx, 19 | const llvm::SimplifyQuery &Q) { 20 | #if VC_INTR_LLVM_VERSION_MAJOR <= 14 21 | return llvm::SimplifyInsertElementInst(Vec, Elt, Idx, Q); 22 | #else 23 | return llvm::simplifyInsertElementInst(Vec, Elt, Idx, Q); 24 | #endif 25 | } 26 | 27 | inline llvm::Value *SimplifyExtractElementInst(llvm::Value *Vec, 28 | llvm::Value *Idx, 29 | const llvm::SimplifyQuery &Q) { 30 | #if VC_INTR_LLVM_VERSION_MAJOR <= 14 31 | return llvm::SimplifyExtractElementInst(Vec, Idx, Q); 32 | #else 33 | return llvm::simplifyExtractElementInst(Vec, Idx, Q); 34 | #endif 35 | } 36 | 37 | inline llvm::Value *SimplifyCastInst(unsigned CastOpc, llvm::Value *Op, 38 | llvm::Type *Ty, 39 | const llvm::SimplifyQuery &Q) { 40 | #if VC_INTR_LLVM_VERSION_MAJOR <= 14 41 | return llvm::SimplifyCastInst(CastOpc, Op, Ty, Q); 42 | #else 43 | return llvm::simplifyCastInst(CastOpc, Op, Ty, Q); 44 | #endif 45 | } 46 | 47 | } // namespace VCINTR 48 | 49 | #endif // VCINTR_ANALYSIS_INSTRUCTIONSIMPLIFY_H 50 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/IR/Attributes.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_IR_ATTRIBUTES_H 10 | #define VCINTR_IR_ATTRIBUTES_H 11 | 12 | #include 13 | 14 | namespace VCINTR { 15 | 16 | namespace AttributeList { 17 | 18 | inline bool hasFnAttr(const llvm::AttributeList &AttrList, 19 | llvm::Attribute::AttrKind Kind) { 20 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 21 | return AttrList.hasFnAttr(Kind); 22 | #else 23 | return AttrList.hasFnAttribute(Kind); 24 | #endif 25 | } 26 | 27 | inline bool hasFnAttr(const llvm::AttributeList &AttrList, 28 | llvm::StringRef Kind) { 29 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 30 | return AttrList.hasFnAttr(Kind); 31 | #else 32 | return AttrList.hasFnAttribute(Kind); 33 | #endif 34 | } 35 | 36 | inline bool hasAttributeAtIndex(const llvm::AttributeList &AttrList, 37 | unsigned Index, 38 | llvm::Attribute::AttrKind Kind) { 39 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 40 | return AttrList.hasAttributeAtIndex(Index, Kind); 41 | #else 42 | return AttrList.hasAttribute(Index, Kind); 43 | #endif 44 | } 45 | 46 | inline bool hasAttributeAtIndex(const llvm::AttributeList &AttrList, 47 | unsigned Index, llvm::StringRef Kind) { 48 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 49 | return AttrList.hasAttributeAtIndex(Index, Kind); 50 | #else 51 | return AttrList.hasAttribute(Index, Kind); 52 | #endif 53 | } 54 | 55 | inline llvm::Attribute getAttributeAtIndex(const llvm::AttributeList &AttrList, 56 | unsigned Index, 57 | llvm::Attribute::AttrKind Kind) { 58 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 59 | return AttrList.getAttributeAtIndex(Index, Kind); 60 | #else 61 | return AttrList.getAttribute(Index, Kind); 62 | #endif 63 | } 64 | 65 | inline llvm::Attribute getAttributeAtIndex(const llvm::AttributeList &AttrList, 66 | unsigned Index, 67 | llvm::StringRef Kind) { 68 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 69 | return AttrList.getAttributeAtIndex(Index, Kind); 70 | #else 71 | return AttrList.getAttribute(Index, Kind); 72 | #endif 73 | } 74 | 75 | inline llvm::AttributeList 76 | removeAttributeAtIndex(llvm::LLVMContext &C, 77 | const llvm::AttributeList &AttrList, unsigned Index, 78 | llvm::Attribute::AttrKind Kind) { 79 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 80 | return AttrList.removeAttributeAtIndex(C, Index, Kind); 81 | #else 82 | return AttrList.removeAttribute(C, Index, Kind); 83 | #endif 84 | } 85 | 86 | inline llvm::AttributeList 87 | removeAttributeAtIndex(llvm::LLVMContext &C, 88 | const llvm::AttributeList &AttrList, unsigned Index, 89 | llvm::StringRef Kind) { 90 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 91 | return AttrList.removeAttributeAtIndex(C, Index, Kind); 92 | #else 93 | return AttrList.removeAttribute(C, Index, Kind); 94 | #endif 95 | } 96 | 97 | } // namespace AttributeList 98 | 99 | } // namespace VCINTR 100 | 101 | #endif // VCINTR_IR_ATTRIBUTES_H 102 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/IR/DerivedTypes.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_IR_DERIVEDYPES_H 10 | #define VCINTR_IR_DERIVEDYPES_H 11 | 12 | #include 13 | #include 14 | 15 | namespace VCINTR { 16 | // TODO: move this to namespace VectorType and rename to "get" 17 | #if VC_INTR_LLVM_VERSION_MAJOR >= 9 18 | inline llvm::VectorType *getVectorType(llvm::Type *ElementType, 19 | llvm::ElementCount EC) { 20 | return llvm::VectorType::get(ElementType, EC); 21 | } 22 | #endif 23 | 24 | inline llvm::VectorType *getVectorType(llvm::Type *ElementType, 25 | unsigned NumElements) { 26 | #if VC_INTR_LLVM_VERSION_MAJOR >= 11 27 | return llvm::VectorType::get(ElementType, NumElements, false /*Scalable*/); 28 | #else 29 | return llvm::VectorType::get(ElementType, NumElements); 30 | #endif 31 | } 32 | 33 | inline llvm::StructType *getTypeByName(llvm::Module *M, 34 | llvm::StringRef Name) { 35 | #if VC_INTR_LLVM_VERSION_MAJOR >= 12 36 | return llvm::StructType::getTypeByName(M->getContext(), Name); 37 | #else 38 | return M->getTypeByName(Name); 39 | #endif 40 | } 41 | 42 | namespace VectorType { 43 | 44 | inline unsigned getNumElements(llvm::VectorType *VecType) { 45 | using namespace llvm; 46 | #if VC_INTR_LLVM_VERSION_MAJOR <= 10 47 | return VecType->getNumElements(); 48 | #else 49 | auto *FixedVecType = cast(VecType); 50 | return FixedVecType->getNumElements(); 51 | #endif 52 | } 53 | 54 | } // namespace VectorType 55 | namespace PointerType { 56 | 57 | inline llvm::PointerType *getWithSamePointeeType(llvm::PointerType *PT, 58 | unsigned AddressSpace) { 59 | #if VC_INTR_LLVM_VERSION_MAJOR < 14 60 | return llvm::PointerType::get(PT->getElementType(), AddressSpace); 61 | #elif VC_INTR_LLVM_VERSION_MAJOR < 17 62 | return llvm::PointerType::getWithSamePointeeType(PT, AddressSpace); 63 | #else 64 | return llvm::PointerType::get(PT->getContext(), AddressSpace); 65 | #endif 66 | } 67 | 68 | } // namespace PointerType 69 | } // namespace VCINTR 70 | 71 | #endif // VCINTR_IR_DERIVEDYPES_H 72 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/IR/Function.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2024 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_IR_FUNCTION_H 10 | #define VCINTR_IR_FUNCTION_H 11 | 12 | #include 13 | 14 | namespace VCINTR { 15 | 16 | namespace Function { 17 | 18 | inline llvm::Argument *getArg(const llvm::Function &F, unsigned ArgNo) { 19 | assert(F.arg_size() > ArgNo); 20 | llvm::Argument *Arg = nullptr; 21 | 22 | #if LLVM_VERSION_MAJOR < 10 23 | // similar to lvm::Function::getArg implementation 24 | auto ArgIt = F.arg_begin(); 25 | std::advance(ArgIt, ArgNo); 26 | Arg = const_cast(&*ArgIt); 27 | #else 28 | Arg = F.getArg(ArgNo); 29 | #endif 30 | 31 | return Arg; 32 | } 33 | 34 | inline void addAttributeAtIndex(llvm::Function &F, unsigned Index, 35 | llvm::Attribute Attr) { 36 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 37 | F.addAttributeAtIndex(Index, Attr); 38 | #else 39 | F.addAttribute(Index, Attr); 40 | #endif 41 | } 42 | 43 | inline void removeAttributeAtIndex(llvm::Function &F, unsigned Index, 44 | llvm::Attribute::AttrKind Kind) { 45 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 46 | F.removeAttributeAtIndex(Index, Kind); 47 | #else 48 | F.removeAttribute(Index, Kind); 49 | #endif 50 | } 51 | 52 | inline void removeAttributeAtIndex(llvm::Function &F, unsigned Index, 53 | llvm::StringRef Kind) { 54 | #if VC_INTR_LLVM_VERSION_MAJOR >= 14 55 | F.removeAttributeAtIndex(Index, Kind); 56 | #else 57 | F.removeAttribute(Index, Kind); 58 | #endif 59 | } 60 | 61 | } // namespace Function 62 | 63 | } // namespace VCINTR 64 | 65 | #endif // VCINTR_IR_GLOBALVARIABLE_H 66 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2022 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_IR_INSTRUCTIONS_H 10 | #define VCINTR_IR_INSTRUCTIONS_H 11 | 12 | #include 13 | #include 14 | #include 15 | 16 | namespace VCINTR { 17 | namespace ShuffleVectorInst { 18 | auto static constexpr UndefMaskElem = -1; 19 | 20 | // LLVM <= 10 does not have ShuffleVectorInst ctor which accepts ArrayRef 21 | // This method returns mask with appropriate type for ShuffleVectorInst ctor 22 | #if VC_INTR_LLVM_VERSION_MAJOR <= 10 23 | inline llvm::Constant *getShuffleMask(llvm::ArrayRef Mask, 24 | llvm::LLVMContext &Context) { 25 | using namespace llvm; 26 | auto Indices = SmallVector{}; 27 | auto *Int32Ty = IntegerType::getInt32Ty(Context); 28 | std::transform(Mask.begin(), Mask.end(), std::back_inserter(Indices), 29 | [&](int El) -> llvm::Constant * { 30 | if (El == UndefMaskElem) 31 | return UndefValue::get(Int32Ty); 32 | else 33 | return ConstantInt::get(Int32Ty, El); 34 | }); 35 | return ConstantVector::get(Indices); 36 | } 37 | #else 38 | inline llvm::ArrayRef getShuffleMask(llvm::ArrayRef Mask, 39 | llvm::LLVMContext &Context) { 40 | return Mask; 41 | } 42 | #endif 43 | 44 | } // namespace ShuffleVectorInst 45 | 46 | template 47 | inline ArgKind &getValue(VCINTR::Optional &opt) { 48 | #if VC_INTR_LLVM_VERSION_MAJOR < 15 49 | return opt.getValue(); 50 | #else 51 | return opt.value(); 52 | #endif 53 | } 54 | 55 | template 56 | inline const ArgKind &getValue(const VCINTR::Optional &opt) { 57 | #if VC_INTR_LLVM_VERSION_MAJOR < 15 58 | return opt.getValue(); 59 | #else 60 | return opt.value(); 61 | #endif 62 | } 63 | 64 | } // namespace VCINTR 65 | 66 | #endif // VCINTR_IR_INSTRUCTIONS_H 67 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/IR/Intrinsics.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2021-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_IR_INTRINSICS_H 10 | #define VCINTR_IR_INTRINSICS_H 11 | 12 | #include 13 | 14 | namespace VCINTR { 15 | 16 | namespace Intrinsic { 17 | inline std::string getName(llvm::Intrinsic::ID Id, 18 | llvm::ArrayRef Tys) { 19 | #if VC_INTR_LLVM_VERSION_MAJOR >= 13 20 | return llvm::Intrinsic::getNameNoUnnamedTypes(Id, Tys); 21 | #else 22 | return llvm::Intrinsic::getName(Id, Tys); 23 | #endif 24 | } 25 | 26 | } // namespace Intrinsic 27 | } // namespace VCINTR 28 | 29 | #endif // VCINTR_IR_INTRINSICS_H 30 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/IR/Type.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2022-2024 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_IR_TYPE_H 10 | #define VCINTR_IR_TYPE_H 11 | 12 | #include 13 | 14 | namespace VCINTR { 15 | namespace Type { 16 | 17 | inline llvm::Type *getNonOpaquePtrEltTy(const llvm::Type *PTy) { 18 | #if VC_INTR_LLVM_VERSION_MAJOR < 14 19 | return PTy->getPointerElementType(); 20 | #elif VC_INTR_LLVM_VERSION_MAJOR < 17 21 | return PTy->getNonOpaquePointerElementType(); 22 | #else 23 | llvm_unreachable("Pointers no longer have element types"); 24 | #endif 25 | } 26 | 27 | inline bool isOpaquePointerTy(const llvm::Type *Ty) { 28 | #if VC_INTR_LLVM_VERSION_MAJOR < 14 29 | return false; 30 | #elif VC_INTR_LLVM_VERSION_MAJOR < 17 31 | return Ty->isOpaquePointerTy(); 32 | #else 33 | return Ty->isPointerTy(); 34 | #endif 35 | } 36 | 37 | } // namespace Type 38 | } // namespace VCINTR 39 | 40 | #endif // VCINTR_IR_TYPE_H 41 | -------------------------------------------------------------------------------- /GenXIntrinsics/include/llvmVCWrapper/Support/Alignment.h: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #ifndef VCINTR_IR_ALIGNMENT_H 10 | #define VCINTR_IR_ALIGNMENT_H 11 | 12 | #include 13 | 14 | namespace VCINTR { 15 | 16 | namespace Align { 17 | 18 | #if VC_INTR_LLVM_VERSION_MAJOR <= 9 19 | template unsigned getAlign(TValue *Val) { 20 | return Val->getAlignment(); 21 | } 22 | #elif VC_INTR_LLVM_VERSION_MAJOR <= 10 23 | template llvm::MaybeAlign getAlign(TValue *Val) { 24 | // LLVM 10 instructions accept MaybeAlign but do not provide 25 | // getMaybeAlignMethod 26 | return llvm::MaybeAlign(Val->getAlignment()); 27 | } 28 | #else 29 | template auto getAlign(TValue *Val) { 30 | return Val->getAlign(); 31 | } 32 | #endif 33 | 34 | } // namespace Align 35 | 36 | } // namespace VCINTR 37 | 38 | #endif // VCINTR_IR_ALIGNMENT_H 39 | -------------------------------------------------------------------------------- /GenXIntrinsics/lib/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2019-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | add_subdirectory(GenXIntrinsics) 10 | -------------------------------------------------------------------------------- /GenXIntrinsics/lib/GenXIntrinsics/AdaptorsCommon.cpp: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #include "AdaptorsCommon.h" 10 | 11 | #include "llvm/IR/Function.h" 12 | #include "llvm/IR/Instructions.h" 13 | 14 | #include "llvmVCWrapper/IR/Type.h" 15 | 16 | namespace llvm { 17 | namespace genx { 18 | #if VC_INTR_LLVM_VERSION_MAJOR >= 9 19 | 20 | static void legalizeAttribute(Argument &Arg, Type *NewType, 21 | Attribute::AttrKind Kind) { 22 | 23 | if (!Arg.hasAttribute(Kind) || 24 | Arg.getAttribute(Kind).getValueAsType() == NewType) 25 | return; 26 | 27 | Arg.removeAttr(Kind); 28 | Arg.addAttr(Attribute::get(Arg.getParent()->getContext(), Kind, NewType)); 29 | } 30 | 31 | #endif 32 | 33 | void legalizeParamAttributes(Function *F) { 34 | assert(F && "Valid function ptr must be passed"); 35 | 36 | #if VC_INTR_LLVM_VERSION_MAJOR >= 9 37 | for (auto &Arg : F->args()) { 38 | auto *PTy = dyn_cast(Arg.getType()); 39 | if (!PTy) 40 | continue; 41 | 42 | #if VC_INTR_LLVM_VERSION_MAJOR >= 13 43 | #if VC_INTR_LLVM_VERSION_MAJOR < 17 44 | if (PTy->isOpaque()) 45 | #endif // VC_INTR_LLVM_VERSION_MAJOR < 18 46 | continue; 47 | #endif // VC_INTR_LLVM_VERSION_MAJOR >= 13 48 | 49 | auto *ElemType = VCINTR::Type::getNonOpaquePtrEltTy(PTy); 50 | 51 | legalizeAttribute(Arg, ElemType, Attribute::ByVal); 52 | 53 | #if VC_INTR_LLVM_VERSION_MAJOR >= 11 54 | legalizeAttribute(Arg, ElemType, Attribute::Preallocated); 55 | #if VC_INTR_LLVM_VERSION_MAJOR >= 12 56 | legalizeAttribute(Arg, ElemType, Attribute::ByRef); 57 | #if VC_INTR_LLVM_VERSION_MAJOR >= 13 58 | legalizeAttribute(Arg, ElemType, Attribute::InAlloca); 59 | legalizeAttribute(Arg, ElemType, Attribute::ElementType); 60 | #endif // VC_INTR_LLVM_VERSION_MAJOR >= 13 61 | #endif // VC_INTR_LLVM_VERSION_MAJOR >= 12 62 | #endif // VC_INTR_LLVM_VERSION_MAJOR >= 11 63 | } 64 | #endif // VC_INTR_LLVM_VERSION_MAJOR >= 9 65 | } 66 | } // namespace genx 67 | } // namespace llvm 68 | -------------------------------------------------------------------------------- /GenXIntrinsics/lib/GenXIntrinsics/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2019-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | set(LLVM_COMPONENTS 10 | CodeGen 11 | Support 12 | Core 13 | Analysis 14 | ) 15 | 16 | if(${LLVM_VERSION_MAJOR} VERSION_GREATER_EQUAL 21) 17 | list(APPEND LLVM_COMPONENTS TargetParser) 18 | endif() 19 | 20 | set(SRC_LIST 21 | GenXIntrinsics.cpp 22 | GenXRestoreIntrAttr.cpp 23 | GenXSimdCFLowering.cpp 24 | GenXSingleElementVectorUtil.cpp 25 | GenXSPIRVReaderAdaptor.cpp 26 | GenXSPIRVWriterAdaptor.cpp 27 | GenXVersion.cpp 28 | AdaptorsCommon.cpp 29 | GenXMetadata.cpp 30 | ) 31 | 32 | if(BUILD_EXTERNAL) 33 | add_library(LLVMGenXIntrinsics ${SRC_LIST}) 34 | llvm_update_compile_flags(LLVMGenXIntrinsics) 35 | add_dependencies(LLVMGenXIntrinsics GenXIntrinsicsGen) 36 | 37 | vc_get_llvm_targets(LLVM_LIBS ${LLVM_COMPONENTS}) 38 | target_link_libraries(LLVMGenXIntrinsics ${LLVM_LIBS}) 39 | else() 40 | # when we are building in LLVM infra, we need to conform 41 | set(LLVM_LINK_COMPONENTS 42 | ${LLVM_COMPONENTS} 43 | ) 44 | 45 | if(LLVM_LINK_LLVM_DYLIB) 46 | add_llvm_library(LLVMGenXIntrinsics STATIC DISABLE_LLVM_LINK_LLVM_DYLIB 47 | ${SRC_LIST} 48 | 49 | ADDITIONAL_HEADER_DIRS 50 | ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics 51 | DEPENDS 52 | GenXIntrinsicsGen 53 | intrinsics_gen 54 | LLVMCodeGen 55 | LLVMSupport 56 | LLVMCore 57 | LLVMAnalysis 58 | LLVMSPIRVLib 59 | ) 60 | else() 61 | add_llvm_library(LLVMGenXIntrinsics 62 | ${SRC_LIST} 63 | 64 | ADDITIONAL_HEADER_DIRS 65 | ${GENX_INTRINSICS_MAIN_INCLUDE_DIR}/llvm/GenXIntrinsics 66 | DEPENDS 67 | GenXIntrinsicsGen 68 | intrinsics_gen 69 | ) 70 | endif() 71 | endif() 72 | 73 | target_include_directories(LLVMGenXIntrinsics PUBLIC 74 | $ 75 | $ 76 | $ 77 | ) 78 | -------------------------------------------------------------------------------- /GenXIntrinsics/lib/GenXIntrinsics/GenXMetadata.cpp: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #include "llvm/GenXIntrinsics/GenXMetadata.h" 10 | 11 | #include 12 | #include 13 | #include 14 | 15 | using namespace llvm; 16 | 17 | MDNode *llvm::genx::GetOldStyleKernelMD(Function const &F) { 18 | auto *KernelMD = static_cast(nullptr); 19 | auto *KernelMDs = F.getParent()->getNamedMetadata(FunctionMD::GenXKernels); 20 | if (!KernelMDs) 21 | return KernelMD; 22 | 23 | for (unsigned I = 0, E = KernelMDs->getNumOperands(); I < E; ++I) { 24 | auto *Kernel = mdconst::dyn_extract( 25 | KernelMDs->getOperand(I)->getOperand(KernelMDOp::FunctionRef)); 26 | if (Kernel == &F) { 27 | KernelMD = KernelMDs->getOperand(I); 28 | break; 29 | } 30 | } 31 | return KernelMD; 32 | } 33 | -------------------------------------------------------------------------------- /GenXIntrinsics/lib/GenXIntrinsics/GenXRestoreIntrAttr.cpp: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | /*========================== begin_copyright_notice ============================ 10 | 11 | This file is distributed under the University of Illinois Open Source License. 12 | See LICENSE.TXT for details. 13 | 14 | ============================= end_copyright_notice ===========================*/ 15 | 16 | //===----------------------------------------------------------------------===// 17 | // 18 | /// GenXRestoreIntrAttr 19 | /// ------------------- 20 | /// 21 | /// This is a module pass that restores attributes for intrinsics: 22 | /// 23 | /// * Since SPIR-V doesn't save intrinsics' attributes, some important 24 | /// information can be lost. This pass restores it. 25 | /// 26 | /// * Only GenX intrinsics are handled. 27 | /// 28 | //===----------------------------------------------------------------------===// 29 | 30 | #include "llvm/GenXIntrinsics/GenXIntrOpts.h" 31 | #include "llvm/GenXIntrinsics/GenXIntrinsics.h" 32 | #include "llvm/Support/Debug.h" 33 | #include "llvm/Pass.h" 34 | 35 | #define DEBUG_TYPE "GENX_RESTOREINTRATTR" 36 | 37 | using namespace llvm; 38 | 39 | namespace { 40 | 41 | // GenXRestoreIntrAttr : restore intrinsics' attributes 42 | class GenXRestoreIntrAttr : public ModulePass { 43 | public: 44 | GenXRestoreIntrAttr(); 45 | 46 | StringRef getPassName() const override { 47 | return "GenX Restore Intrinsics' Attributes"; 48 | } 49 | 50 | bool runOnModule(Module &M) override; 51 | 52 | private: 53 | bool restoreAttributes(Function *F); 54 | 55 | public: 56 | static char ID; 57 | }; 58 | } // namespace 59 | 60 | namespace llvm { 61 | void initializeGenXRestoreIntrAttrPass(PassRegistry &); 62 | } 63 | INITIALIZE_PASS_BEGIN(GenXRestoreIntrAttr, "GenXRestoreIntrAttr", 64 | "GenXRestoreIntrAttr", false, false) 65 | INITIALIZE_PASS_END(GenXRestoreIntrAttr, "GenXRestoreIntrAttr", 66 | "GenXRestoreIntrAttr", false, false) 67 | 68 | char GenXRestoreIntrAttr::ID = 0; 69 | 70 | Pass *llvm::createGenXRestoreIntrAttrPass() { 71 | return new GenXRestoreIntrAttr; 72 | } 73 | 74 | GenXRestoreIntrAttr::GenXRestoreIntrAttr() : ModulePass(ID) { 75 | initializeGenXRestoreIntrAttrPass(*PassRegistry::getPassRegistry()); 76 | } 77 | 78 | bool GenXRestoreIntrAttr::restoreAttributes(Function *F) { 79 | LLVM_DEBUG(dbgs() << "Restoring attributes for: " << F->getName() << "\n"); 80 | F->setAttributes(GenXIntrinsic::getAttributes(F->getContext(), GenXIntrinsic::getGenXIntrinsicID(F))); 81 | return true; 82 | } 83 | 84 | bool GenXRestoreIntrAttr::runOnModule(Module &M) { 85 | bool Modified = false; 86 | 87 | for (auto &F : M.getFunctionList()) { 88 | if (GenXIntrinsic::isGenXIntrinsic(&F)) 89 | Modified |= restoreAttributes(&F); 90 | } 91 | 92 | return Modified; 93 | } 94 | -------------------------------------------------------------------------------- /GenXIntrinsics/lib/GenXIntrinsics/GenXVersion.cpp: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2021 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | // This source file defines interface functions to retrive version info. 10 | 11 | #include "llvm/GenXIntrinsics/GenXVersion.h" 12 | #include "llvm/GenXIntrinsics/GenXVersion.inc" 13 | 14 | std::string llvm::GenXIntrinsic::getVCIntrinsicsRevision() { 15 | #ifdef VCI_REVISION 16 | return VCI_REVISION; 17 | #else 18 | return ""; 19 | #endif 20 | } 21 | 22 | std::string llvm::GenXIntrinsic::getVCIntrinsicsRepository() { 23 | #ifdef VCI_REPOSITORY 24 | return VCI_REPOSITORY; 25 | #else 26 | return ""; 27 | #endif 28 | } 29 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/annot_mess_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test messy annnotations translation in writer. First valid 10 | ; annotation should be matched. 11 | 12 | ; UNSUPPORTED: opaque-pointers 13 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 14 | 15 | ; CHECK: define spir_kernel void @test( 16 | ; CHECK-SAME: %opencl.image2d_ro_t addrspace(1)* 17 | ; CHECK-NOT: "VCArgumentDesc" 18 | ; CHECK-NOT: "VCArgumentKind" 19 | ; CHECK-SAME: [[IM2D:%[^,]+]], 20 | ; CHECK-SAME: %opencl.sampler_t addrspace(2)* 21 | ; CHECK-NOT: "VCArgumentDesc" 22 | ; CHECK-NOT: "VCArgumentKind" 23 | ; CHECK-SAME: [[SAMP:%[^,]+]], 24 | ; CHECK-SAME: i8 addrspace(1)* 25 | ; CHECK-NOT: "VCArgumentDesc" 26 | ; CHECK-NOT: "VCArgumentKind" 27 | ; CHECK-SAME: [[PTR:%[^,]+]], 28 | ; CHECK-SAME: i32 29 | ; CHECK-NOT: "VCArgumentDesc" 30 | ; CHECK-NOT: "VCArgumentKind" 31 | ; CHECK-SAME: [[GEN:%[^)]+]]) 32 | define void @test(i32 %im2d, i32 %samp, i64 %ptr, i32 %gen) { 33 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_ro_t(%opencl.image2d_ro_t addrspace(1)* [[IM2D]]) 34 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p2opencl.sampler_t(%opencl.sampler_t addrspace(2)* [[SAMP]]) 35 | ; CHECK-NEXT: ptrtoint i8 addrspace(1)* [[PTR]] to i64 36 | ; CHECK-NEXT: ret void 37 | ret void 38 | } 39 | 40 | ; CHECK-NOT: !genx.kernels 41 | !genx.kernels = !{!0} 42 | 43 | !0 = !{void (i32, i32, i64, i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 44 | !1 = !{i32 2, i32 1, i32 0, i32 0} 45 | !2 = !{i32 0, i32 0, i32 0, i32 0} 46 | !3 = !{!"image2d_t buffer_t read_only read_write", !"sampler_t read_only", !"svmptr_t write_only", !"write_only"} 47 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that reader can cope with mixed mode when some 10 | ; arguments use address convert and some do not. 11 | 12 | ; UNSUPPORTED: opaque-pointers 13 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 14 | 15 | %intel.buffer_rw_t = type opaque 16 | %opencl.image1d_rw_t = type opaque 17 | %opencl.image1d_buffer_rw_t = type opaque 18 | %opencl.image2d_rw_t = type opaque 19 | %opencl.image3d_rw_t = type opaque 20 | %opencl.sampler_t = type opaque 21 | 22 | ; CHECK: define dllexport spir_kernel void @test( 23 | ; CHECK-SAME: %intel.buffer_rw_t addrspace(1)* 24 | ; CHECK-SAME: [[BUF:%[^,]+]], 25 | ; CHECK-SAME: %opencl.image1d_rw_t addrspace(1)* 26 | ; CHECK-SAME: [[IM1D:%[^,]+]], 27 | ; CHECK-SAME: %opencl.image1d_buffer_rw_t addrspace(1)* 28 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 29 | ; CHECK-SAME: %opencl.image2d_rw_t addrspace(1)* 30 | ; CHECK-SAME: [[IM2D:%[^,]+]], 31 | ; CHECK-SAME: %opencl.image3d_rw_t addrspace(1)* 32 | ; CHECK-SAME: [[IM3D:%[^,]+]], 33 | ; CHECK-SAME: %opencl.sampler_t addrspace(2)* 34 | ; CHECK-SAME: [[SAMP:%[^,]+]], 35 | ; CHECK-SAME: i8 addrspace(1)* 36 | ; CHECK-SAME: [[PTR:%[^,]+]], 37 | ; CHECK-SAME: <4 x i32> 38 | ; CHECK-SAME: [[GEN:%[^)]+]]) 39 | define spir_kernel void @test(%intel.buffer_rw_t addrspace(1)* %buf, %opencl.image1d_rw_t addrspace(1)* %im1d, %opencl.image1d_buffer_rw_t addrspace(1)* %im1db, %opencl.image2d_rw_t addrspace(1)* %im2d, %opencl.image3d_rw_t addrspace(1)* %im3d, %opencl.sampler_t addrspace(2)* %samp, i8 addrspace(1)* %ptr, <4 x i32> %gen) #0 { 40 | ; CHECK-NEXT: ptrtoint %intel.buffer_rw_t addrspace(1)* [[BUF]] to i32 41 | %buf.conv = call i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)* %buf) 42 | ; CHECK-NEXT: ptrtoint %opencl.image1d_buffer_rw_t addrspace(1)* [[IM1DB]] to i32 43 | %im1db.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_buffer_rw_t(%opencl.image1d_buffer_rw_t addrspace(1)* %im1db) 44 | ; CHECK-NEXT: ptrtoint %opencl.image3d_rw_t addrspace(1)* [[IM3D]] to i32 45 | %im3d.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image3d_rw_t(%opencl.image3d_rw_t addrspace(1)* %im3d) 46 | ; CHECK-NEXT: ptrtoint i8 addrspace(1)* [[PTR]] to i64 47 | %ptr.conv = ptrtoint i8 addrspace(1)* %ptr to i64 48 | ; CHECK-NEXT: ret void 49 | ret void 50 | } 51 | 52 | declare i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)*) #0 53 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image1d_buffer_rw_t(%opencl.image1d_buffer_rw_t addrspace(1)*) #0 54 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image3d_rw_t(%opencl.image3d_rw_t addrspace(1)*) #0 55 | 56 | attributes #0 = { "VCFunction" } 57 | 58 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 59 | ; CHECK: [[KERNEL]] = !{void (%intel.buffer_rw_t addrspace(1)*, %opencl.image1d_rw_t addrspace(1)*, %opencl.image1d_buffer_rw_t addrspace(1)*, %opencl.image2d_rw_t addrspace(1)*, %opencl.image3d_rw_t addrspace(1)*, %opencl.sampler_t addrspace(2)*, i8 addrspace(1)*, <4 x i32>)* @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 60 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 2, i32 2, i32 2, i32 2, i32 1, i32 0, i32 0} 61 | ; CHECK-DAG: ![[DESCS]] = !{!"buffer_t read_write", !"image1d_t read_write", !"image1d_buffer_t read_write", !"image2d_t read_write", !"image3d_t read_write", !"sampler_t", !"svmptr_t", !""} 62 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that reader correctly restores metadata and does 10 | ; not change other things if there is no address conversion 11 | ; but correct SPIRV types in signature. 12 | 13 | ; UNSUPPORTED: opaque-pointers 14 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 15 | 16 | %intel.buffer_rw_t = type opaque 17 | %opencl.image1d_rw_t = type opaque 18 | %opencl.image1d_buffer_rw_t = type opaque 19 | %opencl.image2d_rw_t = type opaque 20 | %opencl.image3d_rw_t = type opaque 21 | %opencl.sampler_t = type opaque 22 | 23 | ; CHECK: define dllexport spir_kernel void @test( 24 | ; CHECK-SAME: %intel.buffer_rw_t addrspace(1)* 25 | ; CHECK-SAME: [[BUF:%[^,]+]], 26 | ; CHECK-SAME: %opencl.image1d_rw_t addrspace(1)* 27 | ; CHECK-SAME: [[IM1D:%[^,]+]], 28 | ; CHECK-SAME: %opencl.image1d_buffer_rw_t addrspace(1)* 29 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 30 | ; CHECK-SAME: %opencl.image2d_rw_t addrspace(1)* 31 | ; CHECK-SAME: [[IM2D:%[^,]+]], 32 | ; CHECK-SAME: %opencl.image3d_rw_t addrspace(1)* 33 | ; CHECK-SAME: [[IM3D:%[^,]+]], 34 | ; CHECK-SAME: %opencl.sampler_t addrspace(2)* 35 | ; CHECK-SAME: [[SAMP:%[^,]+]], 36 | ; CHECK-SAME: i8 addrspace(1)* 37 | ; CHECK-SAME: [[PTR:%[^,]+]], 38 | ; CHECK-SAME: <4 x i32> 39 | ; CHECK-SAME: [[GEN:%[^)]+]]) 40 | define spir_kernel void @test(%intel.buffer_rw_t addrspace(1)* %buf, %opencl.image1d_rw_t addrspace(1)* %im1d, %opencl.image1d_buffer_rw_t addrspace(1)* %im1db, %opencl.image2d_rw_t addrspace(1)* %im2d, %opencl.image3d_rw_t addrspace(1)* %im3d, %opencl.sampler_t addrspace(2)* %samp, i8 addrspace(1)* %ptr, <4 x i32> %gen) #0 { 41 | ; CHECK-NEXT: ret void 42 | ret void 43 | } 44 | 45 | attributes #0 = { "VCFunction" } 46 | 47 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 48 | ; CHECK: [[KERNEL]] = !{void (%intel.buffer_rw_t addrspace(1)*, %opencl.image1d_rw_t addrspace(1)*, %opencl.image1d_buffer_rw_t addrspace(1)*, %opencl.image2d_rw_t addrspace(1)*, %opencl.image3d_rw_t addrspace(1)*, %opencl.sampler_t addrspace(2)*, i8 addrspace(1)*, <4 x i32>)* @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 49 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 2, i32 2, i32 2, i32 2, i32 1, i32 0, i32 0} 50 | ; CHECK-DAG: ![[DESCS]] = !{!"buffer_t read_write", !"image1d_t read_write", !"image1d_buffer_t read_write", !"image2d_t read_write", !"image3d_t read_write", !"sampler_t", !"svmptr_t", !""} 51 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that writer does not changes signature if correct 10 | ; types are already used. Just drop all annotations. 11 | 12 | ; UNSUPPORTED: opaque-pointers 13 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 14 | 15 | %intel.buffer_rw_t = type opaque 16 | %opencl.image1d_rw_t = type opaque 17 | %opencl.image1d_buffer_rw_t = type opaque 18 | %opencl.image2d_rw_t = type opaque 19 | %opencl.image3d_rw_t = type opaque 20 | %opencl.sampler_t = type opaque 21 | 22 | ; CHECK: define spir_kernel void @test( 23 | ; CHECK-SAME: %intel.buffer_rw_t addrspace(1)* 24 | ; CHECK-NOT: "VCArgumentDesc" 25 | ; CHECK-NOT: "VCArgumentKind" 26 | ; CHECK-SAME: [[BUF:%[^,]+]], 27 | ; CHECK-SAME: %opencl.image1d_rw_t addrspace(1)* 28 | ; CHECK-NOT: "VCArgumentDesc" 29 | ; CHECK-NOT: "VCArgumentKind" 30 | ; CHECK-SAME: [[IM1D:%[^,]+]], 31 | ; CHECK-SAME: %opencl.image1d_buffer_rw_t addrspace(1)* 32 | ; CHECK-NOT: "VCArgumentDesc" 33 | ; CHECK-NOT: "VCArgumentKind" 34 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 35 | ; CHECK-SAME: %opencl.image2d_rw_t addrspace(1)* 36 | ; CHECK-NOT: "VCArgumentDesc" 37 | ; CHECK-NOT: "VCArgumentKind" 38 | ; CHECK-SAME: [[IM2D:%[^,]+]], 39 | ; CHECK-SAME: %opencl.image3d_rw_t addrspace(1)* 40 | ; CHECK-NOT: "VCArgumentDesc" 41 | ; CHECK-NOT: "VCArgumentKind" 42 | ; CHECK-SAME: [[IM3D:%[^,]+]], 43 | ; CHECK-SAME: %opencl.sampler_t addrspace(2)* 44 | ; CHECK-NOT: "VCArgumentDesc" 45 | ; CHECK-NOT: "VCArgumentKind" 46 | ; CHECK-SAME: [[SAMP:%[^,]+]], 47 | ; CHECK-SAME: i8 addrspace(1)* 48 | ; CHECK-NOT: "VCArgumentDesc" 49 | ; CHECK-NOT: "VCArgumentKind" 50 | ; CHECK-SAME: [[PTR:%[^,]+]], 51 | ; CHECK-SAME: <4 x i32> 52 | ; CHECK-NOT: "VCArgumentDesc" 53 | ; CHECK-NOT: "VCArgumentKind" 54 | ; CHECK-SAME: [[GEN:%[^)]+]]) 55 | define void @test(%intel.buffer_rw_t addrspace(1)* %buf, %opencl.image1d_rw_t addrspace(1)* %im1d, %opencl.image1d_buffer_rw_t addrspace(1)* %im1db, %opencl.image2d_rw_t addrspace(1)* %im2d, %opencl.image3d_rw_t addrspace(1)* %im3d, %opencl.sampler_t addrspace(2)* %samp, i8 addrspace(1)* %ptr, <4 x i32> %gen) { 56 | ; CHECK-NEXT: ret void 57 | ret void 58 | } 59 | 60 | ; CHECK-NOT: !genx.kernels 61 | !genx.kernels = !{!0} 62 | 63 | !0 = !{void (%intel.buffer_rw_t addrspace(1)*, %opencl.image1d_rw_t addrspace(1)*, %opencl.image1d_buffer_rw_t addrspace(1)*, %opencl.image2d_rw_t addrspace(1)*, %opencl.image3d_rw_t addrspace(1)*, %opencl.sampler_t addrspace(2)*, i8 addrspace(1)*, <4 x i32>)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 64 | !1 = !{i32 2, i32 2, i32 2, i32 2, i32 2, i32 1, i32 0, i32 0} 65 | !2 = !{i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0} 66 | !3 = !{!"buffer_t", !"image1d_t", !"image1d_buffer_t", !"image2d_t", !"image3d_t", !"sampler_t", !"svmptr_t", !""} 67 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/annotated_args_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel arguments translation from old style with metadata to 10 | ; new style with opaque types that SPIRV translator can 11 | ; understand. Here annotations for OCL runtime are used. 12 | 13 | ; UNSUPPORTED: opaque-pointers 14 | ; XFAIL: llvm13, llvm14 15 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 16 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 17 | 18 | ; CHECK: define spir_kernel void @test( 19 | ; CHECK-SAME: %intel.buffer_rw_t addrspace(1)* 20 | ; CHECK-NOT: "VCArgumentDesc" 21 | ; CHECK-NOT: "VCArgumentKind" 22 | ; CHECK-SAME: [[BUF:%[^,]+]], 23 | ; CHECK-SAME: %opencl.image1d_rw_t addrspace(1)* 24 | ; CHECK-NOT: "VCArgumentDesc" 25 | ; CHECK-NOT: "VCArgumentKind" 26 | ; CHECK-SAME: [[IM1D:%[^,]+]], 27 | ; CHECK-SAME: %opencl.image1d_buffer_rw_t addrspace(1)* 28 | ; CHECK-NOT: "VCArgumentDesc" 29 | ; CHECK-NOT: "VCArgumentKind" 30 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 31 | ; CHECK-SAME: %opencl.image2d_rw_t addrspace(1)* 32 | ; CHECK-NOT: "VCArgumentDesc" 33 | ; CHECK-NOT: "VCArgumentKind" 34 | ; CHECK-SAME: [[IM2D:%[^,]+]], 35 | ; CHECK-SAME: %opencl.image3d_rw_t addrspace(1)* 36 | ; CHECK-NOT: "VCArgumentDesc" 37 | ; CHECK-NOT: "VCArgumentKind" 38 | ; CHECK-SAME: [[IM3D:%[^,]+]], 39 | ; CHECK-SAME: %opencl.sampler_t addrspace(2)* 40 | ; CHECK-NOT: "VCArgumentDesc" 41 | ; CHECK-NOT: "VCArgumentKind" 42 | ; CHECK-SAME: [[SAMP:%[^,]+]], 43 | ; CHECK-SAME: i8 addrspace(1)* 44 | ; CHECK-NOT: "VCArgumentDesc" 45 | ; CHECK-NOT: "VCArgumentKind" 46 | ; CHECK-SAME: [[PTR:%[^,]+]], 47 | ; CHECK-SAME: <4 x i32> 48 | ; CHECK-NOT: "VCArgumentDesc" 49 | ; CHECK-NOT: "VCArgumentKind" 50 | ; CHECK-SAME: [[GEN:%[^)]+]]) 51 | define void @test(i32 %buf, i32 %im1d, i32 %im1db, i32 %im2d, i32 %im3d, i32 %samp, i64 %ptr, <4 x i32> %gen) { 52 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)* [[BUF]]) 53 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_rw_t(%opencl.image1d_rw_t addrspace(1)* [[IM1D]]) 54 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_buffer_rw_t(%opencl.image1d_buffer_rw_t addrspace(1)* [[IM1DB]]) 55 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_rw_t(%opencl.image2d_rw_t addrspace(1)* [[IM2D]]) 56 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image3d_rw_t(%opencl.image3d_rw_t addrspace(1)* [[IM3D]]) 57 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p2opencl.sampler_t(%opencl.sampler_t addrspace(2)* [[SAMP]]) 58 | ; CHECK-NEXT: ptrtoint i8 addrspace(1)* [[PTR]] to i64 59 | ; CHECK-NEXT: ret void 60 | ret void 61 | } 62 | 63 | ; CHECK-NOT: !genx.kernels 64 | !genx.kernels = !{!0} 65 | 66 | !0 = !{void (i32, i32, i32, i32, i32, i32, i64, <4 x i32>)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 67 | !1 = !{i32 2, i32 2, i32 2, i32 2, i32 2, i32 1, i32 0, i32 0} 68 | !2 = !{i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0} 69 | !3 = !{!"buffer_t", !"image1d_t", !"image1d_buffer_t", !"image2d_t", !"image3d_t", !"sampler_t", !"svmptr_t", !""} 70 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that adaptor correctly handles parameter attributes with types. 10 | 11 | ; UNSUPPORTED: llvm8, opaque-pointers 12 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | %foo = type { i32 } 15 | 16 | ; CHECK: define dllexport spir_kernel void @test( 17 | ; CHECK-SAME: %foo addrspace(1)* byval(%foo) 18 | ; CHECK-SAME: [[ARG:%[^)]+]]) 19 | define spir_kernel void @test(%foo addrspace(1)* byval(%foo) %arg) #0 { 20 | ret void 21 | } 22 | 23 | ; CHECK: define dllexport spir_kernel void @test_restore( 24 | ; CHECK-SAME: %foo* byval(%foo) 25 | ; CHECK-SAME: [[ARG:%[^)]+]]) 26 | define spir_kernel void @test_restore(i8 addrspace(1)* byval(i8) %arg) #0 { 27 | %conv = call %foo* @llvm.genx.address.convert.p0foo.p1i8(i8 addrspace(1)* %arg) 28 | ret void 29 | } 30 | 31 | declare %foo* @llvm.genx.address.convert.p0foo.p1i8(i8 addrspace(1)*) #0 32 | 33 | attributes #0 = { "VCFunction" } 34 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that adaptor correctly handles parameter attributes with types. 10 | 11 | ; UNSUPPORTED: llvm8, opaque-pointers 12 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | %foo = type { i32 } 15 | 16 | ; CHECK: define spir_kernel void @test( 17 | ; CHECK-SAME: %foo addrspace(1)* byval(%foo) 18 | ; CHECK-NOT: "VCArgumentDesc" 19 | ; CHECK-NOT: "VCArgumentKind" 20 | ; CHECK-SAME: [[ARG:%[^)]+]]) 21 | define void @test(%foo addrspace(1)* byval(%foo) %arg) { 22 | ; CHECK-NEXT: ret void 23 | ret void 24 | } 25 | 26 | ; CHECK-NOT: !genx.kernels 27 | !genx.kernels = !{!0} 28 | 29 | !0 = !{void (%foo addrspace(1)*)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0} 30 | !1 = !{i32 0} 31 | !2 = !{i32 0} 32 | !3 = !{!"svmptr_t"} 33 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/combined_args_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test combined reader translation: kernel has both native SPIRV types 10 | ; and impicit arguments. Implicit arguments would not show in normal 11 | ; flow, though they appear in old cmc. 12 | 13 | ; UNSUPPORTED: opaque-pointers 14 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 15 | 16 | %opencl.image2d_ro_t = type opaque 17 | %opencl.image2d_wo_t = type opaque 18 | 19 | ; CHECK: define dllexport spir_kernel void @test( 20 | ; CHECK-SAME: %opencl.image2d_ro_t addrspace(1)* 21 | ; CHECK-SAME: [[IN:%[^,]+]], 22 | ; CHECK-SAME: %opencl.image2d_wo_t addrspace(1)* 23 | ; CHECK-SAME: [[OUT:%[^,]+]], 24 | ; CHECK-SAME: <3 x i32> 25 | ; CHECK-SAME: [[LOCAL_ID:%[^)]+]]) 26 | define spir_kernel void @test(%opencl.image2d_ro_t addrspace(1)* %in, %opencl.image2d_wo_t addrspace(1)* %out, <3 x i32> "VCArgumentKind"="24" %__arg_llvm.genx.local.id) #0 { 27 | ; CHECK-NEXT: [[IN_CONV:%.*]] = ptrtoint %opencl.image2d_ro_t addrspace(1)* [[IN]] to i32 28 | %in.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_ro_t(%opencl.image2d_ro_t addrspace(1)* %in) 29 | ; CHECK-NEXT: [[OUT_CONV:%.*]] = ptrtoint %opencl.image2d_wo_t addrspace(1)* [[OUT]] to i32 30 | %out.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_wo_t(%opencl.image2d_wo_t addrspace(1)* %out) 31 | ; CHECK-NEXT: [[LOCAL_ID_X:%.*]] = extractelement <3 x i32> [[LOCAL_ID]], i32 0 32 | %local.id.x = extractelement <3 x i32> %__arg_llvm.genx.local.id, i32 0 33 | ; CHECK-NEXT: [[VAL:%.*]] = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 [[IN_CONV]], i32 0, i32 32, i32 [[LOCAL_ID_X]], i32 0) 34 | %val = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 %in.conv, i32 0, i32 32, i32 %local.id.x, i32 0) 35 | ; CHECK-NEXT: tail call void @llvm.genx.media.st.v8i32(i32 0, i32 [[OUT_CONV]], i32 0, i32 32, i32 [[LOCAL_ID_X]], i32 0, <8 x i32> [[VAL]]) 36 | tail call void @llvm.genx.media.st.v8i32(i32 0, i32 %out.conv, i32 0, i32 32, i32 %local.id.x, i32 0, <8 x i32> %val) 37 | ; CHECK-NEXT: ret void 38 | ret void 39 | } 40 | 41 | declare <8 x i32> @llvm.genx.media.ld.v8i32(i32, i32, i32, i32, i32, i32) 42 | declare void @llvm.genx.media.st.v8i32(i32, i32, i32, i32, i32, i32, <8 x i32>) 43 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image2d_ro_t(%opencl.image2d_ro_t addrspace(1)*) #0 44 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image2d_wo_t(%opencl.image2d_wo_t addrspace(1)*) #0 45 | 46 | attributes #0 = { "VCFunction" } 47 | 48 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 49 | ; CHECK: [[KERNEL]] = !{void (%opencl.image2d_ro_t addrspace(1)*, %opencl.image2d_wo_t addrspace(1)*, <3 x i32>)* @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 50 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 2, i32 24} 51 | ; CHECK-DAG: ![[DESCS]] = !{!"image2d_t read_only", !"image2d_t write_only", !""} 52 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/combined_args_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test combined writer translation: kernel has both annotated explicit 10 | ; arguments and impicit arguments. Implicit arguments would not show 11 | ; in normal flow, though they appear in old cmc. 12 | 13 | ; XFAIL: llvm13, llvm14 14 | ; UNSUPPORTED: opaque-pointers 15 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 16 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 17 | 18 | ; CHECK: define spir_kernel void @test( 19 | ; CHECK-SAME: %opencl.image2d_ro_t addrspace(1)* 20 | ; CHECK-NOT: "VCArgumentDesc" 21 | ; CHECK-NOT: "VCArgumentKind" 22 | ; CHECK-SAME: [[IN:%[^,]+]], 23 | ; CHECK-SAME: %opencl.image2d_wo_t addrspace(1)* 24 | ; CHECK-NOT: "VCArgumentDesc" 25 | ; CHECK-NOT: "VCArgumentKind" 26 | ; CHECK-SAME: [[OUT:%[^,]+]], 27 | ; CHECK-SAME: <3 x i32> 28 | ; CHECK-SAME: "VCArgumentKind"="24" 29 | ; CHECK-SAME: [[LOCAL_ID:%[^)]+]]) 30 | define void @test(i32 %in, i32 %out, <3 x i32> %__arg_llvm.genx.local.id) { 31 | ; CHECK-NEXT: [[IN_CONV:%.*]] = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_ro_t(%opencl.image2d_ro_t addrspace(1)* [[IN]]) 32 | ; CHECK-NEXT: [[OUT_CONV:%.*]] = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_wo_t(%opencl.image2d_wo_t addrspace(1)* [[OUT]]) 33 | ; CHECK-NEXT: [[LOCAL_ID_X:%.*]] = extractelement <3 x i32> [[LOCAL_ID]], i32 0 34 | ; CHECK-NEXT: [[VAL:%.*]] = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 [[IN_CONV]], i32 0, i32 32, i32 [[LOCAL_ID_X]], i32 0) 35 | ; CHECK-NEXT: tail call void @llvm.genx.media.st.v8i32(i32 0, i32 [[OUT_CONV]], i32 0, i32 32, i32 [[LOCAL_ID_X]], i32 0, <8 x i32> [[VAL]]) 36 | ; CHECK-NEXT: ret void 37 | %local.id.x = extractelement <3 x i32> %__arg_llvm.genx.local.id, i32 0 38 | %val = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 %in, i32 0, i32 32, i32 %local.id.x, i32 0) 39 | tail call void @llvm.genx.media.st.v8i32(i32 0, i32 %out, i32 0, i32 32, i32 %local.id.x, i32 0, <8 x i32> %val) 40 | ret void 41 | } 42 | 43 | declare <8 x i32> @llvm.genx.media.ld.v8i32(i32, i32, i32, i32, i32, i32) 44 | declare void @llvm.genx.media.st.v8i32(i32, i32, i32, i32, i32, i32, <8 x i32>) 45 | 46 | ; CHECK-NOT: !genx.kernels 47 | !genx.kernels = !{!0} 48 | 49 | !0 = !{void (i32, i32, <3 x i32>)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 50 | !1 = !{i32 2, i32 2, i32 24} 51 | !2 = !{i32 0, i32 0} 52 | !3 = !{!"image2d_t read_only", !"image2d_t write_only"} 53 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/empty_kernel_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2022 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test empty kernel metadata translation: old -> new. 10 | 11 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 12 | 13 | ; CHECK: @test() #[[ATTR_GROUP:[0-9]+]] 14 | define void @test() #0 { 15 | ret void 16 | } 17 | 18 | ; CHECK: attributes #[[ATTR_GROUP]] = { 19 | ; CHECK-DAG: "VCFunction" 20 | ; CHECK-DAG: "VCSLMSize"="0" 21 | ; CHECK: } 22 | attributes #0 = { "CMGenxMain" } 23 | 24 | ; CHECK-NOT: !genx.kernels 25 | !genx.kernels = !{!0} 26 | 27 | !0 = !{void ()* @test, !"test", !1, i32 0, i32 0, !1, !1, i32 0, i32 0} 28 | !1 = !{} 29 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that adaptor correctly translates function attributes to VC-specific 10 | ; metadata (the processed attributes are expected to be discarded) 11 | 12 | ; UNSUPPORTED: llvm8 13 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 14 | ; CHECK: @test_VCFunction() 15 | ; CHECK: @test_VCStackCall() 16 | ; CHECK-SAME: #[[FATR_STACK_CALL_ATTR_IDX:[0-9]+]] 17 | ; CHECK: @test_VCCallable() 18 | ; CHECK-SAME: #[[FATR_CALLABLE_ATTR_IDX:[0-9]+]] 19 | ; CHECK: @test_VCFCEntry() 20 | ; CHECK-SAME: #[[FATR_FC_ENTRY_IDX:[0-9]+]] 21 | ; CHECK: @test_VCSIMTCall() 22 | ; CHECK-SAME: #[[FATR_SIMT_CALL_IDX:[0-9]+]] 23 | ; CHECK: @test_VCFloatControl() 24 | ; CHECK-SAME: #[[FATR_FLOAT_CONTROL_IDX:[0-9]+]] 25 | ; CHECK: @test_VCSLMSize() 26 | ; CHECK-SAME: #[[FATR_SLM_SIZE_IDX:[0-9]+]] 27 | 28 | define void @test_VCFunction() #0 { 29 | ret void 30 | } 31 | define void @test_VCStackCall() #1 { 32 | ret void 33 | } 34 | define void @test_VCCallable() #2 { 35 | ret void 36 | } 37 | define void @test_VCFCEntry() #3 { 38 | ret void 39 | } 40 | define void @test_VCSIMTCall() #4 { 41 | ret void 42 | } 43 | define void @test_VCFloatControl() #5 { 44 | ret void 45 | } 46 | define spir_kernel void @test_VCSLMSize() #6 { 47 | ret void 48 | } 49 | 50 | ; CHECK-DAG: attributes #[[FATR_STACK_CALL_ATTR_IDX]] = { "CMStackCall" } 51 | ; CHECK-DAG: attributes #[[FATR_CALLABLE_ATTR_IDX]] = { "CMCallable" } 52 | ; CHECK-DAG: attributes #[[FATR_FC_ENTRY_IDX]] = { "CMEntry" } 53 | ; CHECK-DAG: attributes #[[FATR_SIMT_CALL_IDX]] = { "CMGenxSIMT" } 54 | ; CHECK-DAG: attributes #[[FATR_FLOAT_CONTROL_IDX]] = { "CMFloatControl"="0" } 55 | ; CHECK-DAG: attributes #[[FATR_SLM_SIZE_IDX]] = { "CMGenxMain" } 56 | 57 | ; CHECK-DAG: !{{{.*}} @test_VCSLMSize, !"test_VCSLMSize", !{{[0-9]+}}, i32 100500, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, i32 0} 58 | 59 | attributes #0 = { "VCFunction" } 60 | attributes #1 = { "VCFunction" "VCStackCall" } 61 | attributes #2 = { "VCFunction" "VCCallable" } 62 | attributes #3 = { "VCFunction" "VCFCEntry" } 63 | attributes #4 = { "VCFunction" "VCSIMTCall" } 64 | attributes #5 = { "VCFunction" "VCFloatControl"="0" } 65 | attributes #6 = { "VCFunction" "VCSLMSize"="100500" } 66 | 67 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/image_array_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test reader translation of image array arguments. 10 | 11 | ; UNSUPPORTED: opaque-pointers 12 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | %opencl.image1d_array_ro_t = type opaque 15 | %opencl.image2d_array_wo_t = type opaque 16 | 17 | ; CHECK: define dllexport spir_kernel void @test( 18 | ; CHECK-SAME: %opencl.image1d_array_ro_t addrspace(1)* 19 | ; CHECK-SAME: [[IM1D:%[^,]+]], 20 | ; CHECK-SAME: %opencl.image2d_array_wo_t addrspace(1)* 21 | ; CHECK-SAME: [[IM2D:%[^,]+]]) 22 | define spir_kernel void @test(%opencl.image1d_array_ro_t addrspace(1)* %im1d, %opencl.image2d_array_wo_t addrspace(1)* %im2d) #0 { 23 | ; CHECK-NEXT: ptrtoint %opencl.image1d_array_ro_t addrspace(1)* [[IM1D]] to i32 24 | %im1d.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_array_ro_t(%opencl.image1d_array_ro_t addrspace(1)* %im1d) 25 | ; CHECK-NEXT: ptrtoint %opencl.image2d_array_wo_t addrspace(1)* [[IM2D]] to i32 26 | %im2d.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_array_wo_t(%opencl.image2d_array_wo_t addrspace(1)* %im2d) 27 | ; CHECK-NEXT: ret void 28 | ret void 29 | } 30 | 31 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image1d_array_ro_t(%opencl.image1d_array_ro_t addrspace(1)*) #0 32 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image2d_array_wo_t(%opencl.image2d_array_wo_t addrspace(1)*) #0 33 | 34 | attributes #0 = { "VCFunction" } 35 | 36 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 37 | ; CHECK: [[KERNEL]] = !{void (%opencl.image1d_array_ro_t addrspace(1)*, %opencl.image2d_array_wo_t addrspace(1)*)* @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} 38 | ; CHECK-DAG: [[KINDS]] = !{i32 2, i32 2} 39 | ; CHECK-DAG: [[DESCS]] = !{!"image1d_array_t read_only", !"image2d_array_t write_only"} 40 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/image_array_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test writer translation of image array arguments. 10 | 11 | ; UNSUPPORTED: opaque-pointers 12 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: define spir_kernel void @test( 15 | ; CHECK-SAME: %opencl.image1d_array_ro_t addrspace(1)* 16 | ; CHECK-NOT: "VCArgumentDesc" 17 | ; CHECK-NOT: "VCArgumentKind" 18 | ; CHECK-SAME: [[IM1DARR:%[^,]+]], 19 | ; CHECK-SAME: %opencl.image2d_array_wo_t addrspace(1)* 20 | ; CHECK-NOT: "VCArgumentDesc" 21 | ; CHECK-NOT: "VCArgumentKind" 22 | ; CHECK-SAME: [[IM2DARR:%[^)]+]]) 23 | define void @test(i32 %im1darr, i32 %im2darr) { 24 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_array_ro_t(%opencl.image1d_array_ro_t addrspace(1)* [[IM1DARR]]) 25 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_array_wo_t(%opencl.image2d_array_wo_t addrspace(1)* [[IM2DARR]]) 26 | ; CHECK-NEXT: ret void 27 | ret void 28 | } 29 | 30 | ; CHECK-NOT: !genx.kernels 31 | !genx.kernels = !{!0} 32 | 33 | !0 = !{void (i32, i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 34 | !1 = !{i32 2, i32 2} 35 | !2 = !{i32 0, i32 0} 36 | !3 = !{!"image1d_array_t read_only", !"image2d_array_t write_only"} 37 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/media_block_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test reader translation of media block image arguments. 10 | 11 | ; UNSUPPORTED: opaque-pointers 12 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | %opencl.image2d_ro_t = type opaque 15 | 16 | ; CHECK: define dllexport spir_kernel void @test( 17 | ; CHECK-SAME: %opencl.image2d_ro_t addrspace(1)* 18 | ; CHECK-NOT: "VCMediaBlockIO" 19 | ; CHECK-SAME: [[IM2D:%[^,]+]]) 20 | define spir_kernel void @test(%opencl.image2d_ro_t addrspace(1)* "VCMediaBlockIO" %im2d) #0 { 21 | ; CHECK-NEXT: ptrtoint %opencl.image2d_ro_t addrspace(1)* [[IM2D]] to i32 22 | %im2d.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_ro_t(%opencl.image2d_ro_t addrspace(1)* %im2d) 23 | ; CHECK-NEXT: ret void 24 | ret void 25 | } 26 | 27 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image2d_ro_t(%opencl.image2d_ro_t addrspace(1)*) #0 28 | 29 | attributes #0 = { "VCFunction" } 30 | 31 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 32 | ; CHECK: [[KERNEL]] = !{void (%opencl.image2d_ro_t addrspace(1)*)* @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} 33 | ; CHECK-DAG: [[KINDS]] = !{i32 2} 34 | ; CHECK-DAG: [[DESCS]] = !{!"image2d_media_block_t read_only"} 35 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/media_block_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test writer translation of media block images arguments. 10 | 11 | ; UNSUPPORTED: opaque-pointers 12 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: define spir_kernel void @test( 15 | ; CHECK-SAME: %opencl.image2d_ro_t addrspace(1)* 16 | ; CHECK-SAME: "VCMediaBlockIO" 17 | ; CHECK-NOT: "VCArgumentDesc" 18 | ; CHECK-NOT: "VCArgumentKind" 19 | ; CHECK-SAME: [[IMAGE:%[^)]+]]) 20 | define void @test(i32 %image) { 21 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_ro_t(%opencl.image2d_ro_t addrspace(1)* [[IMAGE]]) 22 | ; CHECK-NEXT: ret void 23 | ret void 24 | } 25 | 26 | ; CHECK-NOT: !genx.kernels 27 | !genx.kernels = !{!0} 28 | 29 | !0 = !{void (i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 30 | !1 = !{i32 2} 31 | !2 = !{i32 0} 32 | !3 = !{!"image2d_media_block_t read_only"} 33 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/no_kernels_module_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2022 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test general translation of attributes within module that has no kernels 10 | 11 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 12 | 13 | ; CHECK: @some_func 14 | ; CHECK-SAME: #[[ATTR_GROUP:[0-9]+]] 15 | define <16 x float> @some_func(<16 x float> %x) local_unnamed_addr #0 { 16 | ret <16 x float> %x 17 | } 18 | 19 | ; CHECK: attributes #[[ATTR_GROUP]] = { 20 | ; CHECK: "CMStackCall" 21 | ; CHECK: } 22 | attributes #0 = { "VCStackCall" "VCFunction"} 23 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/no_kernels_module_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2022 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test general translation of attributes within module that has no kernels 10 | 11 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 12 | 13 | ; CHECK: @some_func 14 | ; CHECK: #[[ATTR_GROUP:[0-9]+]] 15 | 16 | define <16 x float> @some_func(<16 x float> %x) local_unnamed_addr #0 { 17 | ret <16 x float> %x 18 | } 19 | 20 | ; CHECK: attributes #[[ATTR_GROUP]] = { 21 | ; CHECK-DAG: "VCFunction" 22 | ; CHECK-DAG: "VCStackCall" 23 | ; CHECK: } 24 | attributes #0 = { "CMStackCall" } 25 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/no_vcfunction_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2022 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that reader ignores signature rewriting for kernels 10 | ; that are not VCFunction. 11 | 12 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | define spir_kernel void @test(i8 addrspace(1) *%ptr) { 15 | ; CHECK-LABEL: @test( 16 | 17 | ; CHECK-NEXT: entry: 18 | ; CHECK-NEXT: ret void 19 | entry: 20 | ret void 21 | } 22 | 23 | ; CHECK-NOT: !genx.kernels 24 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that reader treats only global pointer as svmptr type 10 | ; and ignores other address spaces. 11 | 12 | ; UNSUPPORTED: opaque-pointers 13 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 14 | 15 | define spir_kernel void @test(i32* %ptr) #0 { 16 | 17 | ; CHECK-LABEL: @test 18 | ; CHECK-SAME: (i32* [[PTR:%[^)]+]]) 19 | 20 | ; CHECK-NEXT: entry: 21 | ; CHECK-NEXT: ret void 22 | ; 23 | entry: 24 | ret void 25 | } 26 | 27 | attributes #0 = { "VCFunction" } 28 | 29 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 30 | ; CHECK: [[KERNEL]] = !{void (i32*)* @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, i32 0} 31 | ; CHECK: ![[KINDS]] = !{i32 0} 32 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test reader translation of old-style decorated arguments. 10 | ; Annotations for these are directly translated from attributes to 11 | ; kernel metadata without any checks. Required until full transition 12 | ; is done. 13 | 14 | ; UNSUPPORTED: opaque-pointers 15 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 16 | 17 | define spir_kernel void @test(i32 "VCArgumentDesc"="image2d_t read_only" "VCArgumentKind"="2" %in, i32 "VCArgumentDesc"="image2d_t write_only" "VCArgumentKind"="2" %out, <3 x i32> "VCArgumentKind"="24" %__arg_llvm.genx.local.id) #0 { 18 | ; CHECK-LABEL: @test 19 | 20 | ; CHECK-SAME: (i32 [[IN:%[^,]+]], i32 [[OUT:%[^,]+]], <3 x i32> [[LOCAL_ID:%[^)]+]]) 21 | 22 | ; CHECK-NEXT: entry: 23 | ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <3 x i32> [[LOCAL_ID]], i32 0 24 | ; CHECK-NEXT: [[CALL1_I_I_I:%.*]] = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 [[IN]], i32 0, i32 32, i32 [[TMP0]], i32 0) 25 | ; CHECK-NEXT: tail call void @llvm.genx.media.st.v8i32(i32 0, i32 [[OUT]], i32 0, i32 32, i32 [[TMP0]], i32 0, <8 x i32> [[CALL1_I_I_I]]) 26 | ; CHECK-NEXT: ret void 27 | ; 28 | entry: 29 | %0 = extractelement <3 x i32> %__arg_llvm.genx.local.id, i32 0 30 | %call1.i.i.i = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 %in, i32 0, i32 32, i32 %0, i32 0) 31 | tail call void @llvm.genx.media.st.v8i32(i32 0, i32 %out, i32 0, i32 32, i32 %0, i32 0, <8 x i32> %call1.i.i.i) 32 | ret void 33 | } 34 | 35 | declare <8 x i32> @llvm.genx.media.ld.v8i32(i32, i32, i32, i32, i32, i32) #0 36 | declare void @llvm.genx.media.st.v8i32(i32, i32, i32, i32, i32, i32, <8 x i32>) #0 37 | 38 | attributes #0 = { "VCFunction" } 39 | 40 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 41 | ; CHECK: [[KERNEL]] = !{{{.*}} @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 42 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 2, i32 24} 43 | ; CHECK-DAG: ![[DESCS]] = !{!"image2d_t read_only", !"image2d_t write_only", !""} 44 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/addr_conv_attribute_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test @llvm.genx.address.convert intrinsic generation with proper attributes 10 | 11 | ; REQUIRES: opaque-pointers 12 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: define spir_kernel void @test( 15 | ; CHECK-SAME: target("spirv.BufferSurfaceINTEL", 2) 16 | ; CHECK-NOT: "VCArgumentDesc" 17 | ; CHECK-NOT: "VCArgumentKind" 18 | ; CHECK-SAME: [[BUF:%[^)]+]]) 19 | define spir_kernel void @test(i32 %buf) { 20 | ; CHECK: call i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_2(target("spirv.BufferSurfaceINTEL", 2) [[BUF]]) 21 | ret void 22 | } 23 | 24 | ; CHECK-NOT: !genx.kernels 25 | !genx.kernels = !{!0} 26 | 27 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 28 | !1 = !{i32 2} 29 | !2 = !{i32 0} 30 | !3 = !{!"buffer_t"} 31 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/annot_mess_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test messy annnotations translation in writer. First valid 10 | ; annotation should be matched. 11 | 12 | ; REQUIRES: opaque-pointers 13 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 14 | 15 | ; CHECK: define spir_kernel void @test( 16 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) 17 | ; CHECK-NOT: "VCArgumentDesc" 18 | ; CHECK-NOT: "VCArgumentKind" 19 | ; CHECK-SAME: [[IM2D:%[^,]+]], 20 | ; CHECK-SAME: target("spirv.Sampler") 21 | ; CHECK-NOT: "VCArgumentDesc" 22 | ; CHECK-NOT: "VCArgumentKind" 23 | ; CHECK-SAME: [[SAMP:%[^,]+]], 24 | ; CHECK-SAME: ptr addrspace(1) 25 | ; CHECK-NOT: "VCArgumentDesc" 26 | ; CHECK-NOT: "VCArgumentKind" 27 | ; CHECK-SAME: [[PTR:%[^,]+]], 28 | ; CHECK-SAME: i32 29 | ; CHECK-NOT: "VCArgumentDesc" 30 | ; CHECK-NOT: "VCArgumentKind" 31 | ; CHECK-SAME: [[GEN:%[^)]+]]) 32 | define spir_kernel void @test(i32 %im2d, i32 %samp, i64 %ptr, i32 %gen) { 33 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_0(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) [[IM2D]]) 34 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.Sampler(target("spirv.Sampler") [[SAMP]]) 35 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[PTR]] to i64 36 | ; CHECK-NEXT: ret void 37 | ret void 38 | } 39 | 40 | ; CHECK-NOT: !genx.kernels 41 | !genx.kernels = !{!0} 42 | 43 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 44 | !1 = !{i32 2, i32 1, i32 0, i32 0} 45 | !2 = !{i32 0, i32 0, i32 0, i32 0} 46 | !3 = !{!"image2d_t buffer_t read_only read_write", !"sampler_t read_only", !"svmptr_t write_only", !"write_only"} 47 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/annotated_args_mixed_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that reader can cope with mixed mode when some 10 | ; arguments use address convert and some do not. 11 | 12 | ; REQUIRES: opaque-pointers 13 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 14 | 15 | ; CHECK: define dllexport spir_kernel void @test( 16 | ; CHECK-SAME: ptr addrspace(1) 17 | ; CHECK-SAME: [[BUF:%[^,]+]], 18 | ; CHECK-SAME: target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) 19 | ; CHECK-SAME: [[IM1D:%[^,]+]], 20 | ; CHECK-SAME: ptr addrspace(1) 21 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 22 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 2) 23 | ; CHECK-SAME: [[IM2D:%[^,]+]], 24 | ; CHECK-SAME: ptr addrspace(1) 25 | ; CHECK-SAME: [[IM3D:%[^,]+]], 26 | ; CHECK-SAME: target("spirv.Sampler") 27 | ; CHECK-SAME: [[SAMP:%[^,]+]], 28 | ; CHECK-SAME: ptr addrspace(1) 29 | ; CHECK-SAME: [[PTR:%[^,]+]], 30 | ; CHECK-SAME: <4 x i32> 31 | ; CHECK-SAME: [[GEN:%[^)]+]]) 32 | define spir_kernel void @test(target("spirv.BufferSurfaceINTEL", 2) %buf, target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) %im1d, target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 2) %im1db, target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 2) %im2d, target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 2) %im3d, target("spirv.Sampler") %samp, ptr addrspace(1) %ptr, <4 x i32> %gen) #0 { 33 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[BUF]] to i32 34 | %buf.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_2(target("spirv.BufferSurfaceINTEL", 2) %buf) 35 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[IM1DB]] to i32 36 | %im1db.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_5_0_0_0_0_0_2(target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 2) %im1db) 37 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[IM3D]] to i32 38 | %im3d.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_2_0_0_0_0_0_2(target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 2) %im3d) 39 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[PTR]] to i64 40 | %ptr.conv = ptrtoint ptr addrspace(1) %ptr to i64 41 | ; CHECK-NEXT: ret void 42 | ret void 43 | } 44 | 45 | declare i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_2(target("spirv.BufferSurfaceINTEL", 2)) 46 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_5_0_0_0_0_0_2(target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 2)) 47 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_2_0_0_0_0_0_2(target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 2)) 48 | 49 | attributes #0 = { "VCFunction" } 50 | 51 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 52 | ; CHECK: [[KERNEL]] = !{ptr @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 53 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 2, i32 2, i32 2, i32 2, i32 1, i32 0, i32 0} 54 | ; CHECK-DAG: ![[DESCS]] = !{!"buffer_t read_write", !"image1d_t read_write", !"image1d_buffer_t read_write", !"image2d_t read_write", !"image3d_t read_write", !"sampler_t", !"svmptr_t", !""} 55 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/annotated_args_no_conv_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that reader correctly restores metadata and does 10 | ; not change other things if there is no address conversion 11 | ; but correct SPIRV types in signature. 12 | 13 | ; REQUIRES: opaque-pointers 14 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: define dllexport spir_kernel void @test( 17 | ; CHECK-SAME: target("spirv.BufferSurfaceINTEL", 2) 18 | ; CHECK-SAME: [[BUF:%[^,]+]], 19 | ; CHECK-SAME: target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) 20 | ; CHECK-SAME: [[IM1D:%[^,]+]], 21 | ; CHECK-SAME: target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 2) 22 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 23 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 2) 24 | ; CHECK-SAME: [[IM2D:%[^,]+]], 25 | ; CHECK-SAME: target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 2) 26 | ; CHECK-SAME: [[IM3D:%[^,]+]], 27 | ; CHECK-SAME: target("spirv.Sampler") 28 | ; CHECK-SAME: [[SAMP:%[^,]+]], 29 | ; CHECK-SAME: ptr addrspace(1) 30 | ; CHECK-SAME: [[PTR:%[^,]+]], 31 | ; CHECK-SAME: <4 x i32> 32 | ; CHECK-SAME: [[GEN:%[^)]+]]) 33 | define spir_kernel void @test(target("spirv.BufferSurfaceINTEL", 2) %buf, target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) %im1d, target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 2) %im1db, target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 2) %im2d, target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 2) %im3d, target("spirv.Sampler") %samp, ptr addrspace(1) %ptr, <4 x i32> %gen) #0 { 34 | ; CHECK-NEXT: ret void 35 | ret void 36 | } 37 | 38 | attributes #0 = { "VCFunction" } 39 | 40 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 41 | ; CHECK: [[KERNEL]] = !{ptr @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 42 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 2, i32 2, i32 2, i32 2, i32 1, i32 0, i32 0} 43 | ; CHECK-DAG: ![[DESCS]] = !{!"buffer_t read_write", !"image1d_t read_write", !"image1d_buffer_t read_write", !"image2d_t read_write", !"image3d_t read_write", !"sampler_t", !"svmptr_t", !""} 44 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/annotated_args_no_conv_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that writer does not changes signature if correct 10 | ; types are already used. Just drop all annotations. 11 | 12 | ; REQUIRES: opaque-pointers 13 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 14 | 15 | ; CHECK: define spir_kernel void @test( 16 | ; CHECK-SAME: target("spirv.BufferSurfaceINTEL", 2) 17 | ; CHECK-NOT: "VCArgumentDesc" 18 | ; CHECK-NOT: "VCArgumentKind" 19 | ; CHECK-SAME: [[BUF:%[^,]+]], 20 | ; CHECK-SAME: target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) 21 | ; CHECK-NOT: "VCArgumentDesc" 22 | ; CHECK-NOT: "VCArgumentKind" 23 | ; CHECK-SAME: [[IM1D:%[^,]+]], 24 | ; CHECK-SAME: target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 2) 25 | ; CHECK-NOT: "VCArgumentDesc" 26 | ; CHECK-NOT: "VCArgumentKind" 27 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 28 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 2) 29 | ; CHECK-NOT: "VCArgumentDesc" 30 | ; CHECK-NOT: "VCArgumentKind" 31 | ; CHECK-SAME: [[IM2D:%[^,]+]], 32 | ; CHECK-SAME: target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 2) 33 | ; CHECK-NOT: "VCArgumentDesc" 34 | ; CHECK-NOT: "VCArgumentKind" 35 | ; CHECK-SAME: [[IM3D:%[^,]+]], 36 | ; CHECK-SAME: target("spirv.Sampler") 37 | ; CHECK-NOT: "VCArgumentDesc" 38 | ; CHECK-NOT: "VCArgumentKind" 39 | ; CHECK-SAME: [[SAMP:%[^,]+]], 40 | ; CHECK-SAME: ptr addrspace(1) 41 | ; CHECK-NOT: "VCArgumentDesc" 42 | ; CHECK-NOT: "VCArgumentKind" 43 | ; CHECK-SAME: [[PTR:%[^,]+]], 44 | ; CHECK-SAME: <4 x i32> 45 | ; CHECK-NOT: "VCArgumentDesc" 46 | ; CHECK-NOT: "VCArgumentKind" 47 | ; CHECK-SAME: [[GEN:%[^)]+]]) 48 | define spir_kernel void @test(target("spirv.BufferSurfaceINTEL", 2) %buf, target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) %im1d, target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 2) %im1db, target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 2) %im2d, target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 2) %im3d, target("spirv.Sampler") %samp, ptr addrspace(1) %ptr, <4 x i32> %gen) { 49 | ; CHECK-NEXT: ret void 50 | ret void 51 | } 52 | 53 | ; CHECK-NOT: !genx.kernels 54 | !genx.kernels = !{!0} 55 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 56 | !1 = !{i32 2, i32 2, i32 2, i32 2, i32 2, i32 1, i32 0, i32 0} 57 | !2 = !{i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0} 58 | !3 = !{!"buffer_t", !"image1d_t", !"image1d_buffer_t", !"image2d_t", !"image3d_t", !"sampler_t", !"svmptr_t", !""} 59 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/annotated_args_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel arguments translation from old style with metadata to 10 | ; new style with opaque types that SPIRV translator can 11 | ; understand. 12 | ; REQUIRES: opaque-pointers 13 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 14 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor,GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: define spir_kernel void @test( 17 | ; CHECK-SAME: target("spirv.BufferSurfaceINTEL", 2) 18 | ; CHECK-NOT: "VCArgumentDesc" 19 | ; CHECK-NOT: "VCArgumentKind" 20 | ; CHECK-SAME: [[BUF:%[^,]+]], 21 | ; CHECK-SAME: target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) 22 | ; CHECK-NOT: "VCArgumentDesc" 23 | ; CHECK-NOT: "VCArgumentKind" 24 | ; CHECK-SAME: [[IM1D:%[^,]+]], 25 | ; CHECK-SAME: target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 2) 26 | ; CHECK-NOT: "VCArgumentDesc" 27 | ; CHECK-NOT: "VCArgumentKind" 28 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 29 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 2) 30 | ; CHECK-NOT: "VCArgumentDesc" 31 | ; CHECK-NOT: "VCArgumentKind" 32 | ; CHECK-SAME: [[IM2D:%[^,]+]], 33 | ; CHECK-SAME: target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 2) 34 | ; CHECK-NOT: "VCArgumentDesc" 35 | ; CHECK-NOT: "VCArgumentKind" 36 | ; CHECK-SAME: [[IM3D:%[^,]+]], 37 | ; CHECK-SAME: target("spirv.Sampler") 38 | ; CHECK-NOT: "VCArgumentDesc" 39 | ; CHECK-NOT: "VCArgumentKind" 40 | ; CHECK-SAME: [[SAMP:%[^,]+]], 41 | ; CHECK-SAME: ptr addrspace(1) 42 | ; CHECK-NOT: "VCArgumentDesc" 43 | ; CHECK-NOT: "VCArgumentKind" 44 | ; CHECK-SAME: [[PTR:%[^,]+]], 45 | ; CHECK-SAME: <4 x i32> 46 | ; CHECK-NOT: "VCArgumentDesc" 47 | ; CHECK-NOT: "VCArgumentKind" 48 | ; CHECK-SAME: [[GEN:%[^)]+]]) 49 | define spir_kernel void @test(i32 %buf, i32 %im1d, i32 %im1db, i32 %im2d, i32 %im3d, i32 %samp, i64 %ptr, <4 x i32> %gen) { 50 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_2(target("spirv.BufferSurfaceINTEL", 2) [[BUF]]) 51 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_0_0_0_0_0_0_2(target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) [[IM1D]]) 52 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_5_0_0_0_0_0_2(target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 2) [[IM1DB]]) 53 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_2(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 2) [[IM2D]]) 54 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_2_0_0_0_0_0_2(target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 2) [[IM3D]]) 55 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.Sampler(target("spirv.Sampler") [[SAMP]]) 56 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[PTR]] to i64 57 | ; CHECK-NEXT: ret void 58 | ret void 59 | } 60 | 61 | ; CHECK-NOT: !genx.kernels 62 | !genx.kernels = !{!0} 63 | 64 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 65 | !1 = !{i32 2, i32 2, i32 2, i32 2, i32 2, i32 1, i32 0, i32 0} 66 | !2 = !{i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0} 67 | !3 = !{!"buffer_t", !"image1d_t", !"image1d_buffer_t", !"image2d_t", !"image3d_t", !"sampler_t", !"svmptr_t", !""} 68 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/args_attributes_transform_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that adaptor correctly handles parameter attributes with types. 10 | 11 | ; REQUIRES: opaque-pointers 12 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | %foo = type { i32 } 15 | 16 | ; CHECK: define dllexport spir_kernel void @test( 17 | ; CHECK-SAME: ptr addrspace(1) byval(%foo) 18 | ; CHECK-SAME: [[ARG:%[^)]+]]) 19 | define spir_kernel void @test(ptr addrspace(1) byval(%foo) %arg) #0 { 20 | ; CHECK-NEXT: ret void 21 | ret void 22 | } 23 | 24 | attributes #0 = { "VCFunction" } 25 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/args_attributes_transform_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that adaptor correctly handles parameter attributes with types. 10 | 11 | ; REQUIRES: opaque-pointers 12 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | %foo = type { i32 } 15 | 16 | ; CHECK: define spir_kernel void @test( 17 | ; CHECK-SAME: ptr addrspace(1) byval(%foo) 18 | ; CHECK-NOT: "VCArgumentDesc" 19 | ; CHECK-NOT: "VCArgumentKind" 20 | ; CHECK-SAME: [[ARG:%[^)]+]]) 21 | define spir_kernel void @test(ptr addrspace(1) byval(%foo) %arg) { 22 | ; CHECK-NEXT: ret void 23 | ret void 24 | } 25 | 26 | ; CHECK-NOT: !genx.kernels 27 | !genx.kernels = !{!0} 28 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0} 29 | !1 = !{i32 0} 30 | !2 = !{i32 0} 31 | !3 = !{!"svmptr_t"} 32 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/combined_args_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test combined reader translation: kernel has both native SPIRV types 10 | ; and impicit arguments. Implicit arguments would not show in normal 11 | ; flow, though they appear in old cmc. 12 | 13 | ; REQUIRES: opaque-pointers 14 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: define dllexport spir_kernel void @test( 17 | ; CHECK-SAME: ptr addrspace(1) 18 | ; CHECK-SAME: [[IN:%[^,]+]], 19 | ; CHECK-SAME: ptr addrspace(1) 20 | ; CHECK-SAME: [[OUT:%[^,]+]], 21 | ; CHECK-SAME: <3 x i32> 22 | ; CHECK-SAME: [[LOCAL_ID:%[^)]+]]) 23 | define spir_kernel void @test(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) %in, target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1) %out, <3 x i32> "VCArgumentKind"="24" %__arg_llvm.genx.local.id) #0 { 24 | ; CHECK-NEXT: [[IN_CONV:%.*]] = ptrtoint ptr addrspace(1) [[IN]] to i32 25 | %in.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_0(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) %in) 26 | ; CHECK-NEXT: [[OUT_CONV:%.*]] = ptrtoint ptr addrspace(1) [[OUT]] to i32 27 | %out.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_1(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1) %out) 28 | ; CHECK-NEXT: [[LOCAL_ID_0:%.*]] = extractelement <3 x i32> [[LOCAL_ID]], i32 0 29 | ; CHECK-NEXT: [[LD:%.*]] = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 [[IN_CONV]], i32 0, i32 32, i32 [[LOCAL_ID_0]], i32 0) 30 | ; CHECK-NEXT: tail call void @llvm.genx.media.st.v8i32(i32 0, i32 [[OUT_CONV]], i32 0, i32 32, i32 [[LOCAL_ID_0]], i32 0, <8 x i32> [[LD]]) 31 | %local.id.0 = extractelement <3 x i32> %__arg_llvm.genx.local.id, i32 0 32 | %ld = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 %in.conv, i32 0, i32 32, i32 %local.id.0, i32 0) 33 | tail call void @llvm.genx.media.st.v8i32(i32 0, i32 %out.conv, i32 0, i32 32, i32 %local.id.0, i32 0, <8 x i32> %ld) 34 | ; CHECK-NEXT: ret void 35 | ret void 36 | } 37 | 38 | declare <8 x i32> @llvm.genx.media.ld.v8i32(i32, i32, i32, i32, i32, i32) 39 | declare void @llvm.genx.media.st.v8i32(i32, i32, i32, i32, i32, i32, <8 x i32>) 40 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_0(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0)) 41 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_1(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1)) 42 | 43 | attributes #0 = { "VCFunction" } 44 | 45 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 46 | ; CHECK: [[KERNEL]] = !{ptr @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 47 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 2, i32 24} 48 | ; CHECK-DAG: ![[DESCS]] = !{!"image2d_t read_only", !"image2d_t write_only", !""} 49 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/combined_args_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test combined writer translation: kernel has both annotated explicit 10 | ; arguments and impicit arguments. Implicit arguments would not show 11 | ; in normal flow, though they appear in old cmc. 12 | ; REQUIRES: opaque-pointers 13 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 14 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor,GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: define spir_kernel void @test( 17 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) 18 | ; CHECK-NOT: "VCArgumentDesc" 19 | ; CHECK-NOT: "VCArgumentKind" 20 | ; CHECK-SAME: [[IN:%[^,]+]], 21 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1) 22 | ; CHECK-NOT: "VCArgumentDesc" 23 | ; CHECK-NOT: "VCArgumentKind" 24 | ; CHECK-SAME: [[OUT:%[^,]+]], 25 | ; CHECK-SAME: <3 x i32> 26 | ; CHECK-SAME: "VCArgumentKind"="24" 27 | ; CHECK-SAME: [[LOCAL_ID:%[^)]+]]) 28 | define spir_kernel void @test(i32 %in, i32 %out, <3 x i32> %__arg_llvm.genx.local.id) { 29 | ; CHECK: [[IN_CONV:%.*]] = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_0(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) [[IN]]) 30 | ; CHECK: [[OUT_CONV:%.*]] = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_1(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1) [[OUT]]) 31 | ; CHECK: [[LOCAL_ID_0:%.*]] = extractelement <3 x i32> [[LOCAL_ID]], i32 0 32 | ; CHECK-NEXT: [[LD:%.*]] = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 [[IN_CONV]], i32 0, i32 32, i32 [[LOCAL_ID_0]], i32 0) 33 | ; CHECK-NEXT: tail call void @llvm.genx.media.st.v8i32(i32 0, i32 [[OUT_CONV]], i32 0, i32 32, i32 [[LOCAL_ID_0]], i32 0, <8 x i32> [[LD]]) 34 | %local.id.0 = extractelement <3 x i32> %__arg_llvm.genx.local.id, i32 0 35 | %ld = tail call <8 x i32> @llvm.genx.media.ld.v8i32(i32 0, i32 %in, i32 0, i32 32, i32 %local.id.0, i32 0) 36 | tail call void @llvm.genx.media.st.v8i32(i32 0, i32 %out, i32 0, i32 32, i32 %local.id.0, i32 0, <8 x i32> %ld) 37 | ret void 38 | } 39 | 40 | declare <8 x i32> @llvm.genx.media.ld.v8i32(i32, i32, i32, i32, i32, i32) 41 | declare void @llvm.genx.media.st.v8i32(i32, i32, i32, i32, i32, i32, <8 x i32>) 42 | 43 | ; CHECK-NOT: !genx.kernels 44 | !genx.kernels = !{!0} 45 | 46 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 47 | !1 = !{i32 2, i32 2, i32 24} 48 | !2 = !{i32 0, i32 0} 49 | !3 = !{!"image2d_t read_only", !"image2d_t write_only"} 50 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/image_array_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test reader translation of image array arguments. 10 | 11 | ; REQUIRES: opaque-pointers 12 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: define dllexport spir_kernel void @test( 15 | ; CHECK-SAME: ptr addrspace(1) 16 | ; CHECK-SAME: [[IM1DARR:%[^,]+]], 17 | ; CHECK-SAME: ptr addrspace(1) 18 | ; CHECK-SAME: [[IM2DARR:%[^,]+]]) 19 | define spir_kernel void @test(target("spirv.Image", void, 0, 0, 1, 0, 0, 0, 0) %im1darr, target("spirv.Image", void, 1, 0, 1, 0, 0, 0, 1) %im2darr) #0 { 20 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[IM1DARR]] to i32 21 | %im1darr.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_0_0_1_0_0_0_0(target("spirv.Image", void, 0, 0, 1, 0, 0, 0, 0) %im1darr) 22 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[IM2DARR]] to i32 23 | %im2darr.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_1_0_0_0_1(target("spirv.Image", void, 1, 0, 1, 0, 0, 0, 1) %im2darr) 24 | ; CHECK-NEXT: ret void 25 | ret void 26 | } 27 | 28 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_0_0_1_0_0_0_0(target("spirv.Image", void, 0, 0, 1, 0, 0, 0, 0)) 29 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_1_0_0_0_1(target("spirv.Image", void, 1, 0, 1, 0, 0, 0, 1)) 30 | 31 | attributes #0 = { "VCFunction" } 32 | 33 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 34 | ; CHECK: [[KERNEL]] = !{ptr @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} 35 | ; CHECK-DAG: [[KINDS]] = !{i32 2, i32 2} 36 | ; CHECK-DAG: [[DESCS]] = !{!"image1d_array_t read_only", !"image2d_array_t write_only"} 37 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/image_array_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test writer translation of image array arguments. 10 | 11 | ; REQUIRES: opaque-pointers 12 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: define spir_kernel void @test( 15 | ; CHECK-SAME: target("spirv.Image", void, 0, 0, 1, 0, 0, 0, 0) 16 | ; CHECK-NOT: "VCArgumentDesc" 17 | ; CHECK-NOT: "VCArgumentKind" 18 | ; CHECK-SAME: [[IM1DARR:%[^,]+]], 19 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 1, 0, 0, 0, 1) 20 | ; CHECK-NOT: "VCArgumentDesc" 21 | ; CHECK-NOT: "VCArgumentKind" 22 | ; CHECK: [[IM2DARR:%[^)]+]]) 23 | define spir_kernel void @test(i32 %im1darr, i32 %im2darr) { 24 | ; CHECK: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_0_0_1_0_0_0_0(target("spirv.Image", void, 0, 0, 1, 0, 0, 0, 0) [[IM1DARR]]) 25 | ; CHECK: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_1_0_0_0_1(target("spirv.Image", void, 1, 0, 1, 0, 0, 0, 1) [[IM2DARR]]) 26 | ret void 27 | } 28 | 29 | ; CHECK-NOT: !genx.kernels 30 | !genx.kernels = !{!0} 31 | 32 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 33 | !1 = !{i32 2, i32 2} 34 | !2 = !{i32 0, i32 0} 35 | !3 = !{!"image1d_array_t read_only", !"image2d_array_t write_only"} 36 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/media_block_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test reader translation of media block image arguments. 10 | 11 | ; REQUIRES: opaque-pointers 12 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: define dllexport spir_kernel void @test( 15 | ; CHECK-SAME: ptr addrspace(1) 16 | ; CHECK-NOT: "VCMediaBlockIO" 17 | ; CHECK-SAME: [[IMAGE:%[^)]+]]) 18 | define spir_kernel void @test(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) "VCMediaBlockIO" %image) #0 { 19 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[IMAGE]] to i32 20 | %image.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_0(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) %image) 21 | ; CHECK-NEXT: ret void 22 | ret void 23 | } 24 | 25 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_0(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0)) 26 | 27 | attributes #0 = { "VCFunction" } 28 | 29 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 30 | ; CHECK: [[KERNEL]] = !{ptr @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} 31 | ; CHECK-DAG: [[KINDS]] = !{i32 2} 32 | ; CHECK-DAG: [[DESCS]] = !{!"image2d_media_block_t read_only"} 33 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/media_block_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test writer translation of media block images arguments. 10 | 11 | ; REQUIRES: opaque-pointers 12 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: define spir_kernel void @test( 15 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) 16 | ; CHECK-SAME: "VCMediaBlockIO" 17 | ; CHECK-NOT: "VCArgumentDesc" 18 | ; CHECK-NOT: "VCArgumentKind" 19 | ; CHECK-SAME: [[IMAGE:%[^)]+]]) 20 | define spir_kernel void @test(i32 %image) { 21 | ; CHECK: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_0(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) [[IMAGE]]) 22 | ret void 23 | } 24 | 25 | ; CHECK-NOT: !genx.kernels 26 | !genx.kernels = !{!0} 27 | 28 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 29 | !1 = !{i32 2} 30 | !2 = !{i32 0} 31 | !3 = !{!"image2d_media_block_t read_only"} 32 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/non_global_ptr_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test that reader treats only global pointer as svmptr type 10 | ; and ignores other address spaces. 11 | 12 | ; REQUIRES: opaque-pointers 13 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 14 | 15 | ; CHECK: define dllexport spir_kernel void @test( 16 | ; CHECK-SAME: ptr [[PTR:%[^)]+]]) 17 | define spir_kernel void @test(ptr %ptr) #0 { 18 | ; CHECK-NEXT: ret void 19 | ret void 20 | } 21 | 22 | attributes #0 = { "VCFunction" } 23 | 24 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 25 | ; CHECK: [[KERNEL]] = !{ptr @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, i32 0} 26 | ; CHECK: ![[KINDS]] = !{i32 0} 27 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/plain_args_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel argument translation from new style with opaque types 10 | ; that SPIRV translator can understand to old style with 11 | ; metadata. Arguments without annotations are used here (CMRT like). 12 | 13 | ; REQUIRES: opaque-pointers 14 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: define dllexport spir_kernel void @test( 17 | ; CHECK-SAME: ptr addrspace(1) 18 | ; CHECK-SAME: [[SURF:%[^,]+]], 19 | ; CHECK-SAME: ptr addrspace(2) 20 | ; CHECK-SAME: [[SAMP:%[^,]+]], 21 | ; CHECK-SAME: i64 22 | ; CHECK-SAME: [[PTR:%[^,]+]], 23 | ; CHECK-SAME: i32 24 | ; CHECK-SAME: [[GEN:%[^)]+]]) 25 | define spir_kernel void @test(target("spirv.BufferSurfaceINTEL", 2) %surf, target("spirv.Sampler") %samp, i64 %ptr, i32 %gen) #0 { 26 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[SURF]] to i32 27 | %surf.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_2(target("spirv.BufferSurfaceINTEL", 2) %surf) 28 | ; CHECK-NEXT: ptrtoint ptr addrspace(2) [[SAMP]] to i32 29 | %samp.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Sampler(target("spirv.Sampler") %samp) 30 | ; CHECK-NEXT: ret void 31 | ret void 32 | } 33 | 34 | declare i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_2(target("spirv.BufferSurfaceINTEL", 2)) 35 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Sampler(target("spirv.Sampler")) 36 | 37 | attributes #0 = { "VCFunction" } 38 | 39 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 40 | ; CHECK: [[KERNEL]] = !{ptr @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 41 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 1, i32 0, i32 0} 42 | ; CHECK-DAG: ![[DESCS]] = !{!"buffer_t read_write", !"sampler_t", !"", !""} 43 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/plain_args_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel arguments translation from old style with metadata to 10 | ; new style with opaque types that SPIRV translator can 11 | ; understand. Arguments without annotations are used here (CMRT like). 12 | ; REQUIRES: opaque-pointers 13 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 14 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor,GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: define spir_kernel void @test( 17 | ; CHECK-SAME: target("spirv.BufferSurfaceINTEL", 2) 18 | ; CHECK-NOT: "VCArgumentDesc" 19 | ; CHECK-NOT: "VCArgumentKind" 20 | ; CHECK-SAME: [[SURF:%[^,]+]], 21 | ; CHECK-SAME: target("spirv.Sampler") 22 | ; CHECK-NOT: "VCArgumentDesc" 23 | ; CHECK-NOT: "VCArgumentKind" 24 | ; CHECK-SAME: [[SAMP:%[^,]+]], 25 | ; CHECK-SAME: i64 26 | ; CHECK-NOT: "VCArgumentDesc" 27 | ; CHECK-NOT: "VCArgumentKind" 28 | ; CHECK-SAME: [[PTR:%[^,]+]], 29 | ; CHECK-SAME: i32 30 | ; CHECK-NOT: "VCArgumentDesc" 31 | ; CHECK-NOT: "VCArgumentKind" 32 | ; CHECK-SAME: [[GEN:%[^)]+]]) 33 | define spir_kernel void @test(i32 %surf, i32 %samp, i64 %ptr, i32 %gen) { 34 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_2(target("spirv.BufferSurfaceINTEL", 2) [[SURF]]) 35 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.t_spirv.Sampler(target("spirv.Sampler") [[SAMP]]) 36 | ; CHECK-NEXT: ret void 37 | ret void 38 | } 39 | 40 | ; CHECK-NOT: !genx.kernels 41 | !genx.kernels = !{!0} 42 | 43 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0} 44 | !1 = !{i32 2, i32 1, i32 0, i32 0} 45 | !2 = !{i32 0, i32 0, i32 0, i32 0} 46 | !3 = !{!"", !"", !"", !""} 47 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/sev_ptr_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; REQUIRES: opaque-pointers 10 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 11 | 12 | define internal "VCSingleElementVector"="1" ptr @foo(ptr "VCSingleElementVector"="2" %in, ptr "VCSingleElementVector"="3" %out) #0 { 13 | ; CHECK: store ptr %in, ptr %out, align 8 14 | ; CHECK-NEXT: ret ptr %out 15 | store ptr %in, ptr %out, align 8 16 | ret ptr %out 17 | } 18 | 19 | define internal "VCSingleElementVector"="0" ptr @bar(ptr "VCSingleElementVector"="0" %in, ptr "VCSingleElementVector"="0" %out) #0 { 20 | ; CHECK: [[EX:[^ ]+]] = extractelement <1 x ptr> %out, i64 0 21 | ; CHECK-NEXT: [[INS:[^ ]+]] = extractelement <1 x ptr> %in, i64 0 22 | ; CHECK-NEXT: store ptr [[INS]], ptr [[EX]], align 8 23 | ; CHECK-NEXT: ret <1 x ptr> %out 24 | store ptr %in, ptr %out, align 8 25 | ret ptr %out 26 | } 27 | 28 | attributes #0 = { "VCFunction" } 29 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/sev_ptr_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; REQUIRES: opaque-pointers 10 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 11 | 12 | define internal void @foo(<1 x ptr> %v) { 13 | ; CHECK: %ld = load i32, ptr %v, align 4 14 | %ex = extractelement <1 x ptr> %v, i64 0 15 | %ld = load i32, ptr %ex, align 4 16 | ret void 17 | } 18 | 19 | define internal <1 x ptr> @bar(<1 x ptr> %in, <1 x ptr> %out) { 20 | ; CHECK: store ptr %in, ptr %out, align 8 21 | ; CHECK-NEXT: ret ptr %out 22 | %ex = extractelement <1 x ptr> %out, i64 0 23 | store <1 x ptr> %in, ptr %ex, align 8 24 | ret <1 x ptr> %out 25 | } 26 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/sev_signature_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test simple signatures tranform 10 | 11 | ; REQUIRES: opaque-pointers 12 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: @global1 = internal global <1 x i32> undef, align 4 15 | ; CHECK: @global2 = internal global <1 x ptr> undef, align 4 16 | ; CHECK: @global3 = external global <1 x ptr> 17 | ; CHECK: @global4 = external global ptr 18 | @global1 = internal global i32 undef, align 4 #1 19 | @global2 = internal global ptr undef, align 4 #1 20 | @global3 = external global ptr #1 21 | @global4 = external global ptr #2 22 | 23 | ; CHECK: define <1 x i32> @f1(<1 x i32> %a, <1 x i32> %b) 24 | define "VCSingleElementVector"="0" i32 @f1(i32 "VCSingleElementVector" %a, i32 "VCSingleElementVector" %b) #0 { 25 | ; CHECK: call void @llvm.genx.intr(ptr @global1) 26 | ; CHECK: call void @llvm.genx.intr(ptr @global2) 27 | ; CHECK: call void @llvm.genx.intr(ptr @global3) 28 | call void @llvm.genx.intr(ptr @global1) 29 | call void @llvm.genx.intr(ptr @global2) 30 | call void @llvm.genx.intr(ptr @global3) 31 | ; CHECK: store i32 0, ptr @global1, align 4 32 | ; CHECK: store ptr @global1, ptr @global2, align 8 33 | ; CHECK: store ptr @global2, ptr @global3, align 8 34 | store i32 0, ptr @global1, align 4 35 | store ptr @global1, ptr @global2, align 8 36 | store ptr @global2, ptr @global3, align 8 37 | ; CHECK: ret <1 x i32> %a 38 | ret i32 %a 39 | } 40 | 41 | ; CHECK: define i32 @f2(<1 x i32> %a, <1 x i32> %b) 42 | define i32 @f2(i32 "VCSingleElementVector"="0" %a, i32 "VCSingleElementVector"="0" %b) #0 { 43 | ; CHECK: [[EX:[^ ]+]] = extractelement <1 x i32> %a, i64 0 44 | ; CHECK: ret i32 [[EX]] 45 | ret i32 %a 46 | } 47 | 48 | ; CHECK: define i32 @f3(i32 %a, <1 x i32> %b) 49 | define i32 @f3(i32 %a, i32 "VCSingleElementVector"="0" %b) #0 { 50 | ret i32 %a 51 | } 52 | 53 | declare void @llvm.genx.intr(ptr) 54 | 55 | attributes #0 = { "VCFunction" } 56 | attributes #1 = { "VCGlobalVariable" "VCSingleElementVector"="0" } 57 | attributes #2 = { "VCGlobalVariable" "VCSingleElementVector"="1" } 58 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/sev_signature_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test simple signatures tranform 10 | 11 | ; REQUIRES: opaque-pointers 12 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: @global1 = internal global i32 undef, align 4 15 | ; CHECK: @global2 = internal global ptr undef, align 4 16 | ; CHECK: @global3 = external global ptr 17 | @global1 = internal global <1 x i32> undef, align 4 #0 18 | @global2 = internal global <1 x ptr> undef, align 4 #0 19 | @global3 = external global <1 x ptr> #0 20 | 21 | ; CHECK: define "VCSingleElementVector"="0" i32 @f1(i32 "VCSingleElementVector"="0" %a, i32 "VCSingleElementVector"="0" %b) 22 | define <1 x i32> @f1(<1 x i32> %a, <1 x i32> %b) { 23 | ; CHECK: call void @llvm.genx.intr(ptr @global1) 24 | ; CHECK: call void @llvm.genx.intr(ptr @global2) 25 | ; CHECK: call void @llvm.genx.intr(ptr @global3) 26 | call void @llvm.genx.intr(ptr @global1) 27 | call void @llvm.genx.intr(ptr @global2) 28 | call void @llvm.genx.intr(ptr @global3) 29 | ; CHECK: store i32 0, ptr @global1, align 4 30 | ; CHECK: store ptr @global1, ptr @global2, align 8 31 | ; CHECK: store ptr @global2, ptr @global3, align 8 32 | store <1 x i32> zeroinitializer, ptr @global1, align 4 33 | %v1 = insertelement <1 x ptr> undef, ptr @global1, i64 0 34 | store <1 x ptr> %v1, ptr @global2, align 8 35 | %v2 = insertelement <1 x ptr> undef, ptr @global2, i64 0 36 | store <1 x ptr> %v2, ptr @global3, align 8 37 | ; CHECK: ret i32 %a 38 | ret <1 x i32> %a 39 | } 40 | 41 | ; CHECK: define i32 @f2(i32 "VCSingleElementVector"="0" %a, i32 "VCSingleElementVector"="0" %b) 42 | define i32 @f2(<1 x i32> %a, <1 x i32> %b) { 43 | ; CHECK ret i32 %a 44 | %c = extractelement <1 x i32> %a, i64 0 45 | ret i32 %c 46 | } 47 | 48 | ; CHECK: define i32 @f3(i32 %a, i32 "VCSingleElementVector"="0" %b) 49 | define i32 @f3(i32 %a, <1 x i32> %b) { 50 | ret i32 %a 51 | } 52 | 53 | declare void @llvm.genx.intr(ptr) 54 | 55 | ; CHECK: "VCSingleElementVector"="0" 56 | attributes #0 = { "VCGlobalVariable" } 57 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/sev_struct.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; REQUIRES: opaque-pointers 10 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 11 | 12 | target datalayout = "e-p:64:64-i64:64-n8:16:32" 13 | target triple = "spir64" 14 | 15 | ; CHECK: [[STRUCT1:[^ ]+]] = type { i32, <2 x i32>, [[STRUCT2:[^ ]+]] } 16 | %struct.sev_test = type { <1 x i32>, <2 x i32>, %struct.sev_test_nested } 17 | ; CHECK: [[STRUCT2]] = type { ptr, ptr, ptr } 18 | %struct.sev_test_nested = type { ptr, ptr, ptr } 19 | 20 | ; CHECK: define void @test(i32 "VCSingleElementVector"="0" %sev, ptr %ptr) 21 | define void @test(<1 x i32> %sev, ptr %ptr) { 22 | ; CHECK: %1 = alloca [[STRUCT1]], align 8 23 | %1 = alloca %struct.sev_test, align 8 24 | ; CHECK: %2 = getelementptr inbounds [[STRUCT1]], ptr %1, i32 0, i32 0 25 | %2 = getelementptr inbounds %struct.sev_test, ptr %1, i32 0, i32 0 26 | ; CHECK: store i32 %sev, ptr %2, align 4 27 | store <1 x i32> %sev, ptr %2, align 4 28 | ; CHECK: %3 = getelementptr inbounds [[STRUCT1]], ptr %1, i32 0, i32 2 29 | %3 = getelementptr inbounds %struct.sev_test, ptr %1, i32 0, i32 2 30 | ; CHECK: %4 = getelementptr inbounds [[STRUCT2]], ptr %3, i32 0, i32 0 31 | %4 = getelementptr inbounds %struct.sev_test_nested, ptr %3, i32 0, i32 0 32 | ; CHECK: store ptr %ptr, ptr %4, align 8 33 | store ptr %ptr, ptr %4, align 8 34 | ; CHECK: %5 = getelementptr inbounds [[STRUCT2]], ptr %3, i32 0, i32 2 35 | %5 = getelementptr inbounds %struct.sev_test_nested, ptr %3, i32 0, i32 2 36 | ; CHECK: store ptr %1, ptr %5, align 8 37 | store ptr %1, ptr %5, align 8 38 | ret void 39 | } 40 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/surface_access_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel surface argument translation from new style with opaque 10 | ; types that SPIRV translator can understand to old style with 11 | ; metadata. This test checks access qualifiers translation. 12 | 13 | ; REQUIRES: opaque-pointers 14 | ; RUN: opt -passes=GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: define dllexport spir_kernel void @test( 17 | ; CHECK-SAME: ptr addrspace(1) 18 | ; CHECK-SAME: [[BUF:%[^,]+]], 19 | ; CHECK-SAME: ptr addrspace(1) 20 | ; CHECK-SAME: [[IM1D:%[^,]+]], 21 | ; CHECK-SAME: ptr addrspace(1) 22 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 23 | ; CHECK-SAME: ptr addrspace(1) 24 | ; CHECK-SAME: [[IM2D:%[^,]+]], 25 | ; CHECK-SAME: ptr addrspace(1) 26 | ; CHECK-SAME: [[IM3D:%[^)]+]]) 27 | define dllexport spir_kernel void @test(target("spirv.BufferSurfaceINTEL", 0) %buf, target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) %im1d, target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 1) %im1db, target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1) %im2d, target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0) %im3d) #0 { 28 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[BUF]] to i32 29 | %buf.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_0(target("spirv.BufferSurfaceINTEL", 0) %buf) 30 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[IM1D]] to i32 31 | %im1d.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_0_0_0_0_0_0_2(target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) %im1d) 32 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[IM1DB]] to i32 33 | %im1db.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_5_0_0_0_0_0_1(target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 1) %im1db) 34 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[IM2D]] to i32 35 | %im2d.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_1(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1) %im2d) 36 | ; CHECK-NEXT: ptrtoint ptr addrspace(1) [[IM3D]] to i32 37 | %im3d.conv = call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_2_0_0_0_0_0_0(target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0) %im3d) 38 | ; CHECK-NEXT: ret void 39 | ret void 40 | } 41 | 42 | declare i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_0(target("spirv.BufferSurfaceINTEL", 0)) 43 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_0_0_0_0_0_0_2(target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2)) 44 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_5_0_0_0_0_0_1(target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 1)) 45 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_1(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1)) 46 | declare i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_2_0_0_0_0_0_0(target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0)) 47 | 48 | attributes #0 = { "VCFunction" } 49 | 50 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 51 | ; CHECK: [[KERNEL]] = !{ptr @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 52 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 2, i32 2, i32 2, i32 2} 53 | ; CHECK-DAG: ![[DESCS]] = !{!"buffer_t read_only", !"image1d_t read_write", !"image1d_buffer_t write_only", !"image2d_t write_only", !"image3d_t read_only"} 54 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/opaque_ptrs/surface_access_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel surface argument translation from old style with 10 | ; metadata to new style with opaque types that SPIRV translator can 11 | ; understand. This test checks access qualifiers translation. 12 | 13 | ; REQUIRES: opaque-pointers 14 | ; RUN: opt -passes=GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: define spir_kernel void @test( 17 | ; CHECK-SAME: target("spirv.BufferSurfaceINTEL", 0) 18 | ; CHECK-NOT: "VCArgumentDesc" 19 | ; CHECK-NOT: "VCArgumentKind" 20 | ; CHECK-SAME: [[BUF:%[^,]+]], 21 | ; CHECK-SAME: target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) 22 | ; CHECK-NOT: "VCArgumentDesc" 23 | ; CHECK-NOT: "VCArgumentKind" 24 | ; CHECK-SAME: [[IM1D:%[^,]+]], 25 | ; CHECK-SAME: target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 1) 26 | ; CHECK-NOT: "VCArgumentDesc" 27 | ; CHECK-NOT: "VCArgumentKind" 28 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 29 | ; CHECK-SAME: target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1) 30 | ; CHECK-NOT: "VCArgumentDesc" 31 | ; CHECK-NOT: "VCArgumentKind" 32 | ; CHECK-SAME: [[IM2D:%[^,]+]], 33 | ; CHECK-SAME: target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0) 34 | ; CHECK-NOT: "VCArgumentDesc" 35 | ; CHECK-NOT: "VCArgumentKind" 36 | ; CHECK: [[IM3D:%[^)]+]]) 37 | define spir_kernel void @test(i32 %buf, i32 %im1d, i32 %im1db, i32 %im2d, i32 %im3d) { 38 | ; CHECK: call i32 @llvm.genx.address.convert.i32.t_spirv.BufferSurfaceINTEL_0(target("spirv.BufferSurfaceINTEL", 0) [[BUF]]) 39 | ; CHECK: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_0_0_0_0_0_0_2(target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 2) [[IM1D]]) 40 | ; CHECK: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_5_0_0_0_0_0_1(target("spirv.Image", void, 5, 0, 0, 0, 0, 0, 1) [[IM1DB]]) 41 | ; CHECK: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_1_0_0_0_0_0_1(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 1) [[IM2D]]) 42 | ; CHECK: call i32 @llvm.genx.address.convert.i32.t_spirv.Image_isVoid_2_0_0_0_0_0_0(target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0) [[IM3D]]) 43 | ret void 44 | } 45 | 46 | ; CHECK-NOT: !genx.kernels 47 | !genx.kernels = !{!0} 48 | 49 | !0 = !{ptr @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 50 | !1 = !{i32 2, i32 2, i32 2, i32 2, i32 2} 51 | !2 = !{i32 0, i32 0, i32 0, i32 0, i32 0} 52 | !3 = !{!"buffer_t read_only", !"image1d_t read_write", !"image1d_buffer_t write_only", !"image2d_t write_only", !"image3d_t read_only"} 53 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/plain_args_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel argument translation from new style with opaque types 10 | ; that SPIRV translator can understand to old style with 11 | ; metadata. Arguments without annotations are used here (CMRT like). 12 | 13 | ; UNSUPPORTED: opaque-pointers 14 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 15 | 16 | %intel.buffer_rw_t = type opaque 17 | %opencl.sampler_t = type opaque 18 | 19 | ; CHECK: define dllexport spir_kernel void @test( 20 | ; CHECK-SAME: %intel.buffer_rw_t addrspace(1)* 21 | ; CHECK-SAME: [[BUF:%[^,]+]], 22 | ; CHECK-SAME: %opencl.sampler_t addrspace(2)* 23 | ; CHECK-SAME: [[SAMP:%[^,]+]], 24 | ; CHECK-SAME: i64 25 | ; CHECK-SAME: [[PTR:%[^,]+]], 26 | ; CHECK-SAME: i32 27 | ; CHECK-SAME: [[GEN:%[^)]+]]) 28 | define spir_kernel void @test(%intel.buffer_rw_t addrspace(1)* %buf, %opencl.sampler_t addrspace(2)* %samp, i64 %ptr, i32 %gen) #0 { 29 | ; CHECK-NEXT: ptrtoint %intel.buffer_rw_t addrspace(1)* [[BUF]] to i32 30 | %buf.conv = call i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)* %buf) 31 | ; CHECK-NEXT: ptrtoint %opencl.sampler_t addrspace(2)* [[SAMP]] to i32 32 | %samp.conv = call i32 @llvm.genx.address.convert.i32.p2opencl.sampler_t(%opencl.sampler_t addrspace(2)* %samp) 33 | ; CHECK-NEXT: ret void 34 | ret void 35 | } 36 | 37 | declare i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)*) #0 38 | declare i32 @llvm.genx.address.convert.i32.p2opencl.sampler_t(%opencl.sampler_t addrspace(2)*) #0 39 | 40 | attributes #0 = { "VCFunction" } 41 | 42 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 43 | ; CHECK: [[KERNEL]] = !{void (%intel.buffer_rw_t addrspace(1)*, %opencl.sampler_t addrspace(2)*, i64, i32)* @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 44 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 1, i32 0, i32 0} 45 | ; CHECK-DAG: ![[DESCS]] = !{!"buffer_t read_write", !"sampler_t", !"", !""} 46 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/plain_args_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel arguments translation from old style with metadata to 10 | ; new style with opaque types that SPIRV translator can 11 | ; understand. Arguments without annotations are used here (CMRT like). 12 | 13 | ; UNSUPPORTED: opaque-pointers 14 | ; XFAIL: llvm13, llvm14 15 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 16 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 17 | 18 | ; CHECK: define spir_kernel void @test( 19 | ; CHECK-SAME: %intel.buffer_rw_t addrspace(1)* 20 | ; CHECK-NOT: "VCArgumentDesc" 21 | ; CHECK-NOT: "VCArgumentKind" 22 | ; CHECK-SAME: [[BUF:%[^,]+]], 23 | ; CHECK: %opencl.sampler_t addrspace(2)* 24 | ; CHECK-NOT: "VCArgumentDesc" 25 | ; CHECK-NOT: "VCArgumentKind" 26 | ; CHECK-SAME: [[SAMP:%[^,]+]], 27 | ; CHECK-SAME: i64 28 | ; CHECK-NOT: "VCArgumentDesc" 29 | ; CHECK-NOT: "VCArgumentKind" 30 | ; CHECK-SAME: [[PTR:%[^,]+]], 31 | ; CHECK-SAME: i32 32 | ; CHECK-NOT: "VCArgumentDesc" 33 | ; CHECK-NOT: "VCArgumentKind" 34 | ; CHECK-SAME: [[GEN:%[^)]+]]) 35 | define spir_kernel void @test(i32 %buf, i32 %samp, i64 %ptr, i32 %gen) { 36 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1intel.buffer_rw_t(%intel.buffer_rw_t addrspace(1)* [[BUF]]) 37 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p2opencl.sampler_t(%opencl.sampler_t addrspace(2)* [[SAMP]]) 38 | ; CHECK-NEXT: ret void 39 | ret void 40 | } 41 | 42 | ; CHECK-NOT: !genx.kernels 43 | !genx.kernels = !{!0} 44 | 45 | !0 = !{void (i32, i32, i64, i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0} 46 | !1 = !{i32 2, i32 1, i32 0, i32 0} 47 | !2 = !{i32 0, i32 0, i32 0, i32 0} 48 | !3 = !{!"", !"", !"", !""} 49 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2022-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test GenXSingleElementVectorUtil preserves calling convention 10 | ; (spir_func here) 11 | 12 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | ; ModuleID = 'start.ll' 15 | source_filename = "start.ll" 16 | target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024" 17 | target triple = "spir64-unknown-unknown" 18 | 19 | ; Function Attrs: noinline nounwind 20 | ; CHECK: define internal spir_func void @bar(<1 x i32> %a) #0 { 21 | define internal spir_func void @bar(i32 "VCSingleElementVector"="0" %a) #0 { 22 | ret void 23 | } 24 | 25 | ; Function Attrs: noinline nounwind 26 | define spir_kernel void @foo() #1 !intel_reqd_sub_group_size !0 { 27 | ; CHECK: call spir_func void @bar(<1 x i32> undef) 28 | call spir_func void @bar(i32 undef) 29 | ret void 30 | } 31 | 32 | attributes #0 = { noinline nounwind "VCFunction" } 33 | attributes #1 = { noinline nounwind "VCFunction" "VCNamedBarrierCount"="0" "VCSLMSize"="0" } 34 | 35 | !0 = !{i32 1} 36 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2022-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test GenXSingleElementVectorUtil preserves calling convention 10 | ; (spir_func here) 11 | 12 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | ; ModuleID = 'sev_calling_conv_reader.ll' 15 | source_filename = "start.ll" 16 | target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024" 17 | target triple = "spir64-unknown-unknown" 18 | 19 | ; Function Attrs: noinline nounwind 20 | ; CHECK: define internal spir_func void @bar(i32 "VCSingleElementVector"="0" %a) #0 21 | define internal spir_func void @bar(<1 x i32> %a) #0 { 22 | ret void 23 | } 24 | 25 | ; Function Attrs: noinline nounwind 26 | define dllexport spir_kernel void @foo() #1 !intel_reqd_sub_group_size !0 { 27 | ; CHECK: call spir_func void @bar(i32 undef) 28 | call spir_func void @bar(<1 x i32> undef) 29 | ret void 30 | } 31 | 32 | attributes #0 = { noinline nounwind } 33 | attributes #1 = { noinline nounwind "CMGenxMain" "oclrt"="1" } 34 | 35 | !0 = !{i32 1} 36 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/sev_ptr_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2023-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; UNSUPPORTED: opaque-pointers 10 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 11 | 12 | define internal void @foo(i32** "VCSingleElementVector"="1" %v) #0 { 13 | entry: 14 | ; CHECK: [[SEV:[^ ]+]] = bitcast <1 x i32*>* %v to i32** 15 | ; CHECK: %ld.v = load i32*, i32** [[SEV]], align 8 16 | ; CHECK: %ld.ex = load i32, i32* %ld.v, align 4 17 | %ld.v = load i32*, i32** %v, align 8 18 | %ld.ex = load i32, i32* %ld.v, align 4 19 | ret void 20 | } 21 | 22 | define internal "VCSingleElementVector"="2" i64*** @bar(i64** "VCSingleElementVector"="2" %in, i64*** "VCSingleElementVector"="2" %out) #0 { 23 | entry: 24 | ; CHECK: [[SEV:[^ ]+]] = bitcast <1 x i64**>* %out to i64*** 25 | ; CHECK: [[SEVIN:[^ ]+]] = extractelement <1 x i64**> %in, i64 0 26 | ; CHECK: store i64** [[SEVIN]], i64*** [[SEV]], align 8 27 | store i64** %in, i64*** %out, align 8 28 | ; CHECK: ret <1 x i64**>* %out 29 | ret i64*** %out 30 | } 31 | 32 | attributes #0 = { "VCFunction" } 33 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/sev_ptr_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2023-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; UNSUPPORTED: opaque-pointers 10 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 11 | 12 | define internal void @foo(<1 x i32*>* %v) #0 { 13 | entry: 14 | ; CHECK: %ld.v = load i32*, i32** %v, align 8 15 | ; CHECK: %ld.ex = load i32, i32* %ld.v, align 4 16 | %ld.v = load <1 x i32*>, <1 x i32*>* %v, align 8 17 | %ex = extractelement <1 x i32*> %ld.v, i32 0 18 | %ld.ex = load i32, i32* %ex, align 4 19 | ret void 20 | } 21 | 22 | define internal <1 x i64**>* @bar(<1 x i64**> %in, <1 x i64**>* %out) #0 { 23 | entry: 24 | ; CHECK: store i64** %in, i64*** %out, align 8 25 | store <1 x i64**> %in, <1 x i64**>* %out, align 8 26 | ret <1 x i64**>* %out 27 | } 28 | 29 | attributes #0 = { "VCFunction" } 30 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/sev_signature_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test simple signatures tranform 10 | 11 | ; UNSUPPORTED: opaque-pointers 12 | ; LLVM16 error: symbol with local linkage cannot have a DLL storage class 13 | ; for test-function (internal dllexport) 14 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: @global_var_0 = internal global <1 x i32> undef, align 4 17 | @global_var_0 = internal global i32 undef, align 4 #2 18 | 19 | ; CHECK: @global_var_1 = internal global <1 x i32**> undef, align 4 20 | @global_var_1 = internal global i32** undef, align 4 #3 21 | 22 | ; CHECK: @global_var_2 = external global <1 x i32**> 23 | @global_var_2 = external global i32** #3 24 | 25 | ; CHECK: @global_var_3 = internal global i32** undef, align 4 26 | @global_var_3 = internal global i32** undef, align 4 27 | 28 | ; CHECK: <1 x i32> @some.func.1(<1 x i32> %a, <1 x i32> %b) 29 | define internal "VCSingleElementVector" i32 @some.func.1(i32 "VCSingleElementVector" %a, i32 "VCSingleElementVector" %b) local_unnamed_addr #0 { 30 | entry: 31 | 32 | ; CHECK: call void @llvm.genx.some.intr.0(<1 x i32>* @global_var_0) 33 | call void @llvm.genx.some.intr.0(i32* @global_var_0) 34 | 35 | ; CHECK: call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_1) 36 | call void @llvm.genx.some.intr.1(i32*** @global_var_1) 37 | 38 | ; CHECK: call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_2) 39 | call void @llvm.genx.some.intr.1(i32*** @global_var_2) 40 | 41 | ret i32 %a 42 | } 43 | 44 | ; CHECK: i32 @some.func.2(<1 x i32> %a, <1 x i32> %b) 45 | define internal i32 @some.func.2(i32 "VCSingleElementVector"="0" %a, i32 "VCSingleElementVector"="0" %b) local_unnamed_addr #0 { 46 | entry: 47 | ret i32 %a 48 | } 49 | 50 | ; CHECK: i32 @some.func.3(i32 %a, <1 x i32> %b) 51 | define internal i32 @some.func.3(i32 %a, i32 "VCSingleElementVector"="0" %b) local_unnamed_addr #0 { 52 | entry: 53 | ret i32 %a 54 | } 55 | 56 | ; CHECK: i32 @some.func.4(<1 x i32***> %a, <1 x i32>*** %b, <1 x i32*>** %c) 57 | define internal i32 @some.func.4(i32*** "VCSingleElementVector"="3" %a, i32*** "VCSingleElementVector"="0" %b, i32*** "VCSingleElementVector"="1" %c) local_unnamed_addr #0 { 58 | entry: 59 | ret i32 0 60 | } 61 | 62 | define dllexport spir_kernel void @test() #1 { 63 | entry: 64 | ret void 65 | } 66 | 67 | declare void @llvm.genx.some.intr.0(i32* "VCSingleElementVector") 68 | declare void @llvm.genx.some.intr.1(i32*** "VCSingleElementVector"="2") 69 | 70 | attributes #0 = { "VCFunction" } 71 | attributes #1 = { "VCFunction" "VCSLMSize"="0" } 72 | attributes #2 = { "VCGlobalVariable" "VCSingleElementVector"="0" } 73 | attributes #3 = { "VCGlobalVariable" "VCSingleElementVector"="2" } 74 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/sev_signature_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test simple signatures tranform 10 | 11 | ; UNSUPPORTED: opaque-pointers 12 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: @global_var_0 = internal global i32 undef, align 4 15 | @global_var_0 = internal global <1 x i32> undef, align 4 #0 16 | 17 | ; CHECK: @global_var_1 = internal global i32** undef, align 4 18 | @global_var_1 = internal global <1 x i32**> undef, align 4 #0 19 | 20 | ; CHECK: @global_var_2 = external global i32** 21 | @global_var_2 = external global <1 x i32**> #0 22 | 23 | ; CHECK: "VCSingleElementVector"="0" i32 @some.func.1(i32 "VCSingleElementVector"="0" %a, i32 "VCSingleElementVector"="0" %b) 24 | define dso_local <1 x i32> @some.func.1(<1 x i32> %a, <1 x i32> %b) local_unnamed_addr { 25 | entry: 26 | 27 | ; CHECK: call void @llvm.genx.some.intr.0(i32* @global_var_0) 28 | call void @llvm.genx.some.intr.0(<1 x i32>* @global_var_0) 29 | 30 | ; CHECK: call void @llvm.genx.some.intr.1(i32*** @global_var_1) 31 | call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_1) 32 | 33 | ; CHECK: call void @llvm.genx.some.intr.1(i32*** @global_var_2) 34 | call void @llvm.genx.some.intr.1(<1 x i32**>* @global_var_2) 35 | 36 | ret <1 x i32> %a 37 | } 38 | 39 | ; CHECK: i32 @some.func.2(i32 "VCSingleElementVector"="0" %a, i32 "VCSingleElementVector"="0" %b) 40 | define dso_local i32 @some.func.2(<1 x i32> %a, <1 x i32> %b) local_unnamed_addr { 41 | entry: 42 | ; CHECK-NOT: extractelement 43 | %c = extractelement <1 x i32> %a, i32 0 44 | ret i32 %c 45 | } 46 | 47 | ; CHECK: i32 @some.func.3(i32 %a, i32 "VCSingleElementVector"="0" %b) 48 | define dso_local i32 @some.func.3(i32 %a, <1 x i32> %b) local_unnamed_addr { 49 | entry: 50 | ret i32 %a 51 | } 52 | 53 | ; CHECK: i32 @some.func.4(i32*** "VCSingleElementVector"="3" %a, i32*** "VCSingleElementVector"="0" %b, i32*** "VCSingleElementVector"="1" %c) 54 | define dso_local i32 @some.func.4(<1 x i32***> %a, <1 x i32>*** %b, <1 x i32*>** %c) local_unnamed_addr { 55 | entry: 56 | ret i32 0 57 | } 58 | 59 | 60 | define spir_kernel void @test() { 61 | entry: 62 | ret void 63 | } 64 | 65 | declare void @llvm.genx.some.intr.0(<1 x i32>*) 66 | declare void @llvm.genx.some.intr.1(<1 x i32**>*) 67 | 68 | ; CHECK: "VCSingleElementVector"="0" 69 | ; CHECK: "VCSingleElementVector"="2" 70 | attributes #0 = { "VCGlobalVariable" } 71 | 72 | !genx.kernels = !{!0} 73 | 74 | !0 = !{void ()* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0} 75 | !1 = !{} 76 | !2 = !{} 77 | !3 = !{} 78 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/sev_struct.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2023-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; UNSUPPORTED: opaque-pointers 10 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 11 | 12 | target datalayout = "e-p:64:64-i64:64-n8:16:32" 13 | target triple = "spir64" 14 | 15 | ; CHECK: [[STRUCT1:[^ ]+]] = type { i32, <2 x i32>, [[STRUCT2:[^ ]+]] } 16 | %struct.sev_test = type { <1 x i32>, <2 x i32>, %struct.sev_test_nested } 17 | ; CHECK: [[STRUCT2]] = type { i32*, <2 x i32>*, [[STRUCT1]]* } 18 | %struct.sev_test_nested = type { <1 x i32>*, <2 x i32>*, %struct.sev_test* } 19 | 20 | ; CHECK: define void @test(i32 "VCSingleElementVector"="0" %sev, i32* "VCSingleElementVector"="0" %sev_ptr) 21 | define void @test(<1 x i32> %sev, <1 x i32>* %sev_ptr) { 22 | ; CHECK: %1 = alloca [[STRUCT1]], align 8 23 | %1 = alloca %struct.sev_test, align 8 24 | ; CHECK: %2 = getelementptr inbounds [[STRUCT1]], [[STRUCT1]]* %1, i32 0, i32 0 25 | %2 = getelementptr inbounds %struct.sev_test, %struct.sev_test* %1, i32 0, i32 0 26 | ; CHECK: store i32 %sev, i32* %2, align 4 27 | store <1 x i32> %sev, <1 x i32>* %2, align 4 28 | ; CHECK: %3 = getelementptr inbounds [[STRUCT1]], [[STRUCT1]]* %1, i32 0, i32 2 29 | %3 = getelementptr inbounds %struct.sev_test, %struct.sev_test* %1, i32 0, i32 2 30 | ; CHECK: %4 = getelementptr inbounds [[STRUCT2]], [[STRUCT2]]* %3, i32 0, i32 0 31 | %4 = getelementptr inbounds %struct.sev_test_nested, %struct.sev_test_nested* %3, i32 0, i32 0 32 | ; CHECK: store i32* %sev_ptr, i32** %4, align 8 33 | store <1 x i32>* %sev_ptr, <1 x i32>** %4, align 8 34 | ; CHECK: %5 = getelementptr inbounds [[STRUCT2]], [[STRUCT2]]* %3, i32 0, i32 2 35 | %5 = getelementptr inbounds %struct.sev_test_nested, %struct.sev_test_nested* %3, i32 0, i32 2 36 | ; CHECK: store [[STRUCT1]]* %1, [[STRUCT1]]** %5, align 8 37 | store %struct.sev_test* %1, %struct.sev_test** %5, align 8 38 | ret void 39 | } 40 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test reader translation of SPIRV friendly IR types 10 | 11 | ; UNSUPPORTED: opaque-pointers 12 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | %spirv.Sampler = type opaque 15 | %spirv.Image._void_0_0_1_0_0_0_0 = type opaque 16 | %spirv.Image._void_1_0_1_0_0_0_1 = type opaque 17 | %spirv.Image._void_2_0_0_0_0_0_2 = type opaque 18 | 19 | ; CHECK: define dllexport spir_kernel void @test( 20 | ; CHECK-SAME: %spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)* 21 | ; CHECK-SAME: [[IM1D:%[^,]+]], 22 | ; CHECK-SAME: %spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)* 23 | ; CHECK-SAME: [[IM2D:%[^,]+]], 24 | ; CHECK-SAME: %spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)* 25 | ; CHECK-SAME: [[IM3D:%[^,]+]], 26 | ; CHECK-SAME: %spirv.Sampler addrspace(2)* 27 | ; CHECK-SAME: [[SAMP:%[^,]+]]) 28 | define spir_kernel void @test(%spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)* %im1d, %spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)* %im2d, %spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)* %im3d, %spirv.Sampler addrspace(2)* %samp) #0 { 29 | ; CHECK-NEXT: ptrtoint %spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)* [[IM1D]] to i32 30 | %im1d.conv = call i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_0_0_1_0_0_0_0(%spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)* %im1d) 31 | ; CHECK-NEXT: ptrtoint %spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)* [[IM2D]] to i32 32 | %im2d.conv = call i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_1_0_1_0_0_0_1(%spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)* %im2d) 33 | ; CHECK-NEXT: ptrtoint %spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)* [[IM3D]] to i32 34 | %im3d.conv = call i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_2_0_0_0_0_0_2(%spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)* %im3d) 35 | ; CHECK-NEXT: ptrtoint %spirv.Sampler addrspace(2)* [[SAMP]] to i32 36 | %samp.conv = call i32 @llvm.genx.address.convert.i32.p2spirv.Sampler(%spirv.Sampler addrspace(2)* %samp) 37 | ; CHECK-NEXT: ret void 38 | ret void 39 | } 40 | 41 | declare i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_0_0_1_0_0_0_0(%spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)*) #0 42 | declare i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_1_0_1_0_0_0_1(%spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)*) #0 43 | declare i32 @llvm.genx.address.convert.i32.p1spirv.Image._void_2_0_0_0_0_0_2(%spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)*) #0 44 | declare i32 @llvm.genx.address.convert.i32.p2spirv.Sampler(%spirv.Sampler addrspace(2)*) #0 45 | 46 | attributes #0 = { "VCFunction" } 47 | 48 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 49 | ; CHECK: [[KERNEL]] = !{void (%spirv.Image._void_0_0_1_0_0_0_0 addrspace(1)*, %spirv.Image._void_1_0_1_0_0_0_1 addrspace(1)*, %spirv.Image._void_2_0_0_0_0_0_2 addrspace(1)*, %spirv.Sampler addrspace(2)*)* @test, !"test", [[KINDS:![0-9]+]], i32 0, i32 0, !{{[0-9]+}}, [[DESCS:![0-9]+]], i32 0} 50 | ; CHECK-DAG: [[KINDS]] = !{i32 2, i32 2, i32 2, i32 1} 51 | ; CHECK-DAG: [[DESCS]] = !{!"image1d_array_t read_only", !"image2d_array_t write_only", !"image3d_t read_write", !"sampler_t"} 52 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/surface_access_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel surface argument translation from new style with opaque 10 | ; types that SPIRV translator can understand to old style with 11 | ; metadata. This test checks access qualifiers translation. 12 | 13 | ; UNSUPPORTED: opaque-pointers 14 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 15 | 16 | %intel.buffer_ro_t = type opaque 17 | %opencl.image1d_rw_t = type opaque 18 | %opencl.image1d_buffer_wo_t = type opaque 19 | %opencl.image2d_wo_t = type opaque 20 | %opencl.image3d_ro_t = type opaque 21 | 22 | ; CHECK: define dllexport spir_kernel void @test( 23 | ; CHECK-SAME: %intel.buffer_ro_t addrspace(1)* 24 | ; CHECK-SAME: [[BUF:%[^,]+]], 25 | ; CHECK-SAME: %opencl.image1d_rw_t addrspace(1)* 26 | ; CHECK-SAME: [[IM1D:%[^,]+]], 27 | ; CHECK-SAME: %opencl.image1d_buffer_wo_t addrspace(1)* 28 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 29 | ; CHECK-SAME: %opencl.image2d_wo_t addrspace(1)* 30 | ; CHECK-SAME: [[IM2D:%[^,]+]], 31 | ; CHECK-SAME: %opencl.image3d_ro_t addrspace(1)* 32 | ; CHECK-SAME: [[IM3D:%[^,]+]]) 33 | define spir_kernel void @test(%intel.buffer_ro_t addrspace(1)* %buf, %opencl.image1d_rw_t addrspace(1)* %im1d, %opencl.image1d_buffer_wo_t addrspace(1)* %im1db, %opencl.image2d_wo_t addrspace(1)* %im2d, %opencl.image3d_ro_t addrspace(1)* %im3d) #0 { 34 | ; CHECK-NEXT: ptrtoint %intel.buffer_ro_t addrspace(1)* [[BUF]] to i32 35 | %buf.conv = call i32 @llvm.genx.address.convert.i32.p1intel.buffer_ro_t(%intel.buffer_ro_t addrspace(1)* %buf) 36 | ; CHECK-NEXT: ptrtoint %opencl.image1d_rw_t addrspace(1)* [[IM1D]] to i32 37 | %im1d.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_rw_t(%opencl.image1d_rw_t addrspace(1)* %im1d) 38 | ; CHECK-NEXT: ptrtoint %opencl.image1d_buffer_wo_t addrspace(1)* [[IM1DB]] to i32 39 | %im1db.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_buffer_wo_t(%opencl.image1d_buffer_wo_t addrspace(1)* %im1db) 40 | ; CHECK-NEXT: ptrtoint %opencl.image2d_wo_t addrspace(1)* [[IM2D]] to i32 41 | %im2d.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_wo_t(%opencl.image2d_wo_t addrspace(1)* %im2d) 42 | ; CHECK-NEXT: ptrtoint %opencl.image3d_ro_t addrspace(1)* [[IM3D]] to i32 43 | %im3d.conv = call i32 @llvm.genx.address.convert.i32.p1opencl.image3d_ro_t(%opencl.image3d_ro_t addrspace(1)* %im3d) 44 | ; CHECK-NEXT: ret void 45 | ret void 46 | } 47 | 48 | declare i32 @llvm.genx.address.convert.i32.p1intel.buffer_ro_t(%intel.buffer_ro_t addrspace(1)*) #0 49 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image1d_rw_t(%opencl.image1d_rw_t addrspace(1)*) #0 50 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image1d_buffer_wo_t(%opencl.image1d_buffer_wo_t addrspace(1)*) #0 51 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image2d_wo_t(%opencl.image2d_wo_t addrspace(1)*) #0 52 | declare i32 @llvm.genx.address.convert.i32.p1opencl.image3d_ro_t(%opencl.image3d_ro_t addrspace(1)*) #0 53 | 54 | attributes #0 = { "VCFunction" } 55 | 56 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 57 | ; CHECK: [[KERNEL]] = !{void (%intel.buffer_ro_t addrspace(1)*, %opencl.image1d_rw_t addrspace(1)*, %opencl.image1d_buffer_wo_t addrspace(1)*, %opencl.image2d_wo_t addrspace(1)*, %opencl.image3d_ro_t addrspace(1)*)* @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, ![[DESCS:[0-9]+]], i32 0} 58 | ; CHECK-DAG: ![[KINDS]] = !{i32 2, i32 2, i32 2, i32 2, i32 2} 59 | ; CHECK-DAG: ![[DESCS]] = !{!"buffer_t read_only", !"image1d_t read_write", !"image1d_buffer_t write_only", !"image2d_t write_only", !"image3d_t read_only"} 60 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/surface_access_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test kernel surface argument translation from old style with 10 | ; metadata to new style with opaque types that SPIRV translator can 11 | ; understand. This test checks access qualifiers translation. 12 | 13 | ; UNSUPPORTED: opaque-pointers 14 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 15 | 16 | ; CHECK: define spir_kernel void @test( 17 | ; CHECK-SAME: %intel.buffer_ro_t addrspace(1)* 18 | ; CHECK-NOT: "VCArgumentDesc" 19 | ; CHECK-NOT: "VCArgumentKind" 20 | ; CHECK-SAME: [[BUF:%[^,]+]], 21 | ; CHECK-SAME: %opencl.image1d_rw_t addrspace(1)* 22 | ; CHECK-NOT: "VCArgumentDesc" 23 | ; CHECK-NOT: "VCArgumentKind" 24 | ; CHECK-SAME: [[IM1D:%[^,]+]], 25 | ; CHECK-SAME: %opencl.image1d_buffer_wo_t addrspace(1)* 26 | ; CHECK-NOT: "VCArgumentDesc" 27 | ; CHECK-NOT: "VCArgumentKind" 28 | ; CHECK-SAME: [[IM1DB:%[^,]+]], 29 | ; CHECK-SAME: %opencl.image2d_wo_t addrspace(1)* 30 | ; CHECK-NOT: "VCArgumentDesc" 31 | ; CHECK-NOT: "VCArgumentKind" 32 | ; CHECK-SAME: [[IM2D:%[^,]+]], 33 | ; CHECK-SAME: %opencl.image3d_ro_t addrspace(1)* 34 | ; CHECK-NOT: "VCArgumentDesc" 35 | ; CHECK-NOT: "VCArgumentKind" 36 | ; CHECK-SAME: [[IM3D:%[^)]+]]) 37 | define void @test(i32 %buf, i32 %im1d, i32 %im1db, i32 %im2d, i32 %im3d) { 38 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1intel.buffer_ro_t(%intel.buffer_ro_t addrspace(1)* [[BUF]]) 39 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_rw_t(%opencl.image1d_rw_t addrspace(1)* [[IM1D]]) 40 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image1d_buffer_wo_t(%opencl.image1d_buffer_wo_t addrspace(1)* [[IM1DB]]) 41 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image2d_wo_t(%opencl.image2d_wo_t addrspace(1)* [[IM2D]]) 42 | ; CHECK-NEXT: call i32 @llvm.genx.address.convert.i32.p1opencl.image3d_ro_t(%opencl.image3d_ro_t addrspace(1)* [[IM3D]]) 43 | ; CHECK-NEXT: ret void 44 | ret void 45 | } 46 | 47 | ; CHECK-NOT: !genx.kernels 48 | !genx.kernels = !{!0} 49 | 50 | !0 = !{void (i32, i32, i32, i32, i32)* @test, !"test", !1, i32 0, i32 0, !2, !3, i32 0, i32 0} 51 | !1 = !{i32 2, i32 2, i32 2, i32 2, i32 2} 52 | !2 = !{i32 0, i32 0, i32 0, i32 0, i32 0} 53 | !3 = !{!"buffer_t read_only", !"image1d_t read_write", !"image1d_buffer_t write_only", !"image2d_t write_only", !"image3d_t read_only"} 54 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test reader translation of implicit argument with argument kind 10 | ; decoration. 11 | 12 | ; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s 13 | 14 | define spir_kernel void @test(<3 x i32> "VCArgumentKind"="24" %__arg_llvm.genx.local.id) #0 { 15 | 16 | ; CHECK-LABEL: @test 17 | ; CHECK-SAME: (<3 x i32> [[LOCAL_ID:%[^)]+]]) 18 | 19 | ; CHECK-NEXT: entry: 20 | ; CHECK-NEXT: ret void 21 | ; 22 | entry: 23 | ret void 24 | } 25 | 26 | attributes #0 = { "VCFunction" } 27 | 28 | ; CHECK: !genx.kernels = !{[[KERNEL:![0-9]+]]} 29 | ; CHECK: [[KERNEL]] = !{{{.*}} @test, !"test", ![[KINDS:[0-9]+]], i32 0, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, i32 0} 30 | ; CHECK: ![[KINDS]] = !{i32 24} 31 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Adaptors/unknown_arg_writer.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2025 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; Test writer translation of implicit argument. Implicit arguments 10 | ; should not appear in current form after transition from cmc. 11 | 12 | ; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s 13 | 14 | ; CHECK: define spir_kernel void @test( 15 | ; CHECK-SAME: <3 x i32> 16 | ; CHECK-SAME: "VCArgumentKind"="24" 17 | ; CHECK-SAME: [[LOCAL_ID:%[^)]+]]) 18 | define void @test(<3 x i32> %__arg_llvm.genx.local.id) { 19 | ; CHECK-NEXT: ret void 20 | ret void 21 | } 22 | 23 | ; CHECK-NOT: !genx.kernels 24 | !genx.kernels = !{!0} 25 | 26 | !0 = !{void (<3 x i32>)* @test, !"test", !1, i32 0, i32 0, !2, !2, i32 0, i32 0} 27 | !1 = !{i32 24} 28 | !2 = !{} 29 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2020-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | if(BUILD_EXTERNAL) 10 | if(NOT EXISTS ${LLVM_EXTERNAL_LIT}) 11 | message(FATAL_ERROR "External build requires LLVM_EXTERNAL_LIT to be defined to lit executable") 12 | endif() 13 | endif() 14 | 15 | # Add plugin with all intrinsics libraries for loading with opt. 16 | add_subdirectory(Plugin) 17 | 18 | set(VC_INTRINSICS_TEST_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) 19 | 20 | # Generate temporary site config with LLVM variables filled. 21 | configure_lit_site_cfg( 22 | ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.py.in 23 | ${CMAKE_CURRENT_BINARY_DIR}/temp.cfg.py 24 | MAIN_CONFIG 25 | ${CMAKE_CURRENT_SOURCE_DIR}/lit.cfg.py 26 | ) 27 | 28 | # Need to regenerate again since plugin name is required and proper 29 | # way to get it is to use generator expressions that are not allowed 30 | # in configure_file. 31 | file(GENERATE 32 | OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/vcint.$.lit.site.cfg.py" 33 | INPUT "${CMAKE_CURRENT_BINARY_DIR}/temp.cfg.py" 34 | ) 35 | 36 | set(USED_TOOLS 37 | # These are required by lit default substitutions. 38 | FileCheck 39 | count 40 | not 41 | # Main tool for plugin testing. 42 | opt 43 | ) 44 | 45 | if(NOT BUILD_EXTERNAL) 46 | set(TEST_DEPS 47 | ${USED_TOOLS} 48 | ) 49 | else() 50 | # Check for tools availability. 51 | foreach(tool ${USED_TOOLS}) 52 | set(TOOL_PATH "${LLVM_TOOLS_BINARY_DIR}/${tool}") 53 | if(NOT EXISTS ${TOOL_PATH}) 54 | message(FATAL_ERROR "Tool ${tool} is not found (required by lit tests)") 55 | endif() 56 | endforeach() 57 | endif() 58 | 59 | # Add testsuite with custom config name that depends on generator. 60 | add_lit_testsuite(check-vc-intrinsics "Running the vc-intrinsics regression tests" 61 | ${CMAKE_CURRENT_BINARY_DIR} 62 | ARGS 63 | "--config-prefix=vcint.$.lit" 64 | "-sv" 65 | DEPENDS 66 | ${TEST_DEPS} 67 | VCIntrinsicsPlugin 68 | ) 69 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Plugin/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2020-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | set(PLUGIN_SOURCES 10 | Plugin.cpp 11 | ) 12 | 13 | add_library(VCIntrinsicsPlugin 14 | MODULE 15 | ${PLUGIN_SOURCES} 16 | ) 17 | 18 | set(LINK_LIBS 19 | LLVMGenXIntrinsics 20 | ) 21 | 22 | target_link_libraries(VCIntrinsicsPlugin 23 | ${LINK_LIBS} 24 | ) 25 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/Plugin/Plugin.cpp: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2020-2022 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #include "llvm/GenXIntrinsics/GenXSimdCFLowering.h" 10 | #include "llvm/GenXIntrinsics/GenXSPIRVReaderAdaptor.h" 11 | #include "llvm/GenXIntrinsics/GenXSPIRVWriterAdaptor.h" 12 | 13 | #include "llvm/PassRegistry.h" 14 | #include "llvm/Passes/PassBuilder.h" 15 | #include "llvm/Passes/PassPlugin.h" 16 | 17 | using namespace llvm; 18 | 19 | //----------------------------------------------------------------------------- 20 | // New PM support 21 | //----------------------------------------------------------------------------- 22 | // Add callback to create plugin pass to pass builder. 23 | // PassArgs - arguments for pass construction, passed by value to avoid 24 | // dangling references in callbacks. 25 | template 26 | static void registerModulePass(PassBuilder &PB, ArgsT... PassArgs) { 27 | auto Reg = [PassArgs...](StringRef Name, ModulePassManager &MPM, 28 | ArrayRef) { 29 | if (Name != PassT::getArgString()) 30 | return false; 31 | MPM.addPass(PassT{PassArgs...}); 32 | return true; 33 | }; 34 | PB.registerPipelineParsingCallback(Reg); 35 | } 36 | 37 | static void registerPasses(PassBuilder &PB) { 38 | registerModulePass(PB); 39 | registerModulePass( 40 | PB, /*RewriteTypes=*/true, /*RewriteSingleElementVectors=*/true); 41 | registerModulePass(PB); 42 | } 43 | 44 | static PassPluginLibraryInfo getIntrinsicsPluginInfo() { 45 | return {LLVM_PLUGIN_API_VERSION, "VC intrinsics plugin", "v1", 46 | registerPasses}; 47 | } 48 | 49 | // Entry point for plugin in new PM infrastructure. 50 | extern "C" ::llvm::PassPluginLibraryInfo LLVM_ATTRIBUTE_WEAK 51 | llvmGetPassPluginInfo() { 52 | return getIntrinsicsPluginInfo(); 53 | } 54 | 55 | //----------------------------------------------------------------------------- 56 | // Legacy PM support 57 | //----------------------------------------------------------------------------- 58 | // Register intrinsics passes on dynamic loading of plugin library. 59 | static int initializePasses() { 60 | PassRegistry &PR = *PassRegistry::getPassRegistry(); 61 | 62 | initializeCMSimdCFLoweringLegacyPass(PR); 63 | initializeGenXSPIRVReaderAdaptorLegacyPass(PR); 64 | initializeGenXSPIRVWriterAdaptorLegacyPass(PR); 65 | 66 | return 0; 67 | } 68 | 69 | static const int Init = initializePasses(); 70 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; UNSUPPORTED: opaque-pointers 10 | ; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | @Rcp_T2 = internal global <64 x double> undef 13 | 14 | ; CHECK: @EM = internal global <32 x i1> 15 | 16 | define dso_local dllexport void @test1(<32 x i16> %mask, <64 x i32> %oldval) { 17 | entry: 18 | %Rcp_T = alloca <64 x double>, align 512 19 | %0 = icmp ne <32 x i16> %mask, zeroinitializer 20 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %0) 21 | br i1 %call, label %if.then, label %if.end 22 | 23 | if.then: 24 | ; CHECK: if.then: 25 | ; CHECK-NEXT: [[EM_LOAD:%.*]] = load <32 x i1>, <32 x i1>* @EM 26 | ; CHECK-NEXT: [[PRED_WRR:%.*]] = call <64 x i32> @llvm.genx.wrregioni.v64i32.v32i32.i16.v32i1(<64 x i32> %oldval, <32 x i32> zeroinitializer, i32 0, i32 32, i32 2, i16 0, i32 undef, <32 x i1> [[EM_LOAD]]) 27 | ; CHECK-NEXT: [[PRED_WRR_CAST:%.*]] = bitcast <64 x i32> [[PRED_WRR]] to <32 x double> 28 | %wrregion26 = call <64 x i32> @llvm.genx.wrregioni.v64i32.v32i32.i16.i1(<64 x i32> %oldval, <32 x i32> zeroinitializer, i32 0, i32 32, i32 2, i16 0, i32 undef, i1 true) 29 | %cast27 = bitcast <64 x i32> %wrregion26 to <32 x double> 30 | 31 | %Rcp_T2_load = load <64 x double>, <64 x double>* %Rcp_T 32 | %wrregion28 = call <64 x double> @llvm.genx.wrregionf.v64f64.v32f64.i16.i1(<64 x double> %Rcp_T2_load, <32 x double> %cast27, i32 0, i32 32, i32 1, i16 0, i32 32, i1 true) 33 | store <64 x double> %wrregion28, <64 x double>* %Rcp_T 34 | br label %if.end 35 | 36 | if.end: 37 | %1 = load <64 x double>, <64 x double>* %Rcp_T 38 | store <64 x double> %1, <64 x double>* @Rcp_T2 39 | ret void 40 | } 41 | 42 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 43 | declare <64 x i32> @llvm.genx.wrregioni.v64i32.v32i32.i16.i1(<64 x i32>, <32 x i32>, i32, i32, i32, i16, i32, i1) 44 | declare <64 x double> @llvm.genx.wrregionf.v64f64.v32f64.i16.i1(<64 x double>, <32 x double>, i32, i32, i32, i16, i32, i1) 45 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/opaque_ptrs/bitcast_between_wrrs.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; REQUIRES: opaque-pointers 10 | ; RUN: opt -passes=cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | @Rcp_T2 = internal global <64 x double> undef 13 | 14 | ; CHECK: @EM = internal global <32 x i1> 15 | 16 | define dso_local dllexport void @test1(<32 x i16> %mask, <64 x i32> %oldval) { 17 | %Rcp_T = alloca <64 x double>, align 512 18 | %cmp = icmp ne <32 x i16> %mask, zeroinitializer 19 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %cmp) 20 | br i1 %call, label %if.then, label %if.end 21 | 22 | ; CHECK-LABEL: if.then: 23 | if.then: 24 | ; CHECK: [[EM_LOAD:%.*]] = load <32 x i1>, ptr @EM 25 | ; CHECK-NEXT: [[PRED_WRR:%.*]] = call <64 x i32> @llvm.genx.wrregioni.v64i32.v32i32.i16.v32i1(<64 x i32> %oldval, <32 x i32> zeroinitializer, i32 0, i32 32, i32 2, i16 0, i32 undef, <32 x i1> [[EM_LOAD]]) 26 | ; CHECK-NEXT: [[PRED_WRR_CAST:%.*]] = bitcast <64 x i32> [[PRED_WRR]] to <32 x double> 27 | %wrregion26 = call <64 x i32> @llvm.genx.wrregioni.v64i32.v32i32.i16.i1(<64 x i32> %oldval, <32 x i32> zeroinitializer, i32 0, i32 32, i32 2, i16 0, i32 undef, i1 true) 28 | %cast27 = bitcast <64 x i32> %wrregion26 to <32 x double> 29 | %Rcp_T2_load = load <64 x double>, ptr %Rcp_T 30 | %wrregion28 = call <64 x double> @llvm.genx.wrregionf.v64f64.v32f64.i16.i1(<64 x double> %Rcp_T2_load, <32 x double> %cast27, i32 0, i32 32, i32 1, i16 0, i32 32, i1 true) 31 | store <64 x double> %wrregion28, ptr %Rcp_T 32 | br label %if.end 33 | 34 | if.end: 35 | %ld = load <64 x double>, ptr %Rcp_T 36 | store <64 x double> %ld, ptr @Rcp_T2 37 | ret void 38 | } 39 | 40 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 41 | declare <64 x i32> @llvm.genx.wrregioni.v64i32.v32i32.i16.i1(<64 x i32>, <32 x i32>, i32, i32, i32, i16, i32, i1) 42 | declare <64 x double> @llvm.genx.wrregionf.v64f64.v32f64.i16.i1(<64 x double>, <32 x double>, i32, i32, i32, i16, i32, i1) 43 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/opaque_ptrs/predicate_masked_gather.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; REQUIRES: opaque-pointers 10 | ; RUN: opt -passes=cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | ; CHECK: @EM = internal global <32 x i1> 13 | 14 | @g2 = internal global <32 x i32> undef 15 | 16 | define dso_local dllexport void @test_gather(<32 x i16> %mask, <32 x i32> %addrs) { 17 | %g = alloca <32 x i32>, align 512 18 | %cmp = icmp ne <32 x i16> %mask, zeroinitializer 19 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %cmp) 20 | br i1 %call, label %if.then, label %if.end 21 | 22 | ; CHECK-LABEL: if.then: 23 | if.then: 24 | ; CHECK: [[EM_LOAD1:%.*]] = load <32 x i1>, ptr @EM 25 | ; CHECK-NEXT: [[CALL1:%.*]] = call <32 x i32> @llvm.genx.gather.masked.scaled2.v32i32.v32i32.v32i1(i32 2, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> [[EM_LOAD1]]) 26 | %call1 = call <32 x i32> @llvm.genx.gather.masked.scaled2.v32i32.v32i32.v32i1(i32 2, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> ) 27 | ; CHECK: [[EM_LOAD2:%.*]] = load <32 x i1>, ptr @EM 28 | ; CHECK-NEXT: [[CALL1_SIMDCFPREDL:%.*]] = select <32 x i1> [[EM_LOAD2:%.*]], <32 x i32> [[CALL1:%.*]] 29 | store <32 x i32> %call1, ptr %g 30 | br label %if.end 31 | 32 | if.end: 33 | %ld = load <32 x i32>, ptr %g 34 | store <32 x i32> %ld, ptr @g2 35 | ret void 36 | } 37 | 38 | declare <32 x i32> @llvm.genx.gather.masked.scaled2.v32i32.v32i32.v32i1(i32, i16, i32, i32, <32 x i32>, <32 x i1>) 39 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 40 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/opaque_ptrs/replicate_mask.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; REQUIRES: opaque-pointers 10 | ; RUN: opt -passes=cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | @g1 = internal global <64 x i32> undef 13 | 14 | ; CHECK: @EM = internal global <32 x i1> 15 | 16 | ; CHECK-LABEL: @test 17 | define dso_local dllexport void @test(<32 x i16> %mask) { 18 | %g = alloca <64 x i32>, align 512 19 | %cmp = icmp ne <32 x i16> %mask, zeroinitializer 20 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %cmp) 21 | br i1 %call, label %if.then, label %if.end 22 | 23 | ; CHECK-LABEL: if.then: 24 | if.then: 25 | ; CHECK: [[CALL1:%.*]] = call <64 x i32> @_Z24func_replicate_mask_attrv() 26 | %call1 = call <64 x i32> @_Z24func_replicate_mask_attrv() 27 | ; CHECK: [[EM_LOAD:%.*]] = load <32 x i1>, ptr @EM 28 | ; CHECK-NEXT: [[CHENNELEM:%.*]] = shufflevector <32 x i1> [[EM_LOAD]], <32 x i1> undef, <64 x i32> 29 | ; CHECK-NEXT: [[CALL1_SIMDCFPREDL:%.*]] = select <64 x i1> [[CHENNELEM]], <64 x i32> [[CALL1]] 30 | store <64 x i32> %call1, ptr %g 31 | br label %if.end 32 | 33 | if.end: 34 | %ld = load <64 x i32>, ptr %g 35 | store <64 x i32> %ld, ptr @g1 36 | ret void 37 | } 38 | 39 | ; CHECK-LABEL: @test_gather4 40 | define dso_local dllexport void @test_gather4(<32 x i16> %mask, <32 x i32> %addrs) { 41 | %g = alloca <64 x i32>, align 512 42 | %cmp = icmp ne <32 x i16> %mask, zeroinitializer 43 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %cmp) 44 | br i1 %call, label %if.then, label %if.end 45 | 46 | ; CHECK-LABEL: if.then: 47 | if.then: 48 | ; CHECK: [[EM_LOAD1:%.*]] = load <32 x i1>, ptr @EM 49 | ; CHECK-NEXT: [[CALL1:%.*]] = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> [[EM_LOAD1]]) 50 | %call1 = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> ) 51 | ; CHECK: [[EM_LOAD2:%.*]] = load <32 x i1>, ptr @EM 52 | ; CHECK-NEXT: [[CHENNELEM:%.*]] = shufflevector <32 x i1> [[EM_LOAD2]], <32 x i1> undef, <64 x i32> 53 | ; CHECK-NEXT: [[CALL1_SIMDCFPREDL:%.*]] = select <64 x i1> [[CHENNELEM]], <64 x i32> [[CALL1]] 54 | store <64 x i32> %call1, ptr %g 55 | br label %if.end 56 | 57 | if.end: 58 | %ld = load <64 x i32>, ptr %g 59 | store <64 x i32> %ld, ptr @g1 60 | ret void 61 | } 62 | 63 | define internal <64 x i32> @_Z24func_replicate_mask_attrv() #0 { 64 | ret <64 x i32> zeroinitializer 65 | } 66 | 67 | declare <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32, i16, i32, i32, <32 x i32>, <32 x i1>) 68 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 69 | 70 | attributes #0 = { noinline nounwind "CMGenxReplicateMask"="2"} 71 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/opaque_ptrs/replicate_mask_masked_gather4.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; REQUIRES: opaque-pointers 10 | ; RUN: opt -passes=cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | @Rcp_T2 = internal global <64 x i32> undef 13 | 14 | ; CHECK: @EM = internal global <32 x i1> 15 | 16 | define dso_local dllexport void @test(<32 x i16> %mask, <32 x i32> %addrs) { 17 | %Rcp_T = alloca <64 x i32>, align 512 18 | %cmp = icmp ne <32 x i16> %mask, zeroinitializer 19 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %cmp) 20 | br i1 %call, label %if.then, label %if.end 21 | 22 | ; CHECK-LABEL: if.then: 23 | if.then: 24 | ; CHECK: [[EM_LOAD1:%.*]] = load <32 x i1>, ptr @EM 25 | ; CHECK-NEXT: [[CALL1:%.*]] = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> [[EM_LOAD1]]) 26 | %call1 = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> ) 27 | ; CHECK: [[EM_LOAD2:%.*]] = load <32 x i1>, ptr @EM 28 | ; CHECK-NEXT: [[CHENNELEM:%.*]] = shufflevector <32 x i1> [[EM_LOAD2]], <32 x i1> undef, <64 x i32> 29 | ; CHECK-NEXT: [[CALL1_SIMDCFPREDL:%.*]] = select <64 x i1> [[CHENNELEM]], <64 x i32> [[CALL1]] 30 | store <64 x i32> %call1, ptr %Rcp_T 31 | br label %if.end 32 | 33 | if.end: 34 | %ld = load <64 x i32>, ptr %Rcp_T 35 | store <64 x i32> %ld, ptr @Rcp_T2 36 | ret void 37 | } 38 | 39 | declare <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32, i16, i32, i32, <32 x i32>, <32 x i1>) 40 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 41 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/opaque_ptrs/update_mask_masked_gather4.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; REQUIRES: opaque-pointers 10 | ; RUN: opt -passes=cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | @g1 = internal global <64 x i32> undef 13 | 14 | ; CHECK: @EM = internal global <32 x i1> 15 | 16 | define dso_local dllexport void @test(<32 x i16> %cond1, <32 x i16> %cond2, <32 x i32> %addrs, <32 x i1> %pred) { 17 | %g = alloca <64 x i32>, align 512 18 | %cmp1 = icmp ne <32 x i16> %cond1, zeroinitializer 19 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %cmp1) 20 | br i1 %call, label %if.then, label %if.end 21 | 22 | ; CHECK-LABEL: if.then: 23 | if.then: 24 | ; CHECK: [[EM_LOAD1:%.*]] = load <32 x i1>, ptr @EM 25 | ; CHECK-NEXT: [[EM_UPDATE1:%.*]] = and <32 x i1> %pred, [[EM_LOAD1]] 26 | ; CHECK-NEXT: [[CALL1:%.*]] = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> [[EM_UPDATE1]]) 27 | %call1 = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> %pred) 28 | ; CHECK: [[EM_LOAD2:%.*]] = load <32 x i1>, ptr @EM 29 | ; CHECK-NEXT: [[EM_UPDATE2:%.*]] = and <32 x i1> %pred, [[EM_LOAD2]] 30 | ; CHECK-NEXT: [[CHENNELEM:%.*]] = shufflevector <32 x i1> [[EM_UPDATE2]], <32 x i1> undef, <64 x i32> 31 | ; CHECK-NEXT: [[CALL1_SIMDCFPRED1:%.*]] = select <64 x i1> [[CHENNELEM]], <64 x i32> [[CALL1]] 32 | store <64 x i32> %call1, ptr %g 33 | %cmp2 = icmp ne <32 x i16> %cond2, zeroinitializer 34 | %nest = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %cmp2) 35 | br i1 %nest, label %if.then2, label %if.end2 36 | 37 | ; CHECK-LABEL: if.then2: 38 | if.then2: 39 | ; CHECK: [[EM_LOAD3:%.*]] = load <32 x i1>, ptr @EM 40 | ; CHECK-NEXT: [[EM_UPDATE2:%.*]] = and <32 x i1> %pred, [[EM_LOAD3]] 41 | ; CHECK-NEXT: [[CHENNELEM2:%.*]] = shufflevector <32 x i1> [[EM_UPDATE2]], <32 x i1> undef, <64 x i32> 42 | ; CHECK-NEXT: %call1.simdcfpred7 = select <64 x i1> [[CHENNELEM2]], <64 x i32> [[CALL1]] 43 | store <64 x i32> %call1, ptr %g 44 | br label %if.end2 45 | 46 | if.end2: 47 | br label %if.end 48 | 49 | if.end: 50 | %ld = load <64 x i32>, ptr %g 51 | store <64 x i32> %ld, ptr @g1 52 | ret void 53 | } 54 | 55 | declare <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32, i16, i32, i32, <32 x i32>, <32 x i1>) 56 | declare <64 x i32> @llvm.genx.wrregioni.v64i32.v16i32.i16.i1(<64 x i32> %load, <64 x i32> %call, i32, i32, i32, i16, i32, i1) 57 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 58 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; UNSUPPORTED: opaque-pointers 10 | ; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | ; CHECK: @EM = internal global <32 x i1> 13 | 14 | @g2 = internal global <32 x i32> undef 15 | 16 | define dso_local dllexport void @test_gather(<32 x i16> %mask, <32 x i32> %addrs) { 17 | entry: 18 | %g = alloca <32 x i32>, align 512 19 | %0 = icmp ne <32 x i16> %mask, zeroinitializer 20 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %0) 21 | br i1 %call, label %if.then, label %if.end 22 | if.then: 23 | ; CHECK-LABEL: if.then: 24 | ; CHECK: [[EM_LOAD1:%.*]] = load <32 x i1>, <32 x i1>* @EM 25 | ; CHECK-NEXT: [[CALL1:%.*]] = call <32 x i32> @llvm.genx.gather.masked.scaled2.v32i32.v32i32.v32i1(i32 2, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> [[EM_LOAD1]]) 26 | %call1 = call <32 x i32> @llvm.genx.gather.masked.scaled2.v32i32.v32i32.v32i1(i32 2, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> ) 27 | 28 | ; CHECK: [[EM_LOAD2:%.*]] = load <32 x i1>, <32 x i1>* @EM 29 | ; CHECK-NEXT: [[CALL1_SIMDCFPREDL:%.*]] = select <32 x i1> [[EM_LOAD2:%.*]], <32 x i32> [[CALL1:%.*]] 30 | store <32 x i32> %call1, <32 x i32>* %g 31 | br label %if.end 32 | 33 | if.end: 34 | %1 = load <32 x i32>, <32 x i32>* %g 35 | store <32 x i32> %1, <32 x i32>* @g2 36 | ret void 37 | } 38 | 39 | declare <32 x i32> @llvm.genx.gather.masked.scaled2.v32i32.v32i32.v32i1(i32, i16, i32, i32, <32 x i32>, <32 x i1>) 40 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 41 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; UNSUPPORTED: opaque-pointers 10 | ; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | @g1 = internal global <64 x i32> undef 13 | 14 | ; CHECK: @EM = internal global <32 x i1> 15 | 16 | ; CHECK-LABEL: @test 17 | define dso_local dllexport void @test(<32 x i16> %mask) { 18 | entry: 19 | %g = alloca <64 x i32>, align 512 20 | %0 = icmp ne <32 x i16> %mask, zeroinitializer 21 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %0) 22 | br i1 %call, label %if.then, label %if.end 23 | 24 | if.then: 25 | ; CHECK: [[CALL1:%.*]] = call <64 x i32> @_Z24func_replicate_mask_attrv() 26 | %call1 = call <64 x i32> @_Z24func_replicate_mask_attrv() 27 | 28 | ; CHECK: [[EM_LOAD:%.*]] = load <32 x i1>, <32 x i1>* @EM 29 | ; CHECK-NEXT: [[CHENNELEM:%.*]] = shufflevector <32 x i1> [[EM_LOAD]], <32 x i1> undef, <64 x i32> 30 | ; CHECK-NEXT: [[CALL1_SIMDCFPREDL:%.*]] = select <64 x i1> [[CHENNELEM]], <64 x i32> [[CALL1]] 31 | store <64 x i32> %call1, <64 x i32>* %g 32 | br label %if.end 33 | 34 | if.end: 35 | %1 = load <64 x i32>, <64 x i32>* %g 36 | store <64 x i32> %1, <64 x i32>* @g1 37 | ret void 38 | } 39 | 40 | ; CHECK-LABEL: @test_gather4 41 | define dso_local dllexport void @test_gather4(<32 x i16> %mask, <32 x i32> %addrs) { 42 | entry: 43 | %g = alloca <64 x i32>, align 512 44 | %0 = icmp ne <32 x i16> %mask, zeroinitializer 45 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %0) 46 | br i1 %call, label %if.then, label %if.end 47 | if.then: 48 | ; CHECK-LABEL: if.then: 49 | ; CHECK: [[EM_LOAD1:%.*]] = load <32 x i1>, <32 x i1>* @EM 50 | ; CHECK-NEXT: [[CALL1:%.*]] = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> [[EM_LOAD1]]) 51 | %call1 = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> ) 52 | 53 | ; CHECK: [[EM_LOAD2:%.*]] = load <32 x i1>, <32 x i1>* @EM 54 | ; CHECK-NEXT: [[CHENNELEM:%.*]] = shufflevector <32 x i1> [[EM_LOAD2]], <32 x i1> undef, <64 x i32> 55 | ; CHECK-NEXT: [[CALL1_SIMDCFPREDL:%.*]] = select <64 x i1> [[CHENNELEM]], <64 x i32> [[CALL1]] 56 | store <64 x i32> %call1, <64 x i32>* %g 57 | br label %if.end 58 | 59 | if.end: 60 | %1 = load <64 x i32>, <64 x i32>* %g 61 | store <64 x i32> %1, <64 x i32>* @g1 62 | ret void 63 | } 64 | 65 | define internal <64 x i32> @_Z24func_replicate_mask_attrv() #0 { 66 | entry: 67 | ret <64 x i32> zeroinitializer 68 | } 69 | 70 | declare <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32, i16, i32, i32, <32 x i32>, <32 x i1>) 71 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 72 | 73 | attributes #0 = { noinline nounwind "CMGenxReplicateMask"="2"} 74 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2021-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; UNSUPPORTED: opaque-pointers 10 | ; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | @Rcp_T2 = internal global <64 x i32> undef 13 | 14 | ; CHECK: @EM = internal global <32 x i1> 15 | 16 | define dso_local dllexport void @test(<32 x i16> %mask, <32 x i32> %addrs) { 17 | entry: 18 | %Rcp_T = alloca <64 x i32>, align 512 19 | %0 = icmp ne <32 x i16> %mask, zeroinitializer 20 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %0) 21 | br i1 %call, label %if.then, label %if.end 22 | if.then: 23 | ; CHECK-LABEL: if.then: 24 | ; CHECK: [[EM_LOAD1:%.*]] = load <32 x i1>, <32 x i1>* @EM 25 | ; CHECK-NEXT: [[CALL1:%.*]] = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> [[EM_LOAD1]]) 26 | %call1 = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> ) 27 | 28 | ; CHECK: [[EM_LOAD2:%.*]] = load <32 x i1>, <32 x i1>* @EM 29 | ; CHECK-NEXT: [[CHENNELEM:%.*]] = shufflevector <32 x i1> [[EM_LOAD2]], <32 x i1> undef, <64 x i32> 30 | ; CHECK-NEXT: [[CALL1_SIMDCFPREDL:%.*]] = select <64 x i1> [[CHENNELEM]], <64 x i32> [[CALL1]] 31 | store <64 x i32> %call1, <64 x i32>* %Rcp_T 32 | br label %if.end 33 | 34 | if.end: 35 | %1 = load <64 x i32>, <64 x i32>* %Rcp_T 36 | store <64 x i32> %1, <64 x i32>* @Rcp_T2 37 | ret void 38 | } 39 | 40 | declare <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32, i16, i32, i32, <32 x i32>, <32 x i1>) 41 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 42 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll: -------------------------------------------------------------------------------- 1 | ;=========================== begin_copyright_notice ============================ 2 | ; 3 | ; Copyright (C) 2020-2024 Intel Corporation 4 | ; 5 | ; SPDX-License-Identifier: MIT 6 | ; 7 | ;============================ end_copyright_notice ============================= 8 | 9 | ; UNSUPPORTED: opaque-pointers 10 | ; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s 11 | 12 | @g1 = internal global <64 x i32> undef 13 | 14 | ; CHECK: @EM = internal global <32 x i1> 15 | 16 | define dso_local dllexport void @test(<32 x i16> %cond1, <32 x i16> %cond2, <32 x i32> %addrs, <32 x i1> %pred) { 17 | entry: 18 | %g = alloca <64 x i32>, align 512 19 | %0 = icmp ne <32 x i16> %cond1, zeroinitializer 20 | %call = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %0) 21 | br i1 %call, label %if.then, label %if.end 22 | if.then: 23 | ; CHECK-LABEL: if.then: 24 | ; CHECK: [[EM_LOAD1:%.*]] = load <32 x i1>, <32 x i1>* @EM 25 | ; CHECK-NEXT: [[EM_UPDATE1:%.*]] = and <32 x i1> %pred, [[EM_LOAD1]] 26 | ; CHECK-NEXT: [[CALL1:%.*]] = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> [[EM_UPDATE1]]) 27 | %call1 = call <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32 12, i16 0, i32 254, i32 0, <32 x i32> %addrs, <32 x i1> %pred) 28 | 29 | ; CHECK: [[EM_LOAD2:%.*]] = load <32 x i1>, <32 x i1>* @EM 30 | ; CHECK-NEXT: [[EM_UPDATE2:%.*]] = and <32 x i1> %pred, [[EM_LOAD2]] 31 | ; CHECK-NEXT: [[CHENNELEM:%.*]] = shufflevector <32 x i1> [[EM_UPDATE2]], <32 x i1> undef, <64 x i32> 32 | ; CHECK-NEXT: [[CALL1_SIMDCFPRED1:%.*]] = select <64 x i1> [[CHENNELEM]], <64 x i32> [[CALL1]] 33 | 34 | store <64 x i32> %call1, <64 x i32>* %g 35 | 36 | %1 = icmp ne <32 x i16> %cond2, zeroinitializer 37 | %nest = call i1 @llvm.genx.simdcf.any.v32i1(<32 x i1> %1) 38 | br i1 %nest, label %if.then2, label %if.end2 39 | 40 | if.then2: 41 | ; CHECK-LABEL: if.then2: 42 | ; CHECK: [[EM_LOAD3:%.*]] = load <32 x i1>, <32 x i1>* @EM 43 | ; CHECK-NEXT: [[EM_UPDATE2:%.*]] = and <32 x i1> %pred, [[EM_LOAD3]] 44 | ; CHECK-NEXT: [[CHENNELEM2:%.*]] = shufflevector <32 x i1> [[EM_UPDATE2]], <32 x i1> undef, <64 x i32> 45 | ; CHECK-NEXT: %call1.simdcfpred7 = select <64 x i1> [[CHENNELEM2]], <64 x i32> [[CALL1]] 46 | store <64 x i32> %call1, <64 x i32>* %g 47 | br label %if.end2 48 | 49 | if.end2: 50 | br label %if.end 51 | if.end: 52 | %2 = load <64 x i32>, <64 x i32>* %g 53 | store <64 x i32> %2, <64 x i32>* @g1 54 | ret void 55 | } 56 | 57 | declare <64 x i32> @llvm.genx.gather4.masked.scaled2.v64i32.v32i32.v32i1(i32, i16, i32, i32, <32 x i32>, <32 x i1>) 58 | declare <64 x i32> @llvm.genx.wrregioni.v64i32.v16i32.i16.i1(<64 x i32> %load, <64 x i32> %call, i32, i32, i32, i16, i32, i1) 59 | declare i1 @llvm.genx.simdcf.any.v32i1(<32 x i1>) 60 | 61 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/lit.cfg.py: -------------------------------------------------------------------------------- 1 | # ========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2020-2024 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | # =========================== end_copyright_notice ============================= 8 | 9 | # -*- Python -*- 10 | 11 | import lit.formats 12 | import lit.util 13 | 14 | from lit.llvm import llvm_config 15 | from lit.llvm.subst import ToolSubst 16 | from lit.llvm.subst import FindTool 17 | 18 | # Configuration file for the 'lit' test runner. 19 | 20 | # name: The name of this test suite. 21 | config.name = 'vc-intrinsics' 22 | 23 | # testFormat: The test format to use to interpret tests. 24 | config.test_format = lit.formats.ShTest(not llvm_config.use_lit_shell) 25 | 26 | # suffixes: A list of file extensions to treat as test files. 27 | config.suffixes = ['.ll'] 28 | 29 | # excludes: A list of directories and files to exclude from the testsuite. 30 | config.excludes = ['CMakeLists.txt', 'Plugin'] 31 | 32 | used_llvm = "llvm{}".format(config.llvm_version_major) 33 | config.available_features = [used_llvm] 34 | if int(config.llvm_version_major) >= 16: 35 | config.available_features.append('opaque-pointers') 36 | 37 | # test_source_root: The root path where tests are located. 38 | config.test_source_root = os.path.dirname(__file__) 39 | 40 | # test_exec_root: The root path where tests should be run. 41 | config.test_exec_root = os.path.join(config.test_run_dir, 'test_output') 42 | 43 | llvm_config.use_default_substitutions() 44 | 45 | config.substitutions.append(('%PATH%', config.environment['PATH'])) 46 | 47 | tool_dirs = [config.llvm_tools_dir] 48 | 49 | # Add extra args for opt to remove boilerplate from tests. 50 | opt_extra_args = ['-load', config.vc_intrinsics_plugin] 51 | 52 | # Add option for new pass manager plugins. Extension instead of 53 | # replacement is needed to hack option parsing mechanism. Argument of 54 | # '-load' is processed during initial option parsing and all passes 55 | # from plugin are registed in legacy PM. This registration allows to 56 | # add passes to new PM via command line options in the same way as 57 | # with old PM. Otherwise, -passes= option will be used for new PM and 58 | # - for old PM. Additionally, LLVM will load plugin only once 59 | # because it permanently loads libraries with caching behavior. 60 | if int(config.llvm_version_major) >= 13: 61 | opt_extra_args.extend(['-load-pass-plugin', config.vc_intrinsics_plugin]) 62 | 63 | if int(config.llvm_version_major) < 13: 64 | config.substitutions.append(('%pass%', ' -')) 65 | else: 66 | config.substitutions.append(('%pass%', ' -passes=')) 67 | 68 | print(f"llvm_version_major:{config.llvm_version_major}") 69 | 70 | tools = [ToolSubst('opt', extra_args=opt_extra_args)] 71 | 72 | llvm_config.add_tool_substitutions(tools, tool_dirs) 73 | -------------------------------------------------------------------------------- /GenXIntrinsics/test/lit.site.cfg.py.in: -------------------------------------------------------------------------------- 1 | # ========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2020-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | # =========================== end_copyright_notice ============================= 8 | 9 | @LIT_SITE_CFG_IN_HEADER@ 10 | 11 | import sys 12 | 13 | config.llvm_src_root = "@LLVM_SOURCE_DIR@" 14 | config.llvm_obj_root = "@LLVM_BINARY_DIR@" 15 | config.llvm_tools_dir = "@LLVM_TOOLS_DIR@" 16 | config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@" 17 | config.host_triple = "@LLVM_HOST_TRIPLE@" 18 | config.target_triple = "@TARGET_TRIPLE@" 19 | config.host_arch = "@HOST_ARCH@" 20 | config.python_executable = "@PYTHON_EXECUTABLE@" 21 | config.test_run_dir = "@CMAKE_CURRENT_BINARY_DIR@" 22 | config.vc_intrinsics_plugin = "$" 23 | config.llvm_version_major = "@LLVM_VERSION_MAJOR@" 24 | 25 | # Support substitution of the tools and libs dirs with user parameters. This is 26 | # used when we can't determine the tool dir at configuration time. 27 | try: 28 | config.llvm_tools_dir = config.llvm_tools_dir % lit_config.params 29 | except KeyError: 30 | e = sys.exc_info()[1] 31 | key, = e.args 32 | lit_config.fatal("unable to find %r parameter, use '--param=%s=VALUE'" % (key,key)) 33 | 34 | import lit.llvm 35 | lit.llvm.initialize(lit_config, config) 36 | 37 | # Let the main config do the real work. 38 | lit_config.load_config(config, "@VC_INTRINSICS_TEST_SOURCE_DIR@/lit.cfg.py") 39 | -------------------------------------------------------------------------------- /GenXIntrinsics/unittests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2019-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | add_custom_target(GenXIntrinsicsUnitTests) 10 | set_target_properties(GenXIntrinsicsUnitTests PROPERTIES FOLDER "GenXIntrinsicsTests") 11 | 12 | function(add_genx_intrinsics_unittest test_dirname) 13 | add_unittest(GenXIntrinsicsUnitTests ${test_dirname} ${ARGN}) 14 | endfunction() 15 | 16 | add_subdirectory(GenXIntrinsics) 17 | -------------------------------------------------------------------------------- /GenXIntrinsics/unittests/GenXIntrinsics/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #=========================== begin_copyright_notice ============================ 2 | # 3 | # Copyright (C) 2019-2021 Intel Corporation 4 | # 5 | # SPDX-License-Identifier: MIT 6 | # 7 | #============================ end_copyright_notice ============================= 8 | 9 | set(LLVM_LINK_COMPONENTS 10 | Core 11 | Support 12 | CodeGen 13 | ) 14 | 15 | add_genx_intrinsics_unittest(GenXIntrinsicsTests 16 | GenXIntrinsicsTest.cpp 17 | ) 18 | 19 | target_link_libraries(GenXIntrinsicsTests 20 | PRIVATE 21 | LLVMGenXIntrinsics 22 | LLVMTestingSupport 23 | ) 24 | -------------------------------------------------------------------------------- /GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp: -------------------------------------------------------------------------------- 1 | /*========================== begin_copyright_notice ============================ 2 | 3 | Copyright (C) 2019-2023 Intel Corporation 4 | 5 | SPDX-License-Identifier: MIT 6 | 7 | ============================= end_copyright_notice ===========================*/ 8 | 9 | #include "llvm/ADT/StringRef.h" 10 | #include "llvm/GenXIntrinsics/GenXIntrinsics.h" 11 | #include "llvm/IR/Intrinsics.h" 12 | #include "llvm/IR/LLVMContext.h" 13 | #include "llvm/IR/Module.h" 14 | 15 | #include "gtest/gtest.h" 16 | 17 | using namespace llvm; 18 | 19 | namespace { 20 | 21 | TEST(GenXIntrinsics, OverloadedTypes) { 22 | EXPECT_EQ(GenXIntrinsic::isOverloadedArg(Intrinsic::fma, 0), false); 23 | EXPECT_EQ(GenXIntrinsic::isOverloadedArg(Intrinsic::fma, 1), false); 24 | EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_3d_sample, 7), 25 | true); 26 | EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_raw_send, 1), 27 | true); 28 | EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_simdcf_any, 0), 29 | true); 30 | EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_ssdp4a, 0), true); 31 | EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_ssdp4a, 1), true); 32 | EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_ssdp4a, 2), true); 33 | EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_dpasw_nosrc0, 2), 34 | false); 35 | EXPECT_EQ( 36 | GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_lsc_store_slm, 10), 37 | true); 38 | EXPECT_EQ( 39 | GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_lsc_store_slm, 11), 40 | true); 41 | EXPECT_EQ( 42 | GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_lsc_store_slm, 12), 43 | false); 44 | } 45 | } // namespace 46 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 Intel Corporation 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Readme.md: -------------------------------------------------------------------------------- 1 | 8 | 9 | # VC Intrinsics 10 | 11 | ## Introduction 12 | 13 | VC Intrinsics project contains a set of new intrinsics on top of core 14 | LLVM IR instructions that represent SIMD semantics of a program 15 | targeting GPU. This set is now used by 16 | 17 | * CMC - https://github.com/intel/cm-compiler 18 | * DPC++ - https://github.com/intel/llvm 19 | * ISPC - https://github.com/ispc/ispc 20 | 21 | frontend compilers and 22 | 23 | * IGC VC backend - https://github.com/intel/intel-graphics-compiler 24 | 25 | ## License 26 | 27 | VC Intrinsics are distributed under the MIT license. 28 | 29 | You may obtain a copy of the License at: 30 | 31 | https://opensource.org/licenses/MIT 32 | 33 | ## Dependencies 34 | 35 | ### Source code 36 | 37 | * LLVM Project - https://github.com/llvm/llvm-project 38 | 39 | ### Tools 40 | 41 | To build libraries: 42 | 43 | * CMake - https://cmake.org/ - 3.13.4 or later 44 | * Python - https://www.python.org/ - 2.7 or later 45 | * C++ compiler - anything that can compile LLVM 46 | 47 | To build documentation: 48 | 49 | * Sphinx - https://www.sphinx-doc.org - 1.5 or later 50 | * GNU Make - https://www.gnu.org/software/make/ - 3.79 or later 51 | * Standard Unix utilities (mkdir, rm, sed) 52 | 53 | ## Building 54 | 55 | VC Intrinsics can be built in two major modes: in-tree and 56 | external. All major LLVM versions starting from LLVM 8 are supported. 57 | 58 | LLVM ToT can be used too, but there is no guarantee that it will 59 | always work (because of sudden breaking changes in LLVM C++ 60 | API). However, maintainers are trying to fix such issues as fast as 61 | possible. 62 | 63 | ### In-tree build 64 | 65 | For in-tree build VC Intrinsics can be considered as an external LLVM 66 | project. Put VC Intrinsics source directory inside `llvm/projects` 67 | directory or add `-DLLVM_EXTERNAL_PROJECTS="vc-intrinsics" 68 | -DLLVM_EXTERNAL_VC_INTRINSICS_SOURCE_DIR=` to cmake 69 | command arguments when configuring LLVM. 70 | 71 | ### External build 72 | 73 | To configure VC Intrinsics with prebuilt LLVM run cmake as follows: 74 | 75 | ```shell 76 | $ cmake -DLLVM_DIR=/lib/cmake/llvm 77 | ``` 78 | 79 | ### Documentation 80 | 81 | VC Intrinsics documentation is inside `docs` subdirectory and can be 82 | built using Sphinx. To build html version do the following: 83 | 84 | ```shell 85 | $ cd docs 86 | $ make -f Makefile.sphinx html 87 | ``` 88 | 89 | This will extract comments from main intrinsics description and 90 | generate readable html output in `_build/html` subdirectory. 91 | 92 | ## Testing 93 | 94 | VC Intrinsics repository contains lit tests that are enabled when 95 | `-DVC_INTR_ENABLE_LIT_TESTS=ON` is passed to cmake command. Lit tests 96 | use LLVM plugins and currently are supported only with dynamic LLVM 97 | (when LLVM is configured with `-DLLVM_LINK_LLVM_DYLIB=ON`). In 98 | external build path to `lit` utility should be specified as follows: 99 | `-DLLVM_EXTERNAL_LIT=`. Full example with external build: 100 | 101 | ```shell 102 | $ cmake -DLLVM_DIR=/lib/cmake/llvm -DVC_INTR_ENABLE_LIT_TESTS=ON -DLLVM_EXTERNAL_LIT= 103 | ``` 104 | 105 | Target `check-vc-intrinsics` will run lit tests. 106 | 107 | ## How to provide feedback 108 | 109 | Please submit an issue using native github.com interface: 110 | https://github.com/intel/vc-intrinsics/issues. 111 | 112 | ## How to contribute 113 | 114 | Create a pull request on github.com with your patch. A maintainer 115 | will contact you if there are questions or concerns. 116 | -------------------------------------------------------------------------------- /SECURITY.md: -------------------------------------------------------------------------------- 1 | # Security Policy 2 | Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation. 3 | 4 | ## Reporting a Vulnerability 5 | Please report any security vulnerabilities in this project [utilizing the guidelines here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html). 6 | --------------------------------------------------------------------------------