Specifies that the local memory addresses should use bits for bank selection.
36 |
37 |
38 |
39 | // Array is implemented with 4 banks where
40 | // bits 6 and 5 of the memory word address
41 | // are used to select between the banks
42 | [[intel::bank_bits(6,5)]] int array[128];
43 |
44 |
45 |
46 |
47 |
48 | bankwidth
49 |
50 |
51 |
Specifies that the memory implementing the variable or array must have memory banks of a defined width.
52 |
53 |
54 |
55 | // Each memory bank is 8 bytes (64-bits) wide
56 | [[intel::bankwidth(8)]] int array[128];
57 |
58 |
59 |
60 |
61 | doublepump
62 |
63 |
64 |
Specifies that the memory implementing the variable, or an array must be clocked at twice the rate as the kernel accessing it.
65 |
66 |
67 |
68 | // Array is implemented in a memory that operates at
69 | // twice the clock frequency of the kernel
70 | [[intel::doublepump, bankwidth(128)]] int array[128];
71 |
72 |
73 |
74 | force_pow2_depth
75 |
76 |
77 |
Specifies that the memory implementing the variable or array has a power-of-2 depth.
78 |
79 |
80 |
81 | // array1 is implemented in a memory with depth 1536
82 | [[intel::force_pow2_depth(0)]] int array1[1536];
83 |
84 |
85 |
86 |
87 | max_replicates
88 |
89 |
90 |
91 |
Specifies that the memory implementing the variable, or an array has no more than the specified number of replicates to enable simultaneous accesses from the datapath.
92 |
93 |
94 |
95 | // Array is implemented in a memory with maximum four
96 | // replicates
97 | [[intel::max_replicates(4)]] int array[128];
98 |
99 |
100 |
101 |
102 | fpga_memory
103 |
104 |
105 |
Forces a variable or an array to be implemented as an embedded memory.
106 |
107 |
108 |
109 | // Array is implemented in memory (MLAB/M20K),
110 | // the actual implementation is automatically decided
111 | // by the compiler
112 | [[intel::fpga_memory]] int array1[128];
113 |
114 | // Array is implemented in M20K
115 | [[intel::fpga_memory("BLOCK_RAM")]] int array2[64];
116 |
117 | // Array is implemented in MLAB
118 | [[intel::fpga_memory("MLAB")]] int array3[64];
119 |
120 |
121 |
122 |
123 | merge
124 |
125 |
126 |
Allows merging of two or more variables or arrays defined in the same scope with respect to width or depth.
127 |
128 |
129 |
130 | // Both arrays are merged width-wise and implemented
131 | // in the same memory system
132 | [[intel::merge("mem", "width")]] short arrayA[128];
133 | [[intel::merge("mem", "width")]] short arrayB[128];
134 |
135 |
136 |
137 |
138 | numbanks
139 |
140 |
141 |
Specifies that the memory implementing the variable or array must have a defined number of memory banks.
142 |
Specifies that the memory implementing the variable, or an array has no more than the specified number of independent copies to enable concurrent thread or loop iteration accesses.
155 |
156 |
157 |
158 | // Array is implemented in a memory with two
159 | // private copies
160 | [[intel::private_copies(2)]] int array[128];
161 |
162 |
163 |
164 |
165 | fpga_register
166 |
167 |
168 |
Forces a variable or an array to be carried through the pipeline in registers.
169 |
Specifies that the memory implementing the variable or array should have no port that serves both reads and writes.
182 |
183 |
184 |
185 | // Array is implemented in a memory such that no
186 | // single port serves both a read and a write
187 | [[intel::simple_dual_port]] int array[128];
188 |
189 |
190 |
191 |
192 | singlepump
193 |
194 |
195 |
Specifies that the memory implementing the variable or array must be clocked at the same rate as the kernel accessing it.
196 |
197 |
198 |
199 | // Array is implemented in a memory that operates
200 | // at the same clock frequency as the kernel
201 | [[intel::singlepump]] int array[128];
202 |
203 |
204 |
205 |
206 |