├── .gitignore ├── .ipynb_checkpoints └── Project Report-checkpoint.ipynb ├── FPGA ├── dhr_dir │ ├── dsp │ │ └── p=(Ax(B+D))+C.v │ ├── try │ │ ├── dsp │ │ │ ├── ipcore_dir │ │ │ │ └── MAC_unit.v │ │ │ └── mac.v │ │ ├── hello_world │ │ │ └── hello_world.v │ │ ├── kishore │ │ │ ├── MAC_with_memory.v │ │ │ ├── MAC_with_memory_tb.v │ │ │ ├── My_Block_RAM.v │ │ │ ├── Random_size_Block_RAM.v │ │ │ ├── VG_ROM.v │ │ │ ├── sigmoid.v │ │ │ └── sigmoid_tb.v │ │ ├── mac_module_testing │ │ │ └── user_defined_modules │ │ │ │ ├── mac_module_stimulus.ucf │ │ │ │ ├── mac_module_stimulus_full_testbench.v │ │ │ │ ├── uart_core │ │ │ │ ├── uart_core.v │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ └── utils │ │ │ │ ├── mac_module_test.v │ │ │ │ ├── pulse_generator.v │ │ │ │ └── reset_controller.v │ │ ├── mac_stimulus_test │ │ │ └── user_defined_modules │ │ │ │ ├── mac_module_stimulus.ucf │ │ │ │ ├── mac_module_stimulus_full_testbench.v │ │ │ │ ├── uart_core │ │ │ │ ├── uart_core.v │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ └── utils │ │ │ │ ├── mac_module_test.v │ │ │ │ ├── pulse_generator.v │ │ │ │ └── reset_controller.v │ │ ├── pulse_gen │ │ │ └── user_defined_modules │ │ │ │ └── pulse_generator.v │ │ ├── sch_try │ │ │ └── user_defined_modules │ │ │ │ ├── mac_module_stimulus.ucf │ │ │ │ ├── mac_module_stimulus.v │ │ │ │ ├── mac_module_stimulus_full_testbench.v │ │ │ │ ├── uart_core │ │ │ │ ├── uart_core.v │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ └── utils │ │ │ │ ├── mac_module.v │ │ │ │ ├── mac_module_test.v │ │ │ │ ├── pulse_generator.v │ │ │ │ └── reset_controller.v │ │ ├── try2 │ │ │ ├── dsp_template.v │ │ │ └── mac.v │ │ ├── tx │ │ │ ├── uart_tx_core.ucf │ │ │ └── user_defined_modules │ │ │ │ ├── uart_tx_core.v │ │ │ │ └── utils │ │ │ │ ├── pulse_generator.v │ │ │ │ ├── reset_controller.v │ │ │ │ ├── transmitter_core_test.v │ │ │ │ ├── tx_baudrate_tick_generator.v │ │ │ │ ├── tx_tick_generator.v │ │ │ │ └── uart_tx_core.ucf │ │ └── uart_core │ │ │ ├── uart_core.ucf │ │ │ └── user_defined_module │ │ │ ├── reset_controller │ │ │ └── reset_controller.v │ │ │ ├── uart_core.v │ │ │ ├── uart_rx_core │ │ │ ├── uart_rx_core.v │ │ │ └── utils │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ └── uart_tx_core │ │ │ ├── uart_tx_core.v │ │ │ └── utils │ │ │ ├── pulse_generator.v │ │ │ └── tx_baudrate_tick_generator.v │ └── working projects with test signals │ │ └── mac_module │ │ ├── mac_module_stimulus.ucf │ │ ├── mac_module_stimulus.v │ │ ├── mac_module_stimulus_full_testbench.v │ │ ├── uart_core │ │ ├── uart_core.v │ │ ├── uart_rx_core │ │ │ ├── uart_rx_core.v │ │ │ └── utils │ │ │ │ └── rx_baudrate_tick_generator.v │ │ └── uart_tx_core │ │ │ ├── uart_tx_core.v │ │ │ └── utils │ │ │ ├── pulse_generator.v │ │ │ └── tx_baudrate_tick_generator.v │ │ └── utils │ │ ├── mac_module.v │ │ ├── mac_module_test.v │ │ ├── pulse_generator.v │ │ └── reset_controller.v ├── final_working_codes │ ├── binary_to_bcd_core.v │ ├── debuoncing_switch.v │ ├── mac_module.v │ ├── pulse_generator.v │ ├── reset_controller.v │ ├── ring_shift_register.v │ ├── rx_baudrate_tick_generator.v │ ├── seven_segment_display.v │ ├── seven_segment_display_core.v │ ├── tick_generator.v │ ├── tx_baudrate_tick_generator.v │ ├── uart_core.v │ ├── uart_rx_core.v │ └── uart_tx_core.v ├── final_working_projects │ ├── binary_to_bcd_core │ │ └── binary_to_bcd_core.v │ ├── integer_seven_segment_display_controller │ │ ├── binary_to_bcd_core │ │ │ └── binary_to_bcd_core.v │ │ ├── integer_seven_segment_display_controller.ucf │ │ ├── integer_seven_segment_display_controller.v │ │ ├── integer_seven_segment_display_controller_test.v │ │ └── seven_segment_display_core │ │ │ ├── seven_segment_display_core.v │ │ │ └── utils │ │ │ ├── ring_shift_register.v │ │ │ ├── seven_segment_display.v │ │ │ └── tick_generator.v │ ├── mac_module │ │ ├── mac_module_stimulus.ucf │ │ ├── mac_module_stimulus.v │ │ ├── uart_core │ │ │ ├── uart_core.v │ │ │ ├── uart_rx_core │ │ │ │ ├── uart_rx_core.v │ │ │ │ └── utils │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ └── uart_tx_core │ │ │ │ ├── uart_tx_core.v │ │ │ │ └── utils │ │ │ │ ├── pulse_generator.v │ │ │ │ └── tx_baudrate_tick_generator.v │ │ └── utils │ │ │ ├── mac_module.v │ │ │ ├── pulse_generator.v │ │ │ └── reset_controller.v │ ├── ring_shift_register │ │ └── ring_shift_register.v │ ├── seven_segment_display │ │ └── seven_segment_display.v │ ├── seven_segment_display_controller │ │ ├── seven_segment_display_controller.v │ │ └── utils │ │ │ ├── ring_shift_register.v │ │ │ ├── seven_segment_display.v │ │ │ ├── shift_register.v │ │ │ └── tick_generator.v │ ├── seven_segment_display_core │ │ ├── seven_segment_display_core.v │ │ └── utils │ │ │ ├── ring_shift_register.v │ │ │ ├── seven_segment_display.v │ │ │ └── tick_generator.v │ ├── shift_register │ │ └── shift_register.v │ ├── uart_core │ │ ├── reset_controller │ │ │ └── reset_controller.v │ │ ├── uart_core.ucf │ │ ├── uart_core.v │ │ ├── uart_rx_core │ │ │ ├── uart_rx_core.v │ │ │ └── utils │ │ │ │ └── rx_baudrate_tick_generator.v │ │ └── uart_tx_core │ │ │ ├── uart_tx_core.v │ │ │ └── utils │ │ │ ├── pulse_generator.v │ │ │ └── tx_baudrate_tick_generator.v │ └── uart_tx_core │ │ ├── uart_tx_core.v │ │ └── utils │ │ ├── pulse_generator.v │ │ ├── transmitter_core_test.v │ │ ├── tx_baudrate_tick_generator.v │ │ ├── tx_tick_generator.v │ │ └── uart_tx_core.ucf ├── ironstein_fpga_working_directory │ ├── verilog_working_directory │ │ └── src │ │ │ ├── FPGA_prototyping_by_verilog_basics │ │ │ ├── arithematic_cores │ │ │ │ └── binary_to_bcd_converter │ │ │ │ │ ├── binary_to_bcd_converter_mark1 │ │ │ │ │ ├── binary_to_bcd_converter_mark1.v │ │ │ │ │ └── seven_segment_display_controller │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ ├── seven_segment_display_controller.v │ │ │ │ │ │ └── tick_generator.v │ │ │ │ │ └── binary_to_bcd_converter_mark2 │ │ │ │ │ ├── binary_to_bcd_converter.v │ │ │ │ │ └── binary_to_bcd_converter_testing.v │ │ │ ├── basics │ │ │ │ ├── 02_blinky.ucf │ │ │ │ ├── 02_blinky.v │ │ │ │ ├── 03_RTL_basics.v │ │ │ │ ├── 04_memory.v │ │ │ │ ├── 05_seven_segment_display_full_controller.v │ │ │ │ └── verilog_general_description.v │ │ │ ├── classifier │ │ │ │ ├── classifier_mark1 │ │ │ │ │ ├── ROM │ │ │ │ │ │ ├── ROM.v │ │ │ │ │ │ └── dual_port_ROM.v │ │ │ │ │ ├── classifier.v │ │ │ │ │ ├── classifier_pulse_generator │ │ │ │ │ │ └── classifier_pulse_generator.v │ │ │ │ │ ├── classifier_tb.v │ │ │ │ │ ├── classifier_test.v │ │ │ │ │ ├── classifier_test_tb.v │ │ │ │ │ ├── counter │ │ │ │ │ │ ├── counter.v │ │ │ │ │ │ ├── counter_tb.v │ │ │ │ │ │ ├── counter_test.v │ │ │ │ │ │ ├── counter_test_tb.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ └── counter_pulse_generator.v │ │ │ │ │ ├── sigmoid │ │ │ │ │ │ ├── sigmoid.v │ │ │ │ │ │ ├── sigmoid_tb.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ ├── VG_ROM_8x18.v │ │ │ │ │ │ │ └── sigmoid_combinational.v │ │ │ │ │ ├── sigmoid_mark2 │ │ │ │ │ │ ├── sigmoid_mark2.v │ │ │ │ │ │ ├── sigmoid_tb.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ ├── sigmoid_ROM.v │ │ │ │ │ │ │ └── sigmoid_combinational.v │ │ │ │ │ └── tdp_bram │ │ │ │ │ │ ├── bram_tdp_wrapper.v │ │ │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ │ │ └── seven_segment_display_core │ │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ │ └── tick_generator.v │ │ │ │ │ │ ├── reset_controller │ │ │ │ │ │ └── reset_controller.v │ │ │ │ │ │ ├── top.ucf │ │ │ │ │ │ ├── top.v │ │ │ │ │ │ ├── top_tb.v │ │ │ │ │ │ └── uart_core_with_tx_buffer │ │ │ │ │ │ ├── tick_generator.v │ │ │ │ │ │ ├── uart_core.ucf │ │ │ │ │ │ ├── uart_core.v │ │ │ │ │ │ ├── uart_rx_core │ │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ │ │ ├── uart_tx_core │ │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ │ ├── uart_tx_core_tb.v │ │ │ │ │ │ ├── uart_tx_core_test.v │ │ │ │ │ │ ├── uart_tx_core_test_tb.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ ├── fifo_ipcore_dir │ │ │ │ │ │ │ ├── FIFO.v │ │ │ │ │ │ │ └── FIFO │ │ │ │ │ │ │ │ └── example_design │ │ │ │ │ │ │ │ └── FIFO_exdes.ucf │ │ │ │ │ │ │ ├── my_fifo.v │ │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ │ │ ├── uart_tx_core_test.v │ │ │ │ │ │ └── uart_tx_core_test_tb.v │ │ │ │ └── classifier_mark2 │ │ │ │ │ ├── classifier.v │ │ │ │ │ ├── classifier_pulse_generator │ │ │ │ │ └── classifier_pulse_generator.v │ │ │ │ │ ├── classifier_tb.v │ │ │ │ │ ├── classifier_test.v │ │ │ │ │ ├── classifier_test_tb.v │ │ │ │ │ ├── counter │ │ │ │ │ ├── counter.v │ │ │ │ │ ├── counter_tb.v │ │ │ │ │ ├── counter_test.v │ │ │ │ │ ├── counter_test_tb.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── counter_pulse_generator.v │ │ │ │ │ ├── duap_port_ROM │ │ │ │ │ ├── ROM.v │ │ │ │ │ └── dual_port_ROM.v │ │ │ │ │ ├── sigmoid │ │ │ │ │ ├── sigmoid.v │ │ │ │ │ ├── sigmoid_tb.v │ │ │ │ │ └── utils │ │ │ │ │ │ ├── VG_ROM_8x18.v │ │ │ │ │ │ └── sigmoid_combinational.v │ │ │ │ │ ├── sigmoid_mark2 │ │ │ │ │ ├── sigmoid_mark2.v │ │ │ │ │ ├── sigmoid_tb.v │ │ │ │ │ └── utils │ │ │ │ │ │ ├── sigmoid_ROM.v │ │ │ │ │ │ └── sigmoid_combinational.v │ │ │ │ │ └── tdp_bram │ │ │ │ │ ├── bram_tdp_wrapper.v │ │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ │ └── seven_segment_display_core │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ └── tick_generator.v │ │ │ │ │ ├── reset_controller │ │ │ │ │ └── reset_controller.v │ │ │ │ │ ├── top.ucf │ │ │ │ │ ├── top.v │ │ │ │ │ ├── top_tb.v │ │ │ │ │ └── uart_core_with_tx_buffer │ │ │ │ │ ├── tick_generator.v │ │ │ │ │ ├── uart_core.ucf │ │ │ │ │ ├── uart_core.v │ │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ │ ├── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ ├── uart_tx_core_tb.v │ │ │ │ │ ├── uart_tx_core_test.v │ │ │ │ │ ├── uart_tx_core_test_tb.v │ │ │ │ │ └── utils │ │ │ │ │ │ ├── fifo_ipcore_dir │ │ │ │ │ │ ├── FIFO.v │ │ │ │ │ │ └── FIFO │ │ │ │ │ │ │ └── example_design │ │ │ │ │ │ │ └── FIFO_exdes.ucf │ │ │ │ │ │ ├── my_fifo.v │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ │ ├── uart_tx_core_test.v │ │ │ │ │ └── uart_tx_core_test_tb.v │ │ │ ├── debouncing │ │ │ │ ├── debuoncing_switch.v │ │ │ │ └── tick_generator.v │ │ │ ├── lpddr_memory_controller │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ │ └── seven_segment_display_core │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ └── tick_generator.v │ │ │ │ ├── reset_controller │ │ │ │ │ └── reset_controller.v │ │ │ │ ├── top.v │ │ │ │ ├── traffic_generator │ │ │ │ │ ├── fifo.v │ │ │ │ │ ├── fifo_test.v │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ ├── traffic_generator.v │ │ │ │ │ ├── traffic_generator_mark2.v │ │ │ │ │ ├── traffic_generator_mark2_test.v │ │ │ │ │ └── traffic_generator_test.v │ │ │ │ ├── uart_core │ │ │ │ │ ├── uart_core.ucf │ │ │ │ │ ├── uart_core.v │ │ │ │ │ ├── uart_rx_core │ │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ │ └── uart_tx_core │ │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ ├── user_design │ │ │ │ │ ├── par │ │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ │ └── memc_wrapper.v │ │ │ │ │ └── sim │ │ │ │ │ │ ├── afifo.v │ │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ │ ├── tg_status.v │ │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ │ └── write_data_path.v │ │ │ │ └── utlis │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tick_generator.v │ │ │ ├── lpddr_memory_controller_mark2 │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ │ └── seven_segment_display_core │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ └── tick_generator.v │ │ │ │ ├── lpddr_memory_controller.ucf │ │ │ │ ├── reset_controller │ │ │ │ │ └── reset_controller.v │ │ │ │ ├── top.v │ │ │ │ ├── traffic_generator │ │ │ │ │ ├── my_fifo.v │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ ├── traffic_generator.v │ │ │ │ │ ├── traffic_generator_mark2.v │ │ │ │ │ ├── traffic_generator_mark2_test.v │ │ │ │ │ └── traffic_generator_test.v │ │ │ │ ├── uart_core │ │ │ │ │ ├── uart_core.ucf │ │ │ │ │ ├── uart_core.v │ │ │ │ │ ├── uart_rx_core │ │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ │ └── uart_tx_core │ │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ │ └── utils │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ ├── user_design │ │ │ │ │ ├── par │ │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ │ └── memc_wrapper.v │ │ │ │ │ └── sim │ │ │ │ │ │ ├── afifo.v │ │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ │ ├── tg_status.v │ │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ │ └── write_data_path.v │ │ │ │ └── utlis │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tick_generator.v │ │ │ ├── lpddr_memory_controller_mark6 │ │ │ │ ├── lpddr_memory_controller.ucf │ │ │ │ ├── top.v │ │ │ │ ├── top_test.v │ │ │ │ ├── top_test_tb.v │ │ │ │ ├── user_design │ │ │ │ │ ├── par │ │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ │ └── memc_wrapper.v │ │ │ │ │ └── sim │ │ │ │ │ │ ├── afifo.v │ │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ │ ├── tg_status.v │ │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ │ └── write_data_path.v │ │ │ │ └── utlis │ │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ │ └── seven_segment_display_core │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ └── tick_generator.v │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ ├── reset_controller │ │ │ │ │ └── reset_controller.v │ │ │ │ │ ├── tick_generator.v │ │ │ │ │ ├── traffic_generator │ │ │ │ │ ├── traffic_generator.v │ │ │ │ │ └── utils │ │ │ │ │ │ ├── my_fifo.v │ │ │ │ │ │ └── traffic_generator_pulse_generator.v │ │ │ │ │ └── uart_core │ │ │ │ │ ├── uart_core.ucf │ │ │ │ │ ├── uart_core.v │ │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ ├── lpddr_memory_controller_mark7 │ │ │ │ ├── lpddr_memory_controller.ucf │ │ │ │ ├── top.v │ │ │ │ ├── top_tb.v │ │ │ │ ├── top_test.v │ │ │ │ ├── top_test_tb.v │ │ │ │ ├── user_design │ │ │ │ │ ├── par │ │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ │ ├── rtl │ │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ │ └── memc_wrapper.v │ │ │ │ │ └── sim │ │ │ │ │ │ ├── afifo.v │ │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ │ ├── tg_status.v │ │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ │ └── write_data_path.v │ │ │ │ └── utils │ │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ │ └── seven_segment_display_core │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ └── tick_generator.v │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ ├── reset_controller │ │ │ │ │ └── reset_controller.v │ │ │ │ │ ├── tick_generator.v │ │ │ │ │ ├── traffic_generator │ │ │ │ │ ├── traffic_generator.v │ │ │ │ │ ├── traffic_generator_tb.v │ │ │ │ │ ├── traffic_generator_test.v │ │ │ │ │ ├── traffic_generator_test_tb.v │ │ │ │ │ └── utils │ │ │ │ │ │ ├── my_fifo.v │ │ │ │ │ │ └── traffic_generator_pulse_generator.v │ │ │ │ │ └── uart_core │ │ │ │ │ ├── uart_core.ucf │ │ │ │ │ ├── uart_core.v │ │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ ├── memory_controller_traffic_generator │ │ │ │ ├── fifo_mark1.v │ │ │ │ └── traffic_generator_mark1.v │ │ │ ├── memory_controller_traffic_generator_mark3 │ │ │ │ ├── my_fifo │ │ │ │ │ ├── my_fifo.v │ │ │ │ │ ├── my_fifo_tb.v │ │ │ │ │ ├── my_fifo_test.v │ │ │ │ │ └── my_fifo_test_tb.v │ │ │ │ ├── pulse_generator │ │ │ │ │ └── pulse_generator.v │ │ │ │ └── traffic_generator │ │ │ │ │ ├── traffic_generator.v │ │ │ │ │ ├── traffic_generator_tb.v │ │ │ │ │ ├── traffic_generator_test.v │ │ │ │ │ └── traffic_generator_test_tb.v │ │ │ ├── memory_controller_traffic_generator_mark4 │ │ │ │ ├── my_fifo │ │ │ │ │ ├── my_fifo.v │ │ │ │ │ ├── my_fifo_tb.v │ │ │ │ │ ├── my_fifo_test.v │ │ │ │ │ └── my_fifo_test_tb.v │ │ │ │ ├── pulse_generator │ │ │ │ │ └── pulse_generator.v │ │ │ │ └── traffic_generator │ │ │ │ │ ├── traffic_generator.v │ │ │ │ │ ├── traffic_generator_tb.v │ │ │ │ │ ├── traffic_generator_test.v │ │ │ │ │ └── traffic_generator_test_tb.v │ │ │ ├── memory_controller_traffic_generator_mark5 │ │ │ │ ├── my_fifo │ │ │ │ │ ├── my_fifo.v │ │ │ │ │ ├── my_fifo_tb.v │ │ │ │ │ ├── my_fifo_test.v │ │ │ │ │ └── my_fifo_test_tb.v │ │ │ │ ├── pulse_generator │ │ │ │ │ └── pulse_generator.v │ │ │ │ └── traffic_generator │ │ │ │ │ ├── traffic_generator.v │ │ │ │ │ ├── traffic_generator_tb.v │ │ │ │ │ ├── traffic_generator_test.v │ │ │ │ │ └── traffic_generator_test_tb.v │ │ │ ├── reset_controller │ │ │ │ └── reset_controller.v │ │ │ ├── seven_segment_display_controller │ │ │ │ ├── integer_display_seven_segment_display_core │ │ │ │ │ ├── binary_to_12bit_bcd_converter.v │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ ├── integer_seven_segment_display_controller_mark2.v │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ ├── seven_segment_display_controller.v │ │ │ │ │ └── tick_generator.v │ │ │ │ ├── integer_seven_segment_display_coer_mark2 │ │ │ │ │ ├── binary_to_12bit_bcd_converter_mark2.v │ │ │ │ │ ├── integer_seven_segment_display_controller_mark2.v │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ ├── seven_segment_display_controller.v │ │ │ │ │ └── tick_generator.v │ │ │ │ ├── integer_seven_segment_display_controller_mark3 │ │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ │ ├── reset_controller │ │ │ │ │ │ └── reset_controller.v │ │ │ │ │ └── seven_segment_display_core │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ └── tick_generator.v │ │ │ │ └── seven_segment_display_core │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ ├── seven_segment_display_controller.v │ │ │ │ │ ├── shift_register.v │ │ │ │ │ └── tick_generator.v │ │ │ ├── uart │ │ │ │ ├── 01_uart_mark1 │ │ │ │ │ ├── counter │ │ │ │ │ │ ├── counter.v │ │ │ │ │ │ └── counter_test_bench.v │ │ │ │ │ ├── pulse generator │ │ │ │ │ │ ├── counter.v │ │ │ │ │ │ ├── counter_and_pulse_generator_test.v │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ └── pulse_generator_test_bench.v │ │ │ │ │ ├── sampling_tick_generator │ │ │ │ │ │ ├── sampling_tick_generator.v │ │ │ │ │ │ └── sampling_tick_generator_test_bench.v │ │ │ │ │ ├── serial_input_parallel_output_shift_register │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ ├── serial_input_parallel_output_shift_register.v │ │ │ │ │ │ ├── serial_input_parallel_output_shift_register_test.v │ │ │ │ │ │ └── tick_generator.v │ │ │ │ │ └── uart_receiver │ │ │ │ │ │ ├── counter.v │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ ├── sampling_tick_generator.v │ │ │ │ │ │ ├── serial_input_parallel_output_shift_register.v │ │ │ │ │ │ └── uart_receiver.v │ │ │ │ ├── uart_core │ │ │ │ │ └── uart_core_verilog_modules │ │ │ │ │ │ ├── counter.v │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ ├── sampling_tick_generator.v │ │ │ │ │ │ ├── serial_input_parallel_output_shift_register.v │ │ │ │ │ │ ├── stimulus.v │ │ │ │ │ │ └── uart_core.v │ │ │ │ ├── uart_receiver │ │ │ │ │ ├── 02_uart_receiver_core_mark2 │ │ │ │ │ │ ├── baudrate_tick_generator.v │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ ├── tick_generator.v │ │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ │ ├── uart_rx_seven_segment_display.v │ │ │ │ │ │ └── uart_rxseven_segment_display_tb.v │ │ │ │ │ ├── 03_uart_receiver_mark3 │ │ │ │ │ │ ├── rx_baudrate_tick_generator.v │ │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ │ └── uart_rx_test.v │ │ │ │ │ ├── 04_uart_receiver_ssd_testing │ │ │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ │ │ │ └── seven_segment_display_core │ │ │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ │ │ └── tick_generator.v │ │ │ │ │ │ ├── reset_controller │ │ │ │ │ │ │ └── reset_controller.v │ │ │ │ │ │ ├── uart_receiver_ssd_test.v │ │ │ │ │ │ └── uart_rx_core │ │ │ │ │ │ │ ├── rx_baudrate_tick_generator.v │ │ │ │ │ │ │ └── uart_rx_core.v │ │ │ │ │ └── uart_rx_ssd_test │ │ │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ │ │ └── seven_segment_display_core │ │ │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ │ │ └── utils │ │ │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ │ │ └── tick_generator.v │ │ │ │ │ │ ├── reset_controller │ │ │ │ │ │ └── reset_controller.v │ │ │ │ │ │ ├── uart_receiver_ssd_test.ucf │ │ │ │ │ │ ├── uart_receiver_ssd_test.v │ │ │ │ │ │ └── uart_rx_core │ │ │ │ │ │ ├── rx_baudrate_tick_generator.v │ │ │ │ │ │ └── uart_rx_core.v │ │ │ │ ├── uart_transmitter │ │ │ │ │ ├── 02_uart_transmitter_core │ │ │ │ │ │ ├── uart_transmitter_core_test.ucf │ │ │ │ │ │ └── uart_transmitter_core_verilog_modules │ │ │ │ │ │ │ ├── baudrate_generator.v │ │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ │ ├── stimulus.v │ │ │ │ │ │ │ ├── tick_generator.v │ │ │ │ │ │ │ ├── uart_transmitter_core.v │ │ │ │ │ │ │ └── uart_transmitter_core_test.v │ │ │ │ │ ├── 03_uart_transmitter_core_mark2 _WORKING_SIMULATION │ │ │ │ │ │ └── uart_transmitter_core_verilog_modules │ │ │ │ │ │ │ ├── baudrate_generator.v │ │ │ │ │ │ │ ├── final_testbenches │ │ │ │ │ │ │ ├── baudrate_tick_generator_tb.v │ │ │ │ │ │ │ ├── pulse_generator_tb.v │ │ │ │ │ │ │ ├── tick_generator_tb.v │ │ │ │ │ │ │ └── uart_transmitter_core_tb.v │ │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ │ ├── stimulus.v │ │ │ │ │ │ │ ├── tick_generator.v │ │ │ │ │ │ │ ├── uart_transmitter_core.v │ │ │ │ │ │ │ ├── uart_transmitter_core_mark2.ucf │ │ │ │ │ │ │ └── uart_transmitter_core_test.v │ │ │ │ │ └── uart_receiver_mark1 │ │ │ │ │ │ ├── test.v │ │ │ │ │ │ └── uart_receiver_verilog_modules │ │ │ │ │ │ ├── counter.v │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ ├── sampling_tick_generator.v │ │ │ │ │ │ ├── serial_input_parallel_output_shift_register.v │ │ │ │ │ │ └── uart_receiver.v │ │ │ │ ├── uart_transmitter_core │ │ │ │ │ ├── transmitter_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ │ ├── reset_controller.v │ │ │ │ │ │ ├── tick_generator.v │ │ │ │ │ │ ├── transmitter_core.ucf │ │ │ │ │ │ ├── transmitter_core_test.v │ │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ ├── uart_transmitter_mark4_rana_chomu │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ ├── reset_controller.v │ │ │ │ │ ├── transmitter_core_test.v │ │ │ │ │ ├── trasnsmitter_core.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ └── uart_transmitter_mark6_rana │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ ├── reset_controller.v │ │ │ │ │ ├── tick_generator.v │ │ │ │ │ ├── transmitter_core.v │ │ │ │ │ ├── transmitter_core_test.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ ├── uart_core_with_tx_fifo │ │ │ │ ├── uart_core.ucf │ │ │ │ ├── uart_core.v │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ ├── uart_tx_core_tb.v │ │ │ │ │ ├── uart_tx_core_test.v │ │ │ │ │ ├── uart_tx_core_test_tb.v │ │ │ │ │ └── utils │ │ │ │ │ ├── my_fifo.v │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ └── vga_controller │ │ │ │ ├── vga_sync_signals_generator.v │ │ │ │ ├── vga_sync_signals_generator │ │ │ │ ├── counter.v │ │ │ │ ├── tick_generator.v │ │ │ │ ├── vga_sync_signals_generator.v │ │ │ │ └── vga_sync_signals_generator_test.v │ │ │ │ └── vga_sync_signals_generator_test.v │ │ │ ├── final_source_codes │ │ │ ├── baudrate_generator.v │ │ │ ├── pulse_generator.v │ │ │ ├── reset_controller │ │ │ │ └── reset_controller.v │ │ │ ├── seven_segment_display_core │ │ │ │ ├── seven_segment_display_controller.v │ │ │ │ └── utils │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ ├── shift_register.v │ │ │ │ │ └── tick_generator.v │ │ │ ├── tick_generator.v │ │ │ ├── uart_core │ │ │ │ ├── reset_controller │ │ │ │ │ └── reset_controller.v │ │ │ │ ├── uart_core.v │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── rx_baudrate_tick_generator.v │ │ │ │ │ └── uart_rx_core.v │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ ├── reset_controller.v │ │ │ │ │ ├── transmitter_core_test.v │ │ │ │ │ ├── tx_baudrate_tick_generator.v │ │ │ │ │ ├── tx_tick_generator.v │ │ │ │ │ └── uart_tx_core.ucf │ │ │ └── uart_rx_ssd_test │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ └── seven_segment_display_core │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ └── tick_generator.v │ │ │ │ ├── reset_controller │ │ │ │ └── reset_controller.v │ │ │ │ ├── uart_receiver_ssd_test.ucf │ │ │ │ ├── uart_receiver_ssd_test.v │ │ │ │ └── uart_rx_core │ │ │ │ ├── rx_baudrate_tick_generator.v │ │ │ │ └── uart_rx_core.v │ │ │ └── verilog_basics │ │ │ ├── 01_hello_world.v │ │ │ ├── 02_basics_01.v │ │ │ ├── 03_shift_register.v │ │ │ ├── 04_logic_gates.v │ │ │ ├── 05_multiplexer.v │ │ │ ├── 06_adder_1_bit.v │ │ │ ├── 07_ripple_carry_adder_4_bit.v │ │ │ ├── 08_mux_4_to_1_dataflow.v │ │ │ └── test.v │ ├── xilinx_coregen_projects │ │ ├── lpddr_interfacing │ │ │ └── lpddr_memory_controller_core │ │ │ │ ├── example_design │ │ │ │ ├── par │ │ │ │ │ └── example_top.ucf │ │ │ │ ├── rtl │ │ │ │ │ ├── example_top.v │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ ├── memc_wrapper.v │ │ │ │ │ └── traffic_gen │ │ │ │ │ │ ├── afifo.v │ │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ │ ├── tg_status.v │ │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ │ └── write_data_path.v │ │ │ │ └── sim │ │ │ │ │ └── functional │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ └── sim_tb_top.v │ │ │ │ └── user_design │ │ │ │ ├── par │ │ │ │ └── lpddr_memory_controller_core.ucf │ │ │ │ ├── rtl │ │ │ │ ├── infrastructure.v │ │ │ │ ├── lpddr_memory_controller_core.v │ │ │ │ ├── mcb_controller │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ └── memc_wrapper.v │ │ │ │ └── sim │ │ │ │ ├── afifo.v │ │ │ │ ├── cmd_gen.v │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ ├── data_prbs_gen.v │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ ├── mcb_flow_control.v │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ ├── memc_tb_top.v │ │ │ │ ├── rd_data_gen.v │ │ │ │ ├── read_data_path.v │ │ │ │ ├── read_posted_fifo.v │ │ │ │ ├── sim_tb_top.v │ │ │ │ ├── sp6_data_gen.v │ │ │ │ ├── tg_status.v │ │ │ │ ├── v6_data_gen.v │ │ │ │ ├── wr_data_gen.v │ │ │ │ └── write_data_path.v │ │ └── lpddr_memory_controller │ │ │ ├── coregen_project │ │ │ └── lpddr_memory_controller │ │ │ │ └── user_design │ │ │ │ ├── par │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ ├── rtl │ │ │ │ ├── infrastructure.v │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ ├── mcb_controller │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ └── memc_wrapper.v │ │ │ │ └── sim │ │ │ │ ├── afifo.v │ │ │ │ ├── cmd_gen.v │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ ├── data_prbs_gen.v │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ ├── mcb_flow_control.v │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ ├── memc_tb_top.v │ │ │ │ ├── rd_data_gen.v │ │ │ │ ├── read_data_path.v │ │ │ │ ├── read_posted_fifo.v │ │ │ │ ├── sim_tb_top.v │ │ │ │ ├── sp6_data_gen.v │ │ │ │ ├── tg_status.v │ │ │ │ ├── v6_data_gen.v │ │ │ │ ├── wr_data_gen.v │ │ │ │ └── write_data_path.v │ │ │ └── user_defined_modules │ │ │ ├── integer_seven_segment_display_controller │ │ │ ├── binary_to_bcd_core │ │ │ │ └── binary_to_bcd_core.v │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ └── seven_segment_display_core │ │ │ │ ├── ring_shift_register.v │ │ │ │ ├── seven_segment_display.v │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ └── tick_generator.v │ │ │ ├── reset_controller │ │ │ └── reset_controller.v │ │ │ ├── top.v │ │ │ ├── uart_core │ │ │ ├── uart_core.ucf │ │ │ ├── uart_core.v │ │ │ ├── uart_rx_core │ │ │ │ ├── uart_rx_core.v │ │ │ │ └── utils │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ └── uart_tx_core │ │ │ │ ├── uart_tx_core.v │ │ │ │ └── utils │ │ │ │ ├── pulse_generator.v │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ ├── user_design │ │ │ ├── par │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ ├── rtl │ │ │ │ ├── infrastructure.v │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ ├── mcb_controller │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ └── memc_wrapper.v │ │ │ └── sim │ │ │ │ ├── afifo.v │ │ │ │ ├── cmd_gen.v │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ ├── data_prbs_gen.v │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ ├── mcb_flow_control.v │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ ├── memc_tb_top.v │ │ │ │ ├── rd_data_gen.v │ │ │ │ ├── read_data_path.v │ │ │ │ ├── read_posted_fifo.v │ │ │ │ ├── sim_tb_top.v │ │ │ │ ├── sp6_data_gen.v │ │ │ │ ├── tg_status.v │ │ │ │ ├── v6_data_gen.v │ │ │ │ ├── wr_data_gen.v │ │ │ │ └── write_data_path.v │ │ │ └── utlis │ │ │ ├── pulse_generator.v │ │ │ └── tick_generator.v │ └── xilinx_ise_project_files │ │ ├── binary_to_bcd_converter │ │ ├── binary_to_12bit_bcd_converter │ │ │ ├── binary_to_12bit_bcd_converter.ucf │ │ │ └── binary_to_12bit_bcd_converter_verilog_modules │ │ │ │ ├── binary_to_12bit_bcd_converter.v │ │ │ │ ├── pulse_generator.v │ │ │ │ ├── ring_shift_register.v │ │ │ │ ├── seven_segment_display.v │ │ │ │ ├── seven_segment_display_controller.v │ │ │ │ └── tick_generator.v │ │ ├── binary_to_12bit_bcd_converter_mark2 │ │ │ ├── binary_to_bcd_converter_mark2_verilog_modules │ │ │ │ ├── binary_to_12bit_bcd_converter.v │ │ │ │ ├── pulse_generator.v │ │ │ │ ├── ring_shift_register.v │ │ │ │ ├── seven_segment_display.v │ │ │ │ ├── seven_segment_display_controller.v │ │ │ │ ├── stimulus.v │ │ │ │ └── tick_generator.v │ │ │ └── stimulus.v │ │ └── binary_to_bcd_converter_mark3 │ │ │ └── user_defined_modules │ │ │ ├── binary_to_bcd_converter.v │ │ │ └── binary_to_bcd_converter_testing.v │ │ ├── debouncing_switch │ │ ├── debouncing_switch.ucf │ │ ├── debouncing_switch_verilog_modules │ │ │ ├── debuoncing_switch.v │ │ │ └── tick_generator.v │ │ └── netgen │ │ │ ├── map │ │ │ └── tick_generator_map.v │ │ │ ├── par │ │ │ └── tick_generator_timesim.v │ │ │ ├── synthesis │ │ │ └── tick_generator_synthesis.v │ │ │ └── translate │ │ │ └── tick_generator_translate.v │ │ ├── integer_seven_segment_display_controller │ │ ├── integer_seven_segment_display_controller_mark1 │ │ │ ├── integer_display_seven_segment_display_verilog_modules │ │ │ │ ├── binary_to_12bit_bcd_converter.v │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ ├── pulse_generator.v │ │ │ │ ├── ring_shift_register.v │ │ │ │ ├── seven_segment_display.v │ │ │ │ ├── seven_segment_display_controller.v │ │ │ │ └── tick_generator.v │ │ │ └── integer_seven_segment_display_controller.ucf │ │ ├── integer_seven_segment_display_controller_mark2 │ │ │ ├── integer_seven_segment_display_controller_mark2.ucf │ │ │ └── integer_seven_segment_display_core_mark2 │ │ │ │ ├── binary_to_12bit_bcd_converter.v │ │ │ │ ├── binary_to_12bit_bcd_converter_mark2.v │ │ │ │ ├── integer_seven_segment_display_controller_mark2.v │ │ │ │ ├── pulse_generator.v │ │ │ │ ├── ring_shift_register.v │ │ │ │ ├── seven_segment_display.v │ │ │ │ ├── seven_segment_display_controller.v │ │ │ │ └── tick_generator.v │ │ └── integer_seven_segment_display_controller_mark3 │ │ │ └── user_defined_modules │ │ │ ├── binary_to_bcd_core │ │ │ └── binary_to_bcd_core.v │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ ├── reset_controller │ │ │ └── reset_controller.v │ │ │ └── seven_segment_display_core │ │ │ ├── ring_shift_register.v │ │ │ ├── seven_segment_display.v │ │ │ ├── seven_segment_display_core.v │ │ │ └── tick_generator.v │ │ ├── lpddr_memory_controller │ │ ├── lpddr_memory_controller │ │ │ ├── coregen_project │ │ │ │ └── lpddr_memory_controller │ │ │ │ │ └── user_design │ │ │ │ │ ├── par │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ │ ├── rtl │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ └── memc_wrapper.v │ │ │ │ │ └── sim │ │ │ │ │ ├── afifo.v │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ ├── tg_status.v │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ └── write_data_path.v │ │ │ └── user_defined_modules │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ └── seven_segment_display_core │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ └── tick_generator.v │ │ │ │ ├── reset_controller │ │ │ │ └── reset_controller.v │ │ │ │ ├── top.v │ │ │ │ ├── uart_core │ │ │ │ ├── uart_core.ucf │ │ │ │ ├── uart_core.v │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ ├── user_design │ │ │ │ ├── par │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ ├── rtl │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ └── memc_wrapper.v │ │ │ │ └── sim │ │ │ │ │ ├── afifo.v │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ ├── tg_status.v │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ └── write_data_path.v │ │ │ │ └── utlis │ │ │ │ ├── pulse_generator.v │ │ │ │ └── tick_generator.v │ │ ├── lpddr_memory_controller_mark2 │ │ │ ├── coregen_project │ │ │ │ └── lpddr_memory_controller │ │ │ │ │ └── user_design │ │ │ │ │ ├── par │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ │ ├── rtl │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ └── memc_wrapper.v │ │ │ │ │ └── sim │ │ │ │ │ ├── afifo.v │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ ├── tg_status.v │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ └── write_data_path.v │ │ │ └── user_defined_modules │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ └── seven_segment_display_core │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ └── tick_generator.v │ │ │ │ ├── lpddr_memory_controller.ucf │ │ │ │ ├── reset_controller │ │ │ │ └── reset_controller.v │ │ │ │ ├── top.v │ │ │ │ ├── traffic_generator │ │ │ │ ├── my_fifo.v │ │ │ │ ├── pulse_generator.v │ │ │ │ ├── traffic_generator.v │ │ │ │ ├── traffic_generator_mark2.v │ │ │ │ ├── traffic_generator_mark2_test.v │ │ │ │ └── traffic_generator_test.v │ │ │ │ ├── uart_core │ │ │ │ ├── uart_core.ucf │ │ │ │ ├── uart_core.v │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ ├── user_design │ │ │ │ ├── par │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ ├── rtl │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ └── memc_wrapper.v │ │ │ │ └── sim │ │ │ │ │ ├── afifo.v │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ ├── tg_status.v │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ └── write_data_path.v │ │ │ │ └── utlis │ │ │ │ ├── pulse_generator.v │ │ │ │ └── tick_generator.v │ │ ├── lpddr_memory_controller_mark3 │ │ │ ├── coregen_project │ │ │ │ └── lpddr_memory_controller │ │ │ │ │ └── user_design │ │ │ │ │ ├── par │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ │ ├── rtl │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ └── memc_wrapper.v │ │ │ │ │ └── sim │ │ │ │ │ ├── afifo.v │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ ├── tg_status.v │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ └── write_data_path.v │ │ │ └── user_defined_modules │ │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ └── seven_segment_display_core │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ └── tick_generator.v │ │ │ │ ├── lpddr_memory_controller.ucf │ │ │ │ ├── reset_controller │ │ │ │ └── reset_controller.v │ │ │ │ ├── top.v │ │ │ │ ├── traffic_generator │ │ │ │ ├── my_fifo.v │ │ │ │ ├── pulse_generator.v │ │ │ │ ├── traffic_generator.v │ │ │ │ ├── traffic_generator_mark2.v │ │ │ │ ├── traffic_generator_mark2_test.v │ │ │ │ └── traffic_generator_test.v │ │ │ │ ├── uart_core │ │ │ │ ├── uart_core.ucf │ │ │ │ ├── uart_core.v │ │ │ │ ├── uart_rx_core │ │ │ │ │ ├── uart_rx_core.v │ │ │ │ │ └── utils │ │ │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ │ └── uart_tx_core │ │ │ │ │ ├── uart_tx_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── pulse_generator.v │ │ │ │ │ └── tx_baudrate_tick_generator.v │ │ │ │ ├── user_design │ │ │ │ ├── par │ │ │ │ │ └── lpddr_memory_controller.ucf │ │ │ │ ├── rtl │ │ │ │ │ ├── infrastructure.v │ │ │ │ │ ├── lpddr_memory_controller.v │ │ │ │ │ ├── mcb_controller │ │ │ │ │ │ ├── iodrp_controller.v │ │ │ │ │ │ ├── iodrp_mcb_controller.v │ │ │ │ │ │ ├── mcb_raw_wrapper.v │ │ │ │ │ │ ├── mcb_soft_calibration.v │ │ │ │ │ │ ├── mcb_soft_calibration_top.v │ │ │ │ │ │ └── mcb_ui_top.v │ │ │ │ │ └── memc_wrapper.v │ │ │ │ └── sim │ │ │ │ │ ├── afifo.v │ │ │ │ │ ├── cmd_gen.v │ │ │ │ │ ├── cmd_prbs_gen.v │ │ │ │ │ ├── data_prbs_gen.v │ │ │ │ │ ├── init_mem_pattern_ctr.v │ │ │ │ │ ├── lpddr_model_c3.v │ │ │ │ │ ├── mcb_flow_control.v │ │ │ │ │ ├── mcb_traffic_gen.v │ │ │ │ │ ├── memc_tb_top.v │ │ │ │ │ ├── rd_data_gen.v │ │ │ │ │ ├── read_data_path.v │ │ │ │ │ ├── read_posted_fifo.v │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ ├── sp6_data_gen.v │ │ │ │ │ ├── tg_status.v │ │ │ │ │ ├── v6_data_gen.v │ │ │ │ │ ├── wr_data_gen.v │ │ │ │ │ └── write_data_path.v │ │ │ │ └── utlis │ │ │ │ ├── pulse_generator.v │ │ │ │ └── tick_generator.v │ │ └── lpddr_memory_controller_traffic_generator │ │ │ └── user_defined_modules │ │ │ ├── fifo_mark1.v │ │ │ └── traffic_generator_mark1.v │ │ ├── mimas_v2_blinky │ │ ├── blinky.ucf │ │ └── blinky.v │ │ ├── reset_controller │ │ ├── reset_controller.ucf │ │ └── reset_controller_verilog_modules │ │ │ └── reset_controller.v │ │ ├── seven_segment_display │ │ ├── ring_shift_register.v │ │ ├── seven_segment_display.ucf │ │ ├── seven_segment_display.v │ │ ├── seven_segment_display_controller.v │ │ ├── seven_segment_display_driver.v │ │ └── tick_generator.v │ │ ├── seven_segment_display_controller │ │ └── seven_segment_display_controller.ucf │ │ ├── seven_segment_display_core │ │ ├── seven_segment_display_core.ucf │ │ └── verilog_modules │ │ │ ├── ring_shift_register.v │ │ │ ├── seven_segment_display.v │ │ │ ├── seven_segment_display_core.v │ │ │ └── tick_generator.v │ │ ├── sigmoid_mark3 │ │ └── user_defined_modules │ │ │ ├── reset_controller │ │ │ └── reset_controller.v │ │ │ ├── sigmoid │ │ │ ├── sigmoid.v │ │ │ ├── sigmoid_tb.v │ │ │ └── utils │ │ │ │ ├── VG_ROM_8x18.v │ │ │ │ └── sigmoid_combinational.v │ │ │ ├── top.v │ │ │ ├── top_tb.v │ │ │ ├── top_test.v │ │ │ ├── top_test_tb.v │ │ │ └── uart_core │ │ │ ├── uart_core.ucf │ │ │ ├── uart_core.v │ │ │ ├── uart_rx_core │ │ │ ├── uart_rx_core.v │ │ │ └── utils │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ └── uart_tx_core │ │ │ ├── uart_tx_core.v │ │ │ └── utils │ │ │ ├── pulse_generator.v │ │ │ └── tx_baudrate_tick_generator.v │ │ ├── sigmoid_mark5 │ │ └── user_defined_modules │ │ │ ├── reset_controller │ │ │ └── reset_controller.v │ │ │ ├── sigmoid.ucf │ │ │ ├── sigmoid │ │ │ ├── sigmoid.v │ │ │ ├── sigmoid_tb.v │ │ │ └── utils │ │ │ │ ├── VG_ROM_8x18.v │ │ │ │ └── sigmoid_combinational.v │ │ │ ├── top.v │ │ │ ├── top_tb.v │ │ │ ├── top_test.v │ │ │ ├── top_test_tb.v │ │ │ └── uart_core │ │ │ ├── uart_core.ucf │ │ │ ├── uart_core.v │ │ │ ├── uart_rx_core │ │ │ ├── uart_rx_core.v │ │ │ └── utils │ │ │ │ └── rx_baudrate_tick_generator.v │ │ │ └── uart_tx_core │ │ │ ├── uart_tx_core.v │ │ │ ├── uart_tx_core_test.v │ │ │ ├── uart_tx_core_test_tb.v │ │ │ └── utils │ │ │ ├── my_fifo.v │ │ │ ├── pulse_generator.v │ │ │ └── tx_baudrate_tick_generator.v │ │ ├── uart │ │ ├── 03_uart_receiver_mark3 │ │ │ ├── rx_baudrate_tick_generator.v │ │ │ ├── uart_rx_core.v │ │ │ └── uart_rx_test.v │ │ ├── 04_uart_receiver_ssd_testing │ │ │ ├── integer_seven_segment_display_controller │ │ │ │ ├── binary_to_bcd_core │ │ │ │ │ └── binary_to_bcd_core.v │ │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ │ └── seven_segment_display_core │ │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ │ └── utils │ │ │ │ │ ├── ring_shift_register.v │ │ │ │ │ ├── seven_segment_display.v │ │ │ │ │ └── tick_generator.v │ │ │ ├── reset_controller │ │ │ │ └── reset_controller.v │ │ │ ├── uart_receiver_ssd_test.v │ │ │ └── uart_rx_core │ │ │ │ ├── rx_baudrate_tick_generator.v │ │ │ │ └── uart_rx_core.v │ │ └── uart_rx_ssd_test │ │ │ └── user_defined_modules │ │ │ ├── integer_seven_segment_display_controller │ │ │ ├── binary_to_bcd_core │ │ │ │ └── binary_to_bcd_core.v │ │ │ ├── integer_seven_segment_display_controller.ucf │ │ │ ├── integer_seven_segment_display_controller.v │ │ │ ├── integer_seven_segment_display_controller_test.v │ │ │ └── seven_segment_display_core │ │ │ │ ├── seven_segment_display_core.v │ │ │ │ └── utils │ │ │ │ ├── ring_shift_register.v │ │ │ │ ├── seven_segment_display.v │ │ │ │ └── tick_generator.v │ │ │ ├── reset_controller │ │ │ └── reset_controller.v │ │ │ ├── uart_receiver_ssd_test.ucf │ │ │ ├── uart_receiver_ssd_test.v │ │ │ └── uart_rx_core │ │ │ ├── rx_baudrate_tick_generator.v │ │ │ └── uart_rx_core.v │ │ └── uart_receiver_verilog_modules │ │ ├── counter.v │ │ ├── pulse_generator.v │ │ ├── sampling_tick_generator.v │ │ ├── serial_input_parallel_output_shift_register.v │ │ └── uart_receiver.v ├── rana_fpga_working_dirctory │ ├── CLA │ │ ├── CLA.ucf │ │ ├── CLA.v │ │ └── testbench.v │ ├── DSP │ │ └── mac.v │ ├── FourBitAdder │ │ ├── FourBitFullAdder.ucf │ │ ├── FourBitFullAdder.v │ │ ├── Testbench.v │ │ ├── adder.v │ │ ├── ipcore_dir │ │ │ ├── try.v │ │ │ └── try_arwz.ucf │ │ ├── try.v │ │ └── try_arwz.ucf │ ├── FullAdder1Bit │ │ ├── FullAdder1Bit.ucf │ │ ├── FullAdder1Bit.v │ │ ├── FullAdder1Bit_PlanAhead │ │ │ └── FullAdder1Bit_PlanAhead.runs │ │ │ │ └── impl_1 │ │ │ │ └── FullAdder1Bit.ucf │ │ ├── TestBench.v │ │ ├── ipcore_dir │ │ │ ├── ip_core.v │ │ │ ├── ip_core │ │ │ │ └── example_design │ │ │ │ │ └── ip_core_exdes.ucf │ │ │ └── try │ │ │ │ ├── example_design │ │ │ │ ├── par │ │ │ │ │ └── try.ucf │ │ │ │ ├── rtl │ │ │ │ │ ├── try.v │ │ │ │ │ ├── try_addr_gen_0.v │ │ │ │ │ ├── try_cal_ctl.v │ │ │ │ │ ├── try_cal_top.v │ │ │ │ │ ├── try_clk_dcm.v │ │ │ │ │ ├── try_cmd_fsm_0.v │ │ │ │ │ ├── try_cmp_data_0.v │ │ │ │ │ ├── try_controller_0.v │ │ │ │ │ ├── try_controller_iobs_0.v │ │ │ │ │ ├── try_data_gen_0.v │ │ │ │ │ ├── try_data_path_0.v │ │ │ │ │ ├── try_data_path_iobs_0.v │ │ │ │ │ ├── try_data_read_0.v │ │ │ │ │ ├── try_data_read_controller_0.v │ │ │ │ │ ├── try_data_write_0.v │ │ │ │ │ ├── try_dqs_delay_0.v │ │ │ │ │ ├── try_fifo_0_wr_en_0.v │ │ │ │ │ ├── try_fifo_1_wr_en_0.v │ │ │ │ │ ├── try_infrastructure.v │ │ │ │ │ ├── try_infrastructure_iobs_0.v │ │ │ │ │ ├── try_infrastructure_top.v │ │ │ │ │ ├── try_iobs_0.v │ │ │ │ │ ├── try_main_0.v │ │ │ │ │ ├── try_parameters_0.v │ │ │ │ │ ├── try_ram8d_0.v │ │ │ │ │ ├── try_rd_gray_cntr.v │ │ │ │ │ ├── try_s3_dm_iob.v │ │ │ │ │ ├── try_s3_dq_iob.v │ │ │ │ │ ├── try_s3_dqs_iob.v │ │ │ │ │ ├── try_tap_dly.v │ │ │ │ │ ├── try_test_bench_0.v │ │ │ │ │ ├── try_top_0.v │ │ │ │ │ └── try_wr_gray_cntr.v │ │ │ │ └── sim │ │ │ │ │ ├── ddr_model.v │ │ │ │ │ ├── sim_tb_top.v │ │ │ │ │ └── wiredly.v │ │ │ │ └── user_design │ │ │ │ ├── par │ │ │ │ └── try.ucf │ │ │ │ ├── rtl │ │ │ │ ├── try.v │ │ │ │ ├── try_cal_ctl.v │ │ │ │ ├── try_cal_top.v │ │ │ │ ├── try_clk_dcm.v │ │ │ │ ├── try_controller_0.v │ │ │ │ ├── try_controller_iobs_0.v │ │ │ │ ├── try_data_path_0.v │ │ │ │ ├── try_data_path_iobs_0.v │ │ │ │ ├── try_data_read_0.v │ │ │ │ ├── try_data_read_controller_0.v │ │ │ │ ├── try_data_write_0.v │ │ │ │ ├── try_dqs_delay_0.v │ │ │ │ ├── try_fifo_0_wr_en_0.v │ │ │ │ ├── try_fifo_1_wr_en_0.v │ │ │ │ ├── try_infrastructure.v │ │ │ │ ├── try_infrastructure_iobs_0.v │ │ │ │ ├── try_infrastructure_top.v │ │ │ │ ├── try_iobs_0.v │ │ │ │ ├── try_parameters_0.v │ │ │ │ ├── try_ram8d_0.v │ │ │ │ ├── try_rd_gray_cntr.v │ │ │ │ ├── try_s3_dm_iob.v │ │ │ │ ├── try_s3_dq_iob.v │ │ │ │ ├── try_s3_dqs_iob.v │ │ │ │ ├── try_tap_dly.v │ │ │ │ ├── try_top_0.v │ │ │ │ └── try_wr_gray_cntr.v │ │ │ │ └── sim │ │ │ │ ├── ddr_model.v │ │ │ │ ├── sim_tb_top.v │ │ │ │ ├── try_addr_gen_0.v │ │ │ │ ├── try_cmd_fsm_0.v │ │ │ │ ├── try_cmp_data_0.v │ │ │ │ ├── try_data_gen_0.v │ │ │ │ ├── try_test_bench_0.v │ │ │ │ └── wiredly.v │ │ └── netgen │ │ │ └── translate │ │ │ └── FullAdder1Bit_translate.v │ ├── Multistages │ │ ├── Multistages.ucf │ │ ├── Multistages.v │ │ ├── netgen │ │ │ └── map │ │ │ │ └── Multistages_map.v │ │ └── test.v │ ├── OR │ │ ├── ThreeInputExorGate.v │ │ ├── ThreeInputOrGate.ucf │ │ ├── ThreeInputOrGate.v │ │ ├── stimulus.v │ │ └── stimulus2.v │ ├── SingleStage │ │ ├── SingleStage.v │ │ └── test.v │ ├── all primitive test projects │ │ ├── clock_gen │ │ │ ├── clock_.ucf │ │ │ ├── clock_.v │ │ │ ├── ipcore_dir │ │ │ │ ├── clk_ip_core.ucf │ │ │ │ ├── clk_ip_core.v │ │ │ │ └── clk_ip_core │ │ │ │ │ ├── example_design │ │ │ │ │ ├── clk_ip_core_exdes.ucf │ │ │ │ │ └── clk_ip_core_exdes.v │ │ │ │ │ └── simulation │ │ │ │ │ ├── clk_ip_core_tb.v │ │ │ │ │ └── timing │ │ │ │ │ └── clk_ip_core_tb.v │ │ │ └── netgen │ │ │ │ └── translate │ │ │ │ └── clock__translate.v │ │ ├── multiplxer │ │ │ └── logic_implemtation.v │ │ ├── read_write_reg │ │ │ └── reg_file.v │ │ ├── regular_sequential_ckt │ │ │ └── D_FF.v │ │ └── shift_reg │ │ │ └── shift_reg.v │ ├── dsp_slice_test │ │ ├── fixed_point_multi │ │ │ ├── fixed_point.v │ │ │ ├── ipcore_dir │ │ │ │ └── fixed_point_core.v │ │ │ └── testbench.v │ │ └── kishores_dsp_slice_test │ │ │ ├── dsp_test.v │ │ │ └── dsp_test_tb.v │ ├── project_1 │ │ ├── project_1.runs │ │ │ └── impl_1 │ │ │ │ ├── .constrs │ │ │ │ └── bft_full.ucf │ │ │ │ └── bft.ucf │ │ └── project_1.srcs │ │ │ ├── constrs_1 │ │ │ └── imports │ │ │ │ └── Sources │ │ │ │ └── bft.ucf │ │ │ ├── constrs_2 │ │ │ └── imports │ │ │ │ └── Sources │ │ │ │ └── bft_full.ucf │ │ │ ├── sim_1 │ │ │ └── imports │ │ │ │ └── hdl │ │ │ │ └── bft_tb.v │ │ │ └── sources_1 │ │ │ └── imports │ │ │ └── hdl │ │ │ ├── FifoBuffer.v │ │ │ └── async_fifo.v │ ├── test │ │ ├── Multipler1818.ucf │ │ ├── ipcore_dir │ │ │ └── test.v │ │ ├── test_tb.v │ │ ├── testbench.ucf │ │ ├── testbench.v │ │ └── testbench_multipler.v │ ├── try │ │ ├── basis.ucf │ │ ├── basis2.ucf │ │ ├── basys.ucf │ │ └── or_gate.v │ ├── uart_transmitter_ciletti_mark2 │ │ └── user defined modules │ │ │ ├── reset_controller.v │ │ │ ├── tick_generator.v │ │ │ ├── transmitter.v │ │ │ └── transmitter_test.v │ ├── uart_transmitter_core │ │ ├── baudrate_generator.v │ │ ├── pulse_generator.v │ │ ├── stimulus.v │ │ ├── tick_generator.v │ │ ├── uart_transmitter_core.v │ │ ├── uart_transmitter_core_test.ucf │ │ ├── uart_transmitter_core_test.v │ │ └── uart_transmitter_core_verilog_modules │ │ │ ├── baudrate_generator.v │ │ │ ├── pulse_generator.v │ │ │ ├── stimulus.v │ │ │ ├── tick_generator.v │ │ │ ├── uart_transmitter_core.v │ │ │ └── uart_transmitter_core_test.v │ ├── uart_transmitter_core_mark2 │ │ └── uart_transmitter_core_verilog_modules │ │ │ ├── baudrate_generator.v │ │ │ ├── final_testbenches │ │ │ ├── baudrate_tick_generator_tb.v │ │ │ ├── pulse_generator_tb.v │ │ │ ├── tick_generator_tb.v │ │ │ └── uart_transmitter_core_tb.v │ │ │ ├── pulse_generator.v │ │ │ ├── stimulus.v │ │ │ ├── tick_generator.v │ │ │ ├── uart_transmitter_core.v │ │ │ ├── uart_transmitter_core_mark2.ucf │ │ │ └── uart_transmitter_core_test.v │ └── uart_transmitter_mark6_self_implemented │ │ └── user_defined_modules │ │ ├── pulse_generator.v │ │ ├── reset_controller.v │ │ ├── tick_generator.v │ │ ├── transmitter_core.ucf │ │ ├── transmitter_core.v │ │ ├── transmitter_core_test.v │ │ └── tx_baudrate_tick_generator.v └── verilog_working_directory │ └── src │ └── FPGA_prototyping_by_verilog_basics │ └── 02_blinky.v ├── README.md ├── image_processing ├── .gitignore ├── C_library_for_image_processing │ ├── .ipynb_checkpoints │ │ └── C library for image processing-checkpoint.ipynb │ ├── 01 - Introduction to python ctypes library, and compilation of C code │ │ ├── .ipynb_checkpoints │ │ │ └── 1 - Introduction to python ctypes library, and compilation of C code-checkpoint.ipynb │ │ ├── 1 - Introduction to python ctypes library, and compilation of C code.ipynb │ │ ├── _convolution.py │ │ ├── convolution.c │ │ ├── convolution.o │ │ ├── libconvolution.so │ │ └── locate_file.py │ ├── 02 - Basics of writing C code and accessing C functions from python │ │ ├── .ipynb_checkpoints │ │ │ └── 2 - Basics of writing C code and accessing C functions from python-checkpoint.ipynb │ │ ├── 2 - Basics of writing C code and accessing C functions from python.ipynb │ │ ├── _convolution.py │ │ ├── convolution.c │ │ ├── convolution.o │ │ ├── libconvolution.so │ │ └── locate_file.py │ ├── 03 - Array basics and Array passing from python to C │ │ ├── .ipynb_checkpoints │ │ │ └── 3 - Array basics and Array passing from python to C-checkpoint.ipynb │ │ ├── 3 - Array basics and Array passing from python to C.ipynb │ │ ├── _convolution.py │ │ ├── convolution.c │ │ ├── convolution.o │ │ ├── libconvolution.so │ │ ├── locate_file.py │ │ └── sample_image_3.png │ ├── 04 - Convolution implemented as a C function and wrapper in python │ │ ├── .ipynb_checkpoints │ │ │ └── 4 - Convolution implemented as a C function and wrapper in python-checkpoint.ipynb │ │ ├── 4 - Convolution implemented as a C function and wrapper in python.ipynb │ │ ├── convolution.c │ │ ├── convolution.o │ │ ├── convolution.so │ │ ├── debug.py │ │ ├── image_processing.py │ │ ├── libconvolution.py │ │ ├── locate_file.py │ │ └── sample_image_3.png │ ├── 05 - Implementing Gaussian filter with variable standard deviation │ │ ├── .ipynb_checkpoints │ │ │ └── 5 - Implementing Gaussian filter with variable standard deviation-checkpoint.ipynb │ │ ├── 5 - Implementing Gaussian filter with variable standard deviation.ipynb │ │ ├── convolution.c │ │ ├── convolution.o │ │ ├── convolution.so │ │ ├── gaussian.py │ │ ├── image_processing.py │ │ ├── libconvolution.py │ │ ├── locate_file.py │ │ └── sample_image_3.png │ ├── 06 - implementing Sobel operator for canny edge detection │ │ ├── .ipynb_checkpoints │ │ │ └── 6 - implementing Sobel operator for canny edge detection-checkpoint.ipynb │ │ ├── 6 - implementing Sobel operator for canny edge detection.ipynb │ │ ├── convolution.c │ │ ├── convolution.o │ │ ├── convolution.so │ │ ├── debug.py │ │ ├── gaussian.py │ │ ├── image_handling.py │ │ ├── libconvolution.py │ │ ├── locate_file.py │ │ ├── sample_images │ │ │ ├── sample_image_1.png │ │ │ ├── sample_image_2.png │ │ │ ├── sample_image_3.png │ │ │ └── sample_image_4.png │ │ └── setup.py │ ├── 07 - Array passing and returning between C and Python │ │ ├── .ipynb_checkpoints │ │ │ └── 7 - Array passing and returning between C and Python-checkpoint.ipynb │ │ ├── 7 - Array passing and returning between C and Python.ipynb │ │ ├── debug.py │ │ ├── gaussian.py │ │ ├── image_handling.py │ │ ├── image_processing.c │ │ ├── image_processing.o │ │ ├── image_processing.so │ │ ├── lib_image_processing.py │ │ ├── locate_file.py │ │ ├── sample_images │ │ │ ├── sample_image_1.png │ │ │ ├── sample_image_2.png │ │ │ ├── sample_image_3.png │ │ │ └── sample_image_4.png │ │ └── setup.py │ ├── 08 - pointers to pointers and implementation of non maximum supression algorithm │ │ ├── .ipynb_checkpoints │ │ │ ├── 8 - pointers to pointers and implementation of non maximum supression algorithm-checkpoint.ipynb │ │ │ └── 8 - pointers to pointers, and implementation of non maximum supression algorithm-checkpoint.ipynb │ │ ├── 8 - pointers to pointers and implementation of non maximum supression algorithm.ipynb │ │ ├── debug.py │ │ ├── gaussian.py │ │ ├── image_handling.py │ │ ├── image_processing.c │ │ ├── image_processing.o │ │ ├── image_processing.so │ │ ├── lib_image_processing.py │ │ ├── locate_file.py │ │ ├── sample_images │ │ │ ├── sample_image_1.png │ │ │ ├── sample_image_2.png │ │ │ ├── sample_image_3.png │ │ │ ├── sample_image_4.png │ │ │ ├── sample_image_5.png │ │ │ ├── sample_image_6.png │ │ │ ├── sample_image_7.png │ │ │ ├── sample_image_8.png │ │ │ └── sample_image_9.png │ │ └── setup.py │ ├── 09 - morphological image processing │ │ ├── .ipynb_checkpoints │ │ │ ├── 7 - improving on the convolution code and adding code for nonmaximum supression-checkpoint.ipynb │ │ │ ├── 8 - improving on the convolution code and adding code for nonmaximum supression-checkpoint.ipynb │ │ │ └── 9 - morphological image processing-checkpoint.ipynb │ │ ├── 9 - morphological image processing.ipynb │ │ ├── debug.py │ │ ├── gaussian.py │ │ ├── image_handling.py │ │ ├── image_processing.c │ │ ├── image_processing.o │ │ ├── image_processing.so │ │ ├── lib_image_processing.py │ │ ├── locate_file.py │ │ ├── sample_images │ │ │ ├── sample_image_1.png │ │ │ ├── sample_image_2.png │ │ │ ├── sample_image_3.png │ │ │ ├── sample_image_4.png │ │ │ ├── sample_image_5.png │ │ │ ├── sample_image_6.png │ │ │ ├── sample_image_7.png │ │ │ ├── sample_image_8.png │ │ │ └── sample_image_9.png │ │ └── setup.py │ └── 10 - plotting 3D graphs │ │ ├── .ipynb_checkpoints │ │ └── 10 - plotting graphs-checkpoint.ipynb │ │ └── 10 - plotting graphs.ipynb ├── color_to_grayscale.py ├── helloworld.c ├── image_processing.py ├── image_processing.pyc ├── image_processing_mark2.py ├── ipython notebooks │ ├── .ipynb_checkpoints │ │ ├── C python binding-checkpoint.ipynb │ │ └── image_processing_mark2-checkpoint.ipynb │ ├── c_python_binding_test.c │ ├── image_processing_mark1 │ │ └── image_processing.ipynb │ ├── image_processing_mark2 │ │ ├── .ipynb_checkpoints │ │ │ └── image_processing_mark2-checkpoint.ipynb │ │ └── image_processing_mark2.ipynb │ ├── image_processing_mark3 │ │ ├── .ipynb_checkpoints │ │ │ └── image_processing_mark3-checkpoint.ipynb │ │ ├── _convolution.py │ │ ├── _convolution.pyc │ │ ├── convolution.c │ │ ├── convolution.o │ │ ├── convolution.so │ │ └── image_processing_mark3.ipynb │ ├── processed images │ │ ├── smoothened_image.bmp │ │ ├── working copy.bmp │ │ └── working_copy.bmp │ ├── python C extension testing │ │ ├── .ipynb_checkpoints │ │ │ └── C python binding-checkpoint.ipynb │ │ ├── mark1 │ │ │ ├── .ipynb_checkpoints │ │ │ │ ├── C python binding-checkpoint.ipynb │ │ │ │ └── Untitled-checkpoint.ipynb │ │ │ ├── C python binding.ipynb │ │ │ ├── __pycache__ │ │ │ │ ├── _helloworld.cpython-34.pyc │ │ │ │ └── superduper.cpython-34.pyc │ │ │ ├── _helloworld.py │ │ │ ├── helloworld.c │ │ │ ├── helloworld.o │ │ │ ├── helloworld.so │ │ │ └── superduper.py │ │ ├── mark2 │ │ │ ├── .ipynb_checkpoints │ │ │ │ ├── C python binding mark2-checkpoint.ipynb │ │ │ │ └── C python binding mark3-checkpoint.ipynb │ │ │ ├── C python binding mark2.ipynb │ │ │ ├── __pycache__ │ │ │ │ └── _test.cpython-34.pyc │ │ │ ├── _test.py │ │ │ ├── _test.pyc │ │ │ ├── default.csv │ │ │ ├── test.c │ │ │ ├── test.csv │ │ │ ├── test.o │ │ │ └── test.so │ │ └── mark3 │ │ │ ├── .ipynb_checkpoints │ │ │ └── C python binding mark3-checkpoint.ipynb │ │ │ ├── C python binding mark3.ipynb │ │ │ ├── _test.py │ │ │ ├── _test.pyc │ │ │ ├── test.c │ │ │ ├── test.csv │ │ │ ├── test.o │ │ │ └── test.so │ ├── rana.txt │ └── sample images │ │ ├── sample_image.png │ │ ├── sample_image_2.png │ │ ├── sample_image_3.png │ │ ├── sample_image_4.png │ │ ├── sample_image_5.png │ │ ├── sample_image_6.png │ │ ├── sample_image_7.png │ │ └── sample_image_8.png ├── morphological image processing │ ├── .ipynb_checkpoints │ │ └── Morphological image processing-checkpoint.ipynb │ └── Morphological image processing.ipynb ├── rgb_to_bnw.c ├── rgb_to_bnw_mark2.py ├── rgb_to_bw.py └── setup.py ├── neural_networks ├── Rana_codes │ ├── .ipynb_checkpoints │ │ ├── My_analysis-checkpoint.ipynb │ │ └── Neural Implementation-checkpoint.ipynb │ └── Analysis.py └── other image sets │ ├── letter-recognition.data │ ├── letter-recognition.data.Z │ └── stanford image dataset │ ├── letter.data │ ├── letter.data.gz │ └── letter.names.txt ├── project report ├── .ipynb_checkpoints │ ├── Project Report-checkpoint.ipynb │ └── Untitled-checkpoint.ipynb ├── images │ ├── 2d_gaussian.png │ ├── after_erosion.png │ ├── after_non_maximum_supression.png │ ├── angle.png │ ├── before_erosion.png │ ├── before_non_maximum_supression.png │ ├── horizontal_and_vertical.png │ ├── horizontal_edge_detection.png │ ├── impulse_response_of_gaussian.png │ ├── log.png │ ├── log_1.png │ ├── log_2.png │ ├── log_threshold.png │ ├── magnitude.png │ ├── mean_filter_after.png │ ├── original_image.png │ ├── sobel_x.png │ ├── sobel_y.png │ └── vertical_edge_detection.png ├── project_report.aux ├── project_report.fdb_latexmk ├── project_report.log ├── project_report.out ├── project_report.pdf ├── project_report.synctex.gz └── project_report.tex ├── receipts └── NumatoLab │ └── NumatoLab │ └── ipxact │ └── MimasV2 │ └── data │ └── default.ucf └── smoothened_image.bmp /.gitignore: -------------------------------------------------------------------------------- 1 | */references/ 2 | neural_networks/other_codes 3 | neural_networks/ironstein_codes/data 4 | technical_paper/ 5 | FPGA/references 6 | 7 | # ------ rana ------------ 8 | FPGA/rana_fpga_working_dirctory 9 | * 10 | !*/ 11 | !*.v 12 | !*.ucf 13 | 14 | # ———— ironstein ————— 15 | FPGA/xilinx_ise_project_files/ 16 | * 17 | !*/ 18 | !*.v 19 | !*.ucf 20 | receipts/ 21 | technical_paper/ 22 | 23 | # ------ dhr ------- 24 | FPGA/dhr_fpga_working_dirctory 25 | * 26 | !*/ 27 | !*.v 28 | !*.ucf 29 | 30 | #————————————————————- 31 | *.pyc -------------------------------------------------------------------------------- /.ipynb_checkpoints/Project Report-checkpoint.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [], 3 | "metadata": {}, 4 | "nbformat": 4, 5 | "nbformat_minor": 0 6 | } 7 | -------------------------------------------------------------------------------- /FPGA/dhr_dir/try/hello_world/hello_world.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:55:57 03/05/2016 7 | // Design Name: 8 | // Module Name: hello_world 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module hello_world( 22 | ); 23 | 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /FPGA/dhr_dir/try/mac_module_testing/user_defined_modules/mac_module_stimulus.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/dhr_dir/try/mac_stimulus_test/user_defined_modules/mac_module_stimulus.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/dhr_dir/try/sch_try/user_defined_modules/mac_module_stimulus.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/dhr_dir/try/tx/uart_tx_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | 6 | // RESET CONNECTIONS 7 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 8 | NET RESET LOC = P15; 9 | 10 | // OTHER SIGNALS 11 | NET BUSY LOC = P16; -------------------------------------------------------------------------------- /FPGA/dhr_dir/try/tx/user_defined_modules/utils/tx_tick_generator.v: -------------------------------------------------------------------------------- 1 | module tx_tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | input wire reset, 7 | output reg tick 8 | ); 9 | 10 | reg [32:0] count; 11 | localparam [32:0] count_threshold = tick_time * frequency; 12 | 13 | initial begin 14 | tick = 1'b0; 15 | count = 32'b0; 16 | end 17 | 18 | always @(posedge(clk),posedge(reset)) begin 19 | if(reset) begin 20 | count = 32'b0; 21 | tick = 1'b0; 22 | end else begin 23 | if(count == count_threshold) begin 24 | count = 32'b0; 25 | tick = 1'b1; 26 | end else begin 27 | tick = 1'b0; 28 | count = count + 1; 29 | end 30 | end 31 | end 32 | 33 | endmodule -------------------------------------------------------------------------------- /FPGA/dhr_dir/try/tx/user_defined_modules/utils/uart_tx_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | 6 | // RESET CONNECTIONS 7 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 8 | NET RESET LOC = P15; 9 | 10 | // OTHER SIGNALS 11 | NET BUSY LOC = P16; -------------------------------------------------------------------------------- /FPGA/dhr_dir/try/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/dhr_dir/working projects with test signals/mac_module/mac_module_stimulus.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/final_working_projects/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/final_working_projects/mac_module/mac_module_stimulus.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/final_working_projects/seven_segment_display_controller/utils/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, // in seconds 3 | parameter frequency = 32'd100000 // in KHz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/final_working_projects/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/final_working_projects/uart_tx_core/utils/tx_tick_generator.v: -------------------------------------------------------------------------------- 1 | module tx_tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | input wire reset, 7 | output reg tick, 8 | ); 9 | 10 | reg [32:0] count; 11 | localparam [32:0] count_threshold = tick_time * frequency / 2; 12 | 13 | initial begin 14 | tick = 1'b0; 15 | count = 32'b0; 16 | end 17 | 18 | always @(posedge(clk),posedge(reset)) begin 19 | if(reset) begin 20 | count = 32'b0; 21 | tick = 1'b0; 22 | end else begin 23 | if(count == count_threshold) begin 24 | count = 32'b0; 25 | tick = 1'b1; 26 | end else begin 27 | tick = 1'b0; 28 | count = count + 1; 29 | end 30 | end 31 | end 32 | 33 | endmodule -------------------------------------------------------------------------------- /FPGA/final_working_projects/uart_tx_core/utils/uart_tx_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | 6 | // RESET CONNECTIONS 7 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 8 | NET RESET LOC = P15; 9 | 10 | // OTHER SIGNALS 11 | NET BUSY LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/basics/02_blinky.ucf: -------------------------------------------------------------------------------- 1 | NET "LED1" LOC = T18; 2 | NET "LED2" LOC = T17; 3 | NET "LED3" LOC = U18; 4 | NET "CLK" LOC = V10 | IOSTANDARD = LVCMOS22 | PERIOD = 100MHz; //100 MHz clock signal 5 | 6 | #------ DISABLING SEVEN SEGMENT DISPLAY ------- 7 | NET "A2" PULLUP; 8 | NET "A2" LOC = A2; 9 | NET "B2" PULLUP; 10 | NET "B2" LOC = B2; 11 | NET "B3" PULLUP; 12 | NET "B3" LOC = B3; 13 | //-------------------------------------------- 14 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/basics/03_RTL_basics.v: -------------------------------------------------------------------------------- 1 | module top_level_module( 2 | input s0, 3 | input s1, 4 | output reg p0, 5 | output reg p1 6 | ); 7 | //always block syntax 8 | 9 | always @(s0,s1) begin 10 | p0 = s0 & s1; 11 | p1 = s0 | s1; 12 | end 13 | endmodule 14 | 15 | module stimulus(); 16 | 17 | reg S0,S1,dummy; 18 | wire P0,P1; 19 | top_level_module t(.s0(S0),.s1(S1),.p0(P0),.p1(P1)); 20 | initial begin 21 | $dumpfile("simulation.vcd"); 22 | $dumpvars(dummy,S0,S1,P0,P1); 23 | S0 = 1'b0; 24 | S1 = 1'b0; 25 | end 26 | 27 | always 28 | #1 S0 = ~S0; 29 | always 30 | #2 S1 = ~S1; 31 | 32 | initial 33 | #10 $finish; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/basics/verilog_general_description.v: -------------------------------------------------------------------------------- 1 | module eq1 2 | 3 | //I/O ports 4 | ( 5 | input wire i0,i1, 6 | output wire eq 7 | ); 8 | 9 | //Signal declaration 10 | wire p0,p1; 11 | 12 | //body 13 | assign eq = p0|p1; 14 | assign p0 = ~i0 & ~i1; 15 | assign p1 = i0 & i1; 16 | 17 | endmodule 18 | 19 | //top level stimulus module 20 | module stimulus; 21 | 22 | reg DUMMY; 23 | reg I0,I1; 24 | wire EQ; 25 | eq1 E(.i0(I0),.i1(I1),.eq(EQ)); 26 | 27 | initial 28 | begin 29 | $dumpfile("simulation.vcd"); 30 | $dumpvars(DUMMY,I0,I1,EQ); 31 | end 32 | 33 | initial 34 | begin 35 | I0 = 1'b0; 36 | I1 = 1'b0; 37 | end 38 | 39 | always 40 | #1 I0 = ~ I0; 41 | 42 | always 43 | #2 I1 = ~ I1; 44 | 45 | initial 46 | #4 $finish; 47 | 48 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark1/sigmoid/sigmoid.v: -------------------------------------------------------------------------------- 1 | `include "utils/sigmoid_combinational.v" 2 | 3 | module sigmoid( 4 | input wire clk, 5 | input wire reset, 6 | input wire enable, 7 | input wire [17:0] x1, 8 | output reg [47:0] fixed_op 9 | ); 10 | 11 | wire [47:0] fixed_op_next; 12 | 13 | sigmoid_combinational sigmoid_combinational_instance1( 14 | .x1(x1), 15 | .fixed_op(fixed_op_next) 16 | ); 17 | 18 | always @(posedge(clk),posedge(reset)) begin 19 | if(reset) begin 20 | fixed_op <= 0; 21 | end else begin 22 | if(enable) begin 23 | fixed_op <= fixed_op_next; 24 | end else begin 25 | fixed_op <= fixed_op; 26 | end 27 | end 28 | end 29 | 30 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark1/sigmoid_mark2/sigmoid_mark2.v: -------------------------------------------------------------------------------- 1 | `include "utils/sigmoid_combinational.v" 2 | 3 | module sigmoid( 4 | input wire clk, 5 | input wire reset, 6 | input wire enable, 7 | input wire [17:0] x1, 8 | output reg [15:0] fixed_op 9 | ); 10 | 11 | wire [47:0] fixed_op_next; 12 | 13 | sigmoid_combinational sigmoid_combinational_instance1( 14 | .x1(x1), 15 | .fixed_op(fixed_op_next) 16 | ); 17 | 18 | always @(posedge(clk),posedge(reset)) begin 19 | if(reset) begin 20 | fixed_op <= 567; 21 | end else begin 22 | if(enable) begin 23 | fixed_op <= fixed_op_next; 24 | end else begin 25 | fixed_op <= fixed_op; 26 | end 27 | end 28 | end 29 | 30 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark1/tdp_bram/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark1/tdp_bram/top.ucf: -------------------------------------------------------------------------------- 1 | NET clk LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET tx LOC = B8; 5 | NET rx LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET reset_switch LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET reset LOC = P15; 10 | 11 | #// OTHER SIGNALS 12 | #NET RX_DONE_TICK LOC = P16; 13 | 14 | // SEVEN SEGMENT DISPLAY CONNECTIONS 15 | NET led1_control_signal LOC = B3; 16 | NET led2_control_signal LOC = A2; 17 | NET led3_control_signal LOC = B2; 18 | 19 | NET display_bits[0] LOC = A5; 20 | NET display_bits[1] LOC = C6; 21 | NET display_bits[2] LOC = D6; 22 | NET display_bits[3] LOC = C5; 23 | NET display_bits[4] LOC = C4; 24 | NET display_bits[5] LOC = A4; 25 | NET display_bits[6] LOC = B4; 26 | NET display_bits[7] LOC = A3; 27 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark1/tdp_bram/uart_core_with_tx_buffer/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark2/sigmoid/sigmoid.v: -------------------------------------------------------------------------------- 1 | `include "utils/sigmoid_combinational.v" 2 | 3 | module sigmoid( 4 | input wire clk, 5 | input wire reset, 6 | input wire enable, 7 | input wire [17:0] x1, 8 | output reg [47:0] fixed_op 9 | ); 10 | 11 | wire [47:0] fixed_op_next; 12 | 13 | sigmoid_combinational sigmoid_combinational_instance1( 14 | .x1(x1), 15 | .fixed_op(fixed_op_next) 16 | ); 17 | 18 | always @(posedge(clk),posedge(reset)) begin 19 | if(reset) begin 20 | fixed_op <= 0; 21 | end else begin 22 | if(enable) begin 23 | fixed_op <= fixed_op_next; 24 | end else begin 25 | fixed_op <= fixed_op; 26 | end 27 | end 28 | end 29 | 30 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark2/sigmoid_mark2/sigmoid_mark2.v: -------------------------------------------------------------------------------- 1 | `include "utils/sigmoid_combinational.v" 2 | 3 | module sigmoid( 4 | input wire clk, 5 | input wire reset, 6 | input wire enable, 7 | input wire [17:0] x1, 8 | output reg [15:0] fixed_op 9 | ); 10 | 11 | wire [47:0] fixed_op_next; 12 | 13 | sigmoid_combinational sigmoid_combinational_instance1( 14 | .x1(x1), 15 | .fixed_op(fixed_op_next) 16 | ); 17 | 18 | always @(posedge(clk),posedge(reset)) begin 19 | if(reset) begin 20 | fixed_op <= 567; 21 | end else begin 22 | if(enable) begin 23 | fixed_op <= fixed_op_next; 24 | end else begin 25 | fixed_op <= fixed_op; 26 | end 27 | end 28 | end 29 | 30 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark2/tdp_bram/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark2/tdp_bram/top.ucf: -------------------------------------------------------------------------------- 1 | NET clk LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET tx LOC = B8; 5 | NET rx LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET reset_switch LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET reset LOC = P15; 10 | 11 | #// OTHER SIGNALS 12 | #NET RX_DONE_TICK LOC = P16; 13 | 14 | // SEVEN SEGMENT DISPLAY CONNECTIONS 15 | NET led1_control_signal LOC = B3; 16 | NET led2_control_signal LOC = A2; 17 | NET led3_control_signal LOC = B2; 18 | 19 | NET display_bits[0] LOC = A5; 20 | NET display_bits[1] LOC = C6; 21 | NET display_bits[2] LOC = D6; 22 | NET display_bits[3] LOC = C5; 23 | NET display_bits[4] LOC = C4; 24 | NET display_bits[5] LOC = A4; 25 | NET display_bits[6] LOC = B4; 26 | NET display_bits[7] LOC = A3; 27 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/classifier/classifier_mark2/tdp_bram/uart_core_with_tx_buffer/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/lpddr_memory_controller/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/lpddr_memory_controller/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/lpddr_memory_controller_mark2/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/lpddr_memory_controller_mark2/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/lpddr_memory_controller_mark6/utlis/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/lpddr_memory_controller_mark6/utlis/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/lpddr_memory_controller_mark7/utils/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/lpddr_memory_controller_mark7/utils/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/memory_controller_traffic_generator/traffic_generator_mark1.v: -------------------------------------------------------------------------------- 1 | module traffic_generator( 2 | input wire clk, 3 | input wire [7:0] input_data -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/seven_segment_display_controller/integer_display_seven_segment_display_core/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/seven_segment_display_controller/integer_display_seven_segment_display_core/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/seven_segment_display_controller/integer_seven_segment_display_coer_mark2/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/seven_segment_display_controller/integer_seven_segment_display_coer_mark2/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/seven_segment_display_controller/integer_seven_segment_display_controller_mark3/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/seven_segment_display_controller/seven_segment_display_core/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/01_uart_mark1/counter/counter.v: -------------------------------------------------------------------------------- 1 | module counter #( 2 | parameter N = 8, 3 | parameter OVERFLOW_VALUE = 2**N-1 4 | )( 5 | input wire clk, 6 | input wire reset, // reset should be available for atleast 2 clock cycles 7 | output reg [N-1:0] count, 8 | output reg overflow 9 | ); 10 | 11 | //signal declarations 12 | 13 | initial 14 | count = 0; 15 | 16 | always @(posedge(clk)) begin 17 | if(reset) begin 18 | count = 1; 19 | end 20 | else begin 21 | count = count + 1; 22 | if(count == OVERFLOW_VALUE) begin 23 | count = 0; 24 | overflow = 1; 25 | end 26 | else begin 27 | overflow = 0; 28 | end 29 | end 30 | end 31 | 32 | endmodule 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/01_uart_mark1/counter/counter_test_bench.v: -------------------------------------------------------------------------------- 1 | `include "counter.v" 2 | 3 | module stimulus(); 4 | 5 | reg CLK,RESET; 6 | wire [3:0] COUNT; 7 | 8 | counter #(.N(4)) 9 | c( 10 | .clk(CLK), 11 | .count(COUNT), 12 | .reset(RESET) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("simulation.vcd"); 17 | $dumpvars(0,CLK,COUNT,RESET); 18 | end 19 | 20 | initial begin 21 | CLK = 1'b0; 22 | RESET = 1'b0; 23 | end 24 | 25 | always 26 | #1 CLK = ~ CLK; 27 | 28 | initial begin 29 | #20 RESET = 1'b1; 30 | #2 RESET = 1'b0; 31 | end 32 | 33 | initial 34 | #100 $finish; 35 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/01_uart_mark1/pulse generator/counter.v: -------------------------------------------------------------------------------- 1 | module counter #( 2 | parameter N = 8, 3 | parameter OVERFLOW_VALUE = 2**N-1 4 | )( 5 | input wire clk, 6 | input wire reset, // reset should be available for atleast 2 clock cycles 7 | output reg [N-1:0] count, 8 | output reg overflow 9 | ); 10 | 11 | //signal declarations 12 | 13 | initial 14 | count = 0; 15 | 16 | always @(posedge(clk)) begin 17 | if(reset) begin 18 | count = 1; 19 | end 20 | else begin 21 | count = count + 1; 22 | if(count == OVERFLOW_VALUE) begin 23 | count = 0; 24 | overflow = 1; 25 | end 26 | else begin 27 | overflow = 0; 28 | end 29 | end 30 | end 31 | 32 | endmodule 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/01_uart_mark1/pulse generator/counter_and_pulse_generator_test.v: -------------------------------------------------------------------------------- 1 | `include "counter.v" 2 | `include "pulse_generator.v" 3 | 4 | module stimulus(); 5 | 6 | // counter signals 7 | reg CLK; 8 | wire [3:0] COUNT; 9 | wire OVERFLOW; 10 | // pulse generator signals 11 | reg GENERATE_PULSE; 12 | wire PULSE; 13 | 14 | counter #(.N(4)) 15 | c( 16 | .clk(CLK), 17 | .count(COUNT), 18 | .reset(PULSE), 19 | .overflow(OVERFLOW) 20 | ); 21 | 22 | pulse_generator #(.PULSE_WIDTH(2)) 23 | p( 24 | .clk(CLK), 25 | .generate_pulse(GENERATE_PULSE), 26 | .pulse(PULSE) 27 | ); 28 | 29 | initial begin 30 | $dumpfile("simulation.vcd"); 31 | $dumpvars(0,CLK,COUNT,PULSE,GENERATE_PULSE,OVERFLOW); 32 | end 33 | 34 | initial begin 35 | CLK = 1'b0; 36 | GENERATE_PULSE = 1'b0; 37 | end 38 | 39 | always 40 | #1 CLK = ~ CLK; 41 | 42 | always 43 | #41 GENERATE_PULSE = ~ GENERATE_PULSE; 44 | 45 | initial 46 | #100 $finish; 47 | 48 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/01_uart_mark1/pulse generator/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 4'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | // state declarations 10 | localparam 11 | off = 1'b0, 12 | on = 1'b1; 13 | 14 | // signal declarations 15 | reg state_reg = off; 16 | reg state_next; 17 | reg [3:0] count = 0; 18 | 19 | // ---------- next state logic -------------- 20 | always @(posedge(clk)) begin 21 | state_reg = state_next; 22 | count = count + 1; 23 | end 24 | 25 | always @(generate_pulse) begin 26 | if(state_reg == off) begin 27 | count = 0; 28 | pulse = 1; 29 | state_next = on; 30 | end 31 | end 32 | 33 | always @(count) begin 34 | if(state_reg == on) begin 35 | if(count == PULSE_WIDTH) begin 36 | pulse = 0; 37 | state_next = off; 38 | end 39 | end 40 | end 41 | //------------------------------------------ 42 | 43 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/01_uart_mark1/pulse generator/pulse_generator_test_bench.v: -------------------------------------------------------------------------------- 1 | `include "pulse_generator.v" 2 | 3 | module stimulus(); 4 | 5 | reg CLK,GENERATE_PULSE; 6 | wire PULSE; 7 | 8 | pulse_generator #(.PULSE_WIDTH(3)) 9 | p( 10 | .clk(CLK), 11 | .generate_pulse(GENERATE_PULSE), 12 | .pulse(PULSE) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("simulation.vcd"); 17 | $dumpvars(0,CLK,GENERATE_PULSE,PULSE); 18 | end 19 | 20 | initial begin 21 | CLK = 1'b0; 22 | GENERATE_PULSE = 1'b0; 23 | end 24 | 25 | always 26 | #1 CLK = ~ CLK; 27 | 28 | 29 | always 30 | #20 GENERATE_PULSE = ~ GENERATE_PULSE; 31 | 32 | initial 33 | #100 $finish; 34 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/01_uart_mark1/sampling_tick_generator/sampling_tick_generator_test_bench.v: -------------------------------------------------------------------------------- 1 | module stimulus(); 2 | 3 | reg CLK; 4 | wire TICK; 5 | 6 | sampling_tick_generator #(.baudrate(32'd112000),.frequency(32'd100000000)) 7 | t1( 8 | .clk(CLK), 9 | .tick(TICK) 10 | ); 11 | 12 | initial begin 13 | $dumpfile("simulation.vcd"); 14 | $dumpvars(1,CLK,TICK); 15 | end 16 | 17 | initial 18 | CLK = 1'b0; 19 | 20 | always 21 | #1 CLK = ~ CLK; 22 | 23 | initial 24 | #500 $finish; 25 | 26 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/01_uart_mark1/uart_receiver/counter.v: -------------------------------------------------------------------------------- 1 | module counter #( 2 | parameter N = 8, 3 | parameter OVERFLOW_VALUE = 2**N-1 4 | )( 5 | input wire clk, 6 | input wire reset, // reset should be available for atleast 2 clock cycles 7 | output reg [N-1:0] count, 8 | output reg overflow 9 | ); 10 | 11 | //signal declarations 12 | 13 | initial 14 | count = 0; 15 | 16 | always @(posedge(clk)) begin 17 | if(reset) begin 18 | count = 1; 19 | end 20 | else begin 21 | count = count + 1; 22 | if(count == OVERFLOW_VALUE) begin 23 | count = 0; 24 | overflow = 1; 25 | end 26 | else begin 27 | overflow = 0; 28 | end 29 | end 30 | end 31 | 32 | endmodule 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/01_uart_mark1/uart_receiver/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 4'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | // state declarations 10 | localparam 11 | off = 1'b0, 12 | on = 1'b1; 13 | 14 | // signal declarations 15 | reg state_reg = off; 16 | reg state_next = off; 17 | reg [3:0] count = 0; 18 | 19 | // ---------- next state logic -------------- 20 | always @(posedge(clk)) begin 21 | state_reg = state_next; 22 | count = count + 1; 23 | end 24 | 25 | always @(generate_pulse) begin 26 | if(state_reg == off) begin 27 | count = 0; 28 | pulse = 1; 29 | state_next = on; 30 | end 31 | end 32 | 33 | always @(count) begin 34 | if(state_reg == on) begin 35 | if(count == PULSE_WIDTH) begin 36 | pulse = 0; 37 | state_next = off; 38 | end 39 | end 40 | end 41 | //------------------------------------------ 42 | 43 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_core/uart_core_verilog_modules/counter.v: -------------------------------------------------------------------------------- 1 | module counter #( 2 | parameter N = 8, 3 | parameter OVERFLOW_VALUE = 2**N-1 4 | )( 5 | input wire clk, 6 | input wire count_increment_clk, 7 | input wire reset, // reset should be available for atleast 2 clock cycles 8 | input wire overflow_enable, 9 | output reg [N-1:0] count, 10 | output reg overflow 11 | ); 12 | 13 | //signal declarations 14 | 15 | initial begin 16 | count = 0; 17 | overflow = 0; 18 | end 19 | 20 | always @(posedge(clk)) begin 21 | if(reset) begin 22 | count = 0; 23 | end 24 | end 25 | 26 | always @(posedge(count_increment_clk)) begin 27 | if(overflow_enable == 1'b1) begin 28 | if(count == OVERFLOW_VALUE) begin 29 | count = 0; 30 | overflow = 1; 31 | end 32 | else begin 33 | overflow = 0; 34 | end 35 | end else begin 36 | overflow = 0; 37 | end 38 | count = count + 1; 39 | end 40 | 41 | endmodule 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_core/uart_core_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 4'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | // state declarations 10 | localparam 11 | off = 1'b0, 12 | on = 1'b1; 13 | 14 | // signal declarations 15 | reg state_reg = off; 16 | reg state_next = off; 17 | reg [3:0] count = 0; 18 | 19 | // ---------- next state logic -------------- 20 | always @(posedge(clk)) begin 21 | state_reg = state_next; 22 | count = count + 1; 23 | end 24 | 25 | always @(generate_pulse) begin 26 | if(state_reg == off) begin 27 | count = 0; 28 | pulse = 1; 29 | state_next = on; 30 | end 31 | end 32 | 33 | always @(count) begin 34 | if(state_reg == on) begin 35 | if(count == PULSE_WIDTH) begin 36 | pulse = 0; 37 | state_next = off; 38 | end 39 | end 40 | end 41 | //------------------------------------------ 42 | 43 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_core/uart_core_verilog_modules/stimulus.v: -------------------------------------------------------------------------------- 1 | `include "uart_core.v" 2 | 3 | module stimulus(); 4 | reg CLK; 5 | reg RX; 6 | wire [7:0] DATA; 7 | wire READ_FINISH; 8 | 9 | initial begin 10 | CLK = 1'b0; 11 | RX = 1'b1; 12 | end 13 | 14 | uart_receiver 15 | u( 16 | .clk(CLK), 17 | .rx(RX), 18 | .data(DATA), 19 | .read_finish(READ_FINISH) 20 | ); 21 | 22 | initial begin 23 | // $dumpfile("simulation.vcd"); 24 | $dumpvars(0, 25 | CLK, 26 | RX, 27 | DATA, 28 | READ_FINISH 29 | ); 30 | end 31 | 32 | always 33 | #1 clk = ~ clk; 34 | 35 | initial begin 36 | #100 rx = 0; 37 | #100 rx = 1; 38 | #17000 rx = 0; 39 | end 40 | 41 | initial begin 42 | #1000000000 $finish; 43 | end 44 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_receiver/02_uart_receiver_core_mark2/baudrate_tick_generator.v: -------------------------------------------------------------------------------- 1 | module baudrate_tick_generator #( 2 | parameter baudrate = 32'd9600, 3 | parameter frequency = 32'd100000000 // in Hz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | // state declaration 9 | localparam 10 | off = 1'b0, 11 | on = 1'b1; 12 | 13 | // signal declaration 14 | localparam [31:0] count_threshold = (frequency)/(baudrate*32); 15 | reg [31:0] count = 0, tick_count = 0; 16 | reg [31:0] tick_threshold = 0; 17 | 18 | initial begin 19 | tick = 1'b0; 20 | count = 32'b0; 21 | end 22 | 23 | always @(posedge(clk)) begin 24 | if(count == count_threshold) begin 25 | tick <= 1; 26 | count <= 0; 27 | tick_count <= 0; 28 | end else begin 29 | if(tick_count != tick_threshold) begin 30 | tick_count <= tick_count + 1; 31 | end else begin 32 | tick <= 0; 33 | end 34 | count <= count + 1; 35 | end 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_receiver/02_uart_receiver_core_mark2/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_receiver/04_uart_receiver_ssd_testing/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_receiver/uart_rx_ssd_test/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_receiver/uart_rx_ssd_test/uart_receiver_ssd_test.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // UART CONNECTIONS 23 | NET RX LOC = A8; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/02_uart_transmitter_core/uart_transmitter_core_test.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | NET INDICATOR_LED LOC = P15; 3 | NET TICK_GENERATOR_TICK LOC = P16; 4 | NET TX LOC = B8; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/02_uart_transmitter_core/uart_transmitter_core_verilog_modules/baudrate_generator.v: -------------------------------------------------------------------------------- 1 | module baudrate_tick_generator #( 2 | parameter baudrate = 32'd9600, 3 | parameter frequency = 32'd100000000 // in Hz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | // state declaration 9 | localparam 10 | off = 1'b0, 11 | on = 1'b1; 12 | 13 | // signal declaration 14 | reg [32:0] count = 0, tick_count = 0; 15 | reg [32:0] count_threshold = (frequency)/(baudrate*32); 16 | reg [32:0] tick_threshold = 1; 17 | 18 | initial begin 19 | tick = 1'b0; 20 | count = 32'b0; 21 | end 22 | 23 | always @(posedge(clk)) begin 24 | if(count == count_threshold) begin 25 | tick <= 1; 26 | count <= 0; 27 | tick_count <= 0; 28 | end else begin 29 | if(tick_count != tick_threshold) begin 30 | tick_count <= tick_count + 1; 31 | end else begin 32 | tick <= 0; 33 | end 34 | count <= count + 1; 35 | end 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/02_uart_transmitter_core/uart_transmitter_core_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/02_uart_transmitter_core/uart_transmitter_core_verilog_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/03_uart_transmitter_core_mark2 _WORKING_SIMULATION/uart_transmitter_core_verilog_modules/baudrate_generator.v: -------------------------------------------------------------------------------- 1 | module baudrate_tick_generator #( 2 | parameter baudrate = 32'd9600, 3 | parameter frequency = 32'd100000000 // in Hz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | // state declaration 9 | localparam 10 | off = 1'b0, 11 | on = 1'b1; 12 | 13 | // signal declaration 14 | reg [31:0] count = 0, tick_count = 0; 15 | reg [31:0] count_threshold = (frequency)/(baudrate*2); 16 | reg [31:0] tick_threshold = 1; 17 | 18 | initial begin 19 | tick = 1'b0; 20 | count = 32'b0; 21 | end 22 | 23 | always @(posedge(clk)) begin 24 | if(count == count_threshold) begin 25 | tick <= 1; 26 | count <= 0; 27 | tick_count <= 0; 28 | end else begin 29 | if(tick_count != tick_threshold) begin 30 | tick_count <= tick_count + 1; 31 | end else begin 32 | tick <= 0; 33 | end 34 | count <= count + 1; 35 | end 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/03_uart_transmitter_core_mark2 _WORKING_SIMULATION/uart_transmitter_core_verilog_modules/final_testbenches/baudrate_tick_generator_tb.v: -------------------------------------------------------------------------------- 1 | module stimulus(); 2 | reg CLK; 3 | wire TICK; 4 | 5 | localparam BAUDRATE = 32'd115200; 6 | 7 | baudrate_tick_generator #(.baudrate(BAUDRATE)) 8 | b( 9 | .clk(CLK), 10 | .tick(TICK) 11 | ); 12 | 13 | initial 14 | CLK = 1'b0; 15 | 16 | always 17 | #1 CLK = ~ CLK; 18 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/03_uart_transmitter_core_mark2 _WORKING_SIMULATION/uart_transmitter_core_verilog_modules/final_testbenches/pulse_generator_tb.v: -------------------------------------------------------------------------------- 1 | module stimulus( 2 | input wire CLK, 3 | output wire GENERATED_PULSE, 4 | output wire TICK 5 | ); 6 | 7 | tick_generator #(.tick_time(32'd6000),.frequency(32'd100000)) 8 | t( 9 | .clk(CLK), 10 | .tick(TICK) 11 | ); 12 | 13 | pulse_generator #(.PULSE_WIDTH(32'd1000000)) 14 | p( 15 | .clk(CLK), 16 | .generate_pulse(TICK), 17 | .pulse(GENERATED_PULSE) 18 | ); 19 | 20 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/03_uart_transmitter_core_mark2 _WORKING_SIMULATION/uart_transmitter_core_verilog_modules/final_testbenches/tick_generator_tb.v: -------------------------------------------------------------------------------- 1 | module stimulus( 2 | input wire CLK, 3 | output wire TICK 4 | ); 5 | 6 | tick_generator #(.tick_time(32'd5000),.frequency(32'd100000)) 7 | t( 8 | .clk(CLK), 9 | .tick(TICK) 10 | ); 11 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/03_uart_transmitter_core_mark2 _WORKING_SIMULATION/uart_transmitter_core_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/03_uart_transmitter_core_mark2 _WORKING_SIMULATION/uart_transmitter_core_verilog_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/03_uart_transmitter_core_mark2 _WORKING_SIMULATION/uart_transmitter_core_verilog_modules/uart_transmitter_core_mark2.ucf: -------------------------------------------------------------------------------- 1 | #NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | #NET TICK LOC = P15; 3 | #NET GENERATED_PULSE LOC = P16; 4 | 5 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 6 | NET INDICATOR_LED LOC = P15; 7 | NET TICK_GENERATOR_TICK LOC = P16; 8 | NET TX LOC = B8; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/uart_receiver_mark1/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05:15:37 02/21/2016 7 | // Design Name: 8 | // Module Name: test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module test( 22 | ); 23 | 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/uart_receiver_mark1/uart_receiver_verilog_modules/counter.v: -------------------------------------------------------------------------------- 1 | module counter #( 2 | parameter N = 8, 3 | parameter OVERFLOW_VALUE = 2**N-1 4 | )( 5 | input wire clk, 6 | input wire count_increment_clk, 7 | input wire reset, // reset should be available for atleast 2 clock cycles 8 | input wire overflow_enable, 9 | output reg [N-1:0] count, 10 | output reg overflow 11 | ); 12 | 13 | //signal declarations 14 | 15 | initial begin 16 | count = 0; 17 | overflow = 0; 18 | end 19 | 20 | always @(posedge(clk)) begin 21 | if(reset) begin 22 | count = 0; 23 | end 24 | end 25 | 26 | always @(posedge(count_increment_clk)) begin 27 | if(overflow_enable == 1'b1) begin 28 | if(count == OVERFLOW_VALUE) begin 29 | count = 0; 30 | overflow = 1; 31 | end 32 | else begin 33 | overflow = 0; 34 | end 35 | end else begin 36 | overflow = 0; 37 | end 38 | count = count + 1; 39 | end 40 | 41 | endmodule 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter/uart_receiver_mark1/uart_receiver_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 4'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | // state declarations 10 | localparam 11 | off = 1'b0, 12 | on = 1'b1; 13 | 14 | // signal declarations 15 | reg state_reg = off; 16 | reg state_next = off; 17 | reg [3:0] count = 0; 18 | 19 | // ---------- next state logic -------------- 20 | always @(posedge(clk)) begin 21 | state_reg = state_next; 22 | count = count + 1; 23 | end 24 | 25 | always @(generate_pulse) begin 26 | if(state_reg == off) begin 27 | count = 0; 28 | pulse = 1; 29 | state_next = on; 30 | end 31 | end 32 | 33 | always @(count) begin 34 | if(state_reg == on) begin 35 | if(count == PULSE_WIDTH) begin 36 | pulse = 0; 37 | state_next = off; 38 | end 39 | end 40 | end 41 | //------------------------------------------ 42 | 43 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter_core/utils/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | localparam [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | if(count == count_threshold) begin 18 | count = 32'b0; 19 | tick = 1'b1; 20 | end else begin 21 | tick = 1'b0; 22 | count = count + 1; 23 | end 24 | end 25 | 26 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter_core/utils/transmitter_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | 6 | // RESET CONNECTIONS 7 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 8 | NET RESET LOC = P15; 9 | 10 | // OTHER SIGNALS 11 | NET BUSY LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart/uart_transmitter_mark6_rana/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | localparam [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | if(count == count_threshold) begin 18 | count = 32'b0; 19 | tick = 1'b1; 20 | end else begin 21 | tick = 1'b0; 22 | count = count + 1; 23 | end 24 | end 25 | 26 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/FPGA_prototyping_by_verilog_basics/uart_core_with_tx_fifo/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/final_source_codes/baudrate_generator.v: -------------------------------------------------------------------------------- 1 | module baudrate_tick_generator #( 2 | parameter baudrate = 32'd9600, 3 | parameter frequency = 32'd100000000 // in Hz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | // state declaration 9 | localparam 10 | off = 1'b0, 11 | on = 1'b1; 12 | 13 | // signal declaration 14 | reg [31:0] count = 0, tick_count = 0; 15 | reg [31:0] count_threshold = (frequency)/(baudrate*2); 16 | reg [31:0] tick_threshold = 1; 17 | 18 | initial begin 19 | tick = 1'b0; 20 | count = 32'b0; 21 | end 22 | 23 | always @(posedge(clk)) begin 24 | if(count == count_threshold) begin 25 | tick <= 1; 26 | count <= 0; 27 | tick_count <= 0; 28 | end else begin 29 | if(tick_count != tick_threshold) begin 30 | tick_count <= tick_count + 1; 31 | end else begin 32 | tick <= 0; 33 | end 34 | count <= count + 1; 35 | end 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/final_source_codes/seven_segment_display_core/utils/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, // in seconds 3 | parameter frequency = 32'd100000 // in KHz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/final_source_codes/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, // seconds 3 | parameter frequency = 32'd100000 // KHz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/final_source_codes/uart_core/uart_tx_core/utils/tx_tick_generator.v: -------------------------------------------------------------------------------- 1 | module tx_tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | input wire reset, 7 | output reg tick 8 | ); 9 | 10 | reg [32:0] count; 11 | localparam [32:0] count_threshold = tick_time * frequency; 12 | 13 | initial begin 14 | tick = 1'b0; 15 | count = 32'b0; 16 | end 17 | 18 | always @(posedge(clk),posedge(reset)) begin 19 | if(reset) begin 20 | count = 32'b0; 21 | tick = 1'b0; 22 | end else begin 23 | if(count == count_threshold) begin 24 | count = 32'b0; 25 | tick = 1'b1; 26 | end else begin 27 | tick = 1'b0; 28 | count = count + 1; 29 | end 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/final_source_codes/uart_core/uart_tx_core/utils/uart_tx_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | 6 | // RESET CONNECTIONS 7 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 8 | NET RESET LOC = P15; 9 | 10 | // OTHER SIGNALS 11 | NET BUSY LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/final_source_codes/uart_rx_ssd_test/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/final_source_codes/uart_rx_ssd_test/uart_receiver_ssd_test.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // UART CONNECTIONS 23 | NET RX LOC = A8; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/verilog_basics/01_hello_world.v: -------------------------------------------------------------------------------- 1 | 2 | //Definea module hello_world 3 | module hello_world; 4 | parameter id_num = 0; //define a module identification number = 0 5 | 6 | initial //display the module identification number 7 | $display("Disp1aying hello_world id number = %d",id_num); 8 | endmodule 9 | //define top_level module 10 | 11 | module top; 12 | //change parameter values in the instantiated modules //Use defparam statement 13 | // defparam w1.id_num = 1, w2.id_num = 2; 14 | //instantiate two hello_world modules 15 | // hello_world w1(); 16 | // hello_world w2(); 17 | endmodule 18 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/verilog_basics/02_basics_01.v: -------------------------------------------------------------------------------- 1 | module stimulus; 2 | 3 | reg x,y,a,b,m,p; 4 | 5 | initial 6 | begin 7 | $dumpfile("test.vcd"); 8 | $dumpvars(0,x,y,a,b,m,p); 9 | end 10 | 11 | initial 12 | begin 13 | p = 1'b0; 14 | m = 1'b0; 15 | end 16 | 17 | initial 18 | begin 19 | #5 a = 1'b1; 20 | #25 b = 1'b0; 21 | end 22 | 23 | initial 24 | begin 25 | #10 x = 1'b0; 26 | #25 y = 1'b1; 27 | end 28 | 29 | // initial 30 | // begin 31 | // p = 1'b0; 32 | // #5 p = 1'b1; 33 | // #5 p = 1'b0; 34 | // #5 p = 1'b1; 35 | // #5 p = 1'b0; 36 | // #5 p = 1'b1; 37 | // #5 p = 1'b0; 38 | // #5 p = 1'b1; 39 | // #5 p = 1'b0; 40 | // #5 p = 1'b1; 41 | // #5 p = 1'b0; 42 | // end 43 | 44 | always 45 | #2 p = ~p; 46 | 47 | initial 48 | #50 $finish; 49 | 50 | // always 51 | // #5 $display("the current time is %t",$time); 52 | 53 | initial 54 | #30 $stop; 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/verilog_basics/04_logic_gates.v: -------------------------------------------------------------------------------- 1 | module logic_gates; 2 | wire OUT_AND,OUT_NAND,OUT_OR,OUT_NOR,OUT_XOR,OUT_XNOR; 3 | reg IN1,IN2; 4 | reg clock; 5 | and a1(OUT_AND,IN1,IN2); 6 | nand na1(OUT_NAND,IN1,IN2); 7 | or or1(OUT_OR,IN1,IN2); 8 | nor nor1(OUT_NOR,IN1,IN2); 9 | xor xor1(OUT_XOR,IN1,IN2); 10 | xnor xnor1(OUT_XNOR,IN1,IN2); 11 | 12 | initial 13 | begin 14 | $dumpfile("logic_gates.vcd"); 15 | $dumpvars(clock,IN1,IN2,OUT_AND,OUT_NAND,OUT_OR,OUT_NOR,OUT_XOR,OUT_XNOR); 16 | clock = 1'b0; 17 | IN1 = 1'b0; 18 | IN2 = 1'b0; 19 | end 20 | 21 | always 22 | #5 clock = ~clock; 23 | 24 | always 25 | #5 IN1 = ~ IN1; 26 | 27 | always 28 | #10 IN2 = ~ IN2; 29 | 30 | initial 31 | #50 $finish; 32 | 33 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/verilog_basics/05_multiplexer.v: -------------------------------------------------------------------------------- 1 | module mux_4_to_1(i0,i1,i2,i3,s0,s1,o0); 2 | input s0,s1; 3 | input i0,i1,i2,i3; 4 | output o0; 5 | 6 | wire s0n,s1n; 7 | wire y0,y1,y2,y3; 8 | not (s0n,s0); 9 | not (s1n,s1); 10 | 11 | and (y0,i0,s0n,s1n); 12 | and (y1,i1,s0,s1n); 13 | and (y2,i2,s0n,s1); 14 | and (y3,i3,s0,s1); 15 | 16 | or (o0,y0,y1,y2,y3); 17 | endmodule 18 | 19 | module stimulus; 20 | reg IN0,IN1,IN2,IN3; 21 | reg S1,S0; 22 | wire OUTPUT; 23 | 24 | mux_4_to_1 m(IN0,IN1,IN2,IN3,S0,S1,OUTPUT); 25 | 26 | initial 27 | begin 28 | $dumpfile("simulation.vcd"); 29 | $dumpvars(IN0,IN1,IN2,IN3,S0,S1,OUTPUT); 30 | end 31 | 32 | initial 33 | begin 34 | IN0 = 1'b0; 35 | IN1 = 1'b1; 36 | IN2 = 1'b0; 37 | IN3 = 1'b1; 38 | S0 = 1'b0; 39 | S1 = 1'b0; 40 | end 41 | 42 | always 43 | #1 S0 = ~ S0; 44 | 45 | always 46 | #2 S1 = ~ S1; 47 | 48 | initial 49 | #10 $finish; 50 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/verilog_basics/06_adder_1_bit.v: -------------------------------------------------------------------------------- 1 | module adder_1_bit(a,b,sum,c_in,c_out); 2 | output sum,c_out; 3 | input a,b,c_in; 4 | wire s1,c1,c2; 5 | 6 | xor (s1,a,b); 7 | xor (sum,s1,c_in); 8 | 9 | and (c1,a,b); 10 | and (c2,s1,c_in); 11 | or (c_out,c1,c2); 12 | endmodule 13 | 14 | module stimulus; 15 | reg C_IN,A,B; 16 | wire C_OUT,SUM,DUMMY; 17 | adder_1_bit a1(A,B,SUM,C_IN,C_OUT); 18 | 19 | initial 20 | begin 21 | $dumpfile("simulation.vcd"); 22 | $dumpvars(DUMMY,A,B,C_IN,SUM,C_OUT); 23 | end 24 | 25 | initial 26 | begin 27 | A = 0; 28 | B = 0; 29 | C_IN = 0; 30 | end 31 | 32 | always 33 | #1 A = ~ A; 34 | 35 | always 36 | #2 B = ~ B; 37 | 38 | always 39 | #4 C_IN = ~ C_IN; 40 | 41 | initial 42 | #16 $finish; 43 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/verilog_basics/08_mux_4_to_1_dataflow.v: -------------------------------------------------------------------------------- 1 | module mux4_to_1(i0,i1,i2,i3,s0,s1,out); 2 | input i0,i1,i2,i3,s0,s1; 3 | output out; 4 | 5 | // assign out = (s0 & s1 & i3) | 6 | // (~s0 & s1 & i2) | 7 | // (s0 & ~s1 & i1) | 8 | // (~s0 & ~s1 & i0); 9 | assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0); 10 | 11 | endmodule 12 | 13 | module stimulus; 14 | 15 | reg DUMMY; 16 | reg [3:0] I; 17 | reg [1:0] S; 18 | wire OUT; 19 | mux4_to_1 m1(I[0],I[1],I[2],I[3],S[0],S[1],OUT); 20 | 21 | initial 22 | begin 23 | $dumpfile("simulation.vcd"); 24 | $dumpvars(DUMMY,I,S,OUT); 25 | end 26 | 27 | initial 28 | begin 29 | I = 4'b1100; 30 | S = 2'd0; 31 | end 32 | 33 | always 34 | #1 S[0] = ~ S[0]; 35 | 36 | always 37 | #2 S[1] = ~ S[1]; 38 | 39 | initial 40 | #4 $finish; 41 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/verilog_working_directory/src/verilog_basics/test.v: -------------------------------------------------------------------------------- 1 | module and_(a,b,c); 2 | input wire a,b; 3 | output reg c; 4 | 5 | always @* 6 | c = a & b; 7 | endmodule 8 | 9 | module stimulus(); 10 | 11 | and_ a(1,1,output_); 12 | and_ b(a=1,b=1,c=output_); //python style 13 | and_ c(.a(1),.b(1),.c(output_)); 14 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_coregen_projects/lpddr_memory_controller/user_defined_modules/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_coregen_projects/lpddr_memory_controller/user_defined_modules/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/binary_to_bcd_converter/binary_to_12bit_bcd_converter/binary_to_12bit_bcd_converter.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | NET LED1_CONTROL_SIGNAL LOC = B3; 4 | NET LED2_CONTROL_SIGNAL LOC = A2; 5 | NET LED3_CONTROL_SIGNAL LOC = B2; 6 | NET LED_CHANGE_TICK LOC = P15; 7 | 8 | NET DISPLAY_BITS[0] LOC = A5; 9 | NET DISPLAY_BITS[1] LOC = C6; 10 | NET DISPLAY_BITS[2] LOC = D6; 11 | NET DISPLAY_BITS[3] LOC = C5; 12 | NET DISPLAY_BITS[4] LOC = C4; 13 | NET DISPLAY_BITS[5] LOC = A4; 14 | NET DISPLAY_BITS[6] LOC = B4; 15 | NET DISPLAY_BITS[7] LOC = A3; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/binary_to_bcd_converter/binary_to_12bit_bcd_converter/binary_to_12bit_bcd_converter_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/binary_to_bcd_converter/binary_to_12bit_bcd_converter/binary_to_12bit_bcd_converter_verilog_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/binary_to_bcd_converter/binary_to_12bit_bcd_converter_mark2/binary_to_bcd_converter_mark2_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/binary_to_bcd_converter/binary_to_12bit_bcd_converter_mark2/binary_to_bcd_converter_mark2_verilog_modules/stimulus.v: -------------------------------------------------------------------------------- 1 | `include "seven_segment_display_controller.v" 2 | `include "binary_to_12bit_bcd_converter.v" 3 | 4 | module stimulus( 5 | input wire CLK, 6 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/binary_to_bcd_converter/binary_to_12bit_bcd_converter_mark2/binary_to_bcd_converter_mark2_verilog_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/binary_to_bcd_converter/binary_to_12bit_bcd_converter_mark2/stimulus.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "seven_segment_display_controller.v" 3 | `include "binary_to_12bit_bcd_converter.v" 4 | module stimulus( 5 | ); 6 | 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/debouncing_switch/debouncing_switch.ucf: -------------------------------------------------------------------------------- 1 | NET clk LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | NET switch_input LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 3 | NET switch_output LOC = P15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/debouncing_switch/debouncing_switch_verilog_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | localparam [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = 1; 21 | end 22 | else begin 23 | tick = 0; 24 | end 25 | end 26 | 27 | endmodule 28 | 29 | // module stimulus(); 30 | // 31 | // reg CLK; 32 | // wire TICK; 33 | // 34 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 35 | // 36 | // initial begin 37 | // $dumpfile("simulation.vcd"); 38 | // $dumpvars(1,CLK,TICK); 39 | // end 40 | // 41 | // initial 42 | // CLK = 1'b0; 43 | // 44 | // always 45 | // #1 CLK = ~ CLK; 46 | // 47 | // initial 48 | // #100 $finish; 49 | // 50 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/integer_seven_segment_display_controller/integer_seven_segment_display_controller_mark1/integer_display_seven_segment_display_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/integer_seven_segment_display_controller/integer_seven_segment_display_controller_mark1/integer_display_seven_segment_display_verilog_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/integer_seven_segment_display_controller/integer_seven_segment_display_controller_mark1/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | NET LED1_CONTROL_SIGNAL LOC = B3; 4 | NET LED2_CONTROL_SIGNAL LOC = A2; 5 | NET LED3_CONTROL_SIGNAL LOC = B2; 6 | NET NUMBER_CHANGE_TICK LOC = P15; 7 | 8 | NET DISPLAY_BITS[0] LOC = A5; 9 | NET DISPLAY_BITS[1] LOC = C6; 10 | NET DISPLAY_BITS[2] LOC = D6; 11 | NET DISPLAY_BITS[3] LOC = C5; 12 | NET DISPLAY_BITS[4] LOC = C4; 13 | NET DISPLAY_BITS[5] LOC = A4; 14 | NET DISPLAY_BITS[6] LOC = B4; 15 | NET DISPLAY_BITS[7] LOC = A3; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/integer_seven_segment_display_controller/integer_seven_segment_display_controller_mark2/integer_seven_segment_display_controller_mark2.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | NET LED1_CONTROL_SIGNAL LOC = B3; 4 | NET LED2_CONTROL_SIGNAL LOC = A2; 5 | NET LED3_CONTROL_SIGNAL LOC = B2; 6 | #NET LED_CHANGE_TICK LOC = P15; 7 | #NET TICK LOC = P16; 8 | #NET GENERATE_START_PULSE LOC = N15; 9 | 10 | NET LED_DISPLAY_VALUE[7] LOC = P15; 11 | NET LED_DISPLAY_VALUE[6] LOC = P16; 12 | NET LED_DISPLAY_VALUE[5] LOC = N15; 13 | NET LED_DISPLAY_VALUE[4] LOC = N16; 14 | NET LED_DISPLAY_VALUE[3] LOC = U17; 15 | NET LED_DISPLAY_VALUE[2] LOC = U18; 16 | NET LED_DISPLAY_VALUE[1] LOC = T17; 17 | NET LED_DISPLAY_VALUE[0] LOC = T18; 18 | 19 | NET DISPLAY_BITS[0] LOC = A5; 20 | NET DISPLAY_BITS[1] LOC = C6; 21 | NET DISPLAY_BITS[2] LOC = D6; 22 | NET DISPLAY_BITS[3] LOC = C5; 23 | NET DISPLAY_BITS[4] LOC = C4; 24 | NET DISPLAY_BITS[5] LOC = A4; 25 | NET DISPLAY_BITS[6] LOC = B4; 26 | NET DISPLAY_BITS[7] LOC = A3; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/integer_seven_segment_display_controller/integer_seven_segment_display_controller_mark2/integer_seven_segment_display_core_mark2/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/integer_seven_segment_display_controller/integer_seven_segment_display_controller_mark2/integer_seven_segment_display_core_mark2/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/integer_seven_segment_display_controller/integer_seven_segment_display_controller_mark3/user_defined_modules/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/lpddr_memory_controller/lpddr_memory_controller/user_defined_modules/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/lpddr_memory_controller/lpddr_memory_controller/user_defined_modules/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/lpddr_memory_controller/lpddr_memory_controller_mark2/user_defined_modules/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/lpddr_memory_controller/lpddr_memory_controller_mark2/user_defined_modules/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/lpddr_memory_controller/lpddr_memory_controller_mark3/user_defined_modules/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/lpddr_memory_controller/lpddr_memory_controller_mark3/user_defined_modules/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/lpddr_memory_controller/lpddr_memory_controller_traffic_generator/user_defined_modules/traffic_generator_mark1.v: -------------------------------------------------------------------------------- 1 | module traffic_generator( 2 | input wire clk, 3 | input wire [7:0] input_data -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/mimas_v2_blinky/blinky.ucf: -------------------------------------------------------------------------------- 1 | NET "LED1" LOC = T18; 2 | NET "LED2" LOC = T17; 3 | NET "LED3" LOC = U18; 4 | NET "LED4" LOC = U17; 5 | NET "CLK" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock 6 | 7 | #------- DISABLING SEVEN SEGMENT DISPLAY ---------- 8 | NET "A2" PULLUP; 9 | NET "A2" LOC = A2; 10 | NET "B2" PULLUP; 11 | NET "B2" LOC = B2; 12 | NET "B3" PULLUP; 13 | NET "B3" LOC = B3; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/reset_controller/reset_controller.ucf: -------------------------------------------------------------------------------- 1 | NET clk LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | NET switch_input LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 3 | NET reset LOC = P15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/seven_segment_display/seven_segment_display.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | NET LED1 LOC = B3; 4 | NET LED2 LOC = A2; 5 | NET LED3 LOC = B2; 6 | NET TICK LOC = P15; 7 | 8 | NET WIRE[0] LOC = A5; 9 | NET WIRE[1] LOC = C6; 10 | NET WIRE[2] LOC = D6; 11 | NET WIRE[3] LOC = C5; 12 | NET WIRE[4] LOC = C4; 13 | NET WIRE[5] LOC = A4; 14 | NET WIRE[6] LOC = B4; 15 | NET WIRE[7] LOC = A3; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/seven_segment_display/seven_segment_display_driver.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:37:25 02/18/2016 7 | // Design Name: 8 | // Module Name: seven_segment_display_driver 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module seven_segment_display_driver( 22 | 23 | ); 24 | 25 | 26 | endmodule 27 | 28 | modul -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/seven_segment_display/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/seven_segment_display_controller/seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | NET LED1 LOC = B3; 4 | NET LED2 LOC = A2; 5 | NET LED3 LOC = B2; 6 | NET LED_CHANGE_TICK LOC = P15; 7 | 8 | NET DISPLAY_BITS[0] LOC = A5; 9 | NET DISPLAY_BITS[1] LOC = C6; 10 | NET DISPLAY_BITS[2] LOC = D6; 11 | NET DISPLAY_BITS[3] LOC = C5; 12 | NET DISPLAY_BITS[4] LOC = C4; 13 | NET DISPLAY_BITS[5] LOC = A4; 14 | NET DISPLAY_BITS[6] LOC = B4; 15 | NET DISPLAY_BITS[7] LOC = A3; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/seven_segment_display_core/seven_segment_display_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | NET LED_CONTROL_SIGNAL_REGISTER[0] LOC = B3; 4 | NET LED_CONTROL_SIGNAL_REGISTER[1] LOC = A2; 5 | NET LED_CONTROL_SIGNAL_REGISTER[2] LOC = B2; 6 | NET LED_CHANGE_TICK LOC = P15; 7 | 8 | NET DISPLAY_BITS[0] LOC = A5; 9 | NET DISPLAY_BITS[1] LOC = C6; 10 | NET DISPLAY_BITS[2] LOC = D6; 11 | NET DISPLAY_BITS[3] LOC = C5; 12 | NET DISPLAY_BITS[4] LOC = C4; 13 | NET DISPLAY_BITS[5] LOC = A4; 14 | NET DISPLAY_BITS[6] LOC = B4; 15 | NET DISPLAY_BITS[7] LOC = A3; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/seven_segment_display_core/verilog_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule 25 | 26 | // module stimulus(); 27 | 28 | // reg CLK; 29 | // wire TICK; 30 | 31 | // tick_generator #(.tick_time(32'd5),.frequency(32'd1)) t1(.clk(CLK),.tick(TICK)); 32 | 33 | // initial begin 34 | // $dumpfile("simulation.vcd"); 35 | // $dumpvars(1,CLK,TICK); 36 | // end 37 | 38 | // initial 39 | // CLK = 1'b0; 40 | 41 | // always 42 | // #1 CLK = ~ CLK; 43 | 44 | // initial 45 | // #100 $finish; 46 | 47 | // endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/sigmoid_mark3/user_defined_modules/sigmoid/sigmoid.v: -------------------------------------------------------------------------------- 1 | `include "utils/sigmoid_combinational.v" 2 | 3 | module sigmoid( 4 | input wire clk, 5 | input wire reset, 6 | input wire [17:0] x1, 7 | output reg [47:0] fixed_op 8 | ); 9 | 10 | wire [47:0] fixed_op_next; 11 | 12 | sigmoid_combinational sigmoid_combinational_instance1( 13 | .x1(x1), 14 | .fixed_op(fixed_op_next) 15 | ); 16 | 17 | always @(posedge(clk),posedge(reset)) begin 18 | if(reset) begin 19 | fixed_op <= 0; 20 | end else begin 21 | fixed_op <= fixed_op_next; 22 | end 23 | end 24 | 25 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/sigmoid_mark3/user_defined_modules/top_tb.v: -------------------------------------------------------------------------------- 1 | `include "top.v" 2 | 3 | module test_bench(); 4 | reg clk; 5 | reg reset_switch; 6 | wire reset; 7 | reg rx; 8 | wire tx; 9 | 10 | // module instantiation 11 | top top_instance1 ( 12 | .clk(clk), 13 | .reset_switch(reset_switch), 14 | .reset(reset), 15 | .rx(rx), 16 | .tx(tx) 17 | ); 18 | 19 | initial begin 20 | $dumpfile("simulation.vcd"); 21 | $dumpvars(0, 22 | clk, 23 | reset_switch, 24 | reset, 25 | rx, 26 | tx 27 | ); 28 | end 29 | 30 | initial begin 31 | // initializing registers 32 | clk = 0; 33 | reset_switch = 0; 34 | rx = 0; 35 | 36 | // add stimulus here 37 | 38 | 39 | end 40 | 41 | initial begin 42 | #1000 $finish; 43 | end 44 | 45 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/sigmoid_mark3/user_defined_modules/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/sigmoid_mark5/user_defined_modules/sigmoid.ucf: -------------------------------------------------------------------------------- 1 | NET clk LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET tx LOC = B8; 5 | NET rx LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET reset_switch LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET reset LOC = P15; 10 | 11 | #// OTHER SIGNALS 12 | #NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/sigmoid_mark5/user_defined_modules/sigmoid/sigmoid.v: -------------------------------------------------------------------------------- 1 | `include "utils/sigmoid_combinational.v" 2 | 3 | module sigmoid( 4 | input wire clk, 5 | input wire reset, 6 | input wire [17:0] x1, 7 | output reg [47:0] fixed_op 8 | ); 9 | 10 | wire [47:0] fixed_op_next; 11 | 12 | sigmoid_combinational sigmoid_combinational_instance1( 13 | .x1(x1), 14 | .fixed_op(fixed_op_next) 15 | ); 16 | 17 | always @(posedge(clk),posedge(reset)) begin 18 | if(reset) begin 19 | fixed_op <= 0; 20 | end else begin 21 | fixed_op <= fixed_op_next; 22 | end 23 | end 24 | 25 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/sigmoid_mark5/user_defined_modules/top_tb.v: -------------------------------------------------------------------------------- 1 | `include "top.v" 2 | 3 | module test_bench(); 4 | reg clk; 5 | reg reset_switch; 6 | wire reset; 7 | reg rx; 8 | wire tx; 9 | wire [7:0] tx_data_in_test; 10 | 11 | // module instantiation 12 | top top_instance1 ( 13 | .clk(clk), 14 | .reset_switch(reset_switch), 15 | .reset(reset), 16 | .rx(rx), 17 | .tx(tx), 18 | .tx_data_in_test(tx_data_in_test) 19 | ); 20 | 21 | initial begin 22 | $dumpfile("simulation.vcd"); 23 | $dumpvars(0, 24 | clk, 25 | reset_switch, 26 | reset, 27 | rx, 28 | tx, 29 | tx_data_in_test 30 | ); 31 | end 32 | 33 | initial begin 34 | // initializing registers 35 | clk = 0; 36 | reset_switch = 0; 37 | rx = 0; 38 | end 39 | 40 | initial begin 41 | reset_switch = 0; 42 | #2 reset_switch = 1; 43 | end 44 | 45 | always begin 46 | #1 clk = ~ clk; 47 | end 48 | 49 | initial begin 50 | #100 rx = 0; 51 | #10000 rx = 1; 52 | end 53 | 54 | initial begin 55 | #10000 $finish; 56 | end 57 | 58 | endmodule -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/sigmoid_mark5/user_defined_modules/uart_core/uart_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | NET RX LOC = A8; 6 | 7 | // RESET CONNECTIONS 8 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 9 | NET RESET LOC = P15; 10 | 11 | // OTHER SIGNALS 12 | NET RX_DONE_TICK LOC = P16; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/uart/04_uart_receiver_ssd_testing/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/uart/uart_rx_ssd_test/user_defined_modules/integer_seven_segment_display_controller/integer_seven_segment_display_controller.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // OTHER CONNECTIONS 23 | NET NUMBER_CHANGE_TICK LOC = N15; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/uart/uart_rx_ssd_test/user_defined_modules/uart_receiver_ssd_test.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | 3 | // SEVEN SEGMENT DISPLAY CONNECTIONS 4 | NET LED1_CONTROL_SIGNAL LOC = B3; 5 | NET LED2_CONTROL_SIGNAL LOC = A2; 6 | NET LED3_CONTROL_SIGNAL LOC = B2; 7 | NET LED_CHANGE_TICK LOC = P16; 8 | 9 | NET DISPLAY_BITS[0] LOC = A5; 10 | NET DISPLAY_BITS[1] LOC = C6; 11 | NET DISPLAY_BITS[2] LOC = D6; 12 | NET DISPLAY_BITS[3] LOC = C5; 13 | NET DISPLAY_BITS[4] LOC = C4; 14 | NET DISPLAY_BITS[5] LOC = A4; 15 | NET DISPLAY_BITS[6] LOC = B4; 16 | NET DISPLAY_BITS[7] LOC = A3; 17 | 18 | // RESET CONNECTIONS 19 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 20 | NET RESET LOC = P15; 21 | 22 | // UART CONNECTIONS 23 | NET RX LOC = A8; -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/uart_receiver_verilog_modules/counter.v: -------------------------------------------------------------------------------- 1 | module counter #( 2 | parameter N = 8, 3 | parameter OVERFLOW_VALUE = 2**N-1 4 | )( 5 | input wire clk, 6 | input wire count_increment_clk, 7 | input wire reset, // reset should be available for atleast 2 clock cycles 8 | output reg [N-1:0] count, 9 | output reg overflow 10 | ); 11 | 12 | //signal declarations 13 | 14 | initial begin 15 | count = 0; 16 | overflow = 0; 17 | end 18 | 19 | always @(posedge(clk)) begin 20 | if(reset) begin 21 | count = 0; 22 | end 23 | end 24 | 25 | always @(posedge(count_increment_clk)) begin 26 | if(count == OVERFLOW_VALUE) begin 27 | count = 0; 28 | overflow = 1; 29 | end 30 | else begin 31 | overflow = 0; 32 | count = count + 1; 33 | end 34 | 35 | end 36 | 37 | endmodule 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /FPGA/ironstein_fpga_working_directory/xilinx_ise_project_files/uart_receiver_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 4'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | // state declarations 10 | localparam 11 | off = 1'b0, 12 | on = 1'b1; 13 | 14 | // signal declarations 15 | reg state_reg = off; 16 | reg state_next = off; 17 | reg [3:0] count = 0; 18 | 19 | // ---------- next state logic -------------- 20 | always @(posedge(clk)) begin 21 | state_reg = state_next; 22 | count = count + 1; 23 | end 24 | 25 | always @(generate_pulse) begin 26 | if(state_reg == off) begin 27 | count = 0; 28 | pulse = 1; 29 | state_next = on; 30 | end 31 | end 32 | 33 | always @(count) begin 34 | if(state_reg == on) begin 35 | if(count == PULSE_WIDTH) begin 36 | pulse = 0; 37 | state_next = off; 38 | end 39 | end 40 | end 41 | //------------------------------------------ 42 | 43 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/CLA/CLA.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/CLA/CLA.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/CLA/testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module testbench; 4 | 5 | // Inputs 6 | reg [7:0] A; 7 | reg [7:0] B; 8 | reg Cin; 9 | 10 | // Outputs 11 | wire [7:0] S; 12 | wire Carry; 13 | wire PG; 14 | wire GG; 15 | 16 | integer i; 17 | 18 | // Instantiate the Unit Under Test (UUT) 19 | CLA uut ( 20 | .A(A), 21 | .B(B), 22 | .S(S), 23 | .Carry(Carry), 24 | .PG(PG), 25 | .GG(GG), 26 | .Cin(Cin) 27 | ); 28 | 29 | initial begin 30 | // Initialize Inputs 31 | A = 0; 32 | B = 0; 33 | Cin = 0; 34 | end 35 | 36 | initial 37 | $monitor ( "A(%b) + B(%b) = carry sum(%b %b)",A ,B ,Carry ,S ); 38 | always @ (A or B or S) 39 | begin 40 | for (i = 10000; i < 65536 ; i = i + 1) 41 | #10 {A,B}= i; 42 | //A = 7'b101111001 ; B = 7'b101111100 ; Cin = 0 ; 43 | //#200 $stop; 44 | end 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/FourBitAdder/FourBitFullAdder.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/FourBitAdder/FourBitFullAdder.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/FourBitAdder/FourBitFullAdder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module FourBitFullAdder( 3 | input [3:0]A,B, 4 | output [3:0]Sum, 5 | output Cout 6 | ); 7 | wire Cin; 8 | assign Cin = 1'b0; 9 | wire carry0; 10 | wire carry1; 11 | wire carry2; 12 | 13 | FullAdder1Bit s1 (.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(carry0) ); 14 | FullAdder1Bit s2 (.A(A[1]), .B(B[1]), .Cin(carry0), .Sum(Sum[1]), .Cout(carry1) ); 15 | FullAdder1Bit s3 (.A(A[2]), .B(B[2]), .Cin(carry1), .Sum(Sum[2]), .Cout(carry2) ); 16 | FullAdder1Bit s4 (.A(A[3]), .B(B[3]), .Cin(carry2), .Sum(Sum[3]),.Cout(Cout) ); 17 | endmodule 18 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/FourBitAdder/ipcore_dir/try_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_SP_INST CLK_FEEDBACK = 1X; 5 | INST DCM_SP_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_SP_INST CLKFX_DIVIDE = 1; 7 | INST DCM_SP_INST CLKFX_MULTIPLY = 4; 8 | INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_SP_INST CLKIN_PERIOD = 10.000; 10 | INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_SP_INST FACTORY_JF = C080; 16 | INST DCM_SP_INST PHASE_SHIFT = 0; 17 | INST DCM_SP_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/FourBitAdder/try_arwz.ucf: -------------------------------------------------------------------------------- 1 | # Generated by Xilinx Architecture Wizard 2 | # --- UCF Template Only --- 3 | # Cut and paste these attributes into the project's UCF file, if desired 4 | INST DCM_SP_INST CLK_FEEDBACK = 1X; 5 | INST DCM_SP_INST CLKDV_DIVIDE = 2.0; 6 | INST DCM_SP_INST CLKFX_DIVIDE = 1; 7 | INST DCM_SP_INST CLKFX_MULTIPLY = 4; 8 | INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; 9 | INST DCM_SP_INST CLKIN_PERIOD = 10.000; 10 | INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; 11 | INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; 12 | INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; 13 | INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; 14 | INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; 15 | INST DCM_SP_INST FACTORY_JF = C080; 16 | INST DCM_SP_INST PHASE_SHIFT = 0; 17 | INST DCM_SP_INST STARTUP_WAIT = FALSE; 18 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/FullAdder1Bit/FullAdder1Bit.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/FullAdder1Bit/FullAdder1Bit.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/FullAdder1Bit/FullAdder1Bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module FullAdder1Bit( 3 | input A,B,Cin, 4 | output Sum,Cout 5 | ); 6 | assign Sum = A ^ B ^ Cin ; 7 | assign Cout= A & B | B & Cin | Cin & A ; 8 | endmodule 9 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/FullAdder1Bit/FullAdder1Bit_PlanAhead/FullAdder1Bit_PlanAhead.runs/impl_1/FullAdder1Bit.ucf: -------------------------------------------------------------------------------- 1 | 2 | #################################################################################### 3 | # Generated by PlanAhead 14.7 built on 'Fri Sep 27 19:29:51 MDT 2013' by 'xbuild' 4 | #################################################################################### 5 | 6 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/FullAdder1Bit/TestBench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module TestBench; 4 | 5 | // Inputs 6 | reg A; 7 | reg B; 8 | reg Cin; 9 | 10 | // Outputs 11 | wire Sum; 12 | wire Cout; 13 | 14 | integer i; 15 | // Instantiate the Unit Under Test (UUT) 16 | FullAdder1Bit uut ( 17 | .A(A), 18 | .B(B), 19 | .Cin(Cin), 20 | .Sum(Sum), 21 | .Cout(Cout) 22 | ); 23 | 24 | initial begin 25 | // Initialize Inputs 26 | A = 0; 27 | B = 0; 28 | Cin = 0; 29 | end 30 | 31 | always @ ( A, B, Cin ) 32 | begin 33 | // generate truth table 34 | for ( i = 0; i < 8; i = i + 1 ) 35 | // every 10 ns set a, b, and cin to the binary rep. of i 36 | #10 {A, B, Cin} = i; 37 | 38 | // stop 10ns after last change of inputs 39 | #10 $stop; 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/Multistages/Multistages.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/Multistages/Multistages.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/Multistages/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | 9 | module test; 10 | 11 | // Inputs 12 | reg [0:3] a; 13 | reg [0:3] b; 14 | 15 | // Outputs 16 | wire [0:3] sum; 17 | wire carry; 18 | 19 | integer i; 20 | // Instantiate the Unit Under Test (UUT) 21 | Multistages uut ( 22 | .a(a), 23 | .b(b), 24 | .sum(sum), 25 | .carry(carry) 26 | ); 27 | 28 | initial begin 29 | // Initialize Inputs 30 | a = 0; 31 | b = 0; 32 | end 33 | initial 34 | $monitor( "a(%b) + b(%b) = carry sum(%b %b)", a, b, carry, sum ); 35 | always @(a or b) 36 | begin 37 | 38 | for ( i = 0; i< 16 * 16; i = i + 1 ) 39 | #10 {a,b} = i; 40 | end 41 | // #10 $stop; 42 | 43 | 44 | endmodule 45 | 46 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/OR/ThreeInputExorGate.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:08:39 10/25/2015 7 | // Design Name: 8 | // Module Name: ThreeInputExorGate 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ThreeInputExorGate( 22 | input i1, 23 | input i2, 24 | input i3, 25 | output Output 26 | ); 27 | 28 | xor (Output,i1,i2,i3); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/OR/ThreeInputOrGate.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/OR/ThreeInputOrGate.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/OR/ThreeInputOrGate.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ThreeInputOrGate( 3 | input i1, 4 | input i2, 5 | input i3, 6 | output gateOutput 7 | ); 8 | 9 | or(gateOutput, i1 , i2 , i3); 10 | endmodule 11 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/SingleStage/SingleStage.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:22:21 10/30/2015 7 | // Design Name: 8 | // Module Name: SingleStage 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module SingleStage( 22 | input a, 23 | input b, 24 | input cin, 25 | output cout, 26 | output s 27 | ); 28 | assign s = a ^ b ^ cin; 29 | assign cout = (a & b) | (a & cin) | (b & cin); 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/all primitive test projects/clock_gen/clock_.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/all primitive test projects/clock_gen/clock_.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/dsp_slice_test/kishores_dsp_slice_test/dsp_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 08:28:45 02/08/2016 7 | // Design Name: 8 | // Module Name: dsp_test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module dsp_test( 22 | input clock, 23 | input [17:0] a, 24 | input [17:0] b, 25 | input [47:0] c, 26 | output [47:0] MAC_op 27 | ); 28 | 29 | dsp48_macro MAC0 (clock,a,b,c,MAC_op); //Instantiate a DSP48 slice 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/project_1/project_1.srcs/constrs_1/imports/Sources/bft.ucf: -------------------------------------------------------------------------------- 1 | 2 | NET "wbClk" TNM_NET = "wbClk"; 3 | TIMESPEC TS_wbClk = PERIOD "wbClk" 9 ns; 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/test/Multipler1818.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/test/Multipler1818.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/test/testbench.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/test/testbench.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/try/basis.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/try/basis.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/try/basis2.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/FPGA/rana_fpga_working_dirctory/try/basis2.ucf -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/try/basys.ucf: -------------------------------------------------------------------------------- 1 | NET "D" LOC = "P11"; 2 | NET "Q" LOC = "M5"; 3 | NET "clk" LOC = "B8"; -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/try/or_gate.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:56:09 10/24/2015 7 | // Design Name: 8 | // Module Name: or_gate 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module or_gate(A,B,Y); 22 | 23 | input A , B ; 24 | 25 | output Y; 26 | 27 | always @ (A==1 or B ==1) 28 | 29 | Y = 1; 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core/baudrate_generator.v: -------------------------------------------------------------------------------- 1 | module baudrate_tick_generator #( 2 | parameter baudrate = 32'd9600, 3 | parameter frequency = 32'd100000000 // in Hz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | // state declaration 9 | localparam 10 | off = 1'b0, 11 | on = 1'b1; 12 | 13 | // signal declaration 14 | reg [32:0] count; 15 | reg [32:0] count_threshold = (frequency)/(baudrate); 16 | reg [32:0] tick_threshold = 5; 17 | reg state_reg,state_next; 18 | 19 | initial begin 20 | tick = 1'b0; 21 | count = 32'b0; 22 | state_reg = 1'b0; 23 | end 24 | 25 | always @(posedge(clk)) begin 26 | count = count + 1; 27 | state_reg = state_next; 28 | end 29 | 30 | always @* begin 31 | state_next = state_reg; 32 | case(state_reg) 33 | off : 34 | if(count == count_threshold) begin 35 | state_next = on; 36 | count = 0; 37 | tick = 1; 38 | end 39 | on : 40 | if(count == tick_threshold) begin 41 | state_next = off; 42 | tick = 0; 43 | end 44 | endcase 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 4'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | // state declarations 10 | localparam 11 | off = 1'b0, 12 | on = 1'b1; 13 | 14 | // signal declarations 15 | reg state_reg = off; 16 | reg state_next = off; 17 | reg [3:0] count = 0; 18 | 19 | // ---------- next state logic -------------- 20 | always @(posedge(clk)) begin 21 | state_reg = state_next; 22 | count = count + 1; 23 | end 24 | 25 | always @(generate_pulse) begin 26 | if(state_reg == off) begin 27 | count = 0; 28 | pulse = 1; 29 | state_next = on; 30 | end 31 | end 32 | 33 | always @(count) begin 34 | if(state_reg == on) begin 35 | if(count == PULSE_WIDTH) begin 36 | pulse = 0; 37 | state_next = off; 38 | end 39 | end 40 | end 41 | //------------------------------------------ 42 | 43 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core/uart_transmitter_core_test.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | NET INDICATOR_LED LOC = P15; 3 | NET TICK_GENERATOR_TICK LOC = P16; 4 | NET TX LOC = B8; -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core/uart_transmitter_core_verilog_modules/baudrate_generator.v: -------------------------------------------------------------------------------- 1 | module baudrate_tick_generator #( 2 | parameter baudrate = 32'd9600, 3 | parameter frequency = 32'd100000000 // in Hz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | // state declaration 9 | localparam 10 | off = 1'b0, 11 | on = 1'b1; 12 | 13 | // signal declaration 14 | reg [32:0] count = 0, tick_count = 0; 15 | reg [32:0] count_threshold = (frequency)/(baudrate*32); 16 | reg [32:0] tick_threshold = 1; 17 | 18 | initial begin 19 | tick = 1'b0; 20 | count = 32'b0; 21 | end 22 | 23 | always @(posedge(clk)) begin 24 | if(count == count_threshold) begin 25 | tick <= 1; 26 | count <= 0; 27 | tick_count <= 0; 28 | end else begin 29 | if(tick_count != tick_threshold) begin 30 | tick_count <= tick_count + 1; 31 | end else begin 32 | tick <= 0; 33 | end 34 | count <= count + 1; 35 | end 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core/uart_transmitter_core_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core/uart_transmitter_core_verilog_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core_mark2/uart_transmitter_core_verilog_modules/baudrate_generator.v: -------------------------------------------------------------------------------- 1 | module baudrate_tick_generator #( 2 | parameter baudrate = 32'd9600, 3 | parameter frequency = 32'd100000000 // in Hz 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | // state declaration 9 | localparam 10 | off = 1'b0, 11 | on = 1'b1; 12 | 13 | // signal declaration 14 | reg [31:0] count = 0, tick_count = 0; 15 | reg [31:0] count_threshold = (frequency)/(baudrate*2); 16 | reg [31:0] tick_threshold = 1; 17 | 18 | initial begin 19 | tick = 1'b0; 20 | count = 32'b0; 21 | end 22 | 23 | always @(posedge(clk)) begin 24 | if(count == count_threshold) begin 25 | tick <= 1; 26 | count <= 0; 27 | tick_count <= 0; 28 | end else begin 29 | if(tick_count != tick_threshold) begin 30 | tick_count <= tick_count + 1; 31 | end else begin 32 | tick <= 0; 33 | end 34 | count <= count + 1; 35 | end 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core_mark2/uart_transmitter_core_verilog_modules/final_testbenches/baudrate_tick_generator_tb.v: -------------------------------------------------------------------------------- 1 | module stimulus(); 2 | reg CLK; 3 | wire TICK; 4 | 5 | localparam BAUDRATE = 32'd115200; 6 | 7 | baudrate_tick_generator #(.baudrate(BAUDRATE)) 8 | b( 9 | .clk(CLK), 10 | .tick(TICK) 11 | ); 12 | 13 | initial 14 | CLK = 1'b0; 15 | 16 | always 17 | #1 CLK = ~ CLK; 18 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core_mark2/uart_transmitter_core_verilog_modules/final_testbenches/pulse_generator_tb.v: -------------------------------------------------------------------------------- 1 | module stimulus( 2 | input wire CLK, 3 | output wire GENERATED_PULSE, 4 | output wire TICK 5 | ); 6 | 7 | tick_generator #(.tick_time(32'd6000),.frequency(32'd100000)) 8 | t( 9 | .clk(CLK), 10 | .tick(TICK) 11 | ); 12 | 13 | pulse_generator #(.PULSE_WIDTH(32'd1000000)) 14 | p( 15 | .clk(CLK), 16 | .generate_pulse(TICK), 17 | .pulse(GENERATED_PULSE) 18 | ); 19 | 20 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core_mark2/uart_transmitter_core_verilog_modules/final_testbenches/tick_generator_tb.v: -------------------------------------------------------------------------------- 1 | module stimulus( 2 | input wire CLK, 3 | output wire TICK 4 | ); 5 | 6 | tick_generator #(.tick_time(32'd5000),.frequency(32'd100000)) 7 | t( 8 | .clk(CLK), 9 | .tick(TICK) 10 | ); 11 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core_mark2/uart_transmitter_core_verilog_modules/pulse_generator.v: -------------------------------------------------------------------------------- 1 | module pulse_generator #( 2 | parameter PULSE_WIDTH = 32'd1 3 | )( 4 | input wire clk, 5 | input wire generate_pulse, 6 | output reg pulse 7 | ); 8 | 9 | reg [31:0] count = 0; 10 | reg previous_pulse_value; 11 | 12 | initial begin 13 | #1 previous_pulse_value = generate_pulse; 14 | pulse = 1'b0; 15 | end 16 | 17 | always @(posedge(clk)) begin 18 | 19 | if(previous_pulse_value != generate_pulse) begin 20 | count = 0; 21 | pulse = 1'b1; 22 | previous_pulse_value = generate_pulse; 23 | end 24 | 25 | if(count == PULSE_WIDTH) begin 26 | pulse <= 1'b0; 27 | end else begin 28 | count <= count + 1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core_mark2/uart_transmitter_core_verilog_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | reg [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | count = count + 1; 18 | if(count == count_threshold) begin 19 | count = 0; 20 | tick = ~ tick; 21 | end 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_core_mark2/uart_transmitter_core_verilog_modules/uart_transmitter_core_mark2.ucf: -------------------------------------------------------------------------------- 1 | #NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 2 | #NET TICK LOC = P15; 3 | #NET GENERATED_PULSE LOC = P16; 4 | 5 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100MHz clock signal 6 | NET INDICATOR_LED LOC = P15; 7 | NET TICK_GENERATOR_TICK LOC = P16; 8 | NET TX LOC = B8; -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_mark6_self_implemented/user_defined_modules/tick_generator.v: -------------------------------------------------------------------------------- 1 | module tick_generator #( 2 | parameter tick_time = 32'd1000, 3 | parameter frequency = 32'd100000 4 | )( 5 | input wire clk, 6 | output reg tick); 7 | 8 | reg [32:0] count; 9 | localparam [32:0] count_threshold = tick_time * frequency / 2; 10 | 11 | initial begin 12 | tick = 1'b0; 13 | count = 32'b0; 14 | end 15 | 16 | always @(posedge(clk)) begin 17 | if(count == count_threshold) begin 18 | count = 32'b0; 19 | tick = 1'b1; 20 | end else begin 21 | tick = 1'b0; 22 | count = count + 1; 23 | end 24 | end 25 | 26 | endmodule -------------------------------------------------------------------------------- /FPGA/rana_fpga_working_dirctory/uart_transmitter_mark6_self_implemented/user_defined_modules/transmitter_core.ucf: -------------------------------------------------------------------------------- 1 | NET CLK LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz; // 100 MHz clock signal 2 | 3 | // UART CONNECTIONS 4 | NET TX LOC = B8; 5 | 6 | // RESET CONNECTIONS 7 | NET RESET_SWITCH LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; 8 | NET RESET LOC = P15; 9 | 10 | // OTHER SIGNALS 11 | NET BUSY LOC = P16; -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # handwriting-recognition-using-neural-networks-on-FPGA-final-year-project 2 | # Collaborators: 3 | - [Riyansh Karani](https://github.com/RiyanshKarani011235) 4 | - [Dhruv Reshamwala](https://github.com/dhr9) 5 | - [Akash Rana](https://github.com/akash9182) 6 | 7 | This is work in Progress. 8 | 9 | Done in collaboration with [dhr9](https://github.com/dhr9), for the other half of this project, please visit [his page](https://github.com/dhr9/HandwritingRecognition_using_ImageProcessing_and_NeuralNetworks_on_an_FPGA) 10 | -------------------------------------------------------------------------------- /image_processing/.gitignore: -------------------------------------------------------------------------------- 1 | image processing books/ -------------------------------------------------------------------------------- /image_processing/C_library_for_image_processing/01 - Introduction to python ctypes library, and compilation of C code/convolution.c: -------------------------------------------------------------------------------- 1 | #import 2 | 3 | void convolution(int *array,int *kernel,int array_height,int array_width,int kernel_height,int kernel_width) { 4 | int i=0; 5 | } -------------------------------------------------------------------------------- /image_processing/C_library_for_image_processing/01 - Introduction to python ctypes library, and compilation of C code/convolution.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/image_processing/C_library_for_image_processing/01 - Introduction to python ctypes library, and compilation of C code/convolution.o -------------------------------------------------------------------------------- /image_processing/C_library_for_image_processing/01 - Introduction to python ctypes library, and compilation of C code/libconvolution.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/image_processing/C_library_for_image_processing/01 - Introduction to python ctypes library, and compilation of C code/libconvolution.so -------------------------------------------------------------------------------- /image_processing/C_library_for_image_processing/01 - Introduction to python ctypes library, and compilation of C code/locate_file.py: -------------------------------------------------------------------------------- 1 | 2 | def locate_file() : 3 | working_directory = '' 4 | for element in __file__.split('/')[:-1] : 5 | working_directory += element + '/' 6 | return working_directory -------------------------------------------------------------------------------- /image_processing/C_library_for_image_processing/02 - Basics of writing C code and accessing C functions from python/convolution.c: -------------------------------------------------------------------------------- 1 | #import 2 | #include 3 | 4 | void convolution(int *array, int length) { 5 | int i; 6 | for(i=0;i 2 | #include 3 | 4 | void convolution(int *array, int rows, int columns) { 5 | int i,j; 6 | int return_array[rows][columns]; 7 | for(i=0;i 2 | 3 | void convolution(int *image,int *kernel,int image_width, int image_height, int kernel_size, int kernel_normalizer) { 4 | 5 | int image_starting_x = 0; 6 | int image_starting_y = 0; 7 | int image_ending_x = image_width; 8 | int image_ending_y = image_height; 9 | 10 | int i,j,u,v; 11 | int sum; 12 | j=0; 13 | 14 | for(i=image_starting_y;i 2 | 3 | void convolution(int *image,int *kernel,int image_width, int image_height, int kernel_size, int kernel_normalizer) { 4 | 5 | int image_starting_x = 0; 6 | int image_starting_y = 0; 7 | int image_ending_x = image_width; 8 | int image_ending_y = image_height; 9 | 10 | int i,j,u,v; 11 | int sum; 12 | j=0; 13 | 14 | for(i=image_starting_y;i 2 | 3 | void convolution(int *image,int *kernel,int image_width, int image_height, int kernel_size, int kernel_normalizer) { 4 | 5 | int image_starting_x = 0; 6 | int image_starting_y = 0; 7 | int image_ending_x = image_width; 8 | int image_ending_y = image_height; 9 | 10 | int i,j,u,v; 11 | int sum; 12 | j=0; 13 | 14 | for(i=image_starting_y;i 2 | 3 | static PyObject* helloworld(PyObject* self) 4 | { 5 | return Py_BuildValue("s", "Hello, Python extensions!!"); 6 | } 7 | 8 | static char helloworld_docs[] = 9 | "helloworld( ): Any message you want to put here!!\n"; 10 | 11 | static PyMethodDef helloworld_funcs[] = { 12 | {"helloworld", (PyCFunction)helloworld, 13 | METH_NOARGS, helloworld_docs}, 14 | {NULL} 15 | }; 16 | 17 | void inithelloworld(void) 18 | { 19 | Py_InitModule3("helloworld", helloworld_funcs, 20 | "Extension module example!"); 21 | } -------------------------------------------------------------------------------- /image_processing/image_processing.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/image_processing/image_processing.pyc -------------------------------------------------------------------------------- /image_processing/ipython notebooks/c_python_binding_test.c: -------------------------------------------------------------------------------- 1 | 2 | #include -------------------------------------------------------------------------------- /image_processing/ipython notebooks/image_processing_mark3/_convolution.py: -------------------------------------------------------------------------------- 1 | 2 | import numpy 3 | import ctypes 4 | 5 | _convolution_ = numpy.ctypeslib.load_library('convolution','.') 6 | _convolution_.array_testing.argtypes = [ctypes.c_int] 7 | _convolution_.array_testing.restype = ctypes.c_void_p 8 | 9 | def array_testing(array) : 10 | _convolution_.array_testing(array) 11 | 12 | # array = [1,2,2,3,4,5,56,6,7,7,8,8,9] 13 | # array_testing(array) -------------------------------------------------------------------------------- /image_processing/ipython notebooks/image_processing_mark3/_convolution.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/image_processing/ipython notebooks/image_processing_mark3/_convolution.pyc -------------------------------------------------------------------------------- /image_processing/ipython notebooks/image_processing_mark3/convolution.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | 4 | void array_testing(int *pointer) { 5 | int i; 6 | for(i=0;i<10;i++) { 7 | printf("%d",pointer[i]); 8 | } 9 | } -------------------------------------------------------------------------------- /image_processing/ipython notebooks/image_processing_mark3/convolution.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/image_processing/ipython notebooks/image_processing_mark3/convolution.o -------------------------------------------------------------------------------- /image_processing/ipython notebooks/image_processing_mark3/convolution.so: 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-------------------------------------------------------------------------------- 1 | { 2 | "cells": [], 3 | "metadata": {}, 4 | "nbformat": 4, 5 | "nbformat_minor": 0 6 | } 7 | -------------------------------------------------------------------------------- /image_processing/ipython notebooks/python C extension testing/mark1/__pycache__/_helloworld.cpython-34.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/image_processing/ipython notebooks/python C extension testing/mark1/__pycache__/_helloworld.cpython-34.pyc -------------------------------------------------------------------------------- /image_processing/ipython notebooks/python C extension testing/mark1/__pycache__/superduper.cpython-34.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ironstein0/handwriting-recognition-using-neural-networks-on-FPGA-final-year-project/a73e2af0d2e326b3041ef3d66d8e1ce8f93e7514/image_processing/ipython notebooks/python C extension testing/mark1/__pycache__/superduper.cpython-34.pyc -------------------------------------------------------------------------------- /image_processing/ipython notebooks/python C extension testing/mark1/_helloworld.py: -------------------------------------------------------------------------------- 1 | 2 | def pqrs() : 3 | print('asdg') 4 | 5 | import numpy 6 | import ctypes 7 | 8 | _helloworld_ = numpy.ctypeslib.load_library('helloworld','.') 9 | 10 | _helloworld_.hello.argtypes = [ctypes.c_int] 11 | _helloworld_.hello.restype = ctypes.c_int 12 | 13 | def m(n) : 14 | print('hmm') 15 | 16 | def rana(n,m) : 17 | print(_helloworld_.hello(n)) -------------------------------------------------------------------------------- /image_processing/ipython notebooks/python C extension testing/mark1/helloworld.c: -------------------------------------------------------------------------------- 1 | 2 | #include 3 | int i; 4 | int hello(int n) { 5 | int val = n*1000; 6 | for(i=0;i 3 | 4 | void for_loop_test(int n) { 5 | int i; 6 | for(i=0;i 3 | 4 | void for_loop_test_without_register_values(int n) { 5 | int i; 6 | int j; 7 | for(i=0;i 2 | 3 | static PyObject* helloworld(PyObject* self) 4 | { 5 | return Py_BuildValue("s", "Hello, Python extensions!!"); 6 | } 7 | 8 | static char helloworld_docs[] = 9 | "helloworld( ): Any message you want to put here!!\n"; 10 | 11 | static PyMethodDef helloworld_funcs[] = { 12 | {"helloworld", (PyCFunction)helloworld, 13 | METH_NOARGS, helloworld_docs}, 14 | {NULL} 15 | }; 16 | 17 | void inithelloworld(void) 18 | { 19 | Py_InitModule3("helloworld", helloworld_funcs, 20 | "Extension module example!"); 21 | } -------------------------------------------------------------------------------- /image_processing/setup.py: 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