├── README.md ├── data ├── compressed.out ├── lena256bw.png └── lena256bw.txt ├── documentation ├── synthesis_schematics │ ├── complete_design.pdf │ ├── top1.pdf │ ├── top2.pdf │ ├── top3.pdf │ ├── top_initial.pdf │ ├── waveleticc1.pdf │ ├── waveleticc2.pdf │ └── waveleticc3.pdf ├── wavelet-solution-documentation_v1.1.docx └── wavelet-solution-documentation_v1.1.pdf ├── for_students ├── README.md ├── data │ └── lena256bw.png ├── image_convert.py └── plot_results.py ├── image_convert.py ├── plot_results.py ├── project ├── .Xil │ ├── PlanAhead-4982-ivan-T530 │ │ └── ngc2edif │ │ │ ├── _xmsgs │ │ │ └── ngc2edif.xmsgs │ │ │ ├── ngc2edif.log │ │ │ └── ramfile.edif │ └── PlanAhead-5228-ivan-T530 │ │ └── ngc2edif │ │ ├── _xmsgs │ │ └── ngc2edif.xmsgs │ │ ├── ngc2edif.log │ │ └── ramfile.edif ├── _xmsgs │ ├── pn_parser.xmsgs │ └── xst.xmsgs ├── controlunit.cmd_log ├── controlunit.lso ├── controlunit.vhd ├── fifomem.lso ├── fifomem.vhd ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── haarhp.lso ├── haarhp.vhd ├── haarlp.lso ├── haarlp.vhd ├── iseconfig │ ├── ramfile.xreport │ ├── top.xreport │ └── wavelet.projectmgr ├── isim.log ├── memcontroler.lso ├── memcontroler.vhd ├── pa.fromNcd.tcl ├── pa.fromNetlist.tcl ├── par_usage_statistics.html ├── pepExtractor.prj ├── planAhead.ngc2edif.log ├── planAhead_pid4982.debug ├── ram_contents.out ├── ramfile.vhd ├── ramfile_guide.ncd ├── ramnormal.lso ├── ramnormal.vhd ├── tb_fifomem.vhd ├── tb_fifomem.wcfg ├── tb_haarhp.vhd ├── tb_haarhp.wcfg ├── tb_haarlp.vhd ├── tb_ramfile.vhd ├── tb_ramfile_isim_beh1.wdb ├── tb_ramfile_isim_beh2.wdb ├── tb_top.vhd ├── tb_top.wcfg ├── tb_top_isim_beh1.wdb ├── top.cmd_log ├── top.lso ├── top.ngc ├── top.ngr ├── top.prj ├── top.stx ├── top.syr ├── top.vhd ├── top.xst ├── top_envsettings.html ├── top_summary.html ├── top_syr.html ├── top_xst.xrpt ├── transmitraw.lso ├── transmitraw.vhd ├── wavelet.gise ├── wavelet.xise ├── waveleticc.lso ├── waveleticc.vhd ├── webtalk_pn.xml └── xst │ └── work │ ├── work.vdbl │ └── work.vdbx └── vhdl_only ├── controlunit.vhd ├── fifomem.vhd ├── haarhp.vhd ├── haarlp.vhd ├── memcontroler.vhd ├── ramfile.vhd ├── ramnormal.vhd ├── tb_fifomem.vhd ├── tb_haarhp.vhd ├── tb_haarlp.vhd ├── tb_ramfile.vhd ├── tb_top.vhd ├── top.vhd ├── transmitraw.vhd └── waveleticc.vhd /README.md: -------------------------------------------------------------------------------- 1 | ## wavelet-image-compression 2 | Simple FPGA-based Wavelet Image Compression component and an example usage. 3 | This is a sample solution to our laboratory exercise *Image compression with Discrete Wavelet Transform* published in the scope of the EU-FP7 project [Embedded Engineering Learning Platform](http://www.e2lp.org/). 4 | Link to the laboratory exercise containing full text of the assignment: [Image compression with Discrete Wavelet Transform](http://moodle.e2lp.org/course/view.php?id=5§ion=65) (select ```Login as guest```). 5 | Description of the implemented solution can be found [here](documentation/wavelet-solution-documentation_v1.1.pdf). 6 | -------------------------------------------------------------------------------- /data/lena256bw.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/data/lena256bw.png -------------------------------------------------------------------------------- /documentation/synthesis_schematics/complete_design.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/documentation/synthesis_schematics/complete_design.pdf -------------------------------------------------------------------------------- /documentation/synthesis_schematics/top1.pdf: -------------------------------------------------------------------------------- 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/documentation/synthesis_schematics/top_initial.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/documentation/synthesis_schematics/top_initial.pdf -------------------------------------------------------------------------------- /documentation/synthesis_schematics/waveleticc1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/documentation/synthesis_schematics/waveleticc1.pdf -------------------------------------------------------------------------------- /documentation/synthesis_schematics/waveleticc2.pdf: -------------------------------------------------------------------------------- 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/documentation/wavelet-solution-documentation_v1.1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/documentation/wavelet-solution-documentation_v1.1.pdf -------------------------------------------------------------------------------- /for_students/README.md: -------------------------------------------------------------------------------- 1 | This folder contains two scripts for preparing data and rapid testing of obtained results, and a sample input image (a greyscale image of Lena, placed in the data folder). 2 | The scripts are: 3 | 4 | 1. image_convert.py 5 | Converts the sample input image into an array of bytes (stored in ASCII format) in the same data folder. This file can then be loaded using VHDL's file loading function for RAM initialization. 6 | 7 | 2. plot_results.py 8 | Loads and plots the compressed image from 'data/compressed.out' file. The file should be obtained from the simulation (or otherwise from the syntesized component). 9 | 10 | The description of data format expected in 'data/compressed.out': 11 | Normally, after wavelet decomposition, 4 components of the image are given: the approximation image (the one that passed through two low-pass filters (LL)), and three detail components (LH, HL and HH). 12 | The LL component contains the majority of information, and is not compressed. If the image size iz WxH, then the size of the LL components if (W/2)x(H/2). 13 | 14 | The rest 3 components are compressed by counting values that are lower than a given threshold, and storing the information as 2 bytes. 15 | The first byte is the count of consecutive pixels that have values below the threshold, followed by a byte that contains the actuall value of the pixel that follows them. 16 | For an example, consider the following array of values: 17 | 0 1 2 1 0 1 2 2 2 0 15 1 0 12 18 | The compressed instance of this array would be (for a threshold of value 10): 19 | 10 15 2 12 20 | This would read as: 10 zero values (or values below the threshold 10), followed by a value 15, followed by 2 zero values, followed by a value of 12. 21 | 22 | The 'data/compressed.out' contains the following information: 23 | (1) array of exact pixel values of the LL component. There are in total (W/2)x(H/2) data bytes stored. For example, if the original image was 256x256 pixels of resolution, then LL component would have 16384 bytes. 24 | (2) array of compressed values for the LH component. The count of values is not given, but can be obtained implicitly by counting the bytes (i.e. the first byte in the pair denotes the number of zero values, while the second one denotes one single value. Thus the count for one pair should be (num_zero_values + 1). This should be repeated for all pairs). Once the count exceeds 16384, the portion of image corresponding to LH has been read. 25 | (3) array of compressed values for the HL component (same as in (2)). 26 | (4) array of compressed values for the HH component (same as in (2)). 27 | 28 | -------------------------------------------------------------------------------- /for_students/data/lena256bw.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/for_students/data/lena256bw.png -------------------------------------------------------------------------------- /for_students/image_convert.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/python 2 | 3 | import Image 4 | 5 | img = Image.open('data/lena256bw.png'); 6 | [width, height] = img.size; 7 | im = img.load(); 8 | 9 | 10 | fileBytes = []; 11 | 12 | i = 0; 13 | while i < height: 14 | j = 0; 15 | while j < width: 16 | fileBytes.append(im[j, i][0]); 17 | 18 | j += 1; 19 | i += 1; 20 | 21 | 22 | fp = open('data/lena256bw.bin', 'wb'); 23 | newFileByteArray = bytearray(fileBytes) 24 | fp.write(newFileByteArray); 25 | fp.close(); 26 | 27 | fp = open('data/lena256bw.txt', 'w'); 28 | for value in fileBytes: 29 | fp.write('{0:08b}'.format(value) + '\n'); 30 | fp.close(); 31 | -------------------------------------------------------------------------------- /for_students/plot_results.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/python 2 | 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import matplotlib.cm as cm 6 | import Image 7 | 8 | def LoadImage(imagePath, imageWidth, imageHeight): 9 | try: 10 | fp = open(imagePath, 'r'); 11 | lines = fp.readlines(); 12 | fp.close(); 13 | except IOError: 14 | print 'ERROR: Could not open file "%s" for reading! Exiting.' % imagePath; 15 | exit(1); 16 | 17 | retImage = [int(line.strip()) for line in lines]; 18 | retImage = np.array(retImage); 19 | retImage = np.reshape(retImage, (imageWidth, imageHeight)); 20 | 21 | return retImage; 22 | 23 | def CompressImage(originalImage, imageWidth, imageHeight, threshold): 24 | retData = []; 25 | 26 | thresheldImage = ThresholdImage(originalImage, imageWidth, imageHeight, threshold); 27 | 28 | numZero = 0; 29 | totalLength = 0; 30 | 31 | i = 0; 32 | j = 0; 33 | while i < imageHeight: 34 | j = 0; 35 | while j < imageWidth: 36 | if numZero < 255 and originalImage[i][j] == 0: 37 | numZero += 1; 38 | else: 39 | retData.append(numZero); 40 | retData.append(originalImage[i][j]); 41 | numZero = 0; 42 | totalLength += (numZero + 1); 43 | j += 1; 44 | i += 1; 45 | 46 | if (totalLength < (imageWidth * imageHeight)): 47 | print 'Remaining data...'; 48 | 49 | if numZero > 0: 50 | retData.append((numZero - 1)); 51 | retData.append(originalImage[-1][-1]); 52 | else: 53 | retData.append(numZero); 54 | retData.append(originalImage[-1][-1]); 55 | 56 | return retData; 57 | 58 | def LoadCompressed(imagePath, imageWidth, imageHeight): 59 | try: 60 | fp = open(imagePath, 'r'); 61 | lines = fp.readlines(); 62 | fp.close(); 63 | 64 | except IOError: 65 | print 'ERROR: Could not open file "%s" for reading! Exiting.' % imagePath; 66 | exit(1); 67 | 68 | retNumBytes = len(lines); 69 | 70 | numImageLines = (imageWidth / 2) * (imageHeight / 2); 71 | 72 | imageLL = np.zeros((imageWidth/2, imageHeight/2)); 73 | imageLH = np.zeros(numImageLines); 74 | imageHL = np.zeros(numImageLines); 75 | imageHH = np.zeros(numImageLines); 76 | 77 | retImage = np.zeros((imageWidth, imageHeight)); 78 | 79 | linesLL = lines[0:numImageLines]; 80 | imageLL = [int(line.strip()) for line in linesLL]; 81 | imageLL = np.array(imageLL); 82 | imageLL = np.reshape(imageLL, (imageWidth/2, imageHeight/2)); 83 | 84 | currentPixel = 0; 85 | currentComponent = 0; 86 | i = numImageLines; 87 | while i < len(lines): 88 | numZeros = int(lines[i + 0]); 89 | pixelValue = int(lines[i + 1]); 90 | 91 | currentPixel += numZeros; 92 | 93 | if currentComponent == 0: 94 | imageLH[currentPixel] = pixelValue; 95 | elif currentComponent == 1: 96 | imageHL[currentPixel] = pixelValue; 97 | elif currentComponent == 2: 98 | imageHH[currentPixel] = pixelValue; 99 | 100 | currentPixel += 1; 101 | 102 | if currentPixel >= numImageLines: 103 | currentPixel = 0; 104 | currentComponent += 1; 105 | 106 | if currentComponent > 2: 107 | break; 108 | 109 | i += 2; 110 | 111 | imageLH = np.reshape(imageLH, (imageWidth/2, imageHeight/2)); 112 | imageHL = np.reshape(imageHL, (imageWidth/2, imageHeight/2)); 113 | imageHH = np.reshape(imageHH, (imageWidth/2, imageHeight/2)); 114 | 115 | i = 0; 116 | j = 0; 117 | while i < (imageHeight/2): 118 | j = 0; 119 | 120 | while j < (imageWidth/2): 121 | retImage[i][j] = imageLL[i][j]; 122 | retImage[i + imageHeight/2][j] = imageHL[i][j]; 123 | retImage[i][j + imageWidth/2] = imageLH[i][j]; 124 | retImage[i + imageHeight/2][j + imageWidth/2] = imageHH[i][j]; 125 | 126 | j += 1; 127 | i += 1; 128 | 129 | return [imageLL, imageLH, imageHL, imageHH, retImage, retNumBytes]; 130 | 131 | imageWidth = 256; 132 | imageHeight = 256; 133 | threshold = 10; 134 | 135 | imageOriginal = LoadImage('data/lena256bw.txt', imageWidth, imageHeight); 136 | 137 | [imageLL, imageLH, imageHL, imageHH, imageComplete, compressedNumBytes] = LoadCompressed('data/compressed.out', 256, 256); 138 | originalNumBytes = 256 * 256; 139 | 140 | print 'Original image: number of bytes = %d' % originalNumBytes; 141 | print 'Compressed image: number of bytes = %d' % compressedNumBytes; 142 | print 'Compression ratio: %.2f%%' % ((float(compressedNumBytes) / float(originalNumBytes)) * 100.0); 143 | print ' '; 144 | 145 | 146 | 147 | plt.subplot(2, 2, 1); 148 | plt.imshow(imageLL, cmap = cm.Greys_r); 149 | 150 | plt.subplot(2, 2, 2); 151 | plt.imshow(imageLH, cmap = cm.Greys_r); 152 | 153 | plt.subplot(2, 2, 3); 154 | plt.imshow(imageHL, cmap = cm.Greys_r); 155 | 156 | plt.subplot(2, 2, 4); 157 | plt.imshow(imageHH, cmap = cm.Greys_r); 158 | 159 | plt.show() 160 | -------------------------------------------------------------------------------- /image_convert.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/python 2 | 3 | import Image 4 | 5 | img = Image.open('data/lena256bw.png'); 6 | [width, height] = img.size; 7 | im = img.load(); 8 | 9 | 10 | fileBytes = []; 11 | 12 | i = 0; 13 | while i < height: 14 | j = 0; 15 | while j < width: 16 | fileBytes.append(im[j, i][0]); 17 | 18 | j += 1; 19 | i += 1; 20 | 21 | 22 | fp = open('data/lena256bw.bin', 'wb'); 23 | newFileByteArray = bytearray(fileBytes) 24 | fp.write(newFileByteArray); 25 | fp.close(); 26 | 27 | fp = open('data/lena256bw.txt', 'w'); 28 | for value in fileBytes: 29 | fp.write('{0:08b}'.format(value) + '\n'); 30 | fp.close(); 31 | -------------------------------------------------------------------------------- /plot_results.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/python 2 | 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import matplotlib.cm as cm 6 | import Image 7 | 8 | def LoadImage(imagePath, imageWidth, imageHeight): 9 | try: 10 | fp = open(imagePath, 'r'); 11 | lines = fp.readlines(); 12 | fp.close(); 13 | except IOError: 14 | print 'ERROR: Could not open file "%s" for reading! Exiting.' % imagePath; 15 | exit(1); 16 | 17 | retImage = [int(line.strip()) for line in lines]; 18 | retImage = np.array(retImage); 19 | retImage = np.reshape(retImage, (imageWidth, imageHeight)); 20 | 21 | return retImage; 22 | 23 | def CompressImage(originalImage, imageWidth, imageHeight, threshold): 24 | retData = []; 25 | 26 | thresheldImage = ThresholdImage(originalImage, imageWidth, imageHeight, threshold); 27 | 28 | numZero = 0; 29 | totalLength = 0; 30 | 31 | i = 0; 32 | j = 0; 33 | while i < imageHeight: 34 | j = 0; 35 | while j < imageWidth: 36 | if numZero < 255 and originalImage[i][j] == 0: 37 | numZero += 1; 38 | else: 39 | retData.append(numZero); 40 | retData.append(originalImage[i][j]); 41 | numZero = 0; 42 | totalLength += (numZero + 1); 43 | j += 1; 44 | i += 1; 45 | 46 | if (totalLength < (imageWidth * imageHeight)): 47 | print 'Remaining data...'; 48 | 49 | if numZero > 0: 50 | retData.append((numZero - 1)); 51 | retData.append(originalImage[-1][-1]); 52 | else: 53 | retData.append(numZero); 54 | retData.append(originalImage[-1][-1]); 55 | 56 | return retData; 57 | 58 | def LoadCompressed(imagePath, imageWidth, imageHeight): 59 | try: 60 | fp = open(imagePath, 'r'); 61 | lines = fp.readlines(); 62 | fp.close(); 63 | 64 | except IOError: 65 | print 'ERROR: Could not open file "%s" for reading! Exiting.' % imagePath; 66 | exit(1); 67 | 68 | retNumBytes = len(lines); 69 | 70 | numImageLines = (imageWidth / 2) * (imageHeight / 2); 71 | 72 | imageLL = np.zeros((imageWidth/2, imageHeight/2)); 73 | imageLH = np.zeros(numImageLines); 74 | imageHL = np.zeros(numImageLines); 75 | imageHH = np.zeros(numImageLines); 76 | 77 | retImage = np.zeros((imageWidth, imageHeight)); 78 | 79 | linesLL = lines[0:numImageLines]; 80 | imageLL = [int(line.strip()) for line in linesLL]; 81 | imageLL = np.array(imageLL); 82 | imageLL = np.reshape(imageLL, (imageWidth/2, imageHeight/2)); 83 | 84 | currentPixel = 0; 85 | currentComponent = 0; 86 | i = numImageLines; 87 | while i < len(lines): 88 | numZeros = int(lines[i + 0]); 89 | pixelValue = int(lines[i + 1]); 90 | 91 | currentPixel += numZeros; 92 | 93 | if currentComponent == 0: 94 | imageLH[currentPixel] = pixelValue; 95 | elif currentComponent == 1: 96 | imageHL[currentPixel] = pixelValue; 97 | elif currentComponent == 2: 98 | imageHH[currentPixel] = pixelValue; 99 | 100 | currentPixel += 1; 101 | 102 | if currentPixel >= numImageLines: 103 | currentPixel = 0; 104 | currentComponent += 1; 105 | 106 | if currentComponent > 2: 107 | break; 108 | 109 | i += 2; 110 | 111 | imageLH = np.reshape(imageLH, (imageWidth/2, imageHeight/2)); 112 | imageHL = np.reshape(imageHL, (imageWidth/2, imageHeight/2)); 113 | imageHH = np.reshape(imageHH, (imageWidth/2, imageHeight/2)); 114 | 115 | i = 0; 116 | j = 0; 117 | while i < (imageHeight/2): 118 | j = 0; 119 | 120 | while j < (imageWidth/2): 121 | retImage[i][j] = imageLL[i][j]; 122 | retImage[i + imageHeight/2][j] = imageHL[i][j]; 123 | retImage[i][j + imageWidth/2] = imageLH[i][j]; 124 | retImage[i + imageHeight/2][j + imageWidth/2] = imageHH[i][j]; 125 | 126 | j += 1; 127 | i += 1; 128 | 129 | return [imageLL, imageLH, imageHL, imageHH, retImage, retNumBytes]; 130 | 131 | imageWidth = 256; 132 | imageHeight = 256; 133 | threshold = 10; 134 | 135 | imageOriginal = LoadImage('data/lena256bw.txt', imageWidth, imageHeight); 136 | 137 | [imageLL, imageLH, imageHL, imageHH, imageComplete, compressedNumBytes] = LoadCompressed('data/compressed.out', 256, 256); 138 | originalNumBytes = 256 * 256; 139 | 140 | print 'Original image: number of bytes = %d' % originalNumBytes; 141 | print 'Compressed image: number of bytes = %d' % compressedNumBytes; 142 | print 'Compression ratio: %.2f%%' % ((float(compressedNumBytes) / float(originalNumBytes)) * 100.0); 143 | print ' '; 144 | 145 | 146 | 147 | plt.subplot(2, 2, 1); 148 | plt.imshow(imageLL, cmap = cm.Greys_r); 149 | 150 | plt.subplot(2, 2, 2); 151 | plt.imshow(imageLH, cmap = cm.Greys_r); 152 | 153 | plt.subplot(2, 2, 3); 154 | plt.imshow(imageHL, cmap = cm.Greys_r); 155 | 156 | plt.subplot(2, 2, 4); 157 | plt.imshow(imageHH, cmap = cm.Greys_r); 158 | 159 | plt.show() 160 | -------------------------------------------------------------------------------- /project/.Xil/PlanAhead-4982-ivan-T530/ngc2edif/_xmsgs/ngc2edif.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No output is written to ramfile.xncf, ignored. 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /project/.Xil/PlanAhead-4982-ivan-T530/ngc2edif/ngc2edif.log: -------------------------------------------------------------------------------- 1 | Release 14.6 - ngc2edif P.68d (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | Reading design ramfile.ngc ... 4 | WARNING:NetListWriters:298 - No output is written to ramfile.xncf, ignored. 5 | Processing design ... 6 | Preping design's networks ... 7 | Preping design's macros ... 8 | finished :Prep 9 | Writing EDIF netlist file ramfile.edif ... 10 | ngc2edif: Total memory usage is 105644 kilobytes 11 | 12 | -------------------------------------------------------------------------------- /project/.Xil/PlanAhead-5228-ivan-T530/ngc2edif/_xmsgs/ngc2edif.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No output is written to ramfile.xncf, ignored. 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /project/.Xil/PlanAhead-5228-ivan-T530/ngc2edif/ngc2edif.log: -------------------------------------------------------------------------------- 1 | Release 14.6 - ngc2edif P.68d (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | Reading design ramfile.ngc ... 4 | WARNING:NetListWriters:298 - No output is written to ramfile.xncf, ignored. 5 | Processing design ... 6 | Preping design's networks ... 7 | Preping design's macros ... 8 | finished :Prep 9 | Writing EDIF netlist file ramfile.edif ... 10 | ngc2edif: Total memory usage is 105644 kilobytes 11 | 12 | -------------------------------------------------------------------------------- /project/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/controlunit.vhd" into library work 12 | 13 | 14 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/fifomem.vhd" into library work 15 | 16 | 17 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/haarhp.vhd" into library work 18 | 19 | 20 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/haarlp.vhd" into library work 21 | 22 | 23 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/memcontroler.vhd" into library work 24 | 25 | 26 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/ramfile.vhd" into library work 27 | 28 | 29 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/ramnormal.vhd" into library work 30 | 31 | 32 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/top.vhd" into library work 33 | 34 | 35 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/transmitraw.vhd" into library work 36 | 37 | 38 | Parsing VHDL file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/waveleticc.vhd" into library work 39 | 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /project/_xmsgs/xst.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | HDL ADVISOR - The RAM <Mram_readyForNextData> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. 9 | 10 | 11 | HDL ADVISOR - The RAM <Mram_weOut> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. 12 | 13 | 14 | The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): 15 | 16 | The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): 17 | 18 | 19 | 20 | -------------------------------------------------------------------------------- /project/controlunit.cmd_log: -------------------------------------------------------------------------------- 1 | vhdtdtfi -prj wavelet -o /home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/controlunit.vhi -module controlunit -template /home/ivan/work/tools/Xilinx/14.6/ISE_DS/ISE//data/vhdlinst.tft -deleteonerror -lib work controlunit.vhd 2 | -------------------------------------------------------------------------------- /project/controlunit.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/controlunit.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 14:05:53 07/29/2014 6 | -- Design Name: 7 | -- Module Name: controlunit - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Implements a state machine which accesses and streams data from the input ROM. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use IEEE.NUMERIC_STD.ALL; 24 | 25 | entity controlunit is 26 | Generic ( IMAGE_WIDTH : integer := 256; 27 | IMAGE_HEIGHT : integer := 256; 28 | ADDR_WIDTH : integer := 16 29 | ); 30 | Port ( clk : in STD_LOGIC; 31 | reset : in STD_LOGIC; 32 | 33 | addrIn : out STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0); 34 | 35 | enRamIn : out STD_LOGIC; 36 | 37 | resetFifoRow : out STD_LOGIC; 38 | weFifoRow : out STD_LOGIC; 39 | resetFifoColumn : out STD_LOGIC; 40 | weFifoColumn : out STD_LOGIC; 41 | 42 | -- isStreamingData : out STD_LOGIC; 43 | isFinishedProcessing : out STD_LOGIC; 44 | 45 | rowReady : out STD_LOGIC; 46 | columnReady : out STD_LOGIC; 47 | readyForNextData : in STD_LOGIC 48 | ); 49 | end controlunit; 50 | 51 | architecture Behavioral of controlunit is 52 | type states is (stateReset, stateReset2, stateStream, stateStream0, stateStream1, stateStream2, stateStream3, stateNewRow, stateNewRow2, stateFinished); 53 | signal currentState : states := stateReset; 54 | signal nextState : states := stateReset; 55 | 56 | signal sigAddrIn : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 57 | signal sigEnRamIn : STD_LOGIC := '0'; 58 | signal sigResetFifoRow, sigWeFifoRow, sigResetFifoColumn, sigWeFifoColumn : STD_LOGIC := '0'; 59 | signal sigIsFinishedProcessing : STD_LOGIC := '0'; 60 | 61 | signal numPixels : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 62 | signal totalNumPixels : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 63 | signal numRows : integer := 0; 64 | 65 | signal sigRowReady : STD_LOGIC := '0'; 66 | signal sigColumnReady : STD_LOGIC := '1'; 67 | 68 | begin 69 | -- Synchronous process of the state machine. 70 | process (clk, reset, nextState) 71 | begin 72 | if reset = '1' then 73 | currentState <= stateReset; 74 | elsif rising_edge(clk) then 75 | -- Perform all synchronous signal changes. These are changes that 76 | -- cannot be performed in the combinational process because they 77 | -- would infer the usage of implicit latches. Example of such a signal 78 | -- is sigAddrIn which counts the current address of the pixel to be 79 | -- analyzed. 80 | if currentState = stateReset then -- Reset all signals used for counting to zero. 81 | numPixels <= (others => '0'); 82 | totalNumPixels <= (others => '0'); 83 | sigColumnReady <= '1'; 84 | sigRowReady <= '0'; 85 | numRows <= 0; 86 | sigAddrIn <= (others => '0'); 87 | 88 | elsif currentState = stateStream0 then -- Increase the counts of pixels, numPixels counts the number of pixels 89 | -- processed in the current row, while totalNumPixels counts the overall 90 | -- pixels of the image processed so far. 91 | numPixels <= numPixels + 1; 92 | totalNumPixels <= totalNumPixels + 1; 93 | sigColumnReady <= not sigColumnReady; -- This signal is used for decimating columns (every other pixel is not 94 | -- taken into account, or in other words, only when sigColumnReady is high 95 | -- the signal will be processed by the memcontroler). 96 | 97 | elsif currentState = stateStream3 then -- Increase the current address for reading input data. 98 | sigAddrIn <= sigAddrIn + 1; 99 | 100 | elsif currentState = stateNewRow then -- If the end of the row has been hit, clear the numPixels count and increase 101 | -- the count of rows processed (numRows). 102 | numRows <= numRows + 1; 103 | numPixels <= (others => '0'); 104 | sigColumnReady <= '0'; 105 | sigRowReady <= not sigRowReady; -- This signal is used for decimating rows (every other row is not 106 | -- taken into account, or in other words, only when sigColumnReady is high 107 | -- the signal will be processed by the memcontroler). 108 | 109 | elsif currentState = stateFinished then -- If we have finished processing the input data, drive the ready signals low. 110 | sigRowReady <= '0'; 111 | sigColumnReady <= '0'; 112 | end if; 113 | 114 | 115 | 116 | -- Change the current state 117 | currentState <= nextState; 118 | 119 | end if; 120 | end process; 121 | 122 | -- Combinational process of the state machine. 123 | process (currentState, numPixels, numRows, readyForNextData) 124 | begin 125 | -- Set the default values for the signals in order to avoid generating latches. 126 | nextState <= stateReset; 127 | sigEnRamIn <= '0'; 128 | sigResetFifoRow <= '0'; 129 | sigWeFifoRow <= '0'; 130 | sigResetFifoColumn <= '0'; 131 | sigWeFifoColumn <= '0'; 132 | sigIsFinishedProcessing <= '0'; 133 | 134 | case currentState is 135 | -- Initialize all components of the design. 136 | when stateReset => -- Drive reset signals high. 137 | sigResetFifoRow <= '1'; 138 | sigResetFifoColumn <= '1'; 139 | nextState <= stateReset2; 140 | when stateReset2 => -- Lower the reset signals. 141 | nextState <= stateStream; 142 | 143 | -- Wait until the memcontroler component (which stores 144 | -- current decomposition values to memory) returns 145 | -- readyForNextData signal. 146 | when stateStream => -- Wait for ready signal to start streaming. 147 | if readyForNextData = '1' then 148 | nextState <= stateStream0; 149 | else 150 | nextState <= stateStream; 151 | end if; 152 | -- Start streaming new pixel of the image from input 153 | -- through FIFO memories and wavelet filters. 154 | when stateStream0 => -- Start streaming. Enable the input ROM. 155 | sigEnRamIn <= '1'; 156 | nextState <= stateStream1; 157 | 158 | when stateStream1 => -- Enable writing new data to the FIFO row component. 159 | sigEnRamIn <= '1'; 160 | sigWeFifoRow <= '1'; 161 | nextState <= stateStream2; 162 | 163 | when stateStream2 => -- Disable writing data to the FIFO row component, and 164 | -- enable writing the filtered data to the FIFO column component. 165 | sigEnRamIn <= '1'; 166 | sigWeFifoColumn <= '1'; 167 | nextState <= stateStream3; 168 | 169 | when stateStream3 => -- Disable writing to all FIFO memories. 170 | sigEnRamIn <= '1'; 171 | 172 | -- Check if we have reached the end of the row. In this case, the FIFO row component needs 173 | -- to be reset, because otherwise we would filter the last pixel of the current line and 174 | -- the first pixel of the next line together (would produce an errouneous signal). 175 | if numPixels = (IMAGE_WIDTH) then 176 | nextState <= stateNewRow; 177 | else 178 | nextState <= stateStream; 179 | end if; 180 | 181 | when stateNewRow => -- If we ran into the end of the row, reset the FIFO row component. 182 | sigEnRamIn <= '1'; 183 | sigResetFifoRow <= '1'; 184 | nextState <= stateNewRow2; 185 | 186 | when stateNewRow2 => -- Return the reset signal for the FIFO row component back to inactive state. 187 | sigEnRamIn <= '1'; 188 | 189 | -- Check if we have reached the end of the image. 190 | if numRows = IMAGE_HEIGHT then 191 | nextState <= stateFinished; 192 | else 193 | nextState <= stateStream; 194 | end if; 195 | 196 | when stateFinished => -- If the entire image has been processed, loop indefinetly. 197 | sigIsFinishedProcessing <= '1'; 198 | nextState <= stateFinished; 199 | 200 | end case; 201 | end process; 202 | 203 | -- Set the output signals to their current values. 204 | addrIn <= sigAddrIn; 205 | enRamIn <= sigEnRamIn; 206 | resetFifoRow <= sigResetFifoRow; 207 | weFifoRow <= sigWeFifoRow; 208 | resetFifoColumn <= sigResetFifoColumn; 209 | weFifoColumn <= sigWeFifoColumn; 210 | isFinishedProcessing <= sigIsFinishedProcessing; 211 | 212 | rowReady <= sigRowReady; 213 | columnReady <= sigColumnReady; 214 | end Behavioral; 215 | -------------------------------------------------------------------------------- /project/fifomem.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/fifomem.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 23:35:22 07/28/2014 6 | -- Design Name: 7 | -- Module Name: fifomem - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Implementation of an n-bit shift register, which provides output of the first and last element in the chain. Synthesis will produce distributed RAM. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | entity fifomem is 24 | generic ( 25 | DATA_WIDTH: natural := 8; -- Width of a single data register (i.e. a byte). 26 | FIFO_DEPTH: natural := 2 -- Number of data registers in the FIFO memory (i.e. the width of the image + 1). 27 | ); 28 | port ( 29 | clk: in std_logic; 30 | reset: in std_logic; 31 | we: in std_logic; 32 | dataIn: in std_logic_vector((DATA_WIDTH - 1) downto 0); 33 | dataOutFirst: out std_logic_vector((DATA_WIDTH - 1) downto 0); 34 | dataOutLast: out std_logic_vector((DATA_WIDTH - 1) downto 0) 35 | ); 36 | end fifomem; 37 | 38 | architecture RTL of fifomem is 39 | type ramtype is array(0 to (FIFO_DEPTH - 1)) of std_logic_vector((DATA_WIDTH - 1) downto 0); 40 | 41 | signal RAM : ramtype := (others => (others => '0')); 42 | 43 | begin 44 | process (clk, reset) 45 | begin 46 | if reset = '1' then 47 | RAM <= (others => (others => '0')); 48 | elsif rising_edge(clk) then 49 | if we = '1' then 50 | RAM <= dataIn & RAM(0 to (FIFO_DEPTH - 2)); 51 | end if; 52 | end if; 53 | end process; 54 | 55 | dataOutFirst <= RAM(0); 56 | dataOutLast <= RAM(FIFO_DEPTH - 1); 57 | end RTL; 58 | -------------------------------------------------------------------------------- /project/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /project/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "secureip" -o "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/tb_top_isim_beh.exe" -prj "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/tb_top_beh.prj" "work.tb_top" 2 | -------------------------------------------------------------------------------- /project/haarhp.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/haarhp.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 10:50:14 03/27/2014 6 | -- Design Name: 7 | -- Module Name: haarhp - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Haar high-pass wavelet filter. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_unsigned.all; 23 | use ieee.numeric_std.all; 24 | 25 | entity haarhp is 26 | Port ( x0 : in std_logic_vector(7 downto 0); 27 | x1 : in std_logic_vector(7 downto 0); 28 | y : out std_logic_vector(7 downto 0)); 29 | end haarhp; 30 | 31 | architecture Behavioral of haarhp is 32 | 33 | begin 34 | y <= std_logic_vector(to_unsigned(((conv_integer(x0) - conv_integer(x1)) / 2), 8)); 35 | end Behavioral; 36 | -------------------------------------------------------------------------------- /project/haarlp.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/haarlp.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:00:42 03/27/2014 6 | -- Design Name: 7 | -- Module Name: haarlp - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Haar low-pass wavelet filter. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_unsigned.all; 23 | use ieee.numeric_std.all; 24 | 25 | entity haarlp is 26 | Port ( x0 : in std_logic_vector(7 downto 0); 27 | x1 : in std_logic_vector(7 downto 0); 28 | y : out std_logic_vector(7 downto 0)); 29 | end haarlp; 30 | 31 | architecture Behavioral of haarlp is 32 | 33 | begin 34 | y <= std_logic_vector(to_unsigned(((conv_integer(x0) + conv_integer(x1)) / 2), 8)); 35 | end Behavioral; 36 | 37 | -------------------------------------------------------------------------------- /project/iseconfig/wavelet.projectmgr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 2 10 | 11 | 12 | top - Behavioral (/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/top.vhd) 13 | 14 | 0 15 | 0 16 | 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001f9000000020000000000000000000000000200000064ffffffff000000810000000300000002000001f90000000100000003000000000000000100000003 17 | true 18 | top - Behavioral (/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/top.vhd) 19 | 20 | 21 | 22 | 1 23 | Design Utilities 24 | 25 | 26 | 27 | 28 | 0 29 | 0 30 | 000000ff00000000000000010000000100000000000000000000000000000000000000000000000131000000010000000100000000000000000000000064ffffffff000000810000000000000001000001310000000100000000 31 | false 32 | 33 | 34 | 35 | 36 | 1 37 | 38 | 39 | 0 40 | 0 41 | 000000ff0000000000000001000000000000000001000000000000000000000000000000000000039c000000040101000100000000000000000000000064ffffffff0000008100000000000000040000005100000001000000000000002900000001000000000000008400000001000000000000029e0000000100000000 42 | false 43 | haarhp.vhd 44 | 45 | 46 | 47 | 1 48 | 49 | 50 | 0 51 | 0 52 | 000000ff00000000000000010000000000000000010000000000000000000000000000000000000121000000010001000100000000000000000000000064ffffffff000000810000000000000001000001210000000100000000 53 | false 54 | work 55 | 56 | 000000ff0000000000000002000001ef0000015901000000060100000002 57 | Implementation 58 | 59 | 60 | 1 61 | Configure Target Device 62 | Implement Design 63 | User Constraints 64 | 65 | 66 | View RTL Schematic 67 | 68 | 1 69 | 0 70 | 000000ff00000000000000010000000100000000000000000000000000000000000000000000000121000000010000000100000000000000000000000064ffffffff000000810000000000000001000001210000000100000000 71 | false 72 | View RTL Schematic 73 | 74 | 75 | 76 | 2 77 | /tb_clkdivider - behavior |home|ivan|Dropbox|IRB|projekti|E2LP|implementirane_vjezbe|wavelet|wavelet|tb_clkdivider.vhd 78 | /tb_controlunit - behavior |home|ivan|Dropbox|IRB|projekti|E2LP|implementirane_vjezbe|wavelet|wavelet|tb_controlunit.vhd 79 | /tb_fifomem - behavior |home|ivan|Dropbox|IRB|projekti|E2LP|implementirane_vjezbe|wavelet|wavelet|tb_fifomem.vhd 80 | /tb_haarhp - behavior |home|ivan|Dropbox|IRB|projekti|E2LP|implementirane_vjezbe|wavelet|wavelet|tb_haarhp.vhd 81 | /tb_haarlp - behavior |home|ivan|Dropbox|IRB|projekti|E2LP|implementirane_vjezbe|wavelet|wavelet|tb_haarlp.vhd 82 | /tb_ramfile - behavior |home|ivan|Dropbox|IRB|projekti|E2LP|implementirane_vjezbe|wavelet|wavelet|tb_ramfile.vhd 83 | /tb_reg - behavior |home|ivan|Dropbox|IRB|projekti|E2LP|implementirane_vjezbe|wavelet|wavelet|tb_reg.vhd 84 | /tb_reginc - behavior |home|ivan|Dropbox|IRB|projekti|E2LP|implementirane_vjezbe|wavelet|wavelet|tb_reginc.vhd 85 | /tb_top - behavior |home|ivan|Dropbox|IRB|projekti|E2LP|implementirane_vjezbe|wavelet|wavelet|tb_top.vhd 86 | 87 | 88 | tb_top - behavior (/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/tb_top.vhd) 89 | 90 | 0 91 | 0 92 | 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000014a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000014a0000000100000003000000000000000100000003 93 | true 94 | tb_top - behavior (/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/tb_top.vhd) 95 | 96 | 97 | 98 | 1 99 | Design Utilities 100 | 101 | 102 | 103 | 104 | 0 105 | 0 106 | 000000ff00000000000000010000000100000000000000000000000000000000000000000000000131000000010000000100000000000000000000000064ffffffff000000810000000000000001000001310000000100000000 107 | false 108 | 109 | 110 | 111 | 112 | 1 113 | 114 | 115 | Simulate Behavioral Model 116 | 117 | 0 118 | 0 119 | 000000ff00000000000000010000000100000000000000000000000000000000000000000000000131000000010000000100000000000000000000000064ffffffff000000810000000000000001000001310000000100000000 120 | false 121 | Simulate Behavioral Model 122 | 123 | 124 | 125 | 1 126 | User Constraints 127 | 128 | 129 | 130 | 131 | 0 132 | 0 133 | 000000ff00000000000000010000000100000000000000000000000000000000000000000000000131000000010000000100000000000000000000000064ffffffff000000810000000000000001000001310000000100000000 134 | false 135 | 136 | 137 | 138 | -------------------------------------------------------------------------------- /project/isim.log: -------------------------------------------------------------------------------- 1 | ISim log file 2 | Running: /home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/tb_top_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/tb_top_isim_beh.wdb 3 | ISim P.68d (signature 0xfbc00daa) 4 | WARNING: A WEBPACK license was found. 5 | WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. 6 | WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. 7 | This is a Lite version of ISim. 8 | Time resolution is 1 ps 9 | # onerror resume 10 | # wave add / 11 | # run 7000.00 us 12 | Simulator is doing circuit initialization process. 13 | at 0 ps, Instance /tb_top/uut/wicc/W0L/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 14 | at 0 ps, Instance /tb_top/uut/wicc/W0L/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 15 | at 0 ps, Instance /tb_top/uut/wicc/W0L/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 16 | at 0 ps, Instance /tb_top/uut/wicc/WLL/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 17 | at 0 ps, Instance /tb_top/uut/wicc/WLL/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 18 | at 0 ps, Instance /tb_top/uut/wicc/WLH/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 19 | at 0 ps, Instance /tb_top/uut/wicc/WLH/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 20 | at 0 ps, Instance /tb_top/uut/wicc/W0H/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 21 | at 0 ps, Instance /tb_top/uut/wicc/W0H/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 22 | at 0 ps, Instance /tb_top/uut/wicc/WHL/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 23 | at 0 ps, Instance /tb_top/uut/wicc/WHL/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 24 | at 0 ps, Instance /tb_top/uut/wicc/WHH/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 25 | at 0 ps, Instance /tb_top/uut/wicc/WHH/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. 26 | Finished circuit initialization process. 27 | # exit 0 28 | -------------------------------------------------------------------------------- /project/memcontroler.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/pa.fromNcd.tcl: -------------------------------------------------------------------------------- 1 | 2 | # PlanAhead Launch Script for Post PAR Floorplanning, created by Project Navigator 3 | 4 | create_project -name wavelet -dir "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/planAhead_run_2" -part xc6slx45fgg676-3 5 | set srcset [get_property srcset [current_run -impl]] 6 | set_property design_mode GateLvl $srcset 7 | set_property edif_top_file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/ramfile.ngc" [ get_property srcset [ current_run ] ] 8 | add_files -norecurse { {/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet} } 9 | set_property target_constrs_file "ramfile.ucf" [current_fileset -constrset] 10 | add_files [list {ramfile.ucf}] -fileset [get_property constrset [current_run]] 11 | link_design 12 | read_xdl -file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/ramfile.ncd" 13 | if {[catch {read_twx -name results_1 -file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/ramfile.twx"} eInfo]} { 14 | puts "WARNING: there was a problem importing \"/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/ramfile.twx\": $eInfo" 15 | } 16 | -------------------------------------------------------------------------------- /project/pa.fromNetlist.tcl: -------------------------------------------------------------------------------- 1 | 2 | # PlanAhead Launch Script for Post-Synthesis floorplanning, created by Project Navigator 3 | 4 | create_project -name wavelet -dir "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/planAhead_run_1" -part xc6slx45fgg676-3 5 | set_property design_mode GateLvl [get_property srcset [current_run -impl]] 6 | set_property edif_top_file "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/ramfile.ngc" [ get_property srcset [ current_run ] ] 7 | add_files -norecurse { {/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet} } 8 | set_property target_constrs_file "ramfile.ucf" [current_fileset -constrset] 9 | add_files [list {ramfile.ucf}] -fileset [get_property constrset [current_run]] 10 | link_design 11 | -------------------------------------------------------------------------------- /project/par_usage_statistics.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 |
Par Statistics
Total Non-vccgnd Signals=74
Total Non-vccgnd Design Pins=739
Total Non-vccgnd Conns=739
Total Non-vccgnd Timing Constrained Conns=0
Phase 1 CPU=5.1 sec
Phase 2 CPU=5.6 sec
Phase 3 CPU=6.6 sec
Phase 4 CPU=7.7 sec
Phase 5 CPU=8.1 sec
Phase 6 CPU=8.1 sec
Phase 7 CPU=8.1 sec
Phase 8 CPU=8.1 sec
Phase 9 CPU=8.1 sec
Phase 10 CPU=8.1 sec
AvgWirelenPerPin Fanout 1=13.0
AvgWirelenPerPin Fanout 2=12.5
AvgWirelenPerPin Fanout 3=14.7
AvgWirelenPerPin Fanout 4=34.5
AvgWirelenPerPin Fanout 10=16.4
AvgWirelenPerPin Fanout 50=21.8
AvgWirelenPerPin Fanout 100=0.0
AvgWirelenPerPin Fanout 500=0.0
AvgWirelenPerPin Fanout 5000=0.0
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 50000=0.0
AvgWirelenPerPin Fanout 100000=0.0
IRR Gamma=1.0061
33 | -------------------------------------------------------------------------------- /project/pepExtractor.prj: -------------------------------------------------------------------------------- 1 | work "controlunit.vhd" 2 | -------------------------------------------------------------------------------- /project/planAhead.ngc2edif.log: -------------------------------------------------------------------------------- 1 | Release 14.6 - ngc2edif P.68d (lin64) 2 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 3 | Reading design ramfile.ngc ... 4 | WARNING:NetListWriters:298 - No output is written to ramfile.xncf, ignored. 5 | Processing design ... 6 | Preping design's networks ... 7 | Preping design's macros ... 8 | finished :Prep 9 | Writing EDIF netlist file ramfile.edif ... 10 | ngc2edif: Total memory usage is 105644 kilobytes 11 | 12 | Release 14.6 - ngc2edif P.68d (lin64) 13 | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. 14 | Reading design ramfile.ngc ... 15 | WARNING:NetListWriters:298 - No output is written to ramfile.xncf, ignored. 16 | Processing design ... 17 | Preping design's networks ... 18 | Preping design's macros ... 19 | finished :Prep 20 | Writing EDIF netlist file ramfile.edif ... 21 | ngc2edif: Total memory usage is 105644 kilobytes 22 | 23 | -------------------------------------------------------------------------------- /project/ramfile.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:59:36 03/26/2014 6 | -- Design Name: 7 | -- Module Name: ramfile - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_unsigned.all; 23 | use std.textio.all; 24 | 25 | entity ramfile is 26 | generic (RAM_SIZE : integer := 65536 27 | ); 28 | port (clk : in std_logic; 29 | we : in std_logic; 30 | en : in std_logic; 31 | addr : in std_logic_vector(15 downto 0); 32 | dataIn : in std_logic_vector(7 downto 0); 33 | dataOut : out std_logic_vector(7 downto 0)); 34 | end ramfile; 35 | 36 | 37 | 38 | -- The following code will infer a Single port Block RAM and initialize it using a FILE 39 | 40 | architecture Behavioral of ramfile is 41 | type ramtype is array(0 to (RAM_SIZE - 1)) of std_logic_vector(7 downto 0); 42 | 43 | impure function ramLoad (ram_file_name : in string) return ramtype is 44 | FILE ram_file : text is in ram_file_name; 45 | variable line_name : line; 46 | variable temp_bv : bit_vector(7 downto 0); 47 | variable temp_ram : ramtype; 48 | begin 49 | for I in ramtype'range loop 50 | readline (ram_file, line_name); 51 | read (line_name, temp_bv); 52 | temp_ram(I) := to_stdlogicvector(temp_bv); 53 | end loop; 54 | return temp_ram; 55 | end function; 56 | 57 | signal RAM : ramtype := ramLoad("../data/lena256bw.txt"); 58 | 59 | begin 60 | process (clk) 61 | begin 62 | if clk'event and clk = '1' then 63 | if EN = '1' then 64 | if WE = '1' then 65 | RAM(conv_integer(addr)) <= dataIn; 66 | end if; 67 | dataOut <= RAM(conv_integer(addr)) ; 68 | end if; 69 | end if; 70 | end process; 71 | 72 | end Behavioral; 73 | 74 | -------------------------------------------------------------------------------- /project/ramnormal.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/ramnormal.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:59:36 03/26/2014 6 | -- Design Name: 7 | -- Module Name: ramfile - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_unsigned.all; 23 | use std.textio.all; 24 | 25 | entity ramnormal is 26 | generic ( RAM_SIZE : integer := 65536; 27 | ADDR_WIDTH : integer := 16 28 | ); 29 | port (clk : in std_logic; 30 | we : in std_logic; 31 | en : in std_logic; 32 | addr : in std_logic_vector((ADDR_WIDTH - 1) downto 0); 33 | dataIn : in std_logic_vector(7 downto 0); 34 | dataOut : out std_logic_vector(7 downto 0)); 35 | end ramnormal; 36 | 37 | 38 | 39 | -- The following code will infer a Single port Block RAM and initialize it using a FILE 40 | 41 | architecture Behavioral of ramnormal is 42 | type ramtype is array(0 to (RAM_SIZE - 1)) of std_logic_vector(7 downto 0); 43 | 44 | impure function ramLoad (ram_file_name : in string) return ramtype is 45 | FILE ram_file : text is in ram_file_name; 46 | variable line_name : line; 47 | variable temp_bv : bit_vector(7 downto 0); 48 | variable temp_ram : ramtype; 49 | begin 50 | for I in ramtype'range loop 51 | readline (ram_file, line_name); 52 | read (line_name, temp_bv); 53 | temp_ram(I) := to_stdlogicvector(temp_bv); 54 | end loop; 55 | return temp_ram; 56 | end function; 57 | 58 | signal RAM : ramtype := (others => "00000000"); -- ramLoad("../data/lena256bw.txt"); 59 | 60 | begin 61 | process (clk) 62 | begin 63 | if clk'event and clk = '1' then 64 | if EN = '1' then 65 | if WE = '1' then 66 | RAM(conv_integer(addr)) <= dataIn; 67 | end if; 68 | dataOut <= RAM(conv_integer(addr)) ; 69 | end if; 70 | end if; 71 | end process; 72 | 73 | end Behavioral; 74 | 75 | -------------------------------------------------------------------------------- /project/tb_fifomem.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 10:38:45 07/29/2014 6 | -- Design Name: 7 | -- Module Name: tb_fifomem.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: fifomem 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | USE ieee.numeric_std.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --USE ieee.numeric_std.ALL; 28 | 29 | ENTITY tb_fifomem IS 30 | END tb_fifomem; 31 | 32 | ARCHITECTURE behavior OF tb_fifomem IS 33 | 34 | -- Component Declaration for the Unit Under Test (UUT) 35 | 36 | COMPONENT fifomem 37 | GENERIC ( 38 | DATA_WIDTH: natural := 8; -- Width of a single data register (i.e. a byte). 39 | FIFO_DEPTH: natural := 2 -- Number of data registers in the FIFO memory (i.e. the width of the image + 1). 40 | ); 41 | PORT( 42 | clk : IN std_logic; 43 | reset : IN std_logic; 44 | we: in std_logic; 45 | dataIn : IN std_logic_vector(7 downto 0); 46 | dataOutFirst: out std_logic_vector((DATA_WIDTH - 1) downto 0); 47 | dataOutLast: out std_logic_vector((DATA_WIDTH - 1) downto 0) 48 | ); 49 | END COMPONENT; 50 | 51 | --Inputs 52 | signal clk : std_logic := '0'; 53 | signal reset : std_logic := '0'; 54 | signal dataIn : std_logic_vector(7 downto 0) := (others => '0'); 55 | signal we : std_logic := '0'; 56 | 57 | --Outputs 58 | signal dataOutFirst : std_logic_vector(7 downto 0); 59 | signal dataOutLast : std_logic_vector(7 downto 0); 60 | 61 | -- Clock period definitions 62 | constant clk_period : time := 10 ns; 63 | 64 | BEGIN 65 | 66 | -- Instantiate the Unit Under Test (UUT) 67 | uut: fifomem 68 | GENERIC MAP (DATA_WIDTH => 8, FIFO_DEPTH => 4) 69 | PORT MAP ( 70 | clk => clk, 71 | reset => reset, 72 | we => we, 73 | dataIn => dataIn, 74 | dataOutFirst => dataOutFirst, 75 | dataOutLast => dataOutLast 76 | ); 77 | 78 | -- Clock process definitions 79 | clk_process :process 80 | begin 81 | clk <= '0'; 82 | wait for clk_period/2; 83 | clk <= '1'; 84 | wait for clk_period/2; 85 | end process; 86 | 87 | -- Stimulus process 88 | stim_proc: process 89 | variable dataCounter: integer := 1; 90 | begin 91 | -- hold reset state for 100 ns. 92 | reset <= '1'; 93 | wait for 100 ns; 94 | reset <= '0'; 95 | we <= '1'; 96 | 97 | wait for clk_period; 98 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 99 | dataCounter := dataCounter + 1; 100 | wait for clk_period; 101 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 102 | dataCounter := dataCounter + 1; 103 | wait for clk_period; 104 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 105 | dataCounter := dataCounter + 1; 106 | wait for clk_period; 107 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 108 | dataCounter := dataCounter + 1; 109 | wait for clk_period; 110 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 111 | dataCounter := dataCounter + 1; 112 | 113 | wait for clk_period*10; 114 | 115 | wait; 116 | end process; 117 | 118 | END; 119 | -------------------------------------------------------------------------------- /project/tb_fifomem.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | clk 17 | clk 18 | 19 | 20 | reset 21 | reset 22 | 23 | 24 | datain[7:0] 25 | datain[7:0] 26 | 27 | 28 | dataoutfirst[7:0] 29 | dataoutfirst[7:0] 30 | 31 | 32 | dataoutlast[7:0] 33 | dataoutlast[7:0] 34 | 35 | 36 | clk_period 37 | clk_period 38 | 39 | 40 | ram[0:3] 41 | ram[0:3] 42 | 43 | 44 | -------------------------------------------------------------------------------- /project/tb_haarhp.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 11:05:28 03/27/2014 6 | -- Design Name: 7 | -- Module Name: tb_haarhp.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: haarhp 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --USE ieee.numeric_std.ALL; 27 | 28 | ENTITY tb_haarhp IS 29 | END tb_haarhp; 30 | 31 | ARCHITECTURE behavior OF tb_haarhp IS 32 | 33 | -- Component Declaration for the Unit Under Test (UUT) 34 | 35 | COMPONENT haarhp 36 | PORT( 37 | x0 : IN std_logic_vector(7 downto 0); 38 | x1 : IN std_logic_vector(7 downto 0); 39 | y : OUT std_logic_vector(7 downto 0) 40 | ); 41 | END COMPONENT; 42 | 43 | 44 | --Inputs 45 | signal x0 : std_logic_vector(7 downto 0) := (others => '0'); 46 | signal x1 : std_logic_vector(7 downto 0) := (others => '0'); 47 | signal reset : std_logic := '0'; 48 | 49 | --Outputs 50 | signal y : std_logic_vector(7 downto 0); 51 | -- No clocks detected in port list. Replace below with 52 | -- appropriate port name 53 | 54 | constant clock_period : time := 10 ns; 55 | signal clock : std_logic := '0'; 56 | 57 | BEGIN 58 | 59 | -- Instantiate the Unit Under Test (UUT) 60 | uut: haarhp PORT MAP ( 61 | x0 => x0, 62 | x1 => x1, 63 | y => y 64 | ); 65 | 66 | -- Clock process definitions 67 | clock_process :process 68 | begin 69 | clock <= '0'; 70 | wait for clock_period/2; 71 | clock <= '1'; 72 | wait for clock_period/2; 73 | end process; 74 | 75 | 76 | -- Stimulus process 77 | stim_proc: process 78 | begin 79 | -- hold reset state for 100 ns. 80 | reset <= '1'; 81 | wait for 100 ns; 82 | 83 | reset <= '0'; 84 | wait for 100 ns; 85 | 86 | x0 <= x"02"; 87 | x1 <= x"00"; 88 | wait for clock_period; 89 | 90 | x0 <= x"03"; 91 | x1 <= x"02"; 92 | wait for clock_period; 93 | 94 | x0 <= x"07"; 95 | x1 <= x"03"; 96 | wait for clock_period; 97 | 98 | x0 <= x"12"; 99 | x1 <= x"07"; 100 | wait for clock_period; 101 | 102 | x0 <= x"FA"; 103 | x1 <= x"12"; 104 | wait for clock_period; 105 | 106 | x0 <= x"00"; 107 | x1 <= x"FA"; 108 | wait for clock_period; 109 | 110 | x0 <= x"20"; 111 | x1 <= x"00"; 112 | wait for clock_period; 113 | 114 | reset <= '1'; 115 | x0 <= x"00"; 116 | x1 <= x"00"; 117 | wait for clock_period; 118 | reset <= '0'; 119 | wait for clock_period; 120 | 121 | x0 <= x"00"; 122 | x1 <= x"00"; 123 | wait for clock_period; 124 | x0 <= x"FF"; 125 | x1 <= x"00"; 126 | wait for clock_period; 127 | x0 <= x"FF"; 128 | x1 <= x"FF"; 129 | wait for clock_period; 130 | 131 | wait for clock_period*10; 132 | 133 | -- insert stimulus here 134 | 135 | wait; 136 | end process; 137 | 138 | END; 139 | -------------------------------------------------------------------------------- /project/tb_haarhp.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | x[7:0] 19 | x[7:0] 20 | UNSIGNEDDECRADIX 21 | 22 | 23 | xold[7:0] 24 | xold[7:0] 25 | UNSIGNEDDECRADIX 26 | 27 | 28 | label 29 | y[7:0] 30 | y[7:0] 31 | UNSIGNEDDECRADIX 32 | y[7:0] 33 | 34 | 35 | reset 36 | reset 37 | 38 | 39 | clock 40 | clock 41 | 42 | 43 | clock_period 44 | clock_period 45 | 46 | 47 | -------------------------------------------------------------------------------- /project/tb_haarlp.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:03:41 03/27/2014 6 | -- Design Name: 7 | -- Module Name: tb_haarlp.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: haarlp 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --USE ieee.numeric_std.ALL; 27 | 28 | ENTITY tb_haarlp IS 29 | END tb_haarlp; 30 | 31 | ARCHITECTURE behavior OF tb_haarlp IS 32 | 33 | -- Component Declaration for the Unit Under Test (UUT) 34 | 35 | COMPONENT haarlp 36 | PORT( 37 | x0 : IN std_logic_vector(7 downto 0); 38 | x1 : IN std_logic_vector(7 downto 0); 39 | y : OUT std_logic_vector(7 downto 0) 40 | ); 41 | END COMPONENT; 42 | 43 | 44 | --Inputs 45 | signal x0 : std_logic_vector(7 downto 0) := (others => '0'); 46 | signal x1 : std_logic_vector(7 downto 0) := (others => '0'); 47 | 48 | --Outputs 49 | signal y : std_logic_vector(7 downto 0); 50 | -- No clocks detected in port list. Replace below with 51 | -- appropriate port name 52 | 53 | constant clock_period : time := 10 ns; 54 | 55 | BEGIN 56 | 57 | -- Instantiate the Unit Under Test (UUT) 58 | uut: haarlp PORT MAP ( 59 | x0 => x0, 60 | x1 => x1, 61 | y => y 62 | ); 63 | 64 | -- -- Clock process definitions 65 | -- _process :process 66 | -- begin 67 | -- <= '0'; 68 | -- wait for _period/2; 69 | -- <= '1'; 70 | -- wait for _period/2; 71 | -- end process; 72 | 73 | 74 | -- Stimulus process 75 | stim_proc: process 76 | begin 77 | -- hold reset state for 100 ns. 78 | wait for 100 ns; 79 | 80 | x0 <= x"02"; 81 | x1 <= x"00"; 82 | wait for clock_period; 83 | 84 | x0 <= x"03"; 85 | x1 <= x"02"; 86 | wait for clock_period; 87 | 88 | x0 <= x"07"; 89 | x1 <= x"03"; 90 | wait for clock_period; 91 | 92 | x0 <= x"12"; 93 | x1 <= x"07"; 94 | wait for clock_period; 95 | 96 | x0 <= x"FA"; 97 | x1 <= x"12"; 98 | wait for clock_period; 99 | 100 | x0 <= x"00"; 101 | x1 <= x"FA"; 102 | wait for clock_period; 103 | 104 | x0 <= x"20"; 105 | x1 <= x"00"; 106 | wait for clock_period; 107 | 108 | x0 <= x"00"; 109 | x1 <= x"00"; 110 | wait for clock_period; 111 | x0 <= x"FF"; 112 | x1 <= x"00"; 113 | wait for clock_period; 114 | x0 <= x"FF"; 115 | x1 <= x"FF"; 116 | wait for clock_period; 117 | 118 | wait for clock_period*10; 119 | -- insert stimulus here 120 | 121 | wait; 122 | end process; 123 | 124 | END; 125 | -------------------------------------------------------------------------------- /project/tb_ramfile.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 18:00:57 03/26/2014 6 | -- Design Name: 7 | -- Module Name: tb_ramfile.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: ramfile 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | use ieee.std_logic_unsigned.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --USE ieee.numeric_std.ALL; 28 | 29 | ENTITY tb_ramfile IS 30 | END tb_ramfile; 31 | 32 | ARCHITECTURE behavior OF tb_ramfile IS 33 | 34 | -- Component Declaration for the Unit Under Test (UUT) 35 | 36 | COMPONENT ramfile 37 | PORT( 38 | clk : IN std_logic; 39 | we : IN std_logic; 40 | en : IN std_logic; 41 | addr : IN std_logic_vector(15 downto 0); 42 | dataIn : IN std_logic_vector(7 downto 0); 43 | dataOut : OUT std_logic_vector(7 downto 0) 44 | ); 45 | END COMPONENT; 46 | 47 | --Inputs 48 | signal clk : std_logic := '0'; 49 | signal we : std_logic := '0'; 50 | signal en : std_logic := '0'; 51 | signal addr : std_logic_vector(15 downto 0) := (others => '0'); 52 | signal dataIn : std_logic_vector(7 downto 0) := (others => '0'); 53 | 54 | --Outputs 55 | signal dataOut : std_logic_vector(7 downto 0); 56 | 57 | -- Clock period definitions 58 | constant clk_period : time := 10 ns; 59 | 60 | BEGIN 61 | 62 | -- Instantiate the Unit Under Test (UUT) 63 | uut: ramfile PORT MAP ( 64 | clk => clk, 65 | we => we, 66 | en => en, 67 | addr => addr, 68 | dataIn => dataIn, 69 | dataOut => dataOut 70 | ); 71 | 72 | -- Clock process definitions 73 | clk_process :process 74 | begin 75 | clk <= '0'; 76 | wait for clk_period/2; 77 | clk <= '1'; 78 | wait for clk_period/2; 79 | end process; 80 | 81 | 82 | -- Stimulus process 83 | stim_proc: process 84 | begin 85 | -- hold reset state for 100 ns. 86 | wait for 100 ns; 87 | 88 | wait for clk_period*10; 89 | addr <= addr + '1'; 90 | en <= '1'; 91 | 92 | wait for clk_period*10; 93 | addr <= addr + '1'; 94 | 95 | wait for clk_period*10; 96 | addr <= addr + '1'; 97 | 98 | wait for clk_period*10; 99 | addr <= addr + '1'; 100 | 101 | wait for clk_period*10; 102 | addr <= addr + '1'; 103 | 104 | -- insert stimulus here 105 | 106 | wait; 107 | end process; 108 | 109 | END; 110 | -------------------------------------------------------------------------------- /project/tb_ramfile_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/project/tb_ramfile_isim_beh1.wdb -------------------------------------------------------------------------------- /project/tb_ramfile_isim_beh2.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/project/tb_ramfile_isim_beh2.wdb -------------------------------------------------------------------------------- /project/tb_top.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 09:35:29 03/27/2014 6 | -- Design Name: 7 | -- Module Name: tb_top.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: top 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | USE IEEE.std_logic_textio.all; 24 | USE STD.textio.all; 25 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 26 | USE IEEE.NUMERIC_STD.ALL; 27 | USE IEEE.STD_LOGIC_ARITH.ALL; 28 | 29 | -- Uncomment the following library declaration if using 30 | -- arithmetic functions with Signed or Unsigned values 31 | --USE ieee.numeric_std.ALL; 32 | 33 | ENTITY tb_top IS 34 | END tb_top; 35 | 36 | ARCHITECTURE behavior OF tb_top IS 37 | 38 | -- Component Declaration for the Unit Under Test (UUT) 39 | 40 | COMPONENT top 41 | Generic ( IMAGE_WIDTH : integer := 256; 42 | IMAGE_HEIGHT : integer := 256; 43 | ADDR_WIDTH : integer := 16 44 | ); 45 | Port ( clk : in std_logic; 46 | reset : in std_logic; 47 | requestNewData : in std_logic; 48 | 49 | outData : out std_logic_vector(7 downto 0); 50 | isFinishedProcessing : out std_logic; 51 | outDataReady : out std_logic; 52 | isFinishedTransmitting : out std_logic 53 | ); 54 | END COMPONENT; 55 | 56 | --Inputs 57 | signal clk : std_logic := '0'; 58 | signal reset : std_logic := '0'; 59 | signal requestNewData : std_logic := '0'; 60 | 61 | --Outputs 62 | signal outData : std_logic_vector(7 downto 0) := (others => '0'); 63 | signal outDataReady : std_logic := '0'; 64 | signal isFinishedTransmitting : std_logic := '0'; 65 | signal isFinishedProcessing : std_logic := '0'; 66 | 67 | -- Clock period definitions 68 | constant clk_period : time := 10 ns; 69 | 70 | BEGIN 71 | 72 | -- Instantiate the Unit Under Test (UUT) 73 | uut: top GENERIC MAP ( 74 | IMAGE_WIDTH => 256, 75 | IMAGE_HEIGHT => 256, 76 | ADDR_WIDTH => 16) 77 | PORT MAP ( 78 | clk => clk, 79 | reset => reset, 80 | outData => outData, 81 | isFinishedProcessing => isFinishedProcessing, 82 | outDataReady => outDataReady, 83 | isFinishedTransmitting => isFinishedTransmitting, 84 | requestNewData => requestNewData 85 | ); 86 | 87 | -- Clock process definitions 88 | clk_process :process 89 | begin 90 | clk <= '0'; 91 | wait for clk_period/2; 92 | clk <= '1'; 93 | wait for clk_period/2; 94 | end process; 95 | 96 | 97 | -- Stimulus process 98 | stim_proc: process 99 | begin 100 | reset <= '1'; 101 | -- hold reset state for 100 ns. 102 | wait for 100 ns; 103 | reset <= '0'; 104 | 105 | wait until isFinishedProcessing'event and isFinishedProcessing = '1'; 106 | 107 | wait; 108 | end process; 109 | 110 | -- Simulate for 7000.00us in order to write the entire memory to file. 111 | writeToDisk: process 112 | file ramOutFile: TEXT open WRITE_MODE is "../data/compressed.out"; 113 | variable myLine : LINE; 114 | variable myOutputLine : LINE; 115 | begin 116 | if isFinishedProcessing = '1' then 117 | wait for clk_period; 118 | requestNewData <= '1'; 119 | 120 | wait until rising_edge(outDataReady); 121 | write(myOutputLine, conv_integer(outData)); 122 | writeline(ramOutFile, myOutputLine); 123 | requestNewData <= '0'; 124 | 125 | if isFinishedTransmitting = '1' then 126 | wait; 127 | end if; 128 | end if; 129 | 130 | wait for clk_period; 131 | end process; 132 | 133 | END; 134 | -------------------------------------------------------------------------------- /project/tb_top.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | clk 21 | clk 22 | 23 | 24 | outdata[7:0] 25 | outdata[7:0] 26 | 27 | 28 | resultramaddr[15:0] 29 | resultramaddr[15:0] 30 | 31 | 32 | isstreaming 33 | isstreaming 34 | 35 | 36 | isfinishedprocessing 37 | isfinishedprocessing 38 | true 39 | #ff00ff 40 | 41 | 42 | done 43 | done 44 | 45 | 46 | outdataready 47 | outdataready 48 | 49 | 50 | isfinishedtransmitting 51 | isfinishedtransmitting 52 | 53 | 54 | requestnewdata 55 | requestnewdata 56 | 57 | 58 | currentstate 59 | currentstate 60 | 61 | 62 | numpixels[15:0] 63 | numpixels[15:0] 64 | UNSIGNEDDECRADIX 65 | 66 | 67 | totalnumpixels[15:0] 68 | totalnumpixels[15:0] 69 | UNSIGNEDDECRADIX 70 | 71 | 72 | numrows 73 | numrows 74 | 75 | 76 | cuisfinishedprocessing 77 | cuisfinishedprocessing 78 | true 79 | #ff0000 80 | 81 | 82 | isfinishedcompressing 83 | isfinishedcompressing 84 | true 85 | #ff00ff 86 | 87 | 88 | spll[15:0] 89 | spll[15:0] 90 | UNSIGNEDDECRADIX 91 | true 92 | #ff0000 93 | 94 | 95 | splh[15:0] 96 | splh[15:0] 97 | UNSIGNEDDECRADIX 98 | 99 | 100 | sphl[15:0] 101 | sphl[15:0] 102 | UNSIGNEDDECRADIX 103 | 104 | 105 | sphlmoving[15:0] 106 | sphlmoving[15:0] 107 | UNSIGNEDDECRADIX 108 | 109 | 110 | sphh[15:0] 111 | sphh[15:0] 112 | UNSIGNEDDECRADIX 113 | 114 | 115 | sphhmoving[15:0] 116 | sphhmoving[15:0] 117 | UNSIGNEDDECRADIX 118 | 119 | 120 | currentstate 121 | currentstate 122 | 123 | 124 | samecountlh 125 | samecountlh 126 | 127 | 128 | samecounthl 129 | samecounthl 130 | 131 | 132 | samecounthh 133 | samecounthh 134 | 135 | 136 | datatosend[7:0] 137 | datatosend[7:0] 138 | UNSIGNEDDECRADIX 139 | 140 | 141 | addresstosend[15:0] 142 | addresstosend[15:0] 143 | UNSIGNEDDECRADIX 144 | 145 | 146 | rowready 147 | rowready 148 | true 149 | #ff00ff 150 | 151 | 152 | columnready 153 | columnready 154 | true 155 | #00ffff 156 | 157 | 158 | readyfornextdata 159 | readyfornextdata 160 | 161 | 162 | ram[0:1] 163 | ram[0:1] 164 | UNSIGNEDDECRADIX 165 | 166 | 167 | ram[0:256] 168 | ram[0:256] 169 | UNSIGNEDDECRADIX 170 | 171 | 172 | dataoutfirst[7:0] 173 | dataoutfirst[7:0] 174 | UNSIGNEDDECRADIX 175 | 176 | 177 | dataoutlast[7:0] 178 | dataoutlast[7:0] 179 | UNSIGNEDDECRADIX 180 | 181 | 182 | yll[7:0] 183 | yll[7:0] 184 | UNSIGNEDDECRADIX 185 | 186 | 187 | ylh[7:0] 188 | ylh[7:0] 189 | UNSIGNEDDECRADIX 190 | 191 | 192 | yhl[7:0] 193 | yhl[7:0] 194 | UNSIGNEDDECRADIX 195 | 196 | 197 | yhh[7:0] 198 | yhh[7:0] 199 | UNSIGNEDDECRADIX 200 | 201 | 202 | raminaddr[15:0] 203 | raminaddr[15:0] 204 | UNSIGNEDDECRADIX 205 | 206 | 207 | originaldata[7:0] 208 | originaldata[7:0] 209 | UNSIGNEDDECRADIX 210 | 211 | 212 | ramoutdata[7:0] 213 | ramoutdata[7:0] 214 | UNSIGNEDDECRADIX 215 | 216 | 217 | ramoutaddr[15:0] 218 | ramoutaddr[15:0] 219 | UNSIGNEDDECRADIX 220 | 221 | 222 | -------------------------------------------------------------------------------- /project/tb_top_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/project/tb_top_isim_beh1.wdb -------------------------------------------------------------------------------- /project/top.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/top.xst" -ofn "/home/ivan/Dropbox/IRB/projekti/E2LP/implementirane_vjezbe/wavelet/wavelet/top.syr" 2 | -------------------------------------------------------------------------------- /project/top.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/top.prj: -------------------------------------------------------------------------------- 1 | vhdl work "memcontroler.vhd" 2 | vhdl work "haarlp.vhd" 3 | vhdl work "haarhp.vhd" 4 | vhdl work "fifomem.vhd" 5 | vhdl work "controlunit.vhd" 6 | vhdl work "waveleticc.vhd" 7 | vhdl work "transmitraw.vhd" 8 | vhdl work "ramnormal.vhd" 9 | vhdl work "ramfile.vhd" 10 | vhdl work "top.vhd" 11 | -------------------------------------------------------------------------------- /project/top.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/project/top.stx -------------------------------------------------------------------------------- /project/top.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 09:14:39 03/27/2014 6 | -- Design Name: 7 | -- Module Name: top - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Top-level design for testing the Wavelet Image Compression Component. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use IEEE.NUMERIC_STD.ALL; 24 | 25 | entity top is 26 | Generic ( IMAGE_WIDTH : integer := 256; 27 | IMAGE_HEIGHT : integer := 256; 28 | ADDR_WIDTH : integer := 16 29 | ); 30 | Port ( clk : in std_logic; 31 | reset : in std_logic; 32 | 33 | outData : out std_logic_vector(7 downto 0); 34 | isFinishedProcessing : out std_logic; 35 | 36 | outDataReady : out std_logic; 37 | isFinishedTransmitting : out std_logic; 38 | requestNewData : in std_logic 39 | ); 40 | end top; 41 | 42 | architecture Behavioral of top is 43 | component ramfile is 44 | generic (RAM_SIZE : integer := 65536 45 | ); 46 | port (clk : in std_logic; 47 | we : in std_logic; 48 | en : in std_logic; 49 | addr : in std_logic_vector(15 downto 0); 50 | dataIn : in std_logic_vector(7 downto 0); 51 | dataOut : out std_logic_vector(7 downto 0)); 52 | end component; 53 | 54 | component ramnormal is 55 | generic ( RAM_SIZE : integer := 65536; 56 | ADDR_WIDTH : integer := 16 57 | ); 58 | port (clk : in std_logic; 59 | we : in std_logic; 60 | en : in std_logic; 61 | addr : in std_logic_vector((ADDR_WIDTH - 1) downto 0); 62 | dataIn : in std_logic_vector(7 downto 0); 63 | dataOut : out std_logic_vector(7 downto 0)); 64 | end component; 65 | 66 | component waveleticc is 67 | Generic ( IMAGE_WIDTH : integer := 256; 68 | IMAGE_HEIGHT : integer := 256; 69 | ADDR_WIDTH : integer := 16 70 | ); 71 | Port ( clk : in std_logic; 72 | reset : in std_logic; 73 | 74 | ramInAddr : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 75 | ramInEn : out STD_LOGIC := '0'; 76 | ramInData : in STD_LOGIC_VECTOR(7 downto 0); 77 | 78 | ramOutDataIn : out STD_LOGIC_VECTOR(7 downto 0); 79 | ramOutDataOut : in STD_LOGIC_VECTOR(7 downto 0); 80 | ramOutWe : out STD_LOGIC; 81 | ramOutAddr: out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 82 | 83 | isFinishedCompressing : out STD_LOGIC; 84 | compressedDataSize : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) 85 | ); 86 | end component; 87 | 88 | component transmitraw is 89 | Generic ( IMAGE_WIDTH : integer := 256; 90 | IMAGE_HEIGHT : integer := 256; 91 | ADDR_WIDTH : integer := 16 92 | ); 93 | Port ( clk : in STD_LOGIC; 94 | en : in STD_LOGIC; 95 | reset : in STD_LOGIC; 96 | request : in STD_LOGIC; 97 | dataIn : in STD_LOGIC_VECTOR (7 downto 0); 98 | 99 | ready : out STD_LOGIC; 100 | done : out STD_LOGIC; 101 | address : out STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0); 102 | stopAddress : in STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 103 | dataOut : out STD_LOGIC_VECTOR (7 downto 0)); 104 | end component; 105 | 106 | signal ramInAddr : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 107 | signal originalData : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 108 | signal enRamIn : STD_LOGIC := '0'; 109 | 110 | signal ramOutDataIn : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 111 | signal ramOutDataOut : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 112 | signal weRamOut : STD_LOGIC := '0'; 113 | 114 | signal transmitAddr : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 115 | signal addrOutMemCtrl : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 116 | signal ramOutAddr : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 117 | 118 | signal isFinishedCompressing : STD_LOGIC := '0'; 119 | signal sigCompressedDataSize : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 120 | 121 | begin 122 | wicc: component waveleticc generic map ( IMAGE_WIDTH => IMAGE_WIDTH, 123 | IMAGE_HEIGHT => IMAGE_HEIGHT, 124 | ADDR_WIDTH => ADDR_WIDTH) 125 | port map ( clk => clk, 126 | reset => reset, 127 | ramInAddr => ramInAddr, 128 | ramInEn => enRamIn, 129 | ramInData => originalData, 130 | 131 | ramOutDataIn => ramOutDataIn, 132 | ramOutDataOut => ramOutDataOut, 133 | ramOutWe => weRamOut, 134 | ramOutAddr => addrOutMemCtrl, 135 | 136 | isFinishedCompressing => isFinishedCompressing, 137 | compressedDataSize => sigCompressedDataSize 138 | ); 139 | 140 | ramIn: component ramfile generic map (RAM_SIZE => (IMAGE_WIDTH*IMAGE_HEIGHT)) 141 | port map ( clk => clk, 142 | we => '0', 143 | en => enRamIn, 144 | addr => ramInAddr, 145 | dataIn => x"00", 146 | dataOut => originalData); 147 | 148 | ramOut: component ramnormal generic map ( RAM_SIZE => 65536, 149 | ADDR_WIDTH => 16) 150 | port map ( clk => clk, 151 | we => weRamOut, 152 | en => '1', 153 | addr => ramOutAddr, 154 | dataIn => ramOutDataIn, 155 | dataOut => ramOutDataOut); 156 | 157 | transmitter: component transmitraw generic map ( IMAGE_WIDTH => IMAGE_WIDTH, 158 | IMAGE_HEIGHT => IMAGE_HEIGHT, 159 | ADDR_WIDTH => ADDR_WIDTH) 160 | port map ( clk => clk, 161 | en => isFinishedCompressing, 162 | reset => reset, 163 | request => requestNewData, 164 | dataIn => ramOutDataOut, 165 | ready => outDataReady, 166 | done => isFinishedTransmitting, 167 | address => transmitAddr, 168 | stopAddress => sigCompressedDataSize, 169 | dataOut => outData); 170 | 171 | ramOutAddr <= (addrOutMemCtrl) when (isFinishedCompressing = '0') else transmitAddr; 172 | isFinishedProcessing <= isFinishedCompressing; 173 | 174 | end Behavioral; 175 | -------------------------------------------------------------------------------- /project/top.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn top.prj 5 | -ofn top 6 | -ofmt NGC 7 | -p xc6slx45-3-fgg676 8 | -top top 9 | -opt_mode Speed 10 | -opt_level 1 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing No 46 | -optimize_primitives NO 47 | -use_clock_enable Auto 48 | -use_sync_set Auto 49 | -use_sync_reset Auto 50 | -iob Auto 51 | -equivalent_register_removal YES 52 | -slice_utilization_ratio_maxmargin 5 53 | -------------------------------------------------------------------------------- /project/top_envsettings.html: -------------------------------------------------------------------------------- 1 | Xilinx System Settings Report 2 | 3 |
System Settings

4 | 5 |  
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Environment Settings
Environment Variablexstngdbuildmappar
LD_LIBRARY_PATH/home/ivan/work/tools/Xilinx/14.6/ISE_DS/ISE//lib/lin64< data not available >< data not available >< data not available >
PATH/home/ivan/work/tools/Xilinx/14.6/ISE_DS/ISE//bin/lin64:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games:
/home/ivan/work/tools/Xilinx/14.6/ISE_DS/ISE/bin/lin64:
/opt/454/bin		< data not available >< data not available >< data not available >
XILINX/home/ivan/work/tools/Xilinx/14.6/ISE_DS/ISE/< data not available >< data not available >< data not available >
38 | 39 |  
40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 |
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn top.prj 
-ofn top 
-ofmt NGCNGC
-p xc6slx45-3-fgg676 
-top top 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchyNoNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract YESYes
-fsm_encoding AutoAuto
-safe_implementation NoNo
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob AutoAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
326 | 327 |  
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Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-3610QM CPU @ 2.30GHz/1200.000 MHz<  data not available  ><  data not available  ><  data not available  >
Hostivan-T530<  data not available  ><  data not available  ><  data not available  >
OS NameLinuxMint<  data not available  ><  data not available  ><  data not available  >
OS ReleaseLinux Mint 16 Petra<  data not available  ><  data not available  ><  data not available  >
367 | -------------------------------------------------------------------------------- /project/top_summary.html: -------------------------------------------------------------------------------- 1 | Xilinx Design Summary 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 49 | 50 | 51 | 52 |
top Project Status (08/19/2014 - 16:18:32)
Project File:wavelet.xiseParser Errors: No Errors
Module Name:topImplementation State:Synthesized
Target Device:xc6slx45-3fgg676
  • Errors:
 23 | No Errors
Product Version:ISE 14.6
  • Warnings:
No Warnings
Design Goal:Balanced
  • Routing Results:
 35 |  
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 46 | 47 | System Settings 48 |
  • Final Timing Score:
  
53 | 54 | 55 | 56 |  
57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 |
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers692545761%
Number of Slice LUTs1094272884%
Number of fully used LUT-FF pairs398138828%
Number of bonded IOBs143583%
Number of Block RAM/FIFO6411655%
Number of BUFG/BUFGCTRLs1166%
91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 |  
99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 |
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentuto kol 19 16:23:16 2014004 Infos (4 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
110 |  
111 | 112 | 113 | 114 |
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Dateuto kol 19 16:21:02 2014
115 | 116 | 117 |
Date Generated: 08/19/2014 - 16:57:50
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220 | 221 | 222 | 223 | -------------------------------------------------------------------------------- /project/transmitraw.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/transmitraw.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 16:43:56 07/31/2014 6 | -- Design Name: 7 | -- Module Name: transmitraw - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: An extra utility component used for transmitting the values of the output RAM. This 12 | -- component is used for evaluation purposes in the testbench, but is also synthesizable and can be 13 | -- used to stream the data when the compression process is over. 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | ---------------------------------------------------------------------------------- 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | use IEEE.NUMERIC_STD.ALL; 26 | 27 | entity transmitraw is 28 | Generic ( IMAGE_WIDTH : integer := 256; 29 | IMAGE_HEIGHT : integer := 256; 30 | ADDR_WIDTH : integer := 16 31 | ); 32 | Port ( clk : in STD_LOGIC; 33 | en : in STD_LOGIC; 34 | reset : in STD_LOGIC; 35 | request : in STD_LOGIC; 36 | dataIn : in STD_LOGIC_VECTOR (7 downto 0); 37 | 38 | ready : out STD_LOGIC; 39 | done : out STD_LOGIC; 40 | address : out STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0); 41 | stopAddress : in STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 42 | dataOut : out STD_LOGIC_VECTOR (7 downto 0)); 43 | end transmitraw; 44 | 45 | architecture Behavioral of transmitraw is 46 | type states is ( stateReset, stateWaitForRequest, stateStream, stateStream2, 47 | stateWaitForRequestNext, stateWaitForRequestNext2, 48 | stateFinished, stateFinished2); 49 | signal currentState : states := stateReset; 50 | signal nextState : states := stateReset; 51 | 52 | signal sigDataOut : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); 53 | signal sigAddress : STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0) := (others => '0'); 54 | signal sigReady : STD_LOGIC := '0'; 55 | signal sigDone : STD_LOGIC := '0'; 56 | 57 | constant totalNumPixels : integer := IMAGE_WIDTH * IMAGE_HEIGHT; 58 | 59 | signal numSentPixels : integer := 0; 60 | 61 | begin 62 | -- Synchronous process of the state machine. 63 | process (clk, reset, nextState) 64 | begin 65 | if reset = '1' then 66 | currentState <= stateReset; 67 | elsif rising_edge(clk) then 68 | if en = '1' then 69 | -- Perform all synchronous signal changes. These are changes that 70 | -- cannot be performed in the combinational process because they 71 | -- would infer the usage of implicit latches. Example of such a signal 72 | -- is sigAddress which counts the current address of the pixel to be 73 | -- transmitted. 74 | if (currentState = stateReset) then -- Reset all the counters to zero. 75 | sigAddress <= (others => '0'); 76 | sigDataOut <= (others => '0'); 77 | numSentPixels <= 0; 78 | elsif (currentState = stateWaitForRequestNext2) then -- Increase the address for the data to be sent. 79 | sigAddress <= sigAddress + 1; 80 | elsif (currentState = stateStream2) then -- Set the data to be output to the output data bus, 81 | -- and count the number of sent pixels. 82 | sigDataOut <= dataIn; 83 | numSentPixels <= numSentPixels + 1; 84 | end if; 85 | 86 | currentState <= nextState; 87 | end if; 88 | end if; 89 | end process; 90 | 91 | -- Combinational process of the state machine. 92 | process (currentState, request, numSentPixels, sigAddress, stopAddress) 93 | begin 94 | -- Set the default values for the signals in order to avoid generating latches. 95 | nextState <= stateReset; 96 | sigReady <= '0'; 97 | sigDone <= '0'; 98 | 99 | case currentState is 100 | when stateReset => -- Reset the state machine. 101 | nextState <= stateWaitForRequest; 102 | 103 | when stateWaitForRequest => -- Wait until the first data byte is requested. 104 | if request = '1' then 105 | nextState <= stateStream; 106 | else 107 | nextState <= stateWaitForRequest; 108 | end if; 109 | 110 | when stateStream => -- Start the streaming of the new data byte. 111 | nextState <= stateStream2; 112 | when stateStream2 => 113 | nextState <= stateWaitForRequestNext; -- After the data has been set to the output bus, jump to the waiting state again. 114 | 115 | when stateWaitForRequestNext => -- Waiting state almost the same as stateWaitForRequest, but this state 116 | -- also sets the sigReady signal to notify the outside devices that the data 117 | -- byte is ready, and also increases the count of currently sent data bytes. 118 | sigReady <= '1'; 119 | 120 | if numSentPixels = totalNumPixels or sigAddress = (stopAddress - 1) then 121 | nextState <= stateFinished; 122 | elsif request = '1' then 123 | nextState <= stateWaitForRequestNext2; 124 | else 125 | nextState <= stateWaitForRequestNext; 126 | end if; 127 | when stateWaitForRequestNext2 => -- When a new data byte has been requested, this state is jumped to. 128 | nextState <= stateStream; 129 | 130 | -- Since the results are obtained on the rising edge of the sigReady signal, 131 | -- we must first clear the last obtained byte of data. We do this by 132 | -- resetting and then setting the sigReady signal to give away one 133 | -- last rising edge. 134 | when stateFinished => -- When all data bytes have been sent, loop in the finished state. 135 | sigReady <= '1'; 136 | sigDone <= '1'; 137 | nextState <= stateFinished2; 138 | when stateFinished2 => -- When all data bytes have been sent, loop in the finished state. 139 | sigDone <= '1'; 140 | nextState <= stateFinished2; 141 | end case; 142 | end process; 143 | 144 | -- Set the output signals to their current values. 145 | done <= sigDone; 146 | ready <= sigReady; 147 | address <= sigAddress; 148 | dataOut <= sigDataOut; 149 | 150 | end Behavioral; 151 | -------------------------------------------------------------------------------- /project/wavelet.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | -------------------------------------------------------------------------------- /project/waveleticc.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /project/waveleticc.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:19:12 08/19/2014 6 | -- Design Name: 7 | -- Module Name: waveleticc - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Wavelet Image Compression Component. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | entity waveleticc is 24 | Generic ( IMAGE_WIDTH : integer := 256; 25 | IMAGE_HEIGHT : integer := 256; 26 | ADDR_WIDTH : integer := 16 27 | ); 28 | Port ( clk : in std_logic; 29 | reset : in std_logic; 30 | 31 | ramInAddr : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 32 | ramInEn : out STD_LOGIC := '0'; 33 | ramInData : in STD_LOGIC_VECTOR(7 downto 0); 34 | 35 | ramOutDataIn : out STD_LOGIC_VECTOR(7 downto 0); 36 | ramOutDataOut : in STD_LOGIC_VECTOR(7 downto 0); 37 | ramOutWe : out STD_LOGIC; 38 | ramOutAddr: out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 39 | 40 | isFinishedCompressing : out STD_LOGIC; 41 | compressedDataSize : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) 42 | ); 43 | end waveleticc; 44 | 45 | architecture Behavioral of waveleticc is 46 | 47 | component controlunit is 48 | Generic ( IMAGE_WIDTH : integer := 256; 49 | IMAGE_HEIGHT : integer := 256; 50 | ADDR_WIDTH : integer := 16 51 | ); 52 | Port ( clk : in STD_LOGIC; 53 | reset : in STD_LOGIC; 54 | addrIn : out STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0); 55 | enRamIn: out STD_LOGIC; 56 | resetFifoRow : out STD_LOGIC; 57 | weFifoRow : out STD_LOGIC; 58 | resetFifoColumn : out STD_LOGIC; 59 | weFifoColumn : out STD_LOGIC; 60 | isFinishedProcessing : out STD_LOGIC; 61 | rowReady : out STD_LOGIC; 62 | columnReady : out STD_LOGIC; 63 | readyForNextData : in STD_LOGIC 64 | ); 65 | end component; 66 | 67 | component haarlp is 68 | Port ( x0 : in std_logic_vector(7 downto 0); 69 | x1 : in std_logic_vector(7 downto 0); 70 | y : out std_logic_vector(7 downto 0)); 71 | end component; 72 | 73 | component haarhp is 74 | Port ( x0 : in std_logic_vector(7 downto 0); 75 | x1 : in std_logic_vector(7 downto 0); 76 | y : out std_logic_vector(7 downto 0)); 77 | end component; 78 | 79 | component fifomem is 80 | generic ( 81 | DATA_WIDTH: natural := 8; -- Width of a single data register (i.e. a byte). 82 | FIFO_DEPTH: natural := 2 -- Number of data registers in the FIFO memory (i.e. the width of the image + 1). 83 | ); 84 | port ( 85 | clk: in std_logic; 86 | reset: in std_logic; 87 | we: in std_logic; 88 | dataIn: in std_logic_vector((DATA_WIDTH - 1) downto 0); 89 | dataOutFirst: out std_logic_vector((DATA_WIDTH - 1) downto 0); 90 | dataOutLast: out std_logic_vector((DATA_WIDTH - 1) downto 0) 91 | ); 92 | end component; 93 | 94 | component memcontroler is 95 | Generic ( THRESHOLD : integer := 10; 96 | DATA_WIDTH : integer := 8; 97 | ADDR_WIDTH : integer := 16; 98 | IMAGE_WIDTH : integer := 256; 99 | IMAGE_HEIGHT : integer := 256 100 | ); 101 | Port ( 102 | clk : in STD_LOGIC; 103 | en : in STD_LOGIC; 104 | reset : in STD_LOGIC; 105 | 106 | inLL : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 107 | inLH : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 108 | inHL : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 109 | inHH : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 110 | 111 | rowReady : in STD_LOGIC; 112 | columnReady : in STD_LOGIC; 113 | 114 | address : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 115 | dataOut : out STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 116 | dataIn : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 117 | weOut : out STD_LOGIC; 118 | 119 | compressedDataSize : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 120 | 121 | cuFinishedProcessing : in STD_LOGIC; 122 | finishedCompressing : out STD_LOGIC; 123 | 124 | readyForNextData : out STD_LOGIC 125 | ); 126 | end component; 127 | 128 | signal resetFifoRow : STD_LOGIC := '0'; 129 | signal weFifoRow : STD_LOGIC := '0'; 130 | signal resetFifoColumn : STD_LOGIC := '0'; 131 | signal weFifoColumn : STD_LOGIC := '0'; 132 | 133 | signal x0 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 134 | signal x1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 135 | signal xL0 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 136 | signal xL1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 137 | signal xH0 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 138 | signal xH1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 139 | signal y0L : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 140 | signal y0H : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 141 | signal yLL : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 142 | signal yLH : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 143 | signal yHL : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 144 | signal yHH : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 145 | 146 | signal cuIsFinishedProcessing : STD_LOGIC := '0'; 147 | signal sigCompressedDataSize : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 148 | signal sigIsFinishedCompressing : STD_LOGIC := '0'; 149 | signal rowReady, columnReady, readyForNextData : STD_LOGIC := '0'; 150 | 151 | begin 152 | cu: component controlunit generic map ( IMAGE_WIDTH => IMAGE_WIDTH, 153 | IMAGE_HEIGHT => IMAGE_HEIGHT, 154 | ADDR_WIDTH => ADDR_WIDTH) 155 | port map ( clk => clk, 156 | reset => reset, 157 | addrIn => ramInAddr, 158 | enRamIn => ramInEn, 159 | resetFifoRow => resetFifoRow, 160 | weFifoRow => weFifoRow, 161 | resetFifoColumn => resetFifoColumn, 162 | weFifoColumn => weFifoColumn, 163 | isFinishedProcessing => cuIsFinishedProcessing, 164 | rowReady => rowReady, 165 | columnReady => columnReady, 166 | readyForNextData => readyForNextData); 167 | 168 | fifoRow: component fifomem generic map ( DATA_WIDTH => 8, 169 | FIFO_DEPTH => 2) 170 | port map ( clk => clk, 171 | reset => resetFifoRow, 172 | we => weFifoRow, 173 | dataIn => ramInData, 174 | dataOutFirst => x0, 175 | dataOutLast => x1); 176 | 177 | fifoColumnW: component fifomem generic map ( DATA_WIDTH => 8, 178 | FIFO_DEPTH => (IMAGE_WIDTH + 1)) 179 | port map ( clk => clk, 180 | reset => resetFifoColumn, 181 | we => weFifoColumn, 182 | dataIn => y0L, 183 | dataOutFirst => xL0, 184 | dataOutLast => xL1); 185 | 186 | fifoColumnH: component fifomem generic map ( DATA_WIDTH => 8, 187 | FIFO_DEPTH => (IMAGE_WIDTH + 1)) 188 | port map ( clk => clk, 189 | reset => resetFifoColumn, 190 | we => weFifoColumn, 191 | dataIn => y0H, 192 | dataOutFirst => xH0, 193 | dataOutLast => xH1); 194 | 195 | W0L: component haarlp port map ( x0 => x0, 196 | x1 => x1, 197 | y => y0L); 198 | 199 | WLL: component haarlp port map ( x0 => xL0, 200 | x1 => xL1, 201 | y => yLL); 202 | 203 | WLH: component haarhp port map ( x0 => xL0, 204 | x1 => xL1, 205 | y => yLH); 206 | 207 | 208 | W0H: component haarhp port map ( x0 => x0, 209 | x1 => x1, 210 | y => y0H); 211 | 212 | WHL: component haarlp port map ( x0 => xH0, 213 | x1 => xH1, 214 | y => yHL); 215 | 216 | WHH: component haarhp port map ( x0 => xH0, 217 | x1 => xH1, 218 | y => yHH); 219 | 220 | compressor: component memcontroler generic map ( THRESHOLD => 10, 221 | DATA_WIDTH => 8, 222 | ADDR_WIDTH => 16, 223 | IMAGE_WIDTH => 256, 224 | IMAGE_HEIGHT => 256) 225 | port map ( clk => clk, 226 | en => '1', 227 | reset => reset, 228 | inLL => yLL, 229 | inLH => yLH, 230 | inHL => yHL, 231 | inHH => yHH, 232 | rowReady => rowReady, 233 | columnReady => columnReady, 234 | address => ramOutAddr, 235 | dataOut => ramOutDataIn, 236 | dataIn => ramOutDataOut, 237 | weOut => ramOutWe, 238 | compressedDataSize => sigCompressedDataSize, 239 | cuFinishedProcessing => cuIsFinishedProcessing, 240 | finishedCompressing => sigIsFinishedCompressing, 241 | readyForNextData => readyForNextData); 242 | 243 | 244 | isFinishedCompressing <= sigIsFinishedCompressing; 245 | compressedDataSize <= sigCompressedDataSize when (sigIsFinishedCompressing = '1') else (others => '0'); 246 | 247 | end Behavioral; 248 | -------------------------------------------------------------------------------- /project/webtalk_pn.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
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45 | 46 | 47 | -------------------------------------------------------------------------------- /project/xst/work/work.vdbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/project/xst/work/work.vdbl -------------------------------------------------------------------------------- /project/xst/work/work.vdbx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/isovic/wavelet-image-compression/f66d629bb25318e972e2b9381c8bd265d8417a9d/project/xst/work/work.vdbx -------------------------------------------------------------------------------- /vhdl_only/controlunit.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 14:05:53 07/29/2014 6 | -- Design Name: 7 | -- Module Name: controlunit - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Implements a state machine which accesses and streams data from the input ROM. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use IEEE.NUMERIC_STD.ALL; 24 | 25 | entity controlunit is 26 | Generic ( IMAGE_WIDTH : integer := 256; 27 | IMAGE_HEIGHT : integer := 256; 28 | ADDR_WIDTH : integer := 16 29 | ); 30 | Port ( clk : in STD_LOGIC; 31 | reset : in STD_LOGIC; 32 | 33 | addrIn : out STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0); 34 | 35 | enRamIn : out STD_LOGIC; 36 | 37 | resetFifoRow : out STD_LOGIC; 38 | weFifoRow : out STD_LOGIC; 39 | resetFifoColumn : out STD_LOGIC; 40 | weFifoColumn : out STD_LOGIC; 41 | 42 | -- isStreamingData : out STD_LOGIC; 43 | isFinishedProcessing : out STD_LOGIC; 44 | 45 | rowReady : out STD_LOGIC; 46 | columnReady : out STD_LOGIC; 47 | readyForNextData : in STD_LOGIC 48 | ); 49 | end controlunit; 50 | 51 | architecture Behavioral of controlunit is 52 | type states is (stateReset, stateReset2, stateStream, stateStream0, stateStream1, stateStream2, stateStream3, stateNewRow, stateNewRow2, stateFinished); 53 | signal currentState : states := stateReset; 54 | signal nextState : states := stateReset; 55 | 56 | signal sigAddrIn : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 57 | signal sigEnRamIn : STD_LOGIC := '0'; 58 | signal sigResetFifoRow, sigWeFifoRow, sigResetFifoColumn, sigWeFifoColumn : STD_LOGIC := '0'; 59 | signal sigIsFinishedProcessing : STD_LOGIC := '0'; 60 | 61 | signal numPixels : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 62 | signal totalNumPixels : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 63 | signal numRows : integer := 0; 64 | 65 | signal sigRowReady : STD_LOGIC := '0'; 66 | signal sigColumnReady : STD_LOGIC := '1'; 67 | 68 | begin 69 | -- Synchronous process of the state machine. 70 | process (clk, reset, nextState) 71 | begin 72 | if reset = '1' then 73 | currentState <= stateReset; 74 | elsif rising_edge(clk) then 75 | -- Perform all synchronous signal changes. These are changes that 76 | -- cannot be performed in the combinational process because they 77 | -- would infer the usage of implicit latches. Example of such a signal 78 | -- is sigAddrIn which counts the current address of the pixel to be 79 | -- analyzed. 80 | if currentState = stateReset then -- Reset all signals used for counting to zero. 81 | numPixels <= (others => '0'); 82 | totalNumPixels <= (others => '0'); 83 | sigColumnReady <= '1'; 84 | sigRowReady <= '0'; 85 | numRows <= 0; 86 | sigAddrIn <= (others => '0'); 87 | 88 | elsif currentState = stateStream0 then -- Increase the counts of pixels, numPixels counts the number of pixels 89 | -- processed in the current row, while totalNumPixels counts the overall 90 | -- pixels of the image processed so far. 91 | numPixels <= numPixels + 1; 92 | totalNumPixels <= totalNumPixels + 1; 93 | sigColumnReady <= not sigColumnReady; -- This signal is used for decimating columns (every other pixel is not 94 | -- taken into account, or in other words, only when sigColumnReady is high 95 | -- the signal will be processed by the memcontroler). 96 | 97 | elsif currentState = stateStream3 then -- Increase the current address for reading input data. 98 | sigAddrIn <= sigAddrIn + 1; 99 | 100 | elsif currentState = stateNewRow then -- If the end of the row has been hit, clear the numPixels count and increase 101 | -- the count of rows processed (numRows). 102 | numRows <= numRows + 1; 103 | numPixels <= (others => '0'); 104 | sigColumnReady <= '0'; 105 | sigRowReady <= not sigRowReady; -- This signal is used for decimating rows (every other row is not 106 | -- taken into account, or in other words, only when sigColumnReady is high 107 | -- the signal will be processed by the memcontroler). 108 | 109 | elsif currentState = stateFinished then -- If we have finished processing the input data, drive the ready signals low. 110 | sigRowReady <= '0'; 111 | sigColumnReady <= '0'; 112 | end if; 113 | 114 | 115 | 116 | -- Change the current state 117 | currentState <= nextState; 118 | 119 | end if; 120 | end process; 121 | 122 | -- Combinational process of the state machine. 123 | process (currentState, numPixels, numRows, readyForNextData) 124 | begin 125 | -- Set the default values for the signals in order to avoid generating latches. 126 | nextState <= stateReset; 127 | sigEnRamIn <= '0'; 128 | sigResetFifoRow <= '0'; 129 | sigWeFifoRow <= '0'; 130 | sigResetFifoColumn <= '0'; 131 | sigWeFifoColumn <= '0'; 132 | sigIsFinishedProcessing <= '0'; 133 | 134 | case currentState is 135 | -- Initialize all components of the design. 136 | when stateReset => -- Drive reset signals high. 137 | sigResetFifoRow <= '1'; 138 | sigResetFifoColumn <= '1'; 139 | nextState <= stateReset2; 140 | when stateReset2 => -- Lower the reset signals. 141 | nextState <= stateStream; 142 | 143 | -- Wait until the memcontroler component (which stores 144 | -- current decomposition values to memory) returns 145 | -- readyForNextData signal. 146 | when stateStream => -- Wait for ready signal to start streaming. 147 | if readyForNextData = '1' then 148 | nextState <= stateStream0; 149 | else 150 | nextState <= stateStream; 151 | end if; 152 | -- Start streaming new pixel of the image from input 153 | -- through FIFO memories and wavelet filters. 154 | when stateStream0 => -- Start streaming. Enable the input ROM. 155 | sigEnRamIn <= '1'; 156 | nextState <= stateStream1; 157 | 158 | when stateStream1 => -- Enable writing new data to the FIFO row component. 159 | sigEnRamIn <= '1'; 160 | sigWeFifoRow <= '1'; 161 | nextState <= stateStream2; 162 | 163 | when stateStream2 => -- Disable writing data to the FIFO row component, and 164 | -- enable writing the filtered data to the FIFO column component. 165 | sigEnRamIn <= '1'; 166 | sigWeFifoColumn <= '1'; 167 | nextState <= stateStream3; 168 | 169 | when stateStream3 => -- Disable writing to all FIFO memories. 170 | sigEnRamIn <= '1'; 171 | 172 | -- Check if we have reached the end of the row. In this case, the FIFO row component needs 173 | -- to be reset, because otherwise we would filter the last pixel of the current line and 174 | -- the first pixel of the next line together (would produce an errouneous signal). 175 | if numPixels = (IMAGE_WIDTH) then 176 | nextState <= stateNewRow; 177 | else 178 | nextState <= stateStream; 179 | end if; 180 | 181 | when stateNewRow => -- If we ran into the end of the row, reset the FIFO row component. 182 | sigEnRamIn <= '1'; 183 | sigResetFifoRow <= '1'; 184 | nextState <= stateNewRow2; 185 | 186 | when stateNewRow2 => -- Return the reset signal for the FIFO row component back to inactive state. 187 | sigEnRamIn <= '1'; 188 | 189 | -- Check if we have reached the end of the image. 190 | if numRows = IMAGE_HEIGHT then 191 | nextState <= stateFinished; 192 | else 193 | nextState <= stateStream; 194 | end if; 195 | 196 | when stateFinished => -- If the entire image has been processed, loop indefinetly. 197 | sigIsFinishedProcessing <= '1'; 198 | nextState <= stateFinished; 199 | 200 | end case; 201 | end process; 202 | 203 | -- Set the output signals to their current values. 204 | addrIn <= sigAddrIn; 205 | enRamIn <= sigEnRamIn; 206 | resetFifoRow <= sigResetFifoRow; 207 | weFifoRow <= sigWeFifoRow; 208 | resetFifoColumn <= sigResetFifoColumn; 209 | weFifoColumn <= sigWeFifoColumn; 210 | isFinishedProcessing <= sigIsFinishedProcessing; 211 | 212 | rowReady <= sigRowReady; 213 | columnReady <= sigColumnReady; 214 | end Behavioral; 215 | -------------------------------------------------------------------------------- /vhdl_only/fifomem.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 23:35:22 07/28/2014 6 | -- Design Name: 7 | -- Module Name: fifomem - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Implementation of an n-bit shift register, which provides output of the first and last element in the chain. Synthesis will produce distributed RAM. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | entity fifomem is 24 | generic ( 25 | DATA_WIDTH: natural := 8; -- Width of a single data register (i.e. a byte). 26 | FIFO_DEPTH: natural := 2 -- Number of data registers in the FIFO memory (i.e. the width of the image + 1). 27 | ); 28 | port ( 29 | clk: in std_logic; 30 | reset: in std_logic; 31 | we: in std_logic; 32 | dataIn: in std_logic_vector((DATA_WIDTH - 1) downto 0); 33 | dataOutFirst: out std_logic_vector((DATA_WIDTH - 1) downto 0); 34 | dataOutLast: out std_logic_vector((DATA_WIDTH - 1) downto 0) 35 | ); 36 | end fifomem; 37 | 38 | architecture RTL of fifomem is 39 | type ramtype is array(0 to (FIFO_DEPTH - 1)) of std_logic_vector((DATA_WIDTH - 1) downto 0); 40 | 41 | signal RAM : ramtype := (others => (others => '0')); 42 | 43 | begin 44 | process (clk, reset) 45 | begin 46 | if reset = '1' then 47 | RAM <= (others => (others => '0')); 48 | elsif rising_edge(clk) then 49 | if we = '1' then 50 | RAM <= dataIn & RAM(0 to (FIFO_DEPTH - 2)); 51 | end if; 52 | end if; 53 | end process; 54 | 55 | dataOutFirst <= RAM(0); 56 | dataOutLast <= RAM(FIFO_DEPTH - 1); 57 | end RTL; 58 | -------------------------------------------------------------------------------- /vhdl_only/haarhp.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 10:50:14 03/27/2014 6 | -- Design Name: 7 | -- Module Name: haarhp - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Haar high-pass wavelet filter. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_unsigned.all; 23 | use ieee.numeric_std.all; 24 | 25 | entity haarhp is 26 | Port ( x0 : in std_logic_vector(7 downto 0); 27 | x1 : in std_logic_vector(7 downto 0); 28 | y : out std_logic_vector(7 downto 0)); 29 | end haarhp; 30 | 31 | architecture Behavioral of haarhp is 32 | 33 | begin 34 | y <= std_logic_vector(to_unsigned(((conv_integer(x0) - conv_integer(x1)) / 2), 8)); 35 | end Behavioral; 36 | -------------------------------------------------------------------------------- /vhdl_only/haarlp.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:00:42 03/27/2014 6 | -- Design Name: 7 | -- Module Name: haarlp - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Haar low-pass wavelet filter. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_unsigned.all; 23 | use ieee.numeric_std.all; 24 | 25 | entity haarlp is 26 | Port ( x0 : in std_logic_vector(7 downto 0); 27 | x1 : in std_logic_vector(7 downto 0); 28 | y : out std_logic_vector(7 downto 0)); 29 | end haarlp; 30 | 31 | architecture Behavioral of haarlp is 32 | 33 | begin 34 | y <= std_logic_vector(to_unsigned(((conv_integer(x0) + conv_integer(x1)) / 2), 8)); 35 | end Behavioral; 36 | 37 | -------------------------------------------------------------------------------- /vhdl_only/ramfile.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:59:36 03/26/2014 6 | -- Design Name: 7 | -- Module Name: ramfile - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_unsigned.all; 23 | use std.textio.all; 24 | 25 | entity ramfile is 26 | generic (RAM_SIZE : integer := 65536 27 | ); 28 | port (clk : in std_logic; 29 | we : in std_logic; 30 | en : in std_logic; 31 | addr : in std_logic_vector(15 downto 0); 32 | dataIn : in std_logic_vector(7 downto 0); 33 | dataOut : out std_logic_vector(7 downto 0)); 34 | end ramfile; 35 | 36 | 37 | 38 | -- The following code will infer a Single port Block RAM and initialize it using a FILE 39 | 40 | architecture Behavioral of ramfile is 41 | type ramtype is array(0 to (RAM_SIZE - 1)) of std_logic_vector(7 downto 0); 42 | 43 | impure function ramLoad (ram_file_name : in string) return ramtype is 44 | FILE ram_file : text is in ram_file_name; 45 | variable line_name : line; 46 | variable temp_bv : bit_vector(7 downto 0); 47 | variable temp_ram : ramtype; 48 | begin 49 | for I in ramtype'range loop 50 | readline (ram_file, line_name); 51 | read (line_name, temp_bv); 52 | temp_ram(I) := to_stdlogicvector(temp_bv); 53 | end loop; 54 | return temp_ram; 55 | end function; 56 | 57 | signal RAM : ramtype := ramLoad("../data/lena256bw.txt"); 58 | 59 | begin 60 | process (clk) 61 | begin 62 | if clk'event and clk = '1' then 63 | if EN = '1' then 64 | if WE = '1' then 65 | RAM(conv_integer(addr)) <= dataIn; 66 | end if; 67 | dataOut <= RAM(conv_integer(addr)) ; 68 | end if; 69 | end if; 70 | end process; 71 | 72 | end Behavioral; 73 | 74 | -------------------------------------------------------------------------------- /vhdl_only/ramnormal.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:59:36 03/26/2014 6 | -- Design Name: 7 | -- Module Name: ramfile - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use ieee.std_logic_unsigned.all; 23 | use std.textio.all; 24 | 25 | entity ramnormal is 26 | generic ( RAM_SIZE : integer := 65536; 27 | ADDR_WIDTH : integer := 16 28 | ); 29 | port (clk : in std_logic; 30 | we : in std_logic; 31 | en : in std_logic; 32 | addr : in std_logic_vector((ADDR_WIDTH - 1) downto 0); 33 | dataIn : in std_logic_vector(7 downto 0); 34 | dataOut : out std_logic_vector(7 downto 0)); 35 | end ramnormal; 36 | 37 | 38 | 39 | -- The following code will infer a Single port Block RAM and initialize it using a FILE 40 | 41 | architecture Behavioral of ramnormal is 42 | type ramtype is array(0 to (RAM_SIZE - 1)) of std_logic_vector(7 downto 0); 43 | 44 | impure function ramLoad (ram_file_name : in string) return ramtype is 45 | FILE ram_file : text is in ram_file_name; 46 | variable line_name : line; 47 | variable temp_bv : bit_vector(7 downto 0); 48 | variable temp_ram : ramtype; 49 | begin 50 | for I in ramtype'range loop 51 | readline (ram_file, line_name); 52 | read (line_name, temp_bv); 53 | temp_ram(I) := to_stdlogicvector(temp_bv); 54 | end loop; 55 | return temp_ram; 56 | end function; 57 | 58 | signal RAM : ramtype := (others => "00000000"); -- ramLoad("../data/lena256bw.txt"); 59 | 60 | begin 61 | process (clk) 62 | begin 63 | if clk'event and clk = '1' then 64 | if EN = '1' then 65 | if WE = '1' then 66 | RAM(conv_integer(addr)) <= dataIn; 67 | end if; 68 | dataOut <= RAM(conv_integer(addr)) ; 69 | end if; 70 | end if; 71 | end process; 72 | 73 | end Behavioral; 74 | 75 | -------------------------------------------------------------------------------- /vhdl_only/tb_fifomem.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 10:38:45 07/29/2014 6 | -- Design Name: 7 | -- Module Name: tb_fifomem.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: fifomem 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | USE ieee.numeric_std.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --USE ieee.numeric_std.ALL; 28 | 29 | ENTITY tb_fifomem IS 30 | END tb_fifomem; 31 | 32 | ARCHITECTURE behavior OF tb_fifomem IS 33 | 34 | -- Component Declaration for the Unit Under Test (UUT) 35 | 36 | COMPONENT fifomem 37 | GENERIC ( 38 | DATA_WIDTH: natural := 8; -- Width of a single data register (i.e. a byte). 39 | FIFO_DEPTH: natural := 2 -- Number of data registers in the FIFO memory (i.e. the width of the image + 1). 40 | ); 41 | PORT( 42 | clk : IN std_logic; 43 | reset : IN std_logic; 44 | we: in std_logic; 45 | dataIn : IN std_logic_vector(7 downto 0); 46 | dataOutFirst: out std_logic_vector((DATA_WIDTH - 1) downto 0); 47 | dataOutLast: out std_logic_vector((DATA_WIDTH - 1) downto 0) 48 | ); 49 | END COMPONENT; 50 | 51 | --Inputs 52 | signal clk : std_logic := '0'; 53 | signal reset : std_logic := '0'; 54 | signal dataIn : std_logic_vector(7 downto 0) := (others => '0'); 55 | signal we : std_logic := '0'; 56 | 57 | --Outputs 58 | signal dataOutFirst : std_logic_vector(7 downto 0); 59 | signal dataOutLast : std_logic_vector(7 downto 0); 60 | 61 | -- Clock period definitions 62 | constant clk_period : time := 10 ns; 63 | 64 | BEGIN 65 | 66 | -- Instantiate the Unit Under Test (UUT) 67 | uut: fifomem 68 | GENERIC MAP (DATA_WIDTH => 8, FIFO_DEPTH => 4) 69 | PORT MAP ( 70 | clk => clk, 71 | reset => reset, 72 | we => we, 73 | dataIn => dataIn, 74 | dataOutFirst => dataOutFirst, 75 | dataOutLast => dataOutLast 76 | ); 77 | 78 | -- Clock process definitions 79 | clk_process :process 80 | begin 81 | clk <= '0'; 82 | wait for clk_period/2; 83 | clk <= '1'; 84 | wait for clk_period/2; 85 | end process; 86 | 87 | -- Stimulus process 88 | stim_proc: process 89 | variable dataCounter: integer := 1; 90 | begin 91 | -- hold reset state for 100 ns. 92 | reset <= '1'; 93 | wait for 100 ns; 94 | reset <= '0'; 95 | we <= '1'; 96 | 97 | wait for clk_period; 98 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 99 | dataCounter := dataCounter + 1; 100 | wait for clk_period; 101 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 102 | dataCounter := dataCounter + 1; 103 | wait for clk_period; 104 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 105 | dataCounter := dataCounter + 1; 106 | wait for clk_period; 107 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 108 | dataCounter := dataCounter + 1; 109 | wait for clk_period; 110 | dataIn <= std_logic_vector(to_unsigned(dataCounter, dataIn'length)); 111 | dataCounter := dataCounter + 1; 112 | 113 | wait for clk_period*10; 114 | 115 | wait; 116 | end process; 117 | 118 | END; 119 | -------------------------------------------------------------------------------- /vhdl_only/tb_haarhp.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 11:05:28 03/27/2014 6 | -- Design Name: 7 | -- Module Name: tb_haarhp.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: haarhp 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --USE ieee.numeric_std.ALL; 27 | 28 | ENTITY tb_haarhp IS 29 | END tb_haarhp; 30 | 31 | ARCHITECTURE behavior OF tb_haarhp IS 32 | 33 | -- Component Declaration for the Unit Under Test (UUT) 34 | 35 | COMPONENT haarhp 36 | PORT( 37 | x0 : IN std_logic_vector(7 downto 0); 38 | x1 : IN std_logic_vector(7 downto 0); 39 | y : OUT std_logic_vector(7 downto 0) 40 | ); 41 | END COMPONENT; 42 | 43 | 44 | --Inputs 45 | signal x0 : std_logic_vector(7 downto 0) := (others => '0'); 46 | signal x1 : std_logic_vector(7 downto 0) := (others => '0'); 47 | signal reset : std_logic := '0'; 48 | 49 | --Outputs 50 | signal y : std_logic_vector(7 downto 0); 51 | -- No clocks detected in port list. Replace below with 52 | -- appropriate port name 53 | 54 | constant clock_period : time := 10 ns; 55 | signal clock : std_logic := '0'; 56 | 57 | BEGIN 58 | 59 | -- Instantiate the Unit Under Test (UUT) 60 | uut: haarhp PORT MAP ( 61 | x0 => x0, 62 | x1 => x1, 63 | y => y 64 | ); 65 | 66 | -- Clock process definitions 67 | clock_process :process 68 | begin 69 | clock <= '0'; 70 | wait for clock_period/2; 71 | clock <= '1'; 72 | wait for clock_period/2; 73 | end process; 74 | 75 | 76 | -- Stimulus process 77 | stim_proc: process 78 | begin 79 | -- hold reset state for 100 ns. 80 | reset <= '1'; 81 | wait for 100 ns; 82 | 83 | reset <= '0'; 84 | wait for 100 ns; 85 | 86 | x0 <= x"02"; 87 | x1 <= x"00"; 88 | wait for clock_period; 89 | 90 | x0 <= x"03"; 91 | x1 <= x"02"; 92 | wait for clock_period; 93 | 94 | x0 <= x"07"; 95 | x1 <= x"03"; 96 | wait for clock_period; 97 | 98 | x0 <= x"12"; 99 | x1 <= x"07"; 100 | wait for clock_period; 101 | 102 | x0 <= x"FA"; 103 | x1 <= x"12"; 104 | wait for clock_period; 105 | 106 | x0 <= x"00"; 107 | x1 <= x"FA"; 108 | wait for clock_period; 109 | 110 | x0 <= x"20"; 111 | x1 <= x"00"; 112 | wait for clock_period; 113 | 114 | reset <= '1'; 115 | x0 <= x"00"; 116 | x1 <= x"00"; 117 | wait for clock_period; 118 | reset <= '0'; 119 | wait for clock_period; 120 | 121 | x0 <= x"00"; 122 | x1 <= x"00"; 123 | wait for clock_period; 124 | x0 <= x"FF"; 125 | x1 <= x"00"; 126 | wait for clock_period; 127 | x0 <= x"FF"; 128 | x1 <= x"FF"; 129 | wait for clock_period; 130 | 131 | wait for clock_period*10; 132 | 133 | -- insert stimulus here 134 | 135 | wait; 136 | end process; 137 | 138 | END; 139 | -------------------------------------------------------------------------------- /vhdl_only/tb_haarlp.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:03:41 03/27/2014 6 | -- Design Name: 7 | -- Module Name: tb_haarlp.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: haarlp 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --USE ieee.numeric_std.ALL; 27 | 28 | ENTITY tb_haarlp IS 29 | END tb_haarlp; 30 | 31 | ARCHITECTURE behavior OF tb_haarlp IS 32 | 33 | -- Component Declaration for the Unit Under Test (UUT) 34 | 35 | COMPONENT haarlp 36 | PORT( 37 | x0 : IN std_logic_vector(7 downto 0); 38 | x1 : IN std_logic_vector(7 downto 0); 39 | y : OUT std_logic_vector(7 downto 0) 40 | ); 41 | END COMPONENT; 42 | 43 | 44 | --Inputs 45 | signal x0 : std_logic_vector(7 downto 0) := (others => '0'); 46 | signal x1 : std_logic_vector(7 downto 0) := (others => '0'); 47 | 48 | --Outputs 49 | signal y : std_logic_vector(7 downto 0); 50 | -- No clocks detected in port list. Replace below with 51 | -- appropriate port name 52 | 53 | constant clock_period : time := 10 ns; 54 | 55 | BEGIN 56 | 57 | -- Instantiate the Unit Under Test (UUT) 58 | uut: haarlp PORT MAP ( 59 | x0 => x0, 60 | x1 => x1, 61 | y => y 62 | ); 63 | 64 | -- -- Clock process definitions 65 | -- _process :process 66 | -- begin 67 | -- <= '0'; 68 | -- wait for _period/2; 69 | -- <= '1'; 70 | -- wait for _period/2; 71 | -- end process; 72 | 73 | 74 | -- Stimulus process 75 | stim_proc: process 76 | begin 77 | -- hold reset state for 100 ns. 78 | wait for 100 ns; 79 | 80 | x0 <= x"02"; 81 | x1 <= x"00"; 82 | wait for clock_period; 83 | 84 | x0 <= x"03"; 85 | x1 <= x"02"; 86 | wait for clock_period; 87 | 88 | x0 <= x"07"; 89 | x1 <= x"03"; 90 | wait for clock_period; 91 | 92 | x0 <= x"12"; 93 | x1 <= x"07"; 94 | wait for clock_period; 95 | 96 | x0 <= x"FA"; 97 | x1 <= x"12"; 98 | wait for clock_period; 99 | 100 | x0 <= x"00"; 101 | x1 <= x"FA"; 102 | wait for clock_period; 103 | 104 | x0 <= x"20"; 105 | x1 <= x"00"; 106 | wait for clock_period; 107 | 108 | x0 <= x"00"; 109 | x1 <= x"00"; 110 | wait for clock_period; 111 | x0 <= x"FF"; 112 | x1 <= x"00"; 113 | wait for clock_period; 114 | x0 <= x"FF"; 115 | x1 <= x"FF"; 116 | wait for clock_period; 117 | 118 | wait for clock_period*10; 119 | -- insert stimulus here 120 | 121 | wait; 122 | end process; 123 | 124 | END; 125 | -------------------------------------------------------------------------------- /vhdl_only/tb_ramfile.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 18:00:57 03/26/2014 6 | -- Design Name: 7 | -- Module Name: tb_ramfile.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: ramfile 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | use ieee.std_logic_unsigned.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --USE ieee.numeric_std.ALL; 28 | 29 | ENTITY tb_ramfile IS 30 | END tb_ramfile; 31 | 32 | ARCHITECTURE behavior OF tb_ramfile IS 33 | 34 | -- Component Declaration for the Unit Under Test (UUT) 35 | 36 | COMPONENT ramfile 37 | PORT( 38 | clk : IN std_logic; 39 | we : IN std_logic; 40 | en : IN std_logic; 41 | addr : IN std_logic_vector(15 downto 0); 42 | dataIn : IN std_logic_vector(7 downto 0); 43 | dataOut : OUT std_logic_vector(7 downto 0) 44 | ); 45 | END COMPONENT; 46 | 47 | --Inputs 48 | signal clk : std_logic := '0'; 49 | signal we : std_logic := '0'; 50 | signal en : std_logic := '0'; 51 | signal addr : std_logic_vector(15 downto 0) := (others => '0'); 52 | signal dataIn : std_logic_vector(7 downto 0) := (others => '0'); 53 | 54 | --Outputs 55 | signal dataOut : std_logic_vector(7 downto 0); 56 | 57 | -- Clock period definitions 58 | constant clk_period : time := 10 ns; 59 | 60 | BEGIN 61 | 62 | -- Instantiate the Unit Under Test (UUT) 63 | uut: ramfile PORT MAP ( 64 | clk => clk, 65 | we => we, 66 | en => en, 67 | addr => addr, 68 | dataIn => dataIn, 69 | dataOut => dataOut 70 | ); 71 | 72 | -- Clock process definitions 73 | clk_process :process 74 | begin 75 | clk <= '0'; 76 | wait for clk_period/2; 77 | clk <= '1'; 78 | wait for clk_period/2; 79 | end process; 80 | 81 | 82 | -- Stimulus process 83 | stim_proc: process 84 | begin 85 | -- hold reset state for 100 ns. 86 | wait for 100 ns; 87 | 88 | wait for clk_period*10; 89 | addr <= addr + '1'; 90 | en <= '1'; 91 | 92 | wait for clk_period*10; 93 | addr <= addr + '1'; 94 | 95 | wait for clk_period*10; 96 | addr <= addr + '1'; 97 | 98 | wait for clk_period*10; 99 | addr <= addr + '1'; 100 | 101 | wait for clk_period*10; 102 | addr <= addr + '1'; 103 | 104 | -- insert stimulus here 105 | 106 | wait; 107 | end process; 108 | 109 | END; 110 | -------------------------------------------------------------------------------- /vhdl_only/tb_top.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 09:35:29 03/27/2014 6 | -- Design Name: 7 | -- Module Name: tb_top.vhd 8 | -- Project Name: wavelet 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: top 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -------------------------------------------------------------------------------- 21 | LIBRARY ieee; 22 | USE ieee.std_logic_1164.ALL; 23 | USE IEEE.std_logic_textio.all; 24 | USE STD.textio.all; 25 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; 26 | USE IEEE.NUMERIC_STD.ALL; 27 | USE IEEE.STD_LOGIC_ARITH.ALL; 28 | 29 | -- Uncomment the following library declaration if using 30 | -- arithmetic functions with Signed or Unsigned values 31 | --USE ieee.numeric_std.ALL; 32 | 33 | ENTITY tb_top IS 34 | END tb_top; 35 | 36 | ARCHITECTURE behavior OF tb_top IS 37 | 38 | -- Component Declaration for the Unit Under Test (UUT) 39 | 40 | COMPONENT top 41 | Generic ( IMAGE_WIDTH : integer := 256; 42 | IMAGE_HEIGHT : integer := 256; 43 | ADDR_WIDTH : integer := 16 44 | ); 45 | Port ( clk : in std_logic; 46 | reset : in std_logic; 47 | requestNewData : in std_logic; 48 | 49 | outData : out std_logic_vector(7 downto 0); 50 | isFinishedProcessing : out std_logic; 51 | outDataReady : out std_logic; 52 | isFinishedTransmitting : out std_logic 53 | ); 54 | END COMPONENT; 55 | 56 | --Inputs 57 | signal clk : std_logic := '0'; 58 | signal reset : std_logic := '0'; 59 | signal requestNewData : std_logic := '0'; 60 | 61 | --Outputs 62 | signal outData : std_logic_vector(7 downto 0) := (others => '0'); 63 | signal outDataReady : std_logic := '0'; 64 | signal isFinishedTransmitting : std_logic := '0'; 65 | signal isFinishedProcessing : std_logic := '0'; 66 | 67 | -- Clock period definitions 68 | constant clk_period : time := 10 ns; 69 | 70 | BEGIN 71 | 72 | -- Instantiate the Unit Under Test (UUT) 73 | uut: top GENERIC MAP ( 74 | IMAGE_WIDTH => 256, 75 | IMAGE_HEIGHT => 256, 76 | ADDR_WIDTH => 16) 77 | PORT MAP ( 78 | clk => clk, 79 | reset => reset, 80 | outData => outData, 81 | isFinishedProcessing => isFinishedProcessing, 82 | outDataReady => outDataReady, 83 | isFinishedTransmitting => isFinishedTransmitting, 84 | requestNewData => requestNewData 85 | ); 86 | 87 | -- Clock process definitions 88 | clk_process :process 89 | begin 90 | clk <= '0'; 91 | wait for clk_period/2; 92 | clk <= '1'; 93 | wait for clk_period/2; 94 | end process; 95 | 96 | 97 | -- Stimulus process 98 | stim_proc: process 99 | begin 100 | reset <= '1'; 101 | -- hold reset state for 100 ns. 102 | wait for 100 ns; 103 | reset <= '0'; 104 | 105 | wait until isFinishedProcessing'event and isFinishedProcessing = '1'; 106 | 107 | wait; 108 | end process; 109 | 110 | -- Simulate for 7000.00us in order to write the entire memory to file. 111 | writeToDisk: process 112 | file ramOutFile: TEXT open WRITE_MODE is "../data/compressed.out"; 113 | variable myLine : LINE; 114 | variable myOutputLine : LINE; 115 | begin 116 | if isFinishedProcessing = '1' then 117 | wait for clk_period; 118 | requestNewData <= '1'; 119 | 120 | wait until rising_edge(outDataReady); 121 | write(myOutputLine, conv_integer(outData)); 122 | writeline(ramOutFile, myOutputLine); 123 | requestNewData <= '0'; 124 | 125 | if isFinishedTransmitting = '1' then 126 | wait; 127 | end if; 128 | end if; 129 | 130 | wait for clk_period; 131 | end process; 132 | 133 | END; 134 | -------------------------------------------------------------------------------- /vhdl_only/top.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 09:14:39 03/27/2014 6 | -- Design Name: 7 | -- Module Name: top - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Top-level design for testing the Wavelet Image Compression Component. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 23 | use IEEE.NUMERIC_STD.ALL; 24 | 25 | entity top is 26 | Generic ( IMAGE_WIDTH : integer := 256; 27 | IMAGE_HEIGHT : integer := 256; 28 | ADDR_WIDTH : integer := 16 29 | ); 30 | Port ( clk : in std_logic; 31 | reset : in std_logic; 32 | 33 | outData : out std_logic_vector(7 downto 0); 34 | isFinishedProcessing : out std_logic; 35 | 36 | outDataReady : out std_logic; 37 | isFinishedTransmitting : out std_logic; 38 | requestNewData : in std_logic 39 | ); 40 | end top; 41 | 42 | architecture Behavioral of top is 43 | component ramfile is 44 | generic (RAM_SIZE : integer := 65536 45 | ); 46 | port (clk : in std_logic; 47 | we : in std_logic; 48 | en : in std_logic; 49 | addr : in std_logic_vector(15 downto 0); 50 | dataIn : in std_logic_vector(7 downto 0); 51 | dataOut : out std_logic_vector(7 downto 0)); 52 | end component; 53 | 54 | component ramnormal is 55 | generic ( RAM_SIZE : integer := 65536; 56 | ADDR_WIDTH : integer := 16 57 | ); 58 | port (clk : in std_logic; 59 | we : in std_logic; 60 | en : in std_logic; 61 | addr : in std_logic_vector((ADDR_WIDTH - 1) downto 0); 62 | dataIn : in std_logic_vector(7 downto 0); 63 | dataOut : out std_logic_vector(7 downto 0)); 64 | end component; 65 | 66 | component waveleticc is 67 | Generic ( IMAGE_WIDTH : integer := 256; 68 | IMAGE_HEIGHT : integer := 256; 69 | ADDR_WIDTH : integer := 16 70 | ); 71 | Port ( clk : in std_logic; 72 | reset : in std_logic; 73 | 74 | ramInAddr : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 75 | ramInEn : out STD_LOGIC := '0'; 76 | ramInData : in STD_LOGIC_VECTOR(7 downto 0); 77 | 78 | ramOutDataIn : out STD_LOGIC_VECTOR(7 downto 0); 79 | ramOutDataOut : in STD_LOGIC_VECTOR(7 downto 0); 80 | ramOutWe : out STD_LOGIC; 81 | ramOutAddr: out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 82 | 83 | isFinishedCompressing : out STD_LOGIC; 84 | compressedDataSize : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) 85 | ); 86 | end component; 87 | 88 | component transmitraw is 89 | Generic ( IMAGE_WIDTH : integer := 256; 90 | IMAGE_HEIGHT : integer := 256; 91 | ADDR_WIDTH : integer := 16 92 | ); 93 | Port ( clk : in STD_LOGIC; 94 | en : in STD_LOGIC; 95 | reset : in STD_LOGIC; 96 | request : in STD_LOGIC; 97 | dataIn : in STD_LOGIC_VECTOR (7 downto 0); 98 | 99 | ready : out STD_LOGIC; 100 | done : out STD_LOGIC; 101 | address : out STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0); 102 | stopAddress : in STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 103 | dataOut : out STD_LOGIC_VECTOR (7 downto 0)); 104 | end component; 105 | 106 | signal ramInAddr : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 107 | signal originalData : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 108 | signal enRamIn : STD_LOGIC := '0'; 109 | 110 | signal ramOutDataIn : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 111 | signal ramOutDataOut : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 112 | signal weRamOut : STD_LOGIC := '0'; 113 | 114 | signal transmitAddr : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 115 | signal addrOutMemCtrl : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 116 | signal ramOutAddr : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 117 | 118 | signal isFinishedCompressing : STD_LOGIC := '0'; 119 | signal sigCompressedDataSize : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) := (others => '0'); 120 | 121 | begin 122 | wicc: component waveleticc generic map ( IMAGE_WIDTH => IMAGE_WIDTH, 123 | IMAGE_HEIGHT => IMAGE_HEIGHT, 124 | ADDR_WIDTH => ADDR_WIDTH) 125 | port map ( clk => clk, 126 | reset => reset, 127 | ramInAddr => ramInAddr, 128 | ramInEn => enRamIn, 129 | ramInData => originalData, 130 | 131 | ramOutDataIn => ramOutDataIn, 132 | ramOutDataOut => ramOutDataOut, 133 | ramOutWe => weRamOut, 134 | ramOutAddr => addrOutMemCtrl, 135 | 136 | isFinishedCompressing => isFinishedCompressing, 137 | compressedDataSize => sigCompressedDataSize 138 | ); 139 | 140 | ramIn: component ramfile generic map (RAM_SIZE => (IMAGE_WIDTH*IMAGE_HEIGHT)) 141 | port map ( clk => clk, 142 | we => '0', 143 | en => enRamIn, 144 | addr => ramInAddr, 145 | dataIn => x"00", 146 | dataOut => originalData); 147 | 148 | ramOut: component ramnormal generic map ( RAM_SIZE => 65536, 149 | ADDR_WIDTH => 16) 150 | port map ( clk => clk, 151 | we => weRamOut, 152 | en => '1', 153 | addr => ramOutAddr, 154 | dataIn => ramOutDataIn, 155 | dataOut => ramOutDataOut); 156 | 157 | transmitter: component transmitraw generic map ( IMAGE_WIDTH => IMAGE_WIDTH, 158 | IMAGE_HEIGHT => IMAGE_HEIGHT, 159 | ADDR_WIDTH => ADDR_WIDTH) 160 | port map ( clk => clk, 161 | en => isFinishedCompressing, 162 | reset => reset, 163 | request => requestNewData, 164 | dataIn => ramOutDataOut, 165 | ready => outDataReady, 166 | done => isFinishedTransmitting, 167 | address => transmitAddr, 168 | stopAddress => sigCompressedDataSize, 169 | dataOut => outData); 170 | 171 | ramOutAddr <= (addrOutMemCtrl) when (isFinishedCompressing = '0') else transmitAddr; 172 | isFinishedProcessing <= isFinishedCompressing; 173 | 174 | end Behavioral; 175 | -------------------------------------------------------------------------------- /vhdl_only/transmitraw.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 16:43:56 07/31/2014 6 | -- Design Name: 7 | -- Module Name: transmitraw - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: An extra utility component used for transmitting the values of the output RAM. This 12 | -- component is used for evaluation purposes in the testbench, but is also synthesizable and can be 13 | -- used to stream the data when the compression process is over. 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | ---------------------------------------------------------------------------------- 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | use IEEE.NUMERIC_STD.ALL; 26 | 27 | entity transmitraw is 28 | Generic ( IMAGE_WIDTH : integer := 256; 29 | IMAGE_HEIGHT : integer := 256; 30 | ADDR_WIDTH : integer := 16 31 | ); 32 | Port ( clk : in STD_LOGIC; 33 | en : in STD_LOGIC; 34 | reset : in STD_LOGIC; 35 | request : in STD_LOGIC; 36 | dataIn : in STD_LOGIC_VECTOR (7 downto 0); 37 | 38 | ready : out STD_LOGIC; 39 | done : out STD_LOGIC; 40 | address : out STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0); 41 | stopAddress : in STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 42 | dataOut : out STD_LOGIC_VECTOR (7 downto 0)); 43 | end transmitraw; 44 | 45 | architecture Behavioral of transmitraw is 46 | type states is ( stateReset, stateWaitForRequest, stateStream, stateStream2, 47 | stateWaitForRequestNext, stateWaitForRequestNext2, 48 | stateFinished, stateFinished2); 49 | signal currentState : states := stateReset; 50 | signal nextState : states := stateReset; 51 | 52 | signal sigDataOut : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); 53 | signal sigAddress : STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0) := (others => '0'); 54 | signal sigReady : STD_LOGIC := '0'; 55 | signal sigDone : STD_LOGIC := '0'; 56 | 57 | constant totalNumPixels : integer := IMAGE_WIDTH * IMAGE_HEIGHT; 58 | 59 | signal numSentPixels : integer := 0; 60 | 61 | begin 62 | -- Synchronous process of the state machine. 63 | process (clk, reset, nextState) 64 | begin 65 | if reset = '1' then 66 | currentState <= stateReset; 67 | elsif rising_edge(clk) then 68 | if en = '1' then 69 | -- Perform all synchronous signal changes. These are changes that 70 | -- cannot be performed in the combinational process because they 71 | -- would infer the usage of implicit latches. Example of such a signal 72 | -- is sigAddress which counts the current address of the pixel to be 73 | -- transmitted. 74 | if (currentState = stateReset) then -- Reset all the counters to zero. 75 | sigAddress <= (others => '0'); 76 | sigDataOut <= (others => '0'); 77 | numSentPixels <= 0; 78 | elsif (currentState = stateWaitForRequestNext2) then -- Increase the address for the data to be sent. 79 | sigAddress <= sigAddress + 1; 80 | elsif (currentState = stateStream2) then -- Set the data to be output to the output data bus, 81 | -- and count the number of sent pixels. 82 | sigDataOut <= dataIn; 83 | numSentPixels <= numSentPixels + 1; 84 | end if; 85 | 86 | currentState <= nextState; 87 | end if; 88 | end if; 89 | end process; 90 | 91 | -- Combinational process of the state machine. 92 | process (currentState, request, numSentPixels, sigAddress, stopAddress) 93 | begin 94 | -- Set the default values for the signals in order to avoid generating latches. 95 | nextState <= stateReset; 96 | sigReady <= '0'; 97 | sigDone <= '0'; 98 | 99 | case currentState is 100 | when stateReset => -- Reset the state machine. 101 | nextState <= stateWaitForRequest; 102 | 103 | when stateWaitForRequest => -- Wait until the first data byte is requested. 104 | if request = '1' then 105 | nextState <= stateStream; 106 | else 107 | nextState <= stateWaitForRequest; 108 | end if; 109 | 110 | when stateStream => -- Start the streaming of the new data byte. 111 | nextState <= stateStream2; 112 | when stateStream2 => 113 | nextState <= stateWaitForRequestNext; -- After the data has been set to the output bus, jump to the waiting state again. 114 | 115 | when stateWaitForRequestNext => -- Waiting state almost the same as stateWaitForRequest, but this state 116 | -- also sets the sigReady signal to notify the outside devices that the data 117 | -- byte is ready, and also increases the count of currently sent data bytes. 118 | sigReady <= '1'; 119 | 120 | if numSentPixels = totalNumPixels or sigAddress = (stopAddress - 1) then 121 | nextState <= stateFinished; 122 | elsif request = '1' then 123 | nextState <= stateWaitForRequestNext2; 124 | else 125 | nextState <= stateWaitForRequestNext; 126 | end if; 127 | when stateWaitForRequestNext2 => -- When a new data byte has been requested, this state is jumped to. 128 | nextState <= stateStream; 129 | 130 | -- Since the results are obtained on the rising edge of the sigReady signal, 131 | -- we must first clear the last obtained byte of data. We do this by 132 | -- resetting and then setting the sigReady signal to give away one 133 | -- last rising edge. 134 | when stateFinished => -- When all data bytes have been sent, loop in the finished state. 135 | sigReady <= '1'; 136 | sigDone <= '1'; 137 | nextState <= stateFinished2; 138 | when stateFinished2 => -- When all data bytes have been sent, loop in the finished state. 139 | sigDone <= '1'; 140 | nextState <= stateFinished2; 141 | end case; 142 | end process; 143 | 144 | -- Set the output signals to their current values. 145 | done <= sigDone; 146 | ready <= sigReady; 147 | address <= sigAddress; 148 | dataOut <= sigDataOut; 149 | 150 | end Behavioral; 151 | -------------------------------------------------------------------------------- /vhdl_only/waveleticc.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: Ruder Boskovic Institute 3 | -- Engineer: Ivan Sovic 4 | -- 5 | -- Create Date: 15:19:12 08/19/2014 6 | -- Design Name: 7 | -- Module Name: waveleticc - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: Wavelet Image Compression Component. 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | 23 | entity waveleticc is 24 | Generic ( IMAGE_WIDTH : integer := 256; 25 | IMAGE_HEIGHT : integer := 256; 26 | ADDR_WIDTH : integer := 16 27 | ); 28 | Port ( clk : in std_logic; 29 | reset : in std_logic; 30 | 31 | ramInAddr : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 32 | ramInEn : out STD_LOGIC := '0'; 33 | ramInData : in STD_LOGIC_VECTOR(7 downto 0); 34 | 35 | ramOutDataIn : out STD_LOGIC_VECTOR(7 downto 0); 36 | ramOutDataOut : in STD_LOGIC_VECTOR(7 downto 0); 37 | ramOutWe : out STD_LOGIC; 38 | ramOutAddr: out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 39 | 40 | isFinishedCompressing : out STD_LOGIC; 41 | compressedDataSize : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0) 42 | ); 43 | end waveleticc; 44 | 45 | architecture Behavioral of waveleticc is 46 | 47 | component controlunit is 48 | Generic ( IMAGE_WIDTH : integer := 256; 49 | IMAGE_HEIGHT : integer := 256; 50 | ADDR_WIDTH : integer := 16 51 | ); 52 | Port ( clk : in STD_LOGIC; 53 | reset : in STD_LOGIC; 54 | addrIn : out STD_LOGIC_VECTOR ((ADDR_WIDTH - 1) downto 0); 55 | enRamIn: out STD_LOGIC; 56 | resetFifoRow : out STD_LOGIC; 57 | weFifoRow : out STD_LOGIC; 58 | resetFifoColumn : out STD_LOGIC; 59 | weFifoColumn : out STD_LOGIC; 60 | isFinishedProcessing : out STD_LOGIC; 61 | rowReady : out STD_LOGIC; 62 | columnReady : out STD_LOGIC; 63 | readyForNextData : in STD_LOGIC 64 | ); 65 | end component; 66 | 67 | component haarlp is 68 | Port ( x0 : in std_logic_vector(7 downto 0); 69 | x1 : in std_logic_vector(7 downto 0); 70 | y : out std_logic_vector(7 downto 0)); 71 | end component; 72 | 73 | component haarhp is 74 | Port ( x0 : in std_logic_vector(7 downto 0); 75 | x1 : in std_logic_vector(7 downto 0); 76 | y : out std_logic_vector(7 downto 0)); 77 | end component; 78 | 79 | component fifomem is 80 | generic ( 81 | DATA_WIDTH: natural := 8; -- Width of a single data register (i.e. a byte). 82 | FIFO_DEPTH: natural := 2 -- Number of data registers in the FIFO memory (i.e. the width of the image + 1). 83 | ); 84 | port ( 85 | clk: in std_logic; 86 | reset: in std_logic; 87 | we: in std_logic; 88 | dataIn: in std_logic_vector((DATA_WIDTH - 1) downto 0); 89 | dataOutFirst: out std_logic_vector((DATA_WIDTH - 1) downto 0); 90 | dataOutLast: out std_logic_vector((DATA_WIDTH - 1) downto 0) 91 | ); 92 | end component; 93 | 94 | component memcontroler is 95 | Generic ( THRESHOLD : integer := 10; 96 | DATA_WIDTH : integer := 8; 97 | ADDR_WIDTH : integer := 16; 98 | IMAGE_WIDTH : integer := 256; 99 | IMAGE_HEIGHT : integer := 256 100 | ); 101 | Port ( 102 | clk : in STD_LOGIC; 103 | en : in STD_LOGIC; 104 | reset : in STD_LOGIC; 105 | 106 | inLL : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 107 | inLH : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 108 | inHL : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 109 | inHH : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 110 | 111 | rowReady : in STD_LOGIC; 112 | columnReady : in STD_LOGIC; 113 | 114 | address : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 115 | dataOut : out STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 116 | dataIn : in STD_LOGIC_VECTOR((DATA_WIDTH - 1) downto 0); 117 | weOut : out STD_LOGIC; 118 | 119 | compressedDataSize : out STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 120 | 121 | cuFinishedProcessing : in STD_LOGIC; 122 | finishedCompressing : out STD_LOGIC; 123 | 124 | readyForNextData : out STD_LOGIC 125 | ); 126 | end component; 127 | 128 | signal resetFifoRow : STD_LOGIC := '0'; 129 | signal weFifoRow : STD_LOGIC := '0'; 130 | signal resetFifoColumn : STD_LOGIC := '0'; 131 | signal weFifoColumn : STD_LOGIC := '0'; 132 | 133 | signal x0 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 134 | signal x1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 135 | signal xL0 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 136 | signal xL1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 137 | signal xH0 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 138 | signal xH1 : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 139 | signal y0L : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 140 | signal y0H : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 141 | signal yLL : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 142 | signal yLH : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 143 | signal yHL : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 144 | signal yHH : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 145 | 146 | signal cuIsFinishedProcessing : STD_LOGIC := '0'; 147 | signal sigCompressedDataSize : STD_LOGIC_VECTOR((ADDR_WIDTH - 1) downto 0); 148 | signal sigIsFinishedCompressing : STD_LOGIC := '0'; 149 | signal rowReady, columnReady, readyForNextData : STD_LOGIC := '0'; 150 | 151 | begin 152 | cu: component controlunit generic map ( IMAGE_WIDTH => IMAGE_WIDTH, 153 | IMAGE_HEIGHT => IMAGE_HEIGHT, 154 | ADDR_WIDTH => ADDR_WIDTH) 155 | port map ( clk => clk, 156 | reset => reset, 157 | addrIn => ramInAddr, 158 | enRamIn => ramInEn, 159 | resetFifoRow => resetFifoRow, 160 | weFifoRow => weFifoRow, 161 | resetFifoColumn => resetFifoColumn, 162 | weFifoColumn => weFifoColumn, 163 | isFinishedProcessing => cuIsFinishedProcessing, 164 | rowReady => rowReady, 165 | columnReady => columnReady, 166 | readyForNextData => readyForNextData); 167 | 168 | fifoRow: component fifomem generic map ( DATA_WIDTH => 8, 169 | FIFO_DEPTH => 2) 170 | port map ( clk => clk, 171 | reset => resetFifoRow, 172 | we => weFifoRow, 173 | dataIn => ramInData, 174 | dataOutFirst => x0, 175 | dataOutLast => x1); 176 | 177 | fifoColumnW: component fifomem generic map ( DATA_WIDTH => 8, 178 | FIFO_DEPTH => (IMAGE_WIDTH + 1)) 179 | port map ( clk => clk, 180 | reset => resetFifoColumn, 181 | we => weFifoColumn, 182 | dataIn => y0L, 183 | dataOutFirst => xL0, 184 | dataOutLast => xL1); 185 | 186 | fifoColumnH: component fifomem generic map ( DATA_WIDTH => 8, 187 | FIFO_DEPTH => (IMAGE_WIDTH + 1)) 188 | port map ( clk => clk, 189 | reset => resetFifoColumn, 190 | we => weFifoColumn, 191 | dataIn => y0H, 192 | dataOutFirst => xH0, 193 | dataOutLast => xH1); 194 | 195 | W0L: component haarlp port map ( x0 => x0, 196 | x1 => x1, 197 | y => y0L); 198 | 199 | WLL: component haarlp port map ( x0 => xL0, 200 | x1 => xL1, 201 | y => yLL); 202 | 203 | WLH: component haarhp port map ( x0 => xL0, 204 | x1 => xL1, 205 | y => yLH); 206 | 207 | 208 | W0H: component haarhp port map ( x0 => x0, 209 | x1 => x1, 210 | y => y0H); 211 | 212 | WHL: component haarlp port map ( x0 => xH0, 213 | x1 => xH1, 214 | y => yHL); 215 | 216 | WHH: component haarhp port map ( x0 => xH0, 217 | x1 => xH1, 218 | y => yHH); 219 | 220 | compressor: component memcontroler generic map ( THRESHOLD => 10, 221 | DATA_WIDTH => 8, 222 | ADDR_WIDTH => 16, 223 | IMAGE_WIDTH => 256, 224 | IMAGE_HEIGHT => 256) 225 | port map ( clk => clk, 226 | en => '1', 227 | reset => reset, 228 | inLL => yLL, 229 | inLH => yLH, 230 | inHL => yHL, 231 | inHH => yHH, 232 | rowReady => rowReady, 233 | columnReady => columnReady, 234 | address => ramOutAddr, 235 | dataOut => ramOutDataIn, 236 | dataIn => ramOutDataOut, 237 | weOut => ramOutWe, 238 | compressedDataSize => sigCompressedDataSize, 239 | cuFinishedProcessing => cuIsFinishedProcessing, 240 | finishedCompressing => sigIsFinishedCompressing, 241 | readyForNextData => readyForNextData); 242 | 243 | 244 | isFinishedCompressing <= sigIsFinishedCompressing; 245 | compressedDataSize <= sigCompressedDataSize when (sigIsFinishedCompressing = '1') else (others => '0'); 246 | 247 | end Behavioral; 248 | --------------------------------------------------------------------------------