├── LICENSE.md ├── README.md ├── example-1-override-step ├── .gitignore ├── README.md ├── build.sbt ├── project │ ├── build.properties │ └── plugins.sbt ├── scalastyle-config.xml ├── scalastyle-test-config.xml └── src │ ├── main │ └── scala │ │ └── overrideStepExample │ │ ├── ExamplePipeline.scala │ │ └── ExamplePipelineMain.scala │ └── test │ └── scala │ └── overrideStepExample │ ├── OverrideStepExampleTest.scala │ └── OverrideStepExampleTester.scala ├── example-10-lamports-bakery-algorithm ├── .gitignore ├── .scalafmt.conf ├── build.sbt ├── ip_cores │ └── lamports_bakery_algo │ │ ├── component.xml │ │ └── xgui │ │ ├── LamportsBakeryAlgo_v1_1.tcl │ │ ├── LamportsBakeryAlgo_v1_2.tcl │ │ ├── LamportsBakeryAlgo_v1_3.tcl │ │ ├── LamportsBakeryAlgo_v1_4.tcl │ │ ├── LamportsBakeryAlgo_v2_0.tcl │ │ ├── LamportsBakeryAlgo_v2_1.tcl │ │ └── LamportsBakeryAlgorithm_v1_0.tcl ├── project │ ├── build.properties │ └── plugins.sbt ├── src │ ├── main │ │ └── scala │ │ │ └── lamports_bakery_algorithm │ │ │ ├── Axi4Manager.scala │ │ │ ├── Axi4ManagerRdCmd.scala │ │ │ ├── Axi4ManagerWrCmd.scala │ │ │ ├── DelayGenLfsr.scala │ │ │ ├── LamportsBakeryAlgorithm.scala │ │ │ ├── LamportsBakeryAlgorithmIncr.scala │ │ │ ├── LamportsBakeryAlgorithmLock.scala │ │ │ ├── LamportsBakeryAlgorithmMain.scala │ │ │ └── LamportsBakeryAlgorithmSequencer.scala │ └── test │ │ └── scala │ │ └── lamports_bakery_algorithm │ │ ├── Axi4LiteManagerTest.scala │ │ ├── Axi4LiteMemSubordinate.scala │ │ ├── Axi4ManagerReg.scala │ │ ├── DelayGenLfsrTest.scala │ │ ├── LamportsBakeryAlgorithmReg.scala │ │ ├── LamportsBakeryAlgorithmTest.scala │ │ └── LamportsBakeryAlgorithmTester.scala ├── test_vivado │ ├── scripts │ │ └── bd.tcl │ └── test │ │ └── tb.sv └── ultra96v2_prj │ ├── project │ └── .gitkeep │ └── scripts │ ├── _bd.tcl │ ├── _compile.tcl │ ├── _export.tcl │ ├── _prj.tcl │ ├── _wrapper.tcl │ └── run_all.tcl ├── example-11-poor-mans-system-ila ├── .gitignore ├── build.sbt ├── ip_cores │ └── poor_mans_system_ila │ │ ├── component.xml │ │ ├── driver │ │ ├── ila_capture.py │ │ └── ila_plot.py │ │ ├── hdl │ │ ├── .gitignore │ │ ├── DualPortRam.v │ │ └── PoorMansSystemILA.sv │ │ ├── xdc │ │ └── poor_mans_system_ila_ooc.xdc │ │ └── xgui │ │ ├── PoorMansSystemILA_v1_0.tcl │ │ ├── PoorMansSystemILA_v1_1.tcl │ │ ├── PoorMansSystemILA_v1_2.tcl │ │ └── PoorMansSystemILA_v1_3.tcl ├── project │ ├── build.properties │ └── plugins.sbt └── src │ ├── main │ ├── resources │ │ └── DualPortRam.v │ └── scala │ │ └── poor_mans_system_ila │ │ ├── DualPortRam.scala │ │ ├── MbdebugBundle.scala │ │ ├── PoorMansSystemILA.scala │ │ ├── PoorMansSystemILAKernel.scala │ │ └── PoorMansSystemILAMain.scala │ └── test │ └── scala │ └── poor_mans_system_ila │ ├── MbdebugGenerator.scala │ ├── PoorMansSystemILATest.scala │ └── PoorMansSystemILATester.scala ├── example-12-axi-proxy ├── .gitignore ├── .scalafmt.conf ├── build.sbt ├── ip_cores │ └── axi_proxy │ │ ├── component.xml │ │ ├── drivers │ │ ├── AxiProxy_regs.hpp │ │ └── _AxiProxyMap.py │ │ └── xgui │ │ ├── AxiProxy_v0_1.tcl │ │ └── AxiProxy_v0_2.tcl ├── project │ ├── build.properties │ └── plugins.sbt ├── src │ ├── main │ │ └── scala │ │ │ └── axi_proxy │ │ │ ├── Axi4Manager.scala │ │ │ ├── Axi4ManagerRdCmd.scala │ │ │ ├── Axi4ManagerWrCmd.scala │ │ │ ├── AxiProxy.scala │ │ │ └── AxiProxyMain.scala │ └── test │ │ └── scala │ │ └── axi_proxy │ │ ├── AxiProxyReg.scala │ │ ├── AxiProxyTest.scala │ │ └── AxiProxyTester.scala └── ultra96v2_prj │ ├── ip_cores │ └── axi4-activity-led │ │ ├── component.xml │ │ ├── hdl │ │ └── axi4_activity_led.sv │ │ └── xgui │ │ └── axi4_activity_led_v1_0.tcl │ ├── project │ └── .gitkeep │ ├── scripts │ ├── _bd.tcl │ ├── _compile.tcl │ ├── _export.tcl │ ├── _prj.tcl │ ├── _wrapper.tcl │ └── run_all.tcl │ └── xdc │ └── pin_assignments.xdc ├── example-13-axi-traffic-gen ├── .gitignore ├── .scalafmt.conf ├── build.sbt ├── ip_cores │ └── axi_traffic_gen │ │ ├── component.xml │ │ └── xgui │ │ ├── AxiTrafficGen_v0_1.tcl │ │ └── AxiTrafficGen_v0_9.tcl ├── project │ ├── build.properties │ └── plugins.sbt ├── src │ └── main │ │ └── scala │ │ └── axi_traffic_gen │ │ ├── Axi4Manager.scala │ │ ├── Axi4ManagerRd.scala │ │ ├── Axi4ManagerRdCmd.scala │ │ ├── Axi4ManagerWr.scala │ │ ├── Axi4ManagerWrCmd.scala │ │ ├── AxiTGConfig.scala │ │ ├── AxiTrafficGen.scala │ │ ├── AxiTrafficGenMain.scala │ │ └── UpDownCounter.scala ├── test │ ├── scripts │ │ └── bd.tcl │ └── src │ │ └── sim_top.sv └── ultra96v2_prj │ ├── project │ └── .gitkeep │ ├── scripts │ ├── _bd.tcl │ ├── _compile.tcl │ ├── _export.tcl │ ├── _prj.tcl │ ├── _wrapper.tcl │ └── run_all.tcl │ └── xdc │ └── pin_assignments.xdc ├── example-14-pcie-endpoint ├── .gitignore ├── .scalafmt.conf ├── README.md ├── build.sbt ├── docs │ ├── example_usage.png │ ├── pcie_endpoint.drawio │ └── pcie_endpoint.drawio.png ├── ip_cores │ └── pcie_endpoint │ │ └── pp_sp_pcie_endpoint_hw.tcl ├── project │ ├── build.properties │ └── plugins.sbt ├── src │ ├── main │ │ └── scala │ │ │ └── pcie_endpoint │ │ │ ├── AvalonAgent.scala │ │ │ ├── BusMaster.scala │ │ │ ├── BusMasterEngine.scala │ │ │ ├── BusMasterRegs.scala │ │ │ ├── CompletionGen.scala │ │ │ ├── CompletionRecv.scala │ │ │ ├── Configuration.scala │ │ │ ├── Interfaces.scala │ │ │ ├── InterruptCtrl.scala │ │ │ ├── Main.scala │ │ │ ├── MemoryReadWriteCompl.scala │ │ │ ├── PcieEndpoint.scala │ │ │ ├── ReadyCorrection.scala │ │ │ ├── SkidBuffer.scala │ │ │ ├── TxArbiter.scala │ │ │ └── package.scala │ └── test │ │ └── scala │ │ └── pcie_endpoint │ │ ├── AvalonStreamDataInBfm.scala │ │ ├── AvalonStreamDataOutBfm.scala │ │ ├── AvalonStreamRxBfm.scala │ │ ├── AvalonStreamTxBfm.scala │ │ ├── BusMasterTest.scala │ │ ├── PcieEndpoint64TestBMLongRead.scala │ │ ├── PcieEndpoint64bInterfaceSimpleTest.scala │ │ ├── PcieEndpoint64bInterfaceTestBM.scala │ │ ├── PcieEndpointComplTest.scala │ │ ├── PcieEndpointSimple64Test.scala │ │ ├── PcieEndpointSimpleTest.scala │ │ ├── PcieEndpointTest.scala │ │ ├── PcieEndpointTestBM.scala │ │ ├── PcieEndpointTestBMLongRead.scala │ │ ├── PciePackets.scala │ │ ├── TLConfigBFM.scala │ │ └── TestMain.scala └── test_sv │ ├── scripts │ ├── sim_cpld.do │ ├── sim_cpld2.do │ └── sim_wr_dma.do │ ├── tb │ ├── PciePackets.sv │ ├── cpld_stim.h │ ├── pp_sp_pcie_endpoint_tb_cpld.sv │ ├── pp_sp_pcie_endpoint_tb_cpld2.sv │ ├── pp_sp_pcie_endpoint_tb_wr_dma.sv │ └── pp_sp_pcie_endpoint_th.sv │ └── work │ ├── .gitignore │ └── .gitkeep ├── example-2-axi-lite-if ├── .gitignore ├── README.md ├── build.sbt ├── project │ ├── build.properties │ └── plugins.sbt ├── scalastyle-config.xml ├── scalastyle-test-config.xml └── src │ ├── main │ └── scala │ │ └── axiLiteExample │ │ ├── AxiLite.scala │ │ ├── PipelineWithAxiLite.scala │ │ ├── PipelineWithAxiLiteMain.scala │ │ └── PipelineWithAxiLiteSlave.scala │ └── test │ └── scala │ └── axiLiteExample │ ├── AxiLiteBfm.scala │ ├── AxiLiteMasterBfm.scala │ ├── ChiselBfm.scala │ ├── PipelineWithAxiLiteTest.scala │ ├── PipelineWithAxiLiteTester.scala │ ├── ValidIfBfm.scala │ ├── ValidIfDriver.scala │ └── ValidIfMonitor.scala ├── example-3-vivado-ip ├── .gitignore ├── README.md ├── build.sbt ├── ip_cores │ └── pipeline_with_axi │ │ ├── component.xml │ │ ├── hdl │ │ └── PipelineWithAxiLite.v │ │ ├── misc │ │ └── chisel_logo.png │ │ ├── xdc │ │ └── pipeline_with_axi_ooc.xdc │ │ └── xgui │ │ └── PipelineWithAxiLite_v1_0.tcl ├── project │ ├── build.properties │ └── plugins.sbt ├── scalastyle-config.xml ├── scalastyle-test-config.xml ├── src │ ├── main │ │ └── scala │ │ │ └── axiLiteExample │ │ │ ├── AxiLite.scala │ │ │ ├── PipelineWithAxiLite.scala │ │ │ ├── PipelineWithAxiLiteMain.scala │ │ │ └── PipelineWithAxiLiteSlave.scala │ └── test │ │ └── scala │ │ └── axiLiteExample │ │ ├── AxiLiteBfm.scala │ │ ├── AxiLiteMasterBfm.scala │ │ ├── ChiselBfm.scala │ │ ├── PipelineWithAxiLiteTest.scala │ │ ├── PipelineWithAxiLiteTester.scala │ │ ├── ValidIfBfm.scala │ │ ├── ValidIfDriver.scala │ │ └── ValidIfMonitor.scala ├── uvvm │ ├── hdl │ │ ├── pipelinewithaxilite_tb.vhd │ │ └── pipelinewithaxilite_th.vhd │ └── sim │ │ ├── .gitignore │ │ ├── compile.do │ │ └── sim.do └── vivado_tb_project │ ├── README.md │ ├── project │ └── PLACEHOLDER.txt │ ├── scripts │ ├── _gen_bd.tcl │ ├── _project.tcl │ └── main.tcl │ └── sim │ ├── pipelinewithaxilite_tb.sv │ └── pipelinewithaxilite_tb_behav.wcfg ├── example-4-ord-decoupled-io-tester ├── README.md ├── build.sbt ├── scalastyle-config.xml ├── scalastyle-test-config.xml ├── src │ ├── main │ │ └── scala │ │ │ └── ord_decoup_io │ │ │ └── OrdDecoupIo.scala │ └── test │ │ └── scala │ │ └── ord_decoup_io │ │ ├── OrdDecoupIoTest.scala │ │ └── OrdDecoupIoTester.scala └── tester_waveform.png ├── example-5-gunzip ├── build.sbt ├── ip_cores │ ├── byte2bit │ │ ├── component.xml │ │ ├── hdl │ │ │ └── ByteStreamToBitStream.v │ │ └── xgui │ │ │ ├── ByteStreamToBitStream_v1_0.tcl │ │ │ └── byte2bit_v1_0.tcl │ └── gunzip │ │ ├── component.xml │ │ ├── hdl │ │ └── GunzipEngine.v │ │ ├── xdc │ │ └── gunzip_ooc.xdc │ │ └── xgui │ │ ├── GunzipEngine_v1_0.tcl │ │ └── gunzip_v1_0.tcl ├── scalastyle-config.xml ├── scalastyle-test-config.xml ├── src │ ├── main │ │ ├── resources │ │ │ ├── in.tar.gz │ │ │ └── out.tar │ │ └── scala │ │ │ └── gunzip │ │ │ ├── BitStream.scala │ │ │ ├── ByteStreamToBitStream.scala │ │ │ ├── GunzipBitSkipper.scala │ │ │ ├── GunzipEngine.scala │ │ │ ├── GunzipHeaderParser.scala │ │ │ ├── GunzipHuffDecoder.scala │ │ │ ├── GunzipHuffDecoderElem.scala │ │ │ ├── GunzipLenDistLut.scala │ │ │ ├── GunzipMain.scala │ │ │ ├── GunzipOutBuf.scala │ │ │ ├── GunzipOutput.scala │ │ │ ├── HuffmanCode.scala │ │ │ └── HuffmanTree.scala │ └── test │ │ └── scala │ │ └── gunzip │ │ ├── ChiselBfm.scala │ │ ├── DecoupledBfm.scala │ │ ├── DecoupledDriver.scala │ │ ├── DecoupledMonitor.scala │ │ ├── GunzipEngineTest.scala │ │ ├── GunzipTester.scala │ │ └── Hexdump.scala └── vivado_tb_project │ ├── scripts │ ├── _add_files.tcl │ ├── _create_prj.tcl │ ├── _create_wrapper.tcl │ ├── _gen_bd.tcl │ ├── _run_sim.tcl │ └── main.tcl │ └── sim │ ├── gunzip_system_tb.sv │ └── resources │ ├── in.tar.gz │ └── out.tar ├── example-7-fft ├── .gitignore ├── .scalafmt.conf ├── build.sbt ├── project │ ├── build.properties │ └── plugins.sbt └── src │ ├── main │ └── scala │ │ └── fft │ │ ├── ComplexBundle.scala │ │ ├── FftButterfly.scala │ │ ├── FftModule.scala │ │ └── InputShuffle.scala │ └── test │ └── scala │ └── fft │ ├── ButterflyDriver.scala │ ├── ButterflyMonitor.scala │ ├── FftButterflyTester.scala │ ├── FftModuleTest.scala │ ├── FftModuleTester.scala │ ├── InputShuffleTester.scala │ └── package.scala ├── example-8-presence-bits-compression ├── .gitignore ├── .scalafmt.conf ├── build.sbt ├── project │ ├── build.properties │ └── plugins.sbt └── src │ ├── main │ └── scala │ │ └── presence_bits_comp │ │ ├── AxiMasterCore.scala │ │ ├── AxiMasterCoreReadIface.scala │ │ ├── AxiMasterCoreReader.scala │ │ ├── AxiMasterCoreRespCounter.scala │ │ ├── AxiMasterCoreWriteIface.scala │ │ ├── AxiMasterCoreWriter.scala │ │ ├── DecompressorAxiSlave.scala │ │ ├── DecompressorInputAdapter.scala │ │ ├── DecompressorKernel.scala │ │ ├── DecompressorKernelInputInterface.scala │ │ ├── DecompressorKernelOutputInterface.scala │ │ ├── DecompressorOutputAdapter.scala │ │ ├── PresenceBitsCompMain.scala │ │ └── PresenceBitsDecompressor.scala │ ├── project │ └── build.properties │ └── test │ ├── resources │ ├── dense_matrix_with_sparse_els.npy │ └── gen_stim.py │ └── scala │ └── presence_bits_comp │ ├── AxiMasterCoreTest.scala │ ├── AxiMasterCoreUserDriver.scala │ ├── AxiMasterCoreUserMonitor.scala │ ├── CompressorDecompressor.scala │ ├── DecompressorAxiSlaveTest.scala │ ├── DecompressorInputAdapterDriver.scala │ ├── DecompressorInputAdapterMonitor.scala │ ├── DecompressorInputAdapterTest.scala │ ├── DecompressorKernelDriver.scala │ ├── DecompressorKernelMonitor.scala │ ├── DecompressorKernelTest.scala │ ├── DecompressorOutputAdapterDriver.scala │ ├── DecompressorOutputAdapterMonitor.scala │ ├── DecompressorOutputAdapterTest.scala │ ├── PresenceBitsCompTester.scala │ └── PresenceBitsDecompressorTest.scala ├── example-9-mem-checker ├── .gitignore ├── .scalafmt.conf ├── build.sbt ├── ip_cores │ └── mem_checker │ │ ├── hdl │ │ └── MemChecker.sv │ │ ├── inc │ │ ├── mem_checker.h │ │ └── mem_checker_regs.h │ │ ├── mem_checker_hw.tcl │ │ ├── mem_checker_sw.tcl │ │ └── src │ │ └── mem_checker.c ├── project │ ├── build.properties │ └── plugins.sbt └── src │ ├── main │ └── scala │ │ └── mem_checker │ │ ├── AvalonMMReader.scala │ │ ├── AvalonMMWriter.scala │ │ ├── DataChecker.scala │ │ ├── DataDriver.scala │ │ ├── MemChecker.scala │ │ ├── MemCheckerAxiSlave.scala │ │ ├── MemCheckerMain.scala │ │ └── PatternGen.scala │ └── test │ └── scala │ └── mem_checker │ ├── MemCheckerAxiSlaveTest.scala │ ├── MemCheckerTest.scala │ └── MemCheckerTester.scala └── utils-chisel-to-vhdl ├── .gitignore ├── build.sbt ├── project └── build.properties └── src ├── main └── scala │ └── chisel_to_vhdl │ ├── ChiselToVhdlMain.scala │ ├── ChiselTokenizer.scala │ ├── ChiselTokens.scala │ ├── Translator.scala │ ├── VhdlTokenizer.scala │ └── VhdlTokens.scala └── test └── scala └── chisel_to_vhdl ├── ChiselTokenizerTest.scala ├── TranslatorTest.scala └── VhdlTokenizerTest.scala /LICENSE.md: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 Jan Marjanovic 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Various examples for Chisel HDL 2 | 3 | Presented in this repository are various examples for 4 | [Chisel](https://chisel.eecs.berkeley.edu/), a modern Hardware Description 5 | Language based on Scala. 6 | -------------------------------------------------------------------------------- /example-1-override-step/README.md: -------------------------------------------------------------------------------- 1 | # Example 1: overloading step() 2 | 3 | -------------------------------------------------------------------------------- /example-1-override-step/build.sbt: -------------------------------------------------------------------------------- 1 | def scalacOptionsVersion(scalaVersion: String): Seq[String] = { 2 | Seq() ++ { 3 | // If we're building with Scala > 2.11, enable the compile option 4 | // switch to support our anonymous Bundle definitions: 5 | // https://github.com/scala/bug/issues/10047 6 | CrossVersion.partialVersion(scalaVersion) match { 7 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq() 8 | case _ => Seq("-Xsource:2.11") 9 | } 10 | } 11 | } 12 | 13 | def javacOptionsVersion(scalaVersion: String): Seq[String] = { 14 | Seq() ++ { 15 | // Scala 2.12 requires Java 8. We continue to generate 16 | // Java 7 compatible code for Scala 2.11 17 | // for compatibility with old clients. 18 | CrossVersion.partialVersion(scalaVersion) match { 19 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => 20 | Seq("-source", "1.7", "-target", "1.7") 21 | case _ => 22 | Seq("-source", "1.8", "-target", "1.8") 23 | } 24 | } 25 | } 26 | 27 | name := "override-step-example" 28 | 29 | version := "1.0.0" 30 | 31 | scalaVersion := "2.11.12" 32 | 33 | crossScalaVersions := Seq("2.11.12", "2.12.4") 34 | 35 | resolvers ++= Seq( 36 | Resolver.sonatypeRepo("snapshots"), 37 | Resolver.sonatypeRepo("releases") 38 | ) 39 | 40 | // Provide a managed dependency on X if -DXVersion="" is supplied on the command line. 41 | val defaultVersions = Map( 42 | "chisel3" -> "3.1.+", 43 | "chisel-iotesters" -> "1.2.+" 44 | ) 45 | 46 | libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map { 47 | dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }) 48 | 49 | scalacOptions ++= scalacOptionsVersion(scalaVersion.value) 50 | 51 | javacOptions ++= javacOptionsVersion(scalaVersion.value) 52 | -------------------------------------------------------------------------------- /example-1-override-step/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.1.1 2 | -------------------------------------------------------------------------------- /example-1-override-step/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn -------------------------------------------------------------------------------- /example-1-override-step/src/main/scala/overrideStepExample/ExamplePipeline.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package overrideStepExample 26 | 27 | import chisel3._ 28 | 29 | class ExamplePipeline extends Module { 30 | val io = IO(new Bundle { 31 | val in_data = Input(UInt(16.W)) 32 | val in_valid = Input(Bool()) 33 | val out_data = Output(UInt(16.W)) 34 | val out_valid = Output(Bool()) 35 | }) 36 | 37 | class DataAndValid extends Bundle { 38 | val data = UInt(16.W) 39 | val valid = Bool() 40 | 41 | def +&(x: UInt): DataAndValid = { 42 | val tmp = Wire(new DataAndValid) 43 | tmp.valid := this.valid 44 | tmp.data := this.data +& x 45 | tmp 46 | } 47 | } 48 | 49 | val in = Wire(new DataAndValid()) 50 | in.data := io.in_data 51 | in.valid := io.in_valid 52 | 53 | val p0 = RegNext(in) 54 | val p1 = RegNext(p0 +& 1.U) 55 | 56 | io.out_data := p1.data 57 | io.out_valid := p1.valid 58 | 59 | } 60 | -------------------------------------------------------------------------------- /example-1-override-step/src/main/scala/overrideStepExample/ExamplePipelineMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package overrideStepExample 26 | 27 | object ExamplePipelineMain extends App { 28 | chisel3.Driver.execute( 29 | Array[String]("--target-dir", "outputs") ++ args, 30 | () => new ExamplePipeline) 31 | } 32 | -------------------------------------------------------------------------------- /example-1-override-step/src/test/scala/overrideStepExample/OverrideStepExampleTest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package overrideStepExample 26 | 27 | import chisel3.iotesters 28 | import chisel3.iotesters.ChiselFlatSpec 29 | 30 | class OverrideStepExampleTest extends ChiselFlatSpec { 31 | "pipeline tester" should "compare expected and obtained response" in { 32 | iotesters.Driver.execute(Array("--backend-name", "verilator", "--fint-write-vcd"), 33 | () => new ExamplePipeline) { 34 | c => new OverrideStepExampleTester(c) 35 | } should be(true) 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/.scalafmt.conf: -------------------------------------------------------------------------------- 1 | version = 2.5.0 2 | maxColumn = 100 3 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/build.sbt: -------------------------------------------------------------------------------- 1 | 2 | ThisBuild / scalaVersion := "2.12.12" 3 | ThisBuild / version := "0.1.0" 4 | 5 | lazy val root = (project in file(".")) 6 | .settings( 7 | name := "LamportsBakeryAlgorithm", 8 | libraryDependencies ++= Seq( 9 | "edu.berkeley.cs" %% "chisel3" % "3.4.+", 10 | "edu.berkeley.cs" %% "chisel-iotesters" % "1.5.+", 11 | "io.j-marjanovic" %% "chisel-bfmtester" % "0.4.0-SNAPSHOT" 12 | ), 13 | scalacOptions ++= Seq( 14 | "-Xsource:2.11", 15 | "-language:reflectiveCalls", 16 | "-deprecation", 17 | "-feature", 18 | "-Xcheckinit" 19 | ), 20 | ) 21 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ip_cores/lamports_bakery_algo/xgui/LamportsBakeryAlgo_v1_1.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ip_cores/lamports_bakery_algo/xgui/LamportsBakeryAlgo_v1_2.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ip_cores/lamports_bakery_algo/xgui/LamportsBakeryAlgo_v1_3.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ip_cores/lamports_bakery_algo/xgui/LamportsBakeryAlgo_v1_4.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ip_cores/lamports_bakery_algo/xgui/LamportsBakeryAlgo_v2_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ip_cores/lamports_bakery_algo/xgui/LamportsBakeryAlgo_v2_1.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ip_cores/lamports_bakery_algo/xgui/LamportsBakeryAlgorithm_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.4.5 2 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn 2 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/src/main/scala/lamports_bakery_algorithm/Axi4ManagerRdCmd.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020-2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package lamports_bakery_algorithm 24 | 25 | import chisel3._ 26 | 27 | class Axi4ManagerRdCmd(val addr_w: Int, val data_w: Int) extends Bundle { 28 | val addr = Input(UInt(addr_w.W)) 29 | val data = Output(UInt(data_w.W)) // valid together with done 30 | val valid = Input(Bool()) 31 | val ready = Output(Bool()) 32 | val done = Output(Bool()) 33 | } 34 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/src/main/scala/lamports_bakery_algorithm/Axi4ManagerWrCmd.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020-2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package lamports_bakery_algorithm 24 | 25 | import chisel3._ 26 | 27 | class Axi4ManagerWrCmd(val addr_w: Int, val data_w: Int) extends Bundle { 28 | val addr = Input(UInt(addr_w.W)) 29 | val data = Input(UInt(data_w.W)) 30 | val valid = Input(Bool()) 31 | val ready = Output(Bool()) 32 | val done = Output(Bool()) 33 | } 34 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/src/main/scala/lamports_bakery_algorithm/LamportsBakeryAlgorithmMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020-2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package lamports_bakery_algorithm 24 | 25 | import chisel3._ 26 | import chisel3.stage.ChiselStage 27 | 28 | object LamportsBakeryAlgorithmMain extends App { 29 | (new ChiselStage()).emitSystemVerilog( 30 | new LamportsBakeryAlgorithm, 31 | Array[String]("--target-dir", "ip_cores/lamports_bakery_algo/hdl") ++ args 32 | ) 33 | } 34 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/src/test/scala/lamports_bakery_algorithm/Axi4LiteManagerTest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020-2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package lamports_bakery_algorithm 24 | 25 | import bfmtester._ 26 | import chisel3._ 27 | 28 | 29 | 30 | 31 | class Axi4ManagerTest(c: Axi4ManagerReg) extends BfmTester(c) { 32 | val mod_axi_mem = BfmFactory.create_axi_slave(c.io.m) 33 | 34 | step(10) 35 | 36 | poke(c.io.wr_cmd.data, 0xabcd1234L) 37 | poke(c.io.wr_cmd.addr, 0x40001020) 38 | poke(c.io.wr_cmd.valid, 1) 39 | step(1) 40 | poke(c.io.wr_cmd.data, 0) 41 | poke(c.io.wr_cmd.addr, 0) 42 | poke(c.io.wr_cmd.valid, 0) 43 | step(20) 44 | 45 | poke(c.io.rd_cmd.addr, 0x40001020) 46 | poke(c.io.rd_cmd.valid, 1) 47 | step(1) 48 | poke(c.io.rd_cmd.addr, 0) 49 | poke(c.io.rd_cmd.valid, 0) 50 | step(20) 51 | 52 | mod_axi_mem.mem_stats() 53 | } 54 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/src/test/scala/lamports_bakery_algorithm/DelayGenLfsrTest.scala: -------------------------------------------------------------------------------- 1 | package lamports_bakery_algorithm 2 | 3 | import chisel3.iotesters._ 4 | 5 | class DelayGenLfsrTest(c: DelayGenLfsr) extends PeekPokeTester(c) { 6 | 7 | poke(c.io.d, 0xaa12) 8 | poke(c.io.load, 1) 9 | step(1) 10 | poke(c.io.d, 0) 11 | poke(c.io.load, 0) 12 | step(1) 13 | 14 | for (_ <- 0 until 10) { 15 | poke(c.io.start, 1) 16 | step(1) 17 | poke(c.io.start, 0) 18 | step(math.pow(2, c.cntr_w).toInt + 5) 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ultra96v2_prj/project/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-10-lamports-bakery-algorithm/ultra96v2_prj/project/.gitkeep -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ultra96v2_prj/scripts/_compile.tcl: -------------------------------------------------------------------------------- 1 | 2 | launch_runs synth_1 3 | wait_on_run synth_1 4 | launch_runs impl_1 -to_step write_bitstream 5 | wait_on_run impl_1 6 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ultra96v2_prj/scripts/_export.tcl: -------------------------------------------------------------------------------- 1 | 2 | exec mkdir -p ../exported_hw 3 | 4 | write_hw_platform -fixed -include_bit -force -file ../exported_hw/axi_lamports_bakery_algo.xsa 5 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ultra96v2_prj/scripts/_prj.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | create_project axi_lamports_bakery_algo . -part xczu3eg-sbva484-1-i 4 | set_property board_part avnet.com:ultra96v2:part0:1.2 [current_project] 5 | set_property ip_repo_paths ../../ip_cores [current_project] 6 | update_ip_catalog 7 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ultra96v2_prj/scripts/_wrapper.tcl: -------------------------------------------------------------------------------- 1 | 2 | update_compile_order -fileset sources_1 3 | set wrapper_file [make_wrapper -files [get_files system.bd] -top] 4 | add_files -norecurse $wrapper_file 5 | -------------------------------------------------------------------------------- /example-10-lamports-bakery-algorithm/ultra96v2_prj/scripts/run_all.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../scripts/_prj.tcl 3 | source ../scripts/_bd.tcl 4 | source ../scripts/_wrapper.tcl 5 | source ../scripts/_compile.tcl 6 | source ../scripts/_export.tcl 7 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/build.sbt: -------------------------------------------------------------------------------- 1 | 2 | ThisBuild / scalaVersion := "2.12.13" 3 | ThisBuild / version := "0.1.0" 4 | ThisBuild / organization := "io.j-marjanovic" 5 | 6 | lazy val root = (project in file(".")) 7 | .settings( 8 | name := "poor-mans-system-ila", 9 | libraryDependencies ++= Seq( 10 | "edu.berkeley.cs" %% "chisel3" % "3.4.3", 11 | "io.j-marjanovic" %% "chisel-bfmtester" % "0.4.0-SNAPSHOT", 12 | ), 13 | scalacOptions ++= Seq( 14 | "-Xsource:2.11", 15 | "-language:reflectiveCalls", 16 | "-deprecation", 17 | "-feature", 18 | "-Xcheckinit", 19 | // Enables autoclonetype2 in 3.4.x (on by default in 3.5) 20 | "-P:chiselplugin:useBundlePlugin" 21 | ), 22 | addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross CrossVersion.full), 23 | addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full) 24 | ) 25 | 26 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/ip_cores/poor_mans_system_ila/driver/ila_plot.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env python3 2 | 3 | import argparse 4 | 5 | import matplotlib.pyplot as plt 6 | import numpy as np 7 | 8 | 9 | def main(): 10 | parser = argparse.ArgumentParser( 11 | description="Plot Poor Man's System ILA capture binary" 12 | ) 13 | parser.add_argument("bin", help="Input file") 14 | args = parser.parse_args() 15 | 16 | buf = open(args.bin, "rb").read() 17 | xs = np.frombuffer(buf, dtype=np.uint32) 18 | 19 | # find start of the buffer 20 | #idx = xs >> 20 21 | state = (xs >> 17) & 0x3 22 | am = np.argmax(np.diff(state)) + 1 23 | xs = np.roll(xs, -am) 24 | idx = xs >> 20 25 | # assert np.all(np.diff(idx) == np.ones(len(idx) - 1, dtype=np.uint32)) 26 | 27 | # extract individual signals 28 | mbdebug_tdi = (xs >> 15) & 1 29 | mbdebug_tdo = (xs >> 14) & 1 30 | mbdebug_clk = (xs >> 13) & 1 31 | mbdebug_reg_en = (xs >> 5) & 0xFF 32 | mbdebug_shift = (xs >> 4) & 1 33 | mbdebug_capture = (xs >> 3) & 1 34 | mbdebug_update = (xs >> 2) & 1 35 | mbdebug_rst = (xs >> 1) & 1 36 | mbdebug_disable = (xs >> 0) & 1 37 | debug_sys_reset = (xs >> 16) & 1 38 | state = (xs >> 17) & 0x3 39 | 40 | signals = [ 41 | (mbdebug_tdi, "mbdebug_tdi"), 42 | (mbdebug_tdo, "mbdebug_tdo"), 43 | (mbdebug_clk, "mbdebug_clk"), 44 | (mbdebug_reg_en, "mbdebug_reg_en"), 45 | (mbdebug_shift, "mbdebug_shift"), 46 | (mbdebug_capture, "mbdebug_capture"), 47 | (mbdebug_update, "mbdebug_update"), 48 | (mbdebug_rst, "mbdebug_rst"), 49 | (mbdebug_disable, "mbdebug_disable"), 50 | (debug_sys_reset, "debug_sys_reset"), 51 | (state, "state"), 52 | (idx, "idx"), 53 | ] 54 | 55 | fig = plt.figure(figsize=(12, 10)) 56 | axes = fig.subplots(len(signals), 1, sharex=True) 57 | 58 | for ax, signal in zip(axes, signals): 59 | ax.plot(signal[0], label=signal[1]) 60 | if signal[1] == "state" or signal[1] == "idx": 61 | pass 62 | elif signal[1] == "mbdebug_reg_en": 63 | ax.set_ylim(-0.2, 8.2) 64 | else: 65 | ax.set_ylim(-0.2, 1.2) 66 | ax.legend(loc=1) 67 | 68 | fig.suptitle(args.bin) 69 | plt.show() 70 | 71 | 72 | if __name__ == "__main__": 73 | main() 74 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/ip_cores/poor_mans_system_ila/hdl/.gitignore: -------------------------------------------------------------------------------- 1 | 2 | *.json 3 | *.f 4 | *.fir 5 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/ip_cores/poor_mans_system_ila/hdl/DualPortRam.v: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2018-2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | module DualPortRam #( 24 | parameter RAM_WIDTH = 64, 25 | parameter RAM_DEPTH = 512 26 | ) ( 27 | input clk, 28 | input [$clog2(RAM_DEPTH-1)-1:0] addra, 29 | input [ RAM_WIDTH-1:0] dina, 30 | output reg [ RAM_WIDTH-1:0] douta, 31 | input wea, 32 | 33 | input [$clog2(RAM_DEPTH-1)-1:0] addrb, 34 | input [ RAM_WIDTH-1:0] dinb, 35 | output reg [ RAM_WIDTH-1:0] doutb, 36 | input web 37 | ); 38 | 39 | reg [RAM_WIDTH-1:0] BRAM[RAM_DEPTH-1:0]; 40 | 41 | 42 | always @(posedge clk) begin : proc_porta 43 | if (wea) begin 44 | BRAM[addra] <= dina; 45 | end 46 | 47 | douta <= BRAM[addra]; 48 | end 49 | 50 | always @(posedge clk) begin : proc_portb 51 | if (web) begin 52 | BRAM[addrb] <= dinb; 53 | end 54 | 55 | doutb <= BRAM[addrb]; 56 | end 57 | 58 | endmodule 59 | 60 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/ip_cores/poor_mans_system_ila/xdc/poor_mans_system_ila_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | 3 | create_clock -name clk -period 4.0 [get_ports clock] 4 | 5 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/ip_cores/poor_mans_system_ila/xgui/PoorMansSystemILA_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/ip_cores/poor_mans_system_ila/xgui/PoorMansSystemILA_v1_1.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/ip_cores/poor_mans_system_ila/xgui/PoorMansSystemILA_v1_2.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/ip_cores/poor_mans_system_ila/xgui/PoorMansSystemILA_v1_3.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.4.9 2 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn 2 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/src/main/resources/DualPortRam.v: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2018-2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | module DualPortRam #( 24 | parameter RAM_WIDTH = 64, 25 | parameter RAM_DEPTH = 512 26 | ) ( 27 | input clk, 28 | input [$clog2(RAM_DEPTH-1)-1:0] addra, 29 | input [ RAM_WIDTH-1:0] dina, 30 | output reg [ RAM_WIDTH-1:0] douta, 31 | input wea, 32 | 33 | input [$clog2(RAM_DEPTH-1)-1:0] addrb, 34 | input [ RAM_WIDTH-1:0] dinb, 35 | output reg [ RAM_WIDTH-1:0] doutb, 36 | input web 37 | ); 38 | 39 | reg [RAM_WIDTH-1:0] BRAM[RAM_DEPTH-1:0]; 40 | 41 | 42 | always @(posedge clk) begin : proc_porta 43 | if (wea) begin 44 | BRAM[addra] <= dina; 45 | end 46 | 47 | douta <= BRAM[addra]; 48 | end 49 | 50 | always @(posedge clk) begin : proc_portb 51 | if (web) begin 52 | BRAM[addrb] <= dinb; 53 | end 54 | 55 | doutb <= BRAM[addrb]; 56 | end 57 | 58 | endmodule 59 | 60 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/src/main/scala/poor_mans_system_ila/DualPortRam.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2018-2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package poor_mans_system_ila 24 | 25 | import chisel3._ 26 | import chisel3.util._ 27 | 28 | class DualPortRam(val RAM_WIDTH: Int, val RAM_DEPTH: Int) 29 | extends BlackBox( 30 | Map("RAM_WIDTH" -> RAM_WIDTH, "RAM_DEPTH" -> RAM_DEPTH) 31 | ) 32 | with HasBlackBoxResource { 33 | 34 | val io = IO(new Bundle { 35 | val clk = Input(Clock()) 36 | val addra = Input(UInt(log2Ceil(RAM_DEPTH).W)) 37 | val dina = Input(UInt(RAM_WIDTH.W)) 38 | val douta = Output(UInt(RAM_WIDTH.W)) 39 | val wea = Input(Bool()) 40 | val addrb = Input(UInt(log2Ceil(RAM_DEPTH).W)) 41 | val dinb = Input(UInt(RAM_WIDTH.W)) 42 | val doutb = Output(UInt(RAM_WIDTH.W)) 43 | val web = Input(Bool()) 44 | }) 45 | 46 | addResource("/DualPortRam.v") 47 | 48 | } 49 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/src/main/scala/poor_mans_system_ila/MbdebugBundle.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package poor_mans_system_ila 24 | 25 | import chisel3._ 26 | 27 | class MbdebugBundle extends Bundle { 28 | val TDI = Input(Bool()) 29 | val TDO = Input(Bool()) 30 | val CLK = Input(Bool()) 31 | val REG_EN = Input(UInt(8.W)) 32 | val SHIFT = Input(Bool()) 33 | val CAPTURE = Input(Bool()) 34 | val UPDATE = Input(Bool()) 35 | val RST = Input(Bool()) 36 | val DISABLE = Input(Bool()) 37 | } 38 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/src/main/scala/poor_mans_system_ila/PoorMansSystemILAMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package poor_mans_system_ila 24 | 25 | import chisel3.stage.ChiselStage 26 | 27 | object PoorMansSystemILAMain extends App { 28 | 29 | (new ChiselStage()).emitSystemVerilog( 30 | new PoorMansSystemILA, 31 | Array[String]("--target-dir", "ip_cores/poor_mans_system_ila/hdl") ++ args 32 | ) 33 | } 34 | -------------------------------------------------------------------------------- /example-11-poor-mans-system-ila/src/test/scala/poor_mans_system_ila/PoorMansSystemILATest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package poor_mans_system_ila 24 | 25 | import chisel3.iotesters 26 | import chisel3.iotesters.ChiselFlatSpec 27 | 28 | class PoorMansSystemILATest extends ChiselFlatSpec { 29 | 30 | it should "check the generated AXI4-Lite module" in { 31 | iotesters.Driver.execute( 32 | Array( 33 | "--backend-name", 34 | "verilator", 35 | "--fint-write-vcd", 36 | "--test-seed", 37 | "1234", 38 | "--target-dir", 39 | "test_run_dir/PoorMansSystemILATester", 40 | "--top-name", 41 | "PoorMansSystemILATester" 42 | ), 43 | () => new PoorMansSystemILA(256) 44 | ) { c => 45 | new PoorMansSystemILATester(c) 46 | } should be(true) 47 | } 48 | } 49 | -------------------------------------------------------------------------------- /example-12-axi-proxy/.scalafmt.conf: -------------------------------------------------------------------------------- 1 | version = 2.5.0 2 | maxColumn = 100 3 | -------------------------------------------------------------------------------- /example-12-axi-proxy/build.sbt: -------------------------------------------------------------------------------- 1 | ThisBuild / scalaVersion := "2.12.13" 2 | ThisBuild / version := "0.1.0" 3 | ThisBuild / organization := "io.j-marjanovic" 4 | 5 | lazy val root = (project in file(".")) 6 | .settings( 7 | name := "axi-proxy", 8 | libraryDependencies ++= Seq( 9 | "edu.berkeley.cs" %% "chisel3" % "3.4.3", 10 | "io.j-marjanovic" %% "chisel-bfmtester" % "0.4.2+" 11 | ), 12 | scalacOptions ++= Seq( 13 | "-Xsource:2.11", 14 | "-language:reflectiveCalls", 15 | "-deprecation", 16 | "-feature", 17 | "-Xcheckinit", 18 | // Enables autoclonetype2 in 3.4.x (on by default in 3.5) 19 | "-P:chiselplugin:useBundlePlugin" 20 | ), 21 | addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross CrossVersion.full), 22 | addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full) 23 | ) 24 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ip_cores/axi_proxy/drivers/_AxiProxyMap.py: -------------------------------------------------------------------------------- 1 | # auto-generated with AxiLiteSubordinateGenerator from chisel-bfm-tester 2 | 3 | import ctypes 4 | 5 | 6 | class _AxiProxyMap(ctypes.Structure): 7 | _pack_ = 1 8 | _fields_ = [ 9 | ("ID_REG", ctypes.c_uint32), 10 | ("VERSION", ctypes.c_uint32), 11 | ("rsvd0x8", ctypes.c_uint32), 12 | ("SCRATCH", ctypes.c_uint32), 13 | ("STATUS", ctypes.c_uint32), 14 | ("CONTROL", ctypes.c_uint32), 15 | ("rsvd0x18", ctypes.c_uint32), 16 | ("rsvd0x1c", ctypes.c_uint32), 17 | ("CONFIG_AXI", ctypes.c_uint32), 18 | ("STATS", ctypes.c_uint32), 19 | ("rsvd0x28", ctypes.c_uint32), 20 | ("rsvd0x2c", ctypes.c_uint32), 21 | ("rsvd0x30", ctypes.c_uint32), 22 | ("rsvd0x34", ctypes.c_uint32), 23 | ("rsvd0x38", ctypes.c_uint32), 24 | ("rsvd0x3c", ctypes.c_uint32), 25 | ("ADDR_LO", ctypes.c_uint32), 26 | ("ADDR_HI", ctypes.c_uint32), 27 | ("rsvd0x48", ctypes.c_uint32), 28 | ("rsvd0x4c", ctypes.c_uint32), 29 | ("rsvd0x50", ctypes.c_uint32), 30 | ("rsvd0x54", ctypes.c_uint32), 31 | ("rsvd0x58", ctypes.c_uint32), 32 | ("rsvd0x5c", ctypes.c_uint32), 33 | ("DATA_WR0", ctypes.c_uint32), 34 | ("DATA_WR1", ctypes.c_uint32), 35 | ("DATA_WR2", ctypes.c_uint32), 36 | ("DATA_WR3", ctypes.c_uint32), 37 | ("rsvd0x70", ctypes.c_uint32), 38 | ("rsvd0x74", ctypes.c_uint32), 39 | ("rsvd0x78", ctypes.c_uint32), 40 | ("rsvd0x7c", ctypes.c_uint32), 41 | ("rsvd0x80", ctypes.c_uint32), 42 | ("rsvd0x84", ctypes.c_uint32), 43 | ("rsvd0x88", ctypes.c_uint32), 44 | ("rsvd0x8c", ctypes.c_uint32), 45 | ("rsvd0x90", ctypes.c_uint32), 46 | ("rsvd0x94", ctypes.c_uint32), 47 | ("rsvd0x98", ctypes.c_uint32), 48 | ("rsvd0x9c", ctypes.c_uint32), 49 | ("DATA_RD0", ctypes.c_uint32), 50 | ("DATA_RD1", ctypes.c_uint32), 51 | ("DATA_RD2", ctypes.c_uint32), 52 | ("DATA_RD3", ctypes.c_uint32), 53 | ] 54 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ip_cores/axi_proxy/xgui/AxiProxy_v0_1.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ip_cores/axi_proxy/xgui/AxiProxy_v0_2.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-12-axi-proxy/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.4.9 2 | -------------------------------------------------------------------------------- /example-12-axi-proxy/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn 2 | -------------------------------------------------------------------------------- /example-12-axi-proxy/src/main/scala/axi_proxy/Axi4ManagerRdCmd.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package axi_proxy 24 | 25 | import chisel3._ 26 | 27 | class Axi4ManagerRdCmd(val addr_w: Int, val data_w: Int) extends Bundle { 28 | val addr = Input(UInt(addr_w.W)) 29 | val data = Output(UInt(data_w.W)) // valid together with done 30 | val valid = Input(Bool()) 31 | val ready = Output(Bool()) 32 | val done = Output(Bool()) 33 | } 34 | -------------------------------------------------------------------------------- /example-12-axi-proxy/src/main/scala/axi_proxy/Axi4ManagerWrCmd.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package axi_proxy 24 | 25 | import chisel3._ 26 | 27 | class Axi4ManagerWrCmd(val addr_w: Int, val data_w: Int) extends Bundle { 28 | val addr = Input(UInt(addr_w.W)) 29 | val data = Input(UInt(data_w.W)) 30 | val valid = Input(Bool()) 31 | val ready = Output(Bool()) 32 | val done = Output(Bool()) 33 | } 34 | -------------------------------------------------------------------------------- /example-12-axi-proxy/src/main/scala/axi_proxy/AxiProxyMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package axi_proxy 24 | 25 | import bfmtester.util.AxiLiteSubordinateGenerator 26 | import chisel3.stage.ChiselStage 27 | 28 | object AxiProxyMain extends App { 29 | new ChiselStage().emitSystemVerilog( 30 | new AxiProxy, 31 | Array[String]("--target-dir", "ip_cores/axi_proxy/hdl") ++ args 32 | ) 33 | 34 | new java.io.File("ip_cores/axi_proxy/drivers").mkdirs 35 | AxiLiteSubordinateGenerator.gen_python_header( 36 | AxiProxy.area_map, 37 | "_AxiProxyMap", 38 | "ip_cores/axi_proxy/drivers/_AxiProxyMap.py" 39 | ) 40 | AxiLiteSubordinateGenerator.gen_c_header( 41 | AxiProxy.area_map, 42 | "AxiProxy", 43 | "ip_cores/axi_proxy/drivers/AxiProxy_regs.hpp", 44 | use_cpp_header = true 45 | ) 46 | } 47 | -------------------------------------------------------------------------------- /example-12-axi-proxy/src/test/scala/axi_proxy/AxiProxyTest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package axi_proxy 24 | 25 | import chisel3.iotesters 26 | import chisel3.iotesters.ChiselFlatSpec 27 | 28 | class AxiProxyTest extends ChiselFlatSpec { 29 | 30 | it should "check the behavior of the DUT" in { 31 | iotesters.Driver.execute( 32 | Array( 33 | "--backend-name", 34 | "verilator", 35 | "--fint-write-vcd", 36 | "--test-seed", 37 | "1234", 38 | "--target-dir", 39 | "test_run_dir/AxiProxyTester", 40 | "--top-name", 41 | "AxiProxyTester" 42 | ), 43 | () => new AxiProxyReg 44 | ) { c => 45 | new AxiProxyTester(c) 46 | } should be(true) 47 | } 48 | } 49 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ultra96v2_prj/ip_cores/axi4-activity-led/hdl/axi4_activity_led.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | module axi4_activity_led #( 4 | parameter PULSE_LEN_CYCLES = 25_000_000 5 | )( 6 | input clk, 7 | input reset_n, 8 | 9 | input slot0_axi_arvalid, 10 | input slot0_axi_arready, 11 | input slot0_axi_awvalid, 12 | input slot0_axi_awready, 13 | 14 | input slot1_axi_arvalid, 15 | input slot1_axi_arready, 16 | input slot1_axi_awvalid, 17 | input slot1_axi_awready, 18 | 19 | input slot2_axi_arvalid, 20 | input slot2_axi_arready, 21 | input slot2_axi_awvalid, 22 | input slot2_axi_awready, 23 | 24 | output LED 25 | ); 26 | 27 | wire act = 28 | (slot0_axi_arvalid && slot0_axi_arready) || 29 | (slot0_axi_awvalid && slot0_axi_awready) || 30 | (slot1_axi_arvalid && slot1_axi_arready) || 31 | (slot1_axi_awvalid && slot1_axi_awready) || 32 | (slot2_axi_arvalid && slot2_axi_arready) || 33 | (slot2_axi_awvalid && slot2_axi_awready) ; 34 | 35 | 36 | localparam CNTR_W = $clog2(PULSE_LEN_CYCLES)+1; 37 | logic [CNTR_W-1:0] cntr; 38 | 39 | enum int unsigned { 40 | S_IDLE, 41 | S_PULSE 42 | } state; 43 | 44 | always_ff @(posedge clk) begin: proc_state 45 | if (!reset_n) begin 46 | state <= S_IDLE; 47 | end else begin 48 | case (state) 49 | S_IDLE: if (act) state <= S_PULSE; 50 | S_PULSE: if (cntr >= PULSE_LEN_CYCLES-1) state <= S_IDLE; 51 | default: state <= S_IDLE; 52 | endcase 53 | end 54 | end 55 | 56 | always_ff @(posedge clk) begin: proc_cntr 57 | if (!reset_n) begin 58 | cntr <= 0; 59 | end else begin 60 | if (act) begin 61 | cntr <= 0; 62 | end else if (state == S_PULSE) begin 63 | cntr <= cntr + 1; 64 | end 65 | end 66 | end 67 | 68 | assign LED = state == S_PULSE; 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ultra96v2_prj/ip_cores/axi4-activity-led/xgui/axi4_activity_led_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "PULSE_LEN_CYCLES" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.PULSE_LEN_CYCLES { PARAM_VALUE.PULSE_LEN_CYCLES } { 12 | # Procedure called to update PULSE_LEN_CYCLES when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.PULSE_LEN_CYCLES { PARAM_VALUE.PULSE_LEN_CYCLES } { 16 | # Procedure called to validate PULSE_LEN_CYCLES 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.PULSE_LEN_CYCLES { MODELPARAM_VALUE.PULSE_LEN_CYCLES PARAM_VALUE.PULSE_LEN_CYCLES } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.PULSE_LEN_CYCLES}] ${MODELPARAM_VALUE.PULSE_LEN_CYCLES} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ultra96v2_prj/project/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-12-axi-proxy/ultra96v2_prj/project/.gitkeep -------------------------------------------------------------------------------- /example-12-axi-proxy/ultra96v2_prj/scripts/_compile.tcl: -------------------------------------------------------------------------------- 1 | 2 | launch_runs synth_1 3 | wait_on_run synth_1 4 | launch_runs impl_1 -to_step write_bitstream 5 | wait_on_run impl_1 6 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ultra96v2_prj/scripts/_export.tcl: -------------------------------------------------------------------------------- 1 | 2 | exec mkdir -p ../exported_hw 3 | 4 | write_hw_platform -fixed -include_bit -force -file ../exported_hw/axi_proxy.xsa 5 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ultra96v2_prj/scripts/_prj.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | create_project axi_proxy . -part xczu3eg-sbva484-1-i 4 | set_property board_part avnet.com:ultra96v2:part0:1.2 [current_project] 5 | set_property ip_repo_paths [list ../../ip_cores ../ip_cores] [current_project] 6 | update_ip_catalog 7 | 8 | add_files -fileset constrs_1 -norecurse ../xdc/pin_assignments.xdc 9 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ultra96v2_prj/scripts/_wrapper.tcl: -------------------------------------------------------------------------------- 1 | 2 | update_compile_order -fileset sources_1 3 | set wrapper_file [make_wrapper -files [get_files system.bd] -top] 4 | add_files -norecurse $wrapper_file 5 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ultra96v2_prj/scripts/run_all.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../scripts/_prj.tcl 3 | source ../scripts/_bd.tcl 4 | source ../scripts/_wrapper.tcl 5 | source ../scripts/_compile.tcl 6 | source ../scripts/_export.tcl 7 | -------------------------------------------------------------------------------- /example-12-axi-proxy/ultra96v2_prj/xdc/pin_assignments.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN A9 [get_ports {RADIO_LED0[0]}] 2 | set_property PACKAGE_PIN B9 [get_ports RADIO_LED1] 3 | set_property IOSTANDARD LVCMOS18 [get_ports {RADIO_LED0[0]}] 4 | set_property IOSTANDARD LVCMOS18 [get_ports RADIO_LED1] 5 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/.scalafmt.conf: -------------------------------------------------------------------------------- 1 | version = 2.5.0 2 | maxColumn = 100 3 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/build.sbt: -------------------------------------------------------------------------------- 1 | 2 | ThisBuild / scalaVersion := "2.12.13" 3 | ThisBuild / version := "0.1.0" 4 | ThisBuild / organization := "io.j-marjanovic" 5 | 6 | lazy val root = (project in file(".")) 7 | .settings( 8 | name := "axi-traffic-gen", 9 | libraryDependencies ++= Seq( 10 | "edu.berkeley.cs" %% "chisel3" % "3.4.3", 11 | "io.j-marjanovic" %% "chisel-bfmtester" % "0.4.2", 12 | ), 13 | scalacOptions ++= Seq( 14 | "-Xsource:2.11", 15 | "-language:reflectiveCalls", 16 | "-deprecation", 17 | "-feature", 18 | "-Xcheckinit", 19 | // Enables autoclonetype2 in 3.4.x (on by default in 3.5) 20 | "-P:chiselplugin:useBundlePlugin" 21 | ), 22 | addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross CrossVersion.full), 23 | addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full) 24 | ) 25 | 26 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/ip_cores/axi_traffic_gen/xgui/AxiTrafficGen_v0_1.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/ip_cores/axi_traffic_gen/xgui/AxiTrafficGen_v0_9.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.4.9 2 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn 2 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/src/main/scala/axi_traffic_gen/Axi4ManagerRdCmd.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package axi_traffic_gen 24 | 25 | import chisel3._ 26 | 27 | class Axi4ManagerRdCmd(val addr_w: Int) extends Bundle { 28 | val addr = Input(UInt(addr_w.W)) 29 | val len = Input(UInt(32.W)) 30 | val valid = Input(Bool()) 31 | val ready = Output(Bool()) 32 | val done = Output(Bool()) 33 | } 34 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/src/main/scala/axi_traffic_gen/Axi4ManagerWrCmd.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package axi_traffic_gen 24 | 25 | import chisel3._ 26 | 27 | class Axi4ManagerWrCmd(val addr_w: Int) extends Bundle { 28 | val addr = Input(UInt(addr_w.W)) 29 | val len = Input(UInt(32.W)) 30 | val valid = Input(Bool()) 31 | val ready = Output(Bool()) 32 | val done = Output(Bool()) 33 | } 34 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/src/main/scala/axi_traffic_gen/AxiTGConfig.scala: -------------------------------------------------------------------------------- 1 | package axi_traffic_gen 2 | 3 | object AxiTGConfig { 4 | val NR_BEATS_PER_BURST: Int = 4 5 | val NR_BURSTS_IN_FLIGHT: Int = 4 6 | } 7 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/src/main/scala/axi_traffic_gen/AxiTrafficGenMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package axi_traffic_gen 24 | 25 | import bfmtester.util.AxiLiteSubordinateGenerator 26 | import chisel3.stage.ChiselStage 27 | 28 | import java.io.File 29 | 30 | object AxiTrafficGenMain extends App { 31 | new ChiselStage().emitSystemVerilog( 32 | new AxiTrafficGen(40, 128, 2), 33 | Array[String]("--target-dir", "ip_cores/axi_traffic_gen/hdl") ++ args 34 | ) 35 | 36 | val directory: File = new File("ip_cores/axi_traffic_gen/drivers"); 37 | if (!directory.exists()) { 38 | directory.mkdirs() 39 | } 40 | 41 | AxiLiteSubordinateGenerator.gen_python_header( 42 | AxiTrafficGen.area_map, 43 | "_AxiTrafficGenMap", 44 | "ip_cores/axi_traffic_gen/drivers/_AxiTrafficGenMap.py" 45 | ) 46 | AxiLiteSubordinateGenerator.gen_c_header( 47 | AxiTrafficGen.area_map, 48 | "AxiTrafficGen", 49 | "ip_cores/axi_traffic_gen/drivers/AxiTrafficGen_regs.hpp", 50 | use_cpp_header = true 51 | ) 52 | } 53 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/src/main/scala/axi_traffic_gen/UpDownCounter.scala: -------------------------------------------------------------------------------- 1 | package axi_traffic_gen 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | 6 | class UpDownCounter private (r: Range, inc: Bool, dec: Bool) { 7 | require(r.nonEmpty, s"Counter range cannot be empty, got: $r") 8 | require(r.start >= 0 && r.end >= 0, s"Counter range must be positive, got: $r") 9 | require(r.step == 1, s"Counter step must be 1, got: $r") 10 | 11 | private lazy val width = math.max(log2Up(r.last + 1), log2Up(r.head + 1)) 12 | 13 | val value = RegInit(r.head.U(width.W)) 14 | 15 | when (inc && !dec) { 16 | when(value < r.end.U) { 17 | value := value + 1.U 18 | } 19 | } 20 | 21 | when (dec && !inc) { 22 | when(value > 0.U) { 23 | value := value - 1.U 24 | } 25 | } 26 | 27 | def is_full(): Bool = { 28 | value === r.end.U 29 | } 30 | 31 | def is_almost_full(): Bool = { 32 | value === (r.end - 1).U 33 | } 34 | 35 | def is_empty(): Bool = { 36 | value === r.start.U 37 | } 38 | } 39 | 40 | object UpDownCounter { 41 | def apply(r: Range, inc: Bool, dec: Bool) = new UpDownCounter(r, inc, dec) 42 | } 43 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/ultra96v2_prj/project/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-13-axi-traffic-gen/ultra96v2_prj/project/.gitkeep -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/ultra96v2_prj/scripts/_compile.tcl: -------------------------------------------------------------------------------- 1 | 2 | launch_runs synth_1 3 | wait_on_run synth_1 4 | launch_runs impl_1 -to_step write_bitstream 5 | wait_on_run impl_1 6 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/ultra96v2_prj/scripts/_export.tcl: -------------------------------------------------------------------------------- 1 | 2 | exec mkdir -p ../exported_hw 3 | 4 | write_hw_platform -fixed -include_bit -force -file ../exported_hw/axi_traffic_gen.xsa 5 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/ultra96v2_prj/scripts/_prj.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | create_project axi_tg . -part xczu3eg-sbva484-1-i 4 | set_property board_part avnet.com:ultra96v2:part0:1.1 [current_project] 5 | set_property ip_repo_paths [list ../../ip_cores ../../../example-12-axi-proxy/ultra96v2_prj/ip_cores] [current_project] 6 | update_ip_catalog 7 | 8 | add_files -fileset constrs_1 -norecurse ../xdc/pin_assignments.xdc 9 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/ultra96v2_prj/scripts/_wrapper.tcl: -------------------------------------------------------------------------------- 1 | 2 | update_compile_order -fileset sources_1 3 | set wrapper_file [make_wrapper -files [get_files system.bd] -top] 4 | add_files -norecurse $wrapper_file 5 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/ultra96v2_prj/scripts/run_all.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../scripts/_prj.tcl 3 | source ../scripts/_bd.tcl 4 | source ../scripts/_wrapper.tcl 5 | source ../scripts/_compile.tcl 6 | source ../scripts/_export.tcl 7 | -------------------------------------------------------------------------------- /example-13-axi-traffic-gen/ultra96v2_prj/xdc/pin_assignments.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN A9 [get_ports {RADIO_LED0[0]}] 2 | set_property PACKAGE_PIN B9 [get_ports RADIO_LED1] 3 | set_property IOSTANDARD LVCMOS18 [get_ports {RADIO_LED0[0]}] 4 | set_property IOSTANDARD LVCMOS18 [get_ports RADIO_LED1] 5 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/.scalafmt.conf: -------------------------------------------------------------------------------- 1 | version = 2.5.0 2 | maxColumn = 100 3 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/README.md: -------------------------------------------------------------------------------- 1 | # PCIe endpoint with a high-performance DMA and an Avalon-MM interface 2 | 3 | Designed to be used together with Stratix V Hard IP for PCI Express Intel FPGA 4 | IP. It provides 256-bit interface, capable of operating at 250 MHz which 5 | corresponds to Gen 3 (8 GT/s) x8 link. 6 | 7 | ## Example usage 8 | 9 | The figure below shows the usage of this IP in Quartus Platform Manager. 10 | 11 | ![PCIe endpoint block diagram](docs/example_usage.png) 12 | 13 | ## Block diagram 14 | 15 | Illustrated in the figure below are the main modules of this IP. 16 | 17 | ![PCIe endpoint block diagram](docs/pcie_endpoint.drawio.png) 18 | 19 | ## Dependencies 20 | 21 | The tests in this Chisel HDL project require [BFM Tester for Chisel 22 | HDL](https://github.com/j-marjanovic/chisel-bfm-tester). 23 | 24 | 25 | --- 26 | 27 | Intel, the Intel logo, Altera, Nios, Quartus and Stratix words and logos are 28 | trademarks of Intel Corporation or its subsidiaries in the U.S. and/or 29 | other countries. 30 | 31 | PCI Express® and PCIe® are registered trademarks of PCI-SIG. 32 | 33 | All trademarks and registered trademarks are the property of their respective 34 | owners. 35 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/build.sbt: -------------------------------------------------------------------------------- 1 | ThisBuild / scalaVersion := "2.12.13" 2 | ThisBuild / version := "0.1.0" 3 | ThisBuild / organization := "io.j-marjanovic" 4 | 5 | lazy val root = (project in file(".")) 6 | .settings( 7 | name := "pcie-endpoint", 8 | libraryDependencies ++= Seq( 9 | "edu.berkeley.cs" %% "chisel3" % "3.4.3", 10 | "edu.berkeley.cs" %% "chisel-iotesters" % "1.5.+", 11 | "io.j-marjanovic" %% "chisel-bfmtester" % "0.4.+", 12 | "org.scodec" %% "scodec-core" % "1.11.8" 13 | ), 14 | scalacOptions ++= Seq( 15 | "-Xsource:2.11", 16 | "-language:reflectiveCalls", 17 | "-deprecation", 18 | "-feature", 19 | "-Xcheckinit", 20 | // Enables autoclonetype2 in 3.4.x (on by default in 3.5) 21 | "-P:chiselplugin:useBundlePlugin" 22 | ), 23 | addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross CrossVersion.full), 24 | addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full) 25 | ) 26 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/docs/example_usage.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-14-pcie-endpoint/docs/example_usage.png -------------------------------------------------------------------------------- /example-14-pcie-endpoint/docs/pcie_endpoint.drawio: -------------------------------------------------------------------------------- 1 | 7Vzfc5s4EP5r/HgdCSHAj46TtDdzmWSSu2nTF48MMqaHkUfIiX1//QkD5oewTZOAaMd+MVqEEPr225V2BSM0XW0/c7Je3jGPhiMDeNsRuh4ZBoSGI/8SyS6V2AClAp8HXlapEDwF/9FMCDLpJvBoXKkoGAtFsK4KXRZF1BUVGeGcvVarLVhYveua+FQRPLkkVKVfA08s8+cCoDjxhQb+Mru1g7MTK5JXzgTxknjstSRCNyM05YyJ9Gi1ndIwGbx8XNLrbo+cPXSM00i0ueDHi/MP/foFeXCGZ/eb7+D1/v6PrJUXEm6yB35wA3oTeWsWyGbTjotdPhqcbSKPJg2CEbp6XQaCPq2Jm5x9lfhL2VKsQlmC8pCEgR/J45AuZAevXigXgRzYSSYWLKm/CMJwykLG9zdAc+I6HpLyWHD2Ly2dMZBpYi+5gkXiKesSzMup3kBTlrMnknej26NDBQ8ASM2lbEUF38kq2QUHzDKlhU5Wfi1UwMxlyxL6ppUJSaZ2/qHtAhl5kIHzE0BZChbUk4qaFRkXS+aziIQ3hfSqilZR5y+WDP1+8H5QIXbZ6JGNYFUE6TYQ30rHz0lTnwycFa+3WdP7wi4vRPJ5v5UL5cuScnHdvpRf2A7Y5LFPwypHiW24S0+MppFZEsJ9Kk7UQ81qwmlIRPBS7UcT5PtLJ5yTXanCnlpxqeWHlGu59pm4qn3GGFWJfa4+RjV1S3tQKN/hUd6uj/Zw9PFt6vhebUwNVO4TkB79NN+pn+8ySYbiO+7oivHdIyXeVy5dw5St1mH/PsRzALAbfcgEA2Dm4Jbki/2vJ99SZ6ul+hbY5Fsg6sq3QFMnmUGFzHZLNsPhOhfUkrzQ0MleE+oE/WcsuA5oxjqhQYphnchjFk18qmNOPmx7ao5r9tRsaU9xV+bURL8Ks946N+p07mO25aij1XwqHN3PdqgIWPRI3ZcLTU/TFAHdNEWG1lnPgZrPpTPnaFow87lCTO1zHtyWtKBZS/ohLVZIe7WJ70hEfMr7JywAGNBFE2EBgNdX02ER1mxLWNgZYw1bwU8HhTv1fuOWRDqGXj9EGitA/L2d8LmkiAYewTmB1GjmkXUzuR3Wet9smJ/a/dJorNXx9TA//UA+5nmo84TUuprPu1li5J+RZCPfrMVUcA1ROAuQMbSbWGlc2xYY2HQU2/YnrHlCmhuGX4iXA47CwbYxdK2hnryXjevIkWGFCd/m0qlafnL0mUYX/1plMlL8q9HA5HEDke3OVpZaQ6sfQWR70NkxaPVE7belb+2aa4G1fRnn6uPT6V5knKzfTbo3H/LGpfNN5AcRvRimqmHC4GCIctPUsI0EYqxaps52kSCtafshxLxiaTTEJNkYJiVuSOI4cHPxbRDmXf5Ia2W3tFYpx7TNRNTgSsHwR+rHF36f5Tdqye/uMvmOAqK3IjO2UdOG8ZKsk8NY0GTo15QHsg+UZ6KHonwO2kWwpfnOTXgU2zirAFSc54AiajXiTB3gOP3gaZv1DEXjkhA0zCQR7gpPNdA2J1xdJ17APAOmnGVpB9PEOpxvt/vU2kbH9Po2Q42OJWYxUBfTOonkBZy6+3W/bI/GQuWWB1za7BCxhaFN9XDLHDetuPvlVv4UJYTFdhYPy+2dB3gYxrOe+Rvrt52GGieTi+LZKg4uCL8fYexox1eNL/x+zrLt7kOtmSRD3X3IB2dJB+kXlR1O+s2m+du/pvGR/Gy7icnUO5lVdzG5LFoE/kyoad4LSU+T1ID6567OcDja9u2L4W5ENFpyOA139p4bqiUrEXbK6nO+vnM6l4Sdk/W7yQ0hre+mlpT2fFahR0V876t5zQBbxpGUUt5EqvgPh7e3b9+mqMfu022SUUuAbFB58w9UwPZ5p/euN95mCmumyszCo0dNYb3+GHevkaa6LJ3u51obTtIdOjV97TwnRve/plkUstAY9fWBhPpLrLAh89X4gYSuMl9YTYoMfaVTsx2tTEdHvqrtrnO9r2/k3SyxkazXs6YPlQw7COh6dO7MdZO4HsfvMgooi8WXblLrXHwvCN38Dw== -------------------------------------------------------------------------------- /example-14-pcie-endpoint/docs/pcie_endpoint.drawio.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-14-pcie-endpoint/docs/pcie_endpoint.drawio.png -------------------------------------------------------------------------------- /example-14-pcie-endpoint/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.4.9 2 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn 2 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/src/main/scala/pcie_endpoint/BusMaster.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package pcie_endpoint 24 | 25 | import chisel3._ 26 | import chisel3.experimental.ChiselEnum 27 | import chisel3.util._ 28 | 29 | import scala.collection.mutable.Map 30 | 31 | class BusMaster(val if_width: Int) extends Module { 32 | val io = IO(new Bundle { 33 | val conf_internal = Input(new Interfaces.ConfigIntern) 34 | 35 | val ctrl_cmd = Flipped(new Interfaces.MemoryCmd) 36 | val ctrl_resp = new Interfaces.MemoryResp 37 | 38 | val mrd_in_flight_dec = Flipped(Valid(UInt(10.W))) 39 | 40 | val arb_hint = Output(Bool()) 41 | val tx_st = new Interfaces.AvalonStreamTx(if_width) 42 | 43 | val dma_in = new Interfaces.AvalonStreamDataIn(if_width) 44 | 45 | val irq_fire = Output(Bool()) 46 | }) 47 | 48 | val mod_regs = Module(new BusMasterRegs) 49 | mod_regs.io.ctrl_cmd <> io.ctrl_cmd 50 | mod_regs.io.ctrl_resp <> io.ctrl_resp 51 | 52 | val mod_engine = Module(new BusMasterEngine(if_width)) 53 | io.arb_hint := mod_engine.io.arb_hint 54 | mod_engine.io.mrd_in_flight_dec := io.mrd_in_flight_dec 55 | mod_engine.io.tx_st <> io.tx_st 56 | mod_engine.io.conf_internal := io.conf_internal 57 | mod_engine.io.dma_desc := mod_regs.io.dma_desc 58 | mod_engine.io.dma_in <> io.dma_in 59 | io.irq_fire := mod_engine.io.irq_fire 60 | 61 | mod_regs.io.fsm_busy := mod_engine.io.fsm_busy 62 | 63 | } 64 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/src/main/scala/pcie_endpoint/Configuration.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package pcie_endpoint 24 | 25 | import chisel3._ 26 | 27 | class Configuration extends Module { 28 | val io = IO(new Bundle { 29 | val cfg = Input(new Interfaces.TLConfig) 30 | 31 | val conf_internal = Output(new Interfaces.ConfigIntern) 32 | }) 33 | 34 | // from "Configuration Space Register Access Timing" 35 | val tl_cfg_add_reg = RegNext(io.cfg.add(0)) 36 | val tl_cfg_add_reg2 = RegNext(tl_cfg_add_reg) 37 | 38 | val cfgctl_addr_change = RegNext(tl_cfg_add_reg2 =/= tl_cfg_add_reg) 39 | val cfgctl_addr_change2 = RegNext(cfgctl_addr_change) 40 | val cfgctl_addr_strobe = RegNext(cfgctl_addr_change2) 41 | 42 | val reg_msicsr = RegInit(UInt(16.W), 0.U) 43 | val reg_busdev = RegInit(UInt(13.W), 0.U) 44 | 45 | when(cfgctl_addr_strobe) { 46 | when(io.cfg.add === 0xd.U) { 47 | reg_msicsr := io.cfg.ctl(15, 0) 48 | }.elsewhen(io.cfg.add === 0xf.U) { 49 | printf(p"Configuration: busdev = ${io.cfg.ctl}\n") 50 | reg_busdev := io.cfg.ctl(12, 0) 51 | } 52 | } 53 | 54 | io.conf_internal.busdev := reg_busdev 55 | io.conf_internal.msicsr := reg_msicsr 56 | 57 | } 58 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/src/main/scala/pcie_endpoint/InterruptCtrl.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package pcie_endpoint 24 | 25 | import chisel3._ 26 | 27 | class InterruptCtrl extends Module { 28 | val io = IO(new Bundle { 29 | val app_int = new Interfaces.AppInt 30 | 31 | val conf_internal = Input(new Interfaces.ConfigIntern) 32 | 33 | val trigger = Input(Bool()) 34 | }) 35 | 36 | val msi_en = WireInit(io.conf_internal.msicsr(0)) 37 | val reg_en = RegInit(false.B) 38 | 39 | val trigger_edge = WireInit(io.trigger && !RegNext(io.trigger)) 40 | 41 | when(trigger_edge) { 42 | reg_en := true.B 43 | }.elsewhen((msi_en && io.app_int.msi_ack) || (!msi_en && io.app_int.ack)) { 44 | reg_en := false.B 45 | } 46 | 47 | io.app_int.sts := reg_en 48 | io.app_int.msi_req := msi_en && reg_en 49 | 50 | io.app_int.msi_num := 0.U 51 | io.app_int.msi_tc := 0.U 52 | 53 | } 54 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/src/main/scala/pcie_endpoint/Main.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package pcie_endpoint 24 | 25 | import chisel3.stage.ChiselStage 26 | 27 | object Main extends App { 28 | for (if_width <- List(64, 256)) { 29 | new ChiselStage().emitSystemVerilog( 30 | new PcieEndpointWrapper(if_width), 31 | Array[String]( 32 | "--target-dir", 33 | "ip_cores/pcie_endpoint/hdl", 34 | "--output-file", 35 | s"PcieEndpointWrapper${if_width}" 36 | ) ++ args 37 | ) 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/src/main/scala/pcie_endpoint/ReadyCorrection.scala: -------------------------------------------------------------------------------- 1 | package pcie_endpoint 2 | 3 | import chisel3._ 4 | 5 | /** 6 | * -1 0 1 2 3 4 7 | * | | | | | | 8 | * +------+ 9 | * ready at the core | | 10 | * ----+ +-------------------------------- 11 | * +------+ 12 | * ready at the app | | 13 | * -------------------------+ +----------- 14 | * +---------------------------+ 15 | * valid at the app | | 16 | * ----+ +----------- 17 | * +------+ 18 | * valid at the core | | 19 | * -------------------------+ +----------- 20 | */ 21 | 22 | class ReadyCorrection extends MultiIOModule { 23 | val core_ready = IO(Input(Bool())) 24 | val app_ready = IO(Output(Bool())) 25 | val core_valid = IO(Output(Bool())) 26 | val app_valid = IO(Input(Bool())) 27 | 28 | val ready_ppp = RegNext(RegNext(RegNext(core_ready))) 29 | 30 | app_ready := ready_ppp 31 | core_valid := ready_ppp && app_valid 32 | } 33 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/src/test/scala/pcie_endpoint/AvalonStreamDataOutBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package pcie_endpoint 24 | 25 | import bfmtester._ 26 | import chisel3._ 27 | 28 | import scala.collection.mutable.ListBuffer 29 | 30 | class AvalonStreamDataOutBfm( 31 | val data_out: Interfaces.AvalonStreamDataOut, 32 | val peek: Bits => BigInt, 33 | val poke: (Bits, BigInt) => Unit, 34 | val println: String => Unit 35 | ) extends Bfm { 36 | 37 | private val data = ListBuffer[Byte]() 38 | 39 | private def printWithBg(s: String): Unit = { 40 | // dark blue on light gray 41 | println("\u001b[38;5;18;47m" + s + "\u001b[39;49m") 42 | } 43 | 44 | def get_data(): List[Byte] = { 45 | val tmp = data.toList 46 | data.clear() 47 | tmp 48 | } 49 | 50 | override def update(t: Long, poke: (Bits, BigInt) => Unit): Unit = { 51 | val valid = peek(data_out.valid) > 0 52 | 53 | if (valid) { 54 | val data_beat = peek(data_out.data) 55 | // TODO: handle empty 56 | for (i <- 0 until data_out.data.getWidth / 8) { 57 | val b: Byte = ((data_beat >> (8 * i)) & 0xff).toByte 58 | data += b 59 | } 60 | printWithBg(f"${t}%5d AvalonStreamDataOutBfm: recv ${data_beat}%x") 61 | } 62 | } 63 | 64 | printWithBg(f" AvalonStreamDataOutBfm: BFM initialized") 65 | } 66 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/src/test/scala/pcie_endpoint/AvalonStreamTxBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package pcie_endpoint 24 | 25 | import bfmtester.Bfm 26 | import chisel3.Bits 27 | 28 | import scala.collection.mutable.ListBuffer 29 | 30 | class AvalonStreamTxBfm( 31 | val av_st_tx: Interfaces.AvalonStreamTx, 32 | val peek: Bits => BigInt, 33 | val poke: (Bits, BigInt) => Unit, 34 | val println: String => Unit 35 | ) extends Bfm { 36 | 37 | class RecvData(val data: BigInt, val empty: BigInt) {} 38 | 39 | val recv_buffer = ListBuffer[RecvData]() 40 | 41 | private def printWithBg(s: String): Unit = { 42 | // dark blue on light gray 43 | println("\u001b[38;5;18;47m" + s + "\u001b[39;49m") 44 | } 45 | 46 | override def update(t: Long, poke: (Bits, BigInt) => Unit): Unit = { 47 | poke(av_st_tx.ready, 1) 48 | val valid = peek(av_st_tx.valid) 49 | if (valid > 0) { 50 | val data = peek(av_st_tx.data) 51 | val empty = peek(av_st_tx.empty) 52 | recv_buffer += new RecvData(data, empty) 53 | printWithBg(f"${t}%5d AvalonStreamTxBfm: data = ${data}%x, empty = ${empty}") 54 | } 55 | } 56 | 57 | printWithBg(f" AvalonStreamTxBfm: BFM initialized") 58 | 59 | } 60 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/src/test/scala/pcie_endpoint/TLConfigBFM.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package pcie_endpoint 24 | 25 | import bfmtester.Bfm 26 | import chisel3.Bits 27 | 28 | import scala.util.Random 29 | 30 | class TLConfigBFM( 31 | iface: Interfaces.TLConfig, 32 | val peek: Bits => BigInt, 33 | val poke: (Bits, BigInt) => Unit, 34 | val println: String => Unit, 35 | val rnd_gen: Random 36 | ) extends Bfm { 37 | 38 | var cntr: Int = 0 39 | var addr: Int = 0 40 | 41 | override def update(t: Long, poke: (Bits, BigInt) => Unit): Unit = { 42 | 43 | poke(iface.add, addr) 44 | if (cntr == 0 || cntr == 1 || cntr == 6 || cntr == 7) { 45 | poke(iface.ctl, rnd_gen.nextLong()) 46 | } else { 47 | if (addr == 0xf) { 48 | poke(iface.ctl, 4) 49 | } else { 50 | // TODO: add other regs 51 | poke(iface.ctl, 0) 52 | } 53 | } 54 | 55 | cntr += 1 56 | if (cntr > 7) { 57 | cntr = 0 58 | addr = (addr + 1) % 16 59 | } 60 | } 61 | } 62 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/test_sv/scripts/sim_cpld2.do: -------------------------------------------------------------------------------- 1 | 2 | .main clear 3 | 4 | if {[file exists work]} { 5 | vdel -lib work -all 6 | } 7 | 8 | # BFMs 9 | set INTEL_QUARUTS_PATH /opt/intelFPGA/20.1 10 | 11 | vlog $INTEL_QUARUTS_PATH/ip/altera/sopc_builder_ip/verification/lib/verbosity_pkg.sv 12 | vlog $INTEL_QUARUTS_PATH/ip/altera/sopc_builder_ip/verification/lib/avalon_utilities_pkg.sv 13 | vlog $INTEL_QUARUTS_PATH/ip/altera/sopc_builder_ip/verification/altera_avalon_clock_reset_source/altera_avalon_clock_reset_source.sv 14 | vlog $INTEL_QUARUTS_PATH/ip/altera/sopc_builder_ip/verification/altera_avalon_st_source_bfm/altera_avalon_st_source_bfm.sv 15 | vlog $INTEL_QUARUTS_PATH/ip/altera/sopc_builder_ip/verification/altera_avalon_st_sink_bfm/altera_avalon_st_sink_bfm.sv 16 | 17 | # DUT 18 | vlog ../../ip_cores/pcie_endpoint/hdl/PcieEndpointWrapper256.sv 19 | 20 | # TB 21 | vlog ../tb/PciePackets.sv 22 | vlog ../tb/pp_sp_pcie_endpoint_th.sv 23 | vlog ../tb/pp_sp_pcie_endpoint_tb_cpld2.sv 24 | 25 | 26 | vsim work.pp_sp_pcie_endpoint_tb_cpld2 27 | 28 | add wave -radix hex \ 29 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/coreclkout_hip \ 30 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/reset_status 31 | 32 | add wave -divider "RX" 33 | add wave -radix hex \ 34 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/rx_st_data \ 35 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/rx_st_sop \ 36 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/rx_st_eop \ 37 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/rx_st_empty \ 38 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/rx_st_ready \ 39 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/rx_st_valid \ 40 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/rx_st_err \ 41 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/rx_st_mask \ 42 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/rx_st_bar 43 | 44 | add wave -divider "Data Out" 45 | add wave -radix hex \ 46 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/dma_out_data \ 47 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/dma_out_valid \ 48 | sim:/pp_sp_pcie_endpoint_tb_cpld2/th/dma_out_empty 49 | 50 | 51 | run -all 52 | 53 | wave zoom full 54 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/test_sv/tb/pp_sp_pcie_endpoint_tb_cpld2.sv: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | `timescale 1ps / 1ps 24 | 25 | module pp_sp_pcie_endpoint_tb_cpld2; 26 | 27 | //============================================================================ 28 | // test harness 29 | 30 | pp_sp_pcie_endpoint_th th (); 31 | 32 | //============================================================================ 33 | // tasks 34 | 35 | 36 | //============================================================================ 37 | // main 38 | 39 | initial begin : proc_main 40 | automatic bit [255:0] resp_data; 41 | automatic bit [ 7:0] resp_empty; 42 | 43 | @(negedge th.reset_status); 44 | th.st_sink_tx.set_ready(1); 45 | #(100ns); 46 | 47 | `include "cpld_stim.h" 48 | 49 | 50 | #(100ns); 51 | 52 | 53 | $finish(); 54 | end 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/test_sv/work/.gitignore: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | !.gitkeep 4 | -------------------------------------------------------------------------------- /example-14-pcie-endpoint/test_sv/work/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-14-pcie-endpoint/test_sv/work/.gitkeep -------------------------------------------------------------------------------- /example-2-axi-lite-if/README.md: -------------------------------------------------------------------------------- 1 | # Example 2: AXI-Lite component 2 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/build.sbt: -------------------------------------------------------------------------------- 1 | def scalacOptionsVersion(scalaVersion: String): Seq[String] = { 2 | Seq() ++ { 3 | // If we're building with Scala > 2.11, enable the compile option 4 | // switch to support our anonymous Bundle definitions: 5 | // https://github.com/scala/bug/issues/10047 6 | CrossVersion.partialVersion(scalaVersion) match { 7 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq() 8 | case _ => Seq("-Xsource:2.11") 9 | } 10 | } 11 | } 12 | 13 | def javacOptionsVersion(scalaVersion: String): Seq[String] = { 14 | Seq() ++ { 15 | // Scala 2.12 requires Java 8. We continue to generate 16 | // Java 7 compatible code for Scala 2.11 17 | // for compatibility with old clients. 18 | CrossVersion.partialVersion(scalaVersion) match { 19 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => 20 | Seq("-source", "1.7", "-target", "1.7") 21 | case _ => 22 | Seq("-source", "1.8", "-target", "1.8") 23 | } 24 | } 25 | } 26 | 27 | name := "override-step-example" 28 | 29 | version := "1.0.0" 30 | 31 | scalaVersion := "2.11.12" 32 | 33 | crossScalaVersions := Seq("2.11.12", "2.12.4") 34 | 35 | resolvers ++= Seq( 36 | Resolver.sonatypeRepo("snapshots"), 37 | Resolver.sonatypeRepo("releases") 38 | ) 39 | 40 | // Provide a managed dependency on X if -DXVersion="" is supplied on the command line. 41 | val defaultVersions = Map( 42 | "chisel3" -> "3.1.+", 43 | "chisel-iotesters" -> "1.2.+" 44 | ) 45 | 46 | libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map { 47 | dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }) 48 | 49 | scalacOptions ++= scalacOptionsVersion(scalaVersion.value) 50 | 51 | javacOptions ++= javacOptionsVersion(scalaVersion.value) 52 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.1.1 2 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn -------------------------------------------------------------------------------- /example-2-axi-lite-if/src/main/scala/axiLiteExample/AxiLite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3._ 28 | import chisel3.util.Irrevocable 29 | 30 | class AxiLite(val ADDR_W: Int, val DATA_W: Int = 32) extends Bundle { 31 | val AW = Flipped(Irrevocable(UInt(ADDR_W.W))) 32 | val W = Flipped(Irrevocable(UInt(DATA_W.W))) 33 | val B = Irrevocable(UInt(2.W)) 34 | val AR = Flipped(Irrevocable(UInt(ADDR_W.W))) 35 | val R = Irrevocable(new Bundle { 36 | val rdata = UInt(DATA_W.W); val rresp = UInt(2.W) 37 | }) 38 | } 39 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/src/main/scala/axiLiteExample/PipelineWithAxiLite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3._ 28 | 29 | class PipelineWithAxiLite extends Module { 30 | val io = IO(new Bundle { 31 | val ctrl = new AxiLite(ADDR_W = 4) 32 | val in_data = Input(UInt(16.W)) 33 | val in_valid = Input(Bool()) 34 | val out_data = Output(UInt(16.W)) 35 | val out_valid = Output(Bool()) 36 | }) 37 | 38 | class DataAndValid extends Bundle { 39 | val data = UInt(16.W) 40 | val valid = Bool() 41 | 42 | def +&(x: UInt): DataAndValid = { 43 | val tmp = Wire(new DataAndValid) 44 | tmp.valid := this.valid 45 | tmp.data := this.data +& x 46 | tmp 47 | } 48 | } 49 | 50 | // axi interface 51 | val axi_ctrl = Module(new PipelineWithAxiLiteSlave) 52 | val coef = Wire(UInt(16.W)) 53 | val nr_samples = Reg(UInt(32.W)) 54 | io.ctrl <> axi_ctrl.io.ctrl 55 | coef := axi_ctrl.io.coef 56 | axi_ctrl.io.stats_nr_samp := nr_samples 57 | 58 | when (io.out_valid) { 59 | nr_samples := nr_samples +& 1.U 60 | } 61 | 62 | val in = Wire(new DataAndValid()) 63 | in.data := io.in_data 64 | in.valid := io.in_valid 65 | 66 | val p0 = RegNext(in) 67 | val p1 = RegNext(p0 +& coef) 68 | 69 | io.out_data := p1.data 70 | io.out_valid := p1.valid 71 | 72 | } 73 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/src/main/scala/axiLiteExample/PipelineWithAxiLiteMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | object PipelineWithAxiLiteMain extends App { 28 | chisel3.Driver.execute( 29 | Array[String]("--target-dir", "outputs") ++ args, 30 | () => new PipelineWithAxiLite) 31 | } 32 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/src/test/scala/axiLiteExample/AxiLiteBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | trait AxiLiteBfm extends ChiselBfm { 28 | val axi: AxiLite 29 | } 30 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/src/test/scala/axiLiteExample/ChiselBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3.Bits 28 | 29 | /** 30 | * Provides needed functions for BFMs (peek, poke, println). 31 | * 32 | * update() gets called every simulation step (every clock cycle). 33 | */ 34 | trait ChiselBfm { 35 | val peek: Bits => BigInt 36 | val poke: (Bits, BigInt) => Unit 37 | val println: String => Unit 38 | 39 | def update(t: Long): Unit 40 | } 41 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/src/test/scala/axiLiteExample/PipelineWithAxiLiteTest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3.iotesters 28 | import chisel3.iotesters.ChiselFlatSpec 29 | 30 | class PipelineWithAxiLiteTest extends ChiselFlatSpec { 31 | "pipeline tester" should "compare expected and obtained response" in { 32 | iotesters.Driver.execute(Array("--backend-name", "verilator", "--fint-write-vcd"), 33 | () => new PipelineWithAxiLite) { 34 | c => new PipelineWithAxiLiteTester(c) 35 | } should be(true) 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/src/test/scala/axiLiteExample/ValidIfBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3.{Bool, UInt} 28 | 29 | /** 30 | * BFM for interface with data and valid (no backpressure = no ready) 31 | */ 32 | trait ValidIfBfm extends ChiselBfm { 33 | val data: UInt 34 | val valid: Bool 35 | } 36 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/src/test/scala/axiLiteExample/ValidIfDriver.scala: -------------------------------------------------------------------------------- 1 | package axiLiteExample 2 | 3 | /* 4 | MIT License 5 | 6 | Copyright (c) 2018 Jan Marjanovic 7 | 8 | Permission is hereby granted, free of charge, to any person obtaining a copy 9 | of this software and associated documentation files (the "Software"), to deal 10 | in the Software without restriction, including without limitation the rights 11 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 | copies of the Software, and to permit persons to whom the Software is 13 | furnished to do so, subject to the following conditions: 14 | 15 | The above copyright notice and this permission notice shall be included in all 16 | copies or substantial portions of the Software. 17 | 18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 24 | SOFTWARE. 25 | */ 26 | 27 | import chisel3.{Bits, Bool, UInt} 28 | 29 | import scala.collection.mutable.ListBuffer 30 | 31 | /** 32 | * Driver for data+valid interface - drives everything which gets appended 33 | * to stimulus on the interface 34 | */ 35 | class ValidIfDriver(val data: UInt, 36 | val valid: Bool, 37 | val peek: Bits => BigInt, 38 | val poke: (Bits, BigInt) => Unit, 39 | val println: String => Unit) extends ValidIfBfm{ 40 | private var stim = ListBuffer[BigInt]() 41 | 42 | def stimAppend(x: BigInt): Unit = { 43 | stim += x 44 | } 45 | 46 | def stimAppend(ls: List[BigInt]): Unit = { 47 | stim ++= ls 48 | } 49 | 50 | private def printWithBg(s: String): Unit = { 51 | // black on orange 52 | println("\u001b[30;48;5;166m" + s + "\u001b[39;49m") 53 | } 54 | 55 | def update(t: Long): Unit = { 56 | if (stim.nonEmpty) { 57 | poke(valid, 1) 58 | val d = stim.remove(0) 59 | poke(data, d) 60 | printWithBg(f"${t}%5d Driver: sent ${d}") 61 | } else { 62 | poke(valid, 0) 63 | } 64 | } 65 | } 66 | -------------------------------------------------------------------------------- /example-2-axi-lite-if/src/test/scala/axiLiteExample/ValidIfMonitor.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3.{Bits, Bool, UInt} 28 | 29 | import scala.collection.mutable.ListBuffer 30 | 31 | /** 32 | * Monitor for data+valid interface - stores all received data in internal list 33 | */ 34 | class ValidIfMonitor(val data: UInt, 35 | val valid: Bool, 36 | val peek: Bits => BigInt, 37 | val poke: (Bits, BigInt) => Unit, 38 | val println: String => Unit) extends ValidIfBfm { 39 | private var resp = ListBuffer[BigInt]() 40 | 41 | def respGet(): List[BigInt] = { 42 | val ls = resp.result() 43 | resp.clear() 44 | ls 45 | } 46 | 47 | private def printWithBg(s: String): Unit = { 48 | // dark blue on light gray 49 | println("\u001b[38;5;18;47m" + s + "\u001b[39;49m") 50 | } 51 | 52 | def update(t: Long): Unit = { 53 | val vld = peek(valid) 54 | if (vld != 0) { 55 | val d = peek(data) 56 | resp += d 57 | printWithBg(f"${t}%5d Monitor: received ${d}") 58 | } 59 | } 60 | } 61 | -------------------------------------------------------------------------------- /example-3-vivado-ip/README.md: -------------------------------------------------------------------------------- 1 | # Example 3: AXI-Lite component as Vivado IP 2 | -------------------------------------------------------------------------------- /example-3-vivado-ip/build.sbt: -------------------------------------------------------------------------------- 1 | def scalacOptionsVersion(scalaVersion: String): Seq[String] = { 2 | Seq() ++ { 3 | // If we're building with Scala > 2.11, enable the compile option 4 | // switch to support our anonymous Bundle definitions: 5 | // https://github.com/scala/bug/issues/10047 6 | CrossVersion.partialVersion(scalaVersion) match { 7 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq() 8 | case _ => Seq("-Xsource:2.11") 9 | } 10 | } 11 | } 12 | 13 | def javacOptionsVersion(scalaVersion: String): Seq[String] = { 14 | Seq() ++ { 15 | // Scala 2.12 requires Java 8. We continue to generate 16 | // Java 7 compatible code for Scala 2.11 17 | // for compatibility with old clients. 18 | CrossVersion.partialVersion(scalaVersion) match { 19 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => 20 | Seq("-source", "1.7", "-target", "1.7") 21 | case _ => 22 | Seq("-source", "1.8", "-target", "1.8") 23 | } 24 | } 25 | } 26 | 27 | name := "chisel-vivado-ip" 28 | 29 | version := "1.0.0" 30 | 31 | scalaVersion := "2.11.12" 32 | 33 | crossScalaVersions := Seq("2.11.12", "2.12.4") 34 | 35 | resolvers ++= Seq( 36 | Resolver.sonatypeRepo("snapshots"), 37 | Resolver.sonatypeRepo("releases") 38 | ) 39 | 40 | // Provide a managed dependency on X if -DXVersion="" is supplied on the command line. 41 | val defaultVersions = Map( 42 | "chisel3" -> "3.1.+", 43 | "chisel-iotesters" -> "1.2.+" 44 | ) 45 | 46 | libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map { 47 | dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }) 48 | 49 | scalacOptions ++= scalacOptionsVersion(scalaVersion.value) 50 | 51 | javacOptions ++= javacOptionsVersion(scalaVersion.value) 52 | -------------------------------------------------------------------------------- /example-3-vivado-ip/ip_cores/pipeline_with_axi/misc/chisel_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-3-vivado-ip/ip_cores/pipeline_with_axi/misc/chisel_logo.png -------------------------------------------------------------------------------- /example-3-vivado-ip/ip_cores/pipeline_with_axi/xgui/PipelineWithAxiLite_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-3-vivado-ip/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.1.1 2 | -------------------------------------------------------------------------------- /example-3-vivado-ip/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn -------------------------------------------------------------------------------- /example-3-vivado-ip/src/main/scala/axiLiteExample/AxiLite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3._ 28 | import chisel3.util.Irrevocable 29 | 30 | class AxiLite(val ADDR_W: Int, val DATA_W: Int = 32) extends Bundle { 31 | val AW = Flipped(Irrevocable(UInt(ADDR_W.W))) 32 | val W = Flipped(Irrevocable(new Bundle { 33 | val wdata = UInt(DATA_W.W) 34 | val wstrb = UInt((DATA_W / 8).W) 35 | })) 36 | val B = Irrevocable(UInt(2.W)) 37 | val AR = Flipped(Irrevocable(UInt(ADDR_W.W))) 38 | val R = Irrevocable(new Bundle { 39 | val rdata = UInt(DATA_W.W); val rresp = UInt(2.W) 40 | }) 41 | } 42 | -------------------------------------------------------------------------------- /example-3-vivado-ip/src/main/scala/axiLiteExample/PipelineWithAxiLite.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3._ 28 | 29 | class PipelineWithAxiLite extends Module { 30 | val io = IO(new Bundle { 31 | val ctrl = new AxiLite(ADDR_W = 4) 32 | val in_data = Input(UInt(16.W)) 33 | val in_valid = Input(Bool()) 34 | val out_data = Output(UInt(16.W)) 35 | val out_valid = Output(Bool()) 36 | }) 37 | 38 | class DataAndValid extends Bundle { 39 | val data = UInt(16.W) 40 | val valid = Bool() 41 | 42 | def +&(x: UInt): DataAndValid = { 43 | val tmp = Wire(new DataAndValid) 44 | tmp.valid := this.valid 45 | tmp.data := this.data +& x 46 | tmp 47 | } 48 | } 49 | 50 | // axi interface 51 | val axi_ctrl = Module(new PipelineWithAxiLiteSlave) 52 | val coef = Wire(UInt(16.W)) 53 | val nr_samples = RegInit(UInt(32.W), 0.U) 54 | io.ctrl <> axi_ctrl.io.ctrl 55 | coef := axi_ctrl.io.coef 56 | axi_ctrl.io.stats_nr_samp := nr_samples 57 | 58 | when (io.out_valid) { 59 | nr_samples := nr_samples +& 1.U 60 | } 61 | 62 | val in = Wire(new DataAndValid()) 63 | in.data := io.in_data 64 | in.valid := io.in_valid 65 | 66 | val p0 = RegNext(in) 67 | val p1 = RegNext(p0 +& coef) 68 | 69 | io.out_data := p1.data 70 | io.out_valid := p1.valid 71 | 72 | } 73 | -------------------------------------------------------------------------------- /example-3-vivado-ip/src/main/scala/axiLiteExample/PipelineWithAxiLiteMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | object PipelineWithAxiLiteMain extends App { 28 | chisel3.Driver.execute( 29 | Array[String]("--target-dir", "ip_cores/pipeline_with_axi/hdl") ++ args, 30 | () => new PipelineWithAxiLite) 31 | } 32 | -------------------------------------------------------------------------------- /example-3-vivado-ip/src/test/scala/axiLiteExample/AxiLiteBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | trait AxiLiteBfm extends ChiselBfm { 28 | val axi: AxiLite 29 | } 30 | -------------------------------------------------------------------------------- /example-3-vivado-ip/src/test/scala/axiLiteExample/ChiselBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3.Bits 28 | 29 | /** 30 | * Provides needed functions for BFMs (peek, poke, println). 31 | * 32 | * update() gets called every simulation step (every clock cycle). 33 | */ 34 | trait ChiselBfm { 35 | val peek: Bits => BigInt 36 | val poke: (Bits, BigInt) => Unit 37 | val println: String => Unit 38 | 39 | def update(t: Long): Unit 40 | } 41 | -------------------------------------------------------------------------------- /example-3-vivado-ip/src/test/scala/axiLiteExample/PipelineWithAxiLiteTest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3.iotesters 28 | import chisel3.iotesters.ChiselFlatSpec 29 | 30 | class PipelineWithAxiLiteTest extends ChiselFlatSpec { 31 | "pipeline tester" should "compare expected and obtained response" in { 32 | iotesters.Driver.execute(Array("--backend-name", "verilator", "--fint-write-vcd"), 33 | () => new PipelineWithAxiLite) { 34 | c => new PipelineWithAxiLiteTester(c) 35 | } should be(true) 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /example-3-vivado-ip/src/test/scala/axiLiteExample/ValidIfBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3.{Bool, UInt} 28 | 29 | /** 30 | * BFM for interface with data and valid (no backpressure = no ready) 31 | */ 32 | trait ValidIfBfm extends ChiselBfm { 33 | val data: UInt 34 | val valid: Bool 35 | } 36 | -------------------------------------------------------------------------------- /example-3-vivado-ip/src/test/scala/axiLiteExample/ValidIfDriver.scala: -------------------------------------------------------------------------------- 1 | package axiLiteExample 2 | 3 | /* 4 | MIT License 5 | 6 | Copyright (c) 2018 Jan Marjanovic 7 | 8 | Permission is hereby granted, free of charge, to any person obtaining a copy 9 | of this software and associated documentation files (the "Software"), to deal 10 | in the Software without restriction, including without limitation the rights 11 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 | copies of the Software, and to permit persons to whom the Software is 13 | furnished to do so, subject to the following conditions: 14 | 15 | The above copyright notice and this permission notice shall be included in all 16 | copies or substantial portions of the Software. 17 | 18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 24 | SOFTWARE. 25 | */ 26 | 27 | import chisel3.{Bits, Bool, UInt} 28 | 29 | import scala.collection.mutable.ListBuffer 30 | 31 | /** 32 | * Driver for data+valid interface - drives everything which gets appended 33 | * to stimulus on the interface 34 | */ 35 | class ValidIfDriver(val data: UInt, 36 | val valid: Bool, 37 | val peek: Bits => BigInt, 38 | val poke: (Bits, BigInt) => Unit, 39 | val println: String => Unit) extends ValidIfBfm{ 40 | private var stim = ListBuffer[BigInt]() 41 | 42 | def stimAppend(x: BigInt): Unit = { 43 | stim += x 44 | } 45 | 46 | def stimAppend(ls: List[BigInt]): Unit = { 47 | stim ++= ls 48 | } 49 | 50 | private def printWithBg(s: String): Unit = { 51 | // black on orange 52 | println("\u001b[30;48;5;166m" + s + "\u001b[39;49m") 53 | } 54 | 55 | def update(t: Long): Unit = { 56 | if (stim.nonEmpty) { 57 | poke(valid, 1) 58 | val d = stim.remove(0) 59 | poke(data, d) 60 | printWithBg(f"${t}%5d Driver: sent ${d}") 61 | } else { 62 | poke(valid, 0) 63 | } 64 | } 65 | } 66 | -------------------------------------------------------------------------------- /example-3-vivado-ip/src/test/scala/axiLiteExample/ValidIfMonitor.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package axiLiteExample 26 | 27 | import chisel3.{Bits, Bool, UInt} 28 | 29 | import scala.collection.mutable.ListBuffer 30 | 31 | /** 32 | * Monitor for data+valid interface - stores all received data in internal list 33 | */ 34 | class ValidIfMonitor(val data: UInt, 35 | val valid: Bool, 36 | val peek: Bits => BigInt, 37 | val poke: (Bits, BigInt) => Unit, 38 | val println: String => Unit) extends ValidIfBfm { 39 | private var resp = ListBuffer[BigInt]() 40 | 41 | def respGet(): List[BigInt] = { 42 | val ls = resp.result() 43 | resp.clear() 44 | ls 45 | } 46 | 47 | private def printWithBg(s: String): Unit = { 48 | // dark blue on light gray 49 | println("\u001b[38;5;18;47m" + s + "\u001b[39;49m") 50 | } 51 | 52 | def update(t: Long): Unit = { 53 | val vld = peek(valid) 54 | if (vld != 0) { 55 | val d = peek(data) 56 | resp += d 57 | printWithBg(f"${t}%5d Monitor: received ${d}") 58 | } 59 | } 60 | } 61 | -------------------------------------------------------------------------------- /example-3-vivado-ip/uvvm/sim/.gitignore: -------------------------------------------------------------------------------- 1 | 2 | # gets generated autmatically by compile.do 3 | modelsim.ini 4 | -------------------------------------------------------------------------------- /example-3-vivado-ip/uvvm/sim/compile.do: -------------------------------------------------------------------------------- 1 | 2 | 3 | # check if UVVM_PATH is defined in environment 4 | # otherwise assume UVVM is installed in $HOME dir 5 | # this should point to the top directory for UVVM 6 | 7 | if {[info exists ::env(UVVM_PATH)]} { 8 | puts "UVVM_PATH: using environment" 9 | set UVVM_PATH $env(UVVM_PATH) 10 | } else { 11 | puts "UVVM_PATH: using default" 12 | set UVVM_PATH $env(HOME)/FPGA/UVVM/UVVM 13 | } 14 | 15 | puts "UVVM_PATH set to $UVVM_PATH" 16 | 17 | 18 | ## compile 19 | 20 | # UVVM utils 21 | set lib_name "uvvm_util" 22 | do $UVVM_PATH/$lib_name/script/compile_src.do $UVVM_PATH/$lib_name 23 | 24 | # VVC framework 25 | set lib_name "uvvm_vvc_framework" 26 | do $UVVM_PATH/$lib_name/script/compile_src.do $UVVM_PATH/$lib_name 27 | 28 | # BFM: axi lite 29 | set lib_name "bitvis_vip_axilite" 30 | do $UVVM_PATH/$lib_name/script/compile_src.do $UVVM_PATH/$lib_name 31 | 32 | # BFM: axi stream 33 | set lib_name "bitvis_vip_axistream" 34 | do $UVVM_PATH/$lib_name/script/compile_src.do $UVVM_PATH/$lib_name 35 | -------------------------------------------------------------------------------- /example-3-vivado-ip/uvvm/sim/sim.do: -------------------------------------------------------------------------------- 1 | 2 | 3 | if {[file exists work]} { 4 | vdel -lib work -all 5 | } 6 | 7 | vlib work 8 | 9 | vlog -work work ../../ip_cores/pipeline_with_axi/hdl/PipelineWithAxiLite.v 10 | vcom -work work -2008 ../hdl/pipelinewithaxilite_th.vhd 11 | vcom -work work -2008 ../hdl/pipelinewithaxilite_tb.vhd 12 | 13 | vsim work.pipelinewithaxilite_tb 14 | 15 | 16 | # 17 | add wave -divider "Clock and reset" 18 | add wave \ 19 | sim:/pipelinewithaxilite_tb/i_test_harness/clock \ 20 | sim:/pipelinewithaxilite_tb/i_test_harness/reset 21 | 22 | add wave -divider "AXI4-Lite slave" 23 | add wave -radix hex \ 24 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_AWREADY \ 25 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_AWVALID \ 26 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_AWADDR \ 27 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_WREADY \ 28 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_WVALID \ 29 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_WDATA \ 30 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_WSTRB \ 31 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_BREADY \ 32 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_BVALID \ 33 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_BRESP \ 34 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_ARREADY \ 35 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_ARVALID \ 36 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_ARADDR \ 37 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_RREADY \ 38 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_RVALID \ 39 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_RDATA \ 40 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXI_RRESP 41 | 42 | add wave -divider "AXI4-Stream input" 43 | add wave -radix hex \ 44 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXIS_IN_TDATA \ 45 | sim:/pipelinewithaxilite_tb/i_test_harness/S_AXIS_IN_TVALID 46 | 47 | add wave -divider "AXI4-Stream output" 48 | add wave -radix hex \ 49 | sim:/pipelinewithaxilite_tb/i_test_harness/M_AXIS_OUT_TDATA \ 50 | sim:/pipelinewithaxilite_tb/i_test_harness/M_AXIS_OUT_TVALID 51 | 52 | run -all 53 | 54 | wave zoom full 55 | -------------------------------------------------------------------------------- /example-3-vivado-ip/vivado_tb_project/README.md: -------------------------------------------------------------------------------- 1 | # Testbench for Vivado 2 | 3 | This project instantiates DUT (Chisel module) and (Bus Functional Models) BFMs 4 | for AXI4-Lite and and AXI4-Stream interfaces on DUT. A testbench reads and 5 | writes to internal registers, feeds the DUT with stimuli and captures its 6 | response. At the end the response of the DUT is compared with the expected 7 | values. 8 | 9 | ## Usage 10 | 11 | ### Recreating project: 12 | 13 | In folder `/project/` run: 14 | 15 | ```tcl 16 | source ../script/main.tcl 17 | ``` 18 | 19 | ### Committing changes to BD 20 | 21 | In folder `/project/` run: 22 | 23 | ```tcl 24 | write_bd_tcl -include_layout -force ../scripts/_gen_bd.tcl 25 | ``` 26 | 27 | ### Commiting changes to project 28 | 29 | In folder `/project/` run. Be careful when committing the file to Git, 30 | as there are some manual changes made to this file. The manual changes should 31 | not be overwritten. 32 | 33 | ```tcl 34 | write_project_tcl -use_bd_files -force ../scripts/_project.tcl 35 | ``` -------------------------------------------------------------------------------- /example-3-vivado-ip/vivado_tb_project/project/PLACEHOLDER.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-3-vivado-ip/vivado_tb_project/project/PLACEHOLDER.txt -------------------------------------------------------------------------------- /example-3-vivado-ip/vivado_tb_project/scripts/main.tcl: -------------------------------------------------------------------------------- 1 | 2 | # recreate the project from the start 3 | proc prj_init {args} { 4 | set origin_dir "." 5 | 6 | source [file normalize "$origin_dir/../scripts/_project.tcl"] 7 | source [file normalize "$origin_dir/../scripts/_gen_bd.tcl"] 8 | } 9 | 10 | prj_init 11 | -------------------------------------------------------------------------------- /example-4-ord-decoupled-io-tester/build.sbt: -------------------------------------------------------------------------------- 1 | // See README.md for license details. 2 | 3 | def scalacOptionsVersion(scalaVersion: String): Seq[String] = { 4 | Seq() ++ { 5 | // If we're building with Scala > 2.11, enable the compile option 6 | // switch to support our anonymous Bundle definitions: 7 | // https://github.com/scala/bug/issues/10047 8 | CrossVersion.partialVersion(scalaVersion) match { 9 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq() 10 | case _ => Seq("-Xsource:2.11") 11 | } 12 | } 13 | } 14 | 15 | def javacOptionsVersion(scalaVersion: String): Seq[String] = { 16 | Seq() ++ { 17 | // Scala 2.12 requires Java 8. We continue to generate 18 | // Java 7 compatible code for Scala 2.11 19 | // for compatibility with old clients. 20 | CrossVersion.partialVersion(scalaVersion) match { 21 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => 22 | Seq("-source", "1.7", "-target", "1.7") 23 | case _ => 24 | Seq("-source", "1.8", "-target", "1.8") 25 | } 26 | } 27 | } 28 | 29 | name := "chisel-example-ord-decoup-io" 30 | 31 | version := "0.1.0" 32 | 33 | scalaVersion := "2.11.12" 34 | 35 | crossScalaVersions := Seq("2.11.12", "2.12.4") 36 | 37 | resolvers ++= Seq( 38 | Resolver.sonatypeRepo("snapshots"), 39 | Resolver.sonatypeRepo("releases") 40 | ) 41 | 42 | // Provide a managed dependency on X if -DXVersion="" is supplied on the command line. 43 | val defaultVersions = Map( 44 | "chisel3" -> "3.1.+", 45 | "chisel-iotesters" -> "1.2.+" 46 | ) 47 | 48 | libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map { 49 | dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }) 50 | 51 | scalacOptions ++= scalacOptionsVersion(scalaVersion.value) 52 | 53 | javacOptions ++= javacOptionsVersion(scalaVersion.value) 54 | -------------------------------------------------------------------------------- /example-4-ord-decoupled-io-tester/src/test/scala/ord_decoup_io/OrdDecoupIoTest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package ord_decoup_io 26 | 27 | import chisel3.iotesters.ChiselFlatSpec 28 | 29 | class OrdDecoupIoTest extends ChiselFlatSpec { 30 | 31 | val c_pkg = chisel3.Module.getClass.getPackage() 32 | println(s"${c_pkg.getSpecificationTitle} version ${c_pkg.getSpecificationVersion}") 33 | 34 | val t_pkg = chisel3.iotesters.Driver.getClass.getPackage() 35 | println(s"${t_pkg.getSpecificationTitle} version ${t_pkg.getSpecificationVersion}") 36 | 37 | "Ord Decoup Io tester" should "compare expected and obtained response" in { 38 | assertTesterPasses { new OrdDecoupIoTester } 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /example-4-ord-decoupled-io-tester/src/test/scala/ord_decoup_io/OrdDecoupIoTester.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package ord_decoup_io 26 | 27 | import chisel3._ 28 | import chisel3.iotesters.{OrderedDecoupledHWIOTester} 29 | 30 | 31 | class OrdDecoupIoTester extends OrderedDecoupledHWIOTester { 32 | val device_under_test = Module(new OrdDecoupIo) 33 | val c = device_under_test 34 | enable_all_debug = true 35 | 36 | OrderedDecoupledHWIOTester.max_tick_count = 10 37 | 38 | inputEvent(c.io.data_in.bits -> 1) 39 | outputEvent(c.io.data_out.bits -> 2) 40 | outputEvent(c.io.data_out.bits -> 3) 41 | 42 | inputEvent(c.io.data_in.bits -> 5) 43 | outputEvent(c.io.data_out.bits -> 6) 44 | outputEvent(c.io.data_out.bits -> 7) 45 | 46 | inputEvent(c.io.data_in.bits -> 10) 47 | outputEvent(c.io.data_out.bits -> 11) 48 | outputEvent(c.io.data_out.bits -> 12) 49 | } 50 | -------------------------------------------------------------------------------- /example-4-ord-decoupled-io-tester/tester_waveform.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-4-ord-decoupled-io-tester/tester_waveform.png -------------------------------------------------------------------------------- /example-5-gunzip/build.sbt: -------------------------------------------------------------------------------- 1 | // See README.md for license details. 2 | 3 | def scalacOptionsVersion(scalaVersion: String): Seq[String] = { 4 | Seq() ++ { 5 | // If we're building with Scala > 2.11, enable the compile option 6 | // switch to support our anonymous Bundle definitions: 7 | // https://github.com/scala/bug/issues/10047 8 | CrossVersion.partialVersion(scalaVersion) match { 9 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq() 10 | case _ => Seq("-Xsource:2.11") 11 | } 12 | } 13 | } 14 | 15 | def javacOptionsVersion(scalaVersion: String): Seq[String] = { 16 | Seq() ++ { 17 | // Scala 2.12 requires Java 8. We continue to generate 18 | // Java 7 compatible code for Scala 2.11 19 | // for compatibility with old clients. 20 | CrossVersion.partialVersion(scalaVersion) match { 21 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => 22 | Seq("-source", "1.7", "-target", "1.7") 23 | case _ => 24 | Seq("-source", "1.8", "-target", "1.8") 25 | } 26 | } 27 | } 28 | 29 | name := "chisel-gunzip" 30 | 31 | version := "0.1.0" 32 | 33 | scalaVersion := "2.11.12" 34 | 35 | crossScalaVersions := Seq("2.11.12", "2.12.4") 36 | 37 | resolvers ++= Seq( 38 | Resolver.sonatypeRepo("snapshots"), 39 | Resolver.sonatypeRepo("releases") 40 | ) 41 | 42 | // Provide a managed dependency on X if -DXVersion="" is supplied on the command line. 43 | val defaultVersions = Map( 44 | "chisel3" -> "3.1.+", 45 | "chisel-iotesters" -> "1.2.+" 46 | ) 47 | 48 | libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map { 49 | dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }) 50 | 51 | scalacOptions ++= scalacOptionsVersion(scalaVersion.value) 52 | 53 | javacOptions ++= javacOptionsVersion(scalaVersion.value) 54 | -------------------------------------------------------------------------------- /example-5-gunzip/ip_cores/byte2bit/xgui/ByteStreamToBitStream_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-5-gunzip/ip_cores/byte2bit/xgui/byte2bit_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-5-gunzip/ip_cores/gunzip/xdc/gunzip_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | create_clock -period 5.000 -name clock [get_ports clock] 3 | 4 | set_input_delay -clock [get_clocks clock] -min -add_delay 0.100 [get_ports reset] 5 | set_input_delay -clock [get_clocks clock] -max -add_delay 2.500 [get_ports reset] 6 | 7 | set_output_delay -clock [get_clocks clock] -min -add_delay 0.100 [get_ports io_data_in_ready] 8 | set_output_delay -clock [get_clocks clock] -max -add_delay 2.000 [get_ports io_data_in_ready] 9 | 10 | set_input_delay -clock [get_clocks clock] -min -add_delay 0.100 [get_ports io_data_in_valid] 11 | set_input_delay -clock [get_clocks clock] -max -add_delay 2.000 [get_ports io_data_in_valid] 12 | 13 | set_input_delay -clock [get_clocks clock] -min -add_delay 0.100 [get_ports io_data_in_bits] 14 | set_input_delay -clock [get_clocks clock] -max -add_delay 2.500 [get_ports io_data_in_bits] 15 | 16 | set_input_delay -clock [get_clocks clock] -min -add_delay 0.100 [get_ports io_data_out_ready] 17 | set_input_delay -clock [get_clocks clock] -max -add_delay 2.500 [get_ports io_data_out_ready] 18 | 19 | set_output_delay -clock [get_clocks clock] -min -add_delay 0.100 [get_ports io_data_out_valid] 20 | set_output_delay -clock [get_clocks clock] -max -add_delay 2.500 [get_ports io_data_out_valid] 21 | 22 | set_output_delay -clock [get_clocks clock] -min -add_delay 0.100 [get_ports {io_data_out_bits_data[*]}] 23 | set_output_delay -clock [get_clocks clock] -max -add_delay 2.500 [get_ports {io_data_out_bits_data[*]}] 24 | 25 | set_output_delay -clock [get_clocks clock] -min -add_delay 0.100 [get_ports io_data_out_bits_last] 26 | set_output_delay -clock [get_clocks clock] -max -add_delay 2.500 [get_ports io_data_out_bits_last] 27 | -------------------------------------------------------------------------------- /example-5-gunzip/ip_cores/gunzip/xgui/GunzipEngine_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-5-gunzip/ip_cores/gunzip/xgui/gunzip_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /example-5-gunzip/src/main/resources/in.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-5-gunzip/src/main/resources/in.tar.gz -------------------------------------------------------------------------------- /example-5-gunzip/src/main/scala/gunzip/BitStream.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | import scala.collection.mutable 28 | import scala.collection.mutable.ListBuffer 29 | 30 | class BitStream(val bytes: List[Byte]) { 31 | private def bytesToBits(bytes: List[Byte]): List[Int] = { 32 | val bits = ListBuffer[Int]() 33 | 34 | for (byt <- bytes) { 35 | for (i <- 0 to 7) { 36 | bits += (byt & (1 << i)) >> i 37 | } 38 | } 39 | 40 | bits.toList 41 | } 42 | 43 | val in_bits = bytesToBits(bytes) 44 | val xs: mutable.Queue[Int] = mutable.Queue[Int]() 45 | xs ++= in_bits 46 | 47 | var bits_read : Int = 0 48 | 49 | def getBits(len: Int): Int = { 50 | var accum : Int = 0 51 | bits_read += len 52 | for (i <- 0 until len) { 53 | accum |= xs.dequeue() << i 54 | } 55 | accum 56 | } 57 | 58 | } 59 | -------------------------------------------------------------------------------- /example-5-gunzip/src/main/scala/gunzip/ByteStreamToBitStream.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | import chisel3._ 28 | import chisel3.util._ 29 | 30 | class ByteStreamToBitStream extends Module { 31 | val io = IO(new Bundle { 32 | val data_in = DeqIO(UInt(8.W)) 33 | val data_out = EnqIO(UInt(8.W)) 34 | }) 35 | 36 | val sel = RegInit(0.U(4.W)) 37 | 38 | io.data_in.ready := sel === 0.U 39 | io.data_out.valid := sel =/= 0.U 40 | 41 | when (sel =/= 0.U && io.data_out.ready) { 42 | when (sel === 8.U) { 43 | sel := 0.U 44 | } .otherwise { 45 | sel := sel + 1.U 46 | } 47 | } .elsewhen (sel === 0.U && io.data_in.valid) { 48 | sel := 1.U 49 | } 50 | 51 | val data_reg = Reg(UInt()) 52 | 53 | when (sel === 0.U && io.data_in.valid) { 54 | data_reg := io.data_in.bits 55 | } 56 | 57 | io.data_out.bits := data_reg(sel - 1.U) 58 | 59 | } 60 | -------------------------------------------------------------------------------- /example-5-gunzip/src/main/scala/gunzip/GunzipBitSkipper.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | import chisel3._ 28 | import chisel3.util._ 29 | 30 | 31 | /** an FPGA equivalent of /dev/null, but with limited length 32 | * 33 | * @param initial_bit_skip bits to skip before done 34 | */ 35 | class GunzipBitSkipper(val initial_bit_skip: Int) extends Module { 36 | val io = IO(new Bundle { 37 | val data_in_valid = Input(Bool()) 38 | val data_in_ready = Output(Bool()) 39 | val done = Output(Bool()) 40 | }) 41 | 42 | val BIT_CNTR_W = log2Ceil(initial_bit_skip + 1) 43 | val bit_cntr = RegInit(0.U(BIT_CNTR_W.W)) 44 | 45 | when (io.data_in_ready && io.data_in_valid && bit_cntr < initial_bit_skip.U) { 46 | bit_cntr := bit_cntr + 1.U 47 | } 48 | 49 | io.done := bit_cntr === initial_bit_skip.U 50 | io.data_in_ready := bit_cntr =/= initial_bit_skip.U 51 | } 52 | -------------------------------------------------------------------------------- /example-5-gunzip/src/main/scala/gunzip/GunzipHuffDecoderElem.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | import chisel3._ 28 | 29 | class GunzipHuffDecoderElem extends Bundle { 30 | val valid = Bool() 31 | val data = UInt(9.W) 32 | } 33 | -------------------------------------------------------------------------------- /example-5-gunzip/src/main/scala/gunzip/GunzipMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | 28 | object GunzipMain extends App { 29 | chisel3.Driver.execute( 30 | Array[String]("--target-dir", "ip_cores/gunzip/hdl") ++ args, 31 | () => new GunzipEngine(getClass.getResource("/in.tar.gz"))) 32 | 33 | chisel3.Driver.execute( 34 | Array[String]("--target-dir", "ip_cores/byte2bit/hdl") ++ args, 35 | () => new ByteStreamToBitStream()) 36 | 37 | } 38 | -------------------------------------------------------------------------------- /example-5-gunzip/src/main/scala/gunzip/GunzipOutput.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | import chisel3._ 28 | 29 | class GunzipOutput extends Bundle { 30 | val data = UInt(8.W) 31 | val last = Bool() 32 | } 33 | -------------------------------------------------------------------------------- /example-5-gunzip/src/main/scala/gunzip/HuffmanCode.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | class HuffmanCode(val code: Int, val length: Int) { 28 | override def toString: String = s"HuffmanCode(${code}, ${length})" 29 | } 30 | -------------------------------------------------------------------------------- /example-5-gunzip/src/test/scala/gunzip/ChiselBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | import chisel3.Bits 28 | 29 | /** 30 | * Provides needed functions for BFMs (peek, poke, println). 31 | * 32 | * update() gets called every simulation step (every clock cycle). 33 | */ 34 | trait ChiselBfm { 35 | val peek: Bits => BigInt 36 | val poke: (Bits, BigInt) => Unit 37 | val println: String => Unit 38 | 39 | def update(t: Long): Unit 40 | } 41 | -------------------------------------------------------------------------------- /example-5-gunzip/src/test/scala/gunzip/DecoupledBfm.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | import chisel3.core.Data 28 | import chisel3.util.DecoupledIO 29 | 30 | /** 31 | * BFM for interface with data and valid (no backpressure = no ready) 32 | */ 33 | trait DecoupledBfm extends ChiselBfm { 34 | val iface: DecoupledIO[Data] 35 | } 36 | -------------------------------------------------------------------------------- /example-5-gunzip/src/test/scala/gunzip/DecoupledMonitor.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | import chisel3.Bits 28 | import chisel3.util.DecoupledIO 29 | 30 | import scala.collection.mutable.ListBuffer 31 | 32 | /** 33 | * Monitor for data+valid interface - stores all received data in internal list 34 | */ 35 | class DecoupledMonitor(val iface: DecoupledIO[GunzipOutput], 36 | val peek: Bits => BigInt, 37 | val poke: (Bits, BigInt) => Unit, 38 | val println: String => Unit) extends DecoupledBfm { 39 | private var resp = ListBuffer[BigInt]() 40 | 41 | private def printWithBg(s: String): Unit = { 42 | // dark blue on light gray 43 | println("\u001b[38;5;18;47m" + s + "\u001b[39;49m") 44 | } 45 | 46 | def respGet(): List[BigInt] = { 47 | val ls = resp.result() 48 | resp.clear() 49 | ls 50 | } 51 | 52 | def update(t: Long): Unit = { 53 | poke(iface.ready, 1) 54 | val vld = peek(iface.valid) 55 | if (vld != 0) { 56 | val d = peek(iface.bits.data) 57 | val last = peek(iface.bits.last) 58 | if (last > 0) { 59 | throw AllDone 60 | } 61 | resp += d 62 | printWithBg(f"${t}%5d Monitor: received ${d}") 63 | } 64 | } 65 | } 66 | -------------------------------------------------------------------------------- /example-5-gunzip/src/test/scala/gunzip/GunzipEngineTest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2018 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package gunzip 26 | 27 | import chisel3.iotesters._ 28 | 29 | class GunzipEngineTest extends ChiselFlatSpec { 30 | 31 | val c_pkg = chisel3.Module.getClass.getPackage() 32 | println(s"${c_pkg.getSpecificationTitle} v ${c_pkg.getSpecificationVersion}") 33 | 34 | val t_pkg = chisel3.iotesters.Driver.getClass.getPackage() 35 | println(s"${t_pkg.getSpecificationTitle} v ${t_pkg.getSpecificationVersion}") 36 | 37 | "Gunzip tester" should "un-gzip a file" in { 38 | Driver.execute(Array("--backend-name", "verilator", "--fint-write-vcd"), 39 | () => new GunzipEngine(getClass.getResource("/in.tar.gz"))) { c => 40 | new GunzipTester(c, getClass.getResource("/in.tar.gz")) 41 | } should be(true) 42 | } 43 | 44 | } 45 | -------------------------------------------------------------------------------- /example-5-gunzip/vivado_tb_project/scripts/_add_files.tcl: -------------------------------------------------------------------------------- 1 | set_property SOURCE_SET sources_1 [get_filesets sim_1] 2 | add_files -fileset sim_1 ../sim/gunzip_system_tb.sv 3 | add_files -fileset sim_1 ../sim/resources/out.tar 4 | add_files -fileset sim_1 ../sim/resources/in.tar.gz 5 | 6 | set_property top gunzip_system_tb [get_filesets sim_1] 7 | -------------------------------------------------------------------------------- /example-5-gunzip/vivado_tb_project/scripts/_create_prj.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_project gunzip_tb . -part xczu3eg-sbva484-1-i 3 | set_property board_part avnet.com:ultra96v2:part0:1.1 [current_project] 4 | 5 | set_property ip_repo_paths ../../ip_cores [current_project] 6 | update_ip_catalog 7 | -------------------------------------------------------------------------------- /example-5-gunzip/vivado_tb_project/scripts/_create_wrapper.tcl: -------------------------------------------------------------------------------- 1 | make_wrapper -files [get_files system.bd] -top 2 | add_files -norecurse /home/jan/FPGA/Chisel/chisel-stuff/example-5-gunzip/vivado_tb_project/project/gunzip_tb.gen/sources_1/bd/system/hdl/system_wrapper.v 3 | -------------------------------------------------------------------------------- /example-5-gunzip/vivado_tb_project/scripts/_run_sim.tcl: -------------------------------------------------------------------------------- 1 | 2 | export_ip_user_files -of_objects [get_files system.bd] -no_script -sync -force -quiet 3 | 4 | export_simulation \ 5 | -of_objects [get_files system.bd] \ 6 | -directory ../project/gunzip_tb.ip_user_files/sim_scripts \ 7 | -ip_user_files_dir ../project/gunzip_tb.ip_user_files \ 8 | -ipstatic_source_dir ../project/gunzip_tb.ip_user_files/ipstatic \ 9 | -lib_map_path [list {modelsim=../project/gunzip_tb.cache/compile_simlib/modelsim} \ 10 | {questa=../project/gunzip_tb.cache/compile_simlib/questa} \ 11 | {ies=../project/gunzip_tb.cache/compile_simlib/ies} \ 12 | {xcelium=../project/gunzip_tb.cache/compile_simlib/xcelium} \ 13 | {vcs=../project/gunzip_tb.cache/compile_simlib/vcs} \ 14 | {riviera=../project/gunzip_tb.cache/compile_simlib/riviera}] \ 15 | -use_ip_compiled_libs -force -quiet 16 | 17 | launch_simulation 18 | 19 | 20 | run 100 us 21 | -------------------------------------------------------------------------------- /example-5-gunzip/vivado_tb_project/scripts/main.tcl: -------------------------------------------------------------------------------- 1 | 2 | source ../scripts/_create_prj.tcl 3 | source ../scripts/_gen_bd.tcl 4 | source ../scripts/_create_wrapper.tcl 5 | source ../scripts/_add_files.tcl 6 | source ../scripts/_run_sim.tcl 7 | -------------------------------------------------------------------------------- /example-5-gunzip/vivado_tb_project/sim/resources/in.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-5-gunzip/vivado_tb_project/sim/resources/in.tar.gz -------------------------------------------------------------------------------- /example-7-fft/.scalafmt.conf: -------------------------------------------------------------------------------- 1 | maxColumn = 100 2 | -------------------------------------------------------------------------------- /example-7-fft/build.sbt: -------------------------------------------------------------------------------- 1 | // See README.md for license details. 2 | 3 | def scalacOptionsVersion(scalaVersion: String): Seq[String] = { 4 | Seq() ++ { 5 | // If we're building with Scala > 2.11, enable the compile option 6 | // switch to support our anonymous Bundle definitions: 7 | // https://github.com/scala/bug/issues/10047 8 | CrossVersion.partialVersion(scalaVersion) match { 9 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq() 10 | case _ => Seq("-Xsource:2.11") 11 | } 12 | } 13 | } 14 | 15 | def javacOptionsVersion(scalaVersion: String): Seq[String] = { 16 | Seq() ++ { 17 | // Scala 2.12 requires Java 8. We continue to generate 18 | // Java 7 compatible code for Scala 2.11 19 | // for compatibility with old clients. 20 | CrossVersion.partialVersion(scalaVersion) match { 21 | case Some((2, scalaMajor: Long)) if scalaMajor < 12 => 22 | Seq("-source", "1.7", "-target", "1.7") 23 | case _ => 24 | Seq("-source", "1.8", "-target", "1.8") 25 | } 26 | } 27 | } 28 | 29 | name := "fft-module" 30 | 31 | version := "0.1.0" 32 | 33 | scalaVersion := "2.12.10" 34 | 35 | crossScalaVersions := Seq("2.12.10", "2.11.12") 36 | 37 | resolvers ++= Seq( 38 | Resolver.sonatypeRepo("snapshots"), 39 | Resolver.sonatypeRepo("releases") 40 | ) 41 | 42 | // Provide a managed dependency on X if -DXVersion="" is supplied on the command line. 43 | val defaultVersions = Map( 44 | "chisel3" -> "3.1.+", 45 | "chisel-iotesters" -> "1.2.+" 46 | ) 47 | 48 | libraryDependencies += "io.j-marjanovic" %% "chisel-bfmtester" % "0.3.1" 49 | libraryDependencies += "org.scalanlp" %% "breeze" % "1.0" 50 | libraryDependencies ++= Seq("chisel3","chisel-iotesters").map { 51 | dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) } 52 | 53 | 54 | scalacOptions ++= scalacOptionsVersion(scalaVersion.value) 55 | 56 | javacOptions ++= javacOptionsVersion(scalaVersion.value) 57 | -------------------------------------------------------------------------------- /example-7-fft/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.3.2 2 | -------------------------------------------------------------------------------- /example-7-fft/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn -------------------------------------------------------------------------------- /example-7-fft/src/main/scala/fft/FftButterfly.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2019 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package fft 26 | 27 | import breeze.math._ 28 | import breeze.numerics._ 29 | import breeze.numerics.constants._ 30 | import chisel3._ 31 | import chisel3.internal.firrtl.{BinaryPoint, Width} 32 | import chisel3.util.ShiftRegister 33 | 34 | class FftButterfly(val w: Width, val bp: BinaryPoint, val k: Int, val N: Int) 35 | extends chisel3.Module { 36 | val io = IO(new Bundle { 37 | val in0 = Input(new ComplexBundle(w, bp)) 38 | val in1 = Input(new ComplexBundle(w, bp)) 39 | val in_vld = Input(Bool()) 40 | val out0 = Output(new ComplexBundle(w, bp)) 41 | val out1 = Output(new ComplexBundle(w, bp)) 42 | val out_vld = Output(Bool()) 43 | }) 44 | 45 | val W: Complex = exp(-1 * i * 2 * Pi * k / N) 46 | 47 | val C_W = Wire(new ComplexBundle(w, bp)) 48 | C_W.re := W.real.F(bp) 49 | C_W.im := W.imag.F(bp) 50 | 51 | val in1_W = RegNext(io.in1 * C_W) 52 | val in0 = ShiftRegister(io.in0, 4) 53 | 54 | val out0 = RegNext(in0 + in1_W) 55 | val out1 = RegNext(in0 - in1_W) 56 | 57 | io.out0 := out0 58 | io.out1 := out1 59 | 60 | val out_vld = ShiftRegister(io.in_vld, 6) 61 | io.out_vld := out_vld 62 | } 63 | -------------------------------------------------------------------------------- /example-7-fft/src/main/scala/fft/InputShuffle.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2019 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package fft 26 | 27 | import chisel3._ 28 | import chisel3.util._ 29 | 30 | class InputShuffle(val n: Int) extends Module { 31 | val io = IO(new Bundle { 32 | val inp = Input(Vec(n, new ComplexBundle(18.W, 16.BP))) 33 | val out = Output(Vec(n, new ComplexBundle(18.W, 16.BP))) 34 | }) 35 | 36 | /// enable printing here 37 | val debug: Boolean = true 38 | 39 | def dbg(s: String) = { 40 | if (debug) { 41 | println("InputShuffle: " + s) 42 | } 43 | } 44 | 45 | val NR_BITS = log2Ceil(n) 46 | dbg(s"NR_BITS = ${NR_BITS}") 47 | 48 | def bit_reverse(x: Int): Int = { 49 | var tmp: Int = 0 50 | for (i <- 0 until NR_BITS) { 51 | tmp |= ((x >> i) & 1) << (NR_BITS - 1 - i) 52 | } 53 | 54 | dbg(f"${x}%2d -> ${tmp}%2d") 55 | 56 | tmp 57 | } 58 | 59 | for (i <- 0 until n) { 60 | io.out(bit_reverse(i)) := io.inp(i) 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /example-7-fft/src/test/scala/fft/ButterflyDriver.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2019 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package fft 26 | 27 | import bfmtester._ 28 | import breeze.math.Complex 29 | import chisel3._ 30 | import chisel3.core.FixedPoint 31 | 32 | import scala.collection.mutable.ListBuffer 33 | 34 | class ButterflyDriver(val in0: ComplexBundle, 35 | val in1: ComplexBundle, 36 | val in_vld: Bool, 37 | val peek: Bits => BigInt, 38 | val poke: (Bits, BigInt) => Unit, 39 | val println: String => Unit) 40 | extends Bfm { 41 | 42 | val stim: ListBuffer[(Complex, Complex)] = ListBuffer() 43 | 44 | override def update(t: Long, poke: (Bits, BigInt) => Unit): Unit = { 45 | if (stim.nonEmpty) { 46 | println(f"${t}%5d Driver: send data") 47 | val el = stim.remove(0) 48 | 49 | poke(in0.re, FixedPoint.toBigInt(el._1.real, 16)) 50 | poke(in0.im, FixedPoint.toBigInt(el._1.imag, 16)) 51 | poke(in1.re, FixedPoint.toBigInt(el._2.real, 16)) 52 | poke(in1.im, FixedPoint.toBigInt(el._2.imag, 16)) 53 | poke(in_vld, 1) 54 | } else { 55 | poke(in0.re, 0) 56 | poke(in0.im, 0) 57 | poke(in1.re, 0) 58 | poke(in1.im, 0) 59 | poke(in_vld, 0) 60 | } 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /example-7-fft/src/test/scala/fft/ButterflyMonitor.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2019 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package fft 26 | 27 | import bfmtester._ 28 | import breeze.math._ 29 | import chisel3._ 30 | import chisel3.core.FixedPoint 31 | 32 | import scala.collection.mutable.ListBuffer 33 | 34 | class ButterflyMonitor(val out0: ComplexBundle, 35 | val out1: ComplexBundle, 36 | val out_vld: Bool, 37 | val peek: Bits => BigInt, 38 | val poke: (Bits, BigInt) => Unit, 39 | val println: String => Unit) 40 | extends Bfm { 41 | 42 | val resp: ListBuffer[(Complex, Complex)] = ListBuffer() 43 | 44 | override def update(t: Long, poke: (Bits, BigInt) => Unit): Unit = { 45 | val vld = peek(out_vld) 46 | if (vld != 0) { 47 | println(f"${t}%5d Monitor: received data") 48 | val out0_re = FixedPoint.toDouble(peek(out0.re), 16) 49 | val out0_im = FixedPoint.toDouble(peek(out0.im), 16) 50 | val out1_re = FixedPoint.toDouble(peek(out1.re), 16) 51 | val out1_im = FixedPoint.toDouble(peek(out1.im), 16) 52 | resp += Tuple2(out0_re + out0_im * i, out1_re + out1_im * i) 53 | } 54 | } 55 | } 56 | -------------------------------------------------------------------------------- /example-7-fft/src/test/scala/fft/InputShuffleTester.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2019 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | package fft 26 | 27 | import chisel3.iotesters._ 28 | 29 | class InputShuffleTester(c: InputShuffle) extends PeekPokeTester(c) { 30 | 31 | assert(c.n == 8, "very simple test, only for 1 size") 32 | 33 | for (i <- 0 until c.n) { 34 | poke(c.io.inp(i).re, i) 35 | poke(c.io.inp(i).im, i) 36 | } 37 | 38 | step(1) 39 | 40 | val expect_vec_8: List[Int] = List( 41 | 0, 4, 2, 6, 1, 5, 3, 7 42 | ) 43 | 44 | for (i <- 0 until c.n) { 45 | expect(c.io.out(i).re, expect_vec_8(i)) 46 | expect(c.io.out(i).im, expect_vec_8(i)) 47 | } 48 | } 49 | -------------------------------------------------------------------------------- /example-7-fft/src/test/scala/fft/package.scala: -------------------------------------------------------------------------------- 1 | /* 2 | MIT License 3 | 4 | Copyright (c) 2019 Jan Marjanovic 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in all 14 | copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 | SOFTWARE. 23 | */ 24 | 25 | import breeze.math.{Complex, i} 26 | import breeze.numerics.pow 27 | 28 | package object fft { 29 | def round(x: Complex, n: Int): Complex = { 30 | val SCALE_FACT = pow(10, n) 31 | (breeze.numerics.round(x.real * SCALE_FACT) + 32 | i * breeze.numerics.round(x.imag * SCALE_FACT)) / SCALE_FACT 33 | } 34 | } 35 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/.scalafmt.conf: -------------------------------------------------------------------------------- 1 | version = 2.5.0 2 | maxColumn = 100 3 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/build.sbt: -------------------------------------------------------------------------------- 1 | 2 | ThisBuild / scalaVersion := "2.12.12" 3 | ThisBuild / version := "0.1.0" 4 | 5 | lazy val root = (project in file(".")) 6 | .settings( 7 | name := "presence-bits-compression", 8 | libraryDependencies ++= Seq( 9 | "edu.berkeley.cs" %% "chisel3" % "3.4.+", 10 | "edu.berkeley.cs" %% "chisel-iotesters" % "1.5.+", 11 | "io.j-marjanovic" %% "chisel-bfmtester" % "0.4.0-SNAPSHOT" 12 | ), 13 | scalacOptions ++= Seq( 14 | "-Xsource:2.11", 15 | "-language:reflectiveCalls", 16 | "-deprecation", 17 | "-feature", 18 | "-Xcheckinit" 19 | ), 20 | //addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.1" cross CrossVersion.full), 21 | //addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full) 22 | ) 23 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.4.5 2 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn 2 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/src/main/scala/presence_bits_comp/AxiMasterCoreReadIface.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020-2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package presence_bits_comp 24 | 25 | import chisel3._ 26 | 27 | class AxiMasterCoreReadIface( 28 | val addr_w: chisel3.internal.firrtl.Width, 29 | val data_w: chisel3.internal.firrtl.Width 30 | ) extends Bundle { 31 | // addr 32 | val addr = Input(UInt(48.W)) 33 | val len = Input(UInt(32.W)) 34 | val start = Input(Bool()) 35 | // data 36 | val data = Output(UInt(128.W)) 37 | val valid = Output(Bool()) 38 | val ready = Input(Bool()) 39 | } 40 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/src/main/scala/presence_bits_comp/AxiMasterCoreWriteIface.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package presence_bits_comp 24 | 25 | import chisel3._ 26 | 27 | class AxiMasterCoreWriteIface( 28 | val addr_w: chisel3.internal.firrtl.Width, 29 | val data_w: chisel3.internal.firrtl.Width 30 | ) extends Bundle { 31 | // address 32 | val addr = Input(UInt(addr_w)) 33 | val len = Input(UInt(32.W)) 34 | val start = Input(Bool()) 35 | // data 36 | val data = Input(UInt(data_w)) 37 | val valid = Input(Bool()) 38 | val ready = Output(Bool()) 39 | } 40 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/src/main/scala/presence_bits_comp/DecompressorKernelInputInterface.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package presence_bits_comp 24 | 25 | import chisel3._ 26 | import chisel3.util.log2Ceil 27 | 28 | class DecompressorKernelInputInterface(val w: Int) extends Bundle { 29 | val en: Bool = Input(Bool()) 30 | val adv: UInt = Output(UInt(log2Ceil(w + 1).W)) 31 | val adv_en: Bool = Output(Bool()) 32 | val data: Vec[UInt] = Input(Vec(w + 1, UInt(w.W))) 33 | } 34 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/src/main/scala/presence_bits_comp/DecompressorKernelOutputInterface.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package presence_bits_comp 24 | 25 | import chisel3._ 26 | 27 | class DecompressorKernelOutputInterface(val w: Int) extends Bundle { 28 | val data: Vec[UInt] = Output(Vec(w, UInt(w.W))) 29 | val vld: Bool = Output(Bool()) 30 | val ready: Bool = Input(Bool()) 31 | } 32 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/src/main/scala/presence_bits_comp/PresenceBitsCompMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package presence_bits_comp 24 | 25 | import chisel3.stage.ChiselStage 26 | 27 | object PresenceBitsCompMain extends App { 28 | (new ChiselStage()).emitSystemVerilog( 29 | new PresenceBitsDecompressor, 30 | Array[String]("--target-dir", "ip_cores/presence_bits_decompressor/hdl") ++ args 31 | ) 32 | } 33 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/src/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.4.6 2 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/src/test/resources/dense_matrix_with_sparse_els.npy: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/j-marjanovic/chisel-stuff/7139e4d03c60373939065a7e221f6a73d69dc710/example-8-presence-bits-compression/src/test/resources/dense_matrix_with_sparse_els.npy -------------------------------------------------------------------------------- /example-8-presence-bits-compression/src/test/resources/gen_stim.py: -------------------------------------------------------------------------------- 1 | #! /usr/bin/env python3 2 | 3 | import random 4 | 5 | import numpy as np 6 | 7 | N = 128 8 | fill_factor = 0.2 9 | 10 | random.seed(1234) 11 | 12 | m = np.zeros((N, N), dtype=np.float16) 13 | non_zero_els = int(N * N * fill_factor) 14 | 15 | for _ in range(non_zero_els): 16 | while True: 17 | i = random.randint(0, N) - 1 18 | j = random.randint(0, N - 1) 19 | if m[i, j] != 0: 20 | continue 21 | v = random.random() 22 | m[i, j] = v 23 | break 24 | 25 | np.save("dense_matrix_with_sparse_els.npy", m) 26 | -------------------------------------------------------------------------------- /example-8-presence-bits-compression/src/test/scala/presence_bits_comp/DecompressorKernelTest.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package presence_bits_comp 24 | 25 | import bfmtester._ 26 | 27 | class DecompressorKernelTest(c: DecompressorKernel) extends BfmTester(c) { 28 | 29 | val STIM1: List[BigInt] = List[BigInt]( 30 | // format: off 31 | 0xf, 0x1, 0x2, 0x3, 0x4, 32 | 0x1, 0x5, 33 | 0x2, 0x6, 34 | 0x4, 0x7, 35 | 0x8, 0x8, 36 | 0x3, 0x9, 0xa, 37 | 0xc, 0xb, 0xc 38 | // format:on 39 | ) 40 | 41 | val EXP1: List[BigInt] = List[BigInt]( 42 | // format: off 43 | 0x1, 0x2, 0x3, 0x4, 44 | 0x5, 0x0, 0x0, 0x0, 45 | 0x0, 0x6, 0x0, 0x0, 46 | 0x0, 0x0, 0x7, 0x0, 47 | 0x0, 0x0, 0x0, 0x8, 48 | 0x9, 0xa, 0x0, 0x0, 49 | 0x0, 0x0, 0xb, 0xc 50 | // format:on 51 | ) 52 | 53 | val driver = new DecompressorKernelDriver(c.io.in, this.rnd, bfm_peek, bfm_poke, println) 54 | val monitor = new DecompressorKernelMonitor(c.io.out, this.rnd, bfm_peek, bfm_poke, println) 55 | 56 | driver.stimAppend(STIM1) 57 | step(100) 58 | val resp = monitor.respGet() 59 | expect(resp.size == EXP1.size, "Response size should match expected size") 60 | for ((r, e) <- resp.zip(EXP1)) { 61 | expect(r == e, f"Data should match (recv = ${r}%02x, exp = ${e}%02x)") 62 | } 63 | } 64 | -------------------------------------------------------------------------------- /example-9-mem-checker/.scalafmt.conf: -------------------------------------------------------------------------------- 1 | version = 2.5.0 2 | maxColumn = 100 3 | -------------------------------------------------------------------------------- /example-9-mem-checker/build.sbt: -------------------------------------------------------------------------------- 1 | 2 | ThisBuild / scalaVersion := "2.12.12" 3 | ThisBuild / version := "0.1.0" 4 | 5 | lazy val root = (project in file(".")) 6 | .settings( 7 | name := "hw-accel-mem-test", 8 | libraryDependencies ++= Seq( 9 | "edu.berkeley.cs" %% "chisel3" % "3.4.+", 10 | "edu.berkeley.cs" %% "chisel-iotesters" % "1.5.+", 11 | "io.j-marjanovic" %% "chisel-bfmtester" % "0.4.0-SNAPSHOT" 12 | ), 13 | scalacOptions ++= Seq( 14 | "-Xsource:2.11", 15 | "-language:reflectiveCalls", 16 | "-deprecation", 17 | "-feature", 18 | "-Xcheckinit" 19 | ), 20 | ) 21 | -------------------------------------------------------------------------------- /example-9-mem-checker/ip_cores/mem_checker/inc/mem_checker.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | #pragma once 24 | 25 | #include 26 | 27 | enum mem_check_mode { 28 | MEM_CHECK_MODE_ALL_0, 29 | MEM_CHECK_MODE_ALL_1, 30 | MEM_CHECK_MODE_WALK_0, 31 | MEM_CHECK_MODE_WALK_1, 32 | MEM_CHECK_MODE_ALT, 33 | MEM_CHECK_MODE_CNTR_8, 34 | MEM_CHECK_MODE_CNTR_32, 35 | MEM_CHECK_MODE_CNTR_128 36 | }; 37 | 38 | int mem_check_write(uint32_t base, uint64_t mem_address, uint32_t mem_size, enum mem_check_mode mode); 39 | 40 | int mem_check_read_and_check(uint32_t base, uint64_t mem_address, uint32_t mem_size, enum mem_check_mode mode); 41 | 42 | int mem_check_full(uint32_t base, uint64_t mem_address, uint32_t mem_size); 43 | -------------------------------------------------------------------------------- /example-9-mem-checker/ip_cores/mem_checker/inc/mem_checker_regs.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | #pragma once 24 | 25 | #define ADDR_ID (0x0) 26 | #define ADDR_VERSION (0x4) 27 | #define ADDR_CONF (0x8) 28 | #define ADDR_CTRL (0x10) 29 | #define ADDR_READ_STATUS (0x20) 30 | #define ADDR_READ_CTRL (0x24) 31 | #define ADDR_READ_ADDR_LO (0x28) 32 | #define ADDR_READ_ADDR_HI (0x2c) 33 | #define ADDR_READ_LEN (0x30) 34 | #define ADDR_READ_RESP_CNTR (0x34) 35 | #define ADDR_READ_DURATION (0x38) 36 | #define ADDR_WRITE_STATUS (0x60) 37 | #define ADDR_WRITE_CTRL (0x64) 38 | #define ADDR_WRITE_ADDR_LO (0x68) 39 | #define ADDR_WRITE_ADDR_HI (0x6c) 40 | #define ADDR_WRITE_LEN (0x70) 41 | #define ADDR_WRITE_RESP_CNTR (0x74) 42 | #define ADDR_WRITE_DURATION (0x78) 43 | #define ADDR_CHECK_TOT (0xa0) 44 | #define ADDR_CHECK_OK (0xa4) 45 | -------------------------------------------------------------------------------- /example-9-mem-checker/ip_cores/mem_checker/mem_checker_sw.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_driver mem_checker_driver 3 | 4 | set_sw_property hw_class_name mem_checker 5 | set_sw_property version 1.1 6 | set_sw_property bsp_subdirectory drivers 7 | set_sw_property min_compatible_hw_version 0.1 8 | 9 | add_sw_property include_source inc/mem_checker.h 10 | add_sw_property include_source inc/mem_checker_regs.h 11 | 12 | add_sw_property c_source src/mem_checker.c 13 | 14 | add_sw_property supported_bsp_type HAL 15 | -------------------------------------------------------------------------------- /example-9-mem-checker/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.4.5 2 | -------------------------------------------------------------------------------- /example-9-mem-checker/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn 2 | -------------------------------------------------------------------------------- /example-9-mem-checker/src/main/scala/mem_checker/MemCheckerMain.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package mem_checker 24 | 25 | import chisel3.stage.ChiselStage 26 | 27 | object MemCheckerMain extends App { 28 | (new ChiselStage()).emitSystemVerilog( 29 | new MemChecker, 30 | Array[String]("--target-dir", "ip_cores/mem_checker/hdl") ++ args 31 | ) 32 | } 33 | -------------------------------------------------------------------------------- /example-9-mem-checker/src/test/scala/mem_checker/MemCheckerTester.scala: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2020-2021 Jan Marjanovic 3 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy 5 | of this software and associated documentation files (the "Software"), to deal 6 | in the Software without restriction, including without limitation the rights 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 | copies of the Software, and to permit persons to whom the Software is 9 | furnished to do so, subject to the following conditions: 10 | 11 | The above copyright notice and this permission notice shall be included in all 12 | copies or substantial portions of the Software. 13 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 | SOFTWARE. 21 | */ 22 | 23 | package mem_checker 24 | 25 | import chisel3.iotesters 26 | import chisel3.iotesters.ChiselFlatSpec 27 | 28 | class MemCheckerTester extends ChiselFlatSpec { 29 | 30 | ignore should "check the axi slave" in { 31 | iotesters.Driver.execute( 32 | Array( 33 | "--backend-name", 34 | "verilator", 35 | "--fint-write-vcd", 36 | "--test-seed", 37 | "1234", 38 | "--target-dir", 39 | "test_run_dir/DecompressorAxiSlaveTest", 40 | "--top-name", 41 | "DecompressorAxiSlaveTest" 42 | ), 43 | () => new MemCheckerAxiSlave(0x00010203, 256, 16) 44 | ) { c => 45 | new MemCheckerAxiSlaveTest(c) 46 | } should be(true) 47 | } 48 | 49 | it should "check the top module" in { 50 | iotesters.Driver.execute( 51 | Array( 52 | "--backend-name", 53 | "verilator", 54 | "--fint-write-vcd", 55 | "--test-seed", 56 | "1234", 57 | "--target-dir", 58 | "test_run_dir/MemCheckerTest", 59 | "--top-name", 60 | "MemCheckerTest" 61 | ), 62 | () => new MemChecker() 63 | ) { c => 64 | new MemCheckerTest(c) 65 | } should be(true) 66 | } 67 | 68 | } 69 | -------------------------------------------------------------------------------- /utils-chisel-to-vhdl/.gitignore: -------------------------------------------------------------------------------- 1 | 2 | /.idea 3 | 4 | 5 | # Simple Build Tool 6 | # http://www.scala-sbt.org/release/docs/Getting-Started/Directories.html#configuring-version-control 7 | 8 | dist/* 9 | target/ 10 | lib_managed/ 11 | src_managed/ 12 | project/boot/ 13 | project/plugins/project/ 14 | .history 15 | .cache 16 | .lib/ 17 | 18 | -------------------------------------------------------------------------------- /utils-chisel-to-vhdl/build.sbt: -------------------------------------------------------------------------------- 1 | name := "chisel-to-vhdl-cli" 2 | 3 | version := "0.1" 4 | 5 | scalaVersion := "2.12.8" 6 | 7 | libraryDependencies += "org.scalatest" % "scalatest_2.12" % "3.0.5" % "test" 8 | 9 | scalacOptions ++= Seq("-unchecked", "-deprecation", "-Xcheckinit", "-encoding", "utf8", "-feature") 10 | 11 | trapExit := false 12 | -------------------------------------------------------------------------------- /utils-chisel-to-vhdl/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.2.7 -------------------------------------------------------------------------------- /utils-chisel-to-vhdl/src/main/scala/chisel_to_vhdl/ChiselToVhdlMain.scala: -------------------------------------------------------------------------------- 1 | package chisel_to_vhdl 2 | 3 | object ChiselToVhdlMain extends App { 4 | val translator = new Translator 5 | Iterator.continually(scala.io.StdIn.readLine) 6 | .takeWhile(_ != null) 7 | .foreach { l => 8 | val s = translator.translate(l) 9 | println(s) 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /utils-chisel-to-vhdl/src/main/scala/chisel_to_vhdl/Translator.scala: -------------------------------------------------------------------------------- 1 | package chisel_to_vhdl 2 | 3 | import scala.language.postfixOps 4 | import scala.util.matching.Regex 5 | 6 | 7 | class Translator { 8 | class TrRegex(val in: Regex, val out: Regex.Match => String) 9 | 10 | val RE_WS = "([ \\t]*)" 11 | val RE_ID = "([A-Za-z_]+[A-Za-z_0-9]*)" 12 | val RE_ID_NR = "([A-Za-z_0-9]+)" 13 | val RE_IO = "(In|Out)put" 14 | 15 | val TRANS_REGEXES: List[TrRegex] = List( 16 | // port, vector 17 | new TrRegex( 18 | in = s"${RE_WS}val $RE_ID = ${RE_IO}\\(UInt\\(${RE_ID_NR}.W\\)\\)".r, 19 | m => s"${m.group(1)}${m.group(2)} : ${m.group(3).toLowerCase} std_logic_vector(${m.group(4)}-1 downto 0);" 20 | ), 21 | // port, bool 22 | new TrRegex( 23 | in = s"${RE_WS}val $RE_ID = ${RE_IO}\\(Bool\\(\\)\\)".r, 24 | m => s"${m.group(1)}${m.group(2)} : ${m.group(3).toLowerCase} std_logic;" 25 | ), 26 | // instantiations 27 | new TrRegex( 28 | in = s"${RE_WS}val $RE_ID = Module\\(new $RE_ID\\)".r, 29 | m => { 30 | val ws = m.group(1) 31 | val in = m.group(2) 32 | val mn = m.group(3) 33 | s"$ws$in: entity work.$mn\n${ws}port map(\n${ws});" 34 | } 35 | ), 36 | // comments 37 | new TrRegex( 38 | in = s"${RE_WS}//(.*)".r, 39 | m => s"${m.group(1)}--${m.group(2)}" 40 | ), 41 | // emtpy string 42 | new TrRegex( 43 | in = "".r, 44 | m => "" 45 | ), 46 | ) 47 | 48 | def translate(line: String): String = { 49 | 50 | TRANS_REGEXES.foreach(tr => { 51 | val m = tr.in.findFirstMatchIn(line) 52 | if (m.isDefined) { 53 | return tr.out(m.get) 54 | } 55 | }) 56 | 57 | s"-- could not translate: $line" 58 | } 59 | } 60 | 61 | -------------------------------------------------------------------------------- /utils-chisel-to-vhdl/src/main/scala/chisel_to_vhdl/VhdlTokens.scala: -------------------------------------------------------------------------------- 1 | package chisel_to_vhdl 2 | 3 | import scala.util.matching.Regex 4 | 5 | object VhdlTokens { 6 | sealed abstract class Token { 7 | var s: String 8 | val m: Regex 9 | } 10 | 11 | case class OpLiteral(var s: String) extends Token { 12 | override val m: Regex = "(===)|(=/=)|(:=)|(<=)|([:=\\.\\+\\-\\,])".r 13 | } 14 | 15 | case class Id(var s: String) extends Token { 16 | override val m: Regex = "[a-zA-Z_][a-zA-Z0-9_]*".r 17 | } 18 | 19 | /** reserved keywords do not have their own regex, they are reassigned from 20 | * Id's after regex matching 21 | */ 22 | case class Keyword(var s: String) extends Token { 23 | override val m: Regex = "---DO_NOT_MATCH---rnd number: 34509215869798602196".r 24 | } 25 | 26 | case class StdLibId(var s: String) extends Token { 27 | override val m: Regex = "---DO_NOT_MATCH---rnd number: 34509215869798602196".r 28 | } 29 | 30 | case class IntLit(var s: String) extends Token { 31 | override val m: Regex = "([0-9]+)|(0x[0-9a-fA-F]+)".r 32 | } 33 | 34 | case class CommentLit(var s: String) extends Token { 35 | override val m: Regex = "--.*".r 36 | } 37 | 38 | case class WhiteSpace(var s: String) extends Token { 39 | override val m: Regex = "[ \t]+".r 40 | } 41 | 42 | case class NewLine(var s: String) extends Token { 43 | override val m: Regex = "\n".r 44 | } 45 | 46 | case class ParensOpen(var s: String) extends Token { 47 | override val m: Regex = "\\(".r 48 | } 49 | 50 | case class ParensClose(var s: String) extends Token { 51 | override val m: Regex = "\\)".r 52 | } 53 | 54 | case class Semicol(var s: String) extends Token { 55 | override val m: Regex = ";".r 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /utils-chisel-to-vhdl/src/test/scala/chisel_to_vhdl/TranslatorTest.scala: -------------------------------------------------------------------------------- 1 | package chisel_to_vhdl 2 | 3 | import org.scalatest.FlatSpec 4 | 5 | class TranslatorTest extends FlatSpec { 6 | 7 | "Translator" should "translate input/output vector ports" in { 8 | val t = new Translator 9 | val cl = "val S_AXI_AWADDR = Input(UInt(ADDR_W.W))" 10 | val vl = "S_AXI_AWADDR : in std_logic_vector(ADDR_W-1 downto 0);" 11 | val tr = t.translate(cl) 12 | assert(vl == tr) 13 | } 14 | 15 | it should "translate input/output boolean ports" in { 16 | val t = new Translator 17 | val cl = "val S_AXI_AWREADY = Output(Bool())" 18 | val vl = "S_AXI_AWREADY : out std_logic;" 19 | val tr = t.translate(cl) 20 | assert(vl == tr) 21 | } 22 | 23 | it should "translate module instantations" in { 24 | val t = new Translator 25 | val cl = " val axi_slave = Module(new StatusAxiSlave)" 26 | val vl = " axi_slave: entity work.StatusAxiSlave\n port map(\n );" 27 | val tr = t.translate(cl) 28 | assert(vl == tr) 29 | } 30 | 31 | it should "preserve leading whitespace" in { 32 | val t = new Translator 33 | val cl = " \tval S_AXI_AWREADY = Output(Bool())" 34 | val vl = " \tS_AXI_AWREADY : out std_logic;" 35 | val tr = t.translate(cl) 36 | assert(vl == tr) 37 | } 38 | 39 | it should "translate single-line comments" in { 40 | val t = new Translator 41 | val cl = " // hello" 42 | val vl = " -- hello" 43 | val tr = t.translate(cl) 44 | assert(vl == tr) 45 | } 46 | 47 | it should "translate empty line" in { 48 | val t = new Translator 49 | val cl = "" 50 | val vl = "" 51 | val tr = t.translate(cl) 52 | assert(vl == tr) 53 | } 54 | } 55 | --------------------------------------------------------------------------------