├── ALU.odp ├── README ├── arduino ├── DigitalDisplay │ └── DigitalDisplay.ino ├── Erase │ └── Erase.ino ├── Microcode │ └── Microcode.ino └── libraries │ └── MyEEPROM │ ├── MyEEPROM.cpp │ └── MyEEPROM.h ├── assembler ├── Makefile ├── asmerror.c ├── asmerror.h ├── assembler.l ├── assembler.y ├── directive.c ├── directive.h ├── instruction.c ├── instruction.h ├── parsenode.c ├── parsenode.h ├── symbols.c └── symbols.h ├── programs ├── README ├── fib.s ├── fib_mult_powers.s ├── fibbak.s ├── multiply.s ├── powers.s ├── powers_of_3.s ├── primes.c ├── primes.s ├── qsort.c ├── qsort.s ├── readram.s └── readwriteram.s └── schematics ├── 7-digit-display.sym ├── 74382-1.sym ├── ALU.pdf ├── ALU.ps ├── ALU.sch ├── AS6C6264-1.sym ├── AT28C64-1.sym ├── ArduinoNano.sym ├── Arduino_programmer.pdf ├── Arduino_programmer.ps ├── Arduino_programmer.sch ├── RAM.pdf ├── RAM.ps ├── RAM.sch ├── RS latch.sym ├── clock.pdf ├── clock.ps ├── clock.sch ├── control_logic.pdf ├── control_logic.ps ├── control_logic.sch ├── decimal_display.pdf ├── decimal_display.ps ├── decimal_display.sch ├── instruction_register.pdf ├── instruction_register.ps ├── instruction_register.sch ├── power.pdf ├── power.ps ├── power.sch ├── program_counter.pdf ├── program_counter.ps ├── program_counter.sch ├── register.pdf ├── register.ps └── register.sch /ALU.odp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/ALU.odp -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | jCPU: My homebuilt 8-bit Ben Eater inspired CPU 2 | =============================================== 3 | 4 | A few months ago, inspired by Ben Eater's wonderful Youtube video series, I built my very 5 | own 8-bit CPU from scratch, on breadboards using basic digital logic components (gates, 6 | latches, EEPROMs). 7 | 8 | I have documented the entire adventure on my Youtube channel: 9 | https://www.youtube.com/channel/UCH09NwwJsfThwLKvc6kxl4Q 10 | 11 | This repository contains the supporting software for this project. It is divided into a 12 | number of sub-projects: 13 | 14 | + arduino/ contains the Arduino C++ code, which is used to program the various EEPROMs 15 | used in the project. 16 | ---+ arduino/DigitalDisplay/ programs an EEPROM to display decimal digits, based on 17 | 8-bit bainry input. See 18 | https://www.youtube.com/watch?v=b3iytSzYhSs 19 | ---+ arduino/Erase/ erases an entire EEPROM, resetting every byte to 0xFF 20 | ---+ arduino/Microcode/ programs microcode into the 4 EEPROMs, which make up the control 21 | unit. See https://www.youtube.com/watch?v=CE615IDVVNA and 22 | https://www.youtube.com/watch?v=O_mTxnFYLXE 23 | ---+ arduino/libraries/MyEEPROM/ support library to provide high-level EEPROM read- and 24 | write-functions. See 25 | https://www.youtube.com/watch?v=b3iytSzYhSs 26 | 27 | + assembler/ A very simple assembler, written in C, using UN*X lex and yacc, which can 28 | translate the assembly files in programs/ to machine code, suitable for the 29 | 8-bit CPU. See https://www.youtube.com/watch?v=-_u6HhAb5mo&t=1509s 30 | 31 | + programs/ Contains several example programs in assembly for the 8-bit CPU. Some 32 | (primes.s and qsport.s) are hand-compiled from corresponding C-code. Others 33 | were written in assembly from scratch. 34 | 35 | + schematics/ generated PDF, and source .sch (gEDA schematics) files, for electrical 36 | schematics describing the various parts of the 8-bit CPU. Shown throughout 37 | the videos in the series. 38 | -------------------------------------------------------------------------------- /arduino/DigitalDisplay/DigitalDisplay.ino: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #define DUMP 1 5 | 6 | #define DP_HOR_TOP (1 << 5) 7 | #define DP_HOR_MID (1 << 7) 8 | #define DP_HOR_BOTTOM (1 << 0) 9 | #define DP_VER_LTOP (1 << 6) 10 | #define DP_VER_LBOTTOM (1 << 3) 11 | #define DP_VER_RTOP (1 << 4) 12 | #define DP_VER_RBOTTOM (1 << 1) 13 | #define DP_POINT (1 << 2) 14 | 15 | uint8_t digits[] = { 16 | /* 0 */ DP_HOR_TOP | DP_HOR_BOTTOM | DP_VER_LTOP | DP_VER_RTOP | DP_VER_LBOTTOM | DP_VER_RBOTTOM, 17 | /* 1 */ DP_VER_RTOP | DP_VER_RBOTTOM, 18 | /* 2 */ DP_HOR_TOP | DP_VER_RTOP | DP_HOR_MID | DP_VER_LBOTTOM | DP_HOR_BOTTOM, 19 | /* 3 */ DP_HOR_TOP | DP_VER_RTOP | DP_HOR_MID | DP_VER_RBOTTOM | DP_HOR_BOTTOM, 20 | /* 4 */ DP_VER_LTOP | DP_VER_RTOP | DP_HOR_MID | DP_VER_RBOTTOM, 21 | /* 5 */ DP_HOR_TOP | DP_VER_LTOP | DP_HOR_MID | DP_VER_RBOTTOM | DP_HOR_BOTTOM, 22 | /* 6 */ DP_HOR_TOP | DP_VER_LTOP | DP_HOR_MID | DP_VER_LBOTTOM | DP_VER_RBOTTOM | DP_HOR_BOTTOM, 23 | /* 7 */ DP_HOR_TOP | DP_VER_RTOP | DP_VER_RBOTTOM, 24 | /* 8 */ DP_HOR_TOP | DP_HOR_MID | DP_HOR_BOTTOM | DP_VER_LTOP | DP_VER_RTOP | DP_VER_LBOTTOM | DP_VER_RBOTTOM, 25 | /* 9 */ DP_HOR_TOP | DP_HOR_MID | DP_HOR_BOTTOM | DP_VER_LTOP | DP_VER_RTOP | DP_VER_RBOTTOM 26 | }; 27 | 28 | void write_display_digits(bool issigned) { 29 | 30 | int16_t min_val = issigned ? -128 : 0; 31 | int16_t max_val = issigned ? 127 : 255; 32 | 33 | uint16_t start_addr = issigned ? 0x400 : 0; 34 | 35 | Serial.print("Writing "); Serial.print(issigned ? "signed" : "unsigned"); Serial.print(" ones "); 36 | for (int16_t value = min_val; value <= max_val; value++) { 37 | 38 | MyEEPROM.write_eeprom(start_addr + ((value < 0) ? 256 : 0) + value, digits[abs(value) % 10]); 39 | if ((value % 10) == 0) { 40 | Serial.print("."); 41 | } 42 | } 43 | Serial.println(" done."); 44 | Serial.print("Writing "); Serial.print(issigned ? "signed" : "unsigned"); Serial.print(" 10s "); 45 | for (int16_t value = min_val; value <= max_val; value++) { 46 | 47 | if (abs(value) < 10) { 48 | 49 | MyEEPROM.write_eeprom(start_addr + ((value < 0) ? 256 : 0) + value + 0x100, 0); 50 | } else { 51 | 52 | MyEEPROM.write_eeprom(start_addr + ((value < 0) ? 256 : 0) + value + 0x100, digits[(abs(value) / 10) % 10]); 53 | } 54 | if ((value % 10) == 0) { 55 | Serial.print("."); 56 | } 57 | } 58 | Serial.println(" done."); 59 | Serial.print("Writing "); Serial.print(issigned ? "signed" : "unsigned"); Serial.print(" 100s "); 60 | for (int16_t value=min_val; value <= max_val; value++) { 61 | 62 | if (abs(value) < 100) { 63 | 64 | MyEEPROM.write_eeprom(start_addr + ((value < 0) ? 256 : 0) + value + 0x200, 0); 65 | } else { 66 | 67 | MyEEPROM.write_eeprom(start_addr + ((value < 0) ? 256 : 0) + value + 0x200, digits[(abs(value) / 100) % 10]); 68 | } 69 | if ((value % 10) == 0) { 70 | Serial.print("."); 71 | } 72 | } 73 | Serial.println(" done."); 74 | Serial.print("Writing "); Serial.print(issigned ? "signed" : "unsigned"); Serial.print(" 1000s "); 75 | for (int16_t value=min_val; value <= max_val; value++) { 76 | 77 | MyEEPROM.write_eeprom(start_addr + ((value < 0) ? 256 : 0) + value + 0x300, (issigned && (value < 0)) ? DP_HOR_MID : 0); 78 | if ((value % 10) == 0) { 79 | Serial.print("."); 80 | } 81 | } 82 | Serial.println(" done."); 83 | } 84 | 85 | 86 | 87 | // the setup function runs once when you press reset or power the board 88 | void setup() { 89 | Serial.begin(115200); 90 | Serial.print("About to program EEPROM for 7-digit display. Press 'y' to continue ... "); 91 | while (Serial.available() <= 0); 92 | char answer = Serial.read(); 93 | Serial.println(answer); 94 | 95 | if (answer == 'y') { 96 | 97 | MyEEPROM.init(); 98 | 99 | write_display_digits(false); 100 | write_display_digits(true); 101 | 102 | #ifdef DUMP 103 | MyEEPROM.dump_eeprom(0, 0x7FF); 104 | #endif 105 | } 106 | Serial.println("Have a nice day."); 107 | } 108 | 109 | // the loop function runs over and over again forever 110 | void loop() { 111 | } 112 | -------------------------------------------------------------------------------- /arduino/Erase/Erase.ino: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | void setup() { 5 | // put your setup code here, to run once: 6 | Serial.begin(115200); 7 | Serial.print("About to erase EEPROM. Press 'y' to contine ... "); 8 | while (Serial.available() <= 0); 9 | char answer = Serial.read(); 10 | Serial.println(answer); 11 | 12 | if (answer == 'y') { 13 | 14 | MyEEPROM.init(); 15 | 16 | Serial.print("Erasing "); 17 | for (uint16_t add=0; add < 0x2000; add++) { 18 | 19 | MyEEPROM.write_eeprom(add, 0xFF); 20 | 21 | if ((add % 0x100) ==0) { 22 | 23 | Serial.print("."); 24 | } 25 | 26 | } 27 | Serial.println("done."); 28 | 29 | MyEEPROM.dump_eeprom(0, 0x1FFF); 30 | } 31 | Serial.println("Have a nice day."); 32 | } 33 | 34 | void loop() { 35 | // put your main code here, to run repeatedly: 36 | 37 | } 38 | -------------------------------------------------------------------------------- /arduino/Microcode/Microcode.ino: -------------------------------------------------------------------------------- 1 | #define ROM_NO 3 2 | 3 | #define INS_MOV 1 4 | //#define INS_LOD 1 5 | //#define INS_STO 1 6 | //#define INS_ALU 1 7 | 8 | //#define DUMP 1 9 | 10 | //#define CHECK_COVERAGE 1 11 | 12 | 13 | #include 14 | #include 15 | 16 | 17 | /* signal word: bit position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 18 | * meaning _TR - - - - - _ME _MW _HLT PGM _MAW _IRW _RdE _RdW _RcE _RcW 19 | * bit position 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 20 | * meaning _RbE _RbW _RaE _RaW _PCE _PCW _SPE _SPW PCC _ALE _ALW _ALB ALS2 ALS1 ALS0 ALC 21 | */ 22 | 23 | 24 | #define ALC ((uint32_t)1 << 0) 25 | #define ALS0 ((uint32_t)1 << 1) 26 | #define ALS1 ((uint32_t)1 << 2) 27 | #define ALS2 ((uint32_t)1 << 3) 28 | #define _ALB ((uint32_t)1 << 4) 29 | #define _ALW ((uint32_t)1 << 5) 30 | #define _ALE ((uint32_t)1 << 6) 31 | #define PCC ((uint32_t)1 << 7) 32 | #define _SPW ((uint32_t)1 << 8) 33 | #define _SPE ((uint32_t)1 << 9) 34 | #define _PCW ((uint32_t)1 << 10) 35 | #define _PCE ((uint32_t)1 << 11) 36 | #define _RaW ((uint32_t)1 << 12) 37 | #define _RaE ((uint32_t)1 << 13) 38 | #define _RbW ((uint32_t)1 << 14) 39 | #define _RbE ((uint32_t)1 << 15) 40 | 41 | #define _RcW ((uint32_t)1 << 16) 42 | #define _RcE ((uint32_t)1 << 17) 43 | #define _RdW ((uint32_t)1 << 18) 44 | #define _RdE ((uint32_t)1 << 19) 45 | #define _IRW ((uint32_t)1 << 20) 46 | #define _MAW ((uint32_t)1 << 21) 47 | #define PGM ((uint32_t)1 << 22) 48 | #define _HLT ((uint32_t)1 << 23) 49 | #define _MW ((uint32_t)1 << 24) 50 | #define _ME ((uint32_t)1 << 25) 51 | 52 | #define _TR ((uint32_t)1 << 31) 53 | 54 | #define ALS(S) ((uint32_t)S << 1) 55 | 56 | #define B_MINUS_A 0b001 57 | #define A_MINUS_B 0b010 58 | #define A_PLUS_B 0b011 59 | #define A_XOR_B 0b100 60 | #define A_OR_B 0b101 61 | #define A_AND_B 0b110 62 | 63 | 64 | #define INC_A 0b000 65 | #define NOT_A 0b111 66 | 67 | 68 | 69 | /* EEPROM address: bit position 12 11 10 .... 8 7 ..... 0 70 | * meaning flags carry (microtime) T opcode 71 | */ 72 | 73 | 74 | #define CARRY_ADDR (1 << 11) 75 | #define FLAGS_ADDR (1 << 12) 76 | 77 | #define ins_eeprom_address(opcode, carry, flags, T) (opcode | (carry ? CARRY_ADDR : 0) | (flags ? FLAGS_ADDR : 0) | (T << 8)) 78 | 79 | 80 | #define MOV 0b00 81 | #define LOD 0b01 82 | #define STO 0b10 83 | 84 | 85 | #define Ra 0b000 86 | #define Rb 0b001 87 | #define Rc 0b010 88 | #define Rd 0b011 89 | #define SP 0b100 90 | #define PC 0b101 91 | #define SPi 0b110 92 | #define IMM 0b111 93 | 94 | 95 | #define OPCODE(op,dreg,sreg) (((op) << 6) | ((dreg) << 3) | (sreg)) 96 | #define ALU_OPCODE(with_carry,S,reg) ((0b11 << 6) | (with_carry ? 1 << 5 : 0) | ((S & 0b111) << 2) | (reg & 0b11)) 97 | 98 | 99 | #ifdef CHECK_COVERAGE 100 | uint8_t write_mask[32]; 101 | #endif 102 | 103 | uint32_t inline flip_active_lows(uint32_t microcode_word) { 104 | 105 | microcode_word ^= (_ALB | _ALW | _ALE | _SPW | _SPE | _PCW | _PCE | _RaW | _RaE | _RbW | _RbE | _RcW | _RcE | _RdW | _RdE | _MAW | _IRW | _HLT | _MW | _ME | _TR); 106 | return microcode_word; 107 | } 108 | 109 | uint32_t _E(uint32_t reg) { 110 | 111 | switch (reg) { 112 | case Ra: return _RaE; 113 | case Rb: return _RbE; 114 | case Rc: return _RcE; 115 | case Rd: return _RdE; 116 | case SP: return _SPE; 117 | case PC: return _PCE; 118 | default: return 0; 119 | } 120 | } 121 | 122 | uint32_t _W(uint8_t reg) { 123 | 124 | switch (reg) { 125 | case Ra: return _RaW; 126 | case Rb: return _RbW; 127 | case Rc: return _RcW; 128 | case Rd: return _RdW; 129 | case SP: return _SPW; 130 | case PC: return _PCW; 131 | default: return 0; 132 | } 133 | } 134 | 135 | #define FETCH0 (_PCE | _MAW) 136 | #define FETCH1 (PGM | _ME | _IRW | PCC) 137 | 138 | uint32_t microcode[8] = {FETCH0,FETCH1,_TR,0,0,0,0,0}; 139 | 140 | 141 | uint32_t *MICROCODE0() { 142 | microcode[2] = _TR; 143 | microcode[3] = microcode[4] = microcode[5] = microcode[6] = microcode[7] = 0; 144 | return microcode; 145 | } 146 | 147 | uint32_t *MICROCODE1(uint32_t c1) { 148 | microcode[2] = c1 | _TR; 149 | microcode[3] = microcode[4] = microcode[5] = microcode[6] = microcode[7] = 0; 150 | return microcode; 151 | } 152 | 153 | uint32_t *MICROCODE2(uint32_t c1, uint32_t c2) { 154 | microcode[2] = c1; 155 | microcode[3] = c2 | _TR; 156 | microcode[4] = microcode[5] = microcode[6] = microcode[7] = 0; 157 | return microcode; 158 | } 159 | 160 | uint32_t *MICROCODE3(uint32_t c1,uint32_t c2,uint32_t c3) { 161 | microcode[2] = c1; 162 | microcode[3] = c2; 163 | microcode[4] = c3 | _TR; 164 | microcode[5] = microcode[6] = microcode[7] = 0; 165 | return microcode; 166 | } 167 | 168 | uint32_t *MICROCODE4(uint32_t c1,uint32_t c2,uint32_t c3, uint32_t c4) { 169 | microcode[2] = c1; 170 | microcode[3] = c2; 171 | microcode[4] = c3; 172 | microcode[5] = c4 | _TR; 173 | microcode[6] = microcode[7] = 0; 174 | return microcode; 175 | } 176 | 177 | 178 | 179 | void write_conditional_instruction(uint16_t opcode, bool carry, bool flags, uint32_t microcode[], uint8_t rom_no) { 180 | 181 | for (uint8_t T = 0; T < 8; T++) { 182 | 183 | uint16_t eeprom_address = ins_eeprom_address(opcode, carry, flags, T); 184 | uint8_t eeprom_byte = (flip_active_lows(microcode[T]) >> (8*rom_no)) & 0xFF; 185 | MyEEPROM.write_eeprom(eeprom_address, eeprom_byte); 186 | 187 | #ifdef CHECK_COVERAGE 188 | uint8_t bit_no = eeprom_address & 0x7; 189 | write_mask[(eeprom_address & 0xFF) >> 3] |= (1 << bit_no); 190 | #endif 191 | } 192 | } 193 | 194 | void write_carrycond_instruction(uint16_t opcode, bool carry, uint32_t microcode[], uint8_t rom_no) { 195 | 196 | write_conditional_instruction(opcode, carry, false, microcode, rom_no); 197 | write_conditional_instruction(opcode, carry, true, microcode, rom_no); 198 | } 199 | 200 | void write_instruction(uint16_t opcode, uint32_t microcode[], uint8_t rom_no) { 201 | 202 | write_carrycond_instruction(opcode, false, microcode, rom_no); 203 | write_carrycond_instruction(opcode, true, microcode, rom_no); 204 | } 205 | 206 | #ifdef INS_MOV 207 | void write_MOVs(uint8_t rom_no) { 208 | 209 | Serial.print("Writing reg <- reg MOV instructions "); 210 | for (uint8_t sreg = Ra; sreg <= PC; sreg++) { 211 | 212 | Serial.print("."); 213 | for (uint8_t dreg = Ra; dreg <= PC; dreg++) { 214 | 215 | if (sreg != dreg) { 216 | 217 | write_instruction(OPCODE(MOV, dreg, sreg), MICROCODE1(_W(dreg) | _E(sreg)), rom_no); 218 | } 219 | } 220 | } 221 | Serial.println(" done."); 222 | 223 | Serial.print("Writing reg <- imm DATA instructions ."); 224 | for (uint8_t dreg = Ra; dreg <= PC; dreg++) { 225 | 226 | write_instruction(OPCODE(MOV, dreg, IMM), MICROCODE2(_PCE | _MAW | PCC, PGM | _ME | _W(dreg)), rom_no); 227 | } 228 | Serial.println(". done."); 229 | 230 | Serial.print("Writing NOP and HLT ."); 231 | write_instruction(OPCODE(MOV, Ra, Ra), MICROCODE0(), rom_no); 232 | write_instruction(OPCODE(MOV, PC, PC), MICROCODE1(_HLT), rom_no); 233 | Serial.println(". done."); 234 | 235 | Serial.print("Writing conditional JC, JZ, JO and JN instructions "); 236 | write_carrycond_instruction(OPCODE(MOV, IMM, 0b000), false, MICROCODE1(PCC), rom_no); 237 | write_carrycond_instruction(OPCODE(MOV, IMM, 0b000), true, MICROCODE2(_MAW | _PCE | PCC, PGM | _ME | _PCW), rom_no); 238 | Serial.print("."); 239 | for (uint8_t flag = 0; flag <= 2; flag++) { 240 | write_conditional_instruction(OPCODE(MOV, IMM, 1<|SPi|IMM (8) | MOV , SPi (6) | MOV , (except Ra, PC) (4) "); 250 | 251 | write_instruction(OPCODE(MOV, IMM, Rd), MICROCODE1(_HLT), rom_no); 252 | write_instruction(OPCODE(MOV, IMM, PC), MICROCODE1(_HLT), rom_no); 253 | write_instruction(OPCODE(MOV, IMM, SPi), MICROCODE1(_HLT), rom_no); 254 | write_instruction(OPCODE(MOV, IMM, IMM), MICROCODE1(_HLT), rom_no); 255 | Serial.print("."); 256 | 257 | for (uint8_t sreg = Ra; sreg <= IMM; sreg++) { 258 | 259 | write_instruction(OPCODE(MOV, SPi, sreg), MICROCODE1(_HLT), rom_no); 260 | } 261 | Serial.print("."); 262 | 263 | for (uint8_t dreg = Ra; dreg <= PC; dreg++) { 264 | 265 | write_instruction(OPCODE(MOV, dreg, SPi), MICROCODE1(_HLT), rom_no); 266 | } 267 | Serial.print("."); 268 | 269 | for (uint8_t reg = Rb; reg <= SP; reg++) { 270 | 271 | write_instruction(OPCODE(MOV, reg, reg), MICROCODE1(_HLT), rom_no); 272 | } 273 | Serial.println(". done."); 274 | } 275 | #endif 276 | 277 | #ifdef INS_LOD 278 | void write_LODs(uint8_t rom_no) { 279 | 280 | Serial.print("Writing reg <- [reg] LOD instructions "); 281 | for (uint8_t sreg = Ra; sreg <= PC; sreg++) { 282 | 283 | Serial.print("."); 284 | for (uint8_t dreg = Ra; dreg <= PC; dreg++) { 285 | 286 | write_instruction(OPCODE(LOD, dreg, sreg), MICROCODE2(_MAW | _E(sreg), ((sreg == Rc) ? PGM : 0) | _ME | _W(dreg)), rom_no); 287 | } 288 | } 289 | Serial.println(" done."); 290 | 291 | Serial.print("Writing reg <- [SPi] POP instructions ."); 292 | for (uint8_t dreg = Ra; dreg <= PC; dreg++) { 293 | 294 | write_instruction(OPCODE(LOD, dreg, SPi), MICROCODE3(_SPE | _ALW | ALC | ALS(A_PLUS_B) | _MAW, _SPW | _ALE, _W(dreg) | _ME), rom_no); 295 | } 296 | Serial.println(". done."); 297 | 298 | Serial.print("Writing reg <- [IMM] LOD instructions ."); 299 | for (uint8_t dreg = Ra; dreg <= PC; dreg++) { 300 | 301 | write_instruction(OPCODE(LOD, dreg, IMM), MICROCODE3(_MAW | _PCE | PCC, _ME | PGM | _MAW, _ME | _W(dreg)), rom_no); 302 | } 303 | Serial.println(". done."); 304 | 305 | Serial.println("48 LOD instructions written."); 306 | Serial.print("Writing HLT to currently unused opcodes (16 total): LOD IMM, [|SPi|IMM] (8) | LOD SPi, [|SPi|IMM] (8) "); 307 | for (uint8_t dreg = SPi; dreg <= IMM; dreg++) { 308 | for (uint8_t sreg = Ra; sreg <= IMM; sreg++) { 309 | 310 | write_instruction(OPCODE(LOD, dreg, sreg), MICROCODE1(_HLT), rom_no); 311 | } 312 | Serial.print("."); 313 | } 314 | Serial.println(" done."); 315 | 316 | } 317 | #endif 318 | 319 | #ifdef INS_STO 320 | void write_STOs(uint8_t rom_no) { 321 | 322 | Serial.print("Writing [reg] <- reg STO instructions "); 323 | for (uint8_t sreg = Ra; sreg <= PC; sreg++) { 324 | 325 | Serial.print("."); 326 | for (uint8_t dreg = Ra; dreg <= PC; dreg++) { 327 | 328 | write_instruction(OPCODE(STO, dreg, sreg), MICROCODE2(_MAW | _E(dreg), _MW | _E(sreg)), rom_no); 329 | } 330 | } 331 | Serial.println(" done."); 332 | 333 | Serial.print("Writing [SPi] <- reg PUSH instructions ."); 334 | for (uint8_t sreg = Ra; sreg <= SP; sreg++) { 335 | 336 | write_instruction(OPCODE(STO, SPi, sreg), MICROCODE3(_SPE | _ALW | ALS(A_MINUS_B), _SPW | _ALE | _MAW, _E(sreg) | _MW), rom_no); 337 | } 338 | Serial.println(". done."); 339 | 340 | Serial.print("Writing CALL instruction ."); 341 | write_instruction(OPCODE(STO, SPi, PC), MICROCODE4(_SPE | _ALW | ALS(A_MINUS_B), _SPW | _ALE | _MAW, _PCE | _MW, _PCW | _RcE), rom_no); 342 | Serial.println(". done."); 343 | 344 | Serial.print("Writing [IMM] <- reg STO instructions ."); 345 | for (uint8_t sreg = Ra; sreg <= PC; sreg++) { 346 | 347 | write_instruction(OPCODE(STO, IMM, sreg), MICROCODE3(_MAW | _PCE | PCC, _ME | PGM | _MAW, _MW | _E(sreg)), rom_no); 348 | } 349 | Serial.println(". done."); 350 | 351 | Serial.println("48 STO instructions written."); 352 | Serial.print("Writing HLT to currently unused opcodes (16 total): STO [|SPi|IMM] <- IMM (8) | STO [|SPi|IMM] <- SPi (8) "); 353 | 354 | for (uint8_t sreg = SPi; sreg <= IMM; sreg++) { 355 | for (uint8_t dreg = Ra; dreg <= IMM; dreg++) { 356 | 357 | write_instruction(OPCODE(STO, dreg, sreg), MICROCODE1(_HLT), rom_no); 358 | } 359 | Serial.print("."); 360 | } 361 | Serial.println(" done."); 362 | } 363 | #endif 364 | 365 | #ifdef INS_ALU 366 | void write_ALU_instructions(uint8_t rom_no) { 367 | 368 | Serial.print("Writing INC reg <- reg + 1 and DEC reg <- reg - 1 instructions ."); 369 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 370 | 371 | write_instruction(ALU_OPCODE(false, INC_A, reg), MICROCODE2(_E(reg) | ALS(A_PLUS_B) | ALC | _ALW, _W(reg) | _ALE), rom_no); 372 | } 373 | Serial.print("."); 374 | 375 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 376 | 377 | write_instruction(ALU_OPCODE(true, INC_A, reg), MICROCODE2(_E(reg) | ALS(A_MINUS_B) | _ALW, _W(reg) | _ALE), rom_no); 378 | } 379 | Serial.println(". done."); 380 | 381 | Serial.print("Writing ADD|ADC reg <- reg + Rb instructions ."); 382 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 383 | 384 | write_instruction(ALU_OPCODE(false, A_PLUS_B, reg), MICROCODE2(_E(reg) | _ALB | ALS(A_PLUS_B) | _ALW, _W(reg) | _ALE), rom_no); 385 | write_carrycond_instruction(ALU_OPCODE(true, A_PLUS_B, reg), false, MICROCODE2(_E(reg) | _ALB | ALS(A_PLUS_B) | _ALW, _W(reg) | _ALE), rom_no); 386 | write_carrycond_instruction(ALU_OPCODE(true, A_PLUS_B, reg), true, MICROCODE2(_E(reg) | _ALB | ALS(A_PLUS_B) | _ALW | ALC, _W(reg) | _ALE), rom_no); 387 | } 388 | Serial.println(". done."); 389 | 390 | Serial.print("Writing SUB|SBC reg <- reg - Rb instructions ."); 391 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 392 | 393 | write_instruction(ALU_OPCODE(false, A_MINUS_B, reg), MICROCODE2(_E(reg) | _ALB | ALC | ALS(A_MINUS_B) | _ALW, _W(reg) | _ALE), rom_no); 394 | write_carrycond_instruction(ALU_OPCODE(true, A_MINUS_B, reg), false, MICROCODE2(_E(reg) | _ALB | ALS(A_MINUS_B) | _ALW, _W(reg) | _ALE), rom_no); 395 | write_carrycond_instruction(ALU_OPCODE(true, A_MINUS_B, reg), true, MICROCODE2(_E(reg) | _ALB | ALS(A_MINUS_B) | _ALW | ALC, _W(reg) | _ALE), rom_no); 396 | } 397 | Serial.println(". done."); 398 | 399 | Serial.print("Writing SUB|SBC reg <- Rb - reg instructions ."); 400 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 401 | 402 | write_instruction(ALU_OPCODE(false, B_MINUS_A, reg), MICROCODE2(_E(reg) | _ALB | ALC | ALS(B_MINUS_A) | _ALW, _W(reg) | _ALE), rom_no); 403 | write_carrycond_instruction(ALU_OPCODE(true, B_MINUS_A, reg), false, MICROCODE2(_E(reg) | _ALB | ALS(B_MINUS_A) | _ALW, _W(reg) | _ALE), rom_no); 404 | write_carrycond_instruction(ALU_OPCODE(true, B_MINUS_A, reg), true, MICROCODE2(_E(reg) | _ALB | ALS(B_MINUS_A) | _ALW | ALC, _W(reg) | _ALE), rom_no); 405 | } 406 | Serial.println(". done."); 407 | 408 | Serial.print("Writing AND reg <- reg & Rb instructions ."); 409 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 410 | 411 | write_instruction(ALU_OPCODE(false, A_AND_B, reg), MICROCODE2(_E(reg) | _ALB | ALS(A_AND_B) | _ALW, _W(reg) | _ALE), rom_no); 412 | } 413 | Serial.println(". done."); 414 | 415 | Serial.print("Writing OR reg <- reg | Rb instructions ."); 416 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 417 | 418 | write_instruction(ALU_OPCODE(false, A_OR_B, reg), MICROCODE2(_E(reg) | _ALB | ALS(A_OR_B) | _ALW, _W(reg) | _ALE), rom_no); 419 | } 420 | Serial.println(". done."); 421 | 422 | Serial.print("Writing XOR reg <- reg ^ Rb instructions ."); 423 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 424 | 425 | write_instruction(ALU_OPCODE(false, A_XOR_B, reg), MICROCODE2(_E(reg) | _ALB | ALS(A_XOR_B) | _ALW, _W(reg) | _ALE), rom_no); 426 | } 427 | Serial.println(". done."); 428 | 429 | Serial.print("Writing NOT reg <- !reg instructions ."); 430 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 431 | 432 | write_instruction(ALU_OPCODE(false, NOT_A, reg), MICROCODE2(_E(reg) | ALS(B_MINUS_A) | _ALW, _W(reg) | _ALE), rom_no); 433 | } 434 | Serial.println(". done."); 435 | 436 | Serial.print("Writing CMP Rb, reg instructions ."); 437 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 438 | 439 | write_instruction(ALU_OPCODE(true, A_OR_B, reg), MICROCODE1(_E(reg) | ALC | _ALB | ALS(B_MINUS_A) | _ALW), rom_no); 440 | } 441 | Serial.println(". done."); 442 | 443 | Serial.print("Writing CMP reg, Rb instructions ."); 444 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 445 | 446 | write_instruction(ALU_OPCODE(true, A_AND_B, reg), MICROCODE1(_E(reg) | ALC | _ALB | ALS(A_MINUS_B) | _ALW), rom_no); 447 | } 448 | Serial.println(". done."); 449 | 450 | Serial.print("Writing TST reg instructions ."); 451 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 452 | 453 | write_instruction(ALU_OPCODE(true, NOT_A, reg), MICROCODE1(_E(reg) | ALS(A_PLUS_B) | _ALW), rom_no); 454 | } 455 | Serial.println(". done."); 456 | 457 | Serial.println("Written 60 ALU instructions."); 458 | Serial.print("Writing HLT to currently unused instructions (4 total): XORC ."); 459 | for (uint8_t reg = Ra; reg <= Rd; reg++) { 460 | write_instruction(ALU_OPCODE(true, A_XOR_B, reg), MICROCODE1(_HLT), rom_no); 461 | } 462 | Serial.println(". done."); 463 | } 464 | #endif 465 | 466 | #ifdef CHECK_COVERAGE 467 | char buf[80]; 468 | #endif 469 | 470 | // the setup function runs once when you press reset or power the board 471 | void setup() { 472 | Serial.begin(115200); 473 | Serial.print("About to program microcode EEPROM no. "); 474 | Serial.print(ROM_NO); 475 | Serial.print(". Press 'y' to continue ... "); 476 | while (Serial.available() <= 0); 477 | char answer = Serial.read(); 478 | Serial.println(answer); 479 | 480 | if (answer == 'y') { 481 | 482 | #ifdef CHECK_COVERAGE 483 | for (uint16_t c=0; c <1024; c++) { 484 | 485 | write_mask[c] = 0; 486 | } 487 | #endif 488 | 489 | MyEEPROM.init(); 490 | 491 | #ifdef INS_MOV 492 | write_MOVs(ROM_NO); 493 | #endif 494 | 495 | #ifdef INS_LOD 496 | write_LODs(ROM_NO); 497 | #endif 498 | 499 | #ifdef INS_STO 500 | write_STOs(ROM_NO); 501 | #endif 502 | 503 | #ifdef INS_ALU 504 | write_ALU_instructions(ROM_NO); 505 | #endif 506 | 507 | #ifdef DUMP 508 | MyEEPROM.dump_eeprom(0, 0x1FFF); 509 | #endif 510 | 511 | #ifdef CHECK_COVERAGE 512 | Serial.println("Output mask"); 513 | for (int c=0; c < 32; c+=16) { 514 | 515 | sprintf(buf, "%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", 516 | write_mask[c], write_mask[c+1], write_mask[c+2], write_mask[c+3], write_mask[c+4], write_mask[c+5], write_mask[c+6], write_mask[c+7], 517 | write_mask[c+8], write_mask[c+9], write_mask[c+10], write_mask[c+11], write_mask[c+12], write_mask[c+13], write_mask[c+14], write_mask[c+15]); 518 | Serial.println(buf); 519 | } 520 | #endif 521 | } 522 | Serial.println("Have a nice day."); 523 | } 524 | 525 | // the loop function runs over and over again forever 526 | void loop() { 527 | } 528 | -------------------------------------------------------------------------------- /arduino/libraries/MyEEPROM/MyEEPROM.cpp: -------------------------------------------------------------------------------- 1 | #include "MyEEPROM.h" 2 | #include "Arduino.h" 3 | #include 4 | 5 | #define PIN_SHCLK 3 6 | #define PIN_STCLK 4 7 | #define PIN_DS 2 8 | 9 | #define PIN_IO0 5 10 | #define PIN_IO1 6 11 | #define PIN_IO2 7 12 | #define PIN_IO3 8 13 | #define PIN_IO4 9 14 | #define PIN_IO5 10 15 | #define PIN_IO6 11 16 | #define PIN_IO7 12 17 | 18 | #define PIN_WE 13 19 | 20 | #define MODE_READ 0x0000 21 | #define MODE_WRITE 0x8000 22 | 23 | static void pulse(int pin) { 24 | 25 | digitalWrite(pin, HIGH); 26 | delay(1); 27 | digitalWrite(pin, LOW); 28 | delay(1); 29 | } 30 | 31 | static void shift_out2(uint16_t value) { 32 | 33 | digitalWrite(PIN_SHCLK, LOW); 34 | digitalWrite(PIN_STCLK, LOW); 35 | shiftOut(PIN_DS, PIN_SHCLK, LSBFIRST, value & 0xFF); 36 | shiftOut(PIN_DS, PIN_SHCLK, LSBFIRST, (value >> 8) & 0xFF); 37 | pulse(PIN_STCLK); 38 | } 39 | 40 | static void set_iopin_mode(int pin_mode) { 41 | 42 | for (int pin = PIN_IO0; pin <= PIN_IO7; pin++) { 43 | 44 | pinMode(pin, pin_mode); 45 | } 46 | } 47 | 48 | static void select_address(uint16_t address, uint16_t mode) { 49 | 50 | if (mode == MODE_READ) { 51 | set_iopin_mode(INPUT); 52 | } 53 | shift_out2(address | mode); 54 | if (mode == MODE_WRITE) { 55 | 56 | set_iopin_mode(OUTPUT); 57 | } 58 | } 59 | 60 | uint8_t MyEEPROM::read_eeprom(uint16_t address) { 61 | 62 | select_address(address, MODE_READ); 63 | delay(2); 64 | uint8_t result = 0; 65 | for (int io_bit=0; io_bit < 8; io_bit++) { 66 | 67 | result |= ((digitalRead(PIN_IO0 + io_bit) == HIGH) ? (1 << io_bit) : 0); 68 | } 69 | 70 | return result; 71 | } 72 | 73 | void MyEEPROM::write_eeprom(uint16_t address, uint8_t value) { 74 | 75 | select_address(address, MODE_WRITE); 76 | for (int io_bit=0; io_bit < 8; io_bit++) { 77 | 78 | digitalWrite(PIN_IO0 + io_bit, value & 1 ? HIGH : LOW); 79 | value >>=1; 80 | } 81 | delay(15); 82 | digitalWrite(PIN_WE, LOW); 83 | delay(1); 84 | digitalWrite(PIN_WE, HIGH); 85 | delay(15); 86 | } 87 | 88 | void MyEEPROM::init() { 89 | pinMode(PIN_WE, OUTPUT); 90 | digitalWrite(PIN_WE, HIGH); 91 | pinMode(PIN_DS, OUTPUT); 92 | pinMode(PIN_SHCLK, OUTPUT); 93 | pinMode(PIN_STCLK, OUTPUT); 94 | } 95 | 96 | void MyEEPROM::dump_eeprom(uint16_t start_address, uint16_t end_address) { 97 | 98 | char output_buffer[80]; 99 | 100 | start_address &= 0xFFF0; 101 | end_address |= 0xF; 102 | 103 | for (uint16_t address = start_address; address < end_address; address+=0x10) { 104 | 105 | sprintf(output_buffer, "%04x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", 106 | address, 107 | read_eeprom(address), 108 | read_eeprom(address + 1), 109 | read_eeprom(address + 2), 110 | read_eeprom(address + 3), 111 | read_eeprom(address + 4), 112 | read_eeprom(address + 5), 113 | read_eeprom(address + 6), 114 | read_eeprom(address + 7), 115 | read_eeprom(address + 8), 116 | read_eeprom(address + 9), 117 | read_eeprom(address + 10), 118 | read_eeprom(address + 11), 119 | read_eeprom(address + 12), 120 | read_eeprom(address + 13), 121 | read_eeprom(address + 14), 122 | read_eeprom(address + 15)); 123 | Serial.println(output_buffer); 124 | } 125 | } 126 | 127 | class MyEEPROM MyEEPROM; 128 | -------------------------------------------------------------------------------- /arduino/libraries/MyEEPROM/MyEEPROM.h: -------------------------------------------------------------------------------- 1 | #ifndef _MYEEPROM_H 2 | #define _MYEEPROM_H 3 | 4 | extern class MyEEPROM { 5 | public: 6 | void init(); 7 | static unsigned char read_eeprom(unsigned int address); 8 | void write_eeprom(unsigned int address, unsigned char value); 9 | void dump_eeprom(unsigned int start_address, unsigned int end_address); 10 | } MyEEPROM; 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /assembler/Makefile: -------------------------------------------------------------------------------- 1 | OBJS = assembler.tab.o assembler.yy.o parsenode.o asmerror.o directive.o symbols.o instruction.o 2 | assembler: $(OBJS) 3 | $(CC) -o $@ $(OBJS) 4 | 5 | .c.o: 6 | $(CC) -c -O2 -o $@ $< 7 | 8 | assembler.yy.c: assembler.l assembler.tab.c 9 | flex -o $@ assembler.l 10 | 11 | assembler.tab.c: assembler.y 12 | bison -d assembler.y 13 | 14 | clean: 15 | rm -f assembler assembler.yy.c assembler.tab.c assembler.tab.h $(OBJS) 16 | 17 | .PHONY: clean 18 | 19 | -------------------------------------------------------------------------------- /assembler/asmerror.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | #include "asmerror.h" 7 | 8 | unsigned int lineno = 1; 9 | 10 | void asmerror(char *reason, char *param) { 11 | 12 | if (param) { 13 | 14 | char *fullreason = (char *) malloc(strlen(reason) + strlen(param)); 15 | sprintf(fullreason, reason, param); 16 | fprintf(stderr, "Line %d: error: %s\n", lineno, fullreason); 17 | free(fullreason); 18 | } else { 19 | 20 | fprintf(stderr, "Line %d: error: %s\n", lineno, reason); 21 | } 22 | exit(1); 23 | } 24 | -------------------------------------------------------------------------------- /assembler/asmerror.h: -------------------------------------------------------------------------------- 1 | #ifndef _ASMERROR_H 2 | #define _ASMERROR_H 3 | 4 | extern unsigned int lineno; 5 | 6 | void asmerror(char *reason, char *param); 7 | 8 | #endif 9 | 10 | -------------------------------------------------------------------------------- /assembler/assembler.l: -------------------------------------------------------------------------------- 1 | %{ 2 | #include 3 | #include 4 | #include 5 | 6 | #include "parsenode.h" 7 | 8 | #define YYSTYPE union parsenode * 9 | 10 | #include "assembler.tab.h" 11 | 12 | char *stolower(char *in) { 13 | 14 | for (char *c = in; (*c) != '\0'; c++) { 15 | 16 | (*c) = tolower(*c); 17 | } 18 | 19 | return in; 20 | } 21 | 22 | 23 | 24 | %} 25 | 26 | %% 27 | \n return NEWLINE; 28 | [A-Za-z\_][A-Za-z0-9\_]* yylval=parsenode_identifier(stolower(strdup(yytext))); return IDENTIFIER; 29 | [0-9]+ yylval=parsenode_value(atoi(yytext)); return NUMBER; 30 | \# return HASH; 31 | \: return COLON; 32 | \, return COMMA; 33 | \. return PERIOD; 34 | \[ return LSQBRACKET; 35 | \] return RSQBRACKET; 36 | \;[^\n]* /* comment: ignore */ 37 | [ \r\t]+ /* whitespace: ignore */; 38 | %% 39 | 40 | -------------------------------------------------------------------------------- /assembler/assembler.y: -------------------------------------------------------------------------------- 1 | %{ 2 | #include 3 | #include 4 | 5 | #include "parsenode.h" 6 | #include "asmerror.h" 7 | #include "instruction.h" 8 | #include "directive.h" 9 | 10 | #define YYSTYPE union parsenode * 11 | 12 | int yylex(); 13 | int yyparse(void); 14 | 15 | void yyerror(const char *str) 16 | { 17 | fprintf(stderr,"Line %d: error: %s\n",lineno,str); 18 | } 19 | 20 | int yywrap() 21 | { 22 | return 1; 23 | } 24 | 25 | int main(void) 26 | { 27 | yyparse(); 28 | assemble_program(); 29 | output_program(); 30 | } 31 | 32 | %} 33 | 34 | %token PERIOD IDENTIFIER NUMBER NEWLINE COLON HASH COMMA LSQBRACKET RSQBRACKET 35 | 36 | 37 | %% 38 | program: 39 | /* empty */ 40 | | 41 | program empty 42 | { 43 | lineno++; 44 | } 45 | | 46 | program line 47 | { 48 | handle_instruction(&$2->instruction); 49 | lineno++; 50 | } 51 | | 52 | program directive 53 | { 54 | lineno++; 55 | } 56 | ; 57 | 58 | empty: 59 | NEWLINE 60 | ; 61 | 62 | directive: 63 | PERIOD IDENTIFIER NUMBER NEWLINE 64 | { 65 | handle_directive($2->identifier, NULL, $3->value); 66 | } 67 | | 68 | PERIOD IDENTIFIER IDENTIFIER COMMA NUMBER NEWLINE 69 | { 70 | handle_directive($2->identifier, $3->identifier, $5->value); 71 | } 72 | ; 73 | 74 | line: 75 | label simpleline NEWLINE 76 | { 77 | $$ = $2; 78 | $2->instruction.label = $1->identifier; 79 | } 80 | | 81 | simpleline NEWLINE 82 | { 83 | $$ = $1; 84 | } 85 | ; 86 | 87 | simpleline: 88 | instruction 89 | { 90 | $$ = $1; 91 | } 92 | | 93 | literal_instruction 94 | { 95 | $$ = $1; 96 | } 97 | ; 98 | 99 | label: 100 | IDENTIFIER COLON 101 | { 102 | $$ = $1; 103 | } 104 | ; 105 | 106 | literal_instruction: 107 | num_literal 108 | { 109 | $$ = parsenode_instruction1(LITERAL, parsenode_immval_operand($1->value)); 110 | } 111 | | 112 | symbol_literal 113 | { 114 | $$ = parsenode_instruction1(LITERAL, parsenode_immsymbol_operand($1->identifier)); 115 | } 116 | ; 117 | 118 | symbol_literal: 119 | HASH IDENTIFIER 120 | { 121 | $$ = $2; 122 | } 123 | ; 124 | 125 | num_literal: 126 | HASH NUMBER 127 | { 128 | $$ = $2; 129 | } 130 | ; 131 | 132 | instruction: 133 | mnemonic 134 | { 135 | $$ = parsenode_instruction0(mnemonic($1->identifier)); 136 | } 137 | | 138 | mnemonic operand 139 | { 140 | $$ = parsenode_instruction1(mnemonic($1->identifier), $2); 141 | } 142 | | 143 | mnemonic operand COMMA operand 144 | { 145 | $$ = parsenode_instruction2(mnemonic($1->identifier), $2, $4); 146 | } 147 | ; 148 | 149 | mnemonic: 150 | IDENTIFIER 151 | { 152 | $$ = $1; 153 | } 154 | ; 155 | 156 | operand: 157 | direct_operand 158 | { 159 | $$ = $1; 160 | } 161 | | 162 | indirect_operand 163 | { 164 | $$ = $1; 165 | } 166 | ; 167 | 168 | direct_operand: 169 | register 170 | { 171 | $$ = parsenode_reg_operand(reg($1->identifier)); 172 | } 173 | | 174 | symbol_literal 175 | { 176 | $$ = parsenode_immsymbol_operand($1->identifier); 177 | } 178 | | 179 | num_literal 180 | { 181 | $$ = parsenode_immval_operand($1->value); 182 | } 183 | ; 184 | 185 | register: 186 | IDENTIFIER 187 | { 188 | $$ = $1; 189 | } 190 | ; 191 | 192 | indirect_operand: 193 | LSQBRACKET direct_operand RSQBRACKET 194 | { 195 | $$ = $2; 196 | $$->operand.is_indirect = true; 197 | } 198 | ; 199 | 200 | -------------------------------------------------------------------------------- /assembler/directive.c: -------------------------------------------------------------------------------- 1 | #include "directive.h" 2 | #include "instruction.h" 3 | #include "symbols.h" 4 | 5 | #include "asmerror.h" 6 | #include 7 | #include 8 | 9 | void handle_directive(char *directive, char *symbol, uint8_t value) { 10 | 11 | if (!strcmp(directive, "org")) { 12 | 13 | if (symbol != NULL) { 14 | 15 | asmerror(".org directive accepts only one operand", NULL); 16 | } 17 | 18 | if (value < out_address) { 19 | 20 | char buf[5]; 21 | sprintf(buf, "%d", value); 22 | 23 | asmerror("Cannot decrease output address to %s", buf); 24 | } 25 | 26 | out_address = value; 27 | } else if (!strcmp(directive, "equ")) { 28 | 29 | if (symbol == NULL) { 30 | 31 | asmerror(".equ directive requires two operands", NULL); 32 | } 33 | 34 | add_symbol(symbol, value); 35 | } else { 36 | 37 | asmerror("Unknown directive .%s", directive); 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /assembler/directive.h: -------------------------------------------------------------------------------- 1 | #ifndef _DIRECTIVE_H 2 | #define _DIRECTIVE_H 3 | 4 | #include 5 | 6 | void handle_directive(char *directive, char *symbol, uint8_t param); 7 | 8 | #endif 9 | 10 | -------------------------------------------------------------------------------- /assembler/instruction.c: -------------------------------------------------------------------------------- 1 | #include "instruction.h" 2 | #include 3 | #include "asmerror.h" 4 | #include "symbols.h" 5 | 6 | unsigned int out_address = 0; 7 | unsigned int instruction_count = 0; 8 | 9 | struct instruction instructions[256]; 10 | 11 | 12 | #define is_imm(o) (o.type == IMMEDIATE_VAL || o.type == IMMEDIATE_SYMBOL) 13 | #define is_alu(o) ((!o.is_indirect) && o.type == REGISTER && (o.value.reg == RA || o.value.reg == RB || o.value.reg == RC || o.value.reg == RD)) 14 | 15 | void check_instruction_operands(struct instruction *i) { 16 | 17 | if (is_imm(i->l_operand) && is_imm(i->r_operand)) { 18 | 19 | asmerror("Instruction cannot have two immediate operands", NULL); 20 | } 21 | 22 | switch(i->mnemonic) { 23 | 24 | case HLT: 25 | case NOP: 26 | case RET: 27 | if ((i->l_operand.type != NONE) || (i->r_operand.type != NONE)) { 28 | 29 | asmerror("Instruction does not support operands", NULL); 30 | } 31 | break; 32 | case JC: 33 | case JN: 34 | case JZ: 35 | case JO: 36 | case LITERAL: 37 | if ((i->r_operand.type != NONE) || (!is_imm(i->l_operand)) || (i->l_operand.is_indirect)) { 38 | 39 | asmerror("Instruction requires one direct immediate operand", NULL); 40 | } 41 | break; 42 | case JMP: 43 | case PUSH: 44 | if ((i->l_operand.type == NONE) || (i->r_operand.type != NONE) || (i->l_operand.is_indirect)) { 45 | 46 | asmerror("Instruction requires one direct immediate or register operand", NULL); 47 | } 48 | break; 49 | case POP: 50 | if ((i->l_operand.type != REGISTER) || (i->r_operand.type != NONE) || (i->l_operand.is_indirect)) { 51 | 52 | asmerror("Instruction requires one direct register operand", NULL); 53 | } 54 | break; 55 | case CALL: 56 | if ((i->l_operand.type != REGISTER) || (i->r_operand.type != NONE) || (i->l_operand.is_indirect) || (i->l_operand.value.reg != RC)) { 57 | 58 | asmerror("Instruction requires single Rc operand", NULL); 59 | } 60 | break; 61 | case NOT: 62 | case INC: 63 | case DEC: 64 | case TST: 65 | if ((!is_alu(i->l_operand)) || (i->r_operand.type != NONE)) { 66 | 67 | asmerror("Instruction requires single direct ALU register operand", NULL); 68 | } 69 | break; 70 | case MOV: 71 | if ((i->l_operand.type != REGISTER) || (i->l_operand.is_indirect) || (i->r_operand.type != REGISTER) || (i->r_operand.is_indirect)) { 72 | 73 | asmerror("Instruction requires two direct register operands", NULL); 74 | } 75 | break; 76 | case DATA: 77 | if ((i->l_operand.type != REGISTER) || (i->l_operand.is_indirect) || (!is_imm(i->r_operand)) || (i->r_operand.is_indirect)) { 78 | 79 | asmerror("Instruction requires one direct register and one direct immediate operand", NULL); 80 | } 81 | break; 82 | case LOD: 83 | if ((i->l_operand.type != REGISTER) || (i->l_operand.is_indirect) || (i->r_operand.type == NONE) || (!i->r_operand.is_indirect)) { 84 | 85 | asmerror("Instruction requires one direct register and one indirect operand", NULL); 86 | } 87 | break; 88 | case STO: 89 | if ((i->l_operand.type == NONE) || (!i->l_operand.is_indirect) || (i->r_operand.type == NONE) || (i->r_operand.is_indirect)) { 90 | 91 | asmerror("Instruction requires one indirect and one direct operand", NULL); 92 | } 93 | break; 94 | case ADD: 95 | case ADC: 96 | case AND: 97 | case OR: 98 | case XOR: 99 | if ((!is_alu(i->l_operand)) || (!is_alu(i->r_operand)) || (i->r_operand.value.reg != RB)) { 100 | 101 | asmerror("Instruction requires direct ALU register and RB operands", NULL); 102 | } 103 | break; 104 | case SUB: 105 | case SBC: 106 | case CMP: 107 | if ((!is_alu(i->l_operand)) || (!is_alu(i->r_operand)) || ((i->r_operand.value.reg != RB) && (i->l_operand.value.reg != RB))) { 108 | 109 | asmerror("Instruction requires direct ALU register and RB operands", NULL); 110 | } 111 | break; 112 | default: 113 | asmerror("Unrecognized instruction.", NULL); 114 | } 115 | } 116 | 117 | 118 | 119 | 120 | void handle_instruction(struct instruction *i) { 121 | 122 | check_instruction_operands(i); 123 | 124 | if (out_address >= 256) { 125 | char buf[5]; 126 | sprintf(buf, "%d", out_address); 127 | 128 | asmerror("Memory overflow. Address %s exceeds memory limit(256 bytes).", buf); 129 | } 130 | i->address = out_address; 131 | if (i->label) { 132 | 133 | add_symbol(i->label, i->address); 134 | } 135 | 136 | if ((i->mnemonic != LITERAL) && (is_imm(i->l_operand) || is_imm(i->r_operand))) { 137 | 138 | i->length = 2; 139 | } else { 140 | 141 | i->length = 1; 142 | } 143 | 144 | out_address += i->length; 145 | 146 | instructions[instruction_count++] = (*i); 147 | } 148 | 149 | #define CLASS_MOV 0b00000000; 150 | #define CLASS_LOD 0b01000000; 151 | #define CLASS_STO 0b10000000; 152 | #define CLASS_ALU 0b11000000; 153 | 154 | static inline uint8_t reg_code(enum reg reg) { 155 | 156 | switch (reg) { 157 | 158 | case RA: return 0b000; 159 | case RB: return 0b001; 160 | case RC: return 0b010; 161 | case RD: return 0b011; 162 | case SP: return 0b100; 163 | case PC: return 0b101; 164 | } 165 | } 166 | 167 | #define SREG(reg) reg_code(reg) 168 | #define DREG(reg) (reg_code(reg) << 3) 169 | #define SIMM 0b111 170 | #define DIMM 0b111000 171 | #define SSPi 0b110 172 | #define DSPi 0b110000 173 | #define ALU(carry, S) ((carry ? 0b00100000 : 0) | (S << 2)) 174 | 175 | static uint8_t instruction_class(enum mnemonic mnemonic) { 176 | 177 | switch (mnemonic) { 178 | 179 | case NOP: 180 | case HLT: 181 | case MOV: 182 | case DATA: 183 | case JMP: 184 | case JC: 185 | case JZ: 186 | case JN: 187 | case JO: 188 | return CLASS_MOV; 189 | case LOD: 190 | case POP: 191 | case RET: 192 | return CLASS_LOD; 193 | case STO: 194 | case PUSH: 195 | case CALL: 196 | return CLASS_STO; 197 | case ADD: 198 | case ADC: 199 | case SUB: 200 | case SBC: 201 | case INC: 202 | case DEC: 203 | case XOR: 204 | case OR: 205 | case AND: 206 | case NOT: 207 | case CMP: 208 | case TST: 209 | return CLASS_ALU; 210 | } 211 | } 212 | 213 | static void assemble_imm(uint8_t *dest, struct operand *o) { 214 | 215 | if (o->type == IMMEDIATE_SYMBOL) { 216 | 217 | unsigned int v = find_symbol(o->value.immsymbol); 218 | if (v == -1) { 219 | 220 | asmerror("Undefined symbol %s", o->value.immsymbol); 221 | } 222 | *dest = v; 223 | } else { 224 | 225 | *dest = o->value.immvalue; 226 | } 227 | } 228 | 229 | 230 | 231 | static void assemble_dest_operand(struct instruction *i) { 232 | 233 | switch (i->mnemonic) { 234 | case MOV: 235 | case LOD: 236 | case STO: 237 | case POP: 238 | case DATA: 239 | if (is_imm(i->l_operand)) { 240 | i->byte0 |= DIMM; 241 | } else { 242 | i->byte0 |= DREG(i->l_operand.value.reg); 243 | } 244 | return; 245 | case PUSH: 246 | case CALL: 247 | i->byte0 |= DSPi; 248 | return; 249 | case JMP: 250 | case RET: 251 | case HLT: 252 | i->byte0 |= DREG(PC); 253 | return; 254 | case NOP: 255 | i->byte0 |= DREG(RA); 256 | return; 257 | case JZ: 258 | case JO: 259 | case JN: 260 | case JC: 261 | i->byte0 |= DIMM; 262 | return; 263 | /* ALU operations*/ 264 | case SUB: 265 | case SBC: 266 | case CMP: 267 | i->byte0 |= (SREG((i->l_operand.value.reg != RB) ? i->l_operand.value.reg : i->r_operand.value.reg)); 268 | return; 269 | default: 270 | i->byte0 |= SREG(i->l_operand.value.reg); 271 | } 272 | } 273 | 274 | 275 | static void assemble_src_operand(struct instruction *i) { 276 | switch (i->mnemonic) { 277 | case MOV: 278 | case LOD: 279 | case STO: 280 | case DATA: 281 | if (is_imm(i->r_operand)) { 282 | i->byte0 |= SIMM; 283 | } else { 284 | i->byte0 |= SREG(i->r_operand.value.reg); 285 | } 286 | return; 287 | case PUSH: 288 | case JMP: 289 | if (is_imm(i->l_operand)) { 290 | i->byte0 |= SIMM; 291 | } else { 292 | i->byte0 |= SREG(i->l_operand.value.reg); 293 | } 294 | return; 295 | case CALL: 296 | case HLT: 297 | i->byte0 |= SREG(PC); 298 | return; 299 | case POP: 300 | case RET: 301 | i->byte0 |= SSPi; 302 | return; 303 | case NOP: 304 | i->byte0 |= SREG(RA); 305 | return; 306 | case JZ: 307 | i->byte0 |= 0b001; 308 | return; 309 | case JO: 310 | i->byte0 |= 0b100; 311 | return; 312 | case JN: 313 | i->byte0 |= 0b010; 314 | return; 315 | case JC: 316 | i->byte0 |= 0b000; 317 | return; 318 | } 319 | } 320 | 321 | static void assemble_alu_instruction(struct instruction *i) { 322 | switch (i->mnemonic) { 323 | 324 | case ADD: 325 | i->byte0 |= ALU(false,0b011); 326 | return; 327 | case ADC: 328 | i->byte0 |= ALU(true,0b011); 329 | return; 330 | case TST: 331 | i->byte0 |= ALU(true,0b111); 332 | return; 333 | case SUB: 334 | i->byte0 |= ALU(false, ((i->l_operand.value.reg != RB) ? 0b010 : 0b001)); 335 | return; 336 | case SBC: 337 | i->byte0 |= ALU(true, ((i->l_operand.value.reg != RB) ? 0b010 : 0b001)); 338 | return; 339 | case CMP: 340 | i->byte0 |= ALU(true, ((i->l_operand.value.reg != RB) ? 0b110 : 0b101)); 341 | return; 342 | case INC: 343 | i->byte0 |= ALU(false, 0b000); 344 | return; 345 | case DEC: 346 | i->byte0 |= ALU(true, 0b000); 347 | return; 348 | case XOR: 349 | i->byte0 |= ALU(false, 0b100); 350 | return; 351 | case OR: 352 | i->byte0 |= ALU(false, 0b101); 353 | return; 354 | case AND: 355 | i->byte0 |= ALU(false, 0b110); 356 | return; 357 | case NOT: 358 | i->byte0 |= ALU(false, 0b111); 359 | return; 360 | } 361 | } 362 | 363 | 364 | static void assemble_instruction(struct instruction *i) { 365 | 366 | if (i->mnemonic == LITERAL) { 367 | 368 | assemble_imm(&i->byte0, &i->l_operand); 369 | return; 370 | } 371 | 372 | i->byte0 = instruction_class(i->mnemonic); 373 | 374 | assemble_dest_operand(i); 375 | assemble_src_operand(i); 376 | assemble_alu_instruction(i); 377 | 378 | if (is_imm(i->l_operand)) { 379 | 380 | assemble_imm(&i->byte1, &i->l_operand); 381 | } 382 | 383 | if (is_imm(i->r_operand)) { 384 | 385 | assemble_imm(&i->byte1, &i->r_operand); 386 | } 387 | } 388 | 389 | void assemble_program() { 390 | 391 | for (int c=0; c < instruction_count; c++) { 392 | 393 | assemble_instruction(&instructions[c]); 394 | } 395 | } 396 | 397 | 398 | 399 | 400 | static void print_binary(uint8_t number) 401 | { 402 | for (int8_t bit = 7; bit >=0; bit--) { 403 | printf("%c", (number & (1 << bit)) ? '1' : '0'); 404 | } 405 | } 406 | 407 | static void print_mnemonic(enum mnemonic mnemonic) { 408 | 409 | switch (mnemonic) { 410 | 411 | case NOP: 412 | printf("NOP"); 413 | break; 414 | case HLT: 415 | printf("HLT"); 416 | break; 417 | case MOV: 418 | printf("MOV "); 419 | break; 420 | case DATA: 421 | printf("DATA "); 422 | break; 423 | case JMP: 424 | printf("JMP "); 425 | break; 426 | case JC: 427 | printf("JC "); 428 | break; 429 | case JZ: 430 | printf("JZ "); 431 | break; 432 | case JN: 433 | printf("JN "); 434 | break; 435 | case JO: 436 | printf("JO "); 437 | break; 438 | case LOD: 439 | printf("LOD "); 440 | break; 441 | case POP: 442 | printf("POP "); 443 | break; 444 | case RET: 445 | printf("RET"); 446 | break; 447 | case STO: 448 | printf("STO "); 449 | break; 450 | case PUSH: 451 | printf("PUSH "); 452 | break; 453 | case CALL: 454 | printf("CALL "); 455 | break; 456 | case ADD: 457 | printf("ADD "); 458 | break; 459 | case ADC: 460 | printf("ADC "); 461 | break; 462 | case SUB: 463 | printf("SUB "); 464 | break; 465 | case SBC: 466 | printf("SBC "); 467 | break; 468 | case INC: 469 | printf("INC "); 470 | break; 471 | case DEC: 472 | printf("DEC "); 473 | break; 474 | case XOR: 475 | printf("XOR "); 476 | break; 477 | case OR: 478 | printf("OR "); 479 | break; 480 | case AND: 481 | printf("AND "); 482 | break; 483 | case NOT: 484 | printf("NOT "); 485 | break; 486 | case CMP: 487 | printf("CMP "); 488 | break; 489 | case TST: 490 | printf("TST "); 491 | break; 492 | case LITERAL: 493 | printf(""); 494 | break; 495 | } 496 | } 497 | 498 | static void print_register(enum reg reg) { 499 | 500 | switch(reg) { 501 | 502 | case RA: 503 | printf("Ra"); 504 | break; 505 | case RB: 506 | printf("Rb"); 507 | break; 508 | case RC: 509 | printf("Rc"); 510 | break; 511 | case RD: 512 | printf("Rd"); 513 | break; 514 | case SP: 515 | printf("SP"); 516 | break; 517 | case PC: 518 | printf("PC"); 519 | break; 520 | } 521 | } 522 | 523 | static void print_operand(struct operand *o) { 524 | 525 | if (o->is_indirect) { 526 | 527 | printf("["); 528 | } 529 | 530 | if (o->type == REGISTER) { 531 | 532 | print_register(o->value.reg); 533 | } else if (o->type == IMMEDIATE_VAL) { 534 | 535 | printf("#%d", o->value.immvalue); 536 | } else { 537 | 538 | printf("#%s", o->value.immsymbol); 539 | } 540 | 541 | if (o->is_indirect) { 542 | 543 | printf("]"); 544 | } 545 | } 546 | 547 | static void print_instruction(struct instruction *i) { 548 | if (i->label) { 549 | printf("%s:\t", i->label); 550 | } else { 551 | printf("\t"); 552 | } 553 | 554 | print_mnemonic(i->mnemonic); 555 | if (i->l_operand.type != NONE) { 556 | 557 | print_operand(&i->l_operand); 558 | if (i->r_operand.type != NONE) { 559 | 560 | printf(", "); 561 | print_operand(&i->r_operand); 562 | } 563 | } 564 | printf("\n"); 565 | } 566 | 567 | 568 | static void output_instruction(struct instruction *i) { 569 | 570 | printf("%03d [", i->address); 571 | print_binary(i->address); 572 | printf("] "); 573 | print_binary(i->byte0); 574 | printf(" //\t"); 575 | print_instruction(i); 576 | if (i->length == 2) { 577 | 578 | printf("%03d [", i->address+1); 579 | print_binary(i->address+1); 580 | printf("] "); 581 | print_binary(i->byte1); 582 | printf("\n"); 583 | } 584 | } 585 | 586 | void output_program() { 587 | 588 | for (int c=0; c < instruction_count; c++) { 589 | 590 | output_instruction(&instructions[c]); 591 | } 592 | } 593 | 594 | 595 | 596 | 597 | 598 | -------------------------------------------------------------------------------- /assembler/instruction.h: -------------------------------------------------------------------------------- 1 | #ifndef _INSTRUCTION_H 2 | #define _INSTRUCTION_H 3 | 4 | #include "parsenode.h" 5 | 6 | extern unsigned int out_address; 7 | 8 | void handle_instruction(struct instruction *i); 9 | void assemble_program(void); 10 | void output_program(void); 11 | 12 | #endif 13 | 14 | -------------------------------------------------------------------------------- /assembler/parsenode.c: -------------------------------------------------------------------------------- 1 | #include "parsenode.h" 2 | 3 | #include 4 | #include 5 | 6 | #include "asmerror.h" 7 | 8 | enum reg reg(char *regname) { 9 | 10 | if (strcmp("ra",regname)==0) { 11 | 12 | return RA; 13 | } 14 | if (strcmp("rb",regname)==0) { 15 | 16 | return RB; 17 | } 18 | if (strcmp("rc",regname)==0) { 19 | 20 | return RC; 21 | } 22 | if (strcmp("rd",regname)==0) { 23 | 24 | return RD; 25 | } 26 | if (strcmp("sp",regname)==0) { 27 | 28 | return SP; 29 | } 30 | if (strcmp("pc",regname)==0) { 31 | 32 | return PC; 33 | } 34 | asmerror("Unknown register %s", regname); 35 | return RA; 36 | } 37 | 38 | enum mnemonic mnemonic(char *name) { 39 | 40 | if (strcmp("data",name)==0) { 41 | 42 | return DATA; 43 | } 44 | if (strcmp("mov",name)==0) { 45 | 46 | return MOV; 47 | } 48 | if (strcmp("nop",name)==0) { 49 | 50 | return NOP; 51 | } 52 | if (strcmp("hlt",name)==0) { 53 | 54 | return HLT; 55 | } 56 | if (strcmp("jmp",name)==0) { 57 | 58 | return JMP; 59 | } 60 | if (strcmp("jc",name)==0) { 61 | 62 | return JC; 63 | } 64 | if (strcmp("jz",name)==0) { 65 | 66 | return JZ; 67 | } 68 | if (strcmp("jn",name)==0) { 69 | 70 | return JN; 71 | } 72 | if (strcmp("jo",name)==0) { 73 | 74 | return JO; 75 | } 76 | if (strcmp("lod",name)==0) { 77 | 78 | return LOD; 79 | } 80 | if (strcmp("pop",name)==0) { 81 | 82 | return POP; 83 | } 84 | if (strcmp("ret",name)==0) { 85 | 86 | return RET; 87 | } 88 | if (strcmp("sto",name)==0) { 89 | 90 | return STO; 91 | } 92 | if (strcmp("push",name)==0) { 93 | 94 | return PUSH; 95 | } 96 | if (strcmp("call",name)==0) { 97 | 98 | return CALL; 99 | } 100 | if (strcmp("add",name)==0) { 101 | 102 | return ADD; 103 | } 104 | if (strcmp("adc",name)==0) { 105 | 106 | return ADC; 107 | } 108 | if (strcmp("sub",name)==0) { 109 | 110 | return SUB; 111 | } 112 | if (strcmp("sbc",name)==0) { 113 | 114 | return SBC; 115 | } 116 | if (strcmp("inc",name)==0) { 117 | 118 | return INC; 119 | } 120 | if (strcmp("dec",name)==0) { 121 | 122 | return DEC; 123 | } 124 | if (strcmp("xor",name)==0) { 125 | 126 | return XOR; 127 | } 128 | if (strcmp("or",name)==0) { 129 | 130 | return OR; 131 | } 132 | if (strcmp("and",name)==0) { 133 | 134 | return AND; 135 | } 136 | if (strcmp("not",name)==0) { 137 | 138 | return NOT; 139 | } 140 | if (strcmp("cmp",name)==0) { 141 | 142 | return CMP; 143 | } 144 | if (strcmp("tst",name)==0) { 145 | 146 | return TST; 147 | } 148 | asmerror("Unknown instruction %s", name); 149 | return NOP; 150 | } 151 | 152 | union parsenode *parsenode_identifier(char *s) { 153 | 154 | union parsenode *r = (union parsenode *) malloc(sizeof(union parsenode)); 155 | r->identifier = s; 156 | return r; 157 | } 158 | 159 | union parsenode *parsenode_value(uint8_t value) { 160 | 161 | union parsenode *r = (union parsenode *) malloc(sizeof(union parsenode)); 162 | r->value = value; 163 | return r; 164 | } 165 | 166 | union parsenode *parsenode_reg_operand(enum reg reg) { 167 | 168 | union parsenode *r = (union parsenode *) malloc(sizeof(union parsenode)); 169 | r->operand.type = REGISTER; 170 | r->operand.is_indirect = false; 171 | r->operand.value.reg = reg; 172 | return r; 173 | } 174 | 175 | union parsenode *parsenode_immval_operand(uint8_t value) { 176 | 177 | union parsenode *r = (union parsenode *) malloc(sizeof(union parsenode)); 178 | r->operand.type = IMMEDIATE_VAL; 179 | r->operand.is_indirect = false; 180 | r->operand.value.immvalue = value; 181 | return r; 182 | } 183 | 184 | union parsenode *parsenode_immsymbol_operand(char *symbol) { 185 | 186 | union parsenode *r = (union parsenode *) malloc(sizeof(union parsenode)); 187 | r->operand.type = IMMEDIATE_SYMBOL; 188 | r->operand.is_indirect = false; 189 | r->operand.value.immsymbol = symbol; 190 | return r; 191 | } 192 | 193 | union parsenode *parsenode_instruction0(enum mnemonic mnemonic) { 194 | 195 | union parsenode *r = (union parsenode *) malloc(sizeof(union parsenode)); 196 | r->instruction.mnemonic = mnemonic; 197 | r->instruction.l_operand.type = NONE; 198 | r->instruction.r_operand.type = NONE; 199 | r->instruction.label = NULL; 200 | return r; 201 | } 202 | 203 | union parsenode *parsenode_instruction1(enum mnemonic mnemonic, union parsenode *operand) { 204 | 205 | union parsenode *r = (union parsenode *) malloc(sizeof(union parsenode)); 206 | r->instruction.mnemonic = mnemonic; 207 | r->instruction.l_operand = operand->operand; 208 | free(operand); 209 | r->instruction.r_operand.type = NONE; 210 | r->instruction.label = NULL; 211 | return r; 212 | } 213 | 214 | union parsenode *parsenode_instruction2(enum mnemonic mnemonic, union parsenode *l_operand, union parsenode *r_operand) { 215 | 216 | union parsenode *r = (union parsenode *) malloc(sizeof(union parsenode)); 217 | r->instruction.mnemonic = mnemonic; 218 | r->instruction.l_operand = l_operand->operand; 219 | free(l_operand); 220 | r->instruction.r_operand = r_operand->operand; 221 | free(r_operand); 222 | r->instruction.label = NULL; 223 | return r; 224 | } 225 | -------------------------------------------------------------------------------- /assembler/parsenode.h: -------------------------------------------------------------------------------- 1 | #ifndef _PARSENODE_H 2 | #define _PARSENODE_H 3 | 4 | #include 5 | #include 6 | 7 | enum reg {RA,RB,RC,RD,PC,SP}; 8 | enum reg reg(char *regname); 9 | 10 | enum operand_type {NONE, REGISTER, IMMEDIATE_VAL, IMMEDIATE_SYMBOL}; 11 | 12 | struct operand { 13 | enum operand_type type; 14 | bool is_indirect; 15 | union operand_value { 16 | enum reg reg; 17 | uint8_t immvalue; 18 | char *immsymbol; 19 | } value; 20 | }; 21 | 22 | enum mnemonic { 23 | DATA,MOV,JMP,JC,JN,JZ,JO,NOP,HLT, 24 | LOD,POP,RET, 25 | STO,PUSH,CALL, 26 | INC,DEC,ADD,ADC,SUB,SBC,XOR,OR,AND,NOT,CMP,TST, 27 | LITERAL 28 | }; 29 | enum mnemonic mnemonic(char *name); 30 | 31 | struct instruction { 32 | enum mnemonic mnemonic; 33 | struct operand l_operand; 34 | struct operand r_operand; 35 | char *label; 36 | unsigned int address; 37 | uint8_t length; 38 | uint8_t byte0; 39 | uint8_t byte1; 40 | }; 41 | 42 | union parsenode { 43 | char *identifier; 44 | uint8_t value; 45 | struct operand operand; 46 | struct instruction instruction; 47 | }; 48 | 49 | union parsenode *parsenode_identifier(char *s); 50 | union parsenode *parsenode_value(uint8_t value); 51 | union parsenode *parsenode_reg_operand(enum reg reg); 52 | union parsenode *parsenode_immval_operand(uint8_t value); 53 | union parsenode *parsenode_immsymbol_operand(char *symbol); 54 | union parsenode *parsenode_instruction0(enum mnemonic mnemonic); 55 | union parsenode *parsenode_instruction1(enum mnemonic mnemonic, union parsenode *operand); 56 | union parsenode *parsenode_instruction2(enum mnemonic mnemonic, union parsenode *l_operand, union parsenode *r_operand); 57 | 58 | #endif 59 | 60 | -------------------------------------------------------------------------------- /assembler/symbols.c: -------------------------------------------------------------------------------- 1 | #include "symbols.h" 2 | #include "asmerror.h" 3 | #include 4 | 5 | unsigned int symbol_t_size = 0; 6 | struct symbol_t_entry symbol_t[512]; 7 | 8 | void add_symbol(char *symbol, unsigned int address) { 9 | 10 | if (find_symbol(symbol) != -1) { 11 | 12 | asmerror("Duplicate symbol definition: %s", symbol); 13 | } 14 | 15 | symbol_t[symbol_t_size].name = symbol; 16 | symbol_t[symbol_t_size].address = address; 17 | symbol_t_size++; 18 | } 19 | 20 | unsigned int find_symbol(char *symbol) { 21 | 22 | for (int c=0; c < symbol_t_size; c++) { 23 | 24 | if (!strcmp(symbol, symbol_t[c].name)) { 25 | 26 | return symbol_t[c].address; 27 | } 28 | } 29 | 30 | return -1; 31 | } 32 | 33 | 34 | -------------------------------------------------------------------------------- /assembler/symbols.h: -------------------------------------------------------------------------------- 1 | #ifndef _SYMBOLS_H 2 | #define _SYMBOLS_H 3 | 4 | struct symbol_t_entry { 5 | 6 | char *name; 7 | unsigned int address; 8 | }; 9 | 10 | extern unsigned int symbol_t_size; 11 | extern struct symbol_t_entry symbol_t[512]; 12 | 13 | void add_symbol(char *symbol, unsigned int address); 14 | unsigned int find_symbol(char *symbol); 15 | 16 | #endif 17 | 18 | -------------------------------------------------------------------------------- /programs/README: -------------------------------------------------------------------------------- 1 | These example programs are written in assembly source code. To obtain machine code for the homebuilt CPU, first build the 'assembler' programme in the 'assembler' folder (just "make" should work on Linux or OSX). 2 | 3 | Then use it to assemble any of thee programs, e.g.: 4 | 5 | $ ../assembler/assembler < fib.s 6 | 7 | That will print out the binary bytes of the programme on stdout. Note that the assembler reads stdin, it doesn't parse or read any of its command-line arguments. 8 | -------------------------------------------------------------------------------- /programs/fib.s: -------------------------------------------------------------------------------- 1 | ; FIBONACCI 2 | 3 | begin: xor Rb, Rb ; 0 11010001 4 | mov Ra, Rb ; 1 00000001 5 | mov Rc, Ra ; 2 00010000 6 | inc Rb ; 3 11000001 7 | loop: add Rc, Rb ; 4 11001110 8 | jc #begin ; 5 00111000 9 | ; 6 00000000 10 | mov Ra, Rc ; 7 00000010 11 | mov Rc, Rb ; 8 00010001 12 | mov Rb, Ra ; 9 00001000 13 | jmp #loop ; 10 00101111 14 | ; 11 00000100 15 | -------------------------------------------------------------------------------- /programs/fib_mult_powers.s: -------------------------------------------------------------------------------- 1 | ; Global variables (in data memory) 2 | .equ cur_prog,0 3 | 4 | ; program text (in program memory) 5 | .org 0 6 | ; Initialize stack 7 | data SP,#0 8 | 9 | ; Programme selector. Desired program is set in #progno 10 | p_select: data Rb,#3 11 | data Rc,#progno 12 | lod Rc,[Rc] 13 | and Rc,Rb 14 | data Rb,#progtab 15 | add Rc,Rb 16 | lod Rc,[Rc] 17 | call Rc 18 | jmp #p_select 19 | 20 | ; Programme entry points table (4 entries) 21 | progtab: #p_alternate 22 | #p_fibonacci 23 | #p_multtables 24 | #p_powerseries 25 | 26 | ; Alternate among 3 other programmes (Fibonacci, multiplication tables, 27 | ; power series) 28 | p_alternate: push Rb 29 | data Rb,#3 30 | lod Rc,[#cur_prog] 31 | alt_inc: inc Rc 32 | and Rc,Rb 33 | jz #alt_inc 34 | sto [#cur_prog],Rc 35 | pop Rb 36 | add Rc,Rb 37 | lod Rc,[Rc] 38 | call Rc 39 | ret: ret 40 | 41 | ; Calculate Fibonacci sequence up to 255 42 | p_fibonacci: xor Rb,Rb 43 | mov Ra,Rb 44 | mov Rc,Ra 45 | inc Rb 46 | fib_loop: add Rc,Rb 47 | jc #ret 48 | mov Ra,Rc 49 | mov Rc,Rb 50 | mov Rb,Ra 51 | jmp #fib_loop 52 | 53 | ; Show all multiplication tables up to 127. Limited to products <= 255 54 | p_multtables: xor Rb,Rb 55 | mult_newtab: inc Rb 56 | jn #ret 57 | data Rc,#0 58 | mult_loop: mov Ra,Rc 59 | add Rc,Rb 60 | jc #mult_newtab 61 | jmp #mult_loop 62 | 63 | ; Show all power series (n^1, n^2, n^3, ...) up to base 15. Limited 64 | ; to results <= 255 65 | p_powerseries: data Rd,#1 66 | push Rd 67 | pow_next: pop Rd 68 | inc Rd 69 | data Rb,#15 70 | and Rd,Rb 71 | jz #ret 72 | push Rd 73 | mov Ra,Rd 74 | mov Rb,Rd 75 | pow_l_power: data Rc,#0 76 | pow_l_mult: dec Rd 77 | jc #pow_cont 78 | mov Ra,Rc 79 | mov Rb,Rc 80 | lod Rd,[SP] 81 | jmp #pow_l_power 82 | pow_cont: add Rc,Rb 83 | jc #pow_next 84 | jmp #pow_l_mult 85 | 86 | .org 255 87 | ; Change this to select a different programme to run in a continuous loop 88 | progno: #0 ;255 [11111111]: 00000000 89 | -------------------------------------------------------------------------------- /programs/fibbak.s: -------------------------------------------------------------------------------- 1 | begin: data Rb,#144 2 | data Ra, #233 3 | loop: mov Rc,Ra 4 | sub Rc,Rb 5 | mov Ra,Rb 6 | mov Rb,Rc 7 | jz #end 8 | jmp #loop 9 | end: mov Ra,Rb 10 | jmp #begin 11 | 12 | -------------------------------------------------------------------------------- /programs/multiply.s: -------------------------------------------------------------------------------- 1 | ; MULTIPLY 2 | 3 | data Rb, #5 ; 0 00001111 4 | ; 1 00000101 5 | data Rc, #3 ; 2 00010111 6 | ; 3 00000011 7 | xor Rd, Rd ; 4 11010011 8 | loop: dec Rc ; 5 11100010 9 | jc #cont ; 6 00111000 10 | ; 7 00001010 11 | mov Ra, Rd ; 8 00000011 12 | hlt ; 9 00101101 13 | cont: add Rd, Rb ; 10 11001111 14 | jmp #loop ; 11 00101111 15 | ; 12 00000101 16 | 17 | -------------------------------------------------------------------------------- /programs/powers.s: -------------------------------------------------------------------------------- 1 | ; Show all power series (n^1, n^2, n^3, ...) up to base 15. Limited 2 | ; to results <= 255 3 | 4 | .org 0 5 | begin: data SP, #0 6 | data Rd, #1 7 | sto [#0], Rd 8 | data Rb, #1 9 | sto [#1], Rb 10 | next: data Rc, #dopow 11 | call Rc 12 | lod Rb, [#1] 13 | tst Rb 14 | jz #begin 15 | jmp #next 16 | dopow: lod Rd, [#0] 17 | inc Rd 18 | data Rb, #15 19 | and Rd,Rb 20 | jz #restart 21 | sto [#0], Rd 22 | mov Ra, Rd 23 | mov Rb, Rd 24 | loop0: data Rc, #0 25 | loop1: dec Rd 26 | jc #cont 27 | mov Ra, Rc 28 | mov Rb, Rc 29 | lod Rd, [#0] 30 | jmp #loop0 31 | cont: add Rc, Rb 32 | jc #ret 33 | jmp #loop1 34 | restart:data Rb, #0 35 | sto [#1], Rb 36 | ret: ret 37 | -------------------------------------------------------------------------------- /programs/powers_of_3.s: -------------------------------------------------------------------------------- 1 | ; POWERS-OF-3 2 | 3 | begin: data Rc, #3 ; 0 00010111 4 | ; 1 00000011 5 | loop: mov Ra, Rc ; 2 00000010 6 | mov Rb, Rc ; 3 00001010 7 | add Rc, Rb ; 4 11001110 8 | jc #begin ; 5 00111000 9 | ; 6 00000000 10 | add Rc, Rb ; 7 11001110 11 | jmp #loop ; 8 00101111 12 | ; 9 00000010 13 | -------------------------------------------------------------------------------- /programs/primes.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | unsigned int prime_count = 0; 5 | unsigned int primes[128]; 6 | 7 | 8 | unsigned int calc_remaind(unsigned int dividend, unsigned int divisor) { 9 | 10 | while (dividend >= divisor) { 11 | dividend -= divisor; 12 | } 13 | return dividend; 14 | } 15 | 16 | bool is_prime(unsigned int candidate) { 17 | 18 | for ( 19 | unsigned int prime_index=0; 20 | (prime_index < prime_count) && (primes[prime_index] < 16); 21 | prime_index++) { 22 | 23 | if (calc_remaind(candidate, primes[prime_index]) == 0) { 24 | 25 | return false; 26 | } 27 | } 28 | 29 | return true; 30 | } 31 | 32 | void show_prime(unsigned int prime) { 33 | 34 | printf("Next prime number: %d\n", prime); 35 | } 36 | 37 | void find_primes() { 38 | 39 | for (unsigned int candidate = 3; candidate < 256; candidate+=2) { 40 | 41 | if (is_prime(candidate)) { 42 | 43 | show_prime(candidate); 44 | primes[prime_count++] = candidate; 45 | } 46 | } 47 | } 48 | 49 | int main(int argc, char **argv) { 50 | 51 | show_prime(2); 52 | find_primes(); 53 | } 54 | -------------------------------------------------------------------------------- /programs/primes.s: -------------------------------------------------------------------------------- 1 | .equ prime_count, 0 2 | .equ primes, 1 3 | .org 0 4 | ; 5 | ; void main(): halt 6 | ; 7 | main: data sp, #0 8 | sto [#prime_count], sp ; prime_count=0 9 | data ra, #2 10 | data rc, #find_primes 11 | call rc 12 | hlt 13 | 14 | .org 32 15 | ; 16 | ; void find_primes() 17 | ; 18 | ; clobbers: ra, rb, rc, rd 19 | ; 20 | find_primes: data rd, #3 ; rd = candidate = 3; 21 | tst rd 22 | _4: jc #_ret 23 | push rd ; stack = [..,candidate] 24 | data rc, #is_prime 25 | call rc 26 | tst rd 27 | jz #_5 28 | lod ra, [sp] ; stack = [..,candidate].ra= candidate 29 | data rd, #primes 30 | lod rb, [#prime_count] 31 | add rd, rb 32 | sto [rd], ra ; primes[prime_count] = candidate 33 | inc rb 34 | sto [#prime_count], rb ; prime_count++ 35 | _5: pop rd 36 | data rb, #2 37 | add rd, rb ; candidate +=2; 38 | jmp #_4 39 | _ret: ret 40 | 41 | .org 64 42 | ; 43 | ; bool is_prime(unsigned int candidate) 44 | ; 45 | ; expects: rd = candidate 46 | ; returns: rd = return value. 47 | ; clobbers: rb, rc 48 | ; 49 | is_prime: data rb, #0 ; unsigned int prime_index=0; 50 | _2: lod rc, [#prime_count] ; rc = prime_count; 51 | cmp rb,rc 52 | jc #_return_true ; if (prime_index >= prime_count) 53 | push rd ; stack = [..,candidate] 54 | data rd, #primes 55 | add rd, rb 56 | lod rc, [rd] ; rc =primes[prime_index] 57 | pop rd ; stack = [..]. rd = candidate 58 | push rb ; stack = [..,prime_index] 59 | data rb, #15 60 | cmp rb, rc 61 | jc #_3 62 | pop rb 63 | jmp #_return_true 64 | _3: mov rb, rc 65 | push rd ; stack = [..,prime_index,candidate] 66 | data rc, #calc_remaind 67 | call rc 68 | tst rd 69 | jz #_return_false 70 | pop rd ; stack =[..,prime_index].rd=candidate 71 | pop rb ; stack = [..]. rb = prime_index 72 | inc rb ; prime_index++ 73 | jmp #_2 74 | _return_false: pop rd ; stack = [..,prime_index] 75 | pop rb ; stack = [..] 76 | data rd,#0 77 | ret 78 | _return_true: data rd,#1 79 | ret 80 | 81 | .org 128 82 | ; 83 | ; unsigned int calc_remaind(unsigned int dividend, unsigned int divisor) 84 | ; 85 | ; expects: rd = dividend. rb = divisor 86 | ; returns: rd = return value. 87 | ; 88 | calc_remaind: cmp rd, rb 89 | jc #_1 90 | ret 91 | _1: sub rd, rb 92 | jmp #calc_remaind 93 | 94 | -------------------------------------------------------------------------------- /programs/qsort.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | uint8_t values[100]; 7 | 8 | 9 | void swap(uint8_t first, uint8_t second) { 10 | 11 | uint8_t t = values[first]; 12 | values[first] = values[second]; 13 | values[second] = t; 14 | } 15 | 16 | 17 | uint8_t partition(uint8_t low, uint8_t high) { 18 | 19 | uint8_t pivot = values[high]; 20 | uint8_t i = low; 21 | for (uint8_t j=low; j < high; j++) { 22 | 23 | if (values[j] < pivot) { 24 | 25 | swap(i,j); 26 | i++; 27 | } 28 | } 29 | 30 | if (values[high] < values[i]) { 31 | 32 | swap(high, i); 33 | } 34 | 35 | return i; 36 | } 37 | 38 | 39 | void quicksort(uint8_t low, uint8_t high) { 40 | 41 | if (low < high) { 42 | 43 | uint8_t p = partition(low, high); 44 | 45 | if (p > 0) { 46 | quicksort(low, p-1); 47 | } 48 | 49 | quicksort(p+1, high); 50 | } 51 | } 52 | 53 | 54 | 55 | void init_values() { 56 | 57 | srand((unsigned int) time(NULL)); 58 | 59 | for (int c=0; c < 100; c++) { 60 | 61 | values[c] = (uint8_t) rand(); 62 | } 63 | } 64 | 65 | void show_values() { 66 | 67 | for (int c=0; c < 100; c++) { 68 | 69 | printf("Random number %d is: %d\n", c, values[c]); 70 | } 71 | } 72 | 73 | int main(int argc, char **argv) { 74 | 75 | init_values(); 76 | quicksort(0, 99); 77 | show_values(); 78 | 79 | return 0; 80 | } 81 | 82 | -------------------------------------------------------------------------------- /programs/qsort.s: -------------------------------------------------------------------------------- 1 | .equ values, 0 2 | .equ pivot, 100 3 | 4 | jmp #main 5 | 6 | 7 | ; 8 | ; void swap(uint8_t first, uint8_t second) 9 | ; 10 | ; expects: rb=first. rd=second 11 | ; clobbers: rb, rc, rd 12 | ; 13 | swap: push rd 14 | data rd, #values 15 | add rd, rb 16 | lod rc, [rd] 17 | pop rb 18 | push rd 19 | data rd, #values 20 | add rd, rb 21 | lod rb, [rd] 22 | sto [rd], rc 23 | pop rd 24 | sto [rd], rb 25 | ret 26 | 27 | ; 28 | ; uint8_t partition(uint8_t low, uint8_t high) 29 | ; 30 | ; expects: rb=low. rd=high 31 | ; returns: rd= return value 32 | ; clobbers: rb, rc 33 | partition: mov rc, rb ; rc=i=low 34 | push rd ; stack = [high] 35 | data rd, #values ; rd = &values 36 | pop rb ; rb = high. stack = [] 37 | add rd, rb ; rd=&values[high] 38 | lod rd, [rd] ; rd=values[high] 39 | sto [#pivot],rd ; pivot=values[high] 40 | mov rd, rb ; rd=high 41 | mov rb, rc ; rb=j=low 42 | _1: cmp rb, rd 43 | jc #_2 44 | push rd ; stack = [high] 45 | data rd, #values 46 | add rd, rb ; rd= &values[j] 47 | lod rd, [rd] ; rd = vaues[j] 48 | push rb ; stack = [high, j] 49 | lod rb, [#pivot] 50 | cmp rd, rb 51 | jc #_3 52 | lod rd, [sp] ; rd = j 53 | mov rb, rc ; rb = i 54 | push rc ; stack = [high, j, i] 55 | data rc, #swap 56 | call rc 57 | pop rc ; stack = [high, j]. rc=i 58 | inc rc ; i++ 59 | _3: pop rb ; stack = [high]. rb=j 60 | inc rb ; j++ 61 | pop rd ; stack = [] 62 | jmp #_1 63 | _2: push rd ; stack = [high] 64 | mov rb, rc ; rb = i 65 | data rd, #values 66 | add rd, rb ; rd = &values[i] 67 | lod rd,[rd] ; rd = values[i] 68 | lod rb,[#pivot] 69 | cmp rb, rd 70 | jc #_4 71 | lod rb,[sp] ; rb = high; stack = [high] 72 | mov rd, rc ; rd = i 73 | push rc ; stack = [high, i] 74 | data rc, #swap 75 | call rc 76 | pop rc ; rc = i, stack=[high] 77 | _4: pop rd ; stack = [] 78 | mov rd, rc 79 | ret 80 | 81 | 82 | ; 83 | ; void quicksort(uint8_t low, uint8_t high) 84 | ; 85 | ; expects: rb=low. rd=high 86 | ; clobbers: rb, rc, rd 87 | ; 88 | quicksort: cmp rb, rd 89 | jc #_5 90 | push rd ; stack = [high] 91 | push rb ; stack = [high, low] 92 | data rc, #partition 93 | call rc ; rd = p 94 | pop rb ; stack = [high]. rb=low 95 | push rd ; stack = [high, p] 96 | tst rd 97 | jz #_6 98 | dec rd 99 | data rc, #quicksort 100 | call rc 101 | _6: pop rb 102 | inc rb 103 | pop rd 104 | data rc, #quicksort 105 | call rc 106 | _5: ret 107 | 108 | ; 109 | ; void show_values() 110 | ; clobbers: ra, rb, rc, rd 111 | ; 112 | show_values: data rb, #0 113 | data rc, #100 114 | _8: cmp rb, rc 115 | jc #_7 116 | data rd, #values 117 | add rd, rb 118 | lod ra, [rd] 119 | inc rb 120 | jmp #_8 121 | _7: ret 122 | 123 | ; 124 | ; void main() 125 | ; 126 | ; halts 127 | ; clobbers: ra,rb,rc,rd 128 | 129 | main: data sp, #0 130 | data rc, #quicksort 131 | data rb, #0, 132 | data rd, #99 133 | call rc 134 | data rc, #show_values 135 | call rc 136 | hlt 137 | 138 | 139 | -------------------------------------------------------------------------------- /programs/readram.s: -------------------------------------------------------------------------------- 1 | .org 0 2 | jmp #start 3 | .org 12 4 | start: data SP,#0 5 | loop: pop Ra 6 | jc #hlt 7 | jmp #loop 8 | hlt: hlt 9 | 10 | -------------------------------------------------------------------------------- /programs/readwriteram.s: -------------------------------------------------------------------------------- 1 | begin: data rd, #0 2 | loop: lod ra, [rd] 3 | sto [rd], rd 4 | inc rd 5 | jc #end 6 | jmp #loop 7 | end: hlt 8 | -------------------------------------------------------------------------------- /schematics/7-digit-display.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | P 0 2900 300 2900 1 0 0 3 | { 4 | T 200 2950 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 200 2850 5 8 0 1 0 8 1 7 | pinseq=3 8 | T 350 2900 9 8 1 1 0 0 1 9 | pinlabel=A 10 | T 350 2900 5 8 0 1 0 2 1 11 | pintype=in 12 | } 13 | P 0 2600 300 2600 1 0 0 14 | { 15 | T 200 2650 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 200 2550 5 8 0 1 0 8 1 18 | pinseq=4 19 | T 350 2600 9 8 1 1 0 0 1 20 | pinlabel=B 21 | T 350 2600 5 8 0 1 0 2 1 22 | pintype=in 23 | } 24 | P 0 2300 300 2300 1 0 0 25 | { 26 | T 200 2350 5 8 1 1 0 6 1 27 | pinnumber=3 28 | T 200 2250 5 8 0 1 0 8 1 29 | pinseq=7 30 | T 350 2300 9 8 1 1 0 0 1 31 | pinlabel=common cathode 32 | T 350 2300 5 8 0 1 0 2 1 33 | pintype=in 34 | } 35 | P 0 2000 300 2000 1 0 0 36 | { 37 | T 200 2050 5 8 1 1 0 6 1 38 | pinnumber=4 39 | T 200 1950 5 8 0 1 0 8 1 40 | pinseq=8 41 | T 350 2000 9 8 1 1 0 0 1 42 | pinlabel=C 43 | T 350 2000 5 8 0 1 0 2 1 44 | pintype=in 45 | } 46 | P 0 1700 300 1700 1 0 0 47 | { 48 | T 200 1750 5 8 1 1 0 6 1 49 | pinnumber=5 50 | T 200 1650 5 8 0 1 0 8 1 51 | pinseq=13 52 | T 350 1700 9 8 1 1 0 0 1 53 | pinlabel=D 54 | T 350 1700 5 8 0 1 0 2 1 55 | pintype=in 56 | } 57 | P 1500 2900 1800 2900 1 0 1 58 | { 59 | T 1600 2950 5 8 1 1 0 0 1 60 | pinnumber=10 61 | T 1600 2850 5 8 0 1 0 2 1 62 | pinseq=2 63 | T 1450 2900 9 8 1 1 0 6 1 64 | pinlabel=E 65 | T 1450 2900 5 8 0 1 0 8 1 66 | pintype=out 67 | } 68 | P 1500 2600 1800 2600 1 0 1 69 | { 70 | T 1600 2650 5 8 1 1 0 0 1 71 | pinnumber=9 72 | T 1600 2550 5 8 0 1 0 2 1 73 | pinseq=5 74 | T 1450 2600 9 8 1 1 0 6 1 75 | pinlabel=F 76 | T 1450 2600 5 8 0 1 0 8 1 77 | pintype=out 78 | } 79 | P 1500 2000 1800 2000 1 0 1 80 | { 81 | T 1600 2050 5 8 1 1 0 0 1 82 | pinnumber=7 83 | T 1600 1950 5 8 0 1 0 2 1 84 | pinseq=9 85 | T 1450 2000 9 8 1 1 0 6 1 86 | pinlabel=G 87 | T 1450 2000 5 8 0 1 0 8 1 88 | pintype=out 89 | } 90 | P 1500 1700 1800 1700 1 0 1 91 | { 92 | T 1600 1750 5 8 1 1 0 0 1 93 | pinnumber=6 94 | T 1600 1650 5 8 0 1 0 2 1 95 | pinseq=12 96 | T 1450 1700 9 8 1 1 0 6 1 97 | pinlabel=H 98 | T 1450 1700 5 8 0 1 0 8 1 99 | pintype=in 100 | } 101 | B 300 1500 1200 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 102 | T 300 3450 5 10 0 0 0 0 1 103 | device=74377 104 | T 1700 3200 8 10 1 1 0 6 1 105 | refdes=U? 106 | T 300 3650 5 10 0 0 0 0 1 107 | footprint=DIP20 108 | T 300 3850 5 10 0 0 0 0 1 109 | description=8 D-type flip-flops with enable 110 | T 300 4450 5 10 0 0 0 0 1 111 | numslots=0 112 | T 300 4050 5 10 0 0 0 0 1 113 | net=Vcc:20 114 | T 300 4250 5 10 0 0 0 0 1 115 | net=GND:10 116 | T 300 3240 9 10 1 0 0 0 1 117 | 7-digit display 118 | T 300 4650 5 10 0 0 0 0 1 119 | documentation=http://www-s.ti.com/sc/ds/sn74hc377.pdf 120 | -------------------------------------------------------------------------------- /schematics/74382-1.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | P 0 500 300 500 1 0 0 3 | { 4 | T 200 550 5 8 1 1 0 6 1 5 | pinnumber=15 6 | T 200 450 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 350 500 9 8 1 1 0 0 1 9 | pinlabel=Cn 10 | T 350 500 5 8 0 1 0 2 1 11 | pintype=in 12 | } 13 | P 0 2900 300 2900 1 0 0 14 | { 15 | T 200 2950 5 8 1 1 0 6 1 16 | pinnumber=3 17 | T 200 2850 5 8 0 1 0 8 1 18 | pinseq=3 19 | T 350 2900 9 8 1 1 0 0 1 20 | pinlabel=A0 21 | T 350 2900 5 8 0 1 0 2 1 22 | pintype=in 23 | } 24 | P 0 2600 300 2600 1 0 0 25 | { 26 | T 200 2650 5 8 1 1 0 6 1 27 | pinnumber=4 28 | T 200 2550 5 8 0 1 0 8 1 29 | pinseq=4 30 | T 350 2600 9 8 1 1 0 0 1 31 | pinlabel=B0 32 | T 350 2600 5 8 0 1 0 2 1 33 | pintype=in 34 | } 35 | P 0 2300 300 2300 1 0 0 36 | { 37 | T 200 2350 5 8 1 1 0 6 1 38 | pinnumber=1 39 | T 200 2250 5 8 0 1 0 8 1 40 | pinseq=7 41 | T 350 2300 9 8 1 1 0 0 1 42 | pinlabel=A1 43 | T 350 2300 5 8 0 1 0 2 1 44 | pintype=in 45 | } 46 | P 0 2000 300 2000 1 0 0 47 | { 48 | T 200 2050 5 8 1 1 0 6 1 49 | pinnumber=2 50 | T 200 1950 5 8 0 1 0 8 1 51 | pinseq=8 52 | T 350 2000 9 8 1 1 0 0 1 53 | pinlabel=B1 54 | T 350 2000 5 8 0 1 0 2 1 55 | pintype=in 56 | } 57 | P 0 1700 300 1700 1 0 0 58 | { 59 | T 200 1750 5 8 1 1 0 6 1 60 | pinnumber=19 61 | T 200 1650 5 8 0 1 0 8 1 62 | pinseq=13 63 | T 350 1700 9 8 1 1 0 0 1 64 | pinlabel=A2 65 | T 350 1700 5 8 0 1 0 2 1 66 | pintype=in 67 | } 68 | P 0 1400 300 1400 1 0 0 69 | { 70 | T 200 1450 5 8 1 1 0 6 1 71 | pinnumber=18 72 | T 200 1350 5 8 0 1 0 8 1 73 | pinseq=14 74 | T 350 1400 9 8 1 1 0 0 1 75 | pinlabel=B2 76 | T 350 1400 5 8 0 1 0 2 1 77 | pintype=in 78 | } 79 | P 0 1100 300 1100 1 0 0 80 | { 81 | T 200 1150 5 8 1 1 0 6 1 82 | pinnumber=17 83 | T 200 1050 5 8 0 1 0 8 1 84 | pinseq=17 85 | T 350 1100 9 8 1 1 0 0 1 86 | pinlabel=A3 87 | T 350 1100 5 8 0 1 0 2 1 88 | pintype=in 89 | } 90 | P 0 800 300 800 1 0 0 91 | { 92 | T 200 850 5 8 1 1 0 6 1 93 | pinnumber=16 94 | T 200 750 5 8 0 1 0 8 1 95 | pinseq=18 96 | T 350 800 9 8 1 1 0 0 1 97 | pinlabel=B3 98 | T 350 800 5 8 0 1 0 2 1 99 | pintype=in 100 | } 101 | P 1700 2900 2000 2900 1 0 1 102 | { 103 | T 1800 2950 5 8 1 1 0 0 1 104 | pinnumber=8 105 | T 1800 2850 5 8 0 1 0 2 1 106 | pinseq=2 107 | T 1650 2900 9 8 1 1 0 6 1 108 | pinlabel=F0 109 | T 1650 2900 5 8 0 1 0 8 1 110 | pintype=out 111 | } 112 | P 1700 2600 2000 2600 1 0 1 113 | { 114 | T 1800 2650 5 8 1 1 0 0 1 115 | pinnumber=9 116 | T 1800 2550 5 8 0 1 0 2 1 117 | pinseq=5 118 | T 1650 2600 9 8 1 1 0 6 1 119 | pinlabel=F1 120 | T 1650 2600 5 8 0 1 0 8 1 121 | pintype=out 122 | } 123 | P 1700 2300 2000 2300 1 0 1 124 | { 125 | T 1800 2350 5 8 1 1 0 0 1 126 | pinnumber=11 127 | T 1800 2250 5 8 0 1 0 2 1 128 | pinseq=6 129 | T 1650 2300 9 8 1 1 0 6 1 130 | pinlabel=F2 131 | T 1650 2300 5 8 0 1 0 8 1 132 | pintype=out 133 | } 134 | P 1700 2000 2000 2000 1 0 1 135 | { 136 | T 1800 2050 5 8 1 1 0 0 1 137 | pinnumber=12 138 | T 1800 1950 5 8 0 1 0 2 1 139 | pinseq=9 140 | T 1650 2000 9 8 1 1 0 6 1 141 | pinlabel=F3 142 | T 1650 2000 5 8 0 1 0 8 1 143 | pintype=out 144 | } 145 | P 1700 1700 2000 1700 1 0 1 146 | { 147 | T 1800 1750 5 8 1 1 0 0 1 148 | pinnumber=5 149 | T 1800 1650 5 8 0 1 0 2 1 150 | pinseq=12 151 | T 1650 1700 9 8 1 1 0 6 1 152 | pinlabel=S0 153 | T 1650 1700 5 8 0 1 0 8 1 154 | pintype=in 155 | } 156 | P 1700 1400 2000 1400 1 0 1 157 | { 158 | T 1800 1450 5 8 1 1 0 0 1 159 | pinnumber=6 160 | T 1800 1350 5 8 0 1 0 2 1 161 | pinseq=15 162 | T 1650 1400 9 8 1 1 0 6 1 163 | pinlabel=S1 164 | T 1650 1400 5 8 0 1 0 8 1 165 | pintype=in 166 | } 167 | P 1700 1100 2000 1100 1 0 1 168 | { 169 | T 1800 1150 5 8 1 1 0 0 1 170 | pinnumber=7 171 | T 1800 1050 5 8 0 1 0 2 1 172 | pinseq=16 173 | T 1650 1100 9 8 1 1 0 6 1 174 | pinlabel=S2 175 | T 1650 1100 5 8 0 1 0 8 1 176 | pintype=in 177 | } 178 | P 1700 800 2000 800 1 0 1 179 | { 180 | T 1800 850 5 8 1 1 0 0 1 181 | pinnumber=14 182 | T 1800 750 5 8 0 1 0 2 1 183 | pinseq=19 184 | T 1650 800 9 8 1 1 0 6 1 185 | pinlabel=Cn+4 186 | T 1650 800 5 8 0 1 0 8 1 187 | pintype=out 188 | } 189 | B 300 0 1400 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 190 | T 300 3450 5 10 0 0 0 0 1 191 | device=74377 192 | P 2000 500 1700 500 1 0 0 193 | { 194 | T 1795 545 5 8 1 1 0 0 1 195 | pinnumber=13 196 | T 1800 450 5 8 0 1 0 2 1 197 | pinseq=11 198 | T 1645 495 9 8 1 1 0 6 1 199 | pinlabel=OVR 200 | T 1625 500 5 8 0 1 0 8 1 201 | pintype=out 202 | } 203 | T 1700 3300 8 10 1 1 0 6 1 204 | refdes=U? 205 | T 300 3650 5 10 0 0 0 0 1 206 | footprint=DIP20 207 | T 300 3850 5 10 0 0 0 0 1 208 | description=8 D-type flip-flops with enable 209 | T 300 4450 5 10 0 0 0 0 1 210 | numslots=0 211 | T 300 4050 5 10 0 0 0 0 1 212 | net=Vcc:20 213 | T 300 4250 5 10 0 0 0 0 1 214 | net=GND:10 215 | T 300 3240 9 10 1 0 0 0 1 216 | 74382 217 | T 300 4650 5 10 0 0 0 0 1 218 | documentation=http://www-s.ti.com/sc/ds/sn74hc377.pdf 219 | -------------------------------------------------------------------------------- /schematics/ALU.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/ALU.pdf -------------------------------------------------------------------------------- /schematics/ALU.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | C 73800 46900 1 90 0 74382-1.sym 3 | { 4 | T 70350 47200 5 10 0 0 90 0 1 5 | device=74377 6 | T 70500 48600 5 10 1 1 90 6 1 7 | refdes=ALU0 8 | T 70150 47200 5 10 0 0 90 0 1 9 | footprint=DIP20 10 | } 11 | C 69600 46900 1 90 0 74382-1.sym 12 | { 13 | T 66150 47200 5 10 0 0 90 0 1 14 | device=74377 15 | T 66300 48600 5 10 1 1 90 6 1 16 | refdes=ALU1 17 | T 65950 47200 5 10 0 0 90 0 1 18 | footprint=DIP20 19 | } 20 | N 67900 48900 67900 49700 4 21 | N 67900 49700 73700 49700 4 22 | N 68200 48900 68200 49800 4 23 | N 72400 49800 72400 48900 4 24 | N 68500 48900 68500 49900 4 25 | N 68500 49900 72700 49900 4 26 | N 73200 49800 73200 53700 4 27 | N 73000 48900 73000 49000 4 28 | N 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3850 5 8 1 1 0 0 1 104 | pinnumber=11 105 | T 2200 3750 5 8 0 1 0 2 1 106 | pinseq=2 107 | T 2050 3800 9 8 1 1 0 6 1 108 | pinlabel=DQ0 109 | T 2050 3800 5 8 0 1 0 8 1 110 | pintype=io 111 | } 112 | P 2100 3500 2400 3500 1 0 1 113 | { 114 | T 2200 3550 5 8 1 1 0 0 1 115 | pinnumber=12 116 | T 2200 3450 5 8 0 1 0 2 1 117 | pinseq=5 118 | T 2050 3500 9 8 1 1 0 6 1 119 | pinlabel=DQ1 120 | T 2050 3500 5 8 0 1 0 8 1 121 | pintype=io 122 | } 123 | P 2100 3200 2400 3200 1 0 1 124 | { 125 | T 2200 3250 5 8 1 1 0 0 1 126 | pinnumber=13 127 | T 2200 3150 5 8 0 1 0 2 1 128 | pinseq=6 129 | T 2050 3200 9 8 1 1 0 6 1 130 | pinlabel=DQ2 131 | T 2050 3200 5 8 0 1 0 8 1 132 | pintype=io 133 | } 134 | P 2100 2900 2400 2900 1 0 1 135 | { 136 | T 2200 2950 5 8 1 1 0 0 1 137 | pinnumber=15 138 | T 2200 2850 5 8 0 1 0 2 1 139 | pinseq=9 140 | T 2050 2900 9 8 1 1 0 6 1 141 | pinlabel=DQ3 142 | T 2050 2900 5 8 0 1 0 8 1 143 | pintype=io 144 | } 145 | P 2100 2600 2400 2600 1 0 1 146 | { 147 | T 2200 2650 5 8 1 1 0 0 1 148 | pinnumber=16 149 | T 2200 2550 5 8 0 1 0 2 1 150 | pinseq=12 151 | T 2050 2600 9 8 1 1 0 6 1 152 | pinlabel=DQ4 153 | T 2050 2600 5 8 0 1 0 8 1 154 | pintype=io 155 | } 156 | P 2100 2300 2400 2300 1 0 1 157 | { 158 | T 2200 2350 5 8 1 1 0 0 1 159 | pinnumber=17 160 | T 2200 2250 5 8 0 1 0 2 1 161 | pinseq=15 162 | T 2050 2300 9 8 1 1 0 6 1 163 | pinlabel=DQ5 164 | T 2050 2300 5 8 0 1 0 8 1 165 | pintype=io 166 | } 167 | P 2100 2000 2400 2000 1 0 1 168 | { 169 | T 2200 2050 5 8 1 1 0 0 1 170 | pinnumber=18 171 | T 2200 1950 5 8 0 1 0 2 1 172 | pinseq=16 173 | T 2050 2000 9 8 1 1 0 6 1 174 | pinlabel=DQ6 175 | T 2050 2000 5 8 0 1 0 8 1 176 | pintype=io 177 | } 178 | P 2100 1700 2400 1700 1 0 1 179 | { 180 | T 2200 1750 5 8 1 1 0 0 1 181 | pinnumber=19 182 | T 2200 1650 5 8 0 1 0 2 1 183 | pinseq=19 184 | T 2050 1700 9 8 1 1 0 6 1 185 | pinlabel=DQ7 186 | T 2050 1700 5 8 0 1 0 8 1 187 | pintype=io 188 | } 189 | B 300 0 1800 4100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 190 | T 300 3450 5 10 0 0 0 0 1 191 | device=74377 192 | P 2400 1400 2100 1400 1 0 0 193 | { 194 | T 2195 1445 5 8 1 1 0 0 1 195 | pinnumber=20 196 | T 2200 1350 5 8 0 1 0 2 1 197 | pinseq=11 198 | T 2045 1395 9 8 1 1 0 6 1 199 | pinlabel=\_CE\_ 200 | T 2025 1400 5 8 0 1 0 8 1 201 | pintype=in 202 | } 203 | T 2000 4200 8 10 1 1 0 6 1 204 | refdes=U? 205 | T 300 3650 5 10 0 0 0 0 1 206 | footprint=DIP20 207 | T 300 3850 5 10 0 0 0 0 1 208 | description=8 D-type flip-flops with enable 209 | T 300 4450 5 10 0 0 0 0 1 210 | numslots=0 211 | T 300 4050 5 10 0 0 0 0 1 212 | net=Vcc:20 213 | T 300 4250 5 10 0 0 0 0 1 214 | net=GND:10 215 | T 300 4140 9 10 1 0 0 0 1 216 | AS6C6264 217 | T 300 4650 5 10 0 0 0 0 1 218 | documentation=http://www-s.ti.com/sc/ds/sn74hc377.pdf 219 | P 0 1100 300 1100 1 0 0 220 | { 221 | T 200 1150 5 8 1 1 0 6 1 222 | pinnumber=24 223 | T 200 1050 5 8 0 1 0 8 1 224 | pinseq=21 225 | T 350 1100 9 8 1 1 0 0 1 226 | pinlabel=A9 227 | T 350 1100 5 8 0 1 0 2 1 228 | pintype=in 229 | } 230 | P 0 800 300 800 1 0 0 231 | { 232 | T 200 850 5 8 1 1 0 6 1 233 | pinnumber=21 234 | T 200 750 5 8 0 1 0 8 1 235 | pinseq=22 236 | T 350 800 9 8 1 1 0 0 1 237 | pinlabel=A10 238 | T 350 800 5 8 0 1 0 2 1 239 | pintype=in 240 | } 241 | P 0 500 300 500 1 0 0 242 | { 243 | T 200 550 5 8 1 1 0 6 1 244 | pinnumber=23 245 | T 200 450 5 8 0 1 0 8 1 246 | pinseq=23 247 | T 350 500 9 8 1 1 0 0 1 248 | pinlabel=A11 249 | T 350 500 5 8 0 1 0 2 1 250 | pintype=in 251 | } 252 | P 0 200 300 200 1 0 0 253 | { 254 | T 200 250 5 8 1 1 0 6 1 255 | pinnumber=2 256 | T 200 150 5 8 0 1 0 8 1 257 | pinseq=24 258 | T 350 200 9 8 1 1 0 0 1 259 | pinlabel=A12 260 | T 350 200 5 8 0 1 0 2 1 261 | pintype=in 262 | } 263 | P 2400 1100 2100 1100 1 0 0 264 | { 265 | T 2195 1145 5 8 1 1 0 0 1 266 | pinnumber=26 267 | T 2200 1050 5 8 0 1 0 2 1 268 | pinseq=25 269 | T 2045 1095 9 8 1 1 0 6 1 270 | pinlabel=CE2 271 | T 2025 1100 5 8 0 1 0 8 1 272 | pintype=in 273 | } 274 | P 2400 800 2100 800 1 0 0 275 | { 276 | T 2195 845 5 8 1 1 0 0 1 277 | pinnumber=27 278 | T 2200 750 5 8 0 1 0 2 1 279 | pinseq=26 280 | T 2045 795 9 8 1 1 0 6 1 281 | pinlabel=\_WE\_ 282 | T 2025 800 5 8 0 1 0 8 1 283 | pintype=in 284 | } 285 | P 2400 500 2100 500 1 0 0 286 | { 287 | T 2195 545 5 8 1 1 0 0 1 288 | pinnumber=22 289 | T 2200 450 5 8 0 1 0 2 1 290 | pinseq=27 291 | T 2045 495 9 8 1 1 0 6 1 292 | pinlabel=\_OE\_ 293 | T 2025 500 5 8 0 1 0 8 1 294 | pintype=in 295 | } 296 | -------------------------------------------------------------------------------- /schematics/AT28C64-1.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | P 0 1400 300 1400 1 0 0 3 | { 4 | T 200 1450 5 8 1 1 0 6 1 5 | pinnumber=25 6 | T 200 1350 5 8 0 1 0 8 1 7 | pinseq=1 8 | T 350 1400 9 8 1 1 0 0 1 9 | pinlabel=A8 10 | T 350 1400 5 8 0 1 0 2 1 11 | pintype=in 12 | } 13 | P 0 3800 300 3800 1 0 0 14 | { 15 | T 200 3850 5 8 1 1 0 6 1 16 | pinnumber=10 17 | T 200 3750 5 8 0 1 0 8 1 18 | pinseq=3 19 | T 350 3800 9 8 1 1 0 0 1 20 | pinlabel=A0 21 | T 350 3800 5 8 0 1 0 2 1 22 | pintype=in 23 | } 24 | P 0 3500 300 3500 1 0 0 25 | { 26 | T 200 3550 5 8 1 1 0 6 1 27 | pinnumber=9 28 | T 200 3450 5 8 0 1 0 8 1 29 | pinseq=4 30 | T 350 3500 9 8 1 1 0 0 1 31 | pinlabel=A1 32 | T 350 3500 5 8 0 1 0 2 1 33 | pintype=in 34 | } 35 | P 0 3200 300 3200 1 0 0 36 | { 37 | T 200 3250 5 8 1 1 0 6 1 38 | pinnumber=8 39 | T 200 3150 5 8 0 1 0 8 1 40 | pinseq=7 41 | T 350 3200 9 8 1 1 0 0 1 42 | pinlabel=A2 43 | T 350 3200 5 8 0 1 0 2 1 44 | pintype=in 45 | } 46 | P 0 2900 300 2900 1 0 0 47 | { 48 | T 200 2950 5 8 1 1 0 6 1 49 | pinnumber=7 50 | T 200 2850 5 8 0 1 0 8 1 51 | pinseq=8 52 | T 350 2900 9 8 1 1 0 0 1 53 | pinlabel=A3 54 | T 350 2900 5 8 0 1 0 2 1 55 | pintype=in 56 | } 57 | P 0 2600 300 2600 1 0 0 58 | { 59 | T 200 2650 5 8 1 1 0 6 1 60 | pinnumber=6 61 | T 200 2550 5 8 0 1 0 8 1 62 | pinseq=13 63 | T 350 2600 9 8 1 1 0 0 1 64 | pinlabel=A4 65 | T 350 2600 5 8 0 1 0 2 1 66 | pintype=in 67 | } 68 | P 0 2300 300 2300 1 0 0 69 | { 70 | T 200 2350 5 8 1 1 0 6 1 71 | pinnumber=5 72 | T 200 2250 5 8 0 1 0 8 1 73 | pinseq=14 74 | T 350 2300 9 8 1 1 0 0 1 75 | pinlabel=A5 76 | T 350 2300 5 8 0 1 0 2 1 77 | pintype=in 78 | } 79 | P 0 2000 300 2000 1 0 0 80 | { 81 | T 200 2050 5 8 1 1 0 6 1 82 | pinnumber=4 83 | T 200 1950 5 8 0 1 0 8 1 84 | pinseq=17 85 | T 350 2000 9 8 1 1 0 0 1 86 | pinlabel=A6 87 | T 350 2000 5 8 0 1 0 2 1 88 | pintype=in 89 | } 90 | P 0 1700 300 1700 1 0 0 91 | { 92 | T 200 1750 5 8 1 1 0 6 1 93 | pinnumber=3 94 | T 200 1650 5 8 0 1 0 8 1 95 | pinseq=18 96 | T 350 1700 9 8 1 1 0 0 1 97 | pinlabel=A7 98 | T 350 1700 5 8 0 1 0 2 1 99 | pintype=in 100 | } 101 | P 2100 3800 2400 3800 1 0 1 102 | { 103 | T 2200 3850 5 8 1 1 0 0 1 104 | pinnumber=11 105 | T 2200 3750 5 8 0 1 0 2 1 106 | pinseq=2 107 | T 2050 3800 9 8 1 1 0 6 1 108 | pinlabel=I/O0 109 | T 2050 3800 5 8 0 1 0 8 1 110 | pintype=io 111 | } 112 | P 2100 3500 2400 3500 1 0 1 113 | { 114 | T 2200 3550 5 8 1 1 0 0 1 115 | pinnumber=12 116 | T 2200 3450 5 8 0 1 0 2 1 117 | pinseq=5 118 | T 2050 3500 9 8 1 1 0 6 1 119 | pinlabel=I/O1 120 | T 2050 3500 5 8 0 1 0 8 1 121 | pintype=io 122 | } 123 | P 2100 3200 2400 3200 1 0 1 124 | { 125 | T 2200 3250 5 8 1 1 0 0 1 126 | pinnumber=13 127 | T 2200 3150 5 8 0 1 0 2 1 128 | pinseq=6 129 | T 2050 3200 9 8 1 1 0 6 1 130 | pinlabel=I/O2 131 | T 2050 3200 5 8 0 1 0 8 1 132 | pintype=io 133 | } 134 | P 2100 2900 2400 2900 1 0 1 135 | { 136 | T 2200 2950 5 8 1 1 0 0 1 137 | pinnumber=15 138 | T 2200 2850 5 8 0 1 0 2 1 139 | pinseq=9 140 | T 2050 2900 9 8 1 1 0 6 1 141 | pinlabel=I/O3 142 | T 2050 2900 5 8 0 1 0 8 1 143 | pintype=io 144 | } 145 | P 2100 2600 2400 2600 1 0 1 146 | { 147 | T 2200 2650 5 8 1 1 0 0 1 148 | pinnumber=16 149 | T 2200 2550 5 8 0 1 0 2 1 150 | pinseq=12 151 | T 2050 2600 9 8 1 1 0 6 1 152 | pinlabel=I/O4 153 | T 2050 2600 5 8 0 1 0 8 1 154 | pintype=io 155 | } 156 | P 2100 2300 2400 2300 1 0 1 157 | { 158 | T 2200 2350 5 8 1 1 0 0 1 159 | pinnumber=17 160 | T 2200 2250 5 8 0 1 0 2 1 161 | pinseq=15 162 | T 2050 2300 9 8 1 1 0 6 1 163 | pinlabel=I/O5 164 | T 2050 2300 5 8 0 1 0 8 1 165 | pintype=io 166 | } 167 | P 2100 2000 2400 2000 1 0 1 168 | { 169 | T 2200 2050 5 8 1 1 0 0 1 170 | pinnumber=18 171 | T 2200 1950 5 8 0 1 0 2 1 172 | pinseq=16 173 | T 2050 2000 9 8 1 1 0 6 1 174 | pinlabel=I/O6 175 | T 2050 2000 5 8 0 1 0 8 1 176 | pintype=io 177 | } 178 | P 2100 1700 2400 1700 1 0 1 179 | { 180 | T 2200 1750 5 8 1 1 0 0 1 181 | pinnumber=19 182 | T 2200 1650 5 8 0 1 0 2 1 183 | pinseq=19 184 | T 2050 1700 9 8 1 1 0 6 1 185 | pinlabel=I/O7 186 | T 2050 1700 5 8 0 1 0 8 1 187 | pintype=io 188 | } 189 | B 300 0 1800 4100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 190 | T 300 3450 5 10 0 0 0 0 1 191 | device=74377 192 | P 2400 1100 2100 1100 1 0 0 193 | { 194 | T 2195 1145 5 8 1 1 0 0 1 195 | pinnumber=20 196 | T 2200 1050 5 8 0 1 0 2 1 197 | pinseq=11 198 | T 2045 1095 9 8 1 1 0 6 1 199 | pinlabel=\_CE\_ 200 | T 2025 1100 5 8 0 1 0 8 1 201 | pintype=in 202 | } 203 | T 2000 4200 8 10 1 1 0 6 1 204 | refdes=U? 205 | T 300 3650 5 10 0 0 0 0 1 206 | footprint=DIP20 207 | T 300 3850 5 10 0 0 0 0 1 208 | description=8 D-type flip-flops with enable 209 | T 300 4450 5 10 0 0 0 0 1 210 | numslots=0 211 | T 300 4050 5 10 0 0 0 0 1 212 | net=Vcc:20 213 | T 300 4250 5 10 0 0 0 0 1 214 | net=GND:10 215 | T 300 4140 9 10 1 0 0 0 1 216 | AT28C64 217 | T 300 4650 5 10 0 0 0 0 1 218 | documentation=http://www-s.ti.com/sc/ds/sn74hc377.pdf 219 | P 0 1100 300 1100 1 0 0 220 | { 221 | T 200 1150 5 8 1 1 0 6 1 222 | pinnumber=24 223 | T 200 1050 5 8 0 1 0 8 1 224 | pinseq=21 225 | T 350 1100 9 8 1 1 0 0 1 226 | pinlabel=A9 227 | T 350 1100 5 8 0 1 0 2 1 228 | pintype=in 229 | } 230 | P 0 800 300 800 1 0 0 231 | { 232 | T 200 850 5 8 1 1 0 6 1 233 | pinnumber=21 234 | T 200 750 5 8 0 1 0 8 1 235 | pinseq=22 236 | T 350 800 9 8 1 1 0 0 1 237 | pinlabel=A10 238 | T 350 800 5 8 0 1 0 2 1 239 | pintype=in 240 | } 241 | P 0 500 300 500 1 0 0 242 | { 243 | T 200 550 5 8 1 1 0 6 1 244 | pinnumber=23 245 | T 200 450 5 8 0 1 0 8 1 246 | pinseq=23 247 | T 350 500 9 8 1 1 0 0 1 248 | pinlabel=A11 249 | T 350 500 5 8 0 1 0 2 1 250 | pintype=in 251 | } 252 | P 0 200 300 200 1 0 0 253 | { 254 | T 200 250 5 8 1 1 0 6 1 255 | pinnumber=2 256 | T 200 150 5 8 0 1 0 8 1 257 | pinseq=24 258 | T 350 200 9 8 1 1 0 0 1 259 | pinlabel=A12 260 | T 350 200 5 8 0 1 0 2 1 261 | pintype=in 262 | } 263 | P 2400 800 2100 800 1 0 0 264 | { 265 | T 2195 845 5 8 1 1 0 0 1 266 | pinnumber=27 267 | T 2200 750 5 8 0 1 0 2 1 268 | pinseq=26 269 | T 2045 795 9 8 1 1 0 6 1 270 | pinlabel=\_WE\_ 271 | T 2025 800 5 8 0 1 0 8 1 272 | pintype=in 273 | } 274 | P 2400 500 2100 500 1 0 0 275 | { 276 | T 2195 545 5 8 1 1 0 0 1 277 | pinnumber=22 278 | T 2200 450 5 8 0 1 0 2 1 279 | pinseq=27 280 | T 2045 495 9 8 1 1 0 6 1 281 | pinlabel=\_OE\_ 282 | T 2025 500 5 8 0 1 0 8 1 283 | pintype=in 284 | } 285 | -------------------------------------------------------------------------------- /schematics/ArduinoNano.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | P 0 1400 300 1400 1 0 0 3 | { 4 | T 200 1450 5 8 1 1 0 6 1 5 | pinnumber=11 6 | T 200 1350 5 8 0 1 0 8 1 7 | pinseq=11 8 | T 350 1400 9 8 1 1 0 0 1 9 | pinlabel=D8 10 | T 350 1400 5 8 0 1 0 2 1 11 | pintype=io 12 | } 13 | P 0 3800 300 3800 1 0 0 14 | { 15 | T 200 3850 5 8 1 1 0 6 1 16 | pinnumber=3 17 | T 200 3750 5 8 0 1 0 8 1 18 | pinseq=3 19 | T 350 3800 9 8 1 1 0 0 1 20 | pinlabel=RESET 21 | T 350 3800 5 8 0 1 0 2 1 22 | pintype=in 23 | } 24 | P 0 3500 300 3500 1 0 0 25 | { 26 | T 200 3550 5 8 1 1 0 6 1 27 | pinnumber=4 28 | T 200 3450 5 8 0 1 0 8 1 29 | pinseq=4 30 | T 350 3500 9 8 1 1 0 0 1 31 | pinlabel=GND 32 | T 350 3500 5 8 0 1 0 2 1 33 | pintype=out 34 | } 35 | P 0 3200 300 3200 1 0 0 36 | { 37 | T 200 3250 5 8 1 1 0 6 1 38 | pinnumber=5 39 | T 200 3150 5 8 0 1 0 8 1 40 | pinseq=5 41 | T 350 3200 9 8 1 1 0 0 1 42 | pinlabel=D2 43 | T 350 3200 5 8 0 1 0 2 1 44 | pintype=io 45 | } 46 | P 0 2900 300 2900 1 0 0 47 | { 48 | T 200 2950 5 8 1 1 0 6 1 49 | pinnumber=6 50 | T 200 2850 5 8 0 1 0 8 1 51 | pinseq=6 52 | T 350 2900 9 8 1 1 0 0 1 53 | pinlabel=D3 54 | T 350 2900 5 8 0 1 0 2 1 55 | pintype=io 56 | } 57 | P 0 2600 300 2600 1 0 0 58 | { 59 | T 200 2650 5 8 1 1 0 6 1 60 | pinnumber=7 61 | T 200 2550 5 8 0 1 0 8 1 62 | pinseq=7 63 | T 350 2600 9 8 1 1 0 0 1 64 | pinlabel=D4 65 | T 350 2600 5 8 0 1 0 2 1 66 | pintype=io 67 | } 68 | P 0 2300 300 2300 1 0 0 69 | { 70 | T 200 2350 5 8 1 1 0 6 1 71 | pinnumber=8 72 | T 200 2250 5 8 0 1 0 8 1 73 | pinseq=8 74 | T 350 2300 9 8 1 1 0 0 1 75 | pinlabel=D5 76 | T 350 2300 5 8 0 1 0 2 1 77 | pintype=io 78 | } 79 | P 0 2000 300 2000 1 0 0 80 | { 81 | T 200 2050 5 8 1 1 0 6 1 82 | pinnumber=9 83 | T 200 1950 5 8 0 1 0 8 1 84 | pinseq=9 85 | T 350 2000 9 8 1 1 0 0 1 86 | pinlabel=D6 87 | T 350 2000 5 8 0 1 0 2 1 88 | pintype=io 89 | } 90 | P 0 1700 300 1700 1 0 0 91 | { 92 | T 200 1750 5 8 1 1 0 6 1 93 | pinnumber=10 94 | T 200 1650 5 8 0 1 0 8 1 95 | pinseq=10 96 | T 350 1700 9 8 1 1 0 0 1 97 | pinlabel=D7 98 | T 350 1700 5 8 0 1 0 2 1 99 | pintype=io 100 | } 101 | P 2100 3800 2400 3800 1 0 1 102 | { 103 | T 2200 3850 5 8 1 1 0 0 1 104 | pinnumber=28 105 | T 2200 3750 5 8 0 1 0 2 1 106 | pinseq=28 107 | T 2050 3800 9 8 1 1 0 6 1 108 | pinlabel=RESET 109 | T 2050 3800 5 8 0 1 0 8 1 110 | pintype=out 111 | } 112 | P 2100 3500 2400 3500 1 0 1 113 | { 114 | T 2200 3550 5 8 1 1 0 0 1 115 | pinnumber=27 116 | T 2200 3450 5 8 0 1 0 2 1 117 | pinseq=27 118 | T 2050 3500 9 8 1 1 0 6 1 119 | pinlabel=+5V 120 | T 2050 3500 5 8 0 1 0 8 1 121 | pintype=out 122 | } 123 | P 2100 3200 2400 3200 1 0 1 124 | { 125 | T 2200 3250 5 8 1 1 0 0 1 126 | pinnumber=26 127 | T 2200 3150 5 8 0 1 0 2 1 128 | pinseq=26 129 | T 2050 3200 9 8 1 1 0 6 1 130 | pinlabel=A0 131 | T 2050 3200 5 8 0 1 0 8 1 132 | pintype=io 133 | } 134 | P 2100 2900 2400 2900 1 0 1 135 | { 136 | T 2200 2950 5 8 1 1 0 0 1 137 | pinnumber=25 138 | T 2200 2850 5 8 0 1 0 2 1 139 | pinseq=25 140 | T 2050 2900 9 8 1 1 0 6 1 141 | pinlabel=A1 142 | T 2050 2900 5 8 0 1 0 8 1 143 | pintype=io 144 | } 145 | P 2100 2600 2400 2600 1 0 1 146 | { 147 | T 2200 2650 5 8 1 1 0 0 1 148 | pinnumber=24 149 | T 2200 2550 5 8 0 1 0 2 1 150 | pinseq=24 151 | T 2050 2600 9 8 1 1 0 6 1 152 | pinlabel=A2 153 | T 2050 2600 5 8 0 1 0 8 1 154 | pintype=io 155 | } 156 | P 2100 2300 2400 2300 1 0 1 157 | { 158 | T 2200 2350 5 8 1 1 0 0 1 159 | pinnumber=23 160 | T 2200 2250 5 8 0 1 0 2 1 161 | pinseq=23 162 | T 2050 2300 9 8 1 1 0 6 1 163 | pinlabel=A3 164 | T 2050 2300 5 8 0 1 0 8 1 165 | pintype=io 166 | } 167 | P 2100 2000 2400 2000 1 0 1 168 | { 169 | T 2200 2050 5 8 1 1 0 0 1 170 | pinnumber=22 171 | T 2200 1950 5 8 0 1 0 2 1 172 | pinseq=22 173 | T 2050 2000 9 8 1 1 0 6 1 174 | pinlabel=A4 175 | T 2050 2000 5 8 0 1 0 8 1 176 | pintype=io 177 | } 178 | P 2100 1700 2400 1700 1 0 1 179 | { 180 | T 2200 1750 5 8 1 1 0 0 1 181 | pinnumber=21 182 | T 2200 1650 5 8 0 1 0 2 1 183 | pinseq=21 184 | T 2050 1700 9 8 1 1 0 6 1 185 | pinlabel=A5 186 | T 2050 1700 5 8 0 1 0 8 1 187 | pintype=io 188 | } 189 | B 300 0 1800 4700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 190 | T 300 3450 5 10 0 0 0 0 1 191 | device=74377 192 | P 2400 1400 2100 1400 1 0 0 193 | { 194 | T 2195 1445 5 8 1 1 0 0 1 195 | pinnumber=20 196 | T 2200 1350 5 8 0 1 0 2 1 197 | pinseq=20 198 | T 2045 1395 9 8 1 1 0 6 1 199 | pinlabel=A6 200 | T 2025 1400 5 8 0 1 0 8 1 201 | pintype=io 202 | } 203 | T 2000 4800 8 10 1 1 0 6 1 204 | refdes=U? 205 | T 300 3650 5 10 0 0 0 0 1 206 | footprint=DIP20 207 | T 300 3850 5 10 0 0 0 0 1 208 | description=8 D-type flip-flops with enable 209 | T 300 4450 5 10 0 0 0 0 1 210 | numslots=0 211 | T 300 4050 5 10 0 0 0 0 1 212 | net=Vcc:20 213 | T 300 4250 5 10 0 0 0 0 1 214 | net=GND:10 215 | T 300 4740 9 10 1 0 0 0 1 216 | ArduinoNano 217 | T 300 4650 5 10 0 0 0 0 1 218 | documentation=http://www-s.ti.com/sc/ds/sn74hc377.pdf 219 | P 0 1100 300 1100 1 0 0 220 | { 221 | T 200 1150 5 8 1 1 0 6 1 222 | pinnumber=12 223 | T 200 1050 5 8 0 1 0 8 1 224 | pinseq=12 225 | T 350 1100 9 8 1 1 0 0 1 226 | pinlabel=D9 227 | T 350 1100 5 8 0 1 0 2 1 228 | pintype=io 229 | } 230 | P 0 800 300 800 1 0 0 231 | { 232 | T 200 850 5 8 1 1 0 6 1 233 | pinnumber=13 234 | T 200 750 5 8 0 1 0 8 1 235 | pinseq=13 236 | T 350 800 9 8 1 1 0 0 1 237 | pinlabel=D10 238 | T 350 800 5 8 0 1 0 2 1 239 | pintype=io 240 | } 241 | P 0 500 300 500 1 0 0 242 | { 243 | T 200 550 5 8 1 1 0 6 1 244 | pinnumber=14 245 | T 200 450 5 8 0 1 0 8 1 246 | pinseq=14 247 | T 350 500 9 8 1 1 0 0 1 248 | pinlabel=D11 249 | T 350 500 5 8 0 1 0 2 1 250 | pintype=io 251 | } 252 | P 0 200 300 200 1 0 0 253 | { 254 | T 200 250 5 8 1 1 0 6 1 255 | pinnumber=15 256 | T 200 150 5 8 0 1 0 8 1 257 | pinseq=15 258 | T 350 200 9 8 1 1 0 0 1 259 | pinlabel=D12 260 | T 350 200 5 8 0 1 0 2 1 261 | pintype=io 262 | } 263 | P 2400 1100 2100 1100 1 0 0 264 | { 265 | T 2195 1145 5 8 1 1 0 0 1 266 | pinnumber=19 267 | T 2200 1050 5 8 0 1 0 2 1 268 | pinseq=19 269 | T 2045 1095 9 8 1 1 0 6 1 270 | pinlabel=A7 271 | T 2025 1100 5 8 0 1 0 8 1 272 | pintype=io 273 | } 274 | P 2400 800 2100 800 1 0 0 275 | { 276 | T 2195 845 5 8 1 1 0 0 1 277 | pinnumber=18 278 | T 2200 750 5 8 0 1 0 2 1 279 | pinseq=18 280 | T 2045 795 9 8 1 1 0 6 1 281 | pinlabel=AREF 282 | T 2025 800 5 8 0 1 0 8 1 283 | pintype=in 284 | } 285 | P 2400 500 2100 500 1 0 0 286 | { 287 | T 2195 545 5 8 1 1 0 0 1 288 | pinnumber=17 289 | T 2200 450 5 8 0 1 0 2 1 290 | pinseq=17 291 | T 2045 495 9 8 1 1 0 6 1 292 | pinlabel=3V3 293 | T 2025 500 5 8 0 1 0 8 1 294 | pintype=out 295 | } 296 | P 0 4100 300 4100 1 0 0 297 | { 298 | T 200 4150 5 8 1 1 0 6 1 299 | pinnumber=2 300 | T 200 4050 5 8 0 1 0 8 1 301 | pinseq=2 302 | T 350 4100 9 8 1 1 0 0 1 303 | pinlabel=D0/RX 304 | T 350 4100 5 8 0 1 0 2 1 305 | pintype=io 306 | } 307 | P 0 4400 300 4400 1 0 0 308 | { 309 | T 200 4450 5 8 1 1 0 6 1 310 | pinnumber=1 311 | T 200 4350 5 8 0 1 0 8 1 312 | pinseq=1 313 | T 350 4400 9 8 1 1 0 0 1 314 | pinlabel=D1/TX 315 | T 350 4400 5 8 0 1 0 2 1 316 | pintype=io 317 | } 318 | P 2100 4100 2400 4100 1 0 1 319 | { 320 | T 2200 4150 5 8 1 1 0 0 1 321 | pinnumber=29 322 | T 2200 4050 5 8 0 1 0 2 1 323 | pinseq=29 324 | T 2050 4100 9 8 1 1 0 6 1 325 | pinlabel=GND 326 | T 2050 4100 5 8 0 1 0 8 1 327 | pintype=out 328 | } 329 | P 2100 4400 2400 4400 1 0 1 330 | { 331 | T 2200 4450 5 8 1 1 0 0 1 332 | pinnumber=30 333 | T 2200 4350 5 8 0 1 0 2 1 334 | pinseq=30 335 | T 2050 4400 9 8 1 1 0 6 1 336 | pinlabel=Vin 337 | T 2050 4400 5 8 0 1 0 8 1 338 | pintype=in 339 | } 340 | P 2100 200 2400 200 1 0 1 341 | { 342 | T 2200 250 5 8 1 1 0 0 1 343 | pinnumber=16 344 | T 2200 150 5 8 0 1 0 2 1 345 | pinseq=16 346 | T 2050 200 9 8 1 1 0 6 1 347 | pinlabel=D13 348 | T 2050 200 5 8 0 1 0 8 1 349 | pintype=io 350 | } 351 | -------------------------------------------------------------------------------- /schematics/Arduino_programmer.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/Arduino_programmer.pdf -------------------------------------------------------------------------------- /schematics/Arduino_programmer.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | C 40600 46200 1 90 0 ArduinoNano.sym 3 | { 4 | T 37150 46500 5 10 0 0 90 0 1 5 | device=74377 6 | T 35800 48200 5 10 1 1 90 6 1 7 | refdes=ARD 8 | T 36950 46500 5 10 0 0 90 0 1 9 | footprint=DIP20 10 | } 11 | C 44500 46200 1 90 0 74595-1.sym 12 | { 13 | T 41660 46500 5 10 0 0 90 0 1 14 | device=74595 15 | T 41800 47900 5 10 1 1 90 6 1 16 | refdes=SHIFT0 17 | T 41450 46500 5 10 0 0 90 0 1 18 | footprint=DIP16 19 | } 20 | C 47500 46200 1 90 0 74595-1.sym 21 | { 22 | T 44660 46500 5 10 0 0 90 0 1 23 | device=74595 24 | T 44800 47900 5 10 1 1 90 6 1 25 | refdes=SHIFT1 26 | T 44450 46500 5 10 0 0 90 0 1 27 | footprint=DIP16 28 | } 29 | C 36900 49200 1 0 0 vcc-1.sym 30 | N 37100 48600 37100 49200 4 31 | C 36900 44500 1 0 0 ground.sym 32 | N 37100 46200 37100 44800 4 33 | N 37100 44900 53300 44900 4 34 | N 42200 44900 42200 46200 4 35 | N 44300 46000 46400 46000 4 36 | N 44300 46000 44300 46200 4 37 | N 46400 46000 46400 46200 4 38 | N 37400 46200 37400 45100 4 39 | N 37400 45100 43400 45100 4 40 | N 43400 46200 43400 45100 4 41 | N 37700 46200 37700 45200 4 42 | N 37700 45200 46100 45200 4 43 | N 43100 46200 43100 45200 4 44 | N 46100 46200 46100 45200 4 45 | N 38000 46200 38000 45300 4 46 | N 38000 45300 45500 45300 4 47 | N 42500 46200 42500 45300 4 48 | N 45500 45300 45500 46200 4 49 | N 45200 44900 45200 46200 4 50 | C 53200 46300 1 90 0 AT28C64-1.sym 51 | { 52 | T 49750 46600 5 10 0 0 90 0 1 53 | device=74377 54 | T 49000 48300 5 10 0 1 90 6 1 55 | refdes=EEPROM 56 | T 49550 46600 5 10 0 0 90 0 1 57 | footprint=DIP20 58 | } 59 | N 47300 48300 47600 48300 4 60 | N 47600 48300 47600 45000 4 61 | N 47600 45000 49400 45000 4 62 | N 49400 45000 49400 46300 4 63 | N 47000 48200 47000 48400 4 64 | N 47000 48400 47700 48400 4 65 | N 47700 48400 47700 45100 4 66 | N 47700 45100 49700 45100 4 67 | N 49700 45100 49700 46300 4 68 | N 46700 48200 46700 48500 4 69 | N 46700 48500 47800 48500 4 70 | N 47800 48500 47800 45200 4 71 | N 47800 45200 50000 45200 4 72 | N 50000 45200 50000 46300 4 73 | N 46400 48200 46400 48600 4 74 | N 46400 48600 47900 48600 4 75 | N 47900 48600 47900 45300 4 76 | N 47900 45300 50300 45300 4 77 | N 50300 45300 50300 46300 4 78 | N 46100 48200 46100 48700 4 79 | N 46100 48700 48000 48700 4 80 | N 48000 48700 48000 45400 4 81 | N 48000 45400 50600 45400 4 82 | N 50600 45400 50600 46300 4 83 | N 45800 48200 45800 48800 4 84 | N 45800 48800 48100 48800 4 85 | N 48100 48800 48100 45500 4 86 | N 48100 45500 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45700 4 146 | N 39200 45700 39200 46200 4 147 | N 50600 48700 50600 50100 4 148 | N 50600 50100 41100 50100 4 149 | N 41100 50100 41100 45800 4 150 | N 41100 45800 39500 45800 4 151 | N 39500 45800 39500 46200 4 152 | N 50900 48700 50900 50200 4 153 | N 50900 50200 41200 50200 4 154 | N 41200 45900 41200 50200 4 155 | N 41200 45900 39800 45900 4 156 | N 39800 45900 39800 46200 4 157 | N 40100 46200 40100 46000 4 158 | N 40100 46000 41300 46000 4 159 | N 41300 46000 41300 50300 4 160 | N 41300 50300 51200 50300 4 161 | N 51200 50300 51200 48700 4 162 | N 45800 46200 45800 46100 4 163 | N 41600 46100 45800 46100 4 164 | N 42800 46100 42800 46200 4 165 | N 41600 46100 41600 48900 4 166 | N 41600 48900 37100 48900 4 167 | N 51500 48700 51500 50400 4 168 | N 51500 50400 41400 50400 4 169 | N 41400 46100 41400 50400 4 170 | N 41400 46100 40400 46100 4 171 | N 40400 46200 40400 46100 4 172 | N 40400 48600 40400 50500 4 173 | N 40400 50500 52400 50500 4 174 | N 52400 50500 52400 48700 4 175 | N 52100 48700 52100 48900 4 176 | N 52100 48900 53300 48900 4 177 | N 53300 48900 53300 44900 4 178 | -------------------------------------------------------------------------------- /schematics/RAM.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/RAM.pdf -------------------------------------------------------------------------------- /schematics/RAM.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | C 65400 53000 1 90 0 74157-1.sym 3 | { 4 | T 60860 53300 5 10 0 0 90 0 1 5 | device=74157 6 | T 61060 53300 5 10 0 0 90 0 1 7 | footprint=DIP16 8 | T 61200 54700 5 10 1 1 90 6 1 9 | refdes=SEL0 10 | } 11 | C 61000 53000 1 90 0 74157-1.sym 12 | { 13 | T 56460 53300 5 10 0 0 90 0 1 14 | device=74157 15 | T 56660 53300 5 10 0 0 90 0 1 16 | footprint=DIP16 17 | T 56800 54700 5 10 1 1 90 6 1 18 | refdes=SEL1 19 | } 20 | C 53900 54700 1 270 0 switch-dip8-1.sym 21 | { 22 | T 56475 53300 5 8 0 0 270 0 1 23 | device=SWITCH_DIP8 24 | T 56250 54400 5 10 1 1 270 0 1 25 | refdes=DIP0 26 | } 27 | N 56400 51100 56400 53400 4 28 | N 56100 51100 56100 53400 4 29 | N 55800 51100 55800 53400 4 30 | N 55500 51100 55500 53400 4 31 | N 55200 51100 55200 53400 4 32 | N 54900 51100 54900 53400 4 33 | N 54600 51100 54600 53400 4 34 | N 54300 51100 54300 53400 4 35 | N 41100 56200 56400 56200 4 36 | C 56200 56200 1 0 0 5V-plus-1.sym 37 | N 54300 54700 54300 56200 4 38 | N 54600 54700 54600 56200 4 39 | N 54900 54700 54900 56200 4 40 | N 55200 54700 55200 56200 4 41 | N 55500 54700 55500 56200 4 42 | N 55800 54700 55800 56200 4 43 | N 56100 54700 56100 56200 4 44 | N 56400 54700 56400 56200 4 45 | N 44100 50100 65200 50100 4 46 | C 57600 49700 1 0 0 ground.sym 47 | N 57800 50000 57800 50100 4 48 | C 54400 50200 1 90 0 resistor-1.sym 49 | { 50 | T 54000 50500 5 10 0 0 90 0 1 51 | device=RESISTOR 52 | T 54100 50400 5 10 0 1 90 0 1 53 | refdes=R? 54 | } 55 | C 54700 50200 1 90 0 resistor-1.sym 56 | { 57 | T 54300 50500 5 10 0 0 90 0 1 58 | device=RESISTOR 59 | T 54400 50400 5 10 0 1 90 0 1 60 | refdes=R? 61 | } 62 | C 55000 50200 1 90 0 resistor-1.sym 63 | { 64 | T 54600 50500 5 10 0 0 90 0 1 65 | device=RESISTOR 66 | T 54700 50400 5 10 0 1 90 0 1 67 | refdes=R? 68 | } 69 | C 55300 50200 1 90 0 resistor-1.sym 70 | { 71 | T 54900 50500 5 10 0 0 90 0 1 72 | device=RESISTOR 73 | T 55000 50400 5 10 0 1 90 0 1 74 | refdes=R? 75 | } 76 | C 55600 50200 1 90 0 resistor-1.sym 77 | { 78 | T 55200 50500 5 10 0 0 90 0 1 79 | device=RESISTOR 80 | T 55300 50400 5 10 0 1 90 0 1 81 | refdes=R? 82 | } 83 | C 55900 50200 1 90 0 resistor-1.sym 84 | { 85 | T 55500 50500 5 10 0 0 90 0 1 86 | device=RESISTOR 87 | T 55600 50400 5 10 0 1 90 0 1 88 | refdes=R? 89 | } 90 | C 56200 50200 1 90 0 resistor-1.sym 91 | { 92 | T 55800 50500 5 10 0 0 90 0 1 93 | device=RESISTOR 94 | T 55900 50400 5 10 0 1 90 0 1 95 | refdes=R? 96 | } 97 | C 56500 50200 1 90 0 resistor-1.sym 98 | { 99 | T 56100 50500 5 10 0 0 90 0 1 100 | device=RESISTOR 101 | T 56200 50400 5 10 0 1 90 0 1 102 | refdes=R? 103 | } 104 | N 54300 50200 54300 50100 4 105 | N 54600 50200 54600 50100 4 106 | N 54900 50200 54900 50100 4 107 | N 55200 50200 55200 50100 4 108 | N 55500 50200 55500 50100 4 109 | N 55800 50200 55800 50100 4 110 | N 56100 50200 56100 50100 4 111 | N 56400 50200 56400 50100 4 112 | N 48300 51400 66500 51400 4 113 | N 48000 51600 66500 51600 4 114 | N 47700 51800 66500 51800 4 115 | N 47400 52000 66500 52000 4 116 | N 47100 52200 66500 52200 4 117 | N 46800 52400 66500 52400 4 118 | N 46500 52600 66500 52600 4 119 | C 52800 53000 1 90 0 74245-1.sym 120 | { 121 | T 49450 53300 5 10 0 0 90 0 1 122 | device=74245 123 | T 49600 54700 5 10 1 1 90 6 1 124 | refdes=BUF_IN 125 | T 49250 53300 5 10 0 0 90 0 1 126 | footprint=DIP20 127 | } 128 | C 49300 53000 1 90 0 74245-1.sym 129 | { 130 | T 45950 53300 5 10 0 0 90 0 1 131 | device=74245 132 | T 46100 54700 5 10 1 1 90 6 1 133 | refdes=BUF_OUT 134 | T 45750 53300 5 10 0 0 90 0 1 135 | footprint=DIP20 136 | } 137 | N 65200 43800 65200 53000 4 138 | N 60800 53000 60800 50100 4 139 | N 50000 53000 50000 52700 4 140 | N 50300 53000 50300 52500 4 141 | N 50600 53000 50600 52300 4 142 | N 50900 53000 50900 52100 4 143 | N 51200 53000 51200 51900 4 144 | N 51500 53000 51500 51700 4 145 | N 51800 51500 51800 53000 4 146 | N 52100 53000 52100 51300 4 147 | N 52700 53000 52700 52900 4 148 | N 46500 55000 46500 55900 4 149 | N 50000 55000 50000 55900 4 150 | N 46800 55000 46800 55800 4 151 | N 50300 55000 50300 55800 4 152 | N 50600 55000 50600 55700 4 153 | N 47100 55000 47100 55700 4 154 | N 50900 55000 50900 55600 4 155 | N 51200 55000 51200 55500 4 156 | N 51500 55000 51500 55400 4 157 | N 51800 55000 51800 55300 4 158 | N 52100 55000 52100 55200 4 159 | N 47400 55000 47400 55600 4 160 | N 47700 55000 47700 55500 4 161 | N 48300 55000 48300 55300 4 162 | N 48000 55000 48000 55400 4 163 | N 48600 55000 48600 55200 4 164 | N 48600 51200 66500 51200 4 165 | N 65700 52900 60400 52900 4 166 | N 60400 53000 60400 52900 4 167 | N 64800 53000 64800 52900 4 168 | N 45800 52900 45800 56000 4 169 | N 45800 52900 48900 52900 4 170 | N 48900 53000 48900 52900 4 171 | N 45700 52800 52400 52800 4 172 | N 52400 53000 52400 52800 4 173 | C 63900 56900 1 270 0 7400-1.sym 174 | { 175 | T 64800 56400 5 10 0 0 270 0 1 176 | device=7400 177 | T 64800 56600 5 10 0 1 270 0 1 178 | refdes=U? 179 | T 66150 56400 5 10 0 0 270 0 1 180 | footprint=DIP14 181 | } 182 | C 63000 56600 1 180 0 7400-1.sym 183 | { 184 | T 62500 55700 5 10 0 0 180 0 1 185 | device=7400 186 | T 62700 55700 5 10 0 1 180 0 1 187 | refdes=U? 188 | T 62500 54350 5 10 0 0 180 0 1 189 | footprint=DIP14 190 | } 191 | N 63500 55600 64400 55600 4 192 | N 63500 55600 63500 55900 4 193 | N 63500 55900 63000 55900 4 194 | N 64200 56900 64200 59800 4 195 | N 45700 56100 45700 52800 4 196 | N 61600 56000 61600 59000 4 197 | N 65700 49000 65700 58000 4 198 | C 64100 58000 1 270 0 7404-1.sym 199 | { 200 | T 65000 57400 5 10 0 1 270 0 1 201 | device=7404 202 | T 65000 57700 5 10 0 1 270 0 1 203 | refdes=U? 204 | T 67600 57400 5 10 0 1 270 0 1 205 | footprint=DIP14 206 | } 207 | T 63600 59900 9 10 1 0 0 0 1 208 | \_ME\_ 209 | T 64100 59900 9 10 1 0 0 0 1 210 | \_MW\_ 211 | T 65600 59900 9 10 1 0 0 0 1 212 | CLK 213 | T 66500 51100 9 10 1 0 0 0 1 214 | D0 215 | T 66500 51300 9 10 1 0 0 0 1 216 | D1 217 | T 66500 51500 9 10 1 0 0 0 1 218 | D2 219 | T 66500 51700 9 10 1 0 0 0 1 220 | D3 221 | T 66500 51900 9 10 1 0 0 0 1 222 | D4 223 | T 66500 52100 9 10 1 0 0 0 1 224 | D5 225 | T 66500 52300 9 10 1 0 0 0 1 226 | D6 227 | T 66500 52500 9 10 1 0 0 0 1 228 | D7 229 | C 63200 56700 1 90 0 capacitor-1.sym 230 | { 231 | T 62500 56900 5 10 0 0 90 0 1 232 | device=CAPACITOR 233 | T 62700 56900 5 10 0 1 90 0 1 234 | refdes=C? 235 | T 62300 56900 5 10 0 0 90 0 1 236 | symversion=0.1 237 | } 238 | C 60600 56600 1 0 0 resistor-1.sym 239 | { 240 | T 60900 57000 5 10 0 0 0 0 1 241 | device=RESISTOR 242 | T 60800 56900 5 10 0 1 0 0 1 243 | refdes=R? 244 | } 245 | N 63000 56700 61500 56700 4 246 | N 65800 48900 65800 59800 4 247 | C 60400 56400 1 0 0 ground.sym 248 | C 60700 46300 1 90 0 74157-1.sym 249 | { 250 | T 56160 46600 5 10 0 0 90 0 1 251 | device=74157 252 | T 56360 46600 5 10 0 0 90 0 1 253 | footprint=DIP16 254 | T 56500 48000 5 10 1 1 90 6 1 255 | refdes=SEL0 256 | } 257 | C 56200 46300 1 90 0 74157-1.sym 258 | { 259 | T 51660 46600 5 10 0 0 90 0 1 260 | device=74157 261 | T 51860 46600 5 10 0 0 90 0 1 262 | footprint=DIP16 263 | T 52000 48000 5 10 1 1 90 6 1 264 | refdes=SEL1 265 | } 266 | C 48700 47900 1 270 0 switch-dip8-1.sym 267 | { 268 | T 51275 46500 5 8 0 0 270 0 1 269 | device=SWITCH_DIP8 270 | T 51450 47600 5 10 1 1 270 0 1 271 | refdes=DIP0 272 | } 273 | N 51200 44700 51200 46600 4 274 | N 51200 44700 59700 44700 4 275 | N 59700 44700 59700 46300 4 276 | N 50900 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49100 44100 5 10 0 0 90 0 1 309 | device=RESISTOR 310 | T 49200 44000 5 10 0 1 90 0 1 311 | refdes=R? 312 | } 313 | C 49800 43800 1 90 0 resistor-1.sym 314 | { 315 | T 49400 44100 5 10 0 0 90 0 1 316 | device=RESISTOR 317 | T 49500 44000 5 10 0 1 90 0 1 318 | refdes=R? 319 | } 320 | C 50100 43800 1 90 0 resistor-1.sym 321 | { 322 | T 49700 44100 5 10 0 0 90 0 1 323 | device=RESISTOR 324 | T 49800 44000 5 10 0 1 90 0 1 325 | refdes=R? 326 | } 327 | C 50400 43800 1 90 0 resistor-1.sym 328 | { 329 | T 50000 44100 5 10 0 0 90 0 1 330 | device=RESISTOR 331 | T 50100 44000 5 10 0 1 90 0 1 332 | refdes=R? 333 | } 334 | C 50700 43800 1 90 0 resistor-1.sym 335 | { 336 | T 50300 44100 5 10 0 0 90 0 1 337 | device=RESISTOR 338 | T 50400 44000 5 10 0 1 90 0 1 339 | refdes=R? 340 | } 341 | C 51000 43800 1 90 0 resistor-1.sym 342 | { 343 | T 50600 44100 5 10 0 0 90 0 1 344 | device=RESISTOR 345 | T 50700 44000 5 10 0 1 90 0 1 346 | refdes=R? 347 | } 348 | C 51300 43800 1 90 0 resistor-1.sym 349 | { 350 | T 50900 44100 5 10 0 0 90 0 1 351 | device=RESISTOR 352 | T 51000 44000 5 10 0 1 90 0 1 353 | refdes=R? 354 | } 355 | N 60500 46300 60500 43800 4 356 | N 56000 46300 56000 43800 4 357 | N 52400 49100 46500 49100 4 358 | N 53200 48300 53200 49000 4 359 | N 53200 49000 46800 49000 4 360 | N 54000 48300 54000 48900 4 361 | N 47100 48900 54000 48900 4 362 | N 54800 48300 54800 48800 4 363 | N 54800 48800 47400 48800 4 364 | N 56900 48300 56900 48700 4 365 | N 56900 48700 47700 48700 4 366 | N 57700 48600 48000 48600 4 367 | N 57700 48300 57700 48600 4 368 | N 58500 48300 58500 48500 4 369 | N 58500 48500 48300 48500 4 370 | N 60800 46100 55600 46100 4 371 | N 55600 46300 55600 46100 4 372 | N 60100 46300 60100 46100 4 373 | N 59300 44600 64000 44600 4 374 | N 58500 44800 63700 44800 4 375 | N 56900 45200 63100 45200 4 376 | N 54800 45400 62800 45400 4 377 | N 54000 45600 62500 45600 4 378 | N 53200 45800 62200 45800 4 379 | N 60800 46100 60800 49000 4 380 | N 47400 43800 65200 43800 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7432-1.sym 413 | { 414 | T 59700 48800 5 10 0 0 180 0 1 415 | device=7432 416 | T 60000 48800 5 10 0 1 180 0 1 417 | refdes=U? 418 | T 59700 47400 5 10 0 0 180 0 1 419 | footprint=DIP14 420 | } 421 | N 50000 50400 50000 50300 4 422 | N 60300 49000 65700 49000 4 423 | N 60300 49400 65500 49400 4 424 | T 64500 59900 9 10 1 0 0 0 1 425 | PGM 426 | N 45300 49200 59000 49200 4 427 | N 57200 55000 57200 55800 4 428 | N 57200 55800 53100 55800 4 429 | N 58000 55000 58000 55700 4 430 | N 58000 55700 53200 55700 4 431 | N 58800 55000 58800 55600 4 432 | N 58800 55600 53300 55600 4 433 | N 59600 55000 59600 55500 4 434 | N 53400 55500 59600 55500 4 435 | N 61600 55000 61600 55400 4 436 | N 61600 55400 53500 55400 4 437 | N 62400 55000 62400 55300 4 438 | N 62400 55300 53600 55300 4 439 | N 63200 54800 63200 55200 4 440 | N 63200 55200 53700 55200 4 441 | N 53800 55100 64000 55100 4 442 | N 64000 55100 64000 55000 4 443 | N 41700 55900 50000 55900 4 444 | N 42000 55800 50300 55800 4 445 | N 42300 55700 50600 55700 4 446 | N 42600 55600 50900 55600 4 447 | N 42900 55500 51200 55500 4 448 | N 43200 55400 51500 55400 4 449 | N 43500 55300 51800 55300 4 450 | N 43800 55200 52100 55200 4 451 | N 57200 53000 57200 52600 4 452 | N 57600 53000 57600 52700 4 453 | N 57600 52700 54300 52700 4 454 | N 58000 53000 58000 52400 4 455 | N 58400 53000 58400 52500 4 456 | N 58400 52500 54600 52500 4 457 | N 58800 53000 58800 52200 4 458 | N 59200 53000 59200 52300 4 459 | N 59200 52300 54900 52300 4 460 | N 59600 53000 59600 52000 4 461 | N 60000 53000 60000 52100 4 462 | N 60000 52100 55200 52100 4 463 | N 61600 53000 61600 51800 4 464 | N 62000 53000 62000 51900 4 465 | N 62000 51900 55500 51900 4 466 | N 62400 53000 62400 51600 4 467 | N 62800 53000 62800 51700 4 468 | N 62800 51700 55800 51700 4 469 | N 63200 53000 63200 51400 4 470 | N 63600 53000 63600 51500 4 471 | N 63600 51500 56100 51500 4 472 | N 64000 53000 64000 51200 4 473 | N 64400 53000 64400 51300 4 474 | N 64400 51300 56400 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45300 5 10 0 0 270 0 1 538 | symversion=0.1 539 | } 540 | C 47800 46100 1 270 0 led-1.sym 541 | { 542 | T 48400 45300 5 10 0 0 270 0 1 543 | device=LED 544 | T 48200 45300 5 10 0 1 270 0 1 545 | refdes=LED? 546 | T 48600 45300 5 10 0 0 270 0 1 547 | symversion=0.1 548 | } 549 | C 47500 46100 1 270 0 led-1.sym 550 | { 551 | T 48100 45300 5 10 0 0 270 0 1 552 | device=LED 553 | T 47900 45300 5 10 0 1 270 0 1 554 | refdes=LED? 555 | T 48300 45300 5 10 0 0 270 0 1 556 | symversion=0.1 557 | } 558 | C 47200 46100 1 270 0 led-1.sym 559 | { 560 | T 47800 45300 5 10 0 0 270 0 1 561 | device=LED 562 | T 47600 45300 5 10 0 1 270 0 1 563 | refdes=LED? 564 | T 48000 45300 5 10 0 0 270 0 1 565 | symversion=0.1 566 | } 567 | C 46900 46100 1 270 0 led-1.sym 568 | { 569 | T 47500 45300 5 10 0 0 270 0 1 570 | device=LED 571 | T 47300 45300 5 10 0 1 270 0 1 572 | refdes=LED? 573 | T 47700 45300 5 10 0 0 270 0 1 574 | symversion=0.1 575 | } 576 | C 46600 46100 1 270 0 led-1.sym 577 | { 578 | T 47200 45300 5 10 0 0 270 0 1 579 | device=LED 580 | T 47000 45300 5 10 0 1 270 0 1 581 | refdes=LED? 582 | T 47400 45300 5 10 0 0 270 0 1 583 | symversion=0.1 584 | } 585 | C 46300 46100 1 270 0 led-1.sym 586 | { 587 | T 46900 45300 5 10 0 0 270 0 1 588 | device=LED 589 | T 46700 45300 5 10 0 1 270 0 1 590 | refdes=LED? 591 | T 47100 45300 5 10 0 0 270 0 1 592 | symversion=0.1 593 | } 594 | C 46000 46900 1 270 0 led-1.sym 595 | { 596 | T 46600 46100 5 10 0 0 270 0 1 597 | device=LED 598 | T 46400 46100 5 10 0 1 270 0 1 599 | refdes=LED? 600 | T 46800 46100 5 10 0 0 270 0 1 601 | symversion=0.1 602 | } 603 | N 46200 46000 46200 45200 4 604 | N 46200 45200 48600 45200 4 605 | C 47500 44300 1 90 0 resistor-1.sym 606 | { 607 | T 47100 44600 5 10 0 0 90 0 1 608 | device=RESISTOR 609 | T 47200 44500 5 10 0 1 90 0 1 610 | refdes=R? 611 | } 612 | C 48800 56300 1 90 0 led-1.sym 613 | { 614 | T 48200 57100 5 10 0 0 90 0 1 615 | device=LED 616 | T 48400 57100 5 10 0 1 90 0 1 617 | refdes=LED? 618 | T 48000 57100 5 10 0 0 90 0 1 619 | symversion=0.1 620 | } 621 | C 48500 56300 1 90 0 led-1.sym 622 | { 623 | T 47900 57100 5 10 0 0 90 0 1 624 | device=LED 625 | T 48100 57100 5 10 0 1 90 0 1 626 | refdes=LED? 627 | T 47700 57100 5 10 0 0 90 0 1 628 | symversion=0.1 629 | } 630 | C 48200 56300 1 90 0 led-1.sym 631 | { 632 | T 47600 57100 5 10 0 0 90 0 1 633 | device=LED 634 | T 47800 57100 5 10 0 1 90 0 1 635 | refdes=LED? 636 | T 47400 57100 5 10 0 0 90 0 1 637 | symversion=0.1 638 | } 639 | C 47900 56300 1 90 0 led-1.sym 640 | { 641 | T 47300 57100 5 10 0 0 90 0 1 642 | device=LED 643 | T 47500 57100 5 10 0 1 90 0 1 644 | refdes=LED? 645 | T 47100 57100 5 10 0 0 90 0 1 646 | symversion=0.1 647 | } 648 | C 47600 56300 1 90 0 led-1.sym 649 | { 650 | T 47000 57100 5 10 0 0 90 0 1 651 | device=LED 652 | T 47200 57100 5 10 0 1 90 0 1 653 | refdes=LED? 654 | T 46800 57100 5 10 0 0 90 0 1 655 | symversion=0.1 656 | } 657 | C 47300 56300 1 90 0 led-1.sym 658 | { 659 | T 46700 57100 5 10 0 0 90 0 1 660 | device=LED 661 | T 46900 57100 5 10 0 1 90 0 1 662 | refdes=LED? 663 | T 46500 57100 5 10 0 0 90 0 1 664 | symversion=0.1 665 | } 666 | C 47000 56300 1 90 0 led-1.sym 667 | { 668 | T 46400 57100 5 10 0 0 90 0 1 669 | device=LED 670 | T 46600 57100 5 10 0 1 90 0 1 671 | refdes=LED? 672 | T 46200 57100 5 10 0 0 90 0 1 673 | symversion=0.1 674 | } 675 | C 46700 56300 1 90 0 led-1.sym 676 | { 677 | T 46100 57100 5 10 0 0 90 0 1 678 | device=LED 679 | T 46300 57100 5 10 0 1 90 0 1 680 | refdes=LED? 681 | T 45900 57100 5 10 0 0 90 0 1 682 | symversion=0.1 683 | } 684 | N 46500 56300 46500 55900 4 685 | N 46800 56300 46800 55800 4 686 | N 47100 56300 47100 55700 4 687 | N 47400 56300 47400 55600 4 688 | N 47700 56300 47700 55500 4 689 | N 48000 56300 48000 55400 4 690 | N 48300 56300 48300 55300 4 691 | N 48600 56300 48600 55200 4 692 | N 46500 57200 48700 57200 4 693 | C 48700 57100 1 0 0 resistor-1.sym 694 | { 695 | T 49000 57500 5 10 0 0 0 0 1 696 | device=RESISTOR 697 | T 48900 57400 5 10 0 1 0 0 1 698 | refdes=R2 699 | } 700 | C 49500 56900 1 0 0 ground.sym 701 | N 49600 57200 49700 57200 4 702 | C 60600 58900 1 90 0 switch-spst-1.sym 703 | { 704 | T 59900 59300 5 10 0 0 90 0 1 705 | device=SPST 706 | T 60300 59200 5 10 1 1 90 0 1 707 | refdes=PROG 708 | } 709 | C 60400 59700 1 0 0 5V-plus-1.sym 710 | C 45500 52600 1 90 0 AS6C6264-1.sym 711 | { 712 | T 42050 52900 5 10 0 0 90 0 1 713 | device=74377 714 | T 41300 54600 5 10 1 1 90 6 1 715 | refdes=SRAM 716 | T 41850 52900 5 10 0 0 90 0 1 717 | footprint=DIP28 718 | } 719 | N 41700 55900 41700 55000 4 720 | N 42000 55800 42000 55000 4 721 | N 42300 55700 42300 55000 4 722 | N 42600 55600 42600 55000 4 723 | N 42900 55500 42900 55000 4 724 | N 44700 56100 44700 55000 4 725 | N 43200 55400 43200 55000 4 726 | N 43500 55300 43500 55000 4 727 | N 43800 55200 43800 55000 4 728 | N 45600 50100 45600 55100 4 729 | N 44100 55000 44100 55100 4 730 | N 45000 55000 45000 55100 4 731 | N 44100 55100 45600 55100 4 732 | N 44400 55000 44400 56200 4 733 | N 45000 52600 45000 50100 4 734 | N 44700 52600 44700 50100 4 735 | N 44400 52600 44400 50100 4 736 | N 44100 52600 44100 50100 4 737 | N 45300 52600 45300 49200 4 738 | N 43800 52600 43800 49300 4 739 | N 43800 49300 48600 49300 4 740 | N 43500 52600 43500 49400 4 741 | N 43500 49400 48300 49400 4 742 | N 43200 52600 43200 49500 4 743 | N 43200 49500 48000 49500 4 744 | N 42900 52600 42900 49600 4 745 | N 42900 49600 47700 49600 4 746 | N 42600 52600 42600 49700 4 747 | N 42600 49700 47400 49700 4 748 | N 42300 52600 42300 49800 4 749 | N 42300 49800 47100 49800 4 750 | N 42000 52600 42000 49900 4 751 | N 42000 49900 46800 49900 4 752 | N 41700 52600 41700 50000 4 753 | N 41700 50000 46500 50000 4 754 | N 52100 51300 53800 51300 4 755 | N 65500 49400 65500 59000 4 756 | N 61600 49200 65600 49200 4 757 | N 65600 49200 65600 59100 4 758 | N 61300 48900 65800 48900 4 759 | N 64000 48300 64000 51200 4 760 | N 63700 48300 63700 51400 4 761 | N 63400 48300 63400 51600 4 762 | N 63100 48300 63100 51800 4 763 | N 62800 48300 62800 50400 4 764 | N 62800 50400 63000 50400 4 765 | N 63000 50400 63000 52000 4 766 | N 62500 48300 62500 52200 4 767 | N 62200 48300 62200 52400 4 768 | N 61900 48300 61900 52600 4 769 | N 47400 44300 47400 43800 4 770 | N 41100 50300 41100 56200 4 771 | N 49200 53000 49200 50100 4 772 | N 53000 56200 53000 52900 4 773 | N 53000 52900 52700 52900 4 774 | C 65400 58900 1 180 0 7404-1.sym 775 | { 776 | T 64800 58000 5 10 0 1 180 0 1 777 | device=7404 778 | T 65100 58000 5 10 0 1 180 0 1 779 | refdes=U? 780 | T 64800 55400 5 10 0 1 180 0 1 781 | footprint=DIP14 782 | } 783 | C 64100 58900 1 180 0 7404-1.sym 784 | { 785 | T 63500 58000 5 10 0 1 180 0 1 786 | device=7404 787 | T 63800 58000 5 10 0 1 180 0 1 788 | refdes=U? 789 | T 63500 55400 5 10 0 1 180 0 1 790 | footprint=DIP14 791 | } 792 | N 63000 57600 63000 58400 4 793 | N 65400 58400 65800 58400 4 794 | N 60600 58000 65700 58000 4 795 | N 60600 57800 60600 58900 4 796 | C 60700 56900 1 90 0 resistor-1.sym 797 | { 798 | T 60300 57200 5 10 0 0 90 0 1 799 | device=RESISTOR 800 | T 60400 57100 5 10 0 1 90 0 1 801 | refdes=R? 802 | } 803 | N 64700 59000 64700 59800 4 804 | N 64300 58400 64100 58400 4 805 | N 65300 59100 65300 59800 4 806 | N 65300 59100 65600 59100 4 807 | N 65500 59000 64700 59000 4 808 | N 61600 59000 63700 59000 4 809 | N 63700 59000 63700 59800 4 810 | N 60600 56700 60600 56900 4 811 | N 63000 56300 63000 56700 4 812 | -------------------------------------------------------------------------------- /schematics/RS latch.sym: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | P 0 2000 300 2000 1 0 0 3 | { 4 | T 200 2050 5 8 1 1 0 6 1 5 | pinnumber=1 6 | T 200 1950 5 8 0 1 0 8 1 7 | pinseq=3 8 | T 350 2000 9 8 1 1 0 0 1 9 | pinlabel=R 10 | T 350 2000 5 8 0 1 0 2 1 11 | pintype=in 12 | } 13 | P 0 1700 300 1700 1 0 0 14 | { 15 | T 200 1750 5 8 1 1 0 6 1 16 | pinnumber=2 17 | T 200 1650 5 8 0 1 0 8 1 18 | pinseq=4 19 | T 350 1700 9 8 1 1 0 0 1 20 | pinlabel=S 21 | T 350 1700 5 8 0 1 0 2 1 22 | pintype=in 23 | } 24 | P 900 2000 1200 2000 1 0 1 25 | { 26 | T 1000 2050 5 8 1 1 0 0 1 27 | pinnumber=7 28 | T 1000 1950 5 8 0 1 0 2 1 29 | pinseq=9 30 | T 850 2000 9 8 1 1 0 6 1 31 | pinlabel=Q 32 | T 850 2000 5 8 0 1 0 8 1 33 | pintype=out 34 | } 35 | P 900 1700 1200 1700 1 0 1 36 | { 37 | T 1000 1750 5 8 1 1 0 0 1 38 | pinnumber=6 39 | T 1000 1650 5 8 0 1 0 2 1 40 | pinseq=12 41 | T 850 1700 9 8 1 1 0 6 1 42 | pinlabel=\_Q\_ 43 | T 850 1700 5 8 0 1 0 8 1 44 | pintype=in 45 | } 46 | B 300 1400 600 900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 47 | T 300 3450 5 10 0 0 0 0 1 48 | device=74377 49 | T 300 3650 5 10 0 0 0 0 1 50 | footprint=DIP20 51 | T 300 3850 5 10 0 0 0 0 1 52 | description=8 D-type flip-flops with enable 53 | T 300 4450 5 10 0 0 0 0 1 54 | numslots=0 55 | T 300 4050 5 10 0 0 0 0 1 56 | net=Vcc:20 57 | T 300 4250 5 10 0 0 0 0 1 58 | net=GND:10 59 | T 300 4650 5 10 0 0 0 0 1 60 | documentation=http://www-s.ti.com/sc/ds/sn74hc377.pdf 61 | -------------------------------------------------------------------------------- /schematics/clock.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/clock.pdf -------------------------------------------------------------------------------- /schematics/clock.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | C 47000 44100 1 90 0 lm555-1.sym 3 | { 4 | T 44600 46400 5 10 0 0 90 0 1 5 | device=LM555 6 | T 47000 45900 5 10 1 1 90 0 1 7 | refdes=auto_clk 8 | } 9 | C 42900 47900 1 0 0 5V-plus-1.sym 10 | N 43100 47800 52100 47800 4 11 | N 43100 44900 43100 47900 4 12 | C 45200 46800 1 90 0 resistor-1.sym 13 | { 14 | T 44800 47100 5 10 0 0 90 0 1 15 | device=RESISTOR 16 | T 44900 47000 5 10 0 1 90 0 1 17 | refdes=R? 18 | } 19 | C 43300 46600 1 0 0 resistor-variable-1.sym 20 | { 21 | T 44100 47500 5 10 0 0 0 0 1 22 | device=VARIABLE_RESISTOR 23 | T 43900 47000 5 10 0 1 0 0 1 24 | refdes=R? 25 | } 26 | C 44200 46600 1 0 0 resistor-1.sym 27 | { 28 | T 44500 47000 5 10 0 0 0 0 1 29 | device=RESISTOR 30 | T 44400 46900 5 10 0 1 0 0 1 31 | refdes=R? 32 | } 33 | N 43300 46700 43300 46500 4 34 | N 43300 46500 45500 46500 4 35 | N 45500 46500 45500 46400 4 36 | N 45100 46800 45100 46400 4 37 | N 44200 45700 43100 45700 4 38 | N 44200 44900 43100 44900 4 39 | N 45500 44100 43900 44100 4 40 | N 43900 44100 43900 46500 4 41 | C 45700 42900 1 90 0 capacitor-1.sym 42 | { 43 | T 45000 43100 5 10 0 0 90 0 1 44 | device=CAPACITOR 45 | T 45200 43100 5 10 0 1 90 0 1 46 | refdes=C? 47 | T 44800 43100 5 10 0 0 90 0 1 48 | symversion=0.1 49 | } 50 | N 45500 44100 45500 43800 4 51 | N 45500 42900 53600 42900 4 52 | N 46600 42900 46600 44100 4 53 | C 46400 42600 1 0 0 ground.sym 54 | C 46100 46400 1 90 0 capacitor-1.sym 55 | { 56 | T 45400 46600 5 10 0 0 90 0 1 57 | device=CAPACITOR 58 | T 45600 46600 5 10 0 1 90 0 1 59 | refdes=C? 60 | T 45200 46600 5 10 0 0 90 0 1 61 | symversion=0.1 62 | } 63 | N 45100 47700 45100 47800 4 64 | C 54000 44100 1 90 0 lm555-1.sym 65 | { 66 | T 51600 46400 5 10 0 0 90 0 1 67 | device=LM555 68 | T 54000 45900 5 10 1 1 90 0 1 69 | refdes=manual_clk 70 | } 71 | C 52600 43000 1 90 0 switch-pushbutton-nc-1.sym 72 | { 73 | T 52800 42550 5 10 0 0 90 0 1 74 | device=SWITCH_PUSHBUTTON_NC 75 | T 52250 43400 5 10 1 1 90 0 1 76 | refdes=M_CLK 77 | } 78 | N 51100 46400 52500 46400 4 79 | C 52200 46400 1 90 0 resistor-1.sym 80 | { 81 | T 51800 46700 5 10 0 0 90 0 1 82 | device=RESISTOR 83 | T 51900 46600 5 10 0 1 90 0 1 84 | refdes=R? 85 | } 86 | N 52100 47800 52100 47300 4 87 | C 51300 42900 1 90 0 capacitor-1.sym 88 | { 89 | T 50600 43100 5 10 0 0 90 0 1 90 | device=CAPACITOR 91 | T 50800 43100 5 10 0 1 90 0 1 92 | refdes=C? 93 | T 50400 43100 5 10 0 0 90 0 1 94 | symversion=0.1 95 | } 96 | N 51100 43800 51100 46400 4 97 | N 51200 44900 50900 44900 4 98 | N 50900 44900 50900 47800 4 99 | N 51200 45700 50900 45700 4 100 | C 53100 46300 1 90 0 capacitor-1.sym 101 | { 102 | T 52400 46500 5 10 0 0 90 0 1 103 | device=CAPACITOR 104 | T 52600 46500 5 10 0 1 90 0 1 105 | refdes=C? 106 | T 52200 46500 5 10 0 0 90 0 1 107 | symversion=0.1 108 | } 109 | N 52900 46300 52900 46400 4 110 | T 43600 47300 9 10 1 0 0 0 1 111 | SPD 112 | C 50700 44100 1 90 0 lm555-1.sym 113 | { 114 | T 48300 46400 5 10 0 0 90 0 1 115 | device=LM555 116 | T 50700 45900 5 10 1 1 90 0 1 117 | refdes=clk_sel 118 | } 119 | N 47700 45700 47700 47800 4 120 | C 49800 46400 1 90 0 capacitor-1.sym 121 | { 122 | T 49100 46600 5 10 0 0 90 0 1 123 | device=CAPACITOR 124 | T 49300 46600 5 10 0 1 90 0 1 125 | refdes=C? 126 | T 48900 46600 5 10 0 0 90 0 1 127 | symversion=0.1 128 | } 129 | N 47500 45700 47900 45700 4 130 | C 47800 44800 1 90 0 resistor-1.sym 131 | { 132 | T 47400 45100 5 10 0 0 90 0 1 133 | device=RESISTOR 134 | T 47500 45000 5 10 0 1 90 0 1 135 | refdes=R? 136 | } 137 | N 47700 44800 47900 44800 4 138 | N 47900 44800 47900 44900 4 139 | C 47600 44800 1 90 0 resistor-1.sym 140 | { 141 | T 47200 45100 5 10 0 0 90 0 1 142 | device=RESISTOR 143 | T 47300 45000 5 10 0 1 90 0 1 144 | refdes=R? 145 | } 146 | N 50300 44100 50300 42900 4 147 | C 47700 42900 1 90 0 switch-pushbutton-spdt-1.sym 148 | { 149 | T 47825 42450 5 10 0 0 90 0 1 150 | device=SWITCH_PUSHBUTTON_SPDT 151 | T 47300 43300 5 10 1 1 90 0 1 152 | refdes=CLK_SEL 153 | } 154 | N 52500 42900 52500 43000 4 155 | N 49200 44100 47500 44100 4 156 | N 47700 44800 47700 43900 4 157 | N 47500 43900 47500 44800 4 158 | C 54100 46300 1 270 0 7400-1.sym 159 | { 160 | T 55000 45800 5 10 0 0 270 0 1 161 | device=7400 162 | T 55000 46000 5 10 0 1 270 0 1 163 | refdes=U? 164 | T 56350 45800 5 10 0 0 270 0 1 165 | footprint=DIP14 166 | } 167 | C 54900 47400 1 270 0 7404-1.sym 168 | { 169 | T 55800 46800 5 10 0 0 270 0 1 170 | device=7404 171 | T 55800 47100 5 10 0 1 270 0 1 172 | refdes=U? 173 | T 58400 46800 5 10 0 0 270 0 1 174 | footprint=DIP14 175 | } 176 | N 50300 46400 50300 47400 4 177 | N 50300 47400 55400 47400 4 178 | N 54400 46300 54400 47400 4 179 | N 54800 46300 54800 47500 4 180 | N 46600 47500 54800 47500 4 181 | N 46600 47500 46600 46400 4 182 | C 55100 46300 1 270 0 7400-1.sym 183 | { 184 | T 56000 45800 5 10 0 0 270 0 1 185 | device=7400 186 | T 56000 46000 5 10 0 1 270 0 1 187 | refdes=U? 188 | T 57350 45800 5 10 0 0 270 0 1 189 | footprint=DIP14 190 | } 191 | N 55800 46300 55800 47600 4 192 | N 53600 47600 55800 47600 4 193 | N 53600 46400 53600 47600 4 194 | N 53600 44100 53600 42900 4 195 | C 54600 45000 1 270 0 7400-1.sym 196 | { 197 | T 55500 44500 5 10 0 0 270 0 1 198 | device=7400 199 | T 55500 44700 5 10 0 1 270 0 1 200 | refdes=U? 201 | T 56850 44500 5 10 0 0 270 0 1 202 | footprint=DIP14 203 | } 204 | N 54600 45000 54900 45000 4 205 | N 55300 45000 55600 45000 4 206 | C 55300 43700 1 270 0 7400-1.sym 207 | { 208 | T 56200 43200 5 10 0 0 270 0 1 209 | device=7400 210 | T 56200 43400 5 10 0 1 270 0 1 211 | refdes=U? 212 | T 57550 43200 5 10 0 0 270 0 1 213 | footprint=DIP14 214 | } 215 | N 56000 43700 56000 48000 4 216 | C 55300 42400 1 270 0 7404-1.sym 217 | { 218 | T 56200 41800 5 10 0 0 270 0 1 219 | device=7404 220 | T 56200 42100 5 10 0 1 270 0 1 221 | refdes=U? 222 | T 58800 41800 5 10 0 0 270 0 1 223 | footprint=DIP14 224 | } 225 | N 55100 43700 55600 43700 4 226 | T 55900 48100 9 10 1 0 0 0 1 227 | \_HLT\_ 228 | T 55600 40900 9 10 1 0 0 0 1 229 | CLK 230 | N 55800 41300 55800 41100 4 231 | C 55100 41500 1 180 0 led-1.sym 232 | { 233 | T 54300 40900 5 10 0 0 180 0 1 234 | device=LED 235 | T 54300 41100 5 10 0 1 180 0 1 236 | refdes=LED? 237 | T 54300 40700 5 10 0 0 180 0 1 238 | symversion=0.1 239 | } 240 | N 55100 41300 55800 41300 4 241 | C 53700 42000 1 90 0 resistor-1.sym 242 | { 243 | T 53300 42300 5 10 0 0 90 0 1 244 | device=RESISTOR 245 | T 53400 42200 5 10 0 1 90 0 1 246 | refdes=R? 247 | } 248 | N 53600 42000 53600 41300 4 249 | N 53600 41300 54200 41300 4 250 | C 51000 44000 1 90 0 resistor-1.sym 251 | { 252 | T 50600 44300 5 10 0 0 90 0 1 253 | device=RESISTOR 254 | T 50700 44200 5 10 0 1 90 0 1 255 | refdes=R? 256 | } 257 | N 50900 44000 52500 44000 4 258 | N 49200 46400 49200 47600 4 259 | N 47100 42900 47100 47600 4 260 | N 52500 44000 52500 44100 4 261 | N 45900 47600 52900 47600 4 262 | N 52900 47200 52900 47600 4 263 | N 49600 47300 49600 47600 4 264 | N 45900 47600 45900 47300 4 265 | -------------------------------------------------------------------------------- /schematics/control_logic.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/control_logic.pdf -------------------------------------------------------------------------------- /schematics/control_logic.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | C 39900 43900 1 90 0 74161-1.sym 3 | { 4 | T 35760 44200 5 10 0 0 90 0 1 5 | device=74161 6 | T 35960 44200 5 10 0 0 90 0 1 7 | footprint=DIP16 8 | T 36100 45600 5 10 1 1 90 6 1 9 | refdes=T_CNT 10 | } 11 | N 38900 43900 38900 41300 4 12 | N 38500 41300 42200 41300 4 13 | T 41900 41100 9 10 1 0 0 0 1 14 | \_TR\_ 15 | N 38500 43900 38500 41300 4 16 | N 36500 42700 58100 42700 4 17 | C 35100 50800 1 270 0 7404-1.sym 18 | { 19 | T 36000 50200 5 10 0 0 270 0 1 20 | device=7404 21 | T 36000 50500 5 10 0 1 270 0 1 22 | refdes=U? 23 | T 38600 50200 5 10 0 0 270 0 1 24 | footprint=DIP14 25 | } 26 | N 35600 43800 35600 49700 4 27 | N 35600 43800 39300 43800 4 28 | N 39300 43800 39300 43900 4 29 | T 35400 50900 9 10 1 0 0 0 1 30 | CLK 31 | C 36300 42400 1 0 0 ground.sym 32 | C 40200 45900 1 270 0 AT28C64-1.sym 33 | { 34 | T 43650 45600 5 10 0 0 270 0 1 35 | device=74377 36 | T 44400 43900 5 10 1 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41500 5 10 0 1 270 0 1 679 | refdes=LED? 680 | T 43900 41500 5 10 0 0 270 0 1 681 | symversion=0.1 682 | } 683 | C 43400 42300 1 270 0 led-1.sym 684 | { 685 | T 44000 41500 5 10 0 0 270 0 1 686 | device=LED 687 | T 43800 41500 5 10 0 1 270 0 1 688 | refdes=LED? 689 | T 44200 41500 5 10 0 0 270 0 1 690 | symversion=0.1 691 | } 692 | C 42000 42300 1 270 0 led-1.sym 693 | { 694 | T 42600 41500 5 10 0 0 270 0 1 695 | device=LED 696 | T 42400 41500 5 10 0 1 270 0 1 697 | refdes=LED? 698 | T 42800 41500 5 10 0 0 270 0 1 699 | symversion=0.1 700 | } 701 | N 42200 42400 42200 42300 4 702 | N 43300 42400 43300 42300 4 703 | N 43600 42400 43600 42300 4 704 | C 40100 42300 1 0 0 resistor-1.sym 705 | { 706 | T 40400 42700 5 10 0 0 0 0 1 707 | device=RESISTOR 708 | T 40300 42600 5 10 0 1 0 0 1 709 | refdes=R? 710 | } 711 | N 43300 41400 43300 40900 4 712 | N 43300 40900 43700 40900 4 713 | N 43600 41400 43600 40800 4 714 | N 43600 40800 44000 40800 4 715 | N 42200 41400 42200 41300 4 716 | N 38100 43600 40000 43600 4 717 | N 36300 49700 36300 47200 4 718 | N 36300 47200 40000 47200 4 719 | N 40000 43600 40000 47200 4 720 | C 35800 50800 1 270 0 7404-1.sym 721 | { 722 | T 36700 50200 5 10 0 0 270 0 1 723 | device=7404 724 | T 36700 50500 5 10 0 1 270 0 1 725 | refdes=U? 726 | T 39300 50200 5 10 0 0 270 0 1 727 | footprint=DIP14 728 | } 729 | T 36000 50900 9 10 1 0 0 0 1 730 | PROG 731 | -------------------------------------------------------------------------------- /schematics/decimal_display.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/decimal_display.pdf -------------------------------------------------------------------------------- /schematics/decimal_display.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | C 44600 55300 1 90 0 lm555-1.sym 3 | { 4 | T 42200 57600 5 10 0 0 90 0 1 5 | device=LM555 6 | T 44600 57100 5 10 1 1 90 0 1 7 | refdes=D_CLK 8 | } 9 | N 43100 55300 43100 55200 4 10 | N 43100 55200 44700 55200 4 11 | N 44700 55200 44700 57800 4 12 | C 42800 57600 1 90 0 resistor-1.sym 13 | { 14 | T 42400 57900 5 10 0 0 90 0 1 15 | device=RESISTOR 16 | T 42500 57800 5 10 0 1 90 0 1 17 | refdes=R? 18 | } 19 | C 42400 57600 1 90 0 resistor-1.sym 20 | { 21 | T 42000 57900 5 10 0 0 90 0 1 22 | device=RESISTOR 23 | T 42100 57800 5 10 0 1 90 0 1 24 | refdes=R? 25 | } 26 | N 42700 57600 42300 57600 4 27 | N 42700 58500 43100 58500 4 28 | N 43100 58500 43100 57600 4 29 | N 44700 57800 43100 57800 4 30 | N 41800 59400 57000 59400 4 31 | N 42300 58500 42300 59400 4 32 | N 41800 56100 41800 59400 4 33 | C 43700 57700 1 90 0 capacitor-1.sym 34 | { 35 | T 43000 57900 5 10 0 0 90 0 1 36 | device=CAPACITOR 37 | T 43200 57900 5 10 0 1 90 0 1 38 | refdes=C? 39 | T 42800 57900 5 10 0 0 90 0 1 40 | symversion=0.1 41 | } 42 | N 43500 57700 43500 57600 4 43 | C 44000 53800 1 0 0 ground.sym 44 | N 44200 55300 44200 54100 4 45 | N 44200 57600 44200 57700 4 46 | N 44200 57700 44800 57700 4 47 | C 48900 55600 1 90 0 74161-1.sym 48 | { 49 | T 44760 55900 5 10 0 0 90 0 1 50 | device=74161 51 | T 44960 55900 5 10 0 0 90 0 1 52 | footprint=DIP16 53 | T 45100 57300 5 10 1 1 90 6 1 54 | refdes=D_CTR 55 | } 56 | N 44800 57700 44800 55300 4 57 | N 48300 55300 44800 55300 4 58 | N 44900 59400 44900 55400 4 59 | N 44900 55400 48700 55400 4 60 | N 47100 55400 47100 55600 4 61 | N 48300 55300 48300 55600 4 62 | N 47500 55400 47500 55600 4 63 | N 47900 55600 47900 55400 4 64 | N 48700 55400 48700 55600 4 65 | N 45500 57600 45500 57800 4 66 | N 45500 57800 49000 57800 4 67 | N 45900 57600 45900 57900 4 68 | N 45900 57900 49100 57900 4 69 | C 52100 55600 1 90 0 74139-1.sym 70 | { 71 | T 49150 55900 5 10 0 0 90 0 1 72 | device=74139 73 | T 49300 57300 5 10 1 1 90 6 1 74 | refdes=D_MPLX 75 | T 48950 55900 5 10 0 0 90 0 1 76 | footprint=DIP16 77 | } 78 | N 49000 57800 49000 55400 4 79 | N 49000 55400 50000 55400 4 80 | N 50000 55100 50000 55600 4 81 | N 49700 55600 49700 54100 4 82 | N 51000 55600 51000 55400 4 83 | N 51000 55400 52200 55400 4 84 | N 52200 55400 52200 59400 4 85 | N 49100 57900 49100 55500 4 86 | N 50300 55500 49100 55500 4 87 | N 50300 55000 50300 55600 4 88 | N 49700 57600 49700 59300 4 89 | N 50000 57600 50000 59100 4 90 | N 50300 57600 50300 58900 4 91 | N 50600 57600 50600 58700 4 92 | N 50600 58700 57800 58700 4 93 | N 50300 58900 59800 58900 4 94 | N 50000 59100 61800 59100 4 95 | C 64700 59400 1 180 0 resistor-1.sym 96 | { 97 | T 64400 59000 5 10 0 0 180 0 1 98 | device=RESISTOR 99 | T 64500 59100 5 10 0 1 180 0 1 100 | refdes=R? 101 | } 102 | C 62700 59200 1 180 0 resistor-1.sym 103 | { 104 | T 62400 58800 5 10 0 0 180 0 1 105 | device=RESISTOR 106 | T 62500 58900 5 10 0 1 180 0 1 107 | refdes=R? 108 | } 109 | C 60700 59000 1 180 0 resistor-1.sym 110 | { 111 | T 60400 58600 5 10 0 0 180 0 1 112 | device=RESISTOR 113 | T 60500 58700 5 10 0 1 180 0 1 114 | refdes=R? 115 | } 116 | C 58700 58800 1 180 0 resistor-1.sym 117 | { 118 | T 58400 58400 5 10 0 0 180 0 1 119 | device=RESISTOR 120 | T 58500 58500 5 10 0 1 180 0 1 121 | refdes=R? 122 | } 123 | N 58700 58700 58700 57500 4 124 | N 60700 57500 60700 58900 4 125 | N 62700 59100 62700 57500 4 126 | N 64700 59300 64700 57500 4 127 | N 49700 59300 63800 59300 4 128 | C 56600 55200 1 90 0 AT28C64-1.sym 129 | { 130 | T 53150 55500 5 10 0 0 90 0 1 131 | device=74377 132 | T 52400 57200 5 10 1 1 90 6 1 133 | refdes=EEPROM 134 | T 52950 55500 5 10 0 0 90 0 1 135 | footprint=DIP20 136 | } 137 | N 55300 54900 55300 53800 4 138 | N 55000 54800 55000 53800 4 139 | N 54400 54600 54400 53800 4 140 | N 53200 54200 53200 53800 4 141 | N 53500 54300 53500 53800 4 142 | N 53800 54400 53800 53800 4 143 | N 54100 54500 54100 53800 4 144 | N 41700 54100 57000 54100 4 145 | N 57000 59400 57000 56700 4 146 | C 57100 54200 1 90 0 resistor-1.sym 147 | { 148 | T 56700 54500 5 10 0 0 90 0 1 149 | device=RESISTOR 150 | T 56800 54400 5 10 0 1 90 0 1 151 | refdes=R? 152 | } 153 | N 56100 55200 56100 54100 4 154 | N 56400 55200 56400 54100 4 155 | C 56800 56700 1 270 0 switcap-switch-1.sym 156 | { 157 | T 57200 56600 5 10 0 0 270 0 1 158 | device=SWITCAP-switch 159 | T 56800 56400 5 10 0 1 270 0 1 160 | clock=clk 161 | T 57200 56300 5 10 1 1 270 0 1 162 | refdes=NEG_D 163 | } 164 | N 57000 55900 57000 55100 4 165 | C 56400 57500 1 270 0 7-digit-display.sym 166 | { 167 | T 59850 57200 5 10 0 0 270 0 1 168 | device=74377 169 | T 59600 55800 5 10 0 1 270 6 1 170 | refdes=U? 171 | T 60050 57200 5 10 0 0 270 0 1 172 | footprint=DIP20 173 | } 174 | C 58400 57500 1 270 0 7-digit-display.sym 175 | { 176 | T 61850 57200 5 10 0 0 270 0 1 177 | device=74377 178 | T 61600 55800 5 10 0 1 270 6 1 179 | refdes=U? 180 | T 62050 57200 5 10 0 0 270 0 1 181 | footprint=DIP20 182 | } 183 | C 60400 57500 1 270 0 7-digit-display.sym 184 | { 185 | T 63850 57200 5 10 0 0 270 0 1 186 | device=74377 187 | T 63600 55800 5 10 0 1 270 6 1 188 | refdes=U? 189 | T 64050 57200 5 10 0 0 270 0 1 190 | footprint=DIP20 191 | } 192 | C 62400 57500 1 270 0 7-digit-display.sym 193 | { 194 | T 65850 57200 5 10 0 0 270 0 1 195 | device=74377 196 | T 65600 55800 5 10 0 1 270 6 1 197 | refdes=U? 198 | T 66050 57200 5 10 0 0 270 0 1 199 | footprint=DIP20 200 | } 201 | N 58100 57500 58100 58500 4 202 | N 54900 58500 64100 58500 4 203 | N 64100 58500 64100 57500 4 204 | N 58400 57500 58400 58400 4 205 | N 54600 58400 64400 58400 4 206 | N 64400 58400 64400 57500 4 207 | N 59000 57500 59000 58300 4 208 | N 54300 58300 65000 58300 4 209 | N 65000 58300 65000 57500 4 210 | N 59300 57500 59300 58200 4 211 | N 54000 58200 65300 58200 4 212 | N 65300 58200 65300 57500 4 213 | N 60100 57500 60100 58500 4 214 | N 60400 57500 60400 58400 4 215 | N 61000 57500 61000 58300 4 216 | N 61300 57500 61300 58200 4 217 | N 62100 57500 62100 58500 4 218 | N 62400 57500 62400 58400 4 219 | N 63000 57500 63000 58300 4 220 | N 63300 57500 63300 58200 4 221 | C 41600 59400 1 0 0 5V-plus-1.sym 222 | N 55800 57600 55800 59400 4 223 | N 56800 54100 56800 57700 4 224 | N 56800 57700 55500 57700 4 225 | N 56100 57700 56100 57600 4 226 | N 55500 57700 55500 57600 4 227 | N 57500 55600 64100 55600 4 228 | N 57600 55500 64400 55500 4 229 | N 57700 55400 65000 55400 4 230 | N 57800 55300 65300 55300 4 231 | N 58100 55600 58100 55700 4 232 | N 58400 55500 58400 55700 4 233 | N 59000 55400 59000 55700 4 234 | N 59300 55300 59300 55700 4 235 | N 60100 55700 60100 55600 4 236 | N 60400 55700 60400 55500 4 237 | N 61000 55700 61000 55400 4 238 | N 61300 55700 61300 55300 4 239 | N 62100 55700 62100 55600 4 240 | N 62400 55700 62400 55500 4 241 | N 63000 55700 63000 55400 4 242 | N 63300 55700 63300 55300 4 243 | N 64100 55700 64100 55600 4 244 | N 64400 55700 64400 55500 4 245 | N 65000 55700 65000 55400 4 246 | N 65300 55700 65300 55300 4 247 | N 57800 57800 57800 55300 4 248 | N 53100 57900 57700 57900 4 249 | N 57700 57900 57700 55400 4 250 | N 53400 58000 57600 58000 4 251 | N 57600 58000 57600 55500 4 252 | N 53700 58100 57500 58100 4 253 | N 57500 58100 57500 55600 4 254 | N 57800 57800 52800 57800 4 255 | N 52800 57800 52800 57600 4 256 | N 53100 57900 53100 57600 4 257 | N 53400 58000 53400 57600 4 258 | N 53700 58100 53700 57600 4 259 | N 54000 58200 54000 57600 4 260 | N 54300 58300 54300 57600 4 261 | N 54600 57600 54600 58400 4 262 | N 54900 57600 54900 58500 4 263 | T 55200 53400 9 10 1 0 0 0 1 264 | A0 265 | T 54900 53400 9 10 1 0 0 0 1 266 | A1 267 | T 54600 53400 9 10 1 0 0 0 1 268 | A2 269 | T 54300 53400 9 10 1 0 0 0 1 270 | A3 271 | T 54000 53400 9 10 1 0 0 0 1 272 | A4 273 | T 53700 53400 9 10 1 0 0 0 1 274 | A5 275 | T 53400 53400 9 10 1 0 0 0 1 276 | A6 277 | T 53100 53400 9 10 1 0 0 0 1 278 | A7 279 | N 55300 54900 52800 54900 4 280 | N 52800 54900 52800 55200 4 281 | N 55000 54800 53100 54800 4 282 | N 53100 54800 53100 55200 4 283 | N 53400 55200 53400 54700 4 284 | N 53400 54700 54700 54700 4 285 | N 54700 54700 54700 53800 4 286 | N 53700 55200 53700 54600 4 287 | N 53700 54600 54400 54600 4 288 | N 54000 55200 54000 54500 4 289 | N 54000 54500 54100 54500 4 290 | N 54300 55200 54300 54400 4 291 | N 54300 54400 53800 54400 4 292 | N 54600 55200 54600 54300 4 293 | N 54600 54300 53500 54300 4 294 | N 54900 55200 54900 54200 4 295 | N 54900 54200 53200 54200 4 296 | N 55800 55100 57000 55100 4 297 | N 43500 58600 41700 58600 4 298 | N 41700 54100 41700 58600 4 299 | C 41600 51000 1 0 0 5V-plus-1.sym 300 | C 43800 48600 1 90 0 resistor-1.sym 301 | { 302 | T 43400 48900 5 10 0 0 90 0 1 303 | device=RESISTOR 304 | T 43500 48800 5 10 0 1 90 0 1 305 | refdes=R? 306 | } 307 | C 43800 47100 1 90 0 resistor-1.sym 308 | { 309 | T 43400 47400 5 10 0 0 90 0 1 310 | device=RESISTOR 311 | T 43500 47300 5 10 0 1 90 0 1 312 | refdes=R? 313 | } 314 | C 43800 45700 1 90 0 resistor-1.sym 315 | { 316 | T 43400 46000 5 10 0 0 90 0 1 317 | device=RESISTOR 318 | T 43500 45900 5 10 0 1 90 0 1 319 | refdes=R? 320 | } 321 | C 44700 47900 1 0 0 lm741-1.sym 322 | { 323 | T 45325 48850 5 8 0 0 0 0 1 324 | device=LM741 325 | T 44900 48800 5 10 0 1 0 0 1 326 | refdes=U? 327 | } 328 | C 44000 46500 1 0 0 lm741-1.sym 329 | { 330 | T 44625 47450 5 8 0 0 0 0 1 331 | device=LM741 332 | T 44200 47400 5 10 0 1 0 0 1 333 | refdes=U? 334 | } 335 | N 43700 48000 43700 48600 4 336 | N 43700 48100 44700 48100 4 337 | N 44700 48500 41800 48500 4 338 | N 43700 47100 44000 47100 4 339 | N 41800 46700 44000 46700 4 340 | N 43700 47100 43700 46600 4 341 | N 44500 47300 44500 51000 4 342 | N 41800 51000 45200 51000 4 343 | N 45200 48700 45200 51000 4 344 | N 41800 45700 45200 45700 4 345 | N 44500 45700 44500 46500 4 346 | N 45200 45700 45200 47900 4 347 | N 45700 47700 45700 48300 4 348 | N 45000 46900 45700 46900 4 349 | N 45700 46900 45700 47400 4 350 | N 46900 47700 47800 47700 4 351 | N 47000 49600 47000 47400 4 352 | N 46900 47400 47000 47400 4 353 | N 47000 49600 43600 49600 4 354 | C 43600 49100 1 0 1 npn-3.sym 355 | { 356 | T 42700 49600 5 10 0 0 0 6 1 357 | device=NPN_TRANSISTOR 358 | T 42700 49600 5 10 0 1 0 6 1 359 | refdes=Q? 360 | } 361 | N 43000 50100 41800 50100 4 362 | N 43000 49100 43000 45700 4 363 | C 41700 45400 1 0 0 gnd-1.sym 364 | N 43700 49500 43700 51000 4 365 | C 41900 50100 1 90 0 resistor-1.sym 366 | { 367 | T 41500 50400 5 10 0 0 90 0 1 368 | device=RESISTOR 369 | T 41600 50300 5 10 0 1 90 0 1 370 | refdes=R? 371 | } 372 | C 41900 48900 1 90 0 resistor-1.sym 373 | { 374 | T 41500 49200 5 10 0 0 90 0 1 375 | device=RESISTOR 376 | T 41600 49100 5 10 0 1 90 0 1 377 | refdes=R? 378 | } 379 | N 41800 48900 41800 46700 4 380 | N 41800 49800 41800 50100 4 381 | U 42500 51500 42500 45200 10 0 382 | U 42500 45200 47200 45200 10 0 383 | U 47200 45200 47200 51500 10 0 384 | U 47200 51500 42500 51500 10 0 385 | C 45700 45700 1 0 0 RS latch.sym 386 | { 387 | T 46000 49150 5 10 0 0 0 0 1 388 | device=74377 389 | T 46000 49350 5 10 0 0 0 0 1 390 | footprint=DIP20 391 | } 392 | N 55800 55100 55800 55200 4 393 | N 50000 55100 55200 55100 4 394 | N 55200 55100 55200 55200 4 395 | N 57000 54200 57000 54100 4 396 | N 50300 55000 55500 55000 4 397 | N 55500 55000 55500 55200 4 398 | -------------------------------------------------------------------------------- /schematics/instruction_register.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/instruction_register.pdf -------------------------------------------------------------------------------- /schematics/instruction_register.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | N 59700 52100 59700 51900 4 3 | N 59700 51900 63400 51900 4 4 | N 60000 52100 60000 51700 4 5 | N 60000 51700 63400 51700 4 6 | N 60300 52100 60300 51500 4 7 | N 60300 51500 63400 51500 4 8 | N 60600 52100 60600 51300 4 9 | N 60600 51300 63400 51300 4 10 | N 60900 52100 60900 51100 4 11 | N 60900 51100 63400 51100 4 12 | N 61200 52100 61200 50900 4 13 | N 61200 50900 63400 50900 4 14 | N 61500 52100 61500 50700 4 15 | N 61500 50700 63400 50700 4 16 | N 61800 52100 61800 50500 4 17 | N 61800 50500 63400 50500 4 18 | N 61800 54100 61800 55100 4 19 | N 58700 54200 61800 54200 4 20 | N 61500 54100 61500 55100 4 21 | N 58400 54300 61500 54300 4 22 | N 61200 54100 61200 55100 4 23 | N 58100 54400 61200 54400 4 24 | N 60900 54100 60900 55100 4 25 | N 57800 54500 60900 54500 4 26 | N 60600 54100 60600 55100 4 27 | N 57500 54600 60600 54600 4 28 | N 60300 54100 60300 55100 4 29 | N 57200 54700 60300 54700 4 30 | N 60000 54100 60000 55100 4 31 | N 56900 54800 60000 54800 4 32 | N 59700 54100 59700 55100 4 33 | N 56600 54900 59700 54900 4 34 | C 58500 53700 1 270 0 led-1.sym 35 | { 36 | T 59100 52900 5 10 0 0 270 0 1 37 | device=LED 38 | T 58900 52900 5 10 0 1 270 0 1 39 | refdes=LED? 40 | T 59300 52900 5 10 0 0 270 0 1 41 | symversion=0.1 42 | } 43 | C 58200 53700 1 270 0 led-1.sym 44 | { 45 | T 58800 52900 5 10 0 0 270 0 1 46 | device=LED 47 | T 58600 52900 5 10 0 1 270 0 1 48 | refdes=LED? 49 | T 59000 52900 5 10 0 0 270 0 1 50 | symversion=0.1 51 | } 52 | C 57900 53700 1 270 0 led-1.sym 53 | { 54 | T 58500 52900 5 10 0 0 270 0 1 55 | device=LED 56 | T 58300 52900 5 10 0 1 270 0 1 57 | refdes=LED? 58 | T 58700 52900 5 10 0 0 270 0 1 59 | symversion=0.1 60 | } 61 | C 57600 53700 1 270 0 led-1.sym 62 | { 63 | T 58200 52900 5 10 0 0 270 0 1 64 | device=LED 65 | T 58000 52900 5 10 0 1 270 0 1 66 | refdes=LED? 67 | T 58400 52900 5 10 0 0 270 0 1 68 | symversion=0.1 69 | } 70 | C 57300 53700 1 270 0 led-1.sym 71 | { 72 | T 57900 52900 5 10 0 0 270 0 1 73 | device=LED 74 | T 57700 52900 5 10 0 1 270 0 1 75 | refdes=LED? 76 | T 58100 52900 5 10 0 0 270 0 1 77 | symversion=0.1 78 | } 79 | C 57000 53700 1 270 0 led-1.sym 80 | { 81 | T 57600 52900 5 10 0 0 270 0 1 82 | device=LED 83 | T 57400 52900 5 10 0 1 270 0 1 84 | refdes=LED? 85 | T 57800 52900 5 10 0 0 270 0 1 86 | symversion=0.1 87 | } 88 | C 56700 53700 1 270 0 led-1.sym 89 | { 90 | T 57300 52900 5 10 0 0 270 0 1 91 | device=LED 92 | T 57100 52900 5 10 0 1 270 0 1 93 | refdes=LED? 94 | T 57500 52900 5 10 0 0 270 0 1 95 | symversion=0.1 96 | } 97 | C 56400 53700 1 270 0 led-1.sym 98 | { 99 | T 57000 52900 5 10 0 0 270 0 1 100 | device=LED 101 | T 56800 52900 5 10 0 1 270 0 1 102 | refdes=LED? 103 | T 57200 52900 5 10 0 0 270 0 1 104 | symversion=0.1 105 | } 106 | N 58700 54200 58700 53700 4 107 | N 58400 54300 58400 53700 4 108 | N 58100 54400 58100 53700 4 109 | N 57800 54500 57800 53700 4 110 | N 57500 54600 57500 53700 4 111 | N 57200 54700 57200 53700 4 112 | N 56900 54800 56900 53700 4 113 | N 56600 54900 56600 53700 4 114 | N 56600 52800 58700 52800 4 115 | C 57600 51900 1 90 0 resistor-1.sym 116 | { 117 | T 57200 52200 5 10 0 0 90 0 1 118 | device=RESISTOR 119 | T 57300 52100 5 10 0 1 90 0 1 120 | refdes=R? 121 | } 122 | C 57300 51600 1 0 0 ground.sym 123 | T 59600 55200 9 10 1 0 0 0 1 124 | I7 125 | T 59900 55200 9 10 1 0 0 0 1 126 | I6 127 | T 60200 55200 9 10 1 0 0 0 1 128 | I5 129 | T 60500 55200 9 10 1 0 0 0 1 130 | I4 131 | T 60800 55200 9 10 1 0 0 0 1 132 | I3 133 | T 61100 55200 9 10 1 0 0 0 1 134 | I2 135 | T 61400 55200 9 10 1 0 0 0 1 136 | I1 137 | T 61700 55200 9 10 1 0 0 0 1 138 | I0 139 | N 62400 52100 62700 52100 4 140 | N 62700 52100 62700 55200 4 141 | N 63000 52000 63000 55200 4 142 | N 62100 52000 63000 52000 4 143 | T 62900 55300 9 10 1 0 0 0 1 144 | \_IRW\_ 145 | T 62500 55300 9 10 1 0 0 0 1 146 | CLK 147 | T 63500 51800 9 10 1 0 0 0 1 148 | D7 149 | T 63500 51600 9 10 1 0 0 0 1 150 | D6 151 | T 63500 51400 9 10 1 0 0 0 1 152 | D5 153 | T 63500 51200 9 10 1 0 0 0 1 154 | D4 155 | T 63500 51000 9 10 1 0 0 0 1 156 | D3 157 | T 63500 50800 9 10 1 0 0 0 1 158 | D2 159 | T 63500 50600 9 10 1 0 0 0 1 160 | D1 161 | T 63500 50400 9 10 1 0 0 0 1 162 | D0 163 | C 62600 52100 1 90 0 74377-1.sym 164 | { 165 | T 59150 52400 5 10 0 0 90 0 1 166 | device=74377 167 | T 59300 53800 5 10 0 1 90 6 1 168 | refdes=U? 169 | T 58950 52400 5 10 0 0 90 0 1 170 | footprint=DIP20 171 | } 172 | N 62100 52100 62100 52000 4 173 | -------------------------------------------------------------------------------- /schematics/power.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/power.pdf -------------------------------------------------------------------------------- /schematics/power.ps: -------------------------------------------------------------------------------- 1 | %!PS-Adobe-3.0 2 | %%Creator: gEDA gschem 1.8.1-20121123-13-g875406c 3 | %%CreationDate: Thu Sep 21 15:53:32 2017 4 | %%Title: /home/james/power.sch 5 | %%Author: (null) 6 | %%BoundingBox: 0 0 595 841 7 | %%Orientation: Landscape 8 | %%Pages: 1 9 | %%EndComments 10 | %%BeginProlog 11 | % Prolog for gEDA, define all the functions needed for rendering 12 | % schematics on Postscript devices 13 | 14 | 15 | % Draw a line from the second coordinate to the first 16 | % x2 y2 x1 y1 width line - 17 | /line { 18 | setlinewidth 19 | % pop off first element and moveto 20 | moveto 21 | % pop off remaining elements and draw a line segment 22 | lineto 23 | % draw it 24 | stroke 25 | } bind def 26 | 27 | 28 | % Draw a dot 29 | % x y r dot - 30 | /dot { 31 | 0 360 arc fill 32 | } bind def 33 | 34 | % Draw a dot-dashed line, a bunch of lined segments, 35 | % if the array element only has length two, draw a dot. 36 | % [ [x2 y2 x1 y1] [x4 y4 x3 y3] [x5 y5] ... ] width dashed - 37 | /width 0 def 38 | /dashed { 39 | dup 2.0 div /width exch def 40 | setlinewidth 41 | % pop off each line segment and draw it as a dot or as a line 42 | { 43 | aload length 2 gt 44 | { moveto lineto stroke} 45 | { width dot } ifelse 46 | } forall 47 | } bind def 48 | 49 | % Draw an arc segment 50 | % x y r ang1 ang2 width darc - 51 | /darc { 52 | setlinewidth 53 | arc stroke 54 | } bind def 55 | 56 | % Draw a series of arc segment bits, if the array element only has a single 57 | % element in it, draw a dot. 58 | % [ [sa1 ea1] [sa2 ea2] ... ] x y r width dashedarc - 59 | /x 0 def 60 | /y 0 def 61 | /dashedarc { 62 | dup /width exch def 63 | setlinewidth 64 | /r exch def 65 | /y exch def 66 | /x exch def 67 | { aload length 1 gt 68 | { 69 | % this element had two angles in it 70 | % extract start and stop angles 71 | x y r % drop x y and r onto stack 72 | % at this point we have: sa ea x y r 73 | % we need x y r sa ea 74 | % so.. 75 | 5 -2 roll 76 | % and add it to the current path, and draw it 77 | arc stroke 78 | } { 79 | % this element only had one angle in it, place a 80 | % filled dot at the appropriate place 81 | % compute center point of the arc using the angle 82 | % that is on the top of the stack 83 | dup % angle angle 84 | cos r mul x add % angle x 85 | exch % x angle 86 | sin r mul y add % x y 87 | width % x y width/2 88 | dot % draw the dot 89 | } ifelse 90 | } forall 91 | 92 | % Now draw it 93 | stroke 94 | } bind def 95 | 96 | % Draw a box 97 | % width height x y linethickness box - 98 | /box { 99 | setlinewidth 100 | moveto 101 | exch dup 0 rlineto % w h, h w w 0 -- Draw bottom line 102 | exch 0 exch rlineto % h w, w h 0, w 0 h -- Draw right line 103 | neg 0 rlineto % w, -w 0 -- Draw Top line 104 | closepath % finish and draw it 105 | stroke 106 | } bind def 107 | 108 | % Draw a filled box 109 | % width height x y fbox - 110 | /fbox { 111 | moveto 112 | exch dup 0 rlineto 113 | exch 0 exch rlineto 114 | neg 0 rlineto 115 | closepath 116 | fill 117 | } bind def 118 | 119 | % Font reincoding utilities 120 | 121 | % ISOLatin1Encoding, extended with remaining uncoded glyphs 122 | /ISOLatin1Extended [ 123 | /.notdef /Lslash /lslash /OE /oe /Scaron /scaron /Zcaron /zcaron 124 | /Ydieresis /trademark /bullet /dagger /daggerdbl /ellipsis /emdash 125 | /endash /fi /fl /florin /fraction /guilsinglleft /guilsinglright 126 | /perthousand /quotedblbase /quotedblleft /quotedblright 127 | /quotesinglbase /quotesingle /.notdef /.notdef /.notdef /space 128 | /exclam /quotedbl /numbersign /dollar /percent /ampersand 129 | /quoteright /parenleft /parenright /asterisk /plus /comma /minus 130 | /period /slash /zero /one /two /three /four /five /six /seven /eight 131 | /nine /colon /semicolon /less /equal /greater /question /at /A /B /C 132 | /D /E /F /G /H /I /J /K /L /M /N /O /P /Q /R /S /T /U /V /W /X /Y /Z 133 | /bracketleft /backslash /bracketright /asciicircum /underscore 134 | /quoteleft /a /b /c /d /e /f /g /h /i /j /k /l /m /n /o /p /q /r /s 135 | /t /u /v /w /x /y /z /braceleft /bar /braceright /asciitilde 136 | /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef 137 | /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef 138 | /.notdef /.notdef /.notdef /dotlessi /grave /acute /circumflex 139 | /tilde /macron /breve /dotaccent /dieresis /.notdef /ring /cedilla 140 | /.notdef /hungarumlaut /ogonek /caron /space /exclamdown /cent 141 | /sterling /currency /yen /brokenbar /section /dieresis /copyright 142 | /ordfeminine /guillemotleft /logicalnot /hyphen /registered /macron 143 | /degree /plusminus /twosuperior /threesuperior /acute /mu /paragraph 144 | /periodcentered /cedilla /onesuperior /ordmasculine /guillemotright 145 | /onequarter /onehalf /threequarters /questiondown /Agrave /Aacute 146 | /Acircumflex /Atilde /Adieresis /Aring /AE /Ccedilla /Egrave /Eacute 147 | /Ecircumflex /Edieresis /Igrave /Iacute /Icircumflex /Idieresis /Eth 148 | /Ntilde /Ograve /Oacute /Ocircumflex /Otilde /Odieresis /multiply 149 | /Oslash /Ugrave /Uacute /Ucircumflex /Udieresis /Yacute /Thorn 150 | /germandbls /agrave /aacute /acircumflex /atilde /adieresis /aring 151 | /ae /ccedilla /egrave /eacute /ecircumflex /edieresis /igrave 152 | /iacute /icircumflex /idieresis /eth /ntilde /ograve /oacute 153 | /ocircumflex /otilde /odieresis /divide /oslash /ugrave /uacute 154 | /ucircumflex /udieresis /yacute /thorn /ydieresis 155 | ] def 156 | 157 | % `new-font-name' `encoding-vector' `old-font-name' RE - 158 | /RE { 159 | findfont 160 | dup maxlength dict begin { 161 | 1 index /FID ne { def } { pop pop } ifelse 162 | } forall 163 | /Encoding exch def 164 | dup /FontName exch def 165 | currentdict end definefont pop 166 | } bind def 167 | 168 | % Text handling functions, select the font and scale it, then we need 169 | % only to apply the appropriate transformations to get the text 170 | % justified into the right spots. The bad thing here is that we don't 171 | % do any kerning, so the output may look a bit strange. 172 | 173 | % compute the height of one character and return lly and ury 174 | % (char) charheight lly ury 175 | /charheight { 176 | gsave % push graphics state 177 | newpath % clear current path 178 | 0 0 moveto % Set current point 179 | false charpath % get path 180 | flattenpath % flatten path 181 | pathbbox % stack = llx lly urx ury 182 | exch pop % stack = llx lly ury 183 | 3 -1 roll pop % stack = lly ury 184 | grestore % pop graphics state 185 | } bind def 186 | 187 | % compute the height of a string, one character at a time 188 | % (string) stringheight lly ury 189 | /lly 0.0 def 190 | /ury 0.0 def 191 | 192 | /stringheight { 193 | /lly 0.0 def % initial value of heightmin 194 | /ury 0.0 def % initial value of heightmax 195 | { % work through string 196 | ( ) dup 0 4 -1 roll put % create one character string 197 | charheight % measure it's height 198 | dup ury gt { % if ury gt heightmax 199 | /ury exch def % update with new value 200 | } { 201 | pop % else discard ury 202 | } ifelse 203 | dup lly lt { % if lly lt heightmin 204 | /lly exch def % update with new value 205 | } { 206 | pop % else discard lly 207 | } ifelse 208 | } forall 209 | lly ury % Return the results 210 | } bind def 211 | 212 | % calculate the string width taking into account the escapes. 213 | /mystrx 0.0 def 214 | /mystry 0.0 def 215 | /mystresc false def 216 | 217 | /mystringwidth { 218 | /mystrx 0.0 def 219 | /mystry 0.0 def 220 | /mystresc false def 221 | { % work through string 222 | % did we process the escape character last? 223 | mystresc { 224 | % last character was escape 225 | % handle the escape 226 | % is it an _ = 95? 227 | dup 95 eq { 228 | pop % we don't need the character anymore 229 | % toggle drawing overbars 230 | 0.0 0.0 % make it like it never happened... 231 | } { 232 | % otherwise measure the character 233 | (\\ ) dup 1 4 -1 roll put % count a \ and the character 234 | stringwidth 235 | } ifelse 236 | % and reset the flag 237 | /mystresc false def 238 | } { 239 | % last character was not escape 240 | % is this escape 241 | dup 92 eq { 242 | % yes, escape character, set flag 243 | /mystresc true def 244 | pop % drop character 245 | 0.0 0.0 % make like this character has no width and height 246 | } { 247 | ( ) dup 0 4 -1 roll put % create one character string 248 | stringwidth % measure it's height/width 249 | } ifelse 250 | } ifelse 251 | % accumulate x and y movements 252 | mystry add /mystry exch def 253 | mystrx add /mystrx exch def 254 | } forall 255 | mystrx mystry % drop results on stack 256 | } bind def 257 | 258 | % Render a string with overbars 259 | % 260 | /escaped false def 261 | /drawoverbar false def 262 | /fontsize 0.0 def 263 | 264 | %string1 string2 append - 265 | /append { 266 | 2 copy length exch length add % find new length 267 | string dup % string1 string2 string string 268 | 4 2 roll % string string string1 string2 269 | 2 index 0 3 index 270 | % string string string1 string2 string 0 string1 271 | putinterval % string string string1 string2 272 | exch length exch putinterval 273 | } bind def 274 | 275 | % If drawoverbar is set, draw a line of the same length as the given string 276 | % string overbarshowline - 277 | /overbarshowline { 278 | % print overbar if necessary 279 | stringwidth pop 0 280 | drawoverbar { 281 | rlineto 282 | gsave stroke grestore 283 | } { 284 | rmoveto 285 | } ifelse 286 | } bind def 287 | 288 | % Draws overbars for the given string, then shows the string itself 289 | % string overbarshow 290 | /overbarshow { 291 | /overbarshowacc () def 292 | /overbarshowtxt () def 293 | 294 | gsave 295 | fontsize 10.0 div setlinewidth 296 | 0 fontsize rmoveto % move to (0,overbarheight) 297 | 298 | { % work through string 299 | escaped { 300 | % the last character was the escape 301 | % handle the escape 302 | % is it an _ = 95? 303 | dup 95 eq { 304 | pop % we don't need the character anymore 305 | overbarshowacc overbarshowline 306 | % toggle drawing overbars 307 | /drawoverbar drawoverbar not def 308 | 309 | % Append the contents off the accumulator to the text 310 | % string we're eventually going to show 311 | /overbarshowtxt overbarshowtxt overbarshowacc append def 312 | 313 | % clear accumulator 314 | /overbarshowacc () def 315 | } { 316 | % add to accumulator 317 | (\\ ) dup 1 4 -1 roll put 318 | overbarshowacc exch append 319 | /overbarshowacc exch def 320 | } ifelse 321 | % and reset the flag 322 | /escaped false def 323 | } { 324 | % check for escape character \ = 92 325 | dup 92 eq { 326 | % yes, escape character, set flag 327 | /escaped true def 328 | pop % drop character 329 | } { 330 | % add to accumulator 331 | ( ) dup 0 4 -1 roll put 332 | overbarshowacc exch append 333 | /overbarshowacc exch def 334 | } ifelse 335 | } ifelse 336 | } forall 337 | % Catch any leftovers 338 | overbarshowacc overbarshowline 339 | overbarshowtxt overbarshowacc append 340 | 341 | grestore 342 | show 343 | } bind def 344 | 345 | % 346 | % hcenter rjustify vcenter vjustify spacing [(line1) (line2) ... ] rot x y size text - 347 | /stringw 0.0 def 348 | /stringh 0.0 def 349 | /spacing 0.0 def 350 | /strings [ ] def 351 | /stringtxt ( ) def 352 | /stringcount 0 def 353 | /rot 0.0 def 354 | 355 | /text { 356 | gsave % save state for later 357 | /drawoverbar false def % start by not drawing overbars 358 | 359 | dup /fontsize exch def % save font size for corrections later 360 | % do font selection 361 | /gEDAFont findfont 362 | exch scalefont 363 | setfont 364 | 365 | % set up coordinates 366 | translate % move origin to given point 367 | rotate % rotate so that text is drawn 368 | 0 0 moveto 369 | dup length /stringcount exch def % Get number of strings 370 | /strings exch def % save strings 371 | /spacing exch def 372 | % do we have more than 1 string to render? 373 | stringcount 1 eq { 374 | /stringtxt strings aload pop def % get the string 375 | /stringw stringtxt mystringwidth pop neg def % get the -width 376 | /stringh stringtxt stringheight exch pop neg def% get the -height 377 | 378 | % First do vertical calculations 379 | % hcenter rjustify vcenter vjustify 380 | % vertical justification 381 | { 0 stringh rmoveto } if 382 | % vertical center 383 | { 0 stringh 0.3571425 mul rmoveto } if % not 0.5, so that 384 | % it looks nicer 385 | % Then do horizontal calculations 386 | % right justify 387 | { stringw 0 rmoveto } if 388 | % center 389 | { stringw 2.0 div 0 rmoveto } if 390 | % Draw the text 391 | stringtxt overbarshow 392 | } { 393 | % More than one line, compute bounding box for the text 394 | 395 | % vertical height, don't use the actual hieght of the characters 396 | % assume that the user wants to make the baselines line up with two 397 | % text boxes placed side by side 398 | /stringh stringcount spacing mul neg def 399 | % Now figure out horizontal size, this amounts to keeping track 400 | % of the longest string 401 | /stringw 0.0 def 402 | strings { 403 | mystringwidth pop 404 | dup stringw gt { 405 | /stringw exch def 406 | } { 407 | pop 408 | } ifelse 409 | } forall 410 | /stringw stringw neg def % get the -width 411 | 412 | % First do vertical calculations 413 | % hcenter rjustify vcenter vjustify 414 | % vertical justification 415 | { 0 stringh fontsize add rmoveto } if 416 | % vertical center 417 | { 0 stringh 0.5 mul rmoveto } if 418 | % Then do horizontal calculations 419 | % right justify 420 | { stringw 0 rmoveto } if 421 | % center 422 | { stringw 2.0 div 0 rmoveto } if 423 | % now move up to the first line and begin rendering 424 | 0 stringcount 1 sub spacing mul rmoveto 425 | strings { 426 | gsave % Save starting point 427 | overbarshow % render the text 428 | grestore 429 | 0 spacing neg rmoveto 430 | } forall 431 | } ifelse 432 | grestore % Restore old state 433 | } bind def 434 | 435 | 436 | %%EndProlog 437 | %%Page: 1 1 438 | /gEDAFont ISOLatin1Extended /Helvetica RE 439 | 2 setlinecap 440 | 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47000 730 | 25 731 | 0 360 arc 732 | fill 733 | newpath 734 | 38000 47000 735 | 25 736 | 0 360 arc 737 | fill 738 | newpath 739 | 34700 47000 740 | 25 741 | 0 360 arc 742 | fill 743 | newpath 744 | 34700 47000 745 | 25 746 | 0 360 arc 747 | fill 748 | newpath 749 | 34700 48800 750 | 25 751 | 0 360 arc 752 | fill 753 | newpath 754 | 34700 48800 755 | 25 756 | 0 360 arc 757 | fill 758 | newpath 759 | 35500 48800 760 | 25 761 | 0 360 arc 762 | fill 763 | newpath 764 | 35500 48800 765 | 25 766 | 0 360 arc 767 | fill 768 | newpath 769 | 35500 47000 770 | 25 771 | 0 360 arc 772 | fill 773 | newpath 774 | 35500 47000 775 | 25 776 | 0 360 arc 777 | fill 778 | newpath 779 | 39800 48600 780 | 25 781 | 0 360 arc 782 | fill 783 | newpath 784 | 39800 48600 785 | 25 786 | 0 360 arc 787 | fill 788 | newpath 789 | 39800 47000 790 | 25 791 | 0 360 arc 792 | fill 793 | newpath 794 | 39800 47000 795 | 25 796 | 0 360 arc 797 | fill 798 | showpage 799 | %%End 800 | -------------------------------------------------------------------------------- /schematics/power.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | C 33800 48800 1 0 0 switch-spst-1.sym 3 | { 4 | T 34200 49500 5 10 0 0 0 0 1 5 | device=SPST 6 | T 34100 49100 5 10 1 1 0 0 1 7 | refdes=PWR 8 | } 9 | C 33600 49600 1 0 0 5V-plus-1.sym 10 | N 34600 48800 35700 48800 4 11 | N 33800 47000 35700 47000 4 12 | C 33600 46700 1 0 0 ground.sym 13 | T 35800 48700 9 10 1 0 0 0 1 14 | 5V 15 | T 35800 46900 9 10 1 0 0 0 1 16 | GND 17 | C 38000 48800 1 0 0 switch-spst-1.sym 18 | { 19 | T 38400 49500 5 10 0 0 180 8 1 20 | device=SPST 21 | T 38300 49100 5 10 1 1 180 8 1 22 | refdes=PWR 23 | } 24 | C 37800 49600 1 0 0 5V-plus-1.sym 25 | N 38000 49600 39400 49600 4 26 | N 39400 48600 40000 48600 4 27 | N 38000 47000 40000 47000 4 28 | C 37800 46700 1 0 0 ground.sym 29 | T 40100 48500 9 10 1 0 0 0 1 30 | 5V 31 | T 40100 46900 9 10 1 0 0 0 1 32 | GND 33 | C 38800 49600 1 180 1 pnp-3.sym 34 | { 35 | T 39700 49100 5 10 0 0 180 6 1 36 | device=PNP_TRANSISTOR 37 | T 39700 49100 5 10 0 1 180 6 1 38 | refdes=Q? 39 | } 40 | N 38800 48800 38800 49100 4 41 | C 38100 47000 1 90 0 resistor-1.sym 42 | { 43 | T 37700 47300 5 10 0 0 90 0 1 44 | device=RESISTOR 45 | T 37800 47200 5 10 0 1 90 0 1 46 | refdes=R? 47 | } 48 | C 37800 48800 1 270 0 led-1.sym 49 | { 50 | T 38400 48000 5 10 0 0 270 0 1 51 | device=LED 52 | T 38200 48000 5 10 0 1 270 0 1 53 | refdes=LED? 54 | T 38600 48000 5 10 0 0 270 0 1 55 | symversion=0.1 56 | } 57 | C 34800 47000 1 90 0 resistor-1.sym 58 | { 59 | T 34400 47300 5 10 0 0 90 0 1 60 | device=RESISTOR 61 | T 34500 47200 5 10 0 1 90 0 1 62 | refdes=R? 63 | } 64 | C 34500 48800 1 270 0 led-1.sym 65 | { 66 | T 35100 48000 5 10 0 0 270 0 1 67 | device=LED 68 | T 34900 48000 5 10 0 1 270 0 1 69 | refdes=LED? 70 | T 35300 48000 5 10 0 0 270 0 1 71 | symversion=0.1 72 | } 73 | N 33800 49600 33800 48800 4 74 | C 35700 47500 1 90 0 capacitor-1.sym 75 | { 76 | T 35000 47700 5 10 0 0 90 0 1 77 | device=CAPACITOR 78 | T 35200 47700 5 10 0 1 90 0 1 79 | refdes=C? 80 | T 34800 47700 5 10 0 0 90 0 1 81 | symversion=0.1 82 | } 83 | N 35500 48400 35500 48800 4 84 | N 35500 47500 35500 47000 4 85 | C 40000 47400 1 90 0 capacitor-1.sym 86 | { 87 | T 39300 47600 5 10 0 0 90 0 1 88 | device=CAPACITOR 89 | T 39500 47600 5 10 0 1 90 0 1 90 | refdes=C? 91 | T 39100 47600 5 10 0 0 90 0 1 92 | symversion=0.1 93 | } 94 | N 39800 48300 39800 48600 4 95 | N 39800 47400 39800 47000 4 96 | -------------------------------------------------------------------------------- /schematics/program_counter.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/program_counter.pdf -------------------------------------------------------------------------------- /schematics/program_counter.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | C 63800 52100 1 90 0 74161-1.sym 3 | { 4 | T 59660 52400 5 10 0 0 90 0 1 5 | device=74161 6 | T 59860 52400 5 10 0 0 90 0 1 7 | footprint=DIP16 8 | T 60000 53800 5 10 1 1 90 6 1 9 | refdes=PC0 10 | } 11 | C 59700 52100 1 90 0 74161-1.sym 12 | { 13 | T 55560 52400 5 10 0 0 90 0 1 14 | device=74161 15 | T 55760 52400 5 10 0 0 90 0 1 16 | footprint=DIP16 17 | T 55900 53800 5 10 1 1 90 6 1 18 | refdes=PC1 19 | } 20 | C 67700 52100 1 90 0 74245-1.sym 21 | { 22 | T 64350 52400 5 10 0 0 90 0 1 23 | device=74245 24 | T 64500 53800 5 10 1 1 90 6 1 25 | refdes=BUF 26 | T 64150 52400 5 10 0 0 90 0 1 27 | footprint=DIP20 28 | } 29 | N 64900 52100 64900 51500 4 30 | N 57500 51500 68200 51500 4 31 | N 65200 52100 65200 51300 4 32 | N 57100 51300 68200 51300 4 33 | N 65500 52100 65500 51100 4 34 | N 56700 51100 68200 51100 4 35 | N 65800 52100 65800 50900 4 36 | N 56300 50900 68200 50900 4 37 | N 66100 52100 66100 50700 4 38 | N 61600 50700 68200 50700 4 39 | N 66400 52100 66400 50500 4 40 | N 61200 50500 68200 50500 4 41 | N 66700 52100 66700 50300 4 42 | N 60800 50300 68200 50300 4 43 | N 67000 52100 67000 50100 4 44 | N 60400 50100 68200 50100 4 45 | N 67300 52100 67300 51900 4 46 | N 67300 51900 68100 51900 4 47 | N 68100 51900 68100 55500 4 48 | N 62400 52000 64300 52000 4 49 | N 67600 50000 67600 52100 4 50 | N 57500 51500 57500 52100 4 51 | N 57100 51300 57100 52100 4 52 | N 56700 51100 56700 52100 4 53 | N 56300 50900 56300 52100 4 54 | N 58700 51900 63900 51900 4 55 | N 62800 52100 62800 51900 4 56 | N 57900 51700 64100 51700 4 57 | N 57900 52100 57900 51700 4 58 | N 62000 52100 62000 51700 4 59 | N 60400 52100 60400 50100 4 60 | N 60800 52100 60800 50300 4 61 | N 61200 52100 61200 50500 4 62 | N 61600 52100 61600 50700 4 63 | N 59100 52100 59100 51800 4 64 | N 59100 51800 64000 51800 4 65 | N 63200 52100 63200 51800 4 66 | N 64000 51800 64000 55300 4 67 | N 64100 51700 64100 55200 4 68 | N 62000 54100 62000 54200 4 69 | N 59800 54200 62000 54200 4 70 | N 59800 54200 59800 52000 4 71 | N 59800 52000 58300 52000 4 72 | N 58300 52000 58300 52100 4 73 | N 58700 51900 58700 52100 4 74 | N 59500 52100 59500 51600 4 75 | N 59500 51600 64200 51600 4 76 | N 63600 52100 63600 51600 4 77 | N 64200 55100 64200 51600 4 78 | N 67000 54100 67000 54300 4 79 | N 67000 54300 60400 54300 4 80 | N 60400 54100 60400 55100 4 81 | N 66700 54100 66700 54400 4 82 | N 60100 54400 66700 54400 4 83 | N 60800 54400 60800 54100 4 84 | N 66400 54100 66400 54500 4 85 | N 59800 54500 66400 54500 4 86 | N 61200 54500 61200 54100 4 87 | N 66100 54100 66100 54600 4 88 | N 59500 54600 66100 54600 4 89 | N 61600 54600 61600 54100 4 90 | N 65800 54100 65800 54700 4 91 | N 65800 54700 56300 54700 4 92 | N 56300 54700 56300 54100 4 93 | N 65500 54100 65500 54800 4 94 | N 65500 54800 56700 54800 4 95 | N 56700 54800 56700 54100 4 96 | N 65200 54100 65200 54900 4 97 | N 65200 54900 57100 54900 4 98 | N 57100 54900 57100 54100 4 99 | N 64900 54100 64900 55000 4 100 | N 64900 55000 57500 55000 4 101 | N 57500 55000 57500 54100 4 102 | N 64200 55100 67700 55100 4 103 | N 64100 55200 67300 55200 4 104 | N 67300 55200 67300 55500 4 105 | N 67700 55100 67700 55500 4 106 | N 64000 55300 66900 55300 4 107 | N 66900 55300 66900 55500 4 108 | T 66700 55600 9 10 1 0 0 0 1 109 | CLK 110 | T 66200 55600 9 10 1 0 0 0 1 111 | \_PCW\_ 112 | T 68000 55600 9 10 1 0 0 0 1 113 | \_PCE\_ 114 | T 67100 55600 9 10 1 0 0 0 1 115 | PCC 116 | C 58500 55100 1 90 0 led-1.sym 117 | { 118 | T 57900 55900 5 10 0 0 90 0 1 119 | device=LED 120 | T 58100 55900 5 10 0 1 90 0 1 121 | refdes=LED? 122 | T 57700 55900 5 10 0 0 90 0 1 123 | symversion=0.1 124 | } 125 | C 58800 55100 1 90 0 led-1.sym 126 | { 127 | T 58200 55900 5 10 0 0 90 0 1 128 | device=LED 129 | T 58400 55900 5 10 0 1 90 0 1 130 | refdes=LED? 131 | T 58000 55900 5 10 0 0 90 0 1 132 | symversion=0.1 133 | } 134 | C 59100 55100 1 90 0 led-1.sym 135 | { 136 | T 58500 55900 5 10 0 0 90 0 1 137 | device=LED 138 | T 58700 55900 5 10 0 1 90 0 1 139 | refdes=LED? 140 | T 58300 55900 5 10 0 0 90 0 1 141 | symversion=0.1 142 | } 143 | C 59400 55100 1 90 0 led-1.sym 144 | { 145 | T 58800 55900 5 10 0 0 90 0 1 146 | device=LED 147 | T 59000 55900 5 10 0 1 90 0 1 148 | refdes=LED? 149 | T 58600 55900 5 10 0 0 90 0 1 150 | symversion=0.1 151 | } 152 | C 59700 55100 1 90 0 led-1.sym 153 | { 154 | T 59100 55900 5 10 0 0 90 0 1 155 | device=LED 156 | T 59300 55900 5 10 0 1 90 0 1 157 | refdes=LED? 158 | T 58900 55900 5 10 0 0 90 0 1 159 | symversion=0.1 160 | } 161 | C 60000 55100 1 90 0 led-1.sym 162 | { 163 | T 59400 55900 5 10 0 0 90 0 1 164 | device=LED 165 | T 59600 55900 5 10 0 1 90 0 1 166 | refdes=LED? 167 | T 59200 55900 5 10 0 0 90 0 1 168 | symversion=0.1 169 | } 170 | C 60300 55100 1 90 0 led-1.sym 171 | { 172 | T 59700 55900 5 10 0 0 90 0 1 173 | device=LED 174 | T 59900 55900 5 10 0 1 90 0 1 175 | refdes=LED? 176 | T 59500 55900 5 10 0 0 90 0 1 177 | symversion=0.1 178 | } 179 | C 60600 55100 1 90 0 led-1.sym 180 | { 181 | T 60000 55900 5 10 0 0 90 0 1 182 | device=LED 183 | T 60200 55900 5 10 0 1 90 0 1 184 | refdes=LED? 185 | T 59800 55900 5 10 0 0 90 0 1 186 | symversion=0.1 187 | } 188 | N 58300 55100 58300 55000 4 189 | N 58600 55100 58600 54900 4 190 | N 58900 55100 58900 54800 4 191 | N 59200 55100 59200 54700 4 192 | N 59500 55100 59500 54600 4 193 | N 59800 55100 59800 54500 4 194 | N 60100 55100 60100 54400 4 195 | N 55500 56000 60400 56000 4 196 | C 55600 50900 1 90 0 resistor-1.sym 197 | { 198 | T 55200 51200 5 10 0 0 90 0 1 199 | device=RESISTOR 200 | T 55300 51100 5 10 0 1 90 0 1 201 | refdes=R? 202 | } 203 | C 55300 49700 1 0 0 ground.sym 204 | T 68400 51400 9 10 1 0 0 0 1 205 | D7 206 | T 68400 51200 9 10 1 0 0 0 1 207 | D6 208 | T 68400 51000 9 10 1 0 0 0 1 209 | D5 210 | T 68400 50800 9 10 1 0 0 0 1 211 | D4 212 | T 68400 50600 9 10 1 0 0 0 1 213 | D3 214 | T 68400 50400 9 10 1 0 0 0 1 215 | D2 216 | T 68400 50200 9 10 1 0 0 0 1 217 | D1 218 | T 68400 50000 9 10 1 0 0 0 1 219 | D0 220 | N 63900 55400 63900 51900 4 221 | N 63900 55400 66500 55400 4 222 | N 66500 55500 66500 55400 4 223 | T 67500 55600 9 10 1 0 0 0 1 224 | \_RST\_ 225 | N 62400 52100 62400 52000 4 226 | N 55500 51800 55500 56000 4 227 | N 67600 50000 55500 50000 4 228 | N 55500 50000 55500 50900 4 229 | N 64300 55700 64300 52000 4 230 | C 64100 55700 1 0 0 5V-plus-1.sym 231 | -------------------------------------------------------------------------------- /schematics/register.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbates/jcpu/7f3888ed8b778cc7da2618b9ca8d00124613cd54/schematics/register.pdf -------------------------------------------------------------------------------- /schematics/register.sch: -------------------------------------------------------------------------------- 1 | v 20130925 2 2 | C 38800 43800 1 90 0 74245-1.sym 3 | { 4 | T 35450 44100 5 10 0 0 90 0 1 5 | device=74245 6 | T 35600 45500 5 10 1 1 90 6 1 7 | refdes=BUF 8 | T 35250 44100 5 10 0 0 90 0 1 9 | footprint=DIP20 10 | } 11 | C 35100 43800 1 90 0 74377-1.sym 12 | { 13 | T 31650 44100 5 10 0 0 90 0 1 14 | device=74377 15 | T 31800 45500 5 10 1 1 90 6 1 16 | refdes=REG 17 | T 31450 44100 5 10 0 0 90 0 1 18 | footprint=DIP20 19 | } 20 | N 38100 45800 38100 45900 4 21 | N 37800 45800 37800 46000 4 22 | N 37500 45800 37500 46100 4 23 | N 37200 45800 37200 46200 4 24 | N 36900 45800 36900 46300 4 25 | N 36600 45800 36600 46400 4 26 | N 36300 45800 36300 46500 4 27 | N 36000 45800 36000 46600 4 28 | N 36000 43800 36000 43600 4 29 | N 32200 43600 39200 43600 4 30 | N 36300 43800 36300 43400 4 31 | N 32500 43400 39200 43400 4 32 | N 36600 43800 36600 43200 4 33 | N 32800 43200 39200 43200 4 34 | N 36900 43800 36900 43000 4 35 | N 33100 43000 39200 43000 4 36 | N 37200 43800 37200 42800 4 37 | N 33400 42800 39200 42800 4 38 | N 37500 43800 37500 42600 4 39 | N 33700 42600 39200 42600 4 40 | N 37800 43800 37800 42400 4 41 | N 34000 42400 39200 42400 4 42 | N 38100 43800 38100 42200 4 43 | N 34300 42200 39200 42200 4 44 | N 34300 45800 34300 46700 4 45 | N 34300 45900 38100 45900 4 46 | N 34000 45800 34000 46700 4 47 | N 34000 46000 37800 46000 4 48 | N 33700 45800 33700 46700 4 49 | N 33700 46100 37500 46100 4 50 | N 33400 45800 33400 46700 4 51 | N 33400 46200 37200 46200 4 52 | N 33100 45800 33100 46700 4 53 | N 33100 46300 36900 46300 4 54 | N 32800 45800 32800 46700 4 55 | N 32800 46400 36600 46400 4 56 | N 32500 45800 32500 46700 4 57 | N 32500 46500 36300 46500 4 58 | N 32200 45800 32200 46700 4 59 | N 32200 46600 36000 46600 4 60 | N 32200 43800 32200 43600 4 61 | N 32500 43800 32500 43400 4 62 | N 32800 43800 32800 43200 4 63 | N 33100 43800 33100 43000 4 64 | N 33400 43800 33400 42800 4 65 | N 33700 43800 33700 42600 4 66 | N 34000 43800 34000 42400 4 67 | N 34300 43800 34300 42200 4 68 | N 34900 43800 35200 43800 4 69 | N 35200 43800 35200 46900 4 70 | N 35200 46900 38200 46900 4 71 | N 38200 46900 38200 47200 4 72 | N 34600 43800 34600 43700 4 73 | N 34600 43700 35400 43700 4 74 | N 35400 43700 35400 46800 4 75 | N 35400 46800 38600 46800 4 76 | N 38600 46800 38600 47200 4 77 | N 38400 43800 38400 43700 4 78 | N 38400 43700 39000 43700 4 79 | N 39000 43700 39000 47200 4 80 | T 39300 43500 9 10 1 0 0 0 1 81 | D7 82 | T 39300 43300 9 10 1 0 0 0 1 83 | D6 84 | T 39300 43100 9 10 1 0 0 0 1 85 | D5 86 | T 39300 42900 9 10 1 0 0 0 1 87 | D4 88 | T 39300 42700 9 10 1 0 0 0 1 89 | D3 90 | T 39300 42500 9 10 1 0 0 0 1 91 | D2 92 | T 39300 42300 9 10 1 0 0 0 1 93 | D1 94 | T 39300 42100 9 10 1 0 0 0 1 95 | D0 96 | C 34500 46700 1 90 0 led-1.sym 97 | { 98 | T 33900 47500 5 10 0 0 90 0 1 99 | device=LED 100 | T 34100 47500 5 10 0 1 90 0 1 101 | refdes=LED? 102 | T 33700 47500 5 10 0 0 90 0 1 103 | symversion=0.1 104 | } 105 | C 34200 46700 1 90 0 led-1.sym 106 | { 107 | T 33600 47500 5 10 0 0 90 0 1 108 | device=LED 109 | T 33800 47500 5 10 0 1 90 0 1 110 | refdes=LED? 111 | T 33400 47500 5 10 0 0 90 0 1 112 | symversion=0.1 113 | } 114 | C 33900 46700 1 90 0 led-1.sym 115 | { 116 | T 33300 47500 5 10 0 0 90 0 1 117 | device=LED 118 | T 33500 47500 5 10 0 1 90 0 1 119 | refdes=LED? 120 | T 33100 47500 5 10 0 0 90 0 1 121 | symversion=0.1 122 | } 123 | C 33600 46700 1 90 0 led-1.sym 124 | { 125 | T 33000 47500 5 10 0 0 90 0 1 126 | device=LED 127 | T 33200 47500 5 10 0 1 90 0 1 128 | refdes=LED? 129 | T 32800 47500 5 10 0 0 90 0 1 130 | symversion=0.1 131 | } 132 | C 33300 46700 1 90 0 led-1.sym 133 | { 134 | T 32700 47500 5 10 0 0 90 0 1 135 | device=LED 136 | T 32900 47500 5 10 0 1 90 0 1 137 | refdes=LED? 138 | T 32500 47500 5 10 0 0 90 0 1 139 | symversion=0.1 140 | } 141 | C 33000 46700 1 90 0 led-1.sym 142 | { 143 | T 32400 47500 5 10 0 0 90 0 1 144 | device=LED 145 | T 32600 47500 5 10 0 1 90 0 1 146 | refdes=LED? 147 | T 32200 47500 5 10 0 0 90 0 1 148 | symversion=0.1 149 | } 150 | C 32700 46700 1 90 0 led-1.sym 151 | { 152 | T 32100 47500 5 10 0 0 90 0 1 153 | device=LED 154 | T 32300 47500 5 10 0 1 90 0 1 155 | refdes=LED? 156 | T 31900 47500 5 10 0 0 90 0 1 157 | symversion=0.1 158 | } 159 | C 32400 46700 1 90 0 led-1.sym 160 | { 161 | T 31800 47500 5 10 0 0 90 0 1 162 | device=LED 163 | T 32000 47500 5 10 0 1 90 0 1 164 | refdes=LED? 165 | T 31600 47500 5 10 0 0 90 0 1 166 | symversion=0.1 167 | } 168 | T 38900 47300 9 10 1 0 0 0 1 169 | \_RxE\_ 170 | T 38400 47300 9 10 1 0 0 0 1 171 | \_RxW\_ 172 | T 38000 47300 9 10 1 0 0 0 1 173 | CLK 174 | C 31300 45200 1 90 0 resistor-1.sym 175 | { 176 | T 30900 45500 5 10 0 0 90 0 1 177 | device=RESISTOR 178 | T 31000 45400 5 10 0 1 90 0 1 179 | refdes=R? 180 | } 181 | N 31200 47600 34300 47600 4 182 | N 38700 43800 38700 41800 4 183 | C 38600 41500 1 0 0 gnd-1.sym 184 | N 31200 46100 31200 47600 4 185 | N 31200 45200 31200 41800 4 186 | N 31200 41800 38700 41800 4 187 | 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