├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── cdp1802.v ├── go ├── ram.v ├── sim_main.cpp ├── software ├── CF1802.hex ├── anstests0.10 │ ├── alltest.fr │ ├── core.fr │ ├── coreexttest.fth │ ├── coreplustest.fth │ ├── doubletest.fth │ ├── exceptiontest.fth │ ├── filetest.fth │ ├── memorytest.fth │ ├── runtests.fth │ ├── searchordertest.fth │ ├── stringtest.fth │ ├── tester.fr │ └── toolstest.fth ├── blink.hex ├── intel2hex.py └── intelhex.py └── testbench.v /.gitignore: -------------------------------------------------------------------------------- 1 | *.pyc 2 | unused 3 | obj_dir 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesbowman/verilog1802/HEAD/LICENSE -------------------------------------------------------------------------------- /Makefile: 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