├── .gitignore ├── 3x3Sad.jpg ├── BlockDiagram2.jpg ├── README └── source ├── AbsoluteDifference.v ├── Accumulator.v ├── AddSubtract.v ├── Adder.v ├── AdderTree.v ├── DelayReg.v ├── FPGALink.v ├── Main.v ├── Pipeline.v ├── Subtractor.v ├── buffer_to_pipeline.v ├── camera_interface.v ├── comm_fpga.v ├── comparator.v ├── compare_ws.v ├── decoder.v ├── disparity_counter.v ├── fifo_buffer.v ├── image_buffer.v ├── left_counter.v ├── line_buffer.v ├── line_buffers.v ├── mux_6_to_1.v ├── output_decoder.v ├── ram_counters.v └── right_counter.v /.gitignore: -------------------------------------------------------------------------------- 1 | source/clock_creator.v 2 | source/disparity_fifo.v 3 | source/fifo.v 4 | -------------------------------------------------------------------------------- /3x3Sad.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesrivas/FPGA_Stereo_Depth_Map/ece08e4acc85b84d7126dee646470c2b6a7d87a7/3x3Sad.jpg -------------------------------------------------------------------------------- /BlockDiagram2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jamesrivas/FPGA_Stereo_Depth_Map/ece08e4acc85b84d7126dee646470c2b6a7d87a7/BlockDiagram2.jpg -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | The purpose of this project was to create and display a real time "depth map" from a pair of stereo video cameras. The information contained in the depth map would give a system depth perception ability, which has various practical applications such as robot navigation and automobile collision avoidance. 2 | 3 | Video was captured at 30fps at a resolution of 640x480 from a stereo camera system. This information was transmitted to an FPGA development board, which attempted to find the relative depth of each pixel in the image. Once the depth of all of the pixels for a particular frame were calculated, the resulting "depth map" was transmitted to a PC via USB interface to be displayed. 4 | 5 | The way to calculate depth from a set of stereo images is simple. First a pixel from one of the stereo images must be matched to the corresponding pixel from the other image. Assuming that the cameras are mounted parallel to each other, the only difference between these pixels should be some horizontal translation. The amount of horizontal translation depends on the distance the pixel is from the cameras. A pixel that is close to the cameras will have a large horizontal translation, while a pixel that is far from the cameras will have a small horizontal translation. By calculating the horizontal translation for each pixel in the image, a color coded depth map can be created that will show how far each pixel is away from the camera. 6 | 7 | Code organization: 8 | camera interface -> pixel data buffers -> processing pipelines -> pipeline output aggregator -> output buffer -> USB interface 9 | 10 | Camera Interface: 11 | The purpose of the camera interface is to find the start of each from and each line, and to capture the pixel data. The camera interface also has to seperate the left and right images for each frame, because they are transmitted from the camera as one combined image. 12 | 13 | Pixel Data Buffers: 14 | The purpose of the pixel data buffers is to store enough lines of pixel data to populate the pipeline. There are five buffers created. One buffer that holds left image data shared by all 4 of the pipelines, and one buffer per pipeline that holds right image data. Each buffer holds 6 lines of data. 15 | 16 | Processing Pipelines: 17 | The purpose of the processing pipelines is to compare pixels from the left image to pixels from the right image, in order to find the matching pixel. In order to improve matching accuracy, a group of 5x5 pixels is compared between images, instead of a single pixel. The pipeline outputs a value which represents how well matched each set of 5x5 pixels is. 18 | 19 | Pipeline Output Aggregator: 20 | The purpose of the pipeline output aggregator is to compare the matching values for the sets of 5x5 pixels, and to output the best matching pair and the horizontal translation between them. 21 | 22 | Output Buffer: 23 | The output buffer stores the horizontal translation data for each of the 640x480 pixels in the image so that they can be transmitted to the PC for display. 24 | 25 | USB Interface: 26 | The USB interface controls the flow of data to and from the PC. 27 | -------------------------------------------------------------------------------- /source/AbsoluteDifference.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:14:05 02/01/2012 7 | // Design Name: 8 | // Module Name: AbsoluteDifference 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module AbsoluteDifference( 22 | input wire [num_bits*window_size-1:0] in1, 23 | input wire [num_bits*window_size-1:0] in2, 24 | input wire clock, 25 | input wire reset_n, 26 | 27 | output wire [num_bits*window_size-1:0] out 28 | ); 29 | 30 | parameter window_size=5; 31 | parameter num_bits=8; 32 | 33 | genvar i; 34 | 35 | generate 36 | for (i=0; i. 16 | // 17 | module FPGALink( 18 | // FX2 interface 19 | input wire fx2Clk_in, // 48MHz clock from FX2 20 | output wire[1:0] fx2Addr_out, // select FIFO: "10" for EP6OUT, "11" for EP8IN 21 | inout wire[7:0] fx2Data_io, // 8-bit data to/from FX2 22 | output wire fx2Read_out, // asserted (active-low) when reading from FX2 23 | output wire fx2OE_out, // asserted (active-low) to tell FX2 to drive bus 24 | input wire fx2GotData_in, // asserted (active-high) when FX2 has data for us 25 | output wire fx2Write_out, // asserted (active-low) when writing to FX2 26 | input wire fx2GotRoom_in, // asserted (active-high) when FX2 has room for more data from us 27 | output wire fx2PktEnd_out, // asserted (active-low) when a host read needs to be committed early 28 | 29 | // Input data 30 | input wire data_clock, 31 | input wire data_valid, 32 | input wire [7:0] data_in 33 | ); 34 | 35 | //Fifo Connections 36 | wire [7:0] FifoOut; 37 | wire FifoRead; 38 | wire FifoEmpty; 39 | wire [6:0] chanAddr; 40 | 41 | 42 | // CommFPGA module 43 | // Needed so that the comm_fpga module can drive both fx2Read_out and fx2OE_out 44 | wire fx2Read; 45 | assign fx2Read_out = fx2Read; 46 | assign fx2OE_out = fx2Read; 47 | assign fx2Addr_out[1] = 1'b1; // Use EP6OUT/EP8IN, not EP2OUT/EP4IN. 48 | comm_fpga comm_fpga( 49 | // FX2 interface 50 | .fx2Clk_in (fx2Clk_in), 51 | .fx2FifoSel_out (fx2Addr_out[0]), 52 | .fx2Data_io (fx2Data_io), 53 | .fx2Read_out (fx2Read), 54 | .fx2GotData_in (fx2GotData_in), 55 | .fx2Write_out (fx2Write_out), 56 | .fx2GotRoom_in (fx2GotRoom_in), 57 | .fx2PktEnd_out (fx2PktEnd_out), 58 | 59 | // Channel read/write interface 60 | .chanAddr_out (chanAddr), 61 | .chanData_in (FifoOut), 62 | .chanRead_out (FifoRead), 63 | .chanGotData_in (~FifoEmpty), 64 | .chanData_out (), 65 | .chanWrite_out (), 66 | .chanGotRoom_in (1'b0) 67 | ); 68 | 69 | 70 | // Data is read by computer 71 | //synthesis attribute box_type fifo "black_box" 72 | fifo read_fifo( 73 | .wr_clk (data_clock), 74 | .rd_clk (fx2Clk_in), 75 | .din (data_in), 76 | .wr_en (data_valid), 77 | .rd_en (FifoRead & (chanAddr == 7'b0000000)), 78 | .dout (FifoOut), 79 | .full (), 80 | .empty (FifoEmpty) 81 | ); 82 | 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /source/Main.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:29:29 04/24/2012 7 | // Design Name: 8 | // Module Name: toplevel 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Main( 22 | input wire clock_100, 23 | input wire pixel_clock, 24 | input wire frame_valid, 25 | input wire line_valid, 26 | input wire [7:0] pixel_data, 27 | 28 | // FX2 interface 29 | input wire fx2Clk_in, // 48MHz clock from FX2 30 | output wire[1:0] fx2Addr_out, // select FIFO: "10" for EP6OUT, "11" for EP8IN 31 | inout wire[7:0] fx2Data_io, // 8-bit data to/from FX2 32 | output wire fx2Read_out, // asserted (active-low) when reading from FX2 33 | output wire fx2OE_out, // asserted (active-low) to tell FX2 to drive bus 34 | input wire fx2GotData_in, // asserted (active-high) when FX2 has data for us 35 | output wire fx2Write_out, // asserted (active-low) when writing to FX2 36 | input wire fx2GotRoom_in, // asserted (active-high) when FX2 has room for more data from us 37 | output wire fx2PktEnd_out // asserted (active-low) when a host read needs to be committed early 38 | 39 | ); 40 | 41 | //200MHz clock to run stereo pipeline 42 | wire clock_200; 43 | 44 | //Signals for camera_interface 45 | wire reset_n; 46 | wire read_start; 47 | wire left_enable; 48 | wire right_enable; 49 | wire [9:0] address_in; 50 | wire [7:0] data_in; 51 | wire [2:0] select; 52 | 53 | //Input to the stereo pipeline 54 | wire [39:0] column_left; 55 | wire [39:0] column_right_1; 56 | wire [39:0] column_right_2; 57 | wire [39:0] column_right_3; 58 | wire [39:0] column_right_4; 59 | 60 | //Outputs from the pipeline 61 | wire [13:0] ws1; 62 | wire [13:0] ws2; 63 | wire [13:0] ws3; 64 | wire [13:0] ws4; 65 | 66 | //Disparity values that correspond to the pipeline outputs 67 | wire [5:0] disparity_1; 68 | wire [5:0] disparity_2; 69 | wire [5:0] disparity_3; 70 | wire [5:0] disparity_4; 71 | 72 | //Final disparity and window sume values 73 | wire [5:0] disparity; 74 | wire [13:0] window_sum; 75 | 76 | //Signals for the output FIFO 77 | wire valid; 78 | wire [19:0] data_out; 79 | wire clear_buffer; 80 | wire valid_out; 81 | 82 | 83 | 84 | clock_creator clks ( 85 | .CLK_IN1 (clock_100), 86 | .CLK_OUT1 (clock_200) 87 | ); 88 | 89 | camera_interface cam ( 90 | //Inputs 91 | .pixel_clock (pixel_clock), 92 | .frame_valid (frame_valid), 93 | .line_valid (line_valid), 94 | .pixel_data (pixel_data), 95 | //Outputs 96 | .reset_n (reset_n), 97 | .read_start (read_start), 98 | .pixels_ps (address_in), 99 | .left_valid (right_enable), //INTENTIONALLY SWITCHED 100 | .right_valid (left_enable), //LEFT=RIGHT and RIGHT=LEFT 101 | .select_ps (select), 102 | .data (data_in) 103 | ); 104 | 105 | buffer_to_pipeline uut ( 106 | //Inputs 107 | .clock_slow (pixel_clock), 108 | .clock_fast (clock_200), 109 | .reset_n (reset_n), 110 | .read_start (read_start), 111 | .left_enable (left_enable), 112 | .right_enable (right_enable), 113 | .address_in (address_in), 114 | .data_in (data_in), 115 | .select (select), 116 | //Outputs 117 | .out_left (column_left), 118 | .out_right_1 (column_right_1), 119 | .out_right_2 (column_right_2), 120 | .out_right_3 (column_right_3), 121 | .out_right_4 (column_right_4) 122 | ); 123 | 124 | Pipeline pipe1 ( 125 | //Inputs 126 | .clock (clock_200), 127 | .reset_n (reset_n), 128 | .in_left (column_left), 129 | .in_right (column_right_1), 130 | //Outputs 131 | .window_sum (ws1) 132 | ); 133 | Pipeline pipe2 ( 134 | //Inputs 135 | .clock (clock_200), 136 | .reset_n (reset_n), 137 | .in_left (column_left), 138 | .in_right (column_right_2), 139 | //Outputs 140 | .window_sum (ws2) 141 | ); 142 | Pipeline pipe3 ( 143 | //Inputs 144 | .clock (clock_200), 145 | .reset_n (reset_n), 146 | .in_left (column_left), 147 | .in_right (column_right_3), 148 | //Outputs 149 | .window_sum (ws3) 150 | ); 151 | Pipeline pipe4 ( 152 | //Inputs 153 | .clock (clock_200), 154 | .reset_n (reset_n), 155 | .in_left (column_left), 156 | .in_right (column_right_4), 157 | //Outputs 158 | .window_sum (ws4) 159 | ); 160 | 161 | compare_ws compare ( 162 | //Inputs 163 | .clock (clock_200), 164 | .reset_n (reset_n), 165 | .ws1 (ws1), 166 | .ws2 (ws2), 167 | .ws3 (ws3), 168 | .ws4 (ws4), 169 | .disp_1 (disparity_1), 170 | .disp_2 (disparity_2), 171 | .disp_3 (disparity_3), 172 | .disp_4 (disparity_4), 173 | //Outputs 174 | .disparity (disparity), 175 | .window_sum (window_sum) 176 | ); 177 | 178 | disparity_counter disp ( 179 | //Inputs 180 | .clock (clock_200), 181 | .reset_n (reset_n), 182 | .read_start (read_start), 183 | //Outputs 184 | .valid (valid), 185 | .pixel (), 186 | .disparity_1 (disparity_1), 187 | .disparity_2 (disparity_2), 188 | .disparity_3 (disparity_3), 189 | .disparity_4 (disparity_4), 190 | .clear_buffer (clear_buffer) 191 | ); 192 | 193 | fifo_buffer fifo ( 194 | //Inputs 195 | .clock (clock_200), 196 | .data_in ({disparity, window_sum}), 197 | .valid (valid), 198 | .disparity (disparity_1), 199 | .read (clear_buffer), 200 | //Outputs 201 | .empty (), 202 | .data_out (data_out) 203 | ); 204 | 205 | output_decoder dec ( 206 | //Inputs 207 | .clock (clock_200), 208 | .valid_in (clear_buffer), 209 | .data_in (data_out[19:14]), 210 | //Outputs 211 | .valid_out (valid_out), 212 | .data_out (decoded_output) 213 | ); 214 | 215 | FPGALink usb ( 216 | //FX2 217 | .fx2Clk_in (fx2Clk_in), 218 | .fx2Addr_out (fx2Addr_out), 219 | .fx2Data_io (fx2Data_io), 220 | .fx2Read_out (fx2Read_out), 221 | .fx2OE_out (fx2OE_out), 222 | .fx2GotData_in (fx2GotData_in), 223 | .fx2Write_out (fx2Write_out), 224 | .fx2GotRoom_in (fx2GotRoom_in), 225 | .fx2PktEnd_out (fx2PktEnd_out), 226 | //FIFO 227 | .data_clock (clock_200), 228 | .data_valid (valid_out), 229 | .data_in (decoded_output) 230 | ); 231 | 232 | endmodule 233 | -------------------------------------------------------------------------------- /source/Pipeline.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:48:53 02/29/2012 7 | // Design Name: 8 | // Module Name: Pipeline 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Pipeline( 22 | input wire clock, 23 | input wire reset_n, 24 | input wire [num_bits*window_size-1:0] in_left, 25 | input wire [num_bits*window_size-1:0] in_right, 26 | 27 | output wire [num_bits_out-1:0] window_sum 28 | ); 29 | 30 | //window_size=5 num_bits_out_add=11 num_bits_out=14 31 | 32 | parameter window_size=5; 33 | parameter num_bits=8; 34 | parameter num_bits_out_add=11; 35 | parameter num_bits_out=14; 36 | 37 | wire [num_bits*window_size-1:0] abs_difs; 38 | wire [num_bits_out_add-1:0] sum; 39 | 40 | AbsoluteDifference #(window_size,num_bits) absdif ( 41 | .in1 (in_left), 42 | .in2 (in_right), 43 | .clock (clock), 44 | .reset_n (reset_n), 45 | .out (abs_difs) 46 | ); 47 | 48 | AdderTree #(window_size,num_bits,num_bits_out_add) add ( 49 | .abs_difs (abs_difs), 50 | .clock (clock), 51 | .reset_n (reset_n), 52 | .sum (sum) 53 | ); 54 | 55 | Accumulator #(window_size,num_bits_out_add,num_bits_out) acc ( 56 | .in (sum), 57 | .clock (clock), 58 | .reset_n (reset_n), 59 | .window_sum (window_sum) 60 | ); 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /source/Subtractor.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:17:28 02/01/2012 7 | // Design Name: 8 | // Module Name: Subtractor 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module Subtractor( 22 | input wire clock, 23 | input wire reset_n, 24 | input wire [num_bits-1:0] in1, 25 | input wire [num_bits-1:0] in2, 26 | output reg [num_bits-1:0] out 27 | ); 28 | 29 | initial 30 | begin 31 | out = 0; 32 | end 33 | 34 | parameter num_bits=8; 35 | 36 | always @(posedge clock or negedge reset_n) 37 | begin: abs_diff 38 | if(~reset_n) 39 | out = 0; 40 | else 41 | begin 42 | if (in1>in2) 43 | begin 44 | out=in1-in2; 45 | end 46 | else 47 | begin 48 | out=in2-in1; 49 | end 50 | end 51 | end 52 | 53 | 54 | // reg [num_bits:0] diff; 55 | // wire diff_neg = diff[num_bits]; 56 | // always @(posedge clock) begin 57 | // // compute difference 58 | // diff <= {1'b0,in1} - {1'b0,in2}; 59 | // // take absolute value 60 | // out <= ( diff[num_bits-1:0] ^ {num_bits{diff_neg}} ) + {{(num_bits-1){1'b0}},diff_neg}; 61 | // end 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /source/buffer_to_pipeline.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:44:16 04/19/2012 7 | // Design Name: 8 | // Module Name: buffer_to_pipeline 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module buffer_to_pipeline( 22 | input wire clock_slow, 23 | input wire clock_fast, 24 | input wire reset_n, 25 | input wire read_start, 26 | input wire left_enable, 27 | input wire right_enable, 28 | input wire [9:0] address_in, 29 | input wire [7:0] data_in, 30 | input wire [2:0] select, 31 | 32 | output wire [39:0] out_left, 33 | output wire [39:0] out_right_1, 34 | output wire [39:0] out_right_2, 35 | output wire [39:0] out_right_3, 36 | output wire [39:0] out_right_4 37 | ); 38 | 39 | 40 | //*********************************************************************** 41 | //Address counters 42 | //*********************************************************************** 43 | wire read_enable; 44 | wire [9:0] address_left; 45 | wire [9:0] address_right_1; 46 | wire [9:0] address_right_2; 47 | wire [9:0] address_right_3; 48 | wire [9:0] address_right_4; 49 | 50 | ram_counters count( 51 | //Inputs 52 | .clock (clock_fast), 53 | .reset_n (reset_n), 54 | .read_start (read_start), 55 | //Outputs 56 | .read_enable (read_enable), 57 | .address_left_1 (address_left), 58 | .address_right_1 (address_right_1), 59 | .address_right_2 (address_right_2), 60 | .address_right_3 (address_right_3), 61 | .address_right_4 (address_right_4) 62 | ); 63 | 64 | //********************************************************************** 65 | //Left image line buffers 66 | //********************************************************************** 67 | line_buffers buff_left( 68 | //Inputs 69 | .clock_slow (clock_slow), 70 | .clock_fast (clock_fast), 71 | .write_enable (left_enable), 72 | .address_in (address_in), 73 | .data_in (data_in), 74 | .read_enable (read_enable), 75 | .address_out (address_left), 76 | .select (select), 77 | //Outputs 78 | .data_out_1 (out_left[7:0]), 79 | .data_out_2 (out_left[15:8]), 80 | .data_out_3 (out_left[23:16]), 81 | .data_out_4 (out_left[31:24]), 82 | .data_out_5 (out_left[39:32]) 83 | ); 84 | 85 | //********************************************************************** 86 | //Right image line buffers 87 | //********************************************************************** 88 | line_buffers buff_right_1( 89 | //Inputs 90 | .clock_slow (clock_slow), 91 | .clock_fast (clock_fast), 92 | .write_enable (right_enable), 93 | .address_in (address_in), 94 | .data_in (data_in), 95 | .read_enable (read_enable), 96 | .address_out (address_right_1), 97 | .select (select), 98 | //Outputs 99 | .data_out_1 (out_right_1[7:0]), 100 | .data_out_2 (out_right_1[15:8]), 101 | .data_out_3 (out_right_1[23:16]), 102 | .data_out_4 (out_right_1[31:24]), 103 | .data_out_5 (out_right_1[39:32]) 104 | ); 105 | 106 | line_buffers buff_right_2( 107 | //Inputs 108 | .clock_slow (clock_slow), 109 | .clock_fast (clock_fast), 110 | .write_enable (right_enable), 111 | .address_in (address_in), 112 | .data_in (data_in), 113 | .read_enable (read_enable), 114 | .address_out (address_right_2), 115 | .select (select), 116 | //Outputs 117 | .data_out_1 (out_right_2[7:0]), 118 | .data_out_2 (out_right_2[15:8]), 119 | .data_out_3 (out_right_2[23:16]), 120 | .data_out_4 (out_right_2[31:24]), 121 | .data_out_5 (out_right_2[39:32]) 122 | ); 123 | 124 | line_buffers buff_right_3( 125 | //Inputs 126 | .clock_slow (clock_slow), 127 | .clock_fast (clock_fast), 128 | .write_enable (right_enable), 129 | .address_in (address_in), 130 | .data_in (data_in), 131 | .read_enable (read_enable), 132 | .address_out (address_right_3), 133 | .select (select), 134 | //Outputs 135 | .data_out_1 (out_right_3[7:0]), 136 | .data_out_2 (out_right_3[15:8]), 137 | .data_out_3 (out_right_3[23:16]), 138 | .data_out_4 (out_right_3[31:24]), 139 | .data_out_5 (out_right_3[39:32]) 140 | ); 141 | 142 | line_buffers buff_right_4( 143 | //Inputs 144 | .clock_slow (clock_slow), 145 | .clock_fast (clock_fast), 146 | .write_enable (right_enable), 147 | .address_in (address_in), 148 | .data_in (data_in), 149 | .read_enable (read_enable), 150 | .address_out (address_right_4), 151 | .select (select), 152 | //Outputs 153 | .data_out_1 (out_right_4[7:0]), 154 | .data_out_2 (out_right_4[15:8]), 155 | .data_out_3 (out_right_4[23:16]), 156 | .data_out_4 (out_right_4[31:24]), 157 | .data_out_5 (out_right_4[39:32]) 158 | ); 159 | 160 | endmodule 161 | -------------------------------------------------------------------------------- /source/camera_interface.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 13:30:54 05/10/2012 7 | // Design Name: 8 | // Module Name: camera_interface 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module camera_interface( 22 | input wire pixel_clock, 23 | input wire frame_valid, 24 | input wire line_valid, 25 | input wire [7:0] pixel_data, 26 | 27 | output reg reset_n, 28 | output reg [9:0] pixels_ps, 29 | output reg read_start, 30 | output reg left_valid, 31 | output reg right_valid, 32 | output reg [2:0] select_ps, 33 | output reg [7:0] data 34 | ); 35 | 36 | parameter RESET_1 = 4'b0000; 37 | parameter RESET_2 = 4'b0001; 38 | parameter RESET_3 = 4'b0010; 39 | parameter RESET_4 = 4'b0011; 40 | parameter RESET_5 = 4'b0100; 41 | parameter FIND_FRAME_1 = 4'b0101; 42 | parameter FIND_FRAME_2 = 4'b0110; 43 | parameter FIND_FRAME_3 = 4'b0111; 44 | parameter FIND_LINE_1 = 4'b1000; 45 | parameter FIND_LINE_2 = 4'b1001; 46 | parameter READ_LEFT = 4'b1010; 47 | parameter READ_RIGHT = 4'b1011; 48 | 49 | //State Machine Connections 50 | //_ps = present state 51 | //_ns = next state 52 | reg [3:0] stream_vid_ps; 53 | reg [3:0] stream_vid_ns; 54 | //Counter Connections 55 | reg [9:0] pixels_ns; 56 | reg [8:0] lines_ps; 57 | reg [8:0] lines_ns; 58 | reg pixels_en; 59 | reg lines_en; 60 | //Valid connections 61 | reg left_valid_ns; 62 | reg right_valid_ns; 63 | //Select 64 | reg [2:0] select_delay; 65 | reg [2:0] select_ns; 66 | reg select_en; 67 | reg select_r; 68 | 69 | //Initialize values 70 | initial 71 | begin 72 | stream_vid_ps <= RESET_1; 73 | stream_vid_ns <= RESET_1; 74 | pixels_ps <= 2; 75 | pixels_ns <= 2; 76 | lines_ps <= 0; 77 | lines_ns <= 0; 78 | pixels_en <= 0; 79 | lines_en <= 0; 80 | select_ps <= 0; 81 | select_delay <= 0; 82 | select_ns <= 0; 83 | select_en <= 0; 84 | select_r <= 0; 85 | left_valid <= 0; 86 | right_valid <= 0; 87 | data <= 0; 88 | end 89 | 90 | //********************************************************** 91 | // Main state machine 92 | //********************************************************** 93 | always @(posedge pixel_clock) 94 | begin 95 | stream_vid_ps <= stream_vid_ns; 96 | end 97 | 98 | always @(stream_vid_ps, frame_valid, line_valid, pixels_ps, lines_ps) 99 | begin 100 | 101 | stream_vid_ns <= stream_vid_ps; 102 | pixels_en <= 1'b0; 103 | lines_en <= 1'b0; 104 | select_en <= 1'b0; 105 | select_r <= 1'b0; 106 | read_start <= 1'b0; 107 | reset_n <= 1'b1; 108 | 109 | case (stream_vid_ps) 110 | RESET_1: begin 111 | reset_n <= 1'b0; 112 | stream_vid_ns <= RESET_2; 113 | end 114 | 115 | RESET_2: begin 116 | reset_n <= 1'b0; 117 | stream_vid_ns <= RESET_3; 118 | end 119 | 120 | RESET_3: begin 121 | reset_n <= 1'b0; 122 | stream_vid_ns <= RESET_4; 123 | end 124 | 125 | RESET_4: begin 126 | reset_n <= 1'b0; 127 | stream_vid_ns <= RESET_5; 128 | end 129 | 130 | RESET_5: begin 131 | reset_n <= 1'b0; 132 | stream_vid_ns <= FIND_FRAME_1; 133 | end 134 | 135 | FIND_FRAME_1: begin 136 | if (frame_valid == 0) 137 | stream_vid_ns <= FIND_FRAME_2; 138 | end 139 | 140 | FIND_FRAME_2: begin 141 | if (frame_valid == 0) 142 | stream_vid_ns <= FIND_FRAME_3; 143 | else 144 | stream_vid_ns <= FIND_FRAME_1; 145 | end 146 | 147 | FIND_FRAME_3: begin 148 | if (frame_valid == 1) 149 | stream_vid_ns <= FIND_LINE_1; 150 | end 151 | 152 | FIND_LINE_1: begin 153 | if (line_valid == 0) 154 | begin 155 | stream_vid_ns <= FIND_LINE_2; 156 | end 157 | end 158 | 159 | FIND_LINE_2: begin 160 | if (line_valid == 1) 161 | begin 162 | pixels_en <= 1'b1; 163 | stream_vid_ns <= READ_LEFT; 164 | end 165 | end 166 | 167 | READ_LEFT: begin 168 | if (pixels_ps == 641) 169 | begin 170 | pixels_en <= 1'b1; 171 | stream_vid_ns <= READ_RIGHT; 172 | end 173 | else 174 | begin 175 | pixels_en <= 1'b1; 176 | end 177 | end 178 | 179 | READ_RIGHT: begin 180 | if (pixels_ps == 641 && lines_ps == 479) 181 | begin 182 | read_start <= 1'b1; 183 | pixels_en <= 1'b1; 184 | lines_en <= 1'b1; 185 | select_r <= 1'b1; 186 | stream_vid_ns <= FIND_FRAME_1; 187 | end 188 | else if (pixels_ps == 641 && lines_ps >= 5) 189 | begin 190 | read_start <= 1'b1; 191 | pixels_en <= 1'b1; 192 | lines_en <= 1'b1; 193 | select_en <= 1'b1; 194 | stream_vid_ns <= FIND_LINE_1; 195 | end 196 | else if (pixels_ps == 641) 197 | begin 198 | pixels_en <= 1'b1; 199 | lines_en <= 1'b1; 200 | select_en <= 1'b1; 201 | stream_vid_ns <= FIND_LINE_1; 202 | end 203 | else 204 | begin 205 | pixels_en <= 1'b1; 206 | end 207 | end 208 | endcase 209 | end 210 | 211 | //********************************************************** 212 | // Valid state machines 213 | //********************************************************** 214 | always @(posedge pixel_clock) 215 | begin 216 | data <= {pixel_data[7:5], 5'b0}; //Use only the top 3 bits to "color blob" 217 | left_valid <= left_valid_ns; 218 | right_valid <= right_valid_ns; 219 | end 220 | 221 | always @(stream_vid_ps, line_valid) 222 | begin 223 | if (((stream_vid_ps == FIND_LINE_2) && (line_valid == 1)) || (stream_vid_ps == READ_LEFT)) 224 | left_valid_ns <= 1'b1; 225 | else 226 | left_valid_ns <= 1'b0; 227 | end 228 | 229 | always @(stream_vid_ps) 230 | begin 231 | if (stream_vid_ps == READ_RIGHT) 232 | right_valid_ns <= 1'b1; 233 | else 234 | right_valid_ns <= 1'b0; 235 | end 236 | 237 | //********************************************************** 238 | // Counter state machines 239 | //********************************************************** 240 | always @(posedge pixel_clock) 241 | begin 242 | pixels_ps <= pixels_ns; 243 | end 244 | 245 | always @(pixels_en, pixels_ps) 246 | begin 247 | if (pixels_en) 248 | begin 249 | if (pixels_ps == 641) 250 | pixels_ns <= 2; 251 | else 252 | pixels_ns <= pixels_ps + 1'b1; 253 | end 254 | else 255 | pixels_ns <= pixels_ps; 256 | end 257 | 258 | 259 | always @(posedge pixel_clock) 260 | begin 261 | lines_ps <= lines_ns; 262 | end 263 | 264 | always @(lines_en, lines_ps) 265 | begin 266 | if (lines_en) 267 | begin 268 | if (lines_ps == 479) 269 | lines_ns <= 0; 270 | else 271 | lines_ns <= lines_ps + 1'b1; 272 | end 273 | else 274 | lines_ns <= lines_ps; 275 | end 276 | 277 | 278 | always @(posedge pixel_clock) 279 | begin 280 | select_ps <= select_delay; 281 | select_delay <= select_ns; 282 | end 283 | 284 | always @(select_en, select_ps, select_r) 285 | begin 286 | if (select_en) 287 | begin 288 | if (select_ps == 5) 289 | select_ns <= 0; 290 | else 291 | select_ns <= select_ps + 1'b1; 292 | end 293 | else if (select_r) 294 | select_ns <= 0; 295 | else 296 | select_ns <= select_ps; 297 | end 298 | endmodule 299 | -------------------------------------------------------------------------------- /source/comm_fpga.v: -------------------------------------------------------------------------------- 1 | // 2 | // Copyright (C) 2009-2012 Chris McClelland 3 | // 4 | // This program is free software: you can redistribute it and/or modify 5 | // it under the terms of the GNU Lesser General Public License as published by 6 | // the Free Software Foundation, either version 3 of the License, or 7 | // (at your option) any later version. 8 | // 9 | // This program is distributed in the hope that it will be useful, 10 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | // GNU Lesser General Public License for more details. 13 | // 14 | // You should have received a copy of the GNU Lesser General Public License 15 | // along with this program. If not, see . 16 | // 17 | module 18 | comm_fpga( 19 | // FX2 interface 20 | input wire fx2Clk_in, // 48MHz clock from FX2 21 | output reg fx2FifoSel_out, // select FIFO: '0' for EP6OUT, '1' for EP8IN 22 | inout wire[7:0] fx2Data_io, // 8-bit data to/from FX2 23 | output wire fx2Read_out, // asserted (active-low) when reading from FX2 24 | input wire fx2GotData_in, // asserted (active-high) when FX2 has data for us 25 | output wire fx2Write_out, // asserted (active-low) when writing to FX2 26 | input wire fx2GotRoom_in, // asserted (active-high) when FX2 has room for more data from us 27 | output reg fx2PktEnd_out, // asserted (active-low) when a host read needs to be committed early 28 | 29 | // Channel read/write interface 30 | output wire[6:0] chanAddr_out, // the selected channel (0-127) 31 | input wire[7:0] chanData_in, // data lines used when the host reads from a channel 32 | output reg chanRead_out, // '1' means "on the next clock rising edge, put your next byte of data on chanData_in" 33 | input wire chanGotData_in, // channel logic can drive this low to say "I don't have data ready for you" 34 | output wire[7:0] chanData_out, // data lines used when the host writes to a channel 35 | output reg chanWrite_out, // '1' means "on the next clock rising edge, please accept the data on chanData_out" 36 | input wire chanGotRoom_in // channel logic can drive this low to say "I'm not ready for more data yet" 37 | ); 38 | 39 | // The read/write nomenclature here refers to the FPGA reading and writing the FX2 FIFOs, and is therefore 40 | // of the opposite sense to the host's read and write. So host reads are fulfilled in the S_WRITE state, and 41 | // vice-versa. Apologies for the confusion. 42 | localparam[3:0] S_IDLE = 4'h0; 43 | localparam[3:0] S_GET_COUNT0 = 4'h1; 44 | localparam[3:0] S_GET_COUNT1 = 4'h2; 45 | localparam[3:0] S_GET_COUNT2 = 4'h3; 46 | localparam[3:0] S_GET_COUNT3 = 4'h4; 47 | localparam[3:0] S_BEGIN_WRITE = 4'h5; 48 | localparam[3:0] S_WRITE = 4'h6; 49 | localparam[3:0] S_END_WRITE_ALIGNED = 4'h7; 50 | localparam[3:0] S_END_WRITE_NONALIGNED = 4'h8; 51 | localparam[3:0] S_READ = 4'h9; 52 | localparam[1:0] FIFO_READ = 2'b10; // assert fx2Read_out (active-low) 53 | localparam[1:0] FIFO_WRITE = 2'b01; // assert fx2Write_out (active-low) 54 | localparam[1:0] FIFO_NOP = 2'b11; // assert nothing 55 | localparam OUT_FIFO = 2'b0; // EP6OUT 56 | localparam IN_FIFO = 2'b1; // EP8IN 57 | reg[3:0] state_next, state = S_IDLE; 58 | reg[1:0] fifoOp = FIFO_NOP; 59 | reg[31:0] count_next, count = 32'h0; // read/write count 60 | reg[6:0] addr_next, addr = 7'h00; // channel being accessed (0-127) 61 | reg isWrite_next, isWrite = 1'b0; // is this access is a write or a read? 62 | reg isAligned_next, isAligned = 1'b0; // is this access block-aligned? 63 | reg[7:0] dataOut; // data to be driven on fx2Data_io 64 | reg driveBus; // whether or not to drive fx2Data_io 65 | 66 | // Infer registers 67 | always @(posedge fx2Clk_in) 68 | begin 69 | state <= state_next; 70 | count <= count_next; 71 | addr <= addr_next; 72 | isWrite <= isWrite_next; 73 | isAligned <= isAligned_next; 74 | end 75 | 76 | // Next state logic 77 | always @* 78 | begin 79 | state_next = state; 80 | count_next = count; 81 | addr_next = addr; 82 | isWrite_next = isWrite; // is the FPGA writing to the FX2? 83 | isAligned_next = isAligned; // does this FIFO write end on a block (512-byte) boundary? 84 | dataOut = 8'h00; 85 | driveBus = 1'b0; // don't drive fx2Data_io by default 86 | fifoOp = FIFO_READ; // read the FX2 FIFO by default 87 | fx2PktEnd_out = 1'b1; // inactive: FPGA does not commit a short packet. 88 | chanRead_out = 1'b0; 89 | chanWrite_out = 1'b0; 90 | 91 | case ( state ) 92 | S_GET_COUNT0: 93 | begin 94 | fx2FifoSel_out = OUT_FIFO; // Reading from FX2 95 | if ( fx2GotData_in == 1'b1 ) 96 | begin 97 | // The count high word high byte will be available on the next clock. 98 | count_next[31:24] = fx2Data_io; 99 | state_next = S_GET_COUNT1; 100 | end 101 | end 102 | 103 | S_GET_COUNT1: 104 | begin 105 | fx2FifoSel_out = OUT_FIFO; // Reading from FX2 106 | if ( fx2GotData_in == 1'b1 ) 107 | begin 108 | // The count high word low byte will be available on the next clock. 109 | count_next[23:16] = fx2Data_io; 110 | state_next = S_GET_COUNT2; 111 | end 112 | end 113 | 114 | S_GET_COUNT2: 115 | begin 116 | fx2FifoSel_out = OUT_FIFO; // Reading from FX2 117 | if ( fx2GotData_in == 1'b1 ) 118 | begin 119 | // The count low word high byte will be available on the next clock. 120 | count_next[15:8] = fx2Data_io; 121 | state_next = S_GET_COUNT3; 122 | end 123 | end 124 | 125 | S_GET_COUNT3: 126 | begin 127 | fx2FifoSel_out = OUT_FIFO; // Reading from FX2 128 | if ( fx2GotData_in == 1'b1 ) 129 | begin 130 | // The count low word low byte will be available on the next clock. 131 | count_next[7:0] = fx2Data_io; 132 | if ( isWrite == 1'b1 ) 133 | state_next = S_BEGIN_WRITE; 134 | else 135 | state_next = S_READ; 136 | end 137 | end 138 | 139 | S_BEGIN_WRITE: 140 | begin 141 | fx2FifoSel_out = IN_FIFO; // Writing to FX2 142 | fifoOp = FIFO_NOP; 143 | if ( count[8:0] == 9'b000000000 ) 144 | isAligned_next = 1'b1; 145 | else 146 | isAligned_next = 1'b0; 147 | state_next = S_WRITE; 148 | end 149 | 150 | S_WRITE: 151 | begin 152 | fx2FifoSel_out = IN_FIFO; // Writing to FX2 153 | if ( fx2GotRoom_in == 1'b1 && chanGotData_in == 1'b1 ) 154 | begin 155 | fifoOp = FIFO_WRITE; 156 | dataOut = chanData_in; 157 | driveBus = 1'b1; 158 | chanRead_out = 1'b1; 159 | count_next = count - 1; 160 | if ( count == 32'h1 ) 161 | begin 162 | if ( isAligned == 1'b1 ) 163 | state_next = S_END_WRITE_ALIGNED; // don't assert fx2PktEnd 164 | else 165 | state_next = S_END_WRITE_NONALIGNED; // assert fx2PktEnd to commit small packet 166 | end 167 | end 168 | else 169 | fifoOp = FIFO_NOP; 170 | end 171 | 172 | S_END_WRITE_ALIGNED: 173 | begin 174 | fx2FifoSel_out = IN_FIFO; // Writing to FX2 175 | fifoOp = FIFO_NOP; 176 | state_next = S_IDLE; 177 | end 178 | 179 | S_END_WRITE_NONALIGNED: 180 | begin 181 | fx2FifoSel_out = IN_FIFO; // Writing to FX2 182 | fifoOp = FIFO_NOP; 183 | fx2PktEnd_out = 1'b0; // Active: FPGA commits the packet early. 184 | state_next = S_IDLE; 185 | end 186 | 187 | S_READ: 188 | begin 189 | fx2FifoSel_out = OUT_FIFO; // Reading from FX2 190 | if ( fx2GotData_in == 1'b1 && chanGotRoom_in == 1'b1 ) 191 | begin 192 | // A data byte will be available on the next clock 193 | chanWrite_out = 1'b1; 194 | count_next = count - 1; 195 | if ( count == 32'h1 ) 196 | state_next = S_IDLE; 197 | end 198 | else 199 | fifoOp = FIFO_NOP; 200 | end 201 | 202 | // S_IDLE and others 203 | default: 204 | begin 205 | fx2FifoSel_out = OUT_FIFO; // Reading from FX2 206 | if ( fx2GotData_in == 1'b1 ) 207 | begin 208 | // The read/write flag and a seven-bit channel address will be available on 209 | // the next clock edge. 210 | addr_next = fx2Data_io[6:0]; 211 | isWrite_next = fx2Data_io[7]; 212 | state_next = S_GET_COUNT0; 213 | end 214 | end 215 | endcase 216 | end 217 | 218 | // Drive stateless signals 219 | assign fx2Read_out = fifoOp[0]; 220 | assign fx2Write_out = fifoOp[1]; 221 | assign chanAddr_out = addr; 222 | assign chanData_out = fx2Data_io; 223 | assign fx2Data_io = driveBus ? dataOut : 8'hZZ; 224 | endmodule 225 | -------------------------------------------------------------------------------- /source/comparator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:12:31 04/24/2012 7 | // Design Name: 8 | // Module Name: comparator 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module comparator( 22 | input wire clock, 23 | input wire reset_n, 24 | input wire [13:0] ws1, 25 | input wire [13:0] ws2, 26 | input wire [5:0] disp1, 27 | input wire [5:0] disp2, 28 | 29 | output reg [5:0] disparity, 30 | output reg [13:0] window_sum 31 | ); 32 | 33 | initial 34 | begin 35 | disparity <= 0; 36 | window_sum <= 0; 37 | end 38 | 39 | always @(posedge clock or negedge reset_n) 40 | begin 41 | if(~reset_n) 42 | begin 43 | disparity <= 0; 44 | window_sum <= 0; 45 | end 46 | else 47 | begin 48 | if (ws2 < ws1) 49 | begin 50 | window_sum <= ws2; 51 | disparity <= disp2; 52 | end 53 | else 54 | begin 55 | window_sum <= ws1; 56 | disparity <= disp1; 57 | end 58 | end 59 | end 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /source/compare_ws.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:17:05 04/24/2012 7 | // Design Name: 8 | // Module Name: compare_ws 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module compare_ws( 22 | input wire clock, 23 | input wire reset_n, 24 | input wire [13:0] ws1, 25 | input wire [13:0] ws2, 26 | input wire [13:0] ws3, 27 | input wire [13:0] ws4, 28 | input wire [5:0] disp_1, 29 | input wire [5:0] disp_2, 30 | input wire [5:0] disp_3, 31 | input wire [5:0] disp_4, 32 | 33 | output wire [5:0] disparity, 34 | output wire [13:0] window_sum 35 | ); 36 | 37 | wire [13:0] con1; 38 | wire [13:0] con2; 39 | wire [5:0] con3; 40 | wire [5:0] con4; 41 | 42 | comparator compare_1 ( 43 | .clock (clock), 44 | .reset_n (reset_n), 45 | .ws1 (ws1), 46 | .ws2 (ws2), 47 | .disp1 (disp_1), 48 | .disp2 (disp_2), 49 | .disparity (con3), 50 | .window_sum (con1) 51 | ); 52 | 53 | comparator compare_2 ( 54 | .clock (clock), 55 | .reset_n (reset_n), 56 | .ws1 (ws3), 57 | .ws2 (ws4), 58 | .disp1 (disp_3), 59 | .disp2 (disp_4), 60 | .disparity (con4), 61 | .window_sum (con2) 62 | ); 63 | 64 | comparator compare_3 ( 65 | .clock (clock), 66 | .reset_n (reset_n), 67 | .ws1 (con1), 68 | .ws2 (con2), 69 | .disp1 (con3), 70 | .disp2 (con4), 71 | .disparity (disparity), 72 | .window_sum (window_sum) 73 | ); 74 | 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /source/decoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16:15:00 04/19/2012 7 | // Design Name: 8 | // Module Name: decoder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module decoder( 22 | input wire write_enable, 23 | input wire [2:0] select, 24 | 25 | output reg enable_0, 26 | output reg enable_1, 27 | output reg enable_2, 28 | output reg enable_3, 29 | output reg enable_4, 30 | output reg enable_5 31 | ); 32 | 33 | always @(write_enable, select) 34 | begin 35 | if (write_enable==1) 36 | begin 37 | case(select) 38 | 0: begin 39 | enable_0 = 1; 40 | enable_1 = 0; 41 | enable_2 = 0; 42 | enable_3 = 0; 43 | enable_4 = 0; 44 | enable_5 = 0; 45 | end 46 | 1: begin 47 | enable_0 = 0; 48 | enable_1 = 1; 49 | enable_2 = 0; 50 | enable_3 = 0; 51 | enable_4 = 0; 52 | enable_5 = 0; 53 | end 54 | 2: begin 55 | enable_0 = 0; 56 | enable_1 = 0; 57 | enable_2 = 1; 58 | enable_3 = 0; 59 | enable_4 = 0; 60 | enable_5 = 0; 61 | end 62 | 3: begin 63 | enable_0 = 0; 64 | enable_1 = 0; 65 | enable_2 = 0; 66 | enable_3 = 1; 67 | enable_4 = 0; 68 | enable_5 = 0; 69 | end 70 | 4: begin 71 | enable_0 = 0; 72 | enable_1 = 0; 73 | enable_2 = 0; 74 | enable_3 = 0; 75 | enable_4 = 1; 76 | enable_5 = 0; 77 | end 78 | 5: begin 79 | enable_0 = 0; 80 | enable_1 = 0; 81 | enable_2 = 0; 82 | enable_3 = 0; 83 | enable_4 = 0; 84 | enable_5 = 1; 85 | end 86 | default: begin 87 | enable_0 = 1'bx; 88 | enable_1 = 1'bx; 89 | enable_2 = 1'bx; 90 | enable_3 = 1'bx; 91 | enable_4 = 1'bx; 92 | enable_5 = 1'bx; 93 | end 94 | endcase 95 | end 96 | 97 | else 98 | begin 99 | enable_0 = 0; 100 | enable_1 = 0; 101 | enable_2 = 0; 102 | enable_3 = 0; 103 | enable_4 = 0; 104 | enable_5 = 0; 105 | end 106 | end 107 | 108 | endmodule 109 | -------------------------------------------------------------------------------- /source/disparity_counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:06:38 04/24/2012 7 | // Design Name: 8 | // Module Name: disparity_counter 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module disparity_counter( 22 | input wire clock, 23 | input wire reset_n, 24 | input wire read_start, 25 | 26 | output reg valid, 27 | output reg [9:0] pixel, 28 | output reg [5:0] disparity_1, 29 | output reg [5:0] disparity_2, 30 | output reg [5:0] disparity_3, 31 | output reg [5:0] disparity_4, 32 | output reg clear_buffer 33 | ); 34 | 35 | reg [1:0] state; 36 | reg [3:0] count; 37 | reg [4:0] cycle; 38 | reg [9:0] clear_buffer_count; 39 | 40 | initial 41 | begin 42 | valid <= 0; 43 | pixel <= 0; 44 | disparity_1 <= 63; 45 | disparity_2 <= 63; 46 | disparity_3 <= 63; 47 | disparity_4 <= 63; 48 | state <= 0; 49 | count <= 0; 50 | cycle <= 0; 51 | clear_buffer <= 0; 52 | clear_buffer_count <= 0; 53 | end 54 | 55 | always @(posedge clock or negedge reset_n) 56 | begin 57 | if(~reset_n) 58 | begin 59 | valid <= 0; 60 | pixel <= 0; 61 | disparity_1 <= 63; 62 | disparity_2 <= 63; 63 | disparity_3 <= 63; 64 | disparity_4 <= 63; 65 | state <= 0; 66 | count <= 0; 67 | cycle <= 0; 68 | clear_buffer <= 0; 69 | clear_buffer_count <= 0; 70 | end 71 | else 72 | begin 73 | case (state) 74 | 0: begin 75 | if (read_start == 1) 76 | begin 77 | count <= 0; 78 | disparity_1 <= 0; 79 | disparity_2 <= 1; 80 | disparity_3 <= 2; 81 | disparity_4 <= 3; 82 | state <= 1; 83 | end 84 | end 85 | 86 | 1: begin 87 | //Wait until entire window has been summed by the pipeline 88 | if (count == 11) 89 | begin 90 | valid <= 1; 91 | pixel <= 0; 92 | state <= 2; 93 | end 94 | else 95 | begin 96 | count <= count + 1'b1; 97 | end 98 | end 99 | 100 | 2: begin 101 | if (cycle == 16) 102 | begin 103 | valid <= 0; 104 | count <= 0; 105 | pixel <= 0; 106 | cycle <= 0; 107 | disparity_1 <= 0; 108 | disparity_2 <= 0; 109 | disparity_3 <= 0; 110 | disparity_4 <= 0; 111 | clear_buffer <= 1; 112 | state <= 3; 113 | end 114 | else 115 | begin 116 | if (pixel == 639) 117 | begin 118 | valid <= 0; 119 | disparity_1 <= disparity_1 + 3'b100; 120 | disparity_2 <= disparity_2 + 3'b100; 121 | disparity_3 <= disparity_3 + 3'b100; 122 | disparity_4 <= disparity_4 + 3'b100; 123 | pixel <= pixel + 1'b1; 124 | end 125 | else if (pixel == 643 && cycle != 15) 126 | begin 127 | valid <= 1; 128 | pixel <= 0; 129 | cycle <= cycle +1'b1; 130 | end 131 | else if (pixel == 643 && cycle == 15) 132 | begin 133 | valid <= 0; 134 | pixel <= 0; 135 | cycle <= cycle +1'b1; 136 | end 137 | else 138 | begin 139 | pixel <= pixel + 1'b1; 140 | end 141 | end 142 | end 143 | 144 | 3: begin 145 | if (clear_buffer_count == 639) 146 | begin 147 | clear_buffer <= 0; 148 | clear_buffer_count <= 0; 149 | state <= 0; 150 | end 151 | else 152 | begin 153 | clear_buffer_count <= clear_buffer_count + 1'b1; 154 | end 155 | end 156 | endcase 157 | end 158 | end 159 | 160 | endmodule 161 | -------------------------------------------------------------------------------- /source/fifo_buffer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:19:25 04/25/2012 7 | // Design Name: 8 | // Module Name: fifo_buffer 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module fifo_buffer( 22 | input wire clock, 23 | input wire [19:0] data_in, 24 | input wire valid, 25 | input wire [5:0] disparity, 26 | input wire read, 27 | 28 | output wire empty, 29 | output wire [19:0] data_out 30 | ); 31 | 32 | reg [19:0] din; 33 | reg wr_en; 34 | reg rd_en; 35 | 36 | //synthesis attribute box_type disparity_fifo "black_box" 37 | disparity_fifo buff ( 38 | .clk (clock), 39 | .din (din), 40 | .wr_en (wr_en), 41 | .rd_en (rd_en), 42 | .dout (data_out), 43 | .full (), 44 | .empty (empty) 45 | ); 46 | 47 | 48 | always @(valid, disparity, data_in, data_out, read) 49 | begin 50 | if (valid == 1) 51 | begin 52 | if (disparity == 0) 53 | begin 54 | wr_en <= 1; 55 | rd_en <= 0; 56 | din <= data_in; 57 | end 58 | else 59 | begin 60 | wr_en <= 1; 61 | rd_en <= 1; 62 | if (data_in[13:0] < data_out[13:0]) 63 | din <= data_in; 64 | else 65 | din <= data_out; 66 | end 67 | end 68 | else if (read == 1) 69 | begin 70 | wr_en <= 0; 71 | rd_en <= 1; 72 | din <= 0; 73 | end 74 | else 75 | begin 76 | wr_en <= 0; 77 | rd_en <= 0; 78 | din <= 0; 79 | end 80 | end 81 | 82 | endmodule 83 | -------------------------------------------------------------------------------- /source/image_buffer.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used solely * 3 | * for design, simulation, implementation and creation of design files * 4 | * limited to Xilinx devices or technologies. Use with non-Xilinx * 5 | * devices or technologies is expressly prohibited and immediately * 6 | * terminates your license. * 7 | * * 8 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * 9 | * FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * 10 | * PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * 11 | * IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * 12 | * MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * 13 | * CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * 14 | * RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * 15 | * DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * 16 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * 17 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * 18 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * 19 | * PARTICULAR PURPOSE. * 20 | * * 21 | * Xilinx products are not intended for use in life support appliances, * 22 | * devices, or systems. Use in such applications are expressly * 23 | * prohibited. * 24 | * * 25 | * (c) Copyright 1995-2012 Xilinx, Inc. * 26 | * All rights reserved. * 27 | *******************************************************************************/ 28 | // You must compile the wrapper file image_buffer.v when simulating 29 | // the core, image_buffer. When compiling the wrapper file, be sure to 30 | // reference the XilinxCoreLib Verilog simulation library. For detailed 31 | // instructions, please refer to the "CORE Generator Help". 32 | 33 | // The synthesis directives "translate_off/translate_on" specified below are 34 | // supported by Xilinx, Mentor Graphics and Synplicity synthesis 35 | // tools. Ensure they are correct for your synthesis tool(s). 36 | 37 | `timescale 1ns/1ps 38 | 39 | module image_buffer( 40 | clk, 41 | din, 42 | wr_en, 43 | rd_en, 44 | dout, 45 | full, 46 | empty 47 | ); 48 | 49 | input clk; 50 | input [7 : 0] din; 51 | input wr_en; 52 | input rd_en; 53 | output [7 : 0] dout; 54 | output full; 55 | output empty; 56 | 57 | // synthesis translate_off 58 | 59 | FIFO_GENERATOR_V8_3 #( 60 | .C_ADD_NGC_CONSTRAINT(0), 61 | .C_APPLICATION_TYPE_AXIS(0), 62 | .C_APPLICATION_TYPE_RACH(0), 63 | .C_APPLICATION_TYPE_RDCH(0), 64 | .C_APPLICATION_TYPE_WACH(0), 65 | .C_APPLICATION_TYPE_WDCH(0), 66 | .C_APPLICATION_TYPE_WRCH(0), 67 | .C_AXI_ADDR_WIDTH(32), 68 | .C_AXI_ARUSER_WIDTH(1), 69 | .C_AXI_AWUSER_WIDTH(1), 70 | .C_AXI_BUSER_WIDTH(1), 71 | .C_AXI_DATA_WIDTH(64), 72 | .C_AXI_ID_WIDTH(4), 73 | .C_AXI_RUSER_WIDTH(1), 74 | .C_AXI_TYPE(0), 75 | .C_AXI_WUSER_WIDTH(1), 76 | .C_AXIS_TDATA_WIDTH(64), 77 | .C_AXIS_TDEST_WIDTH(4), 78 | .C_AXIS_TID_WIDTH(8), 79 | .C_AXIS_TKEEP_WIDTH(4), 80 | .C_AXIS_TSTRB_WIDTH(4), 81 | .C_AXIS_TUSER_WIDTH(4), 82 | .C_AXIS_TYPE(0), 83 | .C_COMMON_CLOCK(1), 84 | .C_COUNT_TYPE(0), 85 | .C_DATA_COUNT_WIDTH(11), 86 | .C_DEFAULT_VALUE("BlankString"), 87 | .C_DIN_WIDTH(8), 88 | .C_DIN_WIDTH_AXIS(1), 89 | .C_DIN_WIDTH_RACH(32), 90 | .C_DIN_WIDTH_RDCH(64), 91 | .C_DIN_WIDTH_WACH(32), 92 | .C_DIN_WIDTH_WDCH(64), 93 | .C_DIN_WIDTH_WRCH(2), 94 | .C_DOUT_RST_VAL("0"), 95 | .C_DOUT_WIDTH(8), 96 | .C_ENABLE_RLOCS(0), 97 | .C_ENABLE_RST_SYNC(1), 98 | .C_ERROR_INJECTION_TYPE(0), 99 | .C_ERROR_INJECTION_TYPE_AXIS(0), 100 | .C_ERROR_INJECTION_TYPE_RACH(0), 101 | .C_ERROR_INJECTION_TYPE_RDCH(0), 102 | .C_ERROR_INJECTION_TYPE_WACH(0), 103 | .C_ERROR_INJECTION_TYPE_WDCH(0), 104 | .C_ERROR_INJECTION_TYPE_WRCH(0), 105 | .C_FAMILY("spartan6"), 106 | .C_FULL_FLAGS_RST_VAL(0), 107 | .C_HAS_ALMOST_EMPTY(0), 108 | .C_HAS_ALMOST_FULL(0), 109 | .C_HAS_AXI_ARUSER(0), 110 | .C_HAS_AXI_AWUSER(0), 111 | .C_HAS_AXI_BUSER(0), 112 | .C_HAS_AXI_RD_CHANNEL(0), 113 | .C_HAS_AXI_RUSER(0), 114 | .C_HAS_AXI_WR_CHANNEL(0), 115 | .C_HAS_AXI_WUSER(0), 116 | .C_HAS_AXIS_TDATA(0), 117 | .C_HAS_AXIS_TDEST(0), 118 | .C_HAS_AXIS_TID(0), 119 | .C_HAS_AXIS_TKEEP(0), 120 | .C_HAS_AXIS_TLAST(0), 121 | .C_HAS_AXIS_TREADY(1), 122 | .C_HAS_AXIS_TSTRB(0), 123 | .C_HAS_AXIS_TUSER(0), 124 | .C_HAS_BACKUP(0), 125 | .C_HAS_DATA_COUNT(0), 126 | .C_HAS_DATA_COUNTS_AXIS(0), 127 | .C_HAS_DATA_COUNTS_RACH(0), 128 | .C_HAS_DATA_COUNTS_RDCH(0), 129 | .C_HAS_DATA_COUNTS_WACH(0), 130 | .C_HAS_DATA_COUNTS_WDCH(0), 131 | .C_HAS_DATA_COUNTS_WRCH(0), 132 | .C_HAS_INT_CLK(0), 133 | .C_HAS_MASTER_CE(0), 134 | .C_HAS_MEMINIT_FILE(0), 135 | .C_HAS_OVERFLOW(0), 136 | .C_HAS_PROG_FLAGS_AXIS(0), 137 | .C_HAS_PROG_FLAGS_RACH(0), 138 | .C_HAS_PROG_FLAGS_RDCH(0), 139 | .C_HAS_PROG_FLAGS_WACH(0), 140 | .C_HAS_PROG_FLAGS_WDCH(0), 141 | .C_HAS_PROG_FLAGS_WRCH(0), 142 | .C_HAS_RD_DATA_COUNT(0), 143 | .C_HAS_RD_RST(0), 144 | .C_HAS_RST(0), 145 | .C_HAS_SLAVE_CE(0), 146 | .C_HAS_SRST(0), 147 | .C_HAS_UNDERFLOW(0), 148 | .C_HAS_VALID(0), 149 | .C_HAS_WR_ACK(0), 150 | .C_HAS_WR_DATA_COUNT(0), 151 | .C_HAS_WR_RST(0), 152 | .C_IMPLEMENTATION_TYPE(0), 153 | .C_IMPLEMENTATION_TYPE_AXIS(1), 154 | .C_IMPLEMENTATION_TYPE_RACH(1), 155 | .C_IMPLEMENTATION_TYPE_RDCH(1), 156 | .C_IMPLEMENTATION_TYPE_WACH(1), 157 | .C_IMPLEMENTATION_TYPE_WDCH(1), 158 | .C_IMPLEMENTATION_TYPE_WRCH(1), 159 | .C_INIT_WR_PNTR_VAL(0), 160 | .C_INTERFACE_TYPE(0), 161 | .C_MEMORY_TYPE(1), 162 | .C_MIF_FILE_NAME("BlankString"), 163 | .C_MSGON_VAL(1), 164 | .C_OPTIMIZATION_MODE(0), 165 | .C_OVERFLOW_LOW(0), 166 | .C_PRELOAD_LATENCY(0), 167 | .C_PRELOAD_REGS(1), 168 | .C_PRIM_FIFO_TYPE("1kx18"), 169 | .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), 170 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), 171 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), 172 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), 173 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), 174 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), 175 | .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), 176 | .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), 177 | .C_PROG_EMPTY_TYPE(0), 178 | .C_PROG_EMPTY_TYPE_AXIS(5), 179 | .C_PROG_EMPTY_TYPE_RACH(5), 180 | .C_PROG_EMPTY_TYPE_RDCH(5), 181 | .C_PROG_EMPTY_TYPE_WACH(5), 182 | .C_PROG_EMPTY_TYPE_WDCH(5), 183 | .C_PROG_EMPTY_TYPE_WRCH(5), 184 | .C_PROG_FULL_THRESH_ASSERT_VAL(1023), 185 | .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), 186 | .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), 187 | .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), 188 | .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), 189 | .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), 190 | .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), 191 | .C_PROG_FULL_THRESH_NEGATE_VAL(1022), 192 | .C_PROG_FULL_TYPE(0), 193 | .C_PROG_FULL_TYPE_AXIS(5), 194 | .C_PROG_FULL_TYPE_RACH(5), 195 | .C_PROG_FULL_TYPE_RDCH(5), 196 | .C_PROG_FULL_TYPE_WACH(5), 197 | .C_PROG_FULL_TYPE_WDCH(5), 198 | .C_PROG_FULL_TYPE_WRCH(5), 199 | .C_RACH_TYPE(0), 200 | .C_RD_DATA_COUNT_WIDTH(11), 201 | .C_RD_DEPTH(1024), 202 | .C_RD_FREQ(1), 203 | .C_RD_PNTR_WIDTH(10), 204 | .C_RDCH_TYPE(0), 205 | .C_REG_SLICE_MODE_AXIS(0), 206 | .C_REG_SLICE_MODE_RACH(0), 207 | .C_REG_SLICE_MODE_RDCH(0), 208 | .C_REG_SLICE_MODE_WACH(0), 209 | .C_REG_SLICE_MODE_WDCH(0), 210 | .C_REG_SLICE_MODE_WRCH(0), 211 | .C_UNDERFLOW_LOW(0), 212 | .C_USE_COMMON_OVERFLOW(0), 213 | .C_USE_COMMON_UNDERFLOW(0), 214 | .C_USE_DEFAULT_SETTINGS(0), 215 | .C_USE_DOUT_RST(0), 216 | .C_USE_ECC(0), 217 | .C_USE_ECC_AXIS(0), 218 | .C_USE_ECC_RACH(0), 219 | .C_USE_ECC_RDCH(0), 220 | .C_USE_ECC_WACH(0), 221 | .C_USE_ECC_WDCH(0), 222 | .C_USE_ECC_WRCH(0), 223 | .C_USE_EMBEDDED_REG(0), 224 | .C_USE_FIFO16_FLAGS(0), 225 | .C_USE_FWFT_DATA_COUNT(1), 226 | .C_VALID_LOW(0), 227 | .C_WACH_TYPE(0), 228 | .C_WDCH_TYPE(0), 229 | .C_WR_ACK_LOW(0), 230 | .C_WR_DATA_COUNT_WIDTH(11), 231 | .C_WR_DEPTH(1024), 232 | .C_WR_DEPTH_AXIS(1024), 233 | .C_WR_DEPTH_RACH(16), 234 | .C_WR_DEPTH_RDCH(1024), 235 | .C_WR_DEPTH_WACH(16), 236 | .C_WR_DEPTH_WDCH(1024), 237 | .C_WR_DEPTH_WRCH(16), 238 | .C_WR_FREQ(1), 239 | .C_WR_PNTR_WIDTH(10), 240 | .C_WR_PNTR_WIDTH_AXIS(10), 241 | .C_WR_PNTR_WIDTH_RACH(4), 242 | .C_WR_PNTR_WIDTH_RDCH(10), 243 | .C_WR_PNTR_WIDTH_WACH(4), 244 | .C_WR_PNTR_WIDTH_WDCH(10), 245 | .C_WR_PNTR_WIDTH_WRCH(4), 246 | .C_WR_RESPONSE_LATENCY(1), 247 | .C_WRCH_TYPE(0) 248 | ) 249 | inst ( 250 | .CLK(clk), 251 | .DIN(din), 252 | .WR_EN(wr_en), 253 | .RD_EN(rd_en), 254 | .DOUT(dout), 255 | .FULL(full), 256 | .EMPTY(empty), 257 | .BACKUP(), 258 | .BACKUP_MARKER(), 259 | .RST(), 260 | .SRST(), 261 | .WR_CLK(), 262 | .WR_RST(), 263 | .RD_CLK(), 264 | .RD_RST(), 265 | .PROG_EMPTY_THRESH(), 266 | .PROG_EMPTY_THRESH_ASSERT(), 267 | .PROG_EMPTY_THRESH_NEGATE(), 268 | .PROG_FULL_THRESH(), 269 | .PROG_FULL_THRESH_ASSERT(), 270 | .PROG_FULL_THRESH_NEGATE(), 271 | .INT_CLK(), 272 | .INJECTDBITERR(), 273 | .INJECTSBITERR(), 274 | .ALMOST_FULL(), 275 | .WR_ACK(), 276 | .OVERFLOW(), 277 | .ALMOST_EMPTY(), 278 | .VALID(), 279 | .UNDERFLOW(), 280 | .DATA_COUNT(), 281 | .RD_DATA_COUNT(), 282 | .WR_DATA_COUNT(), 283 | .PROG_FULL(), 284 | .PROG_EMPTY(), 285 | .SBITERR(), 286 | .DBITERR(), 287 | .M_ACLK(), 288 | .S_ACLK(), 289 | .S_ARESETN(), 290 | .M_ACLK_EN(), 291 | .S_ACLK_EN(), 292 | .S_AXI_AWID(), 293 | .S_AXI_AWADDR(), 294 | .S_AXI_AWLEN(), 295 | .S_AXI_AWSIZE(), 296 | .S_AXI_AWBURST(), 297 | .S_AXI_AWLOCK(), 298 | .S_AXI_AWCACHE(), 299 | .S_AXI_AWPROT(), 300 | .S_AXI_AWQOS(), 301 | .S_AXI_AWREGION(), 302 | .S_AXI_AWUSER(), 303 | .S_AXI_AWVALID(), 304 | .S_AXI_AWREADY(), 305 | .S_AXI_WID(), 306 | .S_AXI_WDATA(), 307 | .S_AXI_WSTRB(), 308 | .S_AXI_WLAST(), 309 | .S_AXI_WUSER(), 310 | .S_AXI_WVALID(), 311 | .S_AXI_WREADY(), 312 | .S_AXI_BID(), 313 | .S_AXI_BRESP(), 314 | .S_AXI_BUSER(), 315 | .S_AXI_BVALID(), 316 | .S_AXI_BREADY(), 317 | .M_AXI_AWID(), 318 | .M_AXI_AWADDR(), 319 | .M_AXI_AWLEN(), 320 | .M_AXI_AWSIZE(), 321 | .M_AXI_AWBURST(), 322 | .M_AXI_AWLOCK(), 323 | .M_AXI_AWCACHE(), 324 | .M_AXI_AWPROT(), 325 | .M_AXI_AWQOS(), 326 | .M_AXI_AWREGION(), 327 | .M_AXI_AWUSER(), 328 | .M_AXI_AWVALID(), 329 | .M_AXI_AWREADY(), 330 | .M_AXI_WID(), 331 | .M_AXI_WDATA(), 332 | .M_AXI_WSTRB(), 333 | .M_AXI_WLAST(), 334 | .M_AXI_WUSER(), 335 | .M_AXI_WVALID(), 336 | .M_AXI_WREADY(), 337 | .M_AXI_BID(), 338 | .M_AXI_BRESP(), 339 | .M_AXI_BUSER(), 340 | .M_AXI_BVALID(), 341 | .M_AXI_BREADY(), 342 | .S_AXI_ARID(), 343 | .S_AXI_ARADDR(), 344 | .S_AXI_ARLEN(), 345 | .S_AXI_ARSIZE(), 346 | .S_AXI_ARBURST(), 347 | .S_AXI_ARLOCK(), 348 | .S_AXI_ARCACHE(), 349 | .S_AXI_ARPROT(), 350 | .S_AXI_ARQOS(), 351 | .S_AXI_ARREGION(), 352 | .S_AXI_ARUSER(), 353 | .S_AXI_ARVALID(), 354 | .S_AXI_ARREADY(), 355 | .S_AXI_RID(), 356 | .S_AXI_RDATA(), 357 | .S_AXI_RRESP(), 358 | .S_AXI_RLAST(), 359 | .S_AXI_RUSER(), 360 | .S_AXI_RVALID(), 361 | .S_AXI_RREADY(), 362 | .M_AXI_ARID(), 363 | .M_AXI_ARADDR(), 364 | .M_AXI_ARLEN(), 365 | .M_AXI_ARSIZE(), 366 | .M_AXI_ARBURST(), 367 | .M_AXI_ARLOCK(), 368 | .M_AXI_ARCACHE(), 369 | .M_AXI_ARPROT(), 370 | .M_AXI_ARQOS(), 371 | .M_AXI_ARREGION(), 372 | .M_AXI_ARUSER(), 373 | .M_AXI_ARVALID(), 374 | .M_AXI_ARREADY(), 375 | .M_AXI_RID(), 376 | .M_AXI_RDATA(), 377 | .M_AXI_RRESP(), 378 | .M_AXI_RLAST(), 379 | .M_AXI_RUSER(), 380 | .M_AXI_RVALID(), 381 | .M_AXI_RREADY(), 382 | .S_AXIS_TVALID(), 383 | .S_AXIS_TREADY(), 384 | .S_AXIS_TDATA(), 385 | .S_AXIS_TSTRB(), 386 | .S_AXIS_TKEEP(), 387 | .S_AXIS_TLAST(), 388 | .S_AXIS_TID(), 389 | .S_AXIS_TDEST(), 390 | .S_AXIS_TUSER(), 391 | .M_AXIS_TVALID(), 392 | .M_AXIS_TREADY(), 393 | .M_AXIS_TDATA(), 394 | .M_AXIS_TSTRB(), 395 | .M_AXIS_TKEEP(), 396 | .M_AXIS_TLAST(), 397 | .M_AXIS_TID(), 398 | .M_AXIS_TDEST(), 399 | .M_AXIS_TUSER(), 400 | .AXI_AW_INJECTSBITERR(), 401 | .AXI_AW_INJECTDBITERR(), 402 | .AXI_AW_PROG_FULL_THRESH(), 403 | .AXI_AW_PROG_EMPTY_THRESH(), 404 | .AXI_AW_DATA_COUNT(), 405 | .AXI_AW_WR_DATA_COUNT(), 406 | .AXI_AW_RD_DATA_COUNT(), 407 | .AXI_AW_SBITERR(), 408 | .AXI_AW_DBITERR(), 409 | .AXI_AW_OVERFLOW(), 410 | .AXI_AW_UNDERFLOW(), 411 | .AXI_W_INJECTSBITERR(), 412 | .AXI_W_INJECTDBITERR(), 413 | .AXI_W_PROG_FULL_THRESH(), 414 | .AXI_W_PROG_EMPTY_THRESH(), 415 | .AXI_W_DATA_COUNT(), 416 | .AXI_W_WR_DATA_COUNT(), 417 | .AXI_W_RD_DATA_COUNT(), 418 | .AXI_W_SBITERR(), 419 | .AXI_W_DBITERR(), 420 | .AXI_W_OVERFLOW(), 421 | .AXI_W_UNDERFLOW(), 422 | .AXI_B_INJECTSBITERR(), 423 | .AXI_B_INJECTDBITERR(), 424 | .AXI_B_PROG_FULL_THRESH(), 425 | .AXI_B_PROG_EMPTY_THRESH(), 426 | .AXI_B_DATA_COUNT(), 427 | .AXI_B_WR_DATA_COUNT(), 428 | .AXI_B_RD_DATA_COUNT(), 429 | .AXI_B_SBITERR(), 430 | .AXI_B_DBITERR(), 431 | .AXI_B_OVERFLOW(), 432 | .AXI_B_UNDERFLOW(), 433 | .AXI_AR_INJECTSBITERR(), 434 | .AXI_AR_INJECTDBITERR(), 435 | .AXI_AR_PROG_FULL_THRESH(), 436 | .AXI_AR_PROG_EMPTY_THRESH(), 437 | .AXI_AR_DATA_COUNT(), 438 | .AXI_AR_WR_DATA_COUNT(), 439 | .AXI_AR_RD_DATA_COUNT(), 440 | .AXI_AR_SBITERR(), 441 | .AXI_AR_DBITERR(), 442 | .AXI_AR_OVERFLOW(), 443 | .AXI_AR_UNDERFLOW(), 444 | .AXI_R_INJECTSBITERR(), 445 | .AXI_R_INJECTDBITERR(), 446 | .AXI_R_PROG_FULL_THRESH(), 447 | .AXI_R_PROG_EMPTY_THRESH(), 448 | .AXI_R_DATA_COUNT(), 449 | .AXI_R_WR_DATA_COUNT(), 450 | .AXI_R_RD_DATA_COUNT(), 451 | .AXI_R_SBITERR(), 452 | .AXI_R_DBITERR(), 453 | .AXI_R_OVERFLOW(), 454 | .AXI_R_UNDERFLOW(), 455 | .AXIS_INJECTSBITERR(), 456 | .AXIS_INJECTDBITERR(), 457 | .AXIS_PROG_FULL_THRESH(), 458 | .AXIS_PROG_EMPTY_THRESH(), 459 | .AXIS_DATA_COUNT(), 460 | .AXIS_WR_DATA_COUNT(), 461 | .AXIS_RD_DATA_COUNT(), 462 | .AXIS_SBITERR(), 463 | .AXIS_DBITERR(), 464 | .AXIS_OVERFLOW(), 465 | .AXIS_UNDERFLOW() 466 | ); 467 | 468 | // synthesis translate_on 469 | 470 | endmodule 471 | -------------------------------------------------------------------------------- /source/left_counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:13:24 04/13/2012 7 | // Design Name: 8 | // Module Name: left_counter 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module left_counter( 22 | input wire rea, 23 | input wire clock, 24 | output reg read_enable, 25 | output reg [9:0] addrb 26 | ); 27 | 28 | reg [4:0] cycle; 29 | reg [9:0] count; 30 | reg running; 31 | 32 | initial 33 | begin 34 | cycle <= 0; 35 | count <= 1; 36 | addrb <= 0; 37 | running <= 0; 38 | read_enable <= 0; 39 | end 40 | 41 | always @(posedge clock) 42 | begin 43 | //Wait for start signal 44 | if (running == 0) 45 | begin 46 | if (rea==1) 47 | begin 48 | running <= 1; 49 | read_enable <= 1; 50 | end 51 | end 52 | 53 | else 54 | begin 55 | //Output addresses 0-643 16 times 56 | if (cycle == 16) 57 | begin 58 | cycle <= 0; 59 | count <= 1; 60 | addrb <= 0; 61 | running <= 0; 62 | read_enable <= 0; 63 | end 64 | 65 | //Reset and return to waiting 66 | else 67 | begin 68 | if (count == 643) 69 | begin 70 | addrb <= count; 71 | cycle <= cycle+1'b1; 72 | count <= 0; 73 | end 74 | else 75 | begin 76 | addrb <= count; 77 | count <= count+1'b1; 78 | end 79 | end 80 | end 81 | end 82 | endmodule 83 | -------------------------------------------------------------------------------- /source/line_buffer.v: -------------------------------------------------------------------------------- 1 | /******************************************************************************* 2 | * This file is owned and controlled by Xilinx and must be used solely * 3 | * for design, simulation, implementation and creation of design files * 4 | * limited to Xilinx devices or technologies. Use with non-Xilinx * 5 | * devices or technologies is expressly prohibited and immediately * 6 | * terminates your license. * 7 | * * 8 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * 9 | * FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * 10 | * PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * 11 | * IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * 12 | * MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * 13 | * CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * 14 | * RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * 15 | * DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * 16 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * 17 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * 18 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * 19 | * PARTICULAR PURPOSE. * 20 | * * 21 | * Xilinx products are not intended for use in life support appliances, * 22 | * devices, or systems. Use in such applications are expressly * 23 | * prohibited. * 24 | * * 25 | * (c) Copyright 1995-2012 Xilinx, Inc. * 26 | * All rights reserved. * 27 | *******************************************************************************/ 28 | // You must compile the wrapper file line_buffer.v when simulating 29 | // the core, line_buffer. When compiling the wrapper file, be sure to 30 | // reference the XilinxCoreLib Verilog simulation library. For detailed 31 | // instructions, please refer to the "CORE Generator Help". 32 | 33 | // The synthesis directives "translate_off/translate_on" specified below are 34 | // supported by Xilinx, Mentor Graphics and Synplicity synthesis 35 | // tools. Ensure they are correct for your synthesis tool(s). 36 | 37 | `timescale 1ns/1ps 38 | 39 | module line_buffer( 40 | clka, 41 | wea, 42 | addra, 43 | dina, 44 | clkb, 45 | enb, 46 | addrb, 47 | doutb 48 | ); 49 | 50 | input clka; 51 | input [0 : 0] wea; 52 | input [9 : 0] addra; 53 | input [7 : 0] dina; 54 | input clkb; 55 | input enb; 56 | input [9 : 0] addrb; 57 | output [7 : 0] doutb; 58 | 59 | // synthesis translate_off 60 | 61 | BLK_MEM_GEN_V6_2 #( 62 | .C_ADDRA_WIDTH(10), 63 | .C_ADDRB_WIDTH(10), 64 | .C_ALGORITHM(1), 65 | .C_AXI_ID_WIDTH(4), 66 | .C_AXI_SLAVE_TYPE(0), 67 | .C_AXI_TYPE(1), 68 | .C_BYTE_SIZE(9), 69 | .C_COMMON_CLK(0), 70 | .C_DEFAULT_DATA("0"), 71 | .C_DISABLE_WARN_BHV_COLL(0), 72 | .C_DISABLE_WARN_BHV_RANGE(0), 73 | .C_FAMILY("spartan6"), 74 | .C_HAS_AXI_ID(0), 75 | .C_HAS_ENA(0), 76 | .C_HAS_ENB(1), 77 | .C_HAS_INJECTERR(0), 78 | .C_HAS_MEM_OUTPUT_REGS_A(0), 79 | .C_HAS_MEM_OUTPUT_REGS_B(0), 80 | .C_HAS_MUX_OUTPUT_REGS_A(0), 81 | .C_HAS_MUX_OUTPUT_REGS_B(0), 82 | .C_HAS_REGCEA(0), 83 | .C_HAS_REGCEB(0), 84 | .C_HAS_RSTA(0), 85 | .C_HAS_RSTB(0), 86 | .C_HAS_SOFTECC_INPUT_REGS_A(0), 87 | .C_HAS_SOFTECC_OUTPUT_REGS_B(0), 88 | .C_INIT_FILE_NAME("no_coe_file_loaded"), 89 | .C_INITA_VAL("0"), 90 | .C_INITB_VAL("0"), 91 | .C_INTERFACE_TYPE(0), 92 | .C_LOAD_INIT_FILE(0), 93 | .C_MEM_TYPE(1), 94 | .C_MUX_PIPELINE_STAGES(0), 95 | .C_PRIM_TYPE(1), 96 | .C_READ_DEPTH_A(708), 97 | .C_READ_DEPTH_B(708), 98 | .C_READ_WIDTH_A(8), 99 | .C_READ_WIDTH_B(8), 100 | .C_RST_PRIORITY_A("CE"), 101 | .C_RST_PRIORITY_B("CE"), 102 | .C_RST_TYPE("SYNC"), 103 | .C_RSTRAM_A(0), 104 | .C_RSTRAM_B(0), 105 | .C_SIM_COLLISION_CHECK("ALL"), 106 | .C_USE_BYTE_WEA(0), 107 | .C_USE_BYTE_WEB(0), 108 | .C_USE_DEFAULT_DATA(0), 109 | .C_USE_ECC(0), 110 | .C_USE_SOFTECC(0), 111 | .C_WEA_WIDTH(1), 112 | .C_WEB_WIDTH(1), 113 | .C_WRITE_DEPTH_A(708), 114 | .C_WRITE_DEPTH_B(708), 115 | .C_WRITE_MODE_A("WRITE_FIRST"), 116 | .C_WRITE_MODE_B("WRITE_FIRST"), 117 | .C_WRITE_WIDTH_A(8), 118 | .C_WRITE_WIDTH_B(8), 119 | .C_XDEVICEFAMILY("spartan6") 120 | ) 121 | inst ( 122 | .CLKA(clka), 123 | .WEA(wea), 124 | .ADDRA(addra), 125 | .DINA(dina), 126 | .CLKB(clkb), 127 | .ENB(enb), 128 | .ADDRB(addrb), 129 | .DOUTB(doutb), 130 | .RSTA(), 131 | .ENA(), 132 | .REGCEA(), 133 | .DOUTA(), 134 | .RSTB(), 135 | .REGCEB(), 136 | .WEB(), 137 | .DINB(), 138 | .INJECTSBITERR(), 139 | .INJECTDBITERR(), 140 | .SBITERR(), 141 | .DBITERR(), 142 | .RDADDRECC(), 143 | .S_ACLK(), 144 | .S_ARESETN(), 145 | .S_AXI_AWID(), 146 | .S_AXI_AWADDR(), 147 | .S_AXI_AWLEN(), 148 | .S_AXI_AWSIZE(), 149 | .S_AXI_AWBURST(), 150 | .S_AXI_AWVALID(), 151 | .S_AXI_AWREADY(), 152 | .S_AXI_WDATA(), 153 | .S_AXI_WSTRB(), 154 | .S_AXI_WLAST(), 155 | .S_AXI_WVALID(), 156 | .S_AXI_WREADY(), 157 | .S_AXI_BID(), 158 | .S_AXI_BRESP(), 159 | .S_AXI_BVALID(), 160 | .S_AXI_BREADY(), 161 | .S_AXI_ARID(), 162 | .S_AXI_ARADDR(), 163 | .S_AXI_ARLEN(), 164 | .S_AXI_ARSIZE(), 165 | .S_AXI_ARBURST(), 166 | .S_AXI_ARVALID(), 167 | .S_AXI_ARREADY(), 168 | .S_AXI_RID(), 169 | .S_AXI_RDATA(), 170 | .S_AXI_RRESP(), 171 | .S_AXI_RLAST(), 172 | .S_AXI_RVALID(), 173 | .S_AXI_RREADY(), 174 | .S_AXI_INJECTSBITERR(), 175 | .S_AXI_INJECTDBITERR(), 176 | .S_AXI_SBITERR(), 177 | .S_AXI_DBITERR(), 178 | .S_AXI_RDADDRECC() 179 | ); 180 | 181 | // synthesis translate_on 182 | 183 | endmodule 184 | -------------------------------------------------------------------------------- /source/line_buffers.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:29:24 04/13/2012 7 | // Design Name: 8 | // Module Name: line_buffers 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module line_buffers( 22 | input wire clock_slow, 23 | input wire clock_fast, 24 | input wire write_enable, 25 | input wire [9:0] address_in, 26 | input wire [7:0] data_in, 27 | input wire read_enable, 28 | input wire [9:0] address_out, 29 | input wire [2:0] select, 30 | 31 | output wire [7:0] data_out_1, 32 | output wire [7:0] data_out_2, 33 | output wire [7:0] data_out_3, 34 | output wire [7:0] data_out_4, 35 | output wire [7:0] data_out_5 36 | ); 37 | 38 | wire [7:0] data_0; 39 | wire [7:0] data_1; 40 | wire [7:0] data_2; 41 | wire [7:0] data_3; 42 | wire [7:0] data_4; 43 | wire [7:0] data_5; 44 | 45 | wire enable_0; 46 | wire enable_1; 47 | wire enable_2; 48 | wire enable_3; 49 | wire enable_4; 50 | wire enable_5; 51 | 52 | //*********************************************************** 53 | //Buffers 54 | //*********************************************************** 55 | //synthesis attribute box_type line_buffer "black_box" 56 | line_buffer buff_0( 57 | .clka (clock_slow), 58 | .wea (enable_0), 59 | .addra (address_in), 60 | .dina (data_in), 61 | .clkb (clock_fast), 62 | .enb (~enable_0 & read_enable), 63 | .addrb (address_out), 64 | .doutb (data_0) 65 | ); 66 | 67 | line_buffer buff_1( 68 | .clka (clock_slow), 69 | .wea (enable_1), 70 | .addra (address_in), 71 | .dina (data_in), 72 | .clkb (clock_fast), 73 | .enb (~enable_1 & read_enable), 74 | .addrb (address_out), 75 | .doutb (data_1) 76 | ); 77 | 78 | line_buffer buff_2( 79 | .clka (clock_slow), 80 | .wea (enable_2), 81 | .addra (address_in), 82 | .dina (data_in), 83 | .clkb (clock_fast), 84 | .enb (~enable_2 & read_enable), 85 | .addrb (address_out), 86 | .doutb (data_2) 87 | ); 88 | 89 | line_buffer buff_3( 90 | .clka (clock_slow), 91 | .wea (enable_3), 92 | .addra (address_in), 93 | .dina (data_in), 94 | .clkb (clock_fast), 95 | .enb (~enable_3 & read_enable), 96 | .addrb (address_out), 97 | .doutb (data_3) 98 | ); 99 | 100 | line_buffer buff_4( 101 | .clka (clock_slow), 102 | .wea (enable_4), 103 | .addra (address_in), 104 | .dina (data_in), 105 | .clkb (clock_fast), 106 | .enb (~enable_4 & read_enable), 107 | .addrb (address_out), 108 | .doutb (data_4) 109 | ); 110 | 111 | line_buffer buff_5( 112 | .clka (clock_slow), 113 | .wea (enable_5), 114 | .addra (address_in), 115 | .dina (data_in), 116 | .clkb (clock_fast), 117 | .enb (~enable_5 & read_enable), 118 | .addrb (address_out), 119 | .doutb (data_5) 120 | ); 121 | 122 | //******************************************************** 123 | //Write Enable Selector 124 | //******************************************************** 125 | decoder dec( 126 | .write_enable (write_enable), 127 | .select (select), 128 | .enable_0 (enable_0), 129 | .enable_1 (enable_1), 130 | .enable_2 (enable_2), 131 | .enable_3 (enable_3), 132 | .enable_4 (enable_4), 133 | .enable_5 (enable_5) 134 | ); 135 | 136 | //******************************************************** 137 | //Multiplexors 138 | //******************************************************** 139 | mux_6_to_1 mux1( 140 | //.clock (clock), 141 | .data_0 (data_0), 142 | .data_1 (data_1), 143 | .data_2 (data_2), 144 | .data_3 (data_3), 145 | .data_4 (data_4), 146 | .data_5 (data_5), 147 | .select (select), 148 | .data_out (data_out_1) 149 | ); 150 | 151 | mux_6_to_1 mux2( 152 | //.clock (clock), 153 | .data_0 (data_1), 154 | .data_1 (data_2), 155 | .data_2 (data_3), 156 | .data_3 (data_4), 157 | .data_4 (data_5), 158 | .data_5 (data_0), 159 | .select (select), 160 | .data_out (data_out_2) 161 | ); 162 | 163 | mux_6_to_1 mux3( 164 | //.clock (clock), 165 | .data_0 (data_2), 166 | .data_1 (data_3), 167 | .data_2 (data_4), 168 | .data_3 (data_5), 169 | .data_4 (data_0), 170 | .data_5 (data_1), 171 | .select (select), 172 | .data_out (data_out_3) 173 | ); 174 | 175 | mux_6_to_1 mux4( 176 | //.clock (clock), 177 | .data_0 (data_3), 178 | .data_1 (data_4), 179 | .data_2 (data_5), 180 | .data_3 (data_0), 181 | .data_4 (data_1), 182 | .data_5 (data_2), 183 | .select (select), 184 | .data_out (data_out_4) 185 | ); 186 | 187 | mux_6_to_1 mux5( 188 | //.clock (clock), 189 | .data_0 (data_4), 190 | .data_1 (data_5), 191 | .data_2 (data_0), 192 | .data_3 (data_1), 193 | .data_4 (data_2), 194 | .data_5 (data_3), 195 | .select (select), 196 | .data_out (data_out_5) 197 | ); 198 | 199 | endmodule 200 | -------------------------------------------------------------------------------- /source/mux_6_to_1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15:46:03 04/19/2012 7 | // Design Name: 8 | // Module Name: mux_6_to_1 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mux_6_to_1( 22 | //input wire clock, 23 | input wire [7:0] data_0, 24 | input wire [7:0] data_1, 25 | input wire [7:0] data_2, 26 | input wire [7:0] data_3, 27 | input wire [7:0] data_4, 28 | input wire [7:0] data_5, 29 | input wire [2:0] select, 30 | 31 | output reg [7:0] data_out 32 | ); 33 | 34 | //******************************************************** 35 | //Multiplexors 36 | //******************************************************** 37 | always @(select, data_0, data_1, data_2, data_3, data_4, data_5) 38 | begin 39 | case(select) 40 | 0: data_out <= data_1; 41 | 1: data_out <= data_2; 42 | 2: data_out <= data_3; 43 | 3: data_out <= data_4; 44 | 4: data_out <= data_5; 45 | 5: data_out <= data_0; 46 | default: data_out <= 8'bx; 47 | endcase 48 | end 49 | endmodule 50 | -------------------------------------------------------------------------------- /source/output_decoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:21:58 05/09/2012 7 | // Design Name: 8 | // Module Name: output_decoder 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module output_decoder( 22 | input wire clock, 23 | input wire valid_in, 24 | input wire [5:0] data_in, 25 | 26 | output reg valid_out, 27 | output reg [7:0] data_out 28 | ); 29 | //16 - 0,17,34,51,68,85,102,119,136,153,170,187,204,221,238,255 30 | // 31 | //6 - 0,37,74,111,148,185,222,255 32 | // 33 | 34 | initial 35 | begin 36 | data_out <= 8'b0; 37 | valid_out <= 1'b0; 38 | end 39 | 40 | always @(posedge clock) 41 | begin 42 | 43 | valid_out <= valid_in; 44 | 45 | case (data_in) 46 | 0: data_out <= 8'd0; 47 | 1: data_out <= 8'd0; 48 | 2: data_out <= 8'd0; 49 | 3: data_out <= 8'd0; 50 | 51 | 4: data_out <= 8'd17; 52 | 5: data_out <= 8'd17; 53 | 6: data_out <= 8'd17; 54 | 7: data_out <= 8'd17; 55 | 56 | 8: data_out <= 8'd34; 57 | 9: data_out <= 8'd34; 58 | 10: data_out <= 8'd34; 59 | 11: data_out <= 8'd34; 60 | 61 | 12: data_out <= 8'd51; 62 | 13: data_out <= 8'd51; 63 | 14: data_out <= 8'd51; 64 | 15: data_out <= 8'd51; 65 | 66 | 16: data_out <= 8'd68; 67 | 17: data_out <= 8'd68; 68 | 18: data_out <= 8'd68; 69 | 19: data_out <= 8'd68; 70 | 71 | 20: data_out <= 8'd85; 72 | 21: data_out <= 8'd85; 73 | 22: data_out <= 8'd85; 74 | 23: data_out <= 8'd85; 75 | 76 | 24: data_out <= 8'd102; 77 | 25: data_out <= 8'd102; 78 | 26: data_out <= 8'd102; 79 | 27: data_out <= 8'd102; 80 | 81 | 28: data_out <= 8'd119; 82 | 29: data_out <= 8'd119; 83 | 30: data_out <= 8'd119; 84 | 31: data_out <= 8'd119; 85 | 86 | 32: data_out <= 8'd136; 87 | 33: data_out <= 8'd136; 88 | 34: data_out <= 8'd136; 89 | 35: data_out <= 8'd136; 90 | 91 | 36: data_out <= 8'd153; 92 | 37: data_out <= 8'd153; 93 | 38: data_out <= 8'd153; 94 | 39: data_out <= 8'd153; 95 | 96 | 40: data_out <= 8'd170; 97 | 41: data_out <= 8'd170; 98 | 42: data_out <= 8'd170; 99 | 43: data_out <= 8'd170; 100 | 101 | 44: data_out <= 8'd187; 102 | 45: data_out <= 8'd187; 103 | 46: data_out <= 8'd187; 104 | 47: data_out <= 8'd187; 105 | 106 | 48: data_out <= 8'd204; 107 | 49: data_out <= 8'd204; 108 | 50: data_out <= 8'd204; 109 | 51: data_out <= 8'd204; 110 | 111 | 52: data_out <= 8'd221; 112 | 53: data_out <= 8'd221; 113 | 54: data_out <= 8'd221; 114 | 55: data_out <= 8'd221; 115 | 116 | 56: data_out <= 8'd238; 117 | 57: data_out <= 8'd238; 118 | 58: data_out <= 8'd238; 119 | 59: data_out <= 8'd238; 120 | 121 | 60: data_out <= 8'd255; 122 | 61: data_out <= 8'd255; 123 | 62: data_out <= 8'd255; 124 | 63: data_out <= 8'd255; 125 | endcase 126 | end 127 | endmodule 128 | -------------------------------------------------------------------------------- /source/ram_counters.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 17:04:17 04/18/2012 7 | // Design Name: 8 | // Module Name: ram_counters 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ram_counters( 22 | input wire clock, 23 | input wire reset_n, 24 | input wire read_start, //Pulse high to read output addresses for one line's worth of data 25 | 26 | output wire read_enable, 27 | output reg [9:0] address_left_1, //Output addresses for left image's line buffers 28 | output reg [9:0] address_right_1, //Output addresses for right image's line buffers 29 | output reg [9:0] address_right_2, //Output addresses for right image's line buffers 30 | output reg [9:0] address_right_3, //Output addresses for right image's line buffers 31 | output reg [9:0] address_right_4 //Output addresses for right image's line buffers 32 | ); 33 | 34 | wire [9:0] address_left; 35 | wire [9:0] address_right; 36 | 37 | initial 38 | begin 39 | address_left_1 <= 0; 40 | address_right_1 <= 0; 41 | address_right_2 <= 1; 42 | address_right_3 <= 2; 43 | address_right_4 <= 3; 44 | end 45 | 46 | 47 | //For left image buffering 48 | //Should count from 0 to 643 16 times 49 | left_counter l_count ( 50 | .rea (read_start), 51 | .clock (clock), 52 | .read_enable (read_enable), 53 | .addrb (address_left) 54 | ); 55 | 56 | 57 | //4 sets of buffers for the right image 58 | //These will be used with four stereo processing pipelines 59 | //Each one will need to be offset by one from the last one 60 | //They need to run through each 640 pixel row 16 times, for 16x4=64 disparity levels 61 | //The address_b for each one will need to be changed so that they can access different pixels and calculate four disparity levels at the same time. 62 | 63 | right_counter r_count ( 64 | .rea (read_start), 65 | .clock (clock), 66 | .addrb (address_right) 67 | ); 68 | 69 | //Updates output registers 70 | always @(address_left, address_right, reset_n) 71 | begin 72 | if(~reset_n) 73 | begin 74 | address_left_1 <= 0; 75 | address_right_1 <= 0; 76 | address_right_2 <= 1; 77 | address_right_3 <= 2; 78 | address_right_4 <= 3; 79 | end 80 | else 81 | begin 82 | address_left_1 <= address_left; 83 | address_right_1 <= address_right; 84 | address_right_2 <= address_right+2'b01; 85 | address_right_3 <= address_right+2'b10; 86 | address_right_4 <= address_right+2'b11; 87 | end 88 | end 89 | 90 | endmodule 91 | -------------------------------------------------------------------------------- /source/right_counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:33:16 04/13/2012 7 | // Design Name: 8 | // Module Name: right_counter 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module right_counter( 22 | input wire rea, 23 | input wire clock, 24 | output reg [9:0] addrb 25 | ); 26 | 27 | reg [4:0] cycle; 28 | reg [9:0] count; 29 | reg running; 30 | 31 | initial 32 | begin 33 | cycle <= 0; 34 | count <= 1; 35 | addrb <= 0; 36 | running <= 0; 37 | end 38 | 39 | always @(posedge clock) 40 | begin 41 | //Wait for start signal 42 | if (running == 0) 43 | begin 44 | if (rea == 1) 45 | begin 46 | running <= 1; 47 | end 48 | end 49 | 50 | else 51 | begin 52 | //Output addresses 53 | if (cycle == 16) 54 | begin 55 | cycle <= 0; 56 | count <= 1; 57 | addrb <= 0; 58 | running <= 0; 59 | end 60 | //Reset and return to waiting 61 | else 62 | begin 63 | if (count == 643+cycle*3'b100) 64 | begin 65 | addrb <= count; 66 | cycle <= cycle+1'b1; 67 | count <= (cycle+1'b1)*3'b100; 68 | end 69 | else 70 | begin 71 | addrb <= count; 72 | count <= count+1'b1; 73 | end 74 | end 75 | end 76 | end 77 | endmodule 78 | --------------------------------------------------------------------------------