├── .gitignore ├── .ocamlformat ├── CHANGES.md ├── CONTRIBUTING.md ├── LICENSE.md ├── Makefile ├── README.md ├── bin ├── convert.ml ├── convert.mli └── dune ├── dune ├── dune-project ├── hardcaml_of_verilog.opam ├── port_verilog ├── dune ├── hardcaml_port_verilog.ml ├── port_verilog.ml └── port_verilog.mli ├── src ├── circuit_bus_map.ml ├── circuit_bus_map.mli ├── circuit_to_json.ml ├── circuit_to_json.mli ├── dune ├── hardcaml_of_verilog.ml ├── lvt.ml ├── lvt.mli ├── netlist.ml ├── netlist.mli ├── ocaml_module.ml ├── ocaml_module.mli ├── pass.ml ├── pass.mli ├── synthesize.ml ├── synthesize.mli ├── techlib.ml ├── techlib.mli ├── verilog_circuit.ml ├── verilog_circuit.mli ├── verilog_design.ml ├── verilog_design.mli ├── with_interface.ml ├── with_interface.mli ├── yosys_netlist.ml └── yosys_netlist.mli └── test ├── apps ├── mram.ml ├── mram.mli ├── sat_cells.ml.unused ├── wrram.ml └── wrram.mli ├── examples ├── picorv32 │ ├── dune │ ├── picorv32.sexp │ ├── picorv32.v │ ├── test.ml │ └── test.mli └── simple_adder │ ├── carry_save_adder.sexp │ ├── dune │ ├── full_adder.v │ ├── simple_adder.sexp │ ├── simple_adder.v │ ├── simple_adder_16.sexp │ ├── simple_adder_8.sexp │ ├── test.ml │ └── test.mli ├── lib ├── dune ├── hardcaml_of_verilog_test.ml ├── test_circuit.ml ├── test_circuit.mli ├── test_circuit_to_json.ml ├── test_circuit_to_json.mli ├── test_interface.ml ├── test_interface.mli ├── test_json.ml ├── test_json.mli ├── test_synthesize.ml ├── test_synthesize.mli ├── test_verilog_design.ml └── test_verilog_design.mli └── verilog ├── adff.v ├── bbox.v ├── counter.v ├── mem.v └── simlib_chk.v /.gitignore: -------------------------------------------------------------------------------- 1 | _build 2 | *.install 3 | *.merlin 4 | _opam 5 | 6 | -------------------------------------------------------------------------------- /.ocamlformat: -------------------------------------------------------------------------------- 1 | profile=janestreet 2 | -------------------------------------------------------------------------------- /CHANGES.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/CHANGES.md -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/CONTRIBUTING.md -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/LICENSE.md -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/Makefile -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/README.md -------------------------------------------------------------------------------- /bin/convert.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/bin/convert.ml -------------------------------------------------------------------------------- /bin/convert.mli: -------------------------------------------------------------------------------- 1 | (*_ This signature is deliberately empty. *) 2 | -------------------------------------------------------------------------------- /bin/dune: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/bin/dune -------------------------------------------------------------------------------- /dune: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /dune-project: -------------------------------------------------------------------------------- 1 | (lang dune 3.17) 2 | -------------------------------------------------------------------------------- /hardcaml_of_verilog.opam: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/hardcaml_of_verilog.opam -------------------------------------------------------------------------------- /port_verilog/dune: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/port_verilog/dune -------------------------------------------------------------------------------- /port_verilog/hardcaml_port_verilog.ml: -------------------------------------------------------------------------------- 1 | include Port_verilog 2 | -------------------------------------------------------------------------------- /port_verilog/port_verilog.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/port_verilog/port_verilog.ml -------------------------------------------------------------------------------- /port_verilog/port_verilog.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/port_verilog/port_verilog.mli -------------------------------------------------------------------------------- /src/circuit_bus_map.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/circuit_bus_map.ml -------------------------------------------------------------------------------- /src/circuit_bus_map.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/circuit_bus_map.mli -------------------------------------------------------------------------------- /src/circuit_to_json.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/circuit_to_json.ml -------------------------------------------------------------------------------- /src/circuit_to_json.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/circuit_to_json.mli -------------------------------------------------------------------------------- /src/dune: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/dune -------------------------------------------------------------------------------- /src/hardcaml_of_verilog.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/hardcaml_of_verilog.ml -------------------------------------------------------------------------------- /src/lvt.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/lvt.ml -------------------------------------------------------------------------------- /src/lvt.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/lvt.mli -------------------------------------------------------------------------------- /src/netlist.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/netlist.ml -------------------------------------------------------------------------------- /src/netlist.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/netlist.mli -------------------------------------------------------------------------------- /src/ocaml_module.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/ocaml_module.ml -------------------------------------------------------------------------------- /src/ocaml_module.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/ocaml_module.mli -------------------------------------------------------------------------------- /src/pass.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/pass.ml -------------------------------------------------------------------------------- /src/pass.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/pass.mli -------------------------------------------------------------------------------- /src/synthesize.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/synthesize.ml -------------------------------------------------------------------------------- /src/synthesize.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/synthesize.mli -------------------------------------------------------------------------------- /src/techlib.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/techlib.ml -------------------------------------------------------------------------------- /src/techlib.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/techlib.mli -------------------------------------------------------------------------------- /src/verilog_circuit.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/verilog_circuit.ml -------------------------------------------------------------------------------- /src/verilog_circuit.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/verilog_circuit.mli -------------------------------------------------------------------------------- /src/verilog_design.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/verilog_design.ml -------------------------------------------------------------------------------- /src/verilog_design.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/verilog_design.mli -------------------------------------------------------------------------------- /src/with_interface.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/with_interface.ml -------------------------------------------------------------------------------- /src/with_interface.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/with_interface.mli -------------------------------------------------------------------------------- /src/yosys_netlist.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/yosys_netlist.ml -------------------------------------------------------------------------------- /src/yosys_netlist.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/src/yosys_netlist.mli -------------------------------------------------------------------------------- /test/apps/mram.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/apps/mram.ml -------------------------------------------------------------------------------- /test/apps/mram.mli: -------------------------------------------------------------------------------- 1 | (*_ This signature is deliberately empty. *) 2 | -------------------------------------------------------------------------------- /test/apps/sat_cells.ml.unused: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/apps/sat_cells.ml.unused -------------------------------------------------------------------------------- /test/apps/wrram.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/apps/wrram.ml -------------------------------------------------------------------------------- /test/apps/wrram.mli: -------------------------------------------------------------------------------- 1 | (*_ This signature is deliberately empty. *) 2 | -------------------------------------------------------------------------------- /test/examples/picorv32/dune: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/picorv32/dune -------------------------------------------------------------------------------- /test/examples/picorv32/picorv32.sexp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/picorv32/picorv32.sexp -------------------------------------------------------------------------------- /test/examples/picorv32/picorv32.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/picorv32/picorv32.v -------------------------------------------------------------------------------- /test/examples/picorv32/test.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/picorv32/test.ml -------------------------------------------------------------------------------- /test/examples/picorv32/test.mli: -------------------------------------------------------------------------------- 1 | (*_ This signature is deliberately empty. *) 2 | -------------------------------------------------------------------------------- /test/examples/simple_adder/carry_save_adder.sexp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/simple_adder/carry_save_adder.sexp -------------------------------------------------------------------------------- /test/examples/simple_adder/dune: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/simple_adder/dune -------------------------------------------------------------------------------- /test/examples/simple_adder/full_adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/simple_adder/full_adder.v -------------------------------------------------------------------------------- /test/examples/simple_adder/simple_adder.sexp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/simple_adder/simple_adder.sexp -------------------------------------------------------------------------------- /test/examples/simple_adder/simple_adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/simple_adder/simple_adder.v -------------------------------------------------------------------------------- /test/examples/simple_adder/simple_adder_16.sexp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/simple_adder/simple_adder_16.sexp -------------------------------------------------------------------------------- /test/examples/simple_adder/simple_adder_8.sexp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/simple_adder/simple_adder_8.sexp -------------------------------------------------------------------------------- /test/examples/simple_adder/test.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/examples/simple_adder/test.ml -------------------------------------------------------------------------------- /test/examples/simple_adder/test.mli: -------------------------------------------------------------------------------- 1 | (*_ This signature is deliberately empty. *) 2 | -------------------------------------------------------------------------------- /test/lib/dune: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/lib/dune -------------------------------------------------------------------------------- /test/lib/hardcaml_of_verilog_test.ml: -------------------------------------------------------------------------------- 1 | (*_ Nothing to export. *) 2 | -------------------------------------------------------------------------------- /test/lib/test_circuit.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/lib/test_circuit.ml -------------------------------------------------------------------------------- /test/lib/test_circuit.mli: -------------------------------------------------------------------------------- 1 | (*_ This signature is deliberately empty. *) 2 | -------------------------------------------------------------------------------- /test/lib/test_circuit_to_json.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/lib/test_circuit_to_json.ml -------------------------------------------------------------------------------- /test/lib/test_circuit_to_json.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/lib/test_circuit_to_json.mli -------------------------------------------------------------------------------- /test/lib/test_interface.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/lib/test_interface.ml -------------------------------------------------------------------------------- /test/lib/test_interface.mli: -------------------------------------------------------------------------------- 1 | (*_ This signature is deliberately empty. *) 2 | -------------------------------------------------------------------------------- /test/lib/test_json.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/lib/test_json.ml -------------------------------------------------------------------------------- /test/lib/test_json.mli: -------------------------------------------------------------------------------- 1 | (*_ This signature is deliberately empty. *) 2 | -------------------------------------------------------------------------------- /test/lib/test_synthesize.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/lib/test_synthesize.ml -------------------------------------------------------------------------------- /test/lib/test_synthesize.mli: -------------------------------------------------------------------------------- 1 | (*_ This signature is deliberately empty. *) 2 | -------------------------------------------------------------------------------- /test/lib/test_verilog_design.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/lib/test_verilog_design.ml -------------------------------------------------------------------------------- /test/lib/test_verilog_design.mli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/lib/test_verilog_design.mli -------------------------------------------------------------------------------- /test/verilog/adff.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/verilog/adff.v -------------------------------------------------------------------------------- /test/verilog/bbox.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/verilog/bbox.v -------------------------------------------------------------------------------- /test/verilog/counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/verilog/counter.v -------------------------------------------------------------------------------- /test/verilog/mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/verilog/mem.v -------------------------------------------------------------------------------- /test/verilog/simlib_chk.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/janestreet/hardcaml_of_verilog/HEAD/test/verilog/simlib_chk.v --------------------------------------------------------------------------------