├── .cargo └── config ├── .gdbinit ├── .gitignore ├── .travis.yml ├── Cargo.toml ├── LICENSE-APACHE ├── LICENSE-MIT ├── README.md ├── ci ├── env.sh ├── install.sh └── script.sh ├── common.ld ├── cortex-m3.json ├── cortex-m3.ld ├── src ├── asm.rs ├── bb │ ├── gpio.rs │ ├── mod.rs │ ├── rcc.rs │ └── tim.rs ├── bin │ ├── 00-empty.rs │ ├── 01-led.rs │ ├── 02-busy-timer.rs │ ├── 03-timer-interrupt.rs │ ├── 04-button.rs │ └── 05-init-data.rs ├── exception.rs ├── interrupt.rs ├── lang_items.rs ├── lib.rs ├── register │ ├── gpio │ │ ├── bsrr.rs │ │ ├── crh.rs │ │ └── mod.rs │ ├── itm │ │ ├── mod.rs │ │ ├── port.rs │ │ ├── tcr.rs │ │ └── ter.rs │ ├── mod.rs │ ├── nvic │ │ ├── iser1.rs │ │ └── mod.rs │ ├── rcc │ │ ├── apb1enr.rs │ │ ├── apb2enr.rs │ │ └── mod.rs │ └── tim │ │ ├── arr.rs │ │ ├── cr1.rs │ │ ├── dier.rs │ │ ├── egr.rs │ │ ├── mod.rs │ │ └── psc.rs └── rt.rs └── stm32f100.ld /.cargo/config: -------------------------------------------------------------------------------- 1 | [build] 2 | target = "cortex-m3" -------------------------------------------------------------------------------- /.gdbinit: -------------------------------------------------------------------------------- 1 | tar ext :3333 2 | load 3 | step 4 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.pdf 2 | *.rs.bk 3 | Cargo.lock 4 | sysroot 5 | target 6 | -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | language: generic 2 | services: docker 3 | sudo: required 4 | 5 | script: 6 | - bash ci/script.sh 7 | 8 | branches: 9 | only: 10 | - auto 11 | - try 12 | 13 | notifications: 14 | email: 15 | on_success: never 16 | webhooks: https://homu.herokuapp.com/travis 17 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | authors = ["Jorge Aparicio "] 3 | license = "MIT/Apache-2.0" 4 | name = "cu" 5 | version = "0.1.0" 6 | 7 | [dependencies] 8 | rlibc = "1.0.0" 9 | rustc_builtins = { git = "https://github.com/japaric/rustc-builtins" } 10 | 11 | [profile.dev] 12 | panic = "abort" 13 | 14 | [profile.release] 15 | lto = true 16 | panic = "abort" 17 | -------------------------------------------------------------------------------- /LICENSE-APACHE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /LICENSE-MIT: -------------------------------------------------------------------------------- 1 | Copyright (c) 2016 Jorge Aparicio 2 | 3 | Permission is hereby granted, free of charge, to any 4 | person obtaining a copy of this software and associated 5 | documentation files (the "Software"), to deal in the 6 | Software without restriction, including without 7 | limitation the rights to use, copy, modify, merge, 8 | publish, distribute, sublicense, and/or sell copies of 9 | the Software, and to permit persons to whom the Software 10 | is furnished to do so, subject to the following 11 | conditions: 12 | 13 | The above copyright notice and this permission notice 14 | shall be included in all copies or substantial portions 15 | of the Software. 16 | 17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF 18 | ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 19 | TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 20 | PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT 21 | SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 22 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR 24 | IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 | DEALINGS IN THE SOFTWARE. 26 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | [![Build Status][status]](https://travis-ci.org/japaric/cu) 2 | 3 | [status]: https://travis-ci.org/japaric/cu.svg?branch=master 4 | 5 | # `Copper` 6 | 7 | > Testing ground for the [Copper book](http://japaric.github.io/copper/). 8 | 9 | ## License 10 | 11 | Licensed under either of 12 | 13 | - Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or 14 | http://www.apache.org/licenses/LICENSE-2.0); 15 | - MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT). 16 | 17 | at your option. 18 | 19 | ### Contribution 20 | 21 | Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the 22 | work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any 23 | additional terms or conditions. 24 | -------------------------------------------------------------------------------- /ci/env.sh: -------------------------------------------------------------------------------- 1 | export PATH="$HOME/.cargo/bin:$PATH" 2 | -------------------------------------------------------------------------------- /ci/install.sh: -------------------------------------------------------------------------------- 1 | set -ex 2 | 3 | . $(dirname $0)/env.sh 4 | 5 | main() { 6 | if [[ ${INSIDE_DOCKER_CONTAINER:-n} == y ]]; then 7 | rustup default nightly 8 | fi 9 | } 10 | 11 | main 12 | -------------------------------------------------------------------------------- /ci/script.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | . $(dirname $0)/env.sh 6 | 7 | build() { 8 | xargo build --release --verbose 9 | } 10 | 11 | inspect() { 12 | local elfs=$(find target/cortex-m3/release -maxdepth 1 -type f -executable | sort) 13 | 14 | for elf in $elfs; do 15 | arm-none-eabi-readelf -h $elf | grep "Entry point address" | grep -v 0x0$; 16 | done 17 | arm-none-eabi-size $elfs 18 | arm-none-eabi-objdump -Cd -j .vector_table -j .text $elfs 19 | } 20 | 21 | main() { 22 | if [[ ${INSIDE_DOCKER_CONTAINER:-n} == n ]]; then 23 | local gid=$(id -g) \ 24 | id=rust \ 25 | uid=$(id -u) 26 | 27 | docker run \ 28 | --entrypoint bash \ 29 | -e INSIDE_DOCKER_CONTAINER=y \ 30 | -v $(pwd):/mnt \ 31 | japaric/copper \ 32 | -c " 33 | set -eux 34 | usermod -u $uid $id 35 | groupmod -g $gid $id 36 | chgrp -R $id /home/$id 37 | HOME=/home/$id USER=$id su -c 'cd /mnt && bash ci/install.sh && bash ci/script.sh' $id 38 | " 39 | else 40 | build 41 | inspect 42 | fi 43 | } 44 | 45 | main 46 | -------------------------------------------------------------------------------- /common.ld: -------------------------------------------------------------------------------- 1 | __DATA_LOAD = LOADADDR(.data); 2 | 3 | SECTIONS 4 | { 5 | .vector_table ORIGIN(FLASH) : 6 | { 7 | LONG(ORIGIN(RAM) + LENGTH(RAM)) 8 | link_reset_start = .; 9 | KEEP(*(.reset)) 10 | link_reset_end = .; 11 | link_exceptions_start = .; 12 | KEEP(*(.exceptions)) 13 | link_exceptions_end = .; 14 | link_interrupts_start = .; 15 | KEEP(*(.interrupts)) 16 | link_interrupts_end = .; 17 | } > FLASH 18 | 19 | .text : 20 | { 21 | *(.text*) 22 | } > FLASH 23 | 24 | .data : ALIGN(4) 25 | { 26 | __DATA_START = .; 27 | *(.data*) 28 | . = ALIGN(4); 29 | __DATA_END = .; 30 | } > RAM AT > FLASH 31 | 32 | /DISCARD/ : 33 | { 34 | *(.ARM.exidx*) 35 | *(.note.gnu.build-id*) 36 | } 37 | } 38 | 39 | /* Sanity checks */ 40 | ASSERT(link_reset_start - ORIGIN(FLASH) == 4, "reset not where expected"); 41 | ASSERT(link_exceptions_start - ORIGIN(FLASH) == 8, "exceptions not where expected"); 42 | ASSERT(link_interrupts_start - ORIGIN(FLASH) == 0x40, "interrupts not where expected"); 43 | ASSERT(link_reset_start < link_reset_end, "reset not linked in"); 44 | ASSERT(link_exceptions_start < link_exceptions_end, "exceptions not linked in"); 45 | ASSERT(link_interrupts_start < link_interrupts_end, "interrupts not linked in"); 46 | -------------------------------------------------------------------------------- /cortex-m3.json: -------------------------------------------------------------------------------- 1 | { 2 | "arch": "arm", 3 | "cpu": "cortex-m3", 4 | "data-layout": "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64", 5 | "executables": true, 6 | "linker": "arm-none-eabi-gcc", 7 | "llvm-target": "thumbv7m-none-eabi", 8 | "no-compiler-rt": true, 9 | "os": "none", 10 | "pre-link-args": ["-Tstm32f100.ld", "-nostartfiles"], 11 | "relocation-model": "static", 12 | "target-endian": "little", 13 | "target-pointer-width": "32" 14 | } 15 | -------------------------------------------------------------------------------- /cortex-m3.ld: -------------------------------------------------------------------------------- 1 | PROVIDE(__nmi = __default_handler); 2 | PROVIDE(__hard_fault = __default_handler); 3 | -------------------------------------------------------------------------------- /src/asm.rs: -------------------------------------------------------------------------------- 1 | //! Assembly 2 | 3 | /// BreaKPoinT 4 | pub fn bkpt() { 5 | unsafe { 6 | asm!("bkpt" :::: "volatile"); 7 | } 8 | } 9 | 10 | /// Wait For Interrupt 11 | pub fn wfi() { 12 | unsafe { 13 | asm!("wfi" :::: "volatile"); 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /src/bb/gpio.rs: -------------------------------------------------------------------------------- 1 | //! General Purpose Input/Output 2 | 3 | use bb::{Ro, Rw}; 4 | 5 | /// Register block 6 | #[repr(C)] 7 | pub struct Block { 8 | crl: [u32; 32], 9 | crh: [u32; 32], 10 | /// 0x08 11 | pub idr: [Ro; 32], 12 | /// 0x0C 13 | pub odr: [Rw; 32], 14 | bsrr: [u32; 32], 15 | brr: [u32; 32], 16 | lckr: [u32; 32], 17 | } 18 | -------------------------------------------------------------------------------- /src/bb/mod.rs: -------------------------------------------------------------------------------- 1 | //! Bit-banded peripherals 2 | 3 | use core::ptr; 4 | 5 | pub mod gpio; 6 | pub mod rcc; 7 | pub mod tim; 8 | 9 | extern "C" { 10 | #[link_name = "__BB_GPIOA"] pub static GPIOA: gpio::Block; 11 | #[link_name = "__BB_GPIOC"] pub static GPIOC: gpio::Block; 12 | #[link_name = "__BB_RCC"] pub static RCC: rcc::Block; 13 | #[link_name = "__BB_TIM7"] pub static TIM7: tim::Block; 14 | } 15 | 16 | /// Bit-banded bit with read-only access 17 | #[repr(C)] 18 | pub struct Ro(u32); 19 | 20 | impl Ro { 21 | /// Checks if the bit is set 22 | pub fn is_set(&self) -> bool { 23 | unsafe { ptr::read_volatile(&self.0) != 0 } 24 | } 25 | } 26 | 27 | /// Bit-banded bit with read/write access 28 | #[repr(C)] 29 | pub struct Rw(u32); 30 | 31 | impl Rw { 32 | /// Clears the bit 33 | pub fn clear(&self) { 34 | unsafe { 35 | ptr::write_volatile(&self.0 as *const _ as *mut _, 0); 36 | } 37 | } 38 | 39 | /// Checks if the bit is set 40 | pub fn is_set(&self) -> bool { 41 | unsafe { ptr::read_volatile(&self.0) != 0 } 42 | } 43 | 44 | /// Sets the bit 45 | pub fn set(&self) { 46 | unsafe { 47 | ptr::write_volatile(&self.0 as *const _ as *mut _, 1); 48 | } 49 | } 50 | } 51 | 52 | // TODO bit-band routine for RAM? 53 | -------------------------------------------------------------------------------- /src/bb/rcc.rs: -------------------------------------------------------------------------------- 1 | //! Register and Clock Control 2 | 3 | use bb::Rw; 4 | 5 | /// Register block 6 | #[repr(C)] 7 | pub struct Block { 8 | cr: [u32; 32], 9 | cfgr: [u32; 32], 10 | cir: [u32; 32], 11 | apb2rstr: [u32; 32], 12 | apb1rstr: [u32; 32], 13 | ahbenr: [u32; 32], 14 | /// 0x18 15 | pub apb2enr: Apb2enr, 16 | apb1enr: [u32; 32], 17 | bdcr: [u32; 32], 18 | csr: [u32; 32], 19 | cfgr2: [u32; 32], 20 | } 21 | 22 | /// APB2 peripheral clock enable 23 | #[repr(C)] 24 | pub struct Apb2enr { 25 | afioen: u32, 26 | _0: u32, 27 | iopaen: u32, 28 | iopben: u32, 29 | /// I/O port C clock enable 30 | pub iopcen: Rw, 31 | iopden: u32, 32 | iopeen: u32, 33 | iopfen: u32, 34 | iopgen: u32, 35 | adc1en: u32, 36 | _1: u32, 37 | tim1en: u32, 38 | spi1en: u32, 39 | _2: u32, 40 | usart1en: u32, 41 | _3: u32, 42 | tim15en: u32, 43 | tim16e: u32, 44 | tim17e: u32, 45 | _4: [u32; 13], 46 | } 47 | -------------------------------------------------------------------------------- /src/bb/tim.rs: -------------------------------------------------------------------------------- 1 | //! Basic timers 2 | 3 | use bb::Rw; 4 | 5 | /// Register block 6 | #[repr(C)] 7 | pub struct Block { 8 | cr1: [u32; 32], 9 | cr2: [u32; 32], 10 | _0: [u32; 32], 11 | dier: [u32; 32], 12 | /// 0x10 13 | pub sr: Sr, 14 | egr: [u32; 32], 15 | _1: [u32; 3 * 32], 16 | cnt: [u32; 32], 17 | psc: [u32; 32], 18 | arr: [u32; 32], 19 | } 20 | 21 | /// Status register 22 | #[repr(C)] 23 | pub struct Sr { 24 | /// Update interrupt flag 25 | pub uif: Rw, 26 | _0: [u32; 31], 27 | } 28 | -------------------------------------------------------------------------------- /src/bin/00-empty.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | extern crate cu; 5 | 6 | #[no_mangle] 7 | pub extern "C" fn start() -> ! { 8 | loop {} 9 | } 10 | -------------------------------------------------------------------------------- /src/bin/01-led.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | extern crate cu; 5 | 6 | use cu::register; 7 | 8 | #[no_mangle] 9 | pub extern "C" fn start() -> ! { 10 | unsafe { 11 | let ref mut rcc = register::RCC; 12 | let ref mut gpioc = register::GPIOC; 13 | 14 | // Enable Port C 15 | rcc.apb2enr.write(*register::rcc::apb2enr::DEFAULT.iopcen(true)); 16 | 17 | // Set PC8 as digital output 18 | gpioc.crh.write(*register::gpio::crh::DEFAULT.cnf(8, 0b00).mode(8, 0b10)); 19 | 20 | // Set PC8 high 21 | gpioc.bsrr.write(*register::gpio::bsrr::DEFAULT.set(8)); 22 | 23 | loop {} 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /src/bin/02-busy-timer.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | extern crate cu; 5 | 6 | use cu::{bb, register}; 7 | 8 | #[no_mangle] 9 | pub extern "C" fn start() -> ! { 10 | unsafe { 11 | setup(); 12 | } 13 | 14 | loop_(); 15 | } 16 | 17 | unsafe fn setup() { 18 | let ref mut gpioc = register::GPIOC; 19 | let ref mut rcc = register::RCC; 20 | let ref mut tim7 = register::TIM7; 21 | 22 | // Enable TIM7 and GPIOC 23 | rcc.apb1enr.write(*register::rcc::apb1enr::DEFAULT.tim7en(true)); 24 | rcc.apb2enr.write(*register::rcc::apb2enr::DEFAULT.iopcen(true)); 25 | 26 | // Set PC8 as digital output 27 | gpioc.crh.write(*register::gpio::crh::DEFAULT.cnf(8, 0b00).mode(8, 0b10)); 28 | 29 | // Configure TIM7 for 1 Hz timeouts 30 | tim7.psc.write(999); 31 | tim7.arr.write(8_000); 32 | tim7.cr1.write(*register::tim::cr1::DEFAULT.cen(true)); 33 | } 34 | 35 | fn loop_() -> ! { 36 | let ref uif = bb::TIM7.sr.uif; 37 | let ref pc8 = bb::GPIOC.odr[8]; 38 | 39 | loop { 40 | if uif.is_set() { 41 | uif.clear(); 42 | 43 | if pc8.is_set() { 44 | pc8.clear() 45 | } else { 46 | pc8.set() 47 | } 48 | } 49 | } 50 | } 51 | -------------------------------------------------------------------------------- /src/bin/03-timer-interrupt.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | extern crate cu; 5 | 6 | use cu::{asm, bb, register}; 7 | 8 | #[no_mangle] 9 | pub extern "C" fn start() -> ! { 10 | unsafe { 11 | setup(); 12 | } 13 | 14 | loop_(); 15 | } 16 | 17 | unsafe fn setup() { 18 | let ref mut gpioc = register::GPIOC; 19 | let ref mut nvic = register::NVIC; 20 | let ref mut rcc = register::RCC; 21 | let ref mut tim7 = register::TIM7; 22 | 23 | // Enable TIM7 and GPIOC 24 | rcc.apb1enr.write(*register::rcc::apb1enr::DEFAULT.tim7en(true)); 25 | rcc.apb2enr.write(*register::rcc::apb2enr::DEFAULT.iopcen(true)); 26 | 27 | // Set PC8 as digital output 28 | gpioc.crh.write(*register::gpio::crh::DEFAULT.cnf(8, 0b00).mode(8, 0b10)); 29 | 30 | // Configure TIM7 interrupt 31 | tim7.dier.write(*register::tim::dier::DEFAULT.uie(true)); 32 | nvic.iser1.write(*register::nvic::iser1::DEFAULT.setena(55)); 33 | 34 | // Configure TIM7 for 1 Hz timeouts 35 | tim7.psc.write(999); 36 | tim7.arr.write(8_000); 37 | tim7.cr1.write(*register::tim::cr1::DEFAULT.cen(true)); 38 | } 39 | 40 | fn loop_() -> ! { 41 | let ref pc8 = bb::GPIOC.odr[8]; 42 | 43 | loop { 44 | asm::wfi(); 45 | pc8.set(); 46 | asm::wfi(); 47 | pc8.clear(); 48 | } 49 | } 50 | 51 | #[no_mangle] 52 | pub unsafe extern "C" fn __tim7() { 53 | let ref uif = bb::TIM7.sr.uif; 54 | 55 | uif.clear(); 56 | } 57 | -------------------------------------------------------------------------------- /src/bin/04-button.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | extern crate cu; 5 | 6 | use cu::{bb, register}; 7 | 8 | #[no_mangle] 9 | pub extern "C" fn start() -> ! { 10 | unsafe { 11 | setup(); 12 | } 13 | loop_(); 14 | } 15 | 16 | unsafe fn setup() { 17 | let ref mut rcc = register::RCC; 18 | let ref mut gpioc = register::GPIOC; 19 | 20 | // Enable Port A and Port C 21 | rcc.apb2enr.write(*register::rcc::apb2enr::DEFAULT.iopaen(true).iopcen(true)); 22 | 23 | // Configure PC8 as digital output 24 | gpioc.crh.write(*register::gpio::crh::DEFAULT.cnf(8, 0b00).mode(8, 0b10)); 25 | } 26 | 27 | fn loop_() -> ! { 28 | let ref pa0 = bb::GPIOA.idr[0]; 29 | let ref pc8 = bb::GPIOC.odr[8]; 30 | 31 | loop { 32 | if pa0.is_set() { 33 | if pc8.is_set() { 34 | pc8.clear(); 35 | } else { 36 | pc8.set(); 37 | } 38 | } 39 | } 40 | } 41 | -------------------------------------------------------------------------------- /src/bin/05-init-data.rs: -------------------------------------------------------------------------------- 1 | #![no_main] 2 | #![no_std] 3 | 4 | extern crate cu; 5 | 6 | #[no_mangle] 7 | pub extern "C" fn start() -> ! { 8 | unsafe { 9 | cu::rt::init_data(); 10 | } 11 | 12 | loop {} 13 | } 14 | -------------------------------------------------------------------------------- /src/exception.rs: -------------------------------------------------------------------------------- 1 | //! Exceptions 2 | 3 | use asm; 4 | 5 | extern "C" { 6 | /// Reset 7 | pub fn start() -> !; 8 | /// Non-maskable interrupt 9 | pub fn __nmi(); 10 | /// Hard fault 11 | pub fn __hard_fault(); 12 | } 13 | 14 | /// Default exception handler 15 | #[no_mangle] 16 | pub unsafe extern "C" fn __default_handler() { 17 | asm::bkpt(); 18 | } 19 | 20 | /// Program entry point: The reset function. 21 | #[link_section = ".reset"] 22 | #[no_mangle] 23 | pub static __RESET: Option !> = Some(start); 24 | 25 | /// Cortex-M processor exceptions 26 | #[link_section = ".exceptions"] 27 | #[no_mangle] 28 | pub static __EXCEPTIONS: [Option; 14] = [None, 29 | None, 30 | None, 31 | None, 32 | None, 33 | None, 34 | None, 35 | None, 36 | None, 37 | None, 38 | None, 39 | None, 40 | None, 41 | None]; 42 | -------------------------------------------------------------------------------- /src/interrupt.rs: -------------------------------------------------------------------------------- 1 | //! Interrupts 2 | 3 | extern "C" { 4 | pub fn __tim7(); 5 | } 6 | 7 | /// STM32F100 interrupts 8 | #[link_section = ".interrupts"] 9 | #[no_mangle] 10 | pub static __INTERRUPTS: [Option; 56] = [None, 11 | None, 12 | None, 13 | None, 14 | None, 15 | None, 16 | None, 17 | None, 18 | None, 19 | None, 20 | None, 21 | None, 22 | None, 23 | None, 24 | None, 25 | None, 26 | None, 27 | None, 28 | None, 29 | None, 30 | None, 31 | None, 32 | None, 33 | None, 34 | None, 35 | None, 36 | None, 37 | None, 38 | None, 39 | None, 40 | None, 41 | None, 42 | None, 43 | None, 44 | None, 45 | None, 46 | None, 47 | None, 48 | None, 49 | None, 50 | None, 51 | None, 52 | None, 53 | None, 54 | None, 55 | None, 56 | None, 57 | None, 58 | None, 59 | None, 60 | None, 61 | None, 62 | None, 63 | None, 64 | None, 65 | Some(__tim7)]; 66 | -------------------------------------------------------------------------------- /src/lang_items.rs: -------------------------------------------------------------------------------- 1 | #[lang = "eh_personality"] 2 | fn eh_personality() {} 3 | 4 | #[lang = "panic_fmt"] 5 | extern fn panic_fmt() {} 6 | -------------------------------------------------------------------------------- /src/lib.rs: -------------------------------------------------------------------------------- 1 | //! STM32VLDISCOVERY 2 | 3 | #![feature(asm)] 4 | #![feature(lang_items)] 5 | 6 | #![allow(dead_code)] 7 | #![deny(missing_docs)] 8 | #![deny(warnings)] 9 | 10 | #![no_std] 11 | 12 | extern crate rustc_builtins; 13 | extern crate rlibc; 14 | 15 | pub mod asm; 16 | pub mod bb; 17 | pub mod exception; 18 | pub mod interrupt; 19 | pub mod register; 20 | pub mod rt; 21 | 22 | mod lang_items; 23 | -------------------------------------------------------------------------------- /src/register/gpio/bsrr.rs: -------------------------------------------------------------------------------- 1 | //! Port bit set/reset register 2 | 3 | use rt; 4 | 5 | /// Reset value 6 | pub const DEFAULT: Register = Register(0x0000_0000); 7 | 8 | /// Register 9 | #[derive(Clone, Copy)] 10 | #[repr(C)] 11 | pub struct Register(u32); 12 | 13 | impl Register { 14 | /// Resets `pin` 15 | pub fn reset(&mut self, pin: u32) -> &mut Self { 16 | match pin { 17 | 0...15 => { 18 | let offset = pin + 16; 19 | 20 | self.0 |= 1 << offset; 21 | } 22 | _ => rt::abort(), 23 | } 24 | 25 | self 26 | } 27 | 28 | /// Sets `pin` 29 | pub fn set(&mut self, pin: u32) -> &mut Self { 30 | match pin { 31 | 0...15 => { 32 | let offset = pin; 33 | 34 | self.0 |= 1 << offset; 35 | } 36 | _ => rt::abort(), 37 | } 38 | 39 | self 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /src/register/gpio/crh.rs: -------------------------------------------------------------------------------- 1 | //! Port configuration register high 2 | 3 | use rt; 4 | 5 | /// Reset value 6 | pub const DEFAULT: Register = Register(0x4444_4444); 7 | 8 | /// Register 9 | #[derive(Clone, Copy)] 10 | #[repr(C)] 11 | pub struct Register(u32); 12 | 13 | impl Register { 14 | /// Sets `pin` configuration 15 | pub fn cnf(&mut self, pin: u32, state: u32) -> &mut Self { 16 | match (state, pin) { 17 | (0b00...0b11, 8...15) => { 18 | const MASK: u32 = 0b11; 19 | 20 | let offset = 4 * (pin - 8) + 2; 21 | 22 | self.0 &= !(MASK << offset); 23 | self.0 |= state << offset; 24 | } 25 | _ => rt::abort(), 26 | } 27 | 28 | self 29 | } 30 | 31 | /// Sets `pin` mode 32 | pub fn mode(&mut self, pin: u32, state: u32) -> &mut Self { 33 | match (state, pin) { 34 | (0b00...0b11, 8...15) => { 35 | const MASK: u32 = 0b11; 36 | 37 | let offset = 4 * (pin - 8); 38 | 39 | self.0 &= !(MASK << offset); 40 | self.0 |= state << offset; 41 | } 42 | _ => rt::abort(), 43 | } 44 | 45 | self 46 | } 47 | } 48 | -------------------------------------------------------------------------------- /src/register/gpio/mod.rs: -------------------------------------------------------------------------------- 1 | //! General Purpose I/O 2 | 3 | pub mod bsrr; 4 | pub mod crh; 5 | 6 | use register::{Rw, Wo}; 7 | 8 | /// Register block 9 | #[repr(C)] 10 | pub struct Block { 11 | crl: u32, 12 | /// 0x04 13 | pub crh: Rw, 14 | idr: u32, 15 | odr: u32, 16 | /// 0x10 17 | pub bsrr: Wo, 18 | brr: u32, 19 | lckr: u32, 20 | } 21 | -------------------------------------------------------------------------------- /src/register/itm/mod.rs: -------------------------------------------------------------------------------- 1 | //! Instrumentation Trace Macrocell 2 | 3 | use register::{Rw, Wo}; 4 | 5 | pub mod port; 6 | pub mod ter; 7 | pub mod tcr; 8 | 9 | /// Register block 10 | #[repr(C)] 11 | pub struct Block { 12 | /// 0x0000 13 | pub port: [port::Register; 32], 14 | _0: [u32; 864], 15 | /// 0x0E00 16 | pub ter: Rw, 17 | _1: [u32; 15], 18 | /// 0x0E40 19 | tpr: Rw, 20 | _2: [u32; 15], 21 | /// 0x0E80 22 | pub tcr: Rw, 23 | _3: [u32; 75], 24 | /// 0x0FB0 25 | lar: Wo, 26 | } 27 | -------------------------------------------------------------------------------- /src/register/itm/port.rs: -------------------------------------------------------------------------------- 1 | //! Stimulus port 2 | 3 | use core::ptr; 4 | 5 | /// Register 6 | #[repr(C)] 7 | pub struct Register(u32); 8 | 9 | impl Register { 10 | /// Checks if the stimulus port FIFO is full 11 | pub fn is_full(&self) -> bool { 12 | unsafe { ptr::read_volatile(&self.0) == 0 } 13 | } 14 | 15 | /// Writes a character to the stimulus port FIFO 16 | pub fn write(&mut self, c: u8) { 17 | unsafe { 18 | ptr::write_volatile(&mut self.0 as *mut _ as *mut u8, c); 19 | } 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /src/register/itm/tcr.rs: -------------------------------------------------------------------------------- 1 | //! Trace Control Register 2 | 3 | /// Register 4 | 5 | /// Reset value 6 | pub const DEFAULT: Register = Register(0x0000_0000); 7 | 8 | /// Register 9 | #[derive(Clone, Copy)] 10 | #[repr(C)] 11 | pub struct Register(u32); 12 | 13 | impl Register { 14 | bits! { 15 | itmena: 0, 16 | tsena: 1, 17 | syncena: 2, 18 | dwtena: 3, 19 | swoena: 4, 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /src/register/itm/ter.rs: -------------------------------------------------------------------------------- 1 | //! Trace Enable Register 2 | 3 | use rt; 4 | 5 | /// Reset value 6 | pub const DEFAULT: Register = Register(0x0000_0000); 7 | 8 | /// Register 9 | #[derive(Clone, Copy)] 10 | #[repr(C)] 11 | pub struct Register(u32); 12 | 13 | impl Register { 14 | /// Enables a stimulus `port` 15 | pub fn enable(&mut self, port: u32) -> &mut Self { 16 | match port { 17 | 0...31 => { 18 | let offset = port; 19 | 20 | self.0 |= 1 << offset; 21 | } 22 | _ => rt::abort(), 23 | } 24 | 25 | self 26 | } 27 | } 28 | -------------------------------------------------------------------------------- /src/register/mod.rs: -------------------------------------------------------------------------------- 1 | //! Registers 2 | 3 | use core::ptr; 4 | 5 | macro_rules! bits { 6 | ($($name:ident: $offset:expr),+,) => { 7 | $( 8 | /// Set/clear bit 9 | pub fn $name(&mut self, on: bool) -> &mut Self { 10 | if on { 11 | self.0 |= 1 << $offset; 12 | } else { 13 | self.0 &= !(1 << 4); 14 | } 15 | 16 | self 17 | } 18 | )+ 19 | } 20 | } 21 | 22 | pub mod gpio; 23 | pub mod itm; 24 | pub mod nvic; 25 | pub mod rcc; 26 | pub mod tim; 27 | 28 | extern "C" { 29 | #[link_name = "__GPIOA"] pub static mut GPIOA: gpio::Block; 30 | #[link_name = "__GPIOC"] pub static mut GPIOC: gpio::Block; 31 | #[link_name = "__NVIC"] pub static mut NVIC: nvic::Block; 32 | #[link_name = "__RCC"] pub static mut RCC: rcc::Block; 33 | #[link_name = "__TIM7"] pub static mut TIM7: tim::Block; 34 | } 35 | 36 | /// Read/write register 37 | #[repr(C)] 38 | pub struct Rw(T) where T: Copy; 39 | 40 | impl Rw 41 | where T: Copy 42 | { 43 | /// Reads the register value 44 | pub fn read(&self) -> T { 45 | unsafe { ptr::read_volatile(&self.0) } 46 | } 47 | 48 | /// Updates the register value 49 | pub fn update(&mut self, f: F) 50 | where F: FnOnce(&mut T) -> &mut T 51 | { 52 | let mut value = self.read(); 53 | f(&mut value); 54 | self.write(value); 55 | } 56 | 57 | /// Writes `value` to the register 58 | pub fn write(&mut self, value: U) 59 | where T: From 60 | { 61 | unsafe { 62 | ptr::write_volatile(&mut self.0, T::from(value)); 63 | } 64 | } 65 | } 66 | 67 | /// Write-only register 68 | #[repr(C)] 69 | pub struct Wo(T) where T: Copy; 70 | 71 | impl Wo 72 | where T: Copy 73 | { 74 | /// Writes `value` to the register 75 | pub fn write(&mut self, value: U) 76 | where T: From 77 | { 78 | unsafe { 79 | ptr::write_volatile(&mut self.0, T::from(value)); 80 | } 81 | } 82 | } 83 | -------------------------------------------------------------------------------- /src/register/nvic/iser1.rs: -------------------------------------------------------------------------------- 1 | //! Interrupt Set-enable 2 register 2 | 3 | /// Reset value 4 | pub const DEFAULT: Register = Register(0x0000_0000); 5 | 6 | /// Register 7 | #[derive(Clone, Copy)] 8 | #[repr(C)] 9 | pub struct Register(u32); 10 | 11 | impl Register { 12 | /// Interrupt set-enable bits 13 | pub fn setena(&mut self, i: u32) -> &mut Self { 14 | match i { 15 | 32...63 => { 16 | self.0 |= 1 << (i - 32); 17 | } 18 | _ => ::rt::abort(), 19 | } 20 | 21 | self 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /src/register/nvic/mod.rs: -------------------------------------------------------------------------------- 1 | //! Nested vector interrupt controller 2 | 3 | pub mod iser1; 4 | 5 | use register::Rw; 6 | 7 | /// Register block 8 | #[repr(C)] 9 | pub struct Block { 10 | iser0: u32, 11 | /// 0x04 12 | pub iser1: Rw, 13 | iser2: u32, 14 | } 15 | -------------------------------------------------------------------------------- /src/register/rcc/apb1enr.rs: -------------------------------------------------------------------------------- 1 | //! APB1 peripheral clock enable register 2 | 3 | /// Reset value 4 | pub const DEFAULT: Register = Register(0x0000_0000); 5 | 6 | /// Register 7 | #[derive(Clone, Copy)] 8 | #[repr(C)] 9 | pub struct Register(u32); 10 | 11 | impl Register { 12 | bits! { 13 | tim7en: 5, 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /src/register/rcc/apb2enr.rs: -------------------------------------------------------------------------------- 1 | //! APB2 peripheral clock enable register 2 | 3 | /// Reset value 4 | pub const DEFAULT: Register = Register(0); 5 | 6 | /// Register 7 | #[derive(Clone, Copy)] 8 | #[repr(C)] 9 | pub struct Register(u32); 10 | 11 | impl Register { 12 | bits! { 13 | iopaen: 2, 14 | iopcen: 4, 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /src/register/rcc/mod.rs: -------------------------------------------------------------------------------- 1 | //! Register and Clock Control 2 | 3 | pub mod apb2enr; 4 | pub mod apb1enr; 5 | 6 | use register::Rw; 7 | 8 | /// Register block 9 | #[repr(C)] 10 | pub struct Block { 11 | cr: u32, 12 | cfgr: u32, 13 | cir: u32, 14 | apb2rstr: u32, 15 | apb1rstr: u32, 16 | ahbenr: u32, 17 | /// 0x18 18 | pub apb2enr: Rw, 19 | /// 0x1C 20 | pub apb1enr: Rw, 21 | bdcr: u32, 22 | csr: u32, 23 | cfgr2: u32, 24 | } 25 | -------------------------------------------------------------------------------- /src/register/tim/arr.rs: -------------------------------------------------------------------------------- 1 | //! Auto-reload register 2 | 3 | /// Register 4 | #[derive(Clone, Copy)] 5 | #[repr(C)] 6 | pub struct Register(u32); 7 | 8 | impl From for Register { 9 | fn from(x: u16) -> Register { 10 | Register(u32::from(x)) 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /src/register/tim/cr1.rs: -------------------------------------------------------------------------------- 1 | //! Control register 1 2 | 3 | /// Reset value 4 | pub const DEFAULT: Register = Register(0x0000_0000); 5 | 6 | /// Register 7 | #[derive(Clone, Copy)] 8 | #[repr(C)] 9 | pub struct Register(u32); 10 | 11 | impl Register { 12 | bits! { 13 | cen: 0, 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /src/register/tim/dier.rs: -------------------------------------------------------------------------------- 1 | //! DMA/interrupt enable register 2 | 3 | /// Reset value 4 | pub const DEFAULT: Register = Register(0x0000_0000); 5 | 6 | /// Register 7 | #[derive(Clone, Copy)] 8 | #[repr(C)] 9 | pub struct Register(u32); 10 | 11 | impl Register { 12 | bits! { 13 | uie: 0, 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /src/register/tim/egr.rs: -------------------------------------------------------------------------------- 1 | //! Event generation register 2 | 3 | /// Reset value 4 | pub const DEFAULT: Register = Register(0x0000_0000); 5 | 6 | /// Register 7 | #[derive(Clone, Copy)] 8 | #[repr(C)] 9 | pub struct Register(u32); 10 | 11 | impl Register { 12 | bits! { 13 | ug: 0, 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /src/register/tim/mod.rs: -------------------------------------------------------------------------------- 1 | //! Basic timers 2 | 3 | pub mod arr; 4 | pub mod dier; 5 | pub mod cr1; 6 | pub mod egr; 7 | pub mod psc; 8 | 9 | use register::{Rw, Wo}; 10 | 11 | /// Register block 12 | #[repr(C)] 13 | pub struct Block { 14 | /// 0x00 15 | pub cr1: Rw, 16 | cr2: u32, 17 | _0: u32, 18 | /// 0x0C 19 | pub dier: Rw, 20 | sr: u32, 21 | /// 0x14 22 | pub egr: Wo, 23 | _1: [u32; 3], 24 | cnt: u32, 25 | /// 0x28 26 | pub psc: Rw, 27 | /// 0x2C 28 | pub arr: Rw, 29 | } 30 | -------------------------------------------------------------------------------- /src/register/tim/psc.rs: -------------------------------------------------------------------------------- 1 | //! Prescaler register 2 | 3 | /// Register 4 | #[derive(Clone, Copy)] 5 | #[repr(C)] 6 | pub struct Register(u32); 7 | 8 | impl From for Register { 9 | fn from(x: u16) -> Register { 10 | Register(u32::from(x)) 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /src/rt.rs: -------------------------------------------------------------------------------- 1 | //! Runtime 2 | 3 | use core::ptr; 4 | 5 | /// Abort 6 | pub fn abort() -> ! { 7 | ::asm::bkpt(); 8 | 9 | loop {} 10 | } 11 | 12 | /// Initializes the .data section 13 | pub unsafe fn init_data() { 14 | extern "C" { 15 | static __DATA_LOAD: u32; 16 | 17 | static mut __DATA_END: u32; 18 | static mut __DATA_START: u32; 19 | } 20 | 21 | // NOTE: wrapping_sub and bitshift are used here to avoid panics due to overflow checks and 22 | // divide by zero. 23 | let n = (&__DATA_END as *const _ as usize).wrapping_sub(&__DATA_START as *const _ as usize) >> 24 | 2; 25 | 26 | ptr::copy_nonoverlapping(&__DATA_LOAD, &mut __DATA_START, n); 27 | } 28 | -------------------------------------------------------------------------------- /stm32f100.ld: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | FLASH : ORIGIN = 0x08000000, LENGTH = 128K 4 | RAM : ORIGIN = 0x20000000, LENGTH = 8K 5 | } 6 | 7 | PROVIDE(__tim7 = __default_handler); 8 | 9 | __GPIOA = 0x40010800; 10 | __GPIOC = 0x40011000; 11 | __RCC = 0x40021000; 12 | __TIM7 = 0x40001400; 13 | 14 | __ITM = 0xE0000000; 15 | __NVIC = 0xE000E100; 16 | 17 | __BITBAND_START = 0x40000000; 18 | __BITBAND_ALIAS = 0x42000000; 19 | 20 | __BB_GPIOA = __BITBAND_ALIAS + 32 * (__GPIOA - __BITBAND_START); 21 | __BB_GPIOC = __BITBAND_ALIAS + 32 * (__GPIOC - __BITBAND_START); 22 | __BB_RCC = __BITBAND_ALIAS + 32 * (__RCC - __BITBAND_START); 23 | __BB_TIM7 = __BITBAND_ALIAS + 32 * (__TIM7 - __BITBAND_START); 24 | 25 | INCLUDE common.ld 26 | INCLUDE cortex-m3.ld 27 | --------------------------------------------------------------------------------