├── .gitignore ├── README.md ├── cli ├── Cargo.lock ├── Cargo.toml ├── src │ └── main.rs └── test_programs │ ├── binfile │ ├── compile │ ├── entry.s │ ├── hello_world │ ├── hello_world.c │ ├── hello_world.elf │ ├── link.ld │ └── shell.nix └── lib ├── Cargo.lock ├── Cargo.toml └── src ├── cpu ├── base.rs ├── csrs.rs ├── instruction_sets │ ├── mod.rs │ ├── op_args.rs │ ├── rv32i.rs │ └── tests │ │ ├── mod.rs │ │ └── rv32i.rs ├── mod.rs ├── registers.rs └── rv32i.rs ├── instruction ├── decoder.rs ├── encoder.rs ├── funct3.rs ├── mod.rs ├── opcodes.rs └── util.rs ├── lib.rs ├── memory.rs └── util.rs /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jawline/risc-v-emulator/HEAD/.gitignore -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 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