├── .gitattributes ├── LICENSE ├── README.md ├── hw ├── cmn │ ├── io │ │ ├── recon_io.v │ │ └── recon_io_hw.tcl │ ├── timer │ │ ├── recon_timer.v │ │ └── recon_timer_hw.tcl │ └── util │ │ ├── buttonDebouncer.v │ │ ├── metaSync.v │ │ └── recon_util.qip ├── recon_0 │ ├── bemicro_max10 │ │ ├── alt_ip │ │ │ ├── alt_pll.qip │ │ │ └── alt_pll.v │ │ ├── constraints │ │ │ └── recon_0.sdc │ │ ├── recon_0.qpf │ │ ├── recon_0.qsf │ │ └── release │ │ │ └── recon_0.sof │ ├── max1000 │ │ ├── alt_ip │ │ │ ├── alt_pll.qip │ │ │ └── alt_pll.v │ │ ├── constraints │ │ │ └── recon_0.sdc │ │ ├── recon_0.qpf │ │ ├── recon_0.qsf │ │ └── release │ │ │ └── recon_0.sof │ ├── recon_0.qsys │ ├── recon_0.sopcinfo │ └── recon_0_top.v ├── recon_0a │ ├── max1000 │ │ ├── alt_ip │ │ │ ├── alt_pll.qip │ │ │ └── alt_pll.v │ │ ├── constraints │ │ │ └── recon_0a.sdc │ │ ├── recon_0a.qpf │ │ └── recon_0a.qsf │ ├── recon_0a.qsys │ ├── recon_0a.sopcinfo │ └── recon_0a_top.v ├── recon_1 │ ├── civ10 │ │ ├── output_files │ │ │ ├── convert_sof_to_hex.sh │ │ │ ├── generate_hw_sw_bundle_jic.cof │ │ │ └── program_fpga_image_to_flash.sh │ │ ├── recon_1.qpf │ │ ├── recon_1.qsf │ │ └── release │ │ │ ├── recon_1.flash │ │ │ ├── recon_1.hex │ │ │ ├── recon_1.jic │ │ │ ├── recon_1.sof │ │ │ └── software.hex │ ├── recon_1.qsys │ ├── recon_1.sopcinfo │ ├── recon_1_top.v │ ├── signal_tap │ │ └── cpu_dbus_ibus.stp │ └── timing_constraints │ │ └── recon_1.sdc └── recon_2 │ ├── max1000 │ ├── alt_ip │ │ ├── alt_ddr.qip │ │ ├── alt_ddr.v │ │ ├── alt_pll.qip │ │ └── alt_pll.v │ ├── constraints │ │ └── recon_2.sdc │ ├── output_files │ │ └── recon_2.sof │ ├── recon_2.qpf │ └── recon_2.qsf │ ├── recon_2.qsys │ ├── recon_2.sopcinfo │ └── recon_2_top.v └── sw ├── cmn ├── adc │ ├── ReconADC.cpp │ ├── ReconADC.h │ └── ReconADCHwDescription.h ├── io │ ├── recon_io.c │ └── recon_io.h ├── kits │ ├── kits_parameters.h │ └── max1000.h ├── serial │ ├── recon_serial.cpp │ └── recon_serial.h ├── timer │ ├── recon_timer.c │ └── recon_timer.h └── util │ ├── app_template │ ├── main_template │ └── recon_types.h ├── examples ├── adc_read │ └── src │ │ ├── app.cpp │ │ └── main.cpp └── frequency_counter │ └── src │ ├── app.cpp │ └── main.cpp ├── recon_0 ├── Makefile └── bsp │ └── settings.bsp ├── recon_0a ├── Makefile └── bsp │ └── settings.bsp ├── recon_1 ├── Makefile ├── bsp │ └── settings.bsp └── readme.txt └── recon_2 ├── Makefile ├── bsp └── settings.bsp └── readme.txt /.gitattributes: -------------------------------------------------------------------------------- 1 | * text=auto 2 | *.sof -text 3 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # recon 2 | RECON stands for Reconfigurable which is a collection of different flavours of NIOS-based embedded system. With RECON repository, new user can quickly turn their Altera low-cost FPGA dev board into a more a familiar microcontroller system such as AVR and start making custom logic based off this initial infrastructure. 3 | Directories structure: 4 | - hw : FPGA hardare/hdl/qsys files 5 | + cmn : common HDL reused across different architectures 6 | + recon_xxx : NIOS-based architectures 7 | 8 | - sw : Drivers/applications/demo 9 | + cmn : drivers for peripherals in hw/cmn 10 | + examples: demonstration applications 11 | + recon_xxx/bsp: preconfigured bsp for a recon_xxx architecture. For further information, go to the directory and type >make help 12 | 13 | 14 | -------------------------------------------------------------------------------- /hw/cmn/io/recon_io.v: -------------------------------------------------------------------------------- 1 | /* 2 | Project: RECON 2017 3 | Author: Jeff Lieu 4 | Description: IO port that supports up to 32 pins 5 | + Support PWM with programmable PWM Period 6 | + Support Interrupts on Changes of Input 7 | 8 | */ 9 | 10 | ///////////////////////////////////////////////////////////////////////////////// 11 | // synthesis translate_off 12 | `timescale 1ns / 1ps 13 | // synthesis translate_on 14 | 15 | // turn off superfluous verilog processor warnings 16 | // altera message_level Level1 17 | // altera message_off 10034 10035 10036 10037 10230 10240 10030 18 | 19 | /* Address definition */ 20 | `define DIR_OFFSET 0 21 | `define OUT_OFFSET 1 22 | `define IN_OFFSET 2 23 | `define OUT_SET_OFFSET 3 24 | `define OUT_CLR_OFFSET 4 25 | `define OPENDRN_OFFSET 5 26 | `define PWM_ENA_OFFSET 6 27 | `define IRQ_STATUS_OFFSET 7 28 | `define IRQ_ENA_OFFSET 8 29 | `define IRQ_REDGE_OFFSET 9 30 | `define IRQ_FEDGE_OFFSET 10 31 | `define DBNC_ENA_OFFSET 11 32 | `define PWM_PERIOD_OFFSET 12 33 | `define PWM_VALUE_OFFSET 16 34 | 35 | 36 | module recon_io ( 37 | // Avalon Interface 38 | // This is a simplest way of communicating to the Processor 39 | // Signals names are self descriptive 40 | address, 41 | chipselect, 42 | clk, 43 | reset_n, 44 | write, 45 | read, 46 | writedata, 47 | readdata, 48 | 49 | // Interrupt sender port 50 | // Interrupt is held high until it's cleared by software ISR that serves the interrupt 51 | irq, 52 | 53 | // IO Port 54 | io_out , 55 | io_in , 56 | io_oe , 57 | io_opdrn 58 | 59 | ) 60 | ; 61 | parameter PORT_WIDTH = 16; 62 | parameter PWM_CNTR_WIDTH = 8; 63 | output [ 31: 0] readdata; 64 | input [ 5: 0] address; 65 | input chipselect; 66 | input clk; 67 | input reset_n; 68 | input write; 69 | input read; 70 | input [ 31: 0] writedata; 71 | output [PORT_WIDTH-1:0] io_out; 72 | output [PORT_WIDTH-1:0] io_oe; 73 | output [PORT_WIDTH-1:0] io_opdrn; 74 | input [PORT_WIDTH-1:0] io_in; 75 | output irq; 76 | 77 | wire [ 31: 0] readdata; 78 | wire clk_en; 79 | reg [ PORT_WIDTH-1: 0] data_out; 80 | wire [ PORT_WIDTH-1: 0] out_port; 81 | reg [ PORT_WIDTH-1: 0] read_mux_reg; 82 | 83 | reg [ PORT_WIDTH-1: 0] pin_mode; 84 | reg [ PORT_WIDTH-1: 0] pin_opdrn; 85 | reg [ PORT_WIDTH-1: 0] data_in; 86 | reg [ PORT_WIDTH-1: 0] data_in_r1; 87 | reg [ PORT_WIDTH-1: 0] data_in_r2; 88 | reg [ PORT_WIDTH-1: 0] data_in_event; 89 | reg [ PORT_WIDTH-1: 0] pwm_ena; 90 | reg [ PORT_WIDTH-1: 0] pwm_out; 91 | wire [ PORT_WIDTH-1: 0] irq_ena; 92 | reg [ PORT_WIDTH-1: 0] irq_redge; 93 | reg [ PORT_WIDTH-1: 0] irq_fedge; 94 | reg [ PORT_WIDTH-1: 0] irq_status; 95 | reg [ PWM_CNTR_WIDTH : 0] pwm_values[PORT_WIDTH-1:0]; 96 | reg [ PWM_CNTR_WIDTH-1: 0] pwm_cntr; 97 | reg [ PWM_CNTR_WIDTH : 0] pwm_period; 98 | 99 | 100 | assign clk_en = 1; 101 | 102 | initial 103 | begin 104 | pwm_ena <= 0; 105 | end 106 | 107 | /** 108 | A very basic and important component in HDL is a register which is described by always(@posedge clk) statement 109 | This statement says that: 110 | - At positive edge of clock 111 | - If chipselect and read are asserted 112 | - Latch the read_mux_reg with the following values depending on the address 113 | - The case statement describes a multiplexer, in this case 13:1 multiplexer 114 | - When the case statement is included in a "clocked" statement, the output of the multiplexer goes into a Register to store the value 115 | */ 116 | always@(posedge clk) 117 | begin 118 | if (chipselect && read) 119 | case(address) 120 | `DIR_OFFSET : read_mux_reg <= pin_mode; 121 | `OUT_OFFSET : read_mux_reg <= data_out; 122 | `IN_OFFSET : read_mux_reg <= data_in; 123 | `OUT_SET_OFFSET : read_mux_reg <= 32'h0; 124 | `OUT_CLR_OFFSET : read_mux_reg <= 32'h0; 125 | `OPENDRN_OFFSET : read_mux_reg <= pin_opdrn; 126 | `IRQ_ENA_OFFSET : read_mux_reg <= irq_ena; 127 | `PWM_ENA_OFFSET : read_mux_reg <= pwm_ena; 128 | `IRQ_STATUS_OFFSET: read_mux_reg <= irq_status; 129 | `IRQ_REDGE_OFFSET : read_mux_reg <= irq_redge; 130 | `IRQ_FEDGE_OFFSET : read_mux_reg <= irq_fedge; 131 | `PWM_PERIOD_OFFSET: read_mux_reg <= pwm_period; 132 | default : read_mux_reg <= data_in; 133 | endcase 134 | end 135 | assign readdata = {32'b0 | read_mux_reg}; 136 | 137 | /* Settings registers 138 | This statement describes registers with asynchronous reset 139 | we have 5 registers: 140 | pin_mode, pwm_ena, irq_redge, irq_fedge and pwm_period 141 | These are asynchronuously reset by the reset_n signal 142 | And synchronously captured the value on the writedata bus when : 143 | - chipselect is assered 144 | - write signal is asserted 145 | - and the address matches the register's address 146 | */ 147 | integer I; 148 | always @(posedge clk or negedge reset_n) 149 | begin 150 | if (reset_n == 0) begin 151 | pin_mode <= 0; 152 | pwm_ena <= 0; 153 | irq_redge<= 0; 154 | irq_fedge<= 0; 155 | pwm_period[PWM_CNTR_WIDTH] <= 1'b1; 156 | pwm_period[PWM_CNTR_WIDTH-1:0] <= 0; 157 | end 158 | else begin 159 | if (chipselect && write && (address == `DIR_OFFSET)) begin 160 | pin_mode <= writedata; 161 | end 162 | if (chipselect && write && (address == `PWM_ENA_OFFSET)) begin 163 | pwm_ena <= writedata; 164 | end 165 | if (chipselect && write && (address == `IRQ_REDGE_OFFSET)) begin 166 | irq_redge <= writedata; 167 | end 168 | if (chipselect && write && (address == `IRQ_FEDGE_OFFSET)) begin 169 | irq_fedge <= writedata; 170 | end 171 | if (chipselect && write && (address == `PWM_PERIOD_OFFSET)) begin 172 | pwm_period <= writedata; 173 | end 174 | end 175 | end 176 | /* This is a combinatorial statement 177 | when you use "assign" to describe the behavior, it is synthesized into Combinatorial logic, i.e there's no registers to hold value 178 | in this case 179 | irq_ena is the output of an or gate whose inputs are irq_redge and irq_fedge. 180 | This simply says that when either irq_redge or irq_fedge is set, we enable the interrupt 181 | */ 182 | assign irq_ena = irq_redge | irq_fedge; 183 | 184 | /* 185 | Data Out Register 186 | */ 187 | always @(posedge clk or negedge reset_n) 188 | begin 189 | if (reset_n == 0) 190 | data_out <= 0; 191 | else 192 | for(I=0;I perform OR operations of all the bits in the vector 239 | */ 240 | assign irq = | irq_status; 241 | 242 | /* 243 | PWM values registers 244 | Again, FOR loop in HDL will be unrolled, usually the RANGE of For loop is a constant 245 | */ 246 | always@(posedge clk) 247 | begin 248 | for(I=0;I 4 | Description: Timer module to support delay function 5 | */ 6 | 7 | ///////////////////////////////////////////////////////////////////////////////// 8 | // synthesis translate_off 9 | `timescale 1ns / 1ps 10 | // synthesis translate_on 11 | 12 | 13 | `define MILLISEC_OFFSET 0 14 | `define SECOND_OFFSET 1 15 | `define IRQ_TIME_OFFSET 2 16 | `define CTRL_OFFSET 3 17 | `define IRQ_STATUS_OFFSET 4 18 | 19 | `define IRQ_COUNTDOWN_ENA_BIT 0 20 | `define IRQ_TIMER_CONTINUOUS_BIT 1 21 | `define IRQ_TIMER_MATCH_ENA_BIT 2 22 | 23 | 24 | module recon_timer ( 25 | //Avalon slave 26 | address, 27 | chipselect, 28 | clk, 29 | reset_n, 30 | write, 31 | read, 32 | writedata, 33 | readdata, 34 | 35 | //IRQ 36 | irq, 37 | 38 | //Timing Pulses 39 | microsec_tick, 40 | millisec_tick, 41 | second_tick 42 | ); 43 | parameter CLK_FREQ = 50000000; 44 | parameter MILLISEC = CLK_FREQ/1000-1; 45 | parameter MICROSEC = CLK_FREQ/1000000-1; 46 | 47 | output [ 31: 0] readdata; 48 | input [ 2: 0] address; 49 | input chipselect; 50 | input clk; 51 | input reset_n; 52 | input write; 53 | input read; 54 | input [ 31: 0] writedata; 55 | output irq; 56 | output reg microsec_tick; 57 | output reg millisec_tick; 58 | output reg second_tick; 59 | wire [ 31: 0] readdata; 60 | 61 | 62 | 63 | reg [ 31: 0] read_mux_reg; 64 | reg [ 9: 0] microsec; 65 | reg [ 31: 0] millisec; 66 | reg [ 31: 0] next_millisec; 67 | reg [ 31: 0] second; 68 | reg [ 3: 0] ctrl_reg; 69 | reg [ 31: 0] irq_timer; 70 | reg [ 31: 0] irq_time; 71 | reg [ 9: 0] timer; 72 | reg irq_active; 73 | reg irq_active_d; 74 | reg irq_pulse; 75 | //s1, which is an e_avalon_slave 76 | 77 | always@(posedge clk) 78 | begin 79 | if (chipselect && read) 80 | case(address) 81 | `MILLISEC_OFFSET : read_mux_reg <= millisec; 82 | `SECOND_OFFSET : read_mux_reg <= second; 83 | `IRQ_TIME_OFFSET : read_mux_reg <= irq_time; 84 | `CTRL_OFFSET : read_mux_reg <= {28'h0, ctrl_reg}; 85 | `IRQ_STATUS_OFFSET : read_mux_reg <= {31'h0, irq_pulse}; 86 | default : read_mux_reg <= 32'h0; 87 | endcase 88 | end 89 | assign readdata = read_mux_reg; 90 | 91 | always@(posedge clk or negedge reset_n) 92 | if (~reset_n) begin 93 | millisec <= 0; 94 | second <= 0; 95 | next_millisec <= 999; 96 | microsec_tick <= 1'b0; 97 | millisec_tick <= 1'b0; 98 | second_tick <= 1'b0; 99 | end else begin 100 | 101 | /* Timer */ 102 | timer <= timer + 1; 103 | millisec_tick <= 1'b0; 104 | second_tick <= 1'b0; 105 | microsec_tick <= 1'b0; 106 | if (timer == MICROSEC) begin 107 | timer <= 0; 108 | microsec <= microsec + 1; 109 | microsec_tick <= 1'b1; 110 | /* Increment millisec */ 111 | if (microsec == 999) begin 112 | microsec <= 0; 113 | millisec <= millisec + 1; 114 | millisec_tick <= 1'b1; 115 | /* Increment second */ 116 | if (millisec == next_millisec) begin 117 | second <= second+1; 118 | next_millisec <= next_millisec + 1000; 119 | second_tick <= 1'b1; 120 | end 121 | end 122 | end 123 | 124 | /* CTRL Register */ 125 | if (chipselect && write && address==`CTRL_OFFSET) 126 | ctrl_reg <= writedata; 127 | 128 | /* Timing Interval */ 129 | if (chipselect && write && address==`IRQ_TIME_OFFSET) 130 | irq_time <= writedata; 131 | 132 | if (irq_active) 133 | irq_pulse <= 1'b1; 134 | else if (chipselect && write && address == `IRQ_STATUS_OFFSET && writedata[0]==1'b1) 135 | irq_pulse <= 1'b0; 136 | 137 | /* Interval Interrupt mode */ 138 | irq_active <= 1'b0; 139 | if (ctrl_reg[`IRQ_COUNTDOWN_ENA_BIT]==1'b1) begin 140 | if (millisec_tick == 1'b1) begin 141 | irq_timer <= irq_timer + 1; 142 | if (irq_timer == irq_time) begin 143 | irq_active <= 1'b1; 144 | /* If Continuous Mode is enabled, we restart the timer */ 145 | if (ctrl_reg[`IRQ_TIMER_CONTINUOUS_BIT]==1'b1) begin 146 | irq_timer <= 0; 147 | end 148 | end 149 | end 150 | end else 151 | /* Match Mode Interrupt */ 152 | if (ctrl_reg[`IRQ_TIMER_MATCH_ENA_BIT]==1'b1) begin 153 | if (millisec == irq_time) begin 154 | irq_active <= 1'b1; 155 | end 156 | end 157 | 158 | end 159 | 160 | assign irq = irq_pulse; 161 | 162 | endmodule 163 | 164 | 165 | -------------------------------------------------------------------------------- /hw/cmn/timer/recon_timer_hw.tcl: -------------------------------------------------------------------------------- 1 | # TCL File Generated by Component Editor 16.0 2 | # Tue May 23 23:30:12 EST 2017 3 | # DO NOT MODIFY 4 | 5 | 6 | # 7 | # recon_timer "recon_timer" v1.0 8 | # JEFF LIEU 2017.05.23.23:30:12 9 | # Timer to support delay function 10 | # 11 | 12 | # 13 | # request TCL package from ACDS 16.0 14 | # 15 | package require -exact qsys 16.0 16 | 17 | 18 | # 19 | # module recon_timer 20 | # 21 | set_module_property DESCRIPTION "Timer to support delay function" 22 | set_module_property NAME recon_timer 23 | set_module_property VERSION 1.0 24 | set_module_property INTERNAL false 25 | set_module_property OPAQUE_ADDRESS_MAP true 26 | set_module_property GROUP "RECON Library" 27 | set_module_property AUTHOR "JEFF LIEU" 28 | set_module_property DISPLAY_NAME recon_timer 29 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 30 | set_module_property EDITABLE false 31 | set_module_property REPORT_TO_TALKBACK false 32 | set_module_property ALLOW_GREYBOX_GENERATION false 33 | set_module_property REPORT_HIERARCHY false 34 | set_module_property VALIDATION_CALLBACK validate 35 | 36 | # 37 | # file sets 38 | # 39 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" 40 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL recon_timer 41 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false 42 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false 43 | add_fileset_file recon_timer.v VERILOG PATH ./recon_timer.v TOP_LEVEL_FILE 44 | 45 | 46 | # 47 | # parameters 48 | # 49 | add_parameter CLK_FREQ INTEGER 50000000 "" 50 | set_parameter_property CLK_FREQ DEFAULT_VALUE 50000000 51 | set_parameter_property CLK_FREQ DISPLAY_NAME CLK_FREQ 52 | set_parameter_property CLK_FREQ TYPE INTEGER 53 | set_parameter_property CLK_FREQ UNITS Hertz 54 | set_parameter_property CLK_FREQ ALLOWED_RANGES 0:1000000000 55 | set_parameter_property CLK_FREQ DESCRIPTION "Frequency of system clock" 56 | set_parameter_property CLK_FREQ HDL_PARAMETER true 57 | 58 | 59 | # 60 | # display items 61 | # 62 | 63 | 64 | # 65 | # connection point clock 66 | # 67 | add_interface clock clock end 68 | set_interface_property clock clockRate 0 69 | set_interface_property clock ENABLED true 70 | set_interface_property clock EXPORT_OF "" 71 | set_interface_property clock PORT_NAME_MAP "" 72 | set_interface_property clock CMSIS_SVD_VARIABLES "" 73 | set_interface_property clock SVD_ADDRESS_GROUP "" 74 | 75 | add_interface_port clock clk clk Input 1 76 | 77 | 78 | # 79 | # connection point reset 80 | # 81 | add_interface reset reset end 82 | set_interface_property reset associatedClock clock 83 | set_interface_property reset synchronousEdges DEASSERT 84 | set_interface_property reset ENABLED true 85 | set_interface_property reset EXPORT_OF "" 86 | set_interface_property reset PORT_NAME_MAP "" 87 | set_interface_property reset CMSIS_SVD_VARIABLES "" 88 | set_interface_property reset SVD_ADDRESS_GROUP "" 89 | 90 | add_interface_port reset reset_n reset_n Input 1 91 | 92 | 93 | # 94 | # connection point irq 95 | # 96 | add_interface irq interrupt end 97 | set_interface_property irq associatedAddressablePoint s0 98 | set_interface_property irq associatedClock clock 99 | set_interface_property irq associatedReset reset 100 | set_interface_property irq bridgedReceiverOffset "" 101 | set_interface_property irq bridgesToReceiver "" 102 | set_interface_property irq ENABLED true 103 | set_interface_property irq EXPORT_OF "" 104 | set_interface_property irq PORT_NAME_MAP "" 105 | set_interface_property irq CMSIS_SVD_VARIABLES "" 106 | set_interface_property irq SVD_ADDRESS_GROUP "" 107 | 108 | add_interface_port irq irq irq Output 1 109 | 110 | 111 | # 112 | # connection point clock_tick 113 | # 114 | add_interface clock_tick conduit end 115 | set_interface_property clock_tick associatedClock clock 116 | set_interface_property clock_tick associatedReset "" 117 | set_interface_property clock_tick ENABLED true 118 | set_interface_property clock_tick EXPORT_OF "" 119 | set_interface_property clock_tick PORT_NAME_MAP "" 120 | set_interface_property clock_tick CMSIS_SVD_VARIABLES "" 121 | set_interface_property clock_tick SVD_ADDRESS_GROUP "" 122 | 123 | add_interface_port clock_tick second_tick second Output 1 124 | add_interface_port clock_tick millisec_tick millisecond Output 1 125 | add_interface_port clock_tick microsec_tick microsec Output 1 126 | 127 | 128 | # 129 | # connection point s0 130 | # 131 | add_interface s0 avalon end 132 | set_interface_property s0 addressUnits WORDS 133 | set_interface_property s0 associatedClock clock 134 | set_interface_property s0 associatedReset reset 135 | set_interface_property s0 bitsPerSymbol 8 136 | set_interface_property s0 burstOnBurstBoundariesOnly false 137 | set_interface_property s0 burstcountUnits WORDS 138 | set_interface_property s0 explicitAddressSpan 0 139 | set_interface_property s0 holdTime 0 140 | set_interface_property s0 linewrapBursts false 141 | set_interface_property s0 maximumPendingReadTransactions 0 142 | set_interface_property s0 maximumPendingWriteTransactions 0 143 | set_interface_property s0 readLatency 1 144 | set_interface_property s0 readWaitTime 1 145 | set_interface_property s0 setupTime 0 146 | set_interface_property s0 timingUnits Cycles 147 | set_interface_property s0 writeWaitTime 0 148 | set_interface_property s0 ENABLED true 149 | set_interface_property s0 EXPORT_OF "" 150 | set_interface_property s0 PORT_NAME_MAP "" 151 | set_interface_property s0 CMSIS_SVD_VARIABLES "" 152 | set_interface_property s0 SVD_ADDRESS_GROUP "" 153 | 154 | add_interface_port s0 address address Input 3 155 | add_interface_port s0 chipselect chipselect Input 1 156 | add_interface_port s0 write write Input 1 157 | add_interface_port s0 read read Input 1 158 | add_interface_port s0 writedata writedata Input 32 159 | add_interface_port s0 readdata readdata Output 32 160 | set_interface_assignment s0 embeddedsw.configuration.isFlash 0 161 | set_interface_assignment s0 embeddedsw.configuration.isMemoryDevice 0 162 | set_interface_assignment s0 embeddedsw.configuration.isNonVolatileStorage 0 163 | set_interface_assignment s0 embeddedsw.configuration.isPrintableDevice 0 164 | 165 | proc validate {} { 166 | set_module_assignment embeddedsw.CMacro.CLK_FREQUENCY [get_parameter_value CLK_FREQ] 167 | } 168 | -------------------------------------------------------------------------------- /hw/cmn/util/buttonDebouncer.v: -------------------------------------------------------------------------------- 1 | /* 2 | Project: RECON 2017 3 | Author: Jeff Lieu 4 | Description: Timer module to support delay function 5 | */ 6 | 7 | module buttonDebouncer 8 | #( /* Debounce time - Count in nanosecond */ 9 | parameter pDEBOUNCE_PERIOD = 100_000_000, 10 | /* Clock Input period - Count in nanosecond */ 11 | parameter pCLKIN_PERIOD = 20, 12 | /* Size of button array */ 13 | parameter pARRAY_SIZE = 2, 14 | /* 15 | Polarity configures the edge detection which edge would cause a tick 16 | Buttons are default to active low, which means a "Button Down" event is generated when the signal level fall from High to Low 17 | Active high (pPOLARITY = 1) means a Button Down when the signal level changes from Low to High 18 | */ 19 | parameter pPOLARITY = 0)( 20 | 21 | input clk , 22 | input [ pARRAY_SIZE-1:0] buttons , 23 | output [ pARRAY_SIZE-1:0] buttonState, 24 | output reg [ pARRAY_SIZE-1:0] buttonUpTick, 25 | output reg [ pARRAY_SIZE-1:0] buttonDwTick 26 | ); 27 | 28 | 29 | reg [pARRAY_SIZE-1:0] buttonsReg0; 30 | reg [pARRAY_SIZE-1:0] buttonsReg1; 31 | reg [pARRAY_SIZE-1:0] buttonsReg2; 32 | /* We share the counter, if buttons are pressed together, 33 | we need to wait for all buttons to settle */ 34 | reg [23:0] debouncer; 35 | reg [pARRAY_SIZE-1:0] buttonsDebounced; 36 | reg [pARRAY_SIZE-1:0] buttonsDebouncedReg; 37 | 38 | reg [pARRAY_SIZE-1:0] buttonTck; 39 | integer I; 40 | 41 | 42 | always@(posedge clk) 43 | begin 44 | buttonsReg0 <= buttons; 45 | buttonsReg1 <= buttonsReg0; 46 | buttonsReg2 <= buttonsReg1; 47 | 48 | if (buttonsReg2 != buttonsReg1) 49 | begin 50 | debouncer <= pDEBOUNCE_PERIOD/pCLKIN_PERIOD; 51 | end 52 | else if (debouncer != 0) 53 | begin 54 | debouncer <= debouncer - 1; 55 | end 56 | else begin 57 | buttonsDebounced <= buttonsReg2; 58 | end 59 | 60 | buttonsDebouncedReg <= buttonsDebounced; 61 | 62 | for(I = 0; I 4 | Description: recon_0_top level 5 | */ 6 | 7 | /* Note that the PORT_0_WIDTH doesn't propagate to the NIOS system */ 8 | module recon_0_top #(parameter PORT_0_WIDTH = 32) ( 9 | input sys_clk, 10 | input sys_rstn, 11 | 12 | inout [ PORT_0_WIDTH-1:0] port_0_io, 13 | output uart_0_txd, 14 | input uart_0_rxd 15 | ); 16 | 17 | wire [PORT_0_WIDTH-1:0] port_0_out; 18 | wire [PORT_0_WIDTH-1:0] port_0_in; 19 | wire [PORT_0_WIDTH-1:0] port_0_oe; 20 | wire [PORT_0_WIDTH-1:0] port_0_opdrn; 21 | wire cpu_clk, locked; 22 | 23 | /* 24 | PLL is put at the top to be shared across boards 25 | THe output of the CPU clock is required to be 80MHz 26 | */ 27 | alt_pll pll( 28 | .areset (~sys_rstn), 29 | .inclk0 (sys_clk), 30 | .c0 (cpu_clk), 31 | .locked (locked)); 32 | 33 | buttonDebouncer 34 | #( /* Debounce time - Count in nanosecond */ 35 | .pDEBOUNCE_PERIOD (100_000_000), 36 | /* Clock Input period - Count in nanosecond */ 37 | .pCLKIN_PERIOD (20 ), 38 | /* Size of button array */ 39 | .pARRAY_SIZE (1 ), 40 | /* 41 | Polarity configures the edge detection which edge would cause a tick 42 | Buttons are default to active low, which means a "Button Down" event is generated when the signal level fall from High to Low 43 | Active high (pPOLARITY = 1) means a Button Down when the signal level changes from Low to High 44 | */ 45 | .pPOLARITY (0)) resetDebounce 46 | ( 47 | .clk (sys_clk), 48 | .buttons (sys_rstn), 49 | .buttonState (sys_rstn_db), /* In Verilog, you can have an implied net declaration */ 50 | .buttonUpTick (), 51 | .buttonDwTick () 52 | ); 53 | 54 | /* NIOS System - Configured and Generated by QSYS */ 55 | recon_0 ( 56 | .clk_clk (cpu_clk), // clk.clk 57 | .recon_io_0_io_port_io_out (port_0_out), // recon_io_0_io_port.io_out 58 | .recon_io_0_io_port_io_opdrn (port_0_opdrn), // .io_opdrn 59 | .recon_io_0_io_port_io_in (port_0_in), // .io_in 60 | .recon_io_0_io_port_io_oe (port_0_oe), // .io_oe 61 | .recon_timer_0_clock_tick_second (), // recon_timer_0_clock_tick.second 62 | .recon_timer_0_clock_tick_millisecond (), // .millisecond 63 | .recon_timer_0_clock_tick_microsec (), // .microsec 64 | .reset_reset_n (sys_rstn_db), // reset.reset_n 65 | .uart_0_rxd (uart_0_rxd), 66 | .uart_0_txd (uart_0_txd) 67 | ); 68 | /* You can Insert your own Debouncer for the Button Here if required */ 69 | genvar IO; 70 | generate 71 | for (IO = 0; IO 4 | Description: recon_2_top level 5 | */ 6 | 7 | /* Note that the PORT_0_WIDTH doesn't propagate to the NIOS system */ 8 | module recon_0a_top #(parameter PORT_0_WIDTH = 16) ( 9 | input sys_clk, 10 | input sys_rstn, 11 | 12 | inout [ PORT_0_WIDTH-1:0] port_0_io, 13 | output uart_0_txd, 14 | input uart_0_rxd 15 | ); 16 | 17 | wire [PORT_0_WIDTH-1:0] port_0_out; 18 | wire [PORT_0_WIDTH-1:0] port_0_in; 19 | wire [PORT_0_WIDTH-1:0] port_0_oe; 20 | wire [PORT_0_WIDTH-1:0] port_0_opdrn; 21 | wire cpu_clk, locked; 22 | 23 | /* 24 | PLL is put at the top to be shared across boards 25 | THe output of the CPU clock is required to be 80MHz 26 | */ 27 | alt_pll pll( 28 | .areset (~sys_rstn), 29 | .inclk0 (sys_clk), 30 | .c0 (cpu_clk), 31 | .locked (locked)); 32 | 33 | buttonDebouncer 34 | #( /* Debounce time - Count in nanosecond */ 35 | .pDEBOUNCE_PERIOD (100_000_000), 36 | /* Clock Input period - Count in nanosecond */ 37 | .pCLKIN_PERIOD (20 ), 38 | /* Size of button array */ 39 | .pARRAY_SIZE (1 ), 40 | /* 41 | Polarity configures the edge detection which edge would cause a tick 42 | Buttons are default to active low, which means a "Button Down" event is generated when the signal level fall from High to Low 43 | Active high (pPOLARITY = 1) means a Button Down when the signal level changes from Low to High 44 | */ 45 | .pPOLARITY (0)) resetDebounce 46 | ( 47 | .clk (sys_clk), 48 | .buttons (sys_rstn), 49 | .buttonState (sys_rstn_db), /* In Verilog, you can have an implied net declaration */ 50 | .buttonUpTick (), 51 | .buttonDwTick () 52 | ); 53 | 54 | /* NIOS System - Configured and Generated by QSYS */ 55 | recon_0a ( 56 | .adc_0_adc_pll_input_export (locked), 57 | .clk_clk (cpu_clk), // clk.clk 58 | .recon_io_0_io_port_io_out (port_0_out), // recon_io_0_io_port.io_out 59 | .recon_io_0_io_port_io_opdrn (port_0_opdrn), // .io_opdrn 60 | .recon_io_0_io_port_io_in (port_0_in), // .io_in 61 | .recon_io_0_io_port_io_oe (port_0_oe), // .io_oe 62 | .recon_timer_0_clock_tick_second (), // recon_timer_0_clock_tick.second 63 | .recon_timer_0_clock_tick_millisecond (), // .millisecond 64 | .recon_timer_0_clock_tick_microsec (), // .microsec 65 | .reset_reset_n (sys_rstn_db), // reset.reset_n 66 | .uart_0_rxd (uart_0_rxd), 67 | .uart_0_txd (uart_0_txd) 68 | ); 69 | /* You can Insert your own Debouncer for the Button Here if required */ 70 | genvar IO; 71 | generate 72 | for (IO = 0; IO 2 | 3 | EPCS16 4 | EP4CE10 5 | output_files/recon_1.jic 6 | 0 7 | 1 8 | 7 9 | 10 | /home/jeff/fpga_workspace/GitIPCores/recon/hw/recon_1/civ10/release/software.hex 11 | absolute 12 | 0 13 | 14 | 15 | /home/jeff/fpga_workspace/GitIPCores/recon/hw/recon_1/civ10/output_files/recon_1.hex 16 | absolute 17 | 0 18 | 19 | 10 20 | 0 21 | 0 22 | 0 23 | 1 24 | 25 | 1 26 | 27 | 28 | 2 29 | 2 30 | 0 31 | -1 32 | -1 33 | 1 34 | 35 | -------------------------------------------------------------------------------- /hw/recon_1/civ10/output_files/program_fpga_image_to_flash.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | nios2-flash-programmer recon_1.flash --epcs --base=0x02000000 3 | -------------------------------------------------------------------------------- /hw/recon_1/civ10/recon_1.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 22 | # Date created = 23:28:18 May 18, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "16.0" 27 | DATE = "23:28:18 May 18, 2017" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "recon_1" 32 | -------------------------------------------------------------------------------- /hw/recon_1/civ10/release/recon_1.jic: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jefflieu/recon/e89ac37aa8fe5b76281c6af2ec8dd8d458510bbb/hw/recon_1/civ10/release/recon_1.jic -------------------------------------------------------------------------------- /hw/recon_1/civ10/release/recon_1.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jefflieu/recon/e89ac37aa8fe5b76281c6af2ec8dd8d458510bbb/hw/recon_1/civ10/release/recon_1.sof -------------------------------------------------------------------------------- /hw/recon_1/recon_1_top.v: -------------------------------------------------------------------------------- 1 | /* 2 | Project: RECON 2017 3 | Author: Jeff Lieu 4 | Description: recon_0_top level 5 | */ 6 | 7 | /* Note that the PORT_0_WIDTH doesn't propagate to the NIOS system */ 8 | module recon_1_top #(parameter PORT_0_WIDTH = 32) ( 9 | input sys_clk, 10 | input sys_rstn, 11 | 12 | inout [ PORT_0_WIDTH-1:0] port_0_io, 13 | output uart_0_txd, 14 | input uart_0_rxd, 15 | output wire epcs_0_dclk, // epcs_0.dclk 16 | output wire epcs_0_sce, // .sce 17 | output wire epcs_0_sdo, // .sdo 18 | input wire epcs_0_data0 19 | ); 20 | 21 | wire [PORT_0_WIDTH-1:0] port_0_out; 22 | wire [PORT_0_WIDTH-1:0] port_0_in; 23 | wire [PORT_0_WIDTH-1:0] port_0_oe; 24 | wire [PORT_0_WIDTH-1:0] port_0_opdrn; 25 | 26 | buttonDebouncer 27 | #( /* Debounce time - Count in nanosecond */ 28 | .pDEBOUNCE_PERIOD (100_000_000), 29 | /* Clock Input period - Count in nanosecond */ 30 | .pCLKIN_PERIOD (20 ), 31 | /* Size of button array */ 32 | .pARRAY_SIZE (1 ), 33 | /* 34 | Polarity configures the edge detection which edge would cause a tick 35 | Buttons are default to active low, which means a "Button Down" event is generated when the signal level fall from High to Low 36 | Active high (pPOLARITY = 1) means a Button Down when the signal level changes from Low to High 37 | */ 38 | .pPOLARITY (0)) resetDebounce 39 | ( 40 | .clk (sys_clk), 41 | .buttons (sys_rstn), 42 | .buttonState (sys_rstn_db), /* In Verilog, you can have an implied net declaration */ 43 | .buttonUpTick (), 44 | .buttonDwTick () 45 | ); 46 | 47 | /* NIOS System - Configured and Generated by QSYS */ 48 | recon_1 ( 49 | .altpll_0_locked_export ( ), // altpll_0_locked.export 50 | .clk_clk (sys_clk), // clk.clk 51 | .recon_io_0_io_port_io_out (port_0_out), // recon_io_0_io_port.io_out 52 | .recon_io_0_io_port_io_opdrn (port_0_opdrn), // .io_opdrn 53 | .recon_io_0_io_port_io_in (port_0_in), // .io_in 54 | .recon_io_0_io_port_io_oe (port_0_oe), // .io_oe 55 | .recon_timer_0_clock_tick_second (), // recon_timer_0_clock_tick.second 56 | .recon_timer_0_clock_tick_millisecond (), // .millisecond 57 | .recon_timer_0_clock_tick_microsec (), // .microsec 58 | .reset_reset_n (sys_rstn_db), // reset.reset_n 59 | .uart_0_rxd (uart_0_rxd), 60 | .uart_0_txd (uart_0_txd), 61 | .epcs_0_dclk (epcs_0_dclk), // epcs_0.dclk 62 | .epcs_0_sce (epcs_0_sce), // .sce 63 | .epcs_0_sdo (epcs_0_sdo), // .sdo 64 | .epcs_0_data0 (epcs_0_data0) 65 | ); 66 | 67 | /* You can Insert your own Debouncer for the Button Here if required */ 68 | genvar IO; 69 | generate 70 | for (IO = 0; IO 67 | // 92 | // Retrieval info: 93 | // Retrieval info: 94 | // Retrieval info: 95 | // Retrieval info: 96 | // Retrieval info: 97 | // Retrieval info: 98 | // Retrieval info: 99 | // Retrieval info: 100 | // Retrieval info: 101 | // Retrieval info: 102 | // Retrieval info: 103 | // Retrieval info: 104 | // Retrieval info: 105 | // Retrieval info: 106 | // Retrieval info: 107 | // Retrieval info: 108 | // Retrieval info: 109 | // Retrieval info: 110 | // Retrieval info: 111 | // Retrieval info: 112 | // Retrieval info: 113 | // Retrieval info: 114 | // Retrieval info: 115 | // Retrieval info: 116 | // Retrieval info: 117 | // Retrieval info: 118 | // Retrieval info: 119 | // Retrieval info: 120 | // Retrieval info: 121 | // Retrieval info: 122 | // IPFS_FILES : alt_ddr.vo 123 | // RELATED_FILES: alt_ddr.v, altera_gpio_lite.sv 124 | -------------------------------------------------------------------------------- /hw/recon_2/max1000/alt_ip/alt_pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "alt_pll.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "alt_pll.ppf"] 6 | -------------------------------------------------------------------------------- /hw/recon_2/max1000/constraints/recon_2.sdc: -------------------------------------------------------------------------------- 1 | ## Generated SDC file "/home/jeff/fpga_workspace/GitIPCores/recon/hw/recon_2/bemicro_max10/timing_constraints/recon_2.sdc" 2 | 3 | ## Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | ## Your use of Altera Corporation's design tools, logic functions 5 | ## and other software and tools, and its AMPP partner logic 6 | ## functions, and any output files from any of the foregoing 7 | ## (including device programming or simulation files), and any 8 | ## associated documentation or information are expressly subject 9 | ## to the terms and conditions of the Altera Program License 10 | ## Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | ## the Altera MegaCore Function License Agreement, or other 12 | ## applicable license agreement, including, without limitation, 13 | ## that your use is for the sole purpose of programming logic 14 | ## devices manufactured by Altera and sold by Altera or its 15 | ## authorized distributors. Please refer to the applicable 16 | ## agreement for further details. 17 | 18 | 19 | ## VENDOR "Altera" 20 | ## PROGRAM "Quartus Prime" 21 | ## VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" 22 | 23 | ## DATE "Tue May 23 22:37:36 2017" 24 | 25 | ## 26 | ## DEVICE "10M08DAF484C8GES" 27 | ## 28 | 29 | 30 | #************************************************************** 31 | # Time Information 32 | #************************************************************** 33 | 34 | set_time_format -unit ns -decimal_places 3 35 | 36 | 37 | 38 | #************************************************************** 39 | # Create Clock 40 | #************************************************************** 41 | 42 | create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}] 43 | create_clock -name {sys_clk_in} -period 83.334 -waveform { 0.000 42.000 } [get_ports {sys_clk}] 44 | 45 | derive_pll_clocks 46 | derive_clock_uncertainty 47 | 48 | # Rename the clock 49 | set cpu_clk {pll|altpll_component|auto_generated|pll1|clk[0]} 50 | set ram_clk {pll|altpll_component|auto_generated|pll1|clk[1]} 51 | 52 | #************************************************************** 53 | # Create Generated Clock 54 | #************************************************************** 55 | create_generated_clock -name sdram_clk -source pll|altpll_component|auto_generated|pll1|clk[1] -divide_by 1 -multiply_by 1 [get_ports {sdram_0_clk}] 56 | create_generated_clock -name flash_se_clk -source pll|altpll_component|auto_generated|pll1|clk[0] -divide_by 2 -multiply_by 1 [get_pins {recon_2:comb_4|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q}] 57 | 58 | #************************************************************** 59 | # Set Clock Latency 60 | #************************************************************** 61 | 62 | 63 | 64 | #************************************************************** 65 | # Set Clock Uncertainty 66 | #************************************************************** 67 | 68 | 69 | 70 | #************************************************************** 71 | # Set Input Delay 72 | #************************************************************** 73 | #From the datasheet, tac = 6ns 74 | set_input_delay -clock {sdram_clk} 6 [get_ports {sdram_0_dq[0] sdram_0_dq[1] sdram_0_dq[2] sdram_0_dq[3] sdram_0_dq[4] sdram_0_dq[5] sdram_0_dq[6] sdram_0_dq[7] sdram_0_dq[8] sdram_0_dq[9] sdram_0_dq[10] sdram_0_dq[11] sdram_0_dq[12] sdram_0_dq[13] sdram_0_dq[14] sdram_0_dq[15]}] 75 | 76 | set_input_delay -clock { altera_reserved_tck } 10 [get_ports {altera_reserved_tdi}] 77 | set_input_delay -clock { altera_reserved_tck } 10 [get_ports {altera_reserved_tms}] 78 | 79 | #************************************************************** 80 | # Set Output Delay 81 | #************************************************************** 82 | #From the datasheet, tds = 1.5ns 83 | set_output_delay -clock {sdram_clk} 1.5 [get_ports {sdram_0_addr[0] sdram_0_addr[1] sdram_0_addr[2] sdram_0_addr[3] sdram_0_addr[4] sdram_0_addr[5] sdram_0_addr[6] sdram_0_addr[7] sdram_0_addr[8] sdram_0_addr[9] sdram_0_addr[10] sdram_0_addr[11] sdram_0_ba[0] sdram_0_ba[1] sdram_0_cas_n sdram_0_cke sdram_0_cs_n sdram_0_dq[0] sdram_0_dq[1] sdram_0_dq[2] sdram_0_dq[3] sdram_0_dq[4] sdram_0_dq[5] sdram_0_dq[6] sdram_0_dq[7] sdram_0_dq[8] sdram_0_dq[9] sdram_0_dq[10] sdram_0_dq[11] sdram_0_dq[12] sdram_0_dq[13] sdram_0_dq[14] sdram_0_dq[15] sdram_0_dqm[0] sdram_0_dqm[1] sdram_0_ras_n sdram_0_we_n}] 84 | 85 | set_output_delay -clock { altera_reserved_tck } 10 [get_ports {altera_reserved_tdo}] 86 | 87 | 88 | #************************************************************** 89 | # Set Clock Groups 90 | #************************************************************** 91 | 92 | set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 93 | 94 | 95 | #************************************************************** 96 | # Set False Path 97 | #************************************************************** 98 | set_false_path -from [get_ports {port_0_io[0] port_0_io[1] port_0_io[2] port_0_io[3] port_0_io[4] port_0_io[5] port_0_io[6] port_0_io[7] port_0_io[8] port_0_io[9] port_0_io[10] port_0_io[11] port_0_io[12] port_0_io[13] port_0_io[14] port_0_io[15] port_0_io[16] port_0_io[17] port_0_io[18] port_0_io[19] port_0_io[20] port_0_io[21] port_0_io[22] port_0_io[23] port_0_io[24] port_0_io[25] port_0_io[26] port_0_io[27] port_0_io[28] port_0_io[29] port_0_io[30] port_0_io[31] uart_0_rxd uart_0_txd sys_rstn}] 99 | set_false_path -to [get_ports {port_0_io[0] port_0_io[1] port_0_io[2] port_0_io[3] port_0_io[4] port_0_io[5] port_0_io[6] port_0_io[7] port_0_io[8] port_0_io[9] port_0_io[10] port_0_io[11] port_0_io[12] port_0_io[13] port_0_io[14] port_0_io[15] port_0_io[16] port_0_io[17] port_0_io[18] port_0_io[19] port_0_io[20] port_0_io[21] port_0_io[22] port_0_io[23] port_0_io[24] port_0_io[25] port_0_io[26] port_0_io[27] port_0_io[28] port_0_io[29] port_0_io[30] port_0_io[31] uart_0_rxd uart_0_txd sys_rstn}] 100 | 101 | #************************************************************** 102 | # Set Multicycle Path 103 | #************************************************************** 104 | 105 | 106 | 107 | #************************************************************** 108 | # Set Maximum Delay 109 | #************************************************************** 110 | 111 | 112 | #************************************************************** 113 | # Set Minimum Delay 114 | #************************************************************** 115 | 116 | 117 | 118 | #************************************************************** 119 | # Set Input Transition 120 | #************************************************************** 121 | 122 | 123 | 124 | #************************************************************** 125 | # Set Net Delay 126 | #************************************************************** 127 | 128 | -------------------------------------------------------------------------------- /hw/recon_2/max1000/output_files/recon_2.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jefflieu/recon/e89ac37aa8fe5b76281c6af2ec8dd8d458510bbb/hw/recon_2/max1000/output_files/recon_2.sof -------------------------------------------------------------------------------- /hw/recon_2/max1000/recon_2.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 22 | # Date created = 23:28:18 May 18, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "16.0" 27 | DATE = "23:28:18 May 18, 2017" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "recon_2" 32 | -------------------------------------------------------------------------------- /hw/recon_2/max1000/recon_2.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus Prime License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition 22 | # Date created = 23:28:19 May 18, 2017 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # recon_0_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus Prime software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "MAX 10" 41 | set_global_assignment -name DEVICE 10M08SAU169C8G 42 | set_global_assignment -name TOP_LEVEL_ENTITY recon_2_top 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:28:18 MAY 18, 2017" 45 | set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 50 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 51 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 52 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 53 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 54 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 55 | 56 | 57 | 58 | set_location_assignment PIN_E6 -to sys_rstn 59 | set_location_assignment PIN_H6 -to sys_clk 60 | set_location_assignment PIN_B4 -to uart_0_txd 61 | set_location_assignment PIN_A4 -to uart_0_rxd 62 | set_location_assignment PIN_H8 -to port_0_io[0] 63 | set_location_assignment PIN_K10 -to port_0_io[1] 64 | set_location_assignment PIN_H5 -to port_0_io[2] 65 | set_location_assignment PIN_H4 -to port_0_io[3] 66 | set_location_assignment PIN_J1 -to port_0_io[4] 67 | set_location_assignment PIN_J2 -to port_0_io[5] 68 | set_location_assignment PIN_L12 -to port_0_io[6] 69 | set_location_assignment PIN_J12 -to port_0_io[7] 70 | set_location_assignment PIN_J13 -to port_0_io[8] 71 | set_location_assignment PIN_K11 -to port_0_io[9] 72 | set_location_assignment PIN_K12 -to port_0_io[10] 73 | set_location_assignment PIN_J10 -to port_0_io[11] 74 | set_location_assignment PIN_H10 -to port_0_io[12] 75 | set_location_assignment PIN_H13 -to port_0_io[13] 76 | set_location_assignment PIN_G12 -to port_0_io[14] 77 | 78 | 79 | 80 | set_global_assignment -name ENABLE_OCT_DONE OFF 81 | set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 82 | set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" 83 | set_global_assignment -name USE_CONFIGURATION_DEVICE OFF 84 | set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE" 85 | set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF 86 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise 87 | set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall 88 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise 89 | set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall 90 | set_global_assignment -name ENABLE_SIGNALTAP OFF 91 | set_global_assignment -name USE_SIGNALTAP_FILE logic_analyzer/cpu.stp 92 | 93 | 94 | set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON 95 | set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" 96 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 97 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 98 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[*] 100 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[14] 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[13] 102 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[12] 103 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[11] 104 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[10] 105 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[9] 106 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[8] 107 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[7] 108 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[6] 109 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[5] 110 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[4] 111 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[3] 112 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[2] 113 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[1] 114 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_0_io[0] 115 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sys_clk 116 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sys_rstn 117 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart_0_txd 118 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart_0_rxd 119 | set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to port_0_io[*] 120 | set_global_assignment -name IP_SEARCH_PATHS ..\\..\\cmn 121 | set_location_assignment PIN_M10 -to sdram_0_addr[11] 122 | set_location_assignment PIN_L10 -to sdram_0_addr[7] 123 | set_location_assignment PIN_J8 -to sdram_0_addr[3] 124 | set_location_assignment PIN_M11 -to sdram_0_addr[5] 125 | set_location_assignment PIN_N10 -to sdram_0_addr[4] 126 | set_location_assignment PIN_N9 -to sdram_0_addr[6] 127 | set_location_assignment PIN_M13 -to sdram_0_addr[8] 128 | set_location_assignment PIN_N8 -to sdram_0_addr[9] 129 | set_location_assignment PIN_N4 -to sdram_0_addr[10] 130 | set_location_assignment PIN_N5 -to sdram_0_addr[2] 131 | set_location_assignment PIN_M5 -to sdram_0_addr[1] 132 | set_location_assignment PIN_K6 -to sdram_0_addr[0] 133 | set_location_assignment PIN_N7 -to sdram_0_cas_n 134 | set_location_assignment PIN_M7 -to sdram_0_ras_n 135 | set_location_assignment PIN_N6 -to sdram_0_ba[0] 136 | set_location_assignment PIN_K8 -to sdram_0_ba[1] 137 | set_location_assignment PIN_K7 -to sdram_0_we_n 138 | set_location_assignment PIN_E9 -to sdram_0_dqm[0] 139 | set_location_assignment PIN_F12 -to sdram_0_dqm[1] 140 | set_location_assignment PIN_M8 -to sdram_0_cke 141 | set_location_assignment PIN_M9 -to sdram_0_clk 142 | set_location_assignment PIN_M4 -to sdram_0_cs_n 143 | set_location_assignment PIN_G9 -to sdram_0_dq[6] 144 | set_location_assignment PIN_G10 -to sdram_0_dq[1] 145 | set_location_assignment PIN_F13 -to sdram_0_dq[8] 146 | set_location_assignment PIN_E13 -to sdram_0_dq[10] 147 | set_location_assignment PIN_E12 -to sdram_0_dq[9] 148 | set_location_assignment PIN_F9 -to sdram_0_dq[3] 149 | set_location_assignment PIN_F10 -to sdram_0_dq[2] 150 | set_location_assignment PIN_F8 -to sdram_0_dq[7] 151 | set_location_assignment PIN_B12 -to sdram_0_dq[13] 152 | set_location_assignment PIN_C12 -to sdram_0_dq[12] 153 | set_location_assignment PIN_B13 -to sdram_0_dq[14] 154 | set_location_assignment PIN_A12 -to sdram_0_dq[15] 155 | set_location_assignment PIN_E10 -to sdram_0_dq[4] 156 | set_location_assignment PIN_D9 -to sdram_0_dq[5] 157 | set_location_assignment PIN_D12 -to sdram_0_dq[11] 158 | set_location_assignment PIN_D11 -to sdram_0_dq[0] 159 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[11] 160 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[10] 161 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[9] 162 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[8] 163 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[7] 164 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[6] 165 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[5] 166 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[4] 167 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[3] 168 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[2] 169 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[1] 170 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_addr[0] 171 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_ba[1] 172 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_ba[0] 173 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_cas_n 174 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_cke 175 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_clk 176 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_cs_n 177 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[15] 178 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[14] 179 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[13] 180 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[12] 181 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[11] 182 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[10] 183 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[9] 184 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[8] 185 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[7] 186 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[6] 187 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[5] 188 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[4] 189 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[3] 190 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[2] 191 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[1] 192 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dq[0] 193 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dqm[1] 194 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_dqm[0] 195 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_ras_n 196 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdram_0_we_n 197 | set_global_assignment -name QIP_FILE alt_ip/alt_ddr.qip 198 | set_global_assignment -name SDC_FILE constraints/recon_2.sdc 199 | set_global_assignment -name VERILOG_FILE ../recon_2_top.v 200 | set_global_assignment -name QSYS_FILE ../recon_2.qsys 201 | set_global_assignment -name QIP_FILE ../../cmn/util/recon_util.qip 202 | set_global_assignment -name QIP_FILE alt_ip/alt_pll.qip 203 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /hw/recon_2/recon_2_top.v: -------------------------------------------------------------------------------- 1 | /* 2 | Project: RECON 2018 3 | Author: Jeff Lieu 4 | Description: recon_2_top level 5 | */ 6 | 7 | /* Note that the PORT_0_WIDTH doesn't propagate to the NIOS system */ 8 | module recon_2_top #(parameter PORT_0_WIDTH = 32) ( 9 | input sys_clk, 10 | input sys_rstn, 11 | 12 | inout [ PORT_0_WIDTH-1:0] port_0_io, 13 | output uart_0_txd, 14 | input uart_0_rxd, 15 | 16 | output sdram_0_clk, 17 | output [11:0] sdram_0_addr, 18 | output [1:0] sdram_0_ba, 19 | output sdram_0_cas_n, 20 | output sdram_0_cke, 21 | output sdram_0_cs_n, 22 | inout [15:0] sdram_0_dq, 23 | output [1:0] sdram_0_dqm, 24 | output sdram_0_ras_n, 25 | output sdram_0_we_n 26 | ); 27 | 28 | wire [PORT_0_WIDTH-1:0] port_0_out; 29 | wire [PORT_0_WIDTH-1:0] port_0_in; 30 | wire [PORT_0_WIDTH-1:0] port_0_oe; 31 | wire [PORT_0_WIDTH-1:0] port_0_opdrn; 32 | wire cpu_clk, locked; 33 | wire sdram_clk; 34 | reg sdram_clk_reg; 35 | 36 | /* 37 | PLL is put at the top to be shared across boards 38 | THe output of the CPU clock is required to be 80MHz 39 | */ 40 | alt_pll pll( 41 | .areset (~sys_rstn), 42 | .inclk0 (sys_clk), 43 | .c0 (cpu_clk), 44 | .c1 (sdram_clk), 45 | .locked (locked)); 46 | 47 | alt_ddr sdram_clk_io( 48 | .outclock (sdram_clk) , // outclock.export 49 | .din (2'b01) , // din.export 50 | .pad_out (sdram_0_clk) // pad_out.export 51 | ); 52 | 53 | 54 | 55 | buttonDebouncer 56 | #( /* Debounce time - Count in nanosecond */ 57 | .pDEBOUNCE_PERIOD (100_000_000), 58 | /* Clock Input period - Count in nanosecond */ 59 | .pCLKIN_PERIOD (20 ), 60 | /* Size of button array */ 61 | .pARRAY_SIZE (1 ), 62 | /* 63 | Polarity configures the edge detection which edge would cause a tick 64 | Buttons are default to active low, which means a "Button Down" event is generated when the signal level fall from High to Low 65 | Active high (pPOLARITY = 1) means a Button Down when the signal level changes from Low to High 66 | */ 67 | .pPOLARITY (0)) resetDebounce 68 | ( 69 | .clk (sys_clk), 70 | .buttons (sys_rstn), 71 | .buttonState (sys_rstn_db), /* In Verilog, you can have an implied net declaration */ 72 | .buttonUpTick (), 73 | .buttonDwTick () 74 | ); 75 | 76 | /* NIOS System - Configured and Generated by QSYS */ 77 | recon_2 ( 78 | .clk_clk (cpu_clk), // clk.clk 79 | .recon_io_0_io_port_io_out (port_0_out), // recon_io_0_io_port.io_out 80 | .recon_io_0_io_port_io_opdrn (port_0_opdrn), // .io_opdrn 81 | .recon_io_0_io_port_io_in (port_0_in), // .io_in 82 | .recon_io_0_io_port_io_oe (port_0_oe), // .io_oe 83 | .recon_timer_0_clock_tick_second (), // recon_timer_0_clock_tick.second 84 | .recon_timer_0_clock_tick_millisecond (), // .millisecond 85 | .recon_timer_0_clock_tick_microsec (), // .microsec 86 | .reset_reset_n (sys_rstn_db), // reset.reset_n 87 | .uart_0_rxd (uart_0_rxd), 88 | .uart_0_txd (uart_0_txd), 89 | .sdram_0_addr (sdram_0_addr ), 90 | .sdram_0_ba (sdram_0_ba ), 91 | .sdram_0_cas_n (sdram_0_cas_n), 92 | .sdram_0_cke (sdram_0_cke ), 93 | .sdram_0_cs_n (sdram_0_cs_n ), 94 | .sdram_0_dq (sdram_0_dq ), 95 | .sdram_0_dqm (sdram_0_dqm ), 96 | .sdram_0_ras_n (sdram_0_ras_n), 97 | .sdram_0_we_n (sdram_0_we_n ) 98 | ); 99 | /* You can Insert your own Debouncer for the Button Here if required */ 100 | genvar IO; 101 | generate 102 | for (IO = 0; IO 5 | #include "recon_types.h" 6 | 7 | #ifdef __ALTERA_MODULAR_ADC 8 | 9 | /** 10 | This class targets Altera's on chip ADC core 11 | */ 12 | #include "ReconADCHwDescription.h" 13 | 14 | #define SEQUENCER_REG(R) HWREG32(m_sequencerBaseAddress + R) 15 | #define SAMPLES_REG(R) HWREG32(m_storageBaseAddress + SAMPLE_STORAGE_REG+(R<<2)) 16 | 17 | class ReconADC { 18 | 19 | public: 20 | ReconADC(){}; 21 | ~ReconADC(){}; 22 | 23 | 24 | /** 25 | m_AnaloguePinMap maps the PIN number (index) to the Sequencer's slot number 26 | */ 27 | u32 m_AnaloguePinMap[ADC_0_SAMPLE_STORE_CSR_CSD_LENGTH]; 28 | 29 | /** 30 | The ADC object has to be "bound" to a physical hardware by giving 31 | @sequencer_base : base address of the sequencer, you'll find it in the system.h file if your system contains Sequencer block 32 | @storage_base : base address of the conversion results 33 | */ 34 | void bind(u32 sequencer_base, u32 storage_base) {m_sequencerBaseAddress = sequencer_base; m_storageBaseAddress = storage_base;}; 35 | 36 | /** 37 | setModeRunOnce and setModeRunContinuous set the mode of the sequencer: 38 | run once : perform one conversion from slot 0 to slot ADC_0_SAMPLE_STORE_CSR_CSD_LENGTH 39 | run continuous : keep doing conversion in the back ground 40 | */ 41 | void setModeRunOnce() {m_modeContinuous = false; SEQUENCER_REG(SEQUENCER_CMD_REG) = SEQUENCER_CMD_MODE_ONCE & SEQUENCER_CMD_MODE_MSK;}; 42 | void setModeRunContinuous() {m_modeContinuous = true; SEQUENCER_REG(SEQUENCER_CMD_REG) = SEQUENCER_CMD_MODE_CONTINUOUS & SEQUENCER_CMD_MODE_MSK;}; 43 | 44 | /** 45 | startConversion : trigger the sequencer start a conversion 46 | stopConversion : wait for the RUN bit to be cleared 47 | */ 48 | void startConversion() {SEQUENCER_REG(SEQUENCER_CMD_REG) = SEQUENCER_CMD_RUN_START & SEQUENCER_CMD_RUN_MSK;}; 49 | void stopConversion() { SEQUENCER_REG(SEQUENCER_CMD_REG) = SEQUENCER_CMD_RUN_STOP & SEQUENCER_CMD_RUN_MSK; 50 | while(SEQUENCER_REG(SEQUENCER_CMD_REG) & SEQUENCER_CMD_RUN_MSK);}; 51 | 52 | /** 53 | When FPGA can have dual ADC block, the results are organized into upper and lower 16-bit of the 32-bit register 54 | readADC1 returns the lower 16-bit at the slot 55 | readADC2 returns the upper 16-bit at the slot 56 | */ 57 | u32 readADC1(u32 slot) {return SAMPLES_REG(slot) & 0x00000FFF;}; 58 | u32 readADC2(u32 slot) {return (SAMPLES_REG(slot) & 0x0FFF0000)>>16;}; 59 | 60 | /** 61 | Helper to check mode and do pin to channel mapping 62 | */ 63 | bool isContinuous() {return m_modeContinuous;}; 64 | void pinRemap(u32 pin, u32 slot) {m_AnaloguePinMap[pin] = slot;}; 65 | 66 | /** 67 | Read analogue value from a pin 68 | */ 69 | u32 analogRead(u32 pin); 70 | 71 | void enableInterrupt() {HWREG32(m_storageBaseAddress+SAMPLE_STORAGE_IRQ_ENABLE_REG)=SAMPLE_STORAGE_IRQ_ENABLED;} 72 | void disableInterrupt(){HWREG32(m_storageBaseAddress+SAMPLE_STORAGE_IRQ_ENABLE_REG)=SAMPLE_STORAGE_IRQ_DISABLED;} 73 | u32 readIrqStatus() {return HWREG32(m_storageBaseAddress+SAMPLE_STORAGE_IRQ_STATUS_REG);} 74 | void clrIrqStatus(u32 statusMask) {HWREG32(m_storageBaseAddress+SAMPLE_STORAGE_IRQ_STATUS_REG) = statusMask;} 75 | 76 | private: 77 | bool m_modeContinuous; 78 | u32 m_sequencerBaseAddress; 79 | u32 m_storageBaseAddress; 80 | }; 81 | 82 | #endif 83 | #endif 84 | -------------------------------------------------------------------------------- /sw/cmn/adc/ReconADCHwDescription.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | Created by Jeff Lieu 3 | ******************************************************************************/ 4 | 5 | #ifndef __RECON_ADC_HW_DESCRIPTION__ 6 | #define __RECON_ADC_HW_DESCRIPTION__ 7 | 8 | #include 9 | 10 | /* 11 | * Sequencer Core Command Register Register 12 | */ 13 | #define SEQUENCER_CMD_REG 0 14 | #define SEQUENCER_CMD_MSK (0x0000000F) 15 | 16 | #define SEQUENCER_CMD_RUN_MSK (0x00000001) 17 | #define SEQUENCER_CMD_RUN_START (0x00000001) 18 | #define SEQUENCER_CMD_RUN_STOP (0x00000000) 19 | 20 | #define SEQUENCER_CMD_MODE_MSK (0x0000000E) 21 | #define SEQUENCER_CMD_MODE_CONTINUOUS (0x00000000) 22 | #define SEQUENCER_CMD_MODE_ONCE (0x00000002) 23 | #define SEQUENCER_CMD_MODE_RECALIBRATE (0x0000000E) 24 | 25 | 26 | 27 | /* 28 | * IO Read Write helper Macros 29 | */ 30 | #define READ_CMD_REG(base) \ 31 | HWREG32(base+SEQUENCER_CMD_REG) 32 | 33 | #define WRITE_CMD_REG(base, data) \ 34 | do {HWREG32(base + SEQUENCER_CMD_REG) = data;} while (0) 35 | 36 | 37 | /* 38 | * RUN - START/STOP helper Macros 39 | */ 40 | #define READ_CMD_RUN_REG(base) \ 41 | READ_CMD_REG(base) \ 42 | & SEQUENCER_CMD_RUN_MSK 43 | 44 | /* 45 | To Start the Sequencer Core 46 | */ 47 | #define SEQUENCER_START(base) \ 48 | WRITE_CMD_REG(base, ( \ 49 | READ_CMD_REG(base) \ 50 | & ~(SEQUENCER_CMD_RUN_MSK) ) \ 51 | | SEQUENCER_CMD_RUN_START) 52 | 53 | /* 54 | To Stop the Sequencer Core 55 | Step: 56 | 1. Write 0 to RUN bit 57 | 2. Poll the RUN bit until it read 0. 58 | */ 59 | #define SEQUENCER_STOP(base) \ 60 | do { \ 61 | WRITE_CMD_REG(base, ( \ 62 | READ_CMD_REG(base) \ 63 | & ~(SEQUENCER_CMD_RUN_MSK)) \ 64 | | SEQUENCER_CMD_RUN_STOP); \ 65 | while( \ 66 | READ_CMD_REG(base) \ 67 | & SEQUENCER_CMD_RUN_MSK); \ 68 | } while (0) 69 | 70 | 71 | 72 | /* 73 | * MODE - ONCE/CONTINUOUS helper Macros 74 | */ 75 | 76 | /* 77 | Set sequencer to run once only 78 | */ 79 | #define SEQUENCER_MODE_RUN_ONCE(base) \ 80 | WRITE_CMD_REG(base, ( \ 81 | READ_CMD_REG(base) \ 82 | & ~(SEQUENCER_CMD_MODE_MSK) ) \ 83 | | SEQUENCER_CMD_MODE_ONCE) 84 | 85 | /* 86 | Set sequencer to run continuously 87 | */ 88 | #define SEQUENCER_MODE_RUN_CONTINUOUSLY(base) \ 89 | WRITE_CMD_REG(base, ( \ 90 | READ_CMD_REG(base) \ 91 | & ~(SEQUENCER_CMD_MODE_MSK) ) \ 92 | | SEQUENCER_CMD_MODE_CONTINUOUS) 93 | 94 | /* 95 | Set sequencer to recalibration mode 96 | */ 97 | #define SEQUENCER_MODE_RUN_RECALIBRATION(base) \ 98 | WRITE_CMD_REG(base, ( \ 99 | READ_CMD_REG(base) \ 100 | & ~(SEQUENCER_CMD_MODE_MSK) ) \ 101 | | SEQUENCER_CMD_MODE_RECALIBRATE) 102 | 103 | 104 | /** 105 | Sample storage space 106 | */ 107 | #define SAMPLE_STORAGE_REG 0 108 | #define SAMPLE_STORAGE_MSK (0x00000FFF) 109 | #define SAMPLE_STORAGE_FIRST_SLOT 0 110 | #define SAMPLE_STORAGE_LAST_SLOT 63 111 | 112 | #define SAMPLE_STORAGE_IRQ_ENABLE_REG 0x40 113 | #define SAMPLE_STORAGE_IRQ_ENABLE_MSK (0x00000001) 114 | #define SAMPLE_STORAGE_IRQ_ENABLED (0x00000001) 115 | #define SAMPLE_STORAGE_IRQ_DISABLED (0x00000000) 116 | #define SAMPLE_STORAGE_IRQ_STATUS_REG 0x44 117 | 118 | #endif /* __RECON_ADC_HW_DESCRIPTION__ */ 119 | -------------------------------------------------------------------------------- /sw/cmn/io/recon_io.c: -------------------------------------------------------------------------------- 1 | /* 2 | * recon_io.c 3 | * 4 | * Created on: Apr 22, 2017 5 | * Author: jeff 6 | */ 7 | #include "recon_types.h" 8 | #include "recon_io.h" 9 | /** 10 | * set mode of pin 11 | * @param pin : pin number 12 | * @param mode : INPUT|OUTPUT|OUTPWM 13 | * @return none 14 | */ 15 | void pinMode(u32 pin, u32 mode) 16 | { 17 | u32 pinmode = recon_io_rd32(PINMODE); 18 | u32 pwm_ena = recon_io_rd32(PWM_ENA); 19 | u32 pinMask = (1<>pin)&0x1); 52 | } 53 | 54 | /** 55 | * set Pulse Width Modulation Value for pin 56 | * @param pin : pin number 57 | * @param value : valid values range on PWM Period settings 58 | * value should always be smaller than or equal to Period Settings 59 | * @return none 60 | */ 61 | void analogWrite(u32 pin, u32 value) 62 | { 63 | u32 addr = PWM_VALUE + ((pin&0x1F)<<2); 64 | recon_io_wr32(addr,value); 65 | } 66 | 67 | /** 68 | * Enable Interrupts for pin 69 | * @param pin : pin number 70 | * @param value : RISING_EDGE or FALLING_EDGE or both 71 | * @return none 72 | */ 73 | void pinInterrupt(u32 pin, u32 value) 74 | { u32 tmp = recon_io_rd32(IRQ_REDGE); 75 | u32 pinMask = 1< 10 | #include 11 | #include 12 | #include 13 | recon_serial::recon_serial(){ 14 | } 15 | void recon_serial::bind(u32 base){ 16 | m_baseAddress = base; 17 | } 18 | u32 recon_serial::putstr(const s8* c) 19 | { 20 | u32 i = 0; 21 | while(c[i]!='\0'){ 22 | putc(c[i]); 23 | i++; 24 | } 25 | return i; 26 | } 27 | 28 | void recon_serial::print(const s8* arg) 29 | { 30 | putstr(arg); 31 | } 32 | 33 | void recon_serial::print(const float f) 34 | { 35 | char buffer[64]; 36 | /* 37 | * We need to rely on system sprintf function for floating point implementation 38 | * If you don't mind the code size, you can use it 39 | */ 40 | //sprintf(buffer,"%f",f); 41 | //putstr(buffer); 42 | } 43 | 44 | void recon_serial::print(const u32 d, u32 base) 45 | { 46 | u32 m = 1000000000; 47 | u32 a, t; 48 | u32 lead_zero; 49 | t = d; 50 | lead_zero = 1; 51 | if (base==HEX) {printh(d); return;} 52 | while(m>0){ 53 | if (t>m) {a = t/m; 54 | putc(a+48); 55 | lead_zero = 0;} 56 | else if (t==m) {putc(49); lead_zero = 0;} 57 | else putc(lead_zero&&(m>1)?' ':'0'); 58 | t = t%m; 59 | m = m/10; 60 | } 61 | } 62 | 63 | void recon_serial::print(const s32 d, u32 base) 64 | { 65 | u32 m = 1000000000; 66 | u32 t,a; 67 | u32 lead_zero; 68 | u32 negative; 69 | t = d>0?d:-d; 70 | negative = d>=0?0:1; 71 | lead_zero = 1; 72 | if (base==HEX) {printh(d); return;} 73 | while(m>0){ 74 | if (t>m) {a = t/m; 75 | if (lead_zero==1&&negative==1) putc('-'); 76 | putc(a+48); 77 | lead_zero = 0; 78 | } 79 | else if (t==m) {if (lead_zero==1&&negative==1) putc('-'); putc(49); lead_zero = 0; 80 | } 81 | else putc(lead_zero&&(m>1)?' ':'0'); 82 | t = t%m; 83 | m = m/10; 84 | } 85 | } 86 | 87 | void recon_serial::printh(u32 d) 88 | { 89 | s32 m = 28; 90 | u32 t,a; 91 | u32 lead_zero; 92 | t = d; 93 | lead_zero = 1; 94 | while(m>=0){ 95 | a = (t >> m) & 0xF; 96 | if(a!=0){ 97 | if (a<=9) putc(a+'0'); else 98 | putc((a-10)+'A'); 99 | lead_zero = 0; 100 | } 101 | else putc(lead_zero&&m>0?' ':'0'); 102 | m = m - 4; 103 | } 104 | } 105 | 106 | void recon_serial::printb(u32 d) 107 | { 108 | s32 m = 31; 109 | u32 t,a; 110 | u32 lead_zero; 111 | t = d; 112 | lead_zero = 1; 113 | while(m>=0){ 114 | a = (t >> m) & 0x1; 115 | if(a!=0){ 116 | putc('1'); 117 | lead_zero = 0; 118 | } 119 | else putc(lead_zero&&m>0?' ':'0'); 120 | m = m - 1; 121 | } 122 | } 123 | 124 | 125 | 126 | void inline recon_serial::putc(const s8 c) 127 | { 128 | while((IORD_ALTERA_AVALON_UART_STATUS(m_baseAddress)& 129 | ALTERA_AVALON_UART_STATUS_TRDY_MSK)==0); 130 | IOWR_ALTERA_AVALON_UART_TXDATA(m_baseAddress,c); 131 | } 132 | 133 | void recon_serial::println(const s8* s) 134 | { 135 | print(s); 136 | putc('\r'); 137 | putc('\n'); 138 | } 139 | 140 | void recon_serial::println(const u32 d, u32 base) 141 | { 142 | print(d, base); 143 | putc('\r'); 144 | putc('\n'); 145 | } 146 | 147 | void recon_serial::println(const s32 d, u32 base) 148 | { 149 | print(d, base); 150 | putc('\r'); 151 | putc('\n'); 152 | } 153 | 154 | void recon_serial::println(const float f) 155 | { 156 | print(f); 157 | putc('\r'); 158 | putc('\n'); 159 | } 160 | 161 | void recon_serial::begin(u32 baud) 162 | { 163 | u16 div = UART_0_FREQ/baud; 164 | IOWR_ALTERA_AVALON_UART_DIVISOR(m_baseAddress,div); 165 | } 166 | 167 | recon_serial::~recon_serial() 168 | { 169 | } 170 | -------------------------------------------------------------------------------- /sw/cmn/serial/recon_serial.h: -------------------------------------------------------------------------------- 1 | /* 2 | * serial.h 3 | * 4 | * Created on: Apr 27, 2017 5 | * Author: jeff 6 | * This serial class provides some basic print-out capability that is similar to Arduino platform 7 | * You can use the printf instead. 8 | */ 9 | 10 | #ifndef SERIAL_H_ 11 | #define SERIAL_H_ 12 | 13 | #include "recon_types.h" 14 | #define DEC 0 15 | #define BIN 1 16 | #define HEX 2 17 | 18 | extern "C" { 19 | 20 | class recon_serial { 21 | public: 22 | recon_serial(); 23 | ~recon_serial(); 24 | 25 | u32 m_baseAddress; 26 | void bind(u32 base); 27 | void begin(u32 baud); 28 | u32 putstr(const s8* c); 29 | void putc(const s8 c); 30 | void print(const s8* s); 31 | void print(const u32 d, u32 = 0); 32 | void print(const s32 d, u32 =0 ); 33 | void printh(const u32 d); 34 | void printb(const u32 d); 35 | void print(const float f); 36 | void println(const s8* s); 37 | void println(const u32 d, u32 = 0); 38 | void println(const s32 d, u32 =0 ); 39 | void println(const float f); 40 | }; 41 | 42 | } 43 | #endif /* SERIAL_H_ */ 44 | -------------------------------------------------------------------------------- /sw/cmn/timer/recon_timer.c: -------------------------------------------------------------------------------- 1 | /* 2 | * recon_timer.c 3 | * 4 | * Created on: Apr 23, 2017 5 | * Author: jeff 6 | */ 7 | #include "recon_timer.h" 8 | 9 | /* Note: 10 | * The 32-bit millisecond counter will roll over in about 49 days 11 | * If your application runs that long or you need to delay more than 25 days, 12 | * you should use delay second 13 | */ 14 | void delay(u32 time) 15 | { 16 | u32 expire_time = RECON_TIMER_MS + time; 17 | while(RECON_TIMER_MS 2 | 3 | void setup() 4 | { 5 | /* Put your setup code here */ 6 | } 7 | 8 | void loop() 9 | { 10 | /* Put your code that will be repeatedly call here */ 11 | } 12 | -------------------------------------------------------------------------------- /sw/cmn/util/main_template: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | void setup(); 6 | void loop(); 7 | 8 | int main(void) 9 | { 10 | alt_sys_init(); 11 | alt_irq_init(0); 12 | 13 | setup(); 14 | 15 | while(1) 16 | { 17 | loop(); 18 | } 19 | 20 | } 21 | 22 | -------------------------------------------------------------------------------- /sw/cmn/util/recon_types.h: -------------------------------------------------------------------------------- 1 | /* 2 | * recon_types.h 3 | * 4 | * Created on: Apr 27, 2017 5 | * Author: jeff 6 | */ 7 | 8 | #ifndef RECON_TYPES_H_ 9 | #define RECON_TYPES_H_ 10 | 11 | typedef unsigned long u32; 12 | typedef long s32; 13 | typedef unsigned char u8; 14 | typedef char s8; 15 | typedef unsigned short u16; 16 | typedef short s16; 17 | 18 | #define HWREG(R) (*(volatile u32*)(R)) 19 | #define HWREG32(R) (*(volatile u32*)(R)) 20 | #define HWREG16(R) (*(volatile u16*)(R)) 21 | #define HWREG8(R) (*(volatile u8*)(R)) 22 | 23 | #endif /* RECON_TYPES_H_ */ 24 | -------------------------------------------------------------------------------- /sw/examples/adc_read/src/app.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include "recon_timer.h" 4 | #include "ReconADC.h" 5 | #include "recon_serial.h" 6 | #include "kits_parameters.h" 7 | 8 | recon_serial Serial; 9 | ReconADC Adc; 10 | 11 | #define analogRead(X) Adc.analogRead(X) 12 | 13 | void setup() 14 | { 15 | /* Put your setup code here */ 16 | 17 | /////////////////////////////////////////////////////////////////////////////////// 18 | // Adc class is defined in the cmn/adc and compiled into the static library 19 | // To use Adc object, we need to "bind" it to the hardware which is .bind method 20 | // and pass in base address of the sequencer and base address of the Sample storage 21 | // Refer to the ReconADC.h for more details of supported method 22 | Adc.bind(ADC_0_SEQUENCER_CSR_BASE, ADC_0_SAMPLE_STORE_CSR_BASE); 23 | 24 | /////////////////////////////////////////////////////////////////////////////////// 25 | // pinRemap method maps the pin number to correct analogue channel 26 | // For example, for max1000 board, AIN0 = 8. 27 | // The definition is created the .h file 28 | // The file is only included when you have correct BOARD_NAME set during make create_app 29 | Adc.pinRemap(0, AIN0); 30 | Adc.setModeRunOnce(); 31 | 32 | /////////////////////////////////////////////////////////////////////////////////// 33 | // Bind and initialize the Serial 34 | Serial.bind(UART_0_BASE); 35 | Serial.begin(115200); 36 | } 37 | 38 | void loop() 39 | { 40 | /* Put your code that will be repeatedly call here */ 41 | u32 val; 42 | delay(100); 43 | val = analogRead(0); 44 | Serial.println(val,DEC); 45 | } 46 | -------------------------------------------------------------------------------- /sw/examples/adc_read/src/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | void setup(); 6 | void loop(); 7 | 8 | int main(void) 9 | { 10 | alt_sys_init(); 11 | alt_irq_init(0); 12 | 13 | setup(); 14 | 15 | while(1) 16 | { 17 | loop(); 18 | } 19 | 20 | } 21 | 22 | -------------------------------------------------------------------------------- /sw/examples/frequency_counter/src/app.cpp: -------------------------------------------------------------------------------- 1 | /* Author : Jeff Lieu 2 | * This application counts number of rising edges of one IO pin in 1 second. 3 | * By doing so, it demonstrates: 4 | * - ReconIO PWM/Wave-Generator feature 5 | * - ReconIO module interrupt and ISR 6 | * - ReconTimer interrupt 7 | * - Recon Serial object 8 | * 9 | */ 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | 17 | recon_serial Serial; 18 | u32 freqCntr; 19 | u32 frequency; 20 | u32 timerUp; 21 | 22 | #define PWM_PIN 24 23 | /* 24 | * We put the ISR into the "exception" section 25 | */ 26 | void io_isr(void* context) __attribute__ ((section (".exceptions"))); 27 | void timer_isr(void* context) __attribute__ ((section (".exceptions"))); 28 | 29 | void setup() 30 | { 31 | /* Put your setup code here */ 32 | ///////////////////////////////////////////////////////////////////////////////////////////////// 33 | // Initialize variables 34 | freqCntr = 0; 35 | timerUp = 0; 36 | 37 | ///////////////////////////////////////////////////////////////////////////////////////////////// 38 | // Bind Serial Object to UART_0 component by assigning the base address 39 | Serial.bind(UART_0_BASE); 40 | 41 | ///////////////////////////////////////////////////////////////////////////////////////////////// 42 | // Setup serial object with baudrate 115200 43 | Serial.begin(115200); 44 | 45 | ///////////////////////////////////////////////////////////////////////////////////////////////// 46 | // Setup mode of Pins, we have INPUT, OUTPUT and OUTPWM modes 47 | pinMode(0,OUTPUT); 48 | pinMode(PWM_PIN,OUTPWM); 49 | setPWMPeriod(1000); 50 | analogWrite(PWM_PIN, 200); 51 | 52 | //Note that we always have internal loopback at the pin 53 | //The pin input path is always available even if we set the pin as OUTPUT or OUTPWM 54 | //When the pin is set to INPUT mode, it will then turn off the driving buffer 55 | pinInterrupt(PWM_PIN,RISING_EDGE); 56 | 57 | ///////////////////////////////////////////////////////////////////////////////////////////////// 58 | // Setup Timer interrupt interval = 1000 ms (write 1000-1) 59 | recon_timer_irq_interval(999); 60 | 61 | ///////////////////////////////////////////////////////////////////////////////////////////////// 62 | // Enable timer, count down mode and continuous, i.e timer restarts after reaching the interval 63 | recon_timer_irq_mode(RECON_TIMER_MODE_COUNT_DOWN|RECON_TIMER_MODE_CONTINUOUS); 64 | 65 | ///////////////////////////////////////////////////////////////////////////////////////////////// 66 | // Register Interrupts Service Routines (ISR) 67 | alt_irq_register(RECON_IO_0_IRQ, &freqCntr, (alt_isr_func) io_isr); 68 | alt_irq_register(RECON_TIMER_0_IRQ, &freqCntr, (alt_isr_func) timer_isr); 69 | 70 | ///////////////////////////////////////////////////////////////////////////////////////////////// 71 | // Print out a message 72 | Serial.print("Setup done\r\n"); 73 | } 74 | 75 | void loop() 76 | { 77 | 78 | /* Put your code that will be repeatedly call here */ 79 | if (timerUp==1) 80 | { 81 | Serial.print("Frequency is "); 82 | Serial.println(frequency); 83 | timerUp = 0; 84 | digitalWrite(0, TOGGLE); 85 | } 86 | } 87 | 88 | /* 89 | * ISR that handles IO IRQ 90 | */ 91 | void io_isr(void* freqCntr) 92 | { 93 | /////////////////////////////////////////////// 94 | //Read back which pin is interrupted 95 | u32 pin = recon_io_rd32(IRQ_STATUS); 96 | /////////////////////////////////////////////// 97 | //Clear Interrupt 98 | recon_io_wr32(IRQ_STATUS,pin); 99 | /////////////////////////////////////////////// 100 | // On each interrupt, we increment the counter 101 | (*((u32*)freqCntr))++; 102 | } 103 | 104 | /** 105 | * ISR that handles Timer Interrupt 106 | */ 107 | void timer_isr(void *context) 108 | { 109 | ////////////////////////////////////////// 110 | // Clear Interrupt 111 | RECON_TIMER_STAT = RECON_TIMER_IRQ_BIT; 112 | timerUp = 1; 113 | ////////////////////////////////////////// 114 | // On each interrupt, we latch the current value of frequency counter 115 | // and reset the count 116 | frequency = freqCntr; 117 | freqCntr = 0; 118 | } 119 | -------------------------------------------------------------------------------- /sw/examples/frequency_counter/src/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | 6 | void setup(); 7 | void loop(); 8 | 9 | int main(void) 10 | { 11 | /* Altera sepcific */ 12 | alt_irq_init(0); 13 | alt_sys_init(); 14 | 15 | setup(); 16 | 17 | while(1) 18 | { 19 | loop(); 20 | } 21 | 22 | } 23 | 24 | -------------------------------------------------------------------------------- /sw/recon_0/Makefile: -------------------------------------------------------------------------------- 1 | # Project : RECON 2017 2 | # Author : Jeff Lieu 3 | # Note that you need to be in NIOS2 Command Line Shell to run this Makefile 4 | # This Makefile simplies the process of developing software for FPGA based embedded system 5 | # Type make help for more information 6 | 7 | #Directory hierarchy: 8 | #recon --> hw --> cmn 9 | # ---> io 10 | # ---> timer 11 | # ---> util 12 | # --> recon_0 : 13 | # ---> bemicro_max10 : board specific settings 14 | # An equivalent hierarchy in software branch 15 | #recon --> sw --> cmn 16 | # --> recon_0 17 | # ---> bsp 18 | # ---> lib_recon_0 19 | # ---> , your app can run on the same platform with any board, because the NIOS system is the same 20 | SHELL :=/bin/bash 21 | ROOT = ../.. 22 | SOFTWARE_PATH = $(shell pwd) 23 | PLATFORM_NAME = $(lastword $(subst /, ,$(SOFTWARE_PATH))) 24 | HARDWARE_PATH = $(ROOT)/hw/$(PLATFORM_NAME) 25 | BOARD_NAME = bemicro_max10 26 | 27 | #You need "find" command in your search path. Windows system may have some difficulty. 28 | #Here we search in hardware directories for the SOF files and with the correct BOARD_NAME 29 | #Then select between released sof file and development sof file 30 | REL_SOF_FILE = $(shell find $(HARDWARE_PATH) | grep $(BOARD_NAME)/release/$(PLATFORM_NAME).sof) 31 | DEV_SOF_FILE = $(shell find $(HARDWARE_PATH) | grep $(BOARD_NAME)/output_files/$(PLATFORM_NAME).sof) 32 | SOF_FILE = $(if $(DEV_SOF_FILE),$(DEV_SOF_FILE),${REL_SOF_FILE}) 33 | 34 | #These commands are available in NIOS2-Command-Shell 35 | CREATE_BSP = nios2-bsp 36 | EDIT_BSP = nios2-bsp-editor 37 | CREATE_LIB = nios2-lib-generate-makefile 38 | CREATE_APP = nios2-app-generate-makefile 39 | 40 | BSP_DIR = ./bsp 41 | LIB_DIR = lib_$(PLATFORM_NAME) 42 | APP_NAME = new_app 43 | EX_NAME = frequency_counter 44 | 45 | .phony : help 46 | help : ##Fancy auto help 47 | @IFS=$$'\n' ; \ 48 | help_lines=(`fgrep -h "##" $(MAKEFILE_LIST) | fgrep -v fgrep | sed -e 's/\\$$//'`); \ 49 | for help_line in $${help_lines[@]}; do \ 50 | IFS=$$'#' ; \ 51 | help_split=($$help_line) ; \ 52 | help_command=`echo $${help_split[0]} | sed -e 's/^ *//' -e 's/ *$$//'` ; \ 53 | help_info=`echo $${help_split[2]} | sed -e 's/^ *//' -e 's/ *$$//'` ; \ 54 | printf "%-30s %s\n" $$help_command $$help_info ; \ 55 | done 56 | 57 | .phony : new_bsp edit_bsp update_bsp 58 | new_bsp : ##Generate or Reset BSP settings to defaults. Always use HAL. Ouput to "bsp" directory. SOPC file is fetched from the hardware 59 | $(CREATE_BSP) hal $(BSP_DIR) $(HARDWARE_PATH)/$(PLATFORM_NAME).sopcinfo 60 | 61 | edit_bsp: ##Open the GUI that we can edit the BSP settings. Remember to Save and then Generate it. 62 | -mkdir $(BSP_DIR)/edit_dir 63 | cd $(BSP_DIR) && $(EDIT_BSP) --settings settings.bsp 64 | 65 | update_bsp : ##Update BSP with latest SOPCINFO but keep changes you've made to BSP 66 | $(CREATE_BSP) hal $(BSP_DIR) $(HARDWARE_PATH)/$(PLATFORM_NAME).sopcinfo --default_stdio DONT_CHANGE --default_memory_regions DONT_CHANGE --default_section_regions DONT_CHANGE --default_sys_timer DONT_CHANGE --default_sections_mapping DONT_CHANGE --use_bootloader DONT_CHANGE 67 | 68 | .phony : lib generate_lib 69 | lib : generate_lib 70 | generate_lib: ##Generate library that contains drivers of our custom hardware (not from Altera). 71 | $(CREATE_LIB) --bsp-dir=$(BSP_DIR) --inc-dir=$(ROOT)/sw/cmn/util --src-rdir=$(ROOT)/sw/cmn --lib-dir=$(LIB_DIR) --lib-name=$(PLATFORM_NAME) 72 | 73 | .phony : generate_app 74 | generate_app: ##Generate a new app. Default APP_NAME=new_app. Overwrite it with make generate_app APP_NAME=. 75 | mkdir $(APP_NAME) 76 | mkdir $(APP_NAME)/src 77 | cp $(ROOT)/sw/cmn/util/main_template $(APP_NAME)/src/main.cpp 78 | cp $(ROOT)/sw/cmn/util/app_template $(APP_NAME)/src/app.cpp 79 | $(CREATE_APP) --bsp-dir=$(BSP_DIR) --inc-rdir=$(ROOT)/sw/cmn --app-dir=./$(APP_NAME) --elf-name=$(APP_NAME).elf --src-dir=$(APP_NAME)/src --use-lib-dir=lib_$(PLATFORM_NAME) 80 | 81 | .phony : app compile_app 82 | compile_app : app 83 | app : ##Build and generate memory initialization file for $(APP_NAME) 84 | make -C $(APP_NAME) mem_init_generate 85 | 86 | .phony : generate_example 87 | generate_example : ##Create an example to run with current platform from the example collection, example $(EX_NAME) is created 88 | #Copy the example to the local directory 89 | #cp -r ../examples/$(EX_NAME) ./ 90 | mkdir $(EX_NAME) 91 | $(CREATE_APP) --bsp-dir=$(BSP_DIR) --inc-rdir=$(ROOT)/sw/cmn --app-dir=./$(EX_NAME) --elf-name=$(EX_NAME).elf --src-dir=$(ROOT)/sw/examples/$(EX_NAME)/src --use-lib-dir=lib_$(PLATFORM_NAME) 92 | 93 | 94 | .phony : pof generate_pof 95 | pof : generate_pof 96 | generate_pof: ##Generate POF file from SOF file and memory initialization file 97 | @echo "Selected SOF : $(SOF_FILE)" 98 | quartus_cpf -c -o compression=on -o ufm_source_file=$(APP_NAME)/mem_init/onchip_flash.hex $(SOF_FILE) ./$(PLATFORM_NAME)_$(BOARD_NAME).pof 99 | 100 | 101 | .phony : clean 102 | clean : ##Clean BSP, LIB and APP folder 103 | make clean -C $(BSP_DIR) 104 | make clean -C $(APP_NAME) 105 | make clean -C $(LIB_DIR) 106 | 107 | .phony: reset 108 | reset : ##Remove BSP and LIB folder 109 | -find $(BSP_DIR) ! -name settings.bsp -delete 110 | rm -rf $(LIB_DIR) 111 | 112 | #You can use this phony target to test your modified Makefile 113 | #I find the way Makefile parses the Makefile is rather confusing and unlike other programmes 114 | #So a test target is quite helpful to do experiment and debug 115 | .phony : test 116 | 117 | test : ##Test target 118 | @echo Current platform is $(PLATFORM_NAME) 119 | -------------------------------------------------------------------------------- /sw/recon_0a/Makefile: -------------------------------------------------------------------------------- 1 | # Project : RECON 2017 2 | # Author : Jeff Lieu 3 | # Note that you need to be in NIOS2 Command Line Shell to run this Makefile 4 | # This Makefile simplies the process of developing software for FPGA based embedded system 5 | # Type make help for more information 6 | 7 | #Directory hierarchy: 8 | #recon --> hw --> cmn 9 | # ---> io 10 | # ---> timer 11 | # ---> util 12 | # --> recon_0 : 13 | # ---> bemicro_max10 : board specific settings 14 | # An equivalent hierarchy in software branch 15 | #recon --> sw --> cmn 16 | # --> recon_0 17 | # ---> bsp 18 | # ---> lib_recon_0 19 | # ---> , your app can run on the same platform with any board, because the NIOS system is the same 20 | SHELL :=/bin/bash 21 | ROOT = ../.. 22 | SOFTWARE_PATH = $(shell pwd) 23 | PLATFORM_NAME = $(lastword $(subst /, ,$(SOFTWARE_PATH))) 24 | HARDWARE_PATH = $(ROOT)/hw/$(PLATFORM_NAME) 25 | BOARD_NAME = bemicro_max10 26 | 27 | #You need "find" command in your search path. Windows system may have some difficulty. 28 | #Here we search in hardware directories for the SOF files and with the correct BOARD_NAME 29 | #Then select between released sof file and development sof file 30 | REL_SOF_FILE = $(shell find $(HARDWARE_PATH) | grep $(BOARD_NAME)/release/$(PLATFORM_NAME).sof) 31 | DEV_SOF_FILE = $(shell find $(HARDWARE_PATH) | grep $(BOARD_NAME)/output_files/$(PLATFORM_NAME).sof) 32 | SOF_FILE = $(if $(DEV_SOF_FILE),$(DEV_SOF_FILE),${REL_SOF_FILE}) 33 | 34 | #These commands are available in NIOS2-Command-Shell 35 | CREATE_BSP = nios2-bsp 36 | EDIT_BSP = nios2-bsp-editor 37 | CREATE_LIB = nios2-lib-generate-makefile 38 | CREATE_APP = nios2-app-generate-makefile 39 | 40 | BSP_DIR = ./bsp 41 | LIB_DIR = lib_$(PLATFORM_NAME) 42 | APP_NAME = new_app 43 | EX_NAME = frequency_counter 44 | 45 | .phony : help 46 | help : ##Fancy auto help 47 | @IFS=$$'\n' ; \ 48 | help_lines=(`fgrep -h "##" $(MAKEFILE_LIST) | fgrep -v fgrep | sed -e 's/\\$$//'`); \ 49 | for help_line in $${help_lines[@]}; do \ 50 | IFS=$$'#' ; \ 51 | help_split=($$help_line) ; \ 52 | help_command=`echo $${help_split[0]} | sed -e 's/^ *//' -e 's/ *$$//'` ; \ 53 | help_info=`echo $${help_split[2]} | sed -e 's/^ *//' -e 's/ *$$//'` ; \ 54 | printf "%-30s %s\n" $$help_command $$help_info ; \ 55 | done 56 | 57 | .phony : new_bsp edit_bsp update_bsp 58 | new_bsp : ##Generate or Reset BSP settings to defaults. Always use HAL. Ouput to "bsp" directory. SOPC file is fetched from the hardware 59 | $(CREATE_BSP) hal $(BSP_DIR) $(HARDWARE_PATH)/$(PLATFORM_NAME).sopcinfo 60 | 61 | edit_bsp: ##Open the GUI that we can edit the BSP settings. Remember to Save and then Generate it. 62 | -mkdir $(BSP_DIR)/edit_dir 63 | cd $(BSP_DIR) && $(EDIT_BSP) --settings settings.bsp 64 | 65 | update_bsp : ##Update BSP with latest SOPCINFO but keep changes you've made to BSP 66 | $(CREATE_BSP) hal $(BSP_DIR) $(HARDWARE_PATH)/$(PLATFORM_NAME).sopcinfo --default_stdio DONT_CHANGE --default_memory_regions DONT_CHANGE --default_section_regions DONT_CHANGE --default_sys_timer DONT_CHANGE --default_sections_mapping DONT_CHANGE --use_bootloader DONT_CHANGE 67 | 68 | .phony : lib generate_lib 69 | lib : generate_lib 70 | generate_lib: ##Generate library that contains drivers of our custom hardware (not from Altera). 71 | $(CREATE_LIB) --bsp-dir=$(BSP_DIR) --inc-dir=$(ROOT)/sw/cmn/util --src-rdir=$(ROOT)/sw/cmn --lib-dir=$(LIB_DIR) --lib-name=$(PLATFORM_NAME) 72 | 73 | .phony : generate_app 74 | generate_app: ##Generate a new app. Default APP_NAME=new_app. Overwrite it with make generate_app APP_NAME=. Set BOARD_NAME to turn on board specific definitions. 75 | mkdir $(APP_NAME) 76 | mkdir $(APP_NAME)/src 77 | cp $(ROOT)/sw/cmn/util/main_template $(APP_NAME)/src/main.cpp 78 | cp $(ROOT)/sw/cmn/util/app_template $(APP_NAME)/src/app.cpp 79 | $(CREATE_APP) --bsp-dir=$(BSP_DIR) --inc-rdir=$(ROOT)/sw/cmn --app-dir=./$(APP_NAME) --elf-name=$(APP_NAME).elf --src-dir=$(APP_NAME)/src --use-lib-dir=lib_$(PLATFORM_NAME) \ 80 | --set APP_CFLAGS_DEFINED_SYMBOLS -D__KIT_$(BOARD_NAME) 81 | 82 | .phony : app compile_app 83 | compile_app : app 84 | app : ##Build and generate memory initialization file for $(APP_NAME) 85 | make -C $(APP_NAME) mem_init_generate 86 | 87 | .phony : generate_example 88 | generate_example : ##Create an example to run with current platform from the example collection, example $(EX_NAME) is created 89 | #Copy the example to the local directory 90 | #cp -r ../examples/$(EX_NAME) ./ 91 | mkdir $(EX_NAME) 92 | $(CREATE_APP) --bsp-dir=$(BSP_DIR) --inc-rdir=$(ROOT)/sw/cmn --app-dir=./$(EX_NAME) --elf-name=$(EX_NAME).elf --src-dir=$(ROOT)/sw/examples/$(EX_NAME)/src --use-lib-dir=lib_$(PLATFORM_NAME) \ 93 | --set APP_CFLAGS_DEFINED_SYMBOLS -D__KIT_$(BOARD_NAME) 94 | 95 | .phony : pof generate_pof 96 | pof : generate_pof 97 | generate_pof: ##Generate POF file from SOF file and memory initialization file 98 | @echo "Selected SOF : $(SOF_FILE)" 99 | quartus_cpf -c -o compression=on -o ufm_source_file=$(APP_NAME)/mem_init/onchip_flash.hex $(SOF_FILE) ./$(PLATFORM_NAME)_$(BOARD_NAME).pof 100 | 101 | 102 | .phony : clean 103 | clean : ##Clean BSP, LIB and APP folder 104 | make clean -C $(BSP_DIR) 105 | make clean -C $(APP_NAME) 106 | make clean -C $(LIB_DIR) 107 | 108 | .phony: reset 109 | reset : ##Remove BSP and LIB folder 110 | -find $(BSP_DIR) ! -name settings.bsp -delete 111 | rm -rf $(LIB_DIR) 112 | 113 | #You can use this phony target to test your modified Makefile 114 | #I find the way Makefile parses the Makefile is rather confusing and unlike other programmes 115 | #So a test target is quite helpful to do experiment and debug 116 | .phony : test 117 | 118 | test : ##Test target 119 | @echo Current platform is $(PLATFORM_NAME) 120 | -------------------------------------------------------------------------------- /sw/recon_1/Makefile: -------------------------------------------------------------------------------- 1 | # Project : RECON 2017 2 | # Author : Jeff Lieu 3 | # Note that you need to be in NIOS2 Command Line Shell to run this Makefile 4 | # This Makefile simplies the process of developing software for FPGA based embedded system 5 | # Type make help for more information 6 | 7 | #Directory hierarchy: 8 | #recon --> hw --> cmn 9 | # ---> io 10 | # ---> timer 11 | # ---> util 12 | # --> recon_0 : 13 | # ---> bemicro_max10 : board specific settings 14 | # An equivalent hierarchy in software branch 15 | #recon --> sw --> cmn 16 | # --> recon_0 17 | # ---> bsp 18 | # ---> lib_recon_0 19 | # ---> , your app can run on the same platform with any board, because the NIOS system is the same 20 | SHELL :=/bin/bash 21 | ROOT = ../.. 22 | SOFTWARE_PATH = $(shell pwd) 23 | PLATFORM_NAME = $(lastword $(subst /, ,$(SOFTWARE_PATH))) 24 | HARDWARE_PATH = $(ROOT)/hw/$(PLATFORM_NAME) 25 | BOARD_NAME = civ10 26 | 27 | #You need "find" command in your search path. Windows system may have some difficulty. 28 | #Here we search in hardware directories for the SOF files and with the correct BOARD_NAME 29 | #Then select between released sof file and development sof file 30 | REL_SOF_FILE = $(shell find $(HARDWARE_PATH) | grep $(BOARD_NAME)/release/$(PLATFORM_NAME).sof) 31 | DEV_SOF_FILE = $(shell find $(HARDWARE_PATH) | grep $(BOARD_NAME)/output_files/$(PLATFORM_NAME).sof) 32 | SOF_FILE = $(if $(DEV_SOF_FILE),$(DEV_SOF_FILE),${REL_SOF_FILE}) 33 | 34 | #These commands are available in NIOS2-Command-Shell 35 | CREATE_BSP = nios2-bsp 36 | EDIT_BSP = nios2-bsp-editor 37 | CREATE_LIB = nios2-lib-generate-makefile 38 | CREATE_APP = nios2-app-generate-makefile 39 | 40 | BSP_DIR = ./bsp 41 | LIB_DIR = lib_$(PLATFORM_NAME) 42 | APP_NAME = new_app 43 | EX_NAME = frequency_counter 44 | 45 | .phony : help 46 | help : ##Fancy auto help 47 | @IFS=$$'\n' ; \ 48 | help_lines=(`fgrep -h "##" $(MAKEFILE_LIST) | fgrep -v fgrep | sed -e 's/\\$$//'`); \ 49 | for help_line in $${help_lines[@]}; do \ 50 | IFS=$$'#' ; \ 51 | help_split=($$help_line) ; \ 52 | help_command=`echo $${help_split[0]} | sed -e 's/^ *//' -e 's/ *$$//'` ; \ 53 | help_info=`echo $${help_split[2]} | sed -e 's/^ *//' -e 's/ *$$//'` ; \ 54 | printf "%-30s %s\n" $$help_command $$help_info ; \ 55 | done 56 | 57 | .phony : new_bsp edit_bsp update_bsp 58 | new_bsp : ##Generate or Reset BSP settings to defaults. Always use HAL. Ouput to "bsp" directory. SOPC file is fetched from the hardware 59 | $(CREATE_BSP) hal $(BSP_DIR) $(HARDWARE_PATH)/$(PLATFORM_NAME).sopcinfo 60 | 61 | edit_bsp: ##Open the GUI that we can edit the BSP settings. Remember to Save and then Generate it. 62 | -mkdir $(BSP_DIR)/edit_dir 63 | cd $(BSP_DIR) && $(EDIT_BSP) --settings settings.bsp 64 | 65 | update_bsp : ##Update BSP with latest SOPCINFO but keep changes you've made to BSP 66 | $(CREATE_BSP) hal $(BSP_DIR) $(HARDWARE_PATH)/$(PLATFORM_NAME).sopcinfo --default_stdio DONT_CHANGE --default_memory_regions DONT_CHANGE --default_section_regions DONT_CHANGE --default_sys_timer DONT_CHANGE --default_sections_mapping DONT_CHANGE --use_bootloader DONT_CHANGE 67 | 68 | .phony : lib generate_lib 69 | lib : generate_lib 70 | generate_lib: ##Generate library that contains drivers of our custom hardware (not from Altera). 71 | $(CREATE_LIB) --bsp-dir=$(BSP_DIR) --inc-dir=$(ROOT)/sw/cmn/util --src-rdir=$(ROOT)/sw/cmn --lib-dir=$(LIB_DIR) --lib-name=$(PLATFORM_NAME) 72 | 73 | .phony : generate_app 74 | generate_app: ##Generate a new app. Default APP_NAME=new_app. Overwrite it with make generate_app APP_NAME=. 75 | mkdir $(APP_NAME) 76 | mkdir $(APP_NAME)/src 77 | cp $(ROOT)/sw/cmn/util/main_template $(APP_NAME)/src/main.cpp 78 | cp $(ROOT)/sw/cmn/util/app_template $(APP_NAME)/src/app.cpp 79 | $(CREATE_APP) --bsp-dir=$(BSP_DIR) --inc-rdir=$(ROOT)/sw/cmn --app-dir=./$(APP_NAME) --elf-name=$(APP_NAME).elf --src-dir=$(APP_NAME)/src --use-lib-dir=lib_$(PLATFORM_NAME) 80 | 81 | .phony : fpga_flash 82 | fpga.flash : $(SOF_FILE) 83 | fpga_flash: fpga.flash 84 | sof2flash --input=$(SOF_FILE) --output=./fpga.flash --epcs --programmingmode=as 85 | 86 | .phony : program-flash 87 | program-flash : 88 | make -C $(APP_NAME) program-flash flash_mem_epcs_flag="--epcs --after=../fpga.flash" 89 | 90 | .phony : app compile_app 91 | compile_app : app 92 | app : fpga.flash ##Build and generate memory initialization file for $(APP_NAME). Note that we need to overwrite the default option with --after. Because 0x0 is fpga image, we need to put the software after that. 93 | make -C $(APP_NAME) mem_init_generate flash_mem_epcs_flag="--epcs --after=../fpga.flash" 94 | 95 | .phony : generate_example 96 | generate_example : ##Create an example to run with current platform from the example collection, example $(EX_NAME) is created 97 | #Copy the example to the local directory 98 | #cp -r ../examples/$(EX_NAME) ./ 99 | mkdir $(EX_NAME) 100 | $(CREATE_APP) --bsp-dir=$(BSP_DIR) --inc-rdir=$(ROOT)/sw/cmn --app-dir=./$(EX_NAME) --elf-name=$(EX_NAME).elf --src-dir=$(ROOT)/sw/examples/$(EX_NAME)/src --use-lib-dir=lib_$(PLATFORM_NAME) 101 | 102 | 103 | .phony : pof generate_pof 104 | pof : generate_pof 105 | generate_pof: ##Generate POF file from SOF file and memory initialization file 106 | @echo "Selected SOF : $(SOF_FILE)" 107 | quartus_cpf -c -o compression=on -o ufm_source_file=$(APP_NAME)/mem_init/onchip_flash.hex $(SOF_FILE) ./$(PLATFORM_NAME)_$(BOARD_NAME).pof 108 | 109 | 110 | .phony : clean 111 | clean : ##Clean BSP, LIB and APP folder 112 | make clean -C $(BSP_DIR) 113 | make clean -C $(APP_NAME) 114 | make clean -C $(LIB_DIR) 115 | 116 | .phony: reset 117 | reset : ##Remove BSP and LIB folder 118 | -find $(BSP_DIR) ! -name settings.bsp -delete 119 | rm -rf $(LIB_DIR) 120 | 121 | #You can use this phony target to test your modified Makefile 122 | #I find the way Makefile parses the Makefile is rather confusing and unlike other programmes 123 | #So a test target is quite helpful to do experiment and debug 124 | .phony : test 125 | 126 | test : ##Test target 127 | @echo Current platform is $(PLATFORM_NAME) 128 | -------------------------------------------------------------------------------- /sw/recon_1/readme.txt: -------------------------------------------------------------------------------- 1 | To download program to flash memory: 2 | - use nios2-flash-program software and the fpga has to be alive with a NIOS+Flash memory controller. What the nios2-flash-program does is that it overtakes the NIOS 3 | and access the flash itself. 4 | - The default Makefile generated by Altera in the folder always puts the .elf image at address 0x0 which is wrong, because the fpga image is there. 5 | Therefore, if you run make program-flash from the folder you have to add 6 | -------------------------------------------------------------------------------- /sw/recon_2/Makefile: -------------------------------------------------------------------------------- 1 | # Project : RECON 2017 2 | # Author : Jeff Lieu 3 | # Note that you need to be in NIOS2 Command Line Shell to run this Makefile 4 | # This Makefile simplies the process of developing software for FPGA based embedded system 5 | # Type make help for more information 6 | 7 | #Directory hierarchy: 8 | #recon --> hw --> cmn 9 | # ---> io 10 | # ---> timer 11 | # ---> util 12 | # --> recon_0 : 13 | # ---> bemicro_max10 : board specific settings 14 | # An equivalent hierarchy in software branch 15 | #recon --> sw --> cmn 16 | # --> recon_0 17 | # ---> bsp 18 | # ---> lib_recon_0 19 | # ---> , your app can run on the same platform with any board, because the NIOS system is the same 20 | 21 | ROOT = ../.. 22 | SOFTWARE_PATH = $(shell pwd) 23 | PLATFORM_NAME = $(lastword $(subst /, ,$(SOFTWARE_PATH))) 24 | HARDWARE_PATH = $(ROOT)/hw/$(PLATFORM_NAME) 25 | BOARD_NAME = civ10 26 | 27 | #You need "find" command in your search path. Windows system may have some difficulty. 28 | #Here we search in hardware directories for the SOF files and with the correct BOARD_NAME 29 | #Then select between released sof file and development sof file 30 | REL_SOF_FILE = $(shell find $(HARDWARE_PATH) | grep $(BOARD_NAME)/release/$(PLATFORM_NAME).sof) 31 | DEV_SOF_FILE = $(shell find $(HARDWARE_PATH) | grep $(BOARD_NAME)/output_files/$(PLATFORM_NAME).sof) 32 | SOF_FILE = $(if $(DEV_SOF_FILE),$(DEV_SOF_FILE),${REL_SOF_FILE}) 33 | 34 | #These commands are available in NIOS2-Command-Shell 35 | CREATE_BSP = nios2-bsp 36 | EDIT_BSP = nios2-bsp-editor 37 | CREATE_LIB = nios2-lib-generate-makefile 38 | CREATE_APP = nios2-app-generate-makefile 39 | 40 | BSP_DIR = ./bsp 41 | LIB_DIR = lib_$(PLATFORM_NAME) 42 | APP_NAME = new_app 43 | EX_NAME = frequency_counter 44 | 45 | .phony : help 46 | help : ##Fancy auto help 47 | @IFS=$$'\n' ; \ 48 | help_lines=(`fgrep -h "##" $(MAKEFILE_LIST) | fgrep -v fgrep | sed -e 's/\\$$//'`); \ 49 | for help_line in $${help_lines[@]}; do \ 50 | IFS=$$'#' ; \ 51 | help_split=($$help_line) ; \ 52 | help_command=`echo $${help_split[0]} | sed -e 's/^ *//' -e 's/ *$$//'` ; \ 53 | help_info=`echo $${help_split[2]} | sed -e 's/^ *//' -e 's/ *$$//'` ; \ 54 | printf "%-30s %s\n" $$help_command $$help_info ; \ 55 | done 56 | 57 | .phony : new_bsp edit_bsp update_bsp 58 | new_bsp : ##Generate or Reset BSP settings to defaults. Always use HAL. Ouput to "bsp" directory. SOPC file is fetched from the hardware 59 | $(CREATE_BSP) hal $(BSP_DIR) $(HARDWARE_PATH)/$(PLATFORM_NAME).sopcinfo 60 | 61 | edit_bsp: ##Open the GUI that we can edit the BSP settings. Remember to Save and then Generate it. 62 | -mkdir $(BSP_DIR)/edit_dir 63 | cd $(BSP_DIR) && $(EDIT_BSP) --settings settings.bsp 64 | 65 | update_bsp : ##Update BSP with latest SOPCINFO but keep changes you've made to BSP 66 | $(CREATE_BSP) hal $(BSP_DIR) $(HARDWARE_PATH)/$(PLATFORM_NAME).sopcinfo --default_stdio DONT_CHANGE --default_memory_regions DONT_CHANGE --default_section_regions DONT_CHANGE --default_sys_timer DONT_CHANGE --default_sections_mapping DONT_CHANGE --use_bootloader DONT_CHANGE 67 | 68 | .phony : lib generate_lib 69 | lib : generate_lib 70 | generate_lib: ##Generate library that contains drivers of our custom hardware (not from Altera). 71 | $(CREATE_LIB) --bsp-dir=$(BSP_DIR) --inc-dir=$(ROOT)/sw/cmn/util --src-rdir=$(ROOT)/sw/cmn --lib-dir=$(LIB_DIR) --lib-name=$(PLATFORM_NAME) 72 | 73 | .phony : generate_app 74 | generate_app: ##Generate a new app. Default APP_NAME=new_app. Overwrite it with make generate_app APP_NAME=. 75 | mkdir $(APP_NAME) 76 | mkdir $(APP_NAME)/src 77 | cp $(ROOT)/sw/cmn/util/main_template $(APP_NAME)/src/main.cpp 78 | cp $(ROOT)/sw/cmn/util/app_template $(APP_NAME)/src/app.cpp 79 | $(CREATE_APP) --bsp-dir=$(BSP_DIR) --inc-rdir=$(ROOT)/sw/cmn --app-dir=./$(APP_NAME) --elf-name=$(APP_NAME).elf --src-dir=$(APP_NAME)/src --use-lib-dir=lib_$(PLATFORM_NAME) 80 | 81 | .phony : fpga_flash 82 | fpga.flash : $(SOF_FILE) 83 | fpga_flash: fpga.flash 84 | sof2flash --input=$(SOF_FILE) --output=./fpga.flash --epcs --programmingmode=as 85 | 86 | .phony : program-flash 87 | program-flash : 88 | make -C $(APP_NAME) program-flash 89 | 90 | .phony : app compile_app 91 | compile_app : app 92 | app : fpga.flash ##Build and generate memory initialization file for $(APP_NAME). Note that we need to overwrite the default option with --after. Because 0x0 is fpga image, we need to put the software after that. 93 | make -C $(APP_NAME) mem_init_generate 94 | 95 | .phony : generate_example 96 | generate_example : ##Create an example to run with current platform from the example collection, example $(EX_NAME) is created 97 | #Copy the example to the local directory 98 | #cp -r ../examples/$(EX_NAME) ./ 99 | mkdir $(EX_NAME) 100 | $(CREATE_APP) --bsp-dir=$(BSP_DIR) --inc-rdir=$(ROOT)/sw/cmn --app-dir=./$(EX_NAME) --elf-name=$(EX_NAME).elf --src-dir=$(ROOT)/sw/examples/$(EX_NAME)/src --use-lib-dir=lib_$(PLATFORM_NAME) 101 | 102 | 103 | .phony : pof generate_pof 104 | pof : generate_pof 105 | generate_pof: ##Generate POF file from SOF file and memory initialization file 106 | @echo "Selected SOF : $(SOF_FILE)" 107 | quartus_cpf -c -o compression=on -o ufm_source_file=$(APP_NAME)/mem_init/onchip_flash.hex $(SOF_FILE) ./$(PLATFORM_NAME)_$(BOARD_NAME).pof 108 | 109 | 110 | .phony : clean 111 | clean : ##Clean BSP, LIB and APP folder 112 | make clean -C $(BSP_DIR) 113 | make clean -C $(APP_NAME) 114 | make clean -C $(LIB_DIR) 115 | 116 | .phony: reset 117 | reset : ##Remove BSP and LIB folder 118 | -find $(BSP_DIR) ! -name settings.bsp -delete 119 | rm -rf $(LIB_DIR) 120 | 121 | #You can use this phony target to test your modified Makefile 122 | #I find the way Makefile parses the Makefile is rather confusing and unlike other programmes 123 | #So a test target is quite helpful to do experiment and debug 124 | .phony : test 125 | 126 | test : ##Test target 127 | @echo Current platform is $(PLATFORM_NAME) 128 | -------------------------------------------------------------------------------- /sw/recon_2/readme.txt: -------------------------------------------------------------------------------- 1 | To download program to flash memory: 2 | - use nios2-flash-program software and the fpga has to be alive with a NIOS+Flash memory controller. What the nios2-flash-program does is that it overtakes the NIOS 3 | and access the flash itself. 4 | - The default Makefile generated by Altera in the folder always puts the .elf image at address 0x0 which is wrong, because the fpga image is there. 5 | Therefore, if you run make program-flash from the folder you have to add 6 | --------------------------------------------------------------------------------