├── .gitignore ├── BIOS.S ├── Calibrat.c ├── Draw.c ├── FWLib └── inc │ ├── Command Prompt.lnk │ ├── cortexm3_macro.h │ ├── stm32f10x_dac.h │ ├── stm32f10x_dma.h │ ├── stm32f10x_flash.h │ ├── stm32f10x_fsmc.h │ ├── stm32f10x_gpio.h │ ├── stm32f10x_lib.h │ ├── stm32f10x_map.h │ ├── stm32f10x_nvic.h │ ├── stm32f10x_rcc.h │ ├── stm32f10x_sdio.h │ ├── stm32f10x_spi.h │ ├── stm32f10x_type.h │ └── stm32f10x_usart.h ├── Files.c ├── Function.c ├── Interrupt.c ├── Main.c ├── Makefile ├── Menu.c ├── Process.c ├── README.TXT ├── README.md ├── User Guide V5.6-6.5.pdf ├── W1.1 FPGA ├── 281_FPGA.BIN ├── AddrCtrl.v ├── DP_RAM.v ├── FPGA_281.ADR ├── FPGA_V25.v ├── IO_Ctrl.v ├── Pins.pcf ├── README.TXT ├── Signal.v └── Time.sdc ├── app1.lds ├── app2.lds ├── app3.lds ├── app4.lds ├── cortexm3_macro.S ├── inc ├── BIOS.h ├── Calibrat.h ├── Draw.h ├── File.h ├── Function.h ├── Interrupt.h ├── Menu.h ├── Process.h └── stm32f10x_conf.h ├── main.lds ├── startup.c └── stm32f10x_nvic.c /.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.d 3 | *.map 4 | *.hex -------------------------------------------------------------------------------- /BIOS.S: -------------------------------------------------------------------------------- 1 | .syntax unified 2 | .thumb 3 | .thumb_func 4 | .code 16 5 | //.text 6 | 7 | //********************* (C) COPYRIGHT 2009 e-Design Co.,Ltd. ********************* 8 | // File Name : ASM.c 9 | // Version : DS203_APP Ver 2.5x Author : bure 10 | //******************************************************************************// 11 | 12 | BIOS: 13 | //=============================================================================== 14 | // System function entrance 15 | //=============================================================================== 16 | // void CTR_HP(void) USB_HP_Interrupt 17 | //------------------------------------------------------------------------------- 18 | .globl __CTR_HP 19 | .thumb_func 20 | . = BIOS + 0x01 21 | __CTR_HP: 22 | //=============================================================================== 23 | // void USB_Istr(void) USB_LP_Interrupt 24 | //------------------------------------------------------------------------------- 25 | .globl __USB_Istr 26 | .thumb_func 27 | . = BIOS + 0x05 28 | __USB_Istr: 29 | //=============================================================================== 30 | // void __LCD_Initial(void) 31 | //------------------------------------------------------------------------------- 32 | .globl __LCD_Initial 33 | .thumb_func 34 | . = BIOS + 0x09 35 | __LCD_Initial : 36 | //=============================================================================== 37 | // void __Point_SCR(u16 x0, u16 y0) 38 | //------------------------------------------------------------------------------- 39 | .globl __Point_SCR 40 | .thumb_func 41 | . = BIOS + 0x0D 42 | __Point_SCR : 43 | //=============================================================================== 44 | // void __LCD_SetPixl(u16 Color) 45 | //------------------------------------------------------------------------------- 46 | .globl __LCD_SetPixl 47 | .thumb_func 48 | . = BIOS + 0x11 49 | __LCD_SetPixl : 50 | //=============================================================================== 51 | // void __Clear_Screen(u16 Color) 52 | //------------------------------------------------------------------------------- 53 | .globl __Clear_Screen 54 | .thumb_func 55 | . = BIOS + 0x15 56 | __Clear_Screen : 57 | //=============================================================================== 58 | // u16 __Get_TAB_8x14(u8 Code, u16 Row) 59 | //------------------------------------------------------------------------------- 60 | .globl __Get_TAB_8x14 61 | .thumb_func 62 | . = BIOS + 0x19 63 | __Get_TAB_8x14 : 64 | //=============================================================================== 65 | // void __LCD_Set_Block(u16 x1, u16 x2, u16 y1, u16 y2) 66 | //------------------------------------------------------------------------------- 67 | .globl __LCD_Set_Block 68 | .thumb_func 69 | . = BIOS + 0x1D 70 | __LCD_Set_Block : 71 | //=============================================================================== 72 | // void __LCD_DMA_Ready(void) Wait LCD data DMA ready 73 | //------------------------------------------------------------------------------- 74 | .globl __LCD_DMA_Ready 75 | .thumb_func 76 | . = BIOS + 0x21 77 | __LCD_DMA_Ready : 78 | //=============================================================================== 79 | // void __LCD_Copy(uc16 *pBuffer, u16 NumPixel) Send a row data to LCD 80 | //------------------------------------------------------------------------------- 81 | .globl __LCD_Copy 82 | .thumb_func 83 | . = BIOS + 0x25 84 | __LCD_Copy: 85 | //=============================================================================== 86 | // void __LCD_Fill(u16 *pBuffer, u16 NumPixel) Fill number of pixel by DMA 87 | //------------------------------------------------------------------------------- 88 | .globl __LCD_Fill 89 | .thumb_func 90 | . = BIOS + 0x29 91 | __LCD_Fill: 92 | //=============================================================================== 93 | // void __Row_DMA_Ready(void) Wait row base data DMA ready 94 | //------------------------------------------------------------------------------- 95 | .globl __Row_DMA_Ready 96 | .thumb_func 97 | . = BIOS + 0x2D 98 | __Row_DMA_Ready : 99 | //=============================================================================== 100 | // void __Row_Copy(uc16 *S_Buffer,u16 *T_Buffer) Copy one row base data to buffer 101 | //------------------------------------------------------------------------------- 102 | .globl __Row_Copy 103 | .thumb_func 104 | . = BIOS + 0x31 105 | __Row_Copy: 106 | //=============================================================================== 107 | // u32 __Read_FIFO(void) 108 | //------------------------------------------------------------------------------- 109 | .globl __Read_FIFO 110 | .thumb_func 111 | . = BIOS + 0x35 112 | __Read_FIFO: 113 | //=============================================================================== 114 | // u32 __Input_Lic(u16 x0, u8 y0, u16 Color)// Return: 32Bits Licence 115 | //------------------------------------------------------------------------------- 116 | .globl __Input_Lic 117 | .thumb_func 118 | . = BIOS + 0x39 119 | __Input_Lic: 120 | //=============================================================================== 121 | // u32 GetDev_SN(void)// Get 32bits Device Serial Number 122 | //------------------------------------------------------------------------------- 123 | .globl __GetDev_SN 124 | .thumb_func 125 | . = BIOS + 0x3D 126 | __GetDev_SN: 127 | //=============================================================================== 128 | // u8 __Chk_SYS(u32 Licence) Check SYS licence RET: 1 = licence ok 129 | //------------------------------------------------------------------------------- 130 | .globl __Chk_SYS 131 | .thumb_func 132 | . = BIOS + 0x41 133 | __Chk_SYS: 134 | //=============================================================================== 135 | // u8 __Ident(u32 Dev_ID, u32 Proj_ID, u32 Lic_No) RET: 1 = licence ok 136 | //------------------------------------------------------------------------------- 137 | .globl __Ident 138 | .thumb_func 139 | . = BIOS + 0x45 140 | __Ident: 141 | //=============================================================================== 142 | // void __Display_Str(u16 x0, u16 y0, u16 Color, u8 Mode, u8 *s) 143 | //------------------------------------------------------------------------------- 144 | .globl __Display_Str 145 | .thumb_func 146 | . = BIOS + 0x49 147 | __Display_Str: 148 | //=============================================================================== 149 | // void __Set(u8 Device, u32 Value) Hardware control device Settings 150 | //------------------------------------------------------------------------------- 151 | .globl __Set 152 | .thumb_func 153 | . = BIOS + 0x4D 154 | __Set: 155 | //=============================================================================== 156 | // void Set_Param(u8 RegAddr, u8 Parameter) Trigger control parameter set 157 | //------------------------------------------------------------------------------- 158 | .globl __Set_Param 159 | .thumb_func 160 | . = BIOS + 0x51 161 | __Set_Param: 162 | //=============================================================================== 163 | // u32 __Get(u8 Kind) Get hardware attribute & status 164 | //------------------------------------------------------------------------------- 165 | .globl __Get 166 | .thumb_func 167 | . = BIOS + 0x55 168 | __Get: 169 | //=============================================================================== 170 | // void __ExtFlash_PageWR(u8* pBuffer, u32 WriteAddr)// 171 | //------------------------------------------------------------------------------- 172 | .globl __ExtFlash_PageWR 173 | .thumb_func 174 | . = BIOS + 0x59 175 | __ExtFlash_PageWR: 176 | //=============================================================================== 177 | // void __Disk_Buff_RD(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead)// 178 | //------------------------------------------------------------------------------- 179 | .globl __ExtFlash_PageRD 180 | .thumb_func 181 | . = BIOS + 0x5D 182 | __ExtFlash_PageRD: 183 | //=============================================================================== 184 | // u8 ReadDiskData(u8* pBuffer, u32 ReadAddr, u16 Lenght) 185 | //------------------------------------------------------------------------------- 186 | .globl __ReadDiskData 187 | .thumb_func 188 | . = BIOS + 0x61 189 | __ReadDiskData: 190 | //=============================================================================== 191 | // u8 ProgDiskPage(u8* pBuffer, u32 ProgAddr) 192 | //------------------------------------------------------------------------------- 193 | .globl __ProgDiskPage 194 | .thumb_func 195 | . = BIOS + 0x65 196 | __ProgDiskPage: 197 | //=============================================================================== 198 | // u16 __LCD_GetPixl(void) 199 | //------------------------------------------------------------------------------- 200 | .globl __LCD_GetPixl 201 | .thumb_func 202 | . = BIOS + 0x69 203 | __LCD_GetPixl : 204 | //=============================================================================== 205 | // void __USB_Init(void) 206 | //------------------------------------------------------------------------------- 207 | .globl __USB_Init 208 | .thumb_func 209 | . = BIOS + 0x6D 210 | __USB_Init: 211 | //=============================================================================== 212 | // u8 __FLASH_Erase(u32 Address) RET: 1 = ok 213 | //------------------------------------------------------------------------------- 214 | .globl __FLASH_Erase 215 | .thumb_func 216 | . = BIOS + 0x71 217 | __FLASH_Erase: 218 | //=============================================================================== 219 | // u8 __FLASH_Prog(u32 Address, u16 Data) RET: 1 = ok 220 | //------------------------------------------------------------------------------- 221 | .globl __FLASH_Prog 222 | .thumb_func 223 | . = BIOS + 0x75 224 | __FLASH_Prog: 225 | //=============================================================================== 226 | // void __FLASH_Unlock(void) 227 | //------------------------------------------------------------------------------- 228 | .globl __FLASH_Unlock 229 | .thumb_func 230 | . = BIOS + 0x79 231 | __FLASH_Unlock: 232 | //=============================================================================== 233 | // void __FLASH_Lock(void) 234 | //------------------------------------------------------------------------------- 235 | .globl __FLASH_Lock 236 | .thumb_func 237 | . = BIOS + 0x7D 238 | __FLASH_Lock: 239 | //=============================================================================== 240 | // u8* __Chk_DFU(void) 241 | //------------------------------------------------------------------------------- 242 | .globl __Chk_DFU 243 | .thumb_func 244 | . = BIOS + 0x81 245 | __Chk_DFU: 246 | //=============================================================================== 247 | // u8* __Chk_HDW(void) 248 | //------------------------------------------------------------------------------- 249 | .globl __Chk_HDW 250 | .thumb_func 251 | . = BIOS + 0x85 252 | __Chk_HDW: 253 | //=============================================================================== 254 | // u8 __OpenFileWr(u8* Buffer, u8* FileName, u16* Cluster, u32* pDirAddr)// 255 | //------------------------------------------------------------------------------- 256 | .globl __OpenFileWr 257 | .thumb_func 258 | . = BIOS + 0x89 259 | __OpenFileWr: 260 | //=============================================================================== 261 | // u8 __OpenFileRd(u8* Buffer, u8* FileName, u16* Cluster, u32* pDirAddr)// 262 | //------------------------------------------------------------------------------- 263 | .globl __OpenFileRd 264 | .thumb_func 265 | . = BIOS + 0x8D 266 | __OpenFileRd: 267 | //=============================================================================== 268 | // u8 __ReadFileSec(u8* Buffer, u16* Cluster)// 269 | //------------------------------------------------------------------------------- 270 | .globl __ReadFileSec 271 | .thumb_func 272 | . = BIOS + 0x91 273 | __ReadFileSec: 274 | //=============================================================================== 275 | // u8 __ProgFileSec(u8* Buffer, u16* Cluster)// 276 | //------------------------------------------------------------------------------- 277 | .globl __ProgFileSec 278 | .thumb_func 279 | . = BIOS + 0x95 280 | __ProgFileSec: 281 | //=============================================================================== 282 | // u8 __CloseFile(u8* Buffer, u32 Lenght, u16* Cluster, u32* pDirAddr)// 283 | //------------------------------------------------------------------------------- 284 | .globl __CloseFile 285 | .thumb_func 286 | . = BIOS + 0x99 287 | __CloseFile: 288 | //=============================================================================== 289 | // void __Row_Fill(uc16 *S_Buffer,u16 *T_Buffer) Fill one row base data to buffer 290 | //------------------------------------------------------------------------------- 291 | .globl __Row_Fill 292 | .thumb_func 293 | . = BIOS + 0x9D 294 | __Row_Fill: 295 | //=============================================================================== 296 | 297 | //******************************* END OF FILE *********************************** 298 | -------------------------------------------------------------------------------- /FWLib/inc/Command Prompt.lnk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/FWLib/inc/Command Prompt.lnk -------------------------------------------------------------------------------- /FWLib/inc/cortexm3_macro.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : cortexm3_macro.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.3 5 | * Date : 09/22/2008 6 | * Description : Header file for cortexm3_macro.s. 7 | ******************************************************************************** 8 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 9 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 10 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 11 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 12 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 13 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 14 | *******************************************************************************/ 15 | 16 | /* Define to prevent recursive inclusion -------------------------------------*/ 17 | #ifndef __CORTEXM3_MACRO_H 18 | #define __CORTEXM3_MACRO_H 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "stm32f10x_type.h" 22 | 23 | /* Exported types ------------------------------------------------------------*/ 24 | /* Exported constants --------------------------------------------------------*/ 25 | /* Exported macro ------------------------------------------------------------*/ 26 | /* Exported functions ------------------------------------------------------- */ 27 | void __WFI(void); 28 | void __WFE(void); 29 | void __SEV(void); 30 | void __ISB(void); 31 | void __DSB(void); 32 | void __DMB(void); 33 | void __SVC(void); 34 | u32 __MRS_CONTROL(void); 35 | void __MSR_CONTROL(u32 Control); 36 | u32 __MRS_PSP(void); 37 | void __MSR_PSP(u32 TopOfProcessStack); 38 | u32 __MRS_MSP(void); 39 | void __MSR_MSP(u32 TopOfMainStack); 40 | void __RESETPRIMASK(void); 41 | void __SETPRIMASK(void); 42 | u32 __READ_PRIMASK(void); 43 | void __RESETFAULTMASK(void); 44 | void __SETFAULTMASK(void); 45 | u32 __READ_FAULTMASK(void); 46 | void __BASEPRICONFIG(u32 NewPriority); 47 | u32 __GetBASEPRI(void); 48 | u16 __REV_HalfWord(u16 Data); 49 | u32 __REV_Word(u32 Data); 50 | 51 | #endif /* __CORTEXM3_MACRO_H */ 52 | 53 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 54 | -------------------------------------------------------------------------------- /FWLib/inc/stm32f10x_dac.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_dac.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.3 5 | * Date : 09/22/2008 6 | * Description : This file contains all the functions prototypes for the 7 | * DAC firmware library. 8 | ******************************************************************************** 9 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 13 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 15 | *******************************************************************************/ 16 | 17 | /* Define to prevent recursive inclusion -------------------------------------*/ 18 | #ifndef __STM32F10x_DAC_H 19 | #define __STM32F10x_DAC_H 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_map.h" 23 | 24 | /* Exported types ------------------------------------------------------------*/ 25 | /* DAC Init structure definition */ 26 | typedef struct 27 | { 28 | u32 DAC_Trigger; 29 | u32 DAC_WaveGeneration; 30 | u32 DAC_LFSRUnmask_TriangleAmplitude; 31 | u32 DAC_OutputBuffer; 32 | }DAC_InitTypeDef; 33 | 34 | /* Exported constants --------------------------------------------------------*/ 35 | /* DAC trigger selection */ 36 | #define DAC_Trigger_None ((u32)0x00000000) 37 | #define DAC_Trigger_T6_TRGO ((u32)0x00000004) 38 | #define DAC_Trigger_T8_TRGO ((u32)0x0000000C) 39 | #define DAC_Trigger_T7_TRGO ((u32)0x00000014) 40 | #define DAC_Trigger_T5_TRGO ((u32)0x0000001C) 41 | #define DAC_Trigger_T2_TRGO ((u32)0x00000024) 42 | #define DAC_Trigger_T4_TRGO ((u32)0x0000002C) 43 | #define DAC_Trigger_Ext_IT9 ((u32)0x00000034) 44 | #define DAC_Trigger_Software ((u32)0x0000003C) 45 | 46 | #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ 47 | ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ 48 | ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ 49 | ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ 50 | ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ 51 | ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ 52 | ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ 53 | ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ 54 | ((TRIGGER) == DAC_Trigger_Software)) 55 | 56 | /* DAC wave generation */ 57 | #define DAC_WaveGeneration_None ((u32)0x00000000) 58 | #define DAC_WaveGeneration_Noise ((u32)0x00000040) 59 | #define DAC_WaveGeneration_Triangle ((u32)0x00000080) 60 | 61 | #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ 62 | ((WAVE) == DAC_WaveGeneration_Noise) || \ 63 | ((WAVE) == DAC_WaveGeneration_Triangle)) 64 | 65 | /* DAC noise wave generation mask / triangle wave generation max amplitude */ 66 | #define DAC_LFSRUnmask_Bit0 ((u32)0x00000000) 67 | #define DAC_LFSRUnmask_Bits1_0 ((u32)0x00000100) 68 | #define DAC_LFSRUnmask_Bits2_0 ((u32)0x00000200) 69 | #define DAC_LFSRUnmask_Bits3_0 ((u32)0x00000300) 70 | #define DAC_LFSRUnmask_Bits4_0 ((u32)0x00000400) 71 | #define DAC_LFSRUnmask_Bits5_0 ((u32)0x00000500) 72 | #define DAC_LFSRUnmask_Bits6_0 ((u32)0x00000600) 73 | #define DAC_LFSRUnmask_Bits7_0 ((u32)0x00000700) 74 | #define DAC_LFSRUnmask_Bits8_0 ((u32)0x00000800) 75 | #define DAC_LFSRUnmask_Bits9_0 ((u32)0x00000900) 76 | #define DAC_LFSRUnmask_Bits10_0 ((u32)0x00000A00) 77 | #define DAC_LFSRUnmask_Bits11_0 ((u32)0x00000B00) 78 | 79 | #define DAC_TriangleAmplitude_1 ((u32)0x00000000) 80 | #define DAC_TriangleAmplitude_3 ((u32)0x00000100) 81 | #define DAC_TriangleAmplitude_7 ((u32)0x00000200) 82 | #define DAC_TriangleAmplitude_15 ((u32)0x00000300) 83 | #define DAC_TriangleAmplitude_31 ((u32)0x00000400) 84 | #define DAC_TriangleAmplitude_63 ((u32)0x00000500) 85 | #define DAC_TriangleAmplitude_127 ((u32)0x00000600) 86 | #define DAC_TriangleAmplitude_255 ((u32)0x00000700) 87 | #define DAC_TriangleAmplitude_511 ((u32)0x00000800) 88 | #define DAC_TriangleAmplitude_1023 ((u32)0x00000900) 89 | #define DAC_TriangleAmplitude_2047 ((u32)0x00000A00) 90 | #define DAC_TriangleAmplitude_4095 ((u32)0x00000B00) 91 | 92 | #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ 93 | ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ 94 | ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ 95 | ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ 96 | ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ 97 | ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ 98 | ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ 99 | ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ 100 | ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ 101 | ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ 102 | ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ 103 | ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ 104 | ((VALUE) == DAC_TriangleAmplitude_1) || \ 105 | ((VALUE) == DAC_TriangleAmplitude_3) || \ 106 | ((VALUE) == DAC_TriangleAmplitude_7) || \ 107 | ((VALUE) == DAC_TriangleAmplitude_15) || \ 108 | ((VALUE) == DAC_TriangleAmplitude_31) || \ 109 | ((VALUE) == DAC_TriangleAmplitude_63) || \ 110 | ((VALUE) == DAC_TriangleAmplitude_127) || \ 111 | ((VALUE) == DAC_TriangleAmplitude_255) || \ 112 | ((VALUE) == DAC_TriangleAmplitude_511) || \ 113 | ((VALUE) == DAC_TriangleAmplitude_1023) || \ 114 | ((VALUE) == DAC_TriangleAmplitude_2047) || \ 115 | ((VALUE) == DAC_TriangleAmplitude_4095)) 116 | 117 | /* DAC output buffer */ 118 | #define DAC_OutputBuffer_Enable ((u32)0x00000000) 119 | #define DAC_OutputBuffer_Disable ((u32)0x00000002) 120 | 121 | #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ 122 | ((STATE) == DAC_OutputBuffer_Disable)) 123 | 124 | /* DAC Channel selection */ 125 | #define DAC_Channel_1 ((u32)0x00000000) 126 | #define DAC_Channel_2 ((u32)0x00000010) 127 | 128 | #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ 129 | ((CHANNEL) == DAC_Channel_2)) 130 | 131 | /* DAC data alignement */ 132 | #define DAC_Align_12b_R ((u32)0x00000000) 133 | #define DAC_Align_12b_L ((u32)0x00000004) 134 | #define DAC_Align_8b_R ((u32)0x00000008) 135 | 136 | #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ 137 | ((ALIGN) == DAC_Align_12b_L) || \ 138 | ((ALIGN) == DAC_Align_8b_R)) 139 | 140 | /* DAC wave generation */ 141 | #define DAC_Wave_Noise ((u32)0x00000040) 142 | #define DAC_Wave_Triangle ((u32)0x00000080) 143 | 144 | #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ 145 | ((WAVE) == DAC_Wave_Triangle)) 146 | 147 | /* DAC data ------------------------------------------------------------------*/ 148 | #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 149 | 150 | /* Exported macro ------------------------------------------------------------*/ 151 | /* Exported functions --------------------------------------------------------*/ 152 | void DAC_DeInit(void); 153 | void DAC_Init(u32 DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); 154 | void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); 155 | void DAC_Cmd(u32 DAC_Channel, FunctionalState NewState); 156 | void DAC_DMACmd(u32 DAC_Channel, FunctionalState NewState); 157 | void DAC_SoftwareTriggerCmd(u32 DAC_Channel, FunctionalState NewState); 158 | void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); 159 | void DAC_WaveGenerationCmd(u32 DAC_Channel, u32 DAC_Wave, FunctionalState NewState); 160 | void DAC_SetChannel1Data(u32 DAC_Align, u16 Data); 161 | void DAC_SetChannel2Data(u32 DAC_Align, u16 Data); 162 | void DAC_SetDualChannelData(u32 DAC_Align, u16 Data2, u16 Data1); 163 | u16 DAC_GetDataOutputValue(u32 DAC_Channel); 164 | 165 | #endif /*__STM32F10x_DAC_H */ 166 | 167 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 168 | -------------------------------------------------------------------------------- /FWLib/inc/stm32f10x_dma.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_dma.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.3 5 | * Date : 09/22/2008 6 | * Description : This file contains all the functions prototypes for the 7 | * DMA firmware library. 8 | ******************************************************************************** 9 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 13 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 15 | *******************************************************************************/ 16 | 17 | /* Define to prevent recursive inclusion -------------------------------------*/ 18 | #ifndef __STM32F10x_DMA_H 19 | #define __STM32F10x_DMA_H 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_map.h" 23 | 24 | /* Exported types ------------------------------------------------------------*/ 25 | /* DMA Init structure definition */ 26 | typedef struct 27 | { 28 | u32 DMA_PeripheralBaseAddr; 29 | u32 DMA_MemoryBaseAddr; 30 | u32 DMA_DIR; 31 | u32 DMA_BufferSize; 32 | u32 DMA_PeripheralInc; 33 | u32 DMA_MemoryInc; 34 | u32 DMA_PeripheralDataSize; 35 | u32 DMA_MemoryDataSize; 36 | u32 DMA_Mode; 37 | u32 DMA_Priority; 38 | u32 DMA_M2M; 39 | }DMA_InitTypeDef; 40 | 41 | /* Exported constants --------------------------------------------------------*/ 42 | #define IS_DMA_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == DMA1_Channel1_BASE) || \ 43 | ((*(u32*)&(PERIPH)) == DMA1_Channel2_BASE) || \ 44 | ((*(u32*)&(PERIPH)) == DMA1_Channel3_BASE) || \ 45 | ((*(u32*)&(PERIPH)) == DMA1_Channel4_BASE) || \ 46 | ((*(u32*)&(PERIPH)) == DMA1_Channel5_BASE) || \ 47 | ((*(u32*)&(PERIPH)) == DMA1_Channel6_BASE) || \ 48 | ((*(u32*)&(PERIPH)) == DMA1_Channel7_BASE) || \ 49 | ((*(u32*)&(PERIPH)) == DMA2_Channel1_BASE) || \ 50 | ((*(u32*)&(PERIPH)) == DMA2_Channel2_BASE) || \ 51 | ((*(u32*)&(PERIPH)) == DMA2_Channel3_BASE) || \ 52 | ((*(u32*)&(PERIPH)) == DMA2_Channel4_BASE) || \ 53 | ((*(u32*)&(PERIPH)) == DMA2_Channel5_BASE)) 54 | 55 | /* DMA data transfer direction -----------------------------------------------*/ 56 | #define DMA_DIR_PeripheralDST ((u32)0x00000010) 57 | #define DMA_DIR_PeripheralSRC ((u32)0x00000000) 58 | 59 | #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ 60 | ((DIR) == DMA_DIR_PeripheralSRC)) 61 | 62 | /* DMA peripheral incremented mode -------------------------------------------*/ 63 | #define DMA_PeripheralInc_Enable ((u32)0x00000040) 64 | #define DMA_PeripheralInc_Disable ((u32)0x00000000) 65 | 66 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ 67 | ((STATE) == DMA_PeripheralInc_Disable)) 68 | 69 | /* DMA memory incremented mode -----------------------------------------------*/ 70 | #define DMA_MemoryInc_Enable ((u32)0x00000080) 71 | #define DMA_MemoryInc_Disable ((u32)0x00000000) 72 | 73 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ 74 | ((STATE) == DMA_MemoryInc_Disable)) 75 | 76 | /* DMA peripheral data size --------------------------------------------------*/ 77 | #define DMA_PeripheralDataSize_Byte ((u32)0x00000000) 78 | #define DMA_PeripheralDataSize_HalfWord ((u32)0x00000100) 79 | #define DMA_PeripheralDataSize_Word ((u32)0x00000200) 80 | 81 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ 82 | ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ 83 | ((SIZE) == DMA_PeripheralDataSize_Word)) 84 | 85 | /* DMA memory data size ------------------------------------------------------*/ 86 | #define DMA_MemoryDataSize_Byte ((u32)0x00000000) 87 | #define DMA_MemoryDataSize_HalfWord ((u32)0x00000400) 88 | #define DMA_MemoryDataSize_Word ((u32)0x00000800) 89 | 90 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ 91 | ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ 92 | ((SIZE) == DMA_MemoryDataSize_Word)) 93 | 94 | /* DMA circular/normal mode --------------------------------------------------*/ 95 | #define DMA_Mode_Circular ((u32)0x00000020) 96 | #define DMA_Mode_Normal ((u32)0x00000000) 97 | 98 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) 99 | 100 | /* DMA priority level --------------------------------------------------------*/ 101 | #define DMA_Priority_VeryHigh ((u32)0x00003000) 102 | #define DMA_Priority_High ((u32)0x00002000) 103 | #define DMA_Priority_Medium ((u32)0x00001000) 104 | #define DMA_Priority_Low ((u32)0x00000000) 105 | 106 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ 107 | ((PRIORITY) == DMA_Priority_High) || \ 108 | ((PRIORITY) == DMA_Priority_Medium) || \ 109 | ((PRIORITY) == DMA_Priority_Low)) 110 | 111 | /* DMA memory to memory ------------------------------------------------------*/ 112 | #define DMA_M2M_Enable ((u32)0x00004000) 113 | #define DMA_M2M_Disable ((u32)0x00000000) 114 | 115 | #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) 116 | 117 | /* DMA interrupts definition -------------------------------------------------*/ 118 | #define DMA_IT_TC ((u32)0x00000002) 119 | #define DMA_IT_HT ((u32)0x00000004) 120 | #define DMA_IT_TE ((u32)0x00000008) 121 | 122 | #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) 123 | 124 | /* For DMA1 */ 125 | #define DMA1_IT_GL1 ((u32)0x00000001) 126 | #define DMA1_IT_TC1 ((u32)0x00000002) 127 | #define DMA1_IT_HT1 ((u32)0x00000004) 128 | #define DMA1_IT_TE1 ((u32)0x00000008) 129 | #define DMA1_IT_GL2 ((u32)0x00000010) 130 | #define DMA1_IT_TC2 ((u32)0x00000020) 131 | #define DMA1_IT_HT2 ((u32)0x00000040) 132 | #define DMA1_IT_TE2 ((u32)0x00000080) 133 | #define DMA1_IT_GL3 ((u32)0x00000100) 134 | #define DMA1_IT_TC3 ((u32)0x00000200) 135 | #define DMA1_IT_HT3 ((u32)0x00000400) 136 | #define DMA1_IT_TE3 ((u32)0x00000800) 137 | #define DMA1_IT_GL4 ((u32)0x00001000) 138 | #define DMA1_IT_TC4 ((u32)0x00002000) 139 | #define DMA1_IT_HT4 ((u32)0x00004000) 140 | #define DMA1_IT_TE4 ((u32)0x00008000) 141 | #define DMA1_IT_GL5 ((u32)0x00010000) 142 | #define DMA1_IT_TC5 ((u32)0x00020000) 143 | #define DMA1_IT_HT5 ((u32)0x00040000) 144 | #define DMA1_IT_TE5 ((u32)0x00080000) 145 | #define DMA1_IT_GL6 ((u32)0x00100000) 146 | #define DMA1_IT_TC6 ((u32)0x00200000) 147 | #define DMA1_IT_HT6 ((u32)0x00400000) 148 | #define DMA1_IT_TE6 ((u32)0x00800000) 149 | #define DMA1_IT_GL7 ((u32)0x01000000) 150 | #define DMA1_IT_TC7 ((u32)0x02000000) 151 | #define DMA1_IT_HT7 ((u32)0x04000000) 152 | #define DMA1_IT_TE7 ((u32)0x08000000) 153 | /* For DMA2 */ 154 | #define DMA2_IT_GL1 ((u32)0x10000001) 155 | #define DMA2_IT_TC1 ((u32)0x10000002) 156 | #define DMA2_IT_HT1 ((u32)0x10000004) 157 | #define DMA2_IT_TE1 ((u32)0x10000008) 158 | #define DMA2_IT_GL2 ((u32)0x10000010) 159 | #define DMA2_IT_TC2 ((u32)0x10000020) 160 | #define DMA2_IT_HT2 ((u32)0x10000040) 161 | #define DMA2_IT_TE2 ((u32)0x10000080) 162 | #define DMA2_IT_GL3 ((u32)0x10000100) 163 | #define DMA2_IT_TC3 ((u32)0x10000200) 164 | #define DMA2_IT_HT3 ((u32)0x10000400) 165 | #define DMA2_IT_TE3 ((u32)0x10000800) 166 | #define DMA2_IT_GL4 ((u32)0x10001000) 167 | #define DMA2_IT_TC4 ((u32)0x10002000) 168 | #define DMA2_IT_HT4 ((u32)0x10004000) 169 | #define DMA2_IT_TE4 ((u32)0x10008000) 170 | #define DMA2_IT_GL5 ((u32)0x10010000) 171 | #define DMA2_IT_TC5 ((u32)0x10020000) 172 | #define DMA2_IT_HT5 ((u32)0x10040000) 173 | #define DMA2_IT_TE5 ((u32)0x10080000) 174 | 175 | #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) 176 | #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ 177 | ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ 178 | ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ 179 | ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ 180 | ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ 181 | ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ 182 | ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ 183 | ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ 184 | ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ 185 | ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ 186 | ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ 187 | ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ 188 | ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ 189 | ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ 190 | ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ 191 | ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ 192 | ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ 193 | ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ 194 | ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ 195 | ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ 196 | ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ 197 | ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ 198 | ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ 199 | ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) 200 | 201 | /* DMA flags definition ------------------------------------------------------*/ 202 | /* For DMA1 */ 203 | #define DMA1_FLAG_GL1 ((u32)0x00000001) 204 | #define DMA1_FLAG_TC1 ((u32)0x00000002) 205 | #define DMA1_FLAG_HT1 ((u32)0x00000004) 206 | #define DMA1_FLAG_TE1 ((u32)0x00000008) 207 | #define DMA1_FLAG_GL2 ((u32)0x00000010) 208 | #define DMA1_FLAG_TC2 ((u32)0x00000020) 209 | #define DMA1_FLAG_HT2 ((u32)0x00000040) 210 | #define DMA1_FLAG_TE2 ((u32)0x00000080) 211 | #define DMA1_FLAG_GL3 ((u32)0x00000100) 212 | #define DMA1_FLAG_TC3 ((u32)0x00000200) 213 | #define DMA1_FLAG_HT3 ((u32)0x00000400) 214 | #define DMA1_FLAG_TE3 ((u32)0x00000800) 215 | #define DMA1_FLAG_GL4 ((u32)0x00001000) 216 | #define DMA1_FLAG_TC4 ((u32)0x00002000) 217 | #define DMA1_FLAG_HT4 ((u32)0x00004000) 218 | #define DMA1_FLAG_TE4 ((u32)0x00008000) 219 | #define DMA1_FLAG_GL5 ((u32)0x00010000) 220 | #define DMA1_FLAG_TC5 ((u32)0x00020000) 221 | #define DMA1_FLAG_HT5 ((u32)0x00040000) 222 | #define DMA1_FLAG_TE5 ((u32)0x00080000) 223 | #define DMA1_FLAG_GL6 ((u32)0x00100000) 224 | #define DMA1_FLAG_TC6 ((u32)0x00200000) 225 | #define DMA1_FLAG_HT6 ((u32)0x00400000) 226 | #define DMA1_FLAG_TE6 ((u32)0x00800000) 227 | #define DMA1_FLAG_GL7 ((u32)0x01000000) 228 | #define DMA1_FLAG_TC7 ((u32)0x02000000) 229 | #define DMA1_FLAG_HT7 ((u32)0x04000000) 230 | #define DMA1_FLAG_TE7 ((u32)0x08000000) 231 | /* For DMA2 */ 232 | #define DMA2_FLAG_GL1 ((u32)0x10000001) 233 | #define DMA2_FLAG_TC1 ((u32)0x10000002) 234 | #define DMA2_FLAG_HT1 ((u32)0x10000004) 235 | #define DMA2_FLAG_TE1 ((u32)0x10000008) 236 | #define DMA2_FLAG_GL2 ((u32)0x10000010) 237 | #define DMA2_FLAG_TC2 ((u32)0x10000020) 238 | #define DMA2_FLAG_HT2 ((u32)0x10000040) 239 | #define DMA2_FLAG_TE2 ((u32)0x10000080) 240 | #define DMA2_FLAG_GL3 ((u32)0x10000100) 241 | #define DMA2_FLAG_TC3 ((u32)0x10000200) 242 | #define DMA2_FLAG_HT3 ((u32)0x10000400) 243 | #define DMA2_FLAG_TE3 ((u32)0x10000800) 244 | #define DMA2_FLAG_GL4 ((u32)0x10001000) 245 | #define DMA2_FLAG_TC4 ((u32)0x10002000) 246 | #define DMA2_FLAG_HT4 ((u32)0x10004000) 247 | #define DMA2_FLAG_TE4 ((u32)0x10008000) 248 | #define DMA2_FLAG_GL5 ((u32)0x10010000) 249 | #define DMA2_FLAG_TC5 ((u32)0x10020000) 250 | #define DMA2_FLAG_HT5 ((u32)0x10040000) 251 | #define DMA2_FLAG_TE5 ((u32)0x10080000) 252 | 253 | #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) 254 | #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ 255 | ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ 256 | ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ 257 | ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ 258 | ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ 259 | ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ 260 | ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ 261 | ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ 262 | ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ 263 | ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ 264 | ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ 265 | ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ 266 | ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ 267 | ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ 268 | ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ 269 | ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ 270 | ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ 271 | ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ 272 | ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ 273 | ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ 274 | ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ 275 | ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ 276 | ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ 277 | ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) 278 | 279 | /* DMA Buffer Size -----------------------------------------------------------*/ 280 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) 281 | 282 | /* Exported macro ------------------------------------------------------------*/ 283 | /* Exported functions ------------------------------------------------------- */ 284 | void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); 285 | void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); 286 | void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); 287 | void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); 288 | void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState); 289 | u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); 290 | FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG); 291 | void DMA_ClearFlag(u32 DMA_FLAG); 292 | ITStatus DMA_GetITStatus(u32 DMA_IT); 293 | void DMA_ClearITPendingBit(u32 DMA_IT); 294 | 295 | #endif /*__STM32F10x_DMA_H */ 296 | 297 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 298 | -------------------------------------------------------------------------------- /FWLib/inc/stm32f10x_flash.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_flash.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.3 5 | * Date : 09/22/2008 6 | * Description : This file contains all the functions prototypes for the 7 | * FLASH firmware library. 8 | ******************************************************************************** 9 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 13 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 15 | *******************************************************************************/ 16 | 17 | /* Define to prevent recursive inclusion -------------------------------------*/ 18 | #ifndef __STM32F10x_FLASH_H 19 | #define __STM32F10x_FLASH_H 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_map.h" 23 | 24 | /* Exported types ------------------------------------------------------------*/ 25 | #ifdef _FLASH_PROG 26 | /* FLASH Status */ 27 | typedef enum 28 | { 29 | FLASH_BUSY = 1, 30 | FLASH_ERROR_PG, 31 | FLASH_ERROR_WRP, 32 | FLASH_COMPLETE, 33 | FLASH_TIMEOUT 34 | }FLASH_Status; 35 | #endif 36 | 37 | /* Flash Latency -------------------------------------------------------------*/ 38 | #define FLASH_Latency_0 ((u32)0x00000000) /* FLASH Zero Latency cycle */ 39 | #define FLASH_Latency_1 ((u32)0x00000001) /* FLASH One Latency cycle */ 40 | #define FLASH_Latency_2 ((u32)0x00000002) /* FLASH Two Latency cycles */ 41 | 42 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ 43 | ((LATENCY) == FLASH_Latency_1) || \ 44 | ((LATENCY) == FLASH_Latency_2)) 45 | 46 | /* Half Cycle Enable/Disable -------------------------------------------------*/ 47 | #define FLASH_HalfCycleAccess_Enable ((u32)0x00000008) /* FLASH Half Cycle Enable */ 48 | #define FLASH_HalfCycleAccess_Disable ((u32)0x00000000) /* FLASH Half Cycle Disable */ 49 | 50 | #define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ 51 | ((STATE) == FLASH_HalfCycleAccess_Disable)) 52 | 53 | 54 | /* Prefetch Buffer Enable/Disable --------------------------------------------*/ 55 | #define FLASH_PrefetchBuffer_Enable ((u32)0x00000010) /* FLASH Prefetch Buffer Enable */ 56 | #define FLASH_PrefetchBuffer_Disable ((u32)0x00000000) /* FLASH Prefetch Buffer Disable */ 57 | 58 | #define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ 59 | ((STATE) == FLASH_PrefetchBuffer_Disable)) 60 | 61 | #ifdef _FLASH_PROG 62 | /* Option Bytes Write Protection ---------------------------------------------*/ 63 | /* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density 64 | ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */ 65 | #define FLASH_WRProt_Pages0to3 ((u32)0x00000001) /* Write protection of page 0 to 3 */ 66 | #define FLASH_WRProt_Pages4to7 ((u32)0x00000002) /* Write protection of page 4 to 7 */ 67 | #define FLASH_WRProt_Pages8to11 ((u32)0x00000004) /* Write protection of page 8 to 11 */ 68 | #define FLASH_WRProt_Pages12to15 ((u32)0x00000008) /* Write protection of page 12 to 15 */ 69 | #define FLASH_WRProt_Pages16to19 ((u32)0x00000010) /* Write protection of page 16 to 19 */ 70 | #define FLASH_WRProt_Pages20to23 ((u32)0x00000020) /* Write protection of page 20 to 23 */ 71 | #define FLASH_WRProt_Pages24to27 ((u32)0x00000040) /* Write protection of page 24 to 27 */ 72 | #define FLASH_WRProt_Pages28to31 ((u32)0x00000080) /* Write protection of page 28 to 31 */ 73 | #define FLASH_WRProt_Pages32to35 ((u32)0x00000100) /* Write protection of page 32 to 35 */ 74 | #define FLASH_WRProt_Pages36to39 ((u32)0x00000200) /* Write protection of page 36 to 39 */ 75 | #define FLASH_WRProt_Pages40to43 ((u32)0x00000400) /* Write protection of page 40 to 43 */ 76 | #define FLASH_WRProt_Pages44to47 ((u32)0x00000800) /* Write protection of page 44 to 47 */ 77 | #define FLASH_WRProt_Pages48to51 ((u32)0x00001000) /* Write protection of page 48 to 51 */ 78 | #define FLASH_WRProt_Pages52to55 ((u32)0x00002000) /* Write protection of page 52 to 55 */ 79 | #define FLASH_WRProt_Pages56to59 ((u32)0x00004000) /* Write protection of page 56 to 59 */ 80 | #define FLASH_WRProt_Pages60to63 ((u32)0x00008000) /* Write protection of page 60 to 63 */ 81 | #define FLASH_WRProt_Pages64to67 ((u32)0x00010000) /* Write protection of page 64 to 67 */ 82 | #define FLASH_WRProt_Pages68to71 ((u32)0x00020000) /* Write protection of page 68 to 71 */ 83 | #define FLASH_WRProt_Pages72to75 ((u32)0x00040000) /* Write protection of page 72 to 75 */ 84 | #define FLASH_WRProt_Pages76to79 ((u32)0x00080000) /* Write protection of page 76 to 79 */ 85 | #define FLASH_WRProt_Pages80to83 ((u32)0x00100000) /* Write protection of page 80 to 83 */ 86 | #define FLASH_WRProt_Pages84to87 ((u32)0x00200000) /* Write protection of page 84 to 87 */ 87 | #define FLASH_WRProt_Pages88to91 ((u32)0x00400000) /* Write protection of page 88 to 91 */ 88 | #define FLASH_WRProt_Pages92to95 ((u32)0x00800000) /* Write protection of page 92 to 95 */ 89 | #define FLASH_WRProt_Pages96to99 ((u32)0x01000000) /* Write protection of page 96 to 99 */ 90 | #define FLASH_WRProt_Pages100to103 ((u32)0x02000000) /* Write protection of page 100 to 103 */ 91 | #define FLASH_WRProt_Pages104to107 ((u32)0x04000000) /* Write protection of page 104 to 107 */ 92 | #define FLASH_WRProt_Pages108to111 ((u32)0x08000000) /* Write protection of page 108 to 111 */ 93 | #define FLASH_WRProt_Pages112to115 ((u32)0x10000000) /* Write protection of page 112 to 115 */ 94 | #define FLASH_WRProt_Pages116to119 ((u32)0x20000000) /* Write protection of page 115 to 119 */ 95 | #define FLASH_WRProt_Pages120to123 ((u32)0x40000000) /* Write protection of page 120 to 123 */ 96 | #define FLASH_WRProt_Pages124to127 ((u32)0x80000000) /* Write protection of page 124 to 127 */ 97 | /* Values to be used with STM32F10Xxx High-density devices: FLASH memory density 98 | ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */ 99 | #define FLASH_WRProt_Pages0to1 ((u32)0x00000001) /* Write protection of page 0 to 1 */ 100 | #define FLASH_WRProt_Pages2to3 ((u32)0x00000002) /* Write protection of page 2 to 3 */ 101 | #define FLASH_WRProt_Pages4to5 ((u32)0x00000004) /* Write protection of page 4 to 5 */ 102 | #define FLASH_WRProt_Pages6to7 ((u32)0x00000008) /* Write protection of page 6 to 7 */ 103 | #define FLASH_WRProt_Pages8to9 ((u32)0x00000010) /* Write protection of page 8 to 9 */ 104 | #define FLASH_WRProt_Pages10to11 ((u32)0x00000020) /* Write protection of page 10 to 11 */ 105 | #define FLASH_WRProt_Pages12to13 ((u32)0x00000040) /* Write protection of page 12 to 13 */ 106 | #define FLASH_WRProt_Pages14to15 ((u32)0x00000080) /* Write protection of page 14 to 15 */ 107 | #define FLASH_WRProt_Pages16to17 ((u32)0x00000100) /* Write protection of page 16 to 17 */ 108 | #define FLASH_WRProt_Pages18to19 ((u32)0x00000200) /* Write protection of page 18 to 19 */ 109 | #define FLASH_WRProt_Pages20to21 ((u32)0x00000400) /* Write protection of page 20 to 21 */ 110 | #define FLASH_WRProt_Pages22to23 ((u32)0x00000800) /* Write protection of page 22 to 23 */ 111 | #define FLASH_WRProt_Pages24to25 ((u32)0x00001000) /* Write protection of page 24 to 25 */ 112 | #define FLASH_WRProt_Pages26to27 ((u32)0x00002000) /* Write protection of page 26 to 27 */ 113 | #define FLASH_WRProt_Pages28to29 ((u32)0x00004000) /* Write protection of page 28 to 29 */ 114 | #define FLASH_WRProt_Pages30to31 ((u32)0x00008000) /* Write protection of page 30 to 31 */ 115 | #define FLASH_WRProt_Pages32to33 ((u32)0x00010000) /* Write protection of page 32 to 33 */ 116 | #define FLASH_WRProt_Pages34to35 ((u32)0x00020000) /* Write protection of page 34 to 35 */ 117 | #define FLASH_WRProt_Pages36to37 ((u32)0x00040000) /* Write protection of page 36 to 37 */ 118 | #define FLASH_WRProt_Pages38to39 ((u32)0x00080000) /* Write protection of page 38 to 39 */ 119 | #define FLASH_WRProt_Pages40to41 ((u32)0x00100000) /* Write protection of page 40 to 41 */ 120 | #define FLASH_WRProt_Pages42to43 ((u32)0x00200000) /* Write protection of page 42 to 43 */ 121 | #define FLASH_WRProt_Pages44to45 ((u32)0x00400000) /* Write protection of page 44 to 45 */ 122 | #define FLASH_WRProt_Pages46to47 ((u32)0x00800000) /* Write protection of page 46 to 47 */ 123 | #define FLASH_WRProt_Pages48to49 ((u32)0x01000000) /* Write protection of page 48 to 49 */ 124 | #define FLASH_WRProt_Pages50to51 ((u32)0x02000000) /* Write protection of page 50 to 51 */ 125 | #define FLASH_WRProt_Pages52to53 ((u32)0x04000000) /* Write protection of page 52 to 53 */ 126 | #define FLASH_WRProt_Pages54to55 ((u32)0x08000000) /* Write protection of page 54 to 55 */ 127 | #define FLASH_WRProt_Pages56to57 ((u32)0x10000000) /* Write protection of page 56 to 57 */ 128 | #define FLASH_WRProt_Pages58to59 ((u32)0x20000000) /* Write protection of page 58 to 59 */ 129 | #define FLASH_WRProt_Pages60to61 ((u32)0x40000000) /* Write protection of page 60 to 61 */ 130 | #define FLASH_WRProt_Pages62to255 ((u32)0x80000000) /* Write protection of page 62 to 255 */ 131 | #define FLASH_WRProt_AllPages ((u32)0xFFFFFFFF) /* Write protection of all Pages */ 132 | 133 | #define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) 134 | 135 | #define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) 136 | #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) 137 | 138 | /* Option Bytes IWatchdog ----------------------------------------------------*/ 139 | #define OB_IWDG_SW ((u16)0x0001) /* Software IWDG selected */ 140 | #define OB_IWDG_HW ((u16)0x0000) /* Hardware IWDG selected */ 141 | 142 | #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) 143 | 144 | /* Option Bytes nRST_STOP ----------------------------------------------------*/ 145 | #define OB_STOP_NoRST ((u16)0x0002) /* No reset generated when entering in STOP */ 146 | #define OB_STOP_RST ((u16)0x0000) /* Reset generated when entering in STOP */ 147 | 148 | #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) 149 | 150 | /* Option Bytes nRST_STDBY ---------------------------------------------------*/ 151 | #define OB_STDBY_NoRST ((u16)0x0004) /* No reset generated when entering in STANDBY */ 152 | #define OB_STDBY_RST ((u16)0x0000) /* Reset generated when entering in STANDBY */ 153 | 154 | #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) 155 | 156 | /* FLASH Interrupts ----------------------------------------------------------*/ 157 | #define FLASH_IT_ERROR ((u32)0x00000400) /* FPEC error interrupt source */ 158 | #define FLASH_IT_EOP ((u32)0x00001000) /* End of FLASH Operation Interrupt source */ 159 | 160 | #define IS_FLASH_IT(IT) ((((IT) & (u32)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) 161 | 162 | /* FLASH Flags ---------------------------------------------------------------*/ 163 | #define FLASH_FLAG_BSY ((u32)0x00000001) /* FLASH Busy flag */ 164 | #define FLASH_FLAG_EOP ((u32)0x00000020) /* FLASH End of Operation flag */ 165 | #define FLASH_FLAG_PGERR ((u32)0x00000004) /* FLASH Program error flag */ 166 | #define FLASH_FLAG_WRPRTERR ((u32)0x00000010) /* FLASH Write protected error flag */ 167 | #define FLASH_FLAG_OPTERR ((u32)0x00000001) /* FLASH Option Byte error flag */ 168 | 169 | #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) 170 | 171 | #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ 172 | ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ 173 | ((FLAG) == FLASH_FLAG_OPTERR)) 174 | #endif 175 | 176 | /* Exported constants --------------------------------------------------------*/ 177 | /* Exported macro ------------------------------------------------------------*/ 178 | /* Exported functions ------------------------------------------------------- */ 179 | void FLASH_SetLatency(u32 FLASH_Latency); 180 | void FLASH_HalfCycleAccessCmd(u32 FLASH_HalfCycleAccess); 181 | void FLASH_PrefetchBufferCmd(u32 FLASH_PrefetchBuffer); 182 | 183 | #ifdef _FLASH_PROG 184 | void FLASH_Unlock(void); 185 | void FLASH_Lock(void); 186 | FLASH_Status FLASH_ErasePage(u32 Page_Address); 187 | FLASH_Status FLASH_EraseAllPages(void); 188 | FLASH_Status FLASH_EraseOptionBytes(void); 189 | FLASH_Status FLASH_ProgramWord(u32 Address, u32 Data); 190 | FLASH_Status FLASH_ProgramHalfWord(u32 Address, u16 Data); 191 | FLASH_Status FLASH_ProgramOptionByteData(u32 Address, u8 Data); 192 | FLASH_Status FLASH_EnableWriteProtection(u32 FLASH_Pages); 193 | FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); 194 | FLASH_Status FLASH_UserOptionByteConfig(u16 OB_IWDG, u16 OB_STOP, u16 OB_STDBY); 195 | u32 FLASH_GetUserOptionByte(void); 196 | u32 FLASH_GetWriteProtectionOptionByte(void); 197 | FlagStatus FLASH_GetReadOutProtectionStatus(void); 198 | FlagStatus FLASH_GetPrefetchBufferStatus(void); 199 | void FLASH_ITConfig(u16 FLASH_IT, FunctionalState NewState); 200 | FlagStatus FLASH_GetFlagStatus(u16 FLASH_FLAG); 201 | void FLASH_ClearFlag(u16 FLASH_FLAG); 202 | FLASH_Status FLASH_GetStatus(void); 203 | FLASH_Status FLASH_WaitForLastOperation(u32 Timeout); 204 | #endif 205 | 206 | #endif /* __STM32F10x_FLASH_H */ 207 | 208 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 209 | -------------------------------------------------------------------------------- /FWLib/inc/stm32f10x_gpio.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_gpio.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.3 5 | * Date : 09/22/2008 6 | * Description : This file contains all the functions prototypes for the 7 | * GPIO firmware library. 8 | ******************************************************************************** 9 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 13 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 15 | *******************************************************************************/ 16 | 17 | /* Define to prevent recursive inclusion -------------------------------------*/ 18 | #ifndef __STM32F10x_GPIO_H 19 | #define __STM32F10x_GPIO_H 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_map.h" 23 | 24 | /* Exported types ------------------------------------------------------------*/ 25 | #define IS_GPIO_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == GPIOA_BASE) || \ 26 | ((*(u32*)&(PERIPH)) == GPIOB_BASE) || \ 27 | ((*(u32*)&(PERIPH)) == GPIOC_BASE) || \ 28 | ((*(u32*)&(PERIPH)) == GPIOD_BASE) || \ 29 | ((*(u32*)&(PERIPH)) == GPIOE_BASE) || \ 30 | ((*(u32*)&(PERIPH)) == GPIOF_BASE) || \ 31 | ((*(u32*)&(PERIPH)) == GPIOG_BASE)) 32 | 33 | /* Output Maximum frequency selection ----------------------------------------*/ 34 | typedef enum 35 | { 36 | GPIO_Speed_10MHz = 1, 37 | GPIO_Speed_2MHz, 38 | GPIO_Speed_50MHz 39 | }GPIOSpeed_TypeDef; 40 | 41 | #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ 42 | ((SPEED) == GPIO_Speed_50MHz)) 43 | 44 | /* Configuration Mode enumeration --------------------------------------------*/ 45 | typedef enum 46 | { GPIO_Mode_AIN = 0x0, 47 | GPIO_Mode_IN_FLOATING = 0x04, 48 | GPIO_Mode_IPD = 0x28, 49 | GPIO_Mode_IPU = 0x48, 50 | GPIO_Mode_Out_OD = 0x14, 51 | GPIO_Mode_Out_PP = 0x10, 52 | GPIO_Mode_AF_OD = 0x1C, 53 | GPIO_Mode_AF_PP = 0x18 54 | }GPIOMode_TypeDef; 55 | 56 | #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ 57 | ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ 58 | ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ 59 | ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) 60 | 61 | /* GPIO Init structure definition */ 62 | typedef struct 63 | { 64 | u16 GPIO_Pin; 65 | GPIOSpeed_TypeDef GPIO_Speed; 66 | GPIOMode_TypeDef GPIO_Mode; 67 | }GPIO_InitTypeDef; 68 | 69 | /* Bit_SET and Bit_RESET enumeration -----------------------------------------*/ 70 | typedef enum 71 | { Bit_RESET = 0, 72 | Bit_SET 73 | }BitAction; 74 | #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) 75 | 76 | /* Exported constants --------------------------------------------------------*/ 77 | /* GPIO pins define ----------------------------------------------------------*/ 78 | #define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */ 79 | #define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */ 80 | #define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */ 81 | #define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */ 82 | #define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */ 83 | #define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */ 84 | #define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */ 85 | #define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */ 86 | #define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */ 87 | #define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */ 88 | #define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */ 89 | #define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */ 90 | #define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */ 91 | #define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */ 92 | #define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */ 93 | #define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */ 94 | #define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */ 95 | 96 | #define IS_GPIO_PIN(PIN) ((((PIN) & (u16)0x00) == 0x00) && ((PIN) != (u16)0x00)) 97 | 98 | #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ 99 | ((PIN) == GPIO_Pin_1) || \ 100 | ((PIN) == GPIO_Pin_2) || \ 101 | ((PIN) == GPIO_Pin_3) || \ 102 | ((PIN) == GPIO_Pin_4) || \ 103 | ((PIN) == GPIO_Pin_5) || \ 104 | ((PIN) == GPIO_Pin_6) || \ 105 | ((PIN) == GPIO_Pin_7) || \ 106 | ((PIN) == GPIO_Pin_8) || \ 107 | ((PIN) == GPIO_Pin_9) || \ 108 | ((PIN) == GPIO_Pin_10) || \ 109 | ((PIN) == GPIO_Pin_11) || \ 110 | ((PIN) == GPIO_Pin_12) || \ 111 | ((PIN) == GPIO_Pin_13) || \ 112 | ((PIN) == GPIO_Pin_14) || \ 113 | ((PIN) == GPIO_Pin_15)) 114 | 115 | /* GPIO Remap define ---------------------------------------------------------*/ 116 | #define GPIO_Remap_SPI1 ((u32)0x00000001) /* SPI1 Alternate Function mapping */ 117 | #define GPIO_Remap_I2C1 ((u32)0x00000002) /* I2C1 Alternate Function mapping */ 118 | #define GPIO_Remap_USART1 ((u32)0x00000004) /* USART1 Alternate Function mapping */ 119 | #define GPIO_Remap_USART2 ((u32)0x00000008) /* USART2 Alternate Function mapping */ 120 | #define GPIO_PartialRemap_USART3 ((u32)0x00140010) /* USART3 Partial Alternate Function mapping */ 121 | #define GPIO_FullRemap_USART3 ((u32)0x00140030) /* USART3 Full Alternate Function mapping */ 122 | #define GPIO_PartialRemap_TIM1 ((u32)0x00160040) /* TIM1 Partial Alternate Function mapping */ 123 | #define GPIO_FullRemap_TIM1 ((u32)0x001600C0) /* TIM1 Full Alternate Function mapping */ 124 | #define GPIO_PartialRemap1_TIM2 ((u32)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ 125 | #define GPIO_PartialRemap2_TIM2 ((u32)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ 126 | #define GPIO_FullRemap_TIM2 ((u32)0x00180300) /* TIM2 Full Alternate Function mapping */ 127 | #define GPIO_PartialRemap_TIM3 ((u32)0x001A0800) /* TIM3 Partial Alternate Function mapping */ 128 | #define GPIO_FullRemap_TIM3 ((u32)0x001A0C00) /* TIM3 Full Alternate Function mapping */ 129 | #define GPIO_Remap_TIM4 ((u32)0x00001000) /* TIM4 Alternate Function mapping */ 130 | #define GPIO_Remap1_CAN ((u32)0x001D4000) /* CAN Alternate Function mapping */ 131 | #define GPIO_Remap2_CAN ((u32)0x001D6000) /* CAN Alternate Function mapping */ 132 | #define GPIO_Remap_PD01 ((u32)0x00008000) /* PD01 Alternate Function mapping */ 133 | #define GPIO_Remap_TIM5CH4_LSI ((u32)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ 134 | #define GPIO_Remap_ADC1_ETRGINJ ((u32)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ 135 | #define GPIO_Remap_ADC1_ETRGREG ((u32)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ 136 | #define GPIO_Remap_ADC2_ETRGINJ ((u32)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ 137 | #define GPIO_Remap_ADC2_ETRGREG ((u32)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ 138 | #define GPIO_Remap_SWJ_NoJTRST ((u32)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ 139 | #define GPIO_Remap_SWJ_JTAGDisable ((u32)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ 140 | #define GPIO_Remap_SWJ_Disable ((u32)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ 141 | 142 | 143 | #define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ 144 | ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ 145 | ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ 146 | ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ 147 | ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ 148 | ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ 149 | ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ 150 | ((REMAP) == GPIO_Remap1_CAN) || ((REMAP) == GPIO_Remap2_CAN) || \ 151 | ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ 152 | ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ 153 | ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ 154 | ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \ 155 | ((REMAP) == GPIO_Remap_SWJ_Disable)) 156 | 157 | /* GPIO Port Sources ---------------------------------------------------------*/ 158 | #define GPIO_PortSourceGPIOA ((u8)0x00) 159 | #define GPIO_PortSourceGPIOB ((u8)0x01) 160 | #define GPIO_PortSourceGPIOC ((u8)0x02) 161 | #define GPIO_PortSourceGPIOD ((u8)0x03) 162 | #define GPIO_PortSourceGPIOE ((u8)0x04) 163 | #define GPIO_PortSourceGPIOF ((u8)0x05) 164 | #define GPIO_PortSourceGPIOG ((u8)0x06) 165 | 166 | #define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ 167 | ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ 168 | ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ 169 | ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ 170 | ((PORTSOURCE) == GPIO_PortSourceGPIOE)) 171 | 172 | #define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ 173 | ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ 174 | ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ 175 | ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ 176 | ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ 177 | ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ 178 | ((PORTSOURCE) == GPIO_PortSourceGPIOG)) 179 | 180 | /* GPIO Pin sources ----------------------------------------------------------*/ 181 | #define GPIO_PinSource0 ((u8)0x00) 182 | #define GPIO_PinSource1 ((u8)0x01) 183 | #define GPIO_PinSource2 ((u8)0x02) 184 | #define GPIO_PinSource3 ((u8)0x03) 185 | #define GPIO_PinSource4 ((u8)0x04) 186 | #define GPIO_PinSource5 ((u8)0x05) 187 | #define GPIO_PinSource6 ((u8)0x06) 188 | #define GPIO_PinSource7 ((u8)0x07) 189 | #define GPIO_PinSource8 ((u8)0x08) 190 | #define GPIO_PinSource9 ((u8)0x09) 191 | #define GPIO_PinSource10 ((u8)0x0A) 192 | #define GPIO_PinSource11 ((u8)0x0B) 193 | #define GPIO_PinSource12 ((u8)0x0C) 194 | #define GPIO_PinSource13 ((u8)0x0D) 195 | #define GPIO_PinSource14 ((u8)0x0E) 196 | #define GPIO_PinSource15 ((u8)0x0F) 197 | 198 | #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ 199 | ((PINSOURCE) == GPIO_PinSource1) || \ 200 | ((PINSOURCE) == GPIO_PinSource2) || \ 201 | ((PINSOURCE) == GPIO_PinSource3) || \ 202 | ((PINSOURCE) == GPIO_PinSource4) || \ 203 | ((PINSOURCE) == GPIO_PinSource5) || \ 204 | ((PINSOURCE) == GPIO_PinSource6) || \ 205 | ((PINSOURCE) == GPIO_PinSource7) || \ 206 | ((PINSOURCE) == GPIO_PinSource8) || \ 207 | ((PINSOURCE) == GPIO_PinSource9) || \ 208 | ((PINSOURCE) == GPIO_PinSource10) || \ 209 | ((PINSOURCE) == GPIO_PinSource11) || \ 210 | ((PINSOURCE) == GPIO_PinSource12) || \ 211 | ((PINSOURCE) == GPIO_PinSource13) || \ 212 | ((PINSOURCE) == GPIO_PinSource14) || \ 213 | ((PINSOURCE) == GPIO_PinSource15)) 214 | 215 | /* Exported macro ------------------------------------------------------------*/ 216 | /* Exported functions ------------------------------------------------------- */ 217 | void GPIO_DeInit(GPIO_TypeDef* GPIOx); 218 | void GPIO_AFIODeInit(void); 219 | void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); 220 | void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); 221 | u8 GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); 222 | u16 GPIO_ReadInputData(GPIO_TypeDef* GPIOx); 223 | u8 GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); 224 | u16 GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); 225 | void GPIO_SetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); 226 | void GPIO_ResetBits(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); 227 | void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u16 GPIO_Pin, BitAction BitVal); 228 | void GPIO_Write(GPIO_TypeDef* GPIOx, u16 PortVal); 229 | void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, u16 GPIO_Pin); 230 | void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); 231 | void GPIO_EventOutputCmd(FunctionalState NewState); 232 | void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState); 233 | void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource); 234 | 235 | #endif /* __STM32F10x_GPIO_H */ 236 | 237 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 238 | -------------------------------------------------------------------------------- /FWLib/inc/stm32f10x_lib.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_lib.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.3 5 | * Date : 09/22/2008 6 | * Description : This file includes the peripherals header files in the 7 | * user application. 8 | ******************************************************************************** 9 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 13 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 15 | *******************************************************************************/ 16 | 17 | /* Define to prevent recursive inclusion -------------------------------------*/ 18 | #ifndef __STM32F10x_LIB_H 19 | #define __STM32F10x_LIB_H 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_map.h" 23 | 24 | #ifdef _ADC 25 | #include "stm32f10x_adc.h" 26 | #endif /*_ADC */ 27 | 28 | #ifdef _BKP 29 | #include "stm32f10x_bkp.h" 30 | #endif /*_BKP */ 31 | 32 | #ifdef _CAN 33 | #include "stm32f10x_can.h" 34 | #endif /*_CAN */ 35 | 36 | #ifdef _CRC 37 | #include "stm32f10x_crc.h" 38 | #endif /*_CRC */ 39 | 40 | #ifdef _DAC 41 | #include "stm32f10x_dac.h" 42 | #endif /*_DAC */ 43 | 44 | #ifdef _DBGMCU 45 | #include "stm32f10x_dbgmcu.h" 46 | #endif /*_DBGMCU */ 47 | 48 | #ifdef _DMA 49 | #include "stm32f10x_dma.h" 50 | #endif /*_DMA */ 51 | 52 | #ifdef _EXTI 53 | #include "stm32f10x_exti.h" 54 | #endif /*_EXTI */ 55 | 56 | #ifdef _FLASH 57 | #include "stm32f10x_flash.h" 58 | #endif /*_FLASH */ 59 | 60 | #ifdef _FSMC 61 | #include "stm32f10x_fsmc.h" 62 | #endif /*_FSMC */ 63 | 64 | #ifdef _GPIO 65 | #include "stm32f10x_gpio.h" 66 | #endif /*_GPIO */ 67 | 68 | #ifdef _I2C 69 | #include "stm32f10x_i2c.h" 70 | #endif /*_I2C */ 71 | 72 | #ifdef _IWDG 73 | #include "stm32f10x_iwdg.h" 74 | #endif /*_IWDG */ 75 | 76 | #ifdef _NVIC 77 | #include "stm32f10x_nvic.h" 78 | #endif /*_NVIC */ 79 | 80 | #ifdef _PWR 81 | #include "stm32f10x_pwr.h" 82 | #endif /*_PWR */ 83 | 84 | #ifdef _RCC 85 | #include "stm32f10x_rcc.h" 86 | #endif /*_RCC */ 87 | 88 | #ifdef _RTC 89 | #include "stm32f10x_rtc.h" 90 | #endif /*_RTC */ 91 | 92 | #ifdef _SDIO 93 | #include "stm32f10x_sdio.h" 94 | #endif /*_SDIO */ 95 | 96 | #ifdef _SPI 97 | #include "stm32f10x_spi.h" 98 | #endif /*_SPI */ 99 | 100 | #ifdef _SysTick 101 | #include "stm32f10x_systick.h" 102 | #endif /*_SysTick */ 103 | 104 | #ifdef _TIM 105 | #include "stm32f10x_tim.h" 106 | #endif /*_TIM */ 107 | 108 | #ifdef _USART 109 | #include "stm32f10x_usart.h" 110 | #endif /*_USART */ 111 | 112 | #ifdef _WWDG 113 | #include "stm32f10x_wwdg.h" 114 | #endif /*_WWDG */ 115 | 116 | /* Exported types ------------------------------------------------------------*/ 117 | /* Exported constants --------------------------------------------------------*/ 118 | /* Exported macro ------------------------------------------------------------*/ 119 | /* Exported functions ------------------------------------------------------- */ 120 | void debug(void); 121 | 122 | #endif /* __STM32F10x_LIB_H */ 123 | 124 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 125 | -------------------------------------------------------------------------------- /FWLib/inc/stm32f10x_rcc.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_rcc.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.3 5 | * Date : 09/22/2008 6 | * Description : This file contains all the functions prototypes for the 7 | * RCC firmware library. 8 | ******************************************************************************** 9 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 13 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 15 | *******************************************************************************/ 16 | 17 | /* Define to prevent recursive inclusion -------------------------------------*/ 18 | #ifndef __STM32F10x_RCC_H 19 | #define __STM32F10x_RCC_H 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_map.h" 23 | 24 | /* Exported types ------------------------------------------------------------*/ 25 | typedef struct 26 | { 27 | u32 SYSCLK_Frequency; 28 | u32 HCLK_Frequency; 29 | u32 PCLK1_Frequency; 30 | u32 PCLK2_Frequency; 31 | u32 ADCCLK_Frequency; 32 | }RCC_ClocksTypeDef; 33 | 34 | /* Exported constants --------------------------------------------------------*/ 35 | /* HSE configuration */ 36 | #define RCC_HSE_OFF ((u32)0x00000000) 37 | #define RCC_HSE_ON ((u32)0x00010000) 38 | #define RCC_HSE_Bypass ((u32)0x00040000) 39 | 40 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 41 | ((HSE) == RCC_HSE_Bypass)) 42 | 43 | /* PLL entry clock source */ 44 | #define RCC_PLLSource_HSI_Div2 ((u32)0x00000000) 45 | #define RCC_PLLSource_HSE_Div1 ((u32)0x00010000) 46 | #define RCC_PLLSource_HSE_Div2 ((u32)0x00030000) 47 | 48 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 49 | ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ 50 | ((SOURCE) == RCC_PLLSource_HSE_Div2)) 51 | 52 | /* PLL multiplication factor */ 53 | #define RCC_PLLMul_2 ((u32)0x00000000) 54 | #define RCC_PLLMul_3 ((u32)0x00040000) 55 | #define RCC_PLLMul_4 ((u32)0x00080000) 56 | #define RCC_PLLMul_5 ((u32)0x000C0000) 57 | #define RCC_PLLMul_6 ((u32)0x00100000) 58 | #define RCC_PLLMul_7 ((u32)0x00140000) 59 | #define RCC_PLLMul_8 ((u32)0x00180000) 60 | #define RCC_PLLMul_9 ((u32)0x001C0000) 61 | #define RCC_PLLMul_10 ((u32)0x00200000) 62 | #define RCC_PLLMul_11 ((u32)0x00240000) 63 | #define RCC_PLLMul_12 ((u32)0x00280000) 64 | #define RCC_PLLMul_13 ((u32)0x002C0000) 65 | #define RCC_PLLMul_14 ((u32)0x00300000) 66 | #define RCC_PLLMul_15 ((u32)0x00340000) 67 | #define RCC_PLLMul_16 ((u32)0x00380000) 68 | 69 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 70 | ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 71 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 72 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 73 | ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 74 | ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 75 | ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 76 | ((MUL) == RCC_PLLMul_16)) 77 | 78 | /* System clock source */ 79 | #define RCC_SYSCLKSource_HSI ((u32)0x00000000) 80 | #define RCC_SYSCLKSource_HSE ((u32)0x00000001) 81 | #define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002) 82 | 83 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 84 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 85 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 86 | 87 | /* AHB clock source */ 88 | #define RCC_SYSCLK_Div1 ((u32)0x00000000) 89 | #define RCC_SYSCLK_Div2 ((u32)0x00000080) 90 | #define RCC_SYSCLK_Div4 ((u32)0x00000090) 91 | #define RCC_SYSCLK_Div8 ((u32)0x000000A0) 92 | #define RCC_SYSCLK_Div16 ((u32)0x000000B0) 93 | #define RCC_SYSCLK_Div64 ((u32)0x000000C0) 94 | #define RCC_SYSCLK_Div128 ((u32)0x000000D0) 95 | #define RCC_SYSCLK_Div256 ((u32)0x000000E0) 96 | #define RCC_SYSCLK_Div512 ((u32)0x000000F0) 97 | 98 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 99 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 100 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 101 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 102 | ((HCLK) == RCC_SYSCLK_Div512)) 103 | 104 | /* APB1/APB2 clock source */ 105 | #define RCC_HCLK_Div1 ((u32)0x00000000) 106 | #define RCC_HCLK_Div2 ((u32)0x00000400) 107 | #define RCC_HCLK_Div4 ((u32)0x00000500) 108 | #define RCC_HCLK_Div8 ((u32)0x00000600) 109 | #define RCC_HCLK_Div16 ((u32)0x00000700) 110 | 111 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 112 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 113 | ((PCLK) == RCC_HCLK_Div16)) 114 | 115 | /* RCC Interrupt source */ 116 | #define RCC_IT_LSIRDY ((u8)0x01) 117 | #define RCC_IT_LSERDY ((u8)0x02) 118 | #define RCC_IT_HSIRDY ((u8)0x04) 119 | #define RCC_IT_HSERDY ((u8)0x08) 120 | #define RCC_IT_PLLRDY ((u8)0x10) 121 | #define RCC_IT_CSS ((u8)0x80) 122 | 123 | #define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00)) 124 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 125 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 126 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) 127 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00)) 128 | 129 | /* USB clock source */ 130 | #define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00) 131 | #define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01) 132 | 133 | #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ 134 | ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) 135 | 136 | /* ADC clock source */ 137 | #define RCC_PCLK2_Div2 ((u32)0x00000000) 138 | #define RCC_PCLK2_Div4 ((u32)0x00004000) 139 | #define RCC_PCLK2_Div6 ((u32)0x00008000) 140 | #define RCC_PCLK2_Div8 ((u32)0x0000C000) 141 | 142 | #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ 143 | ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) 144 | 145 | /* LSE configuration */ 146 | #define RCC_LSE_OFF ((u8)0x00) 147 | #define RCC_LSE_ON ((u8)0x01) 148 | #define RCC_LSE_Bypass ((u8)0x04) 149 | 150 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 151 | ((LSE) == RCC_LSE_Bypass)) 152 | 153 | /* RTC clock source */ 154 | #define RCC_RTCCLKSource_LSE ((u32)0x00000100) 155 | #define RCC_RTCCLKSource_LSI ((u32)0x00000200) 156 | #define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300) 157 | 158 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 159 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 160 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) 161 | 162 | /* AHB peripheral */ 163 | #define RCC_AHBPeriph_DMA1 ((u32)0x00000001) 164 | #define RCC_AHBPeriph_DMA2 ((u32)0x00000002) 165 | #define RCC_AHBPeriph_SRAM ((u32)0x00000004) 166 | #define RCC_AHBPeriph_FLITF ((u32)0x00000010) 167 | #define RCC_AHBPeriph_CRC ((u32)0x00000040) 168 | #define RCC_AHBPeriph_FSMC ((u32)0x00000100) 169 | #define RCC_AHBPeriph_SDIO ((u32)0x00000400) 170 | 171 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) 172 | 173 | /* APB2 peripheral */ 174 | #define RCC_APB2Periph_AFIO ((u32)0x00000001) 175 | #define RCC_APB2Periph_GPIOA ((u32)0x00000004) 176 | #define RCC_APB2Periph_GPIOB ((u32)0x00000008) 177 | #define RCC_APB2Periph_GPIOC ((u32)0x00000010) 178 | #define RCC_APB2Periph_GPIOD ((u32)0x00000020) 179 | #define RCC_APB2Periph_GPIOE ((u32)0x00000040) 180 | #define RCC_APB2Periph_GPIOF ((u32)0x00000080) 181 | #define RCC_APB2Periph_GPIOG ((u32)0x00000100) 182 | #define RCC_APB2Periph_ADC1 ((u32)0x00000200) 183 | #define RCC_APB2Periph_ADC2 ((u32)0x00000400) 184 | #define RCC_APB2Periph_TIM1 ((u32)0x00000800) 185 | #define RCC_APB2Periph_SPI1 ((u32)0x00001000) 186 | #define RCC_APB2Periph_TIM8 ((u32)0x00002000) 187 | #define RCC_APB2Periph_USART1 ((u32)0x00004000) 188 | #define RCC_APB2Periph_ADC3 ((u32)0x00008000) 189 | #define RCC_APB2Periph_ALL ((u32)0x0000FFFD) 190 | 191 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00)) 192 | 193 | /* APB1 peripheral */ 194 | #define RCC_APB1Periph_TIM2 ((u32)0x00000001) 195 | #define RCC_APB1Periph_TIM3 ((u32)0x00000002) 196 | #define RCC_APB1Periph_TIM4 ((u32)0x00000004) 197 | #define RCC_APB1Periph_TIM5 ((u32)0x00000008) 198 | #define RCC_APB1Periph_TIM6 ((u32)0x00000010) 199 | #define RCC_APB1Periph_TIM7 ((u32)0x00000020) 200 | #define RCC_APB1Periph_WWDG ((u32)0x00000800) 201 | #define RCC_APB1Periph_SPI2 ((u32)0x00004000) 202 | #define RCC_APB1Periph_SPI3 ((u32)0x00008000) 203 | #define RCC_APB1Periph_USART2 ((u32)0x00020000) 204 | #define RCC_APB1Periph_USART3 ((u32)0x00040000) 205 | #define RCC_APB1Periph_UART4 ((u32)0x00080000) 206 | #define RCC_APB1Periph_UART5 ((u32)0x00100000) 207 | #define RCC_APB1Periph_I2C1 ((u32)0x00200000) 208 | #define RCC_APB1Periph_I2C2 ((u32)0x00400000) 209 | #define RCC_APB1Periph_USB ((u32)0x00800000) 210 | #define RCC_APB1Periph_CAN ((u32)0x02000000) 211 | #define RCC_APB1Periph_BKP ((u32)0x08000000) 212 | #define RCC_APB1Periph_PWR ((u32)0x10000000) 213 | #define RCC_APB1Periph_DAC ((u32)0x20000000) 214 | #define RCC_APB1Periph_ALL ((u32)0x3AFEC83F) 215 | 216 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) 217 | 218 | /* Clock source to output on MCO pin */ 219 | #define RCC_MCO_NoClock ((u8)0x00) 220 | #define RCC_MCO_SYSCLK ((u8)0x04) 221 | #define RCC_MCO_HSI ((u8)0x05) 222 | #define RCC_MCO_HSE ((u8)0x06) 223 | #define RCC_MCO_PLLCLK_Div2 ((u8)0x07) 224 | 225 | #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 226 | ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 227 | ((MCO) == RCC_MCO_PLLCLK_Div2)) 228 | 229 | /* RCC Flag */ 230 | #define RCC_FLAG_HSIRDY ((u8)0x21) 231 | #define RCC_FLAG_HSERDY ((u8)0x31) 232 | #define RCC_FLAG_PLLRDY ((u8)0x39) 233 | #define RCC_FLAG_LSERDY ((u8)0x41) 234 | #define RCC_FLAG_LSIRDY ((u8)0x61) 235 | #define RCC_FLAG_PINRST ((u8)0x7A) 236 | #define RCC_FLAG_PORRST ((u8)0x7B) 237 | #define RCC_FLAG_SFTRST ((u8)0x7C) 238 | #define RCC_FLAG_IWDGRST ((u8)0x7D) 239 | #define RCC_FLAG_WWDGRST ((u8)0x7E) 240 | #define RCC_FLAG_LPWRRST ((u8)0x7F) 241 | 242 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 243 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 244 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 245 | ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 246 | ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ 247 | ((FLAG) == RCC_FLAG_LPWRRST)) 248 | 249 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 250 | 251 | /* Exported macro ------------------------------------------------------------*/ 252 | /* Exported functions ------------------------------------------------------- */ 253 | void RCC_DeInit(void); 254 | void RCC_HSEConfig(u32 RCC_HSE); 255 | ErrorStatus RCC_WaitForHSEStartUp(void); 256 | void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue); 257 | void RCC_HSICmd(FunctionalState NewState); 258 | void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul); 259 | void RCC_PLLCmd(FunctionalState NewState); 260 | void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource); 261 | u8 RCC_GetSYSCLKSource(void); 262 | void RCC_HCLKConfig(u32 RCC_SYSCLK); 263 | void RCC_PCLK1Config(u32 RCC_HCLK); 264 | void RCC_PCLK2Config(u32 RCC_HCLK); 265 | void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState); 266 | void RCC_USBCLKConfig(u32 RCC_USBCLKSource); 267 | void RCC_ADCCLKConfig(u32 RCC_PCLK2); 268 | void RCC_LSEConfig(u8 RCC_LSE); 269 | void RCC_LSICmd(FunctionalState NewState); 270 | void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource); 271 | void RCC_RTCCLKCmd(FunctionalState NewState); 272 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 273 | void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState); 274 | void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState); 275 | void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState); 276 | void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState); 277 | void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState); 278 | void RCC_BackupResetCmd(FunctionalState NewState); 279 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 280 | void RCC_MCOConfig(u8 RCC_MCO); 281 | FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG); 282 | void RCC_ClearFlag(void); 283 | ITStatus RCC_GetITStatus(u8 RCC_IT); 284 | void RCC_ClearITPendingBit(u8 RCC_IT); 285 | 286 | #endif /* __STM32F10x_RCC_H */ 287 | 288 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 289 | -------------------------------------------------------------------------------- /FWLib/inc/stm32f10x_spi.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** 2 | * File Name : stm32f10x_spi.h 3 | * Author : MCD Application Team 4 | * Version : V1.0 5 | * Date : 10/08/2007 6 | * Description : This file contains all the functions prototypes for the 7 | * SPI firmware library. 8 | ******************************************************************************** 9 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 13 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 15 | *******************************************************************************/ 16 | 17 | /* Define to prevent recursive inclusion -------------------------------------*/ 18 | #ifndef __STM32F10x_SPI_H 19 | #define __STM32F10x_SPI_H 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_map.h" 23 | 24 | /* Exported types ------------------------------------------------------------*/ 25 | /* SPI Init structure definition */ 26 | typedef struct 27 | { 28 | u16 SPI_Direction; 29 | u16 SPI_Mode; 30 | u16 SPI_DataSize; 31 | u16 SPI_CPOL; 32 | u16 SPI_CPHA; 33 | u16 SPI_NSS; 34 | u16 SPI_BaudRatePrescaler; 35 | u16 SPI_FirstBit; 36 | u16 SPI_CRCPolynomial; 37 | }SPI_InitTypeDef; 38 | 39 | /* Exported constants --------------------------------------------------------*/ 40 | /* SPI data direction mode */ 41 | #define SPI_Direction_2Lines_FullDuplex ((u16)0x0000) 42 | #define SPI_Direction_2Lines_RxOnly ((u16)0x0400) 43 | #define SPI_Direction_1Line_Rx ((u16)0x8000) 44 | #define SPI_Direction_1Line_Tx ((u16)0xC000) 45 | 46 | #define IS_SPI_DIRECTION_MODE(MODE) ((MODE == SPI_Direction_2Lines_FullDuplex) || \ 47 | (MODE == SPI_Direction_2Lines_RxOnly) || \ 48 | (MODE == SPI_Direction_1Line_Rx) || \ 49 | (MODE == SPI_Direction_1Line_Tx)) 50 | 51 | /* SPI master/slave mode */ 52 | #define SPI_Mode_Master ((u16)0x0104) 53 | #define SPI_Mode_Slave ((u16)0x0000) 54 | 55 | #define IS_SPI_MODE(MODE) ((MODE == SPI_Mode_Master) || \ 56 | (MODE == SPI_Mode_Slave)) 57 | 58 | /* SPI data size */ 59 | #define SPI_DataSize_16b ((u16)0x0800) 60 | #define SPI_DataSize_8b ((u16)0x0000) 61 | 62 | #define IS_SPI_DATASIZE(DATASIZE) ((DATASIZE == SPI_DataSize_16b) || \ 63 | (DATASIZE == SPI_DataSize_8b)) 64 | 65 | /* SPI Clock Polarity */ 66 | #define SPI_CPOL_Low ((u16)0x0000) 67 | #define SPI_CPOL_High ((u16)0x0002) 68 | 69 | #define IS_SPI_CPOL(CPOL) ((CPOL == SPI_CPOL_Low) || \ 70 | (CPOL == SPI_CPOL_High)) 71 | 72 | /* SPI Clock Phase */ 73 | #define SPI_CPHA_1Edge ((u16)0x0000) 74 | #define SPI_CPHA_2Edge ((u16)0x0001) 75 | 76 | #define IS_SPI_CPHA(CPHA) ((CPHA == SPI_CPHA_1Edge) || \ 77 | (CPHA == SPI_CPHA_2Edge)) 78 | 79 | /* SPI Slave Select management */ 80 | #define SPI_NSS_Soft ((u16)0x0200) 81 | #define SPI_NSS_Hard ((u16)0x0000) 82 | 83 | #define IS_SPI_NSS(NSS) ((NSS == SPI_NSS_Soft) || \ 84 | (NSS == SPI_NSS_Hard)) 85 | 86 | /* SPI BaudRate Prescaler */ 87 | #define SPI_BaudRatePrescaler_2 ((u16)0x0000) 88 | #define SPI_BaudRatePrescaler_4 ((u16)0x0008) 89 | #define SPI_BaudRatePrescaler_8 ((u16)0x0010) 90 | #define SPI_BaudRatePrescaler_16 ((u16)0x0018) 91 | #define SPI_BaudRatePrescaler_32 ((u16)0x0020) 92 | #define SPI_BaudRatePrescaler_64 ((u16)0x0028) 93 | #define SPI_BaudRatePrescaler_128 ((u16)0x0030) 94 | #define SPI_BaudRatePrescaler_256 ((u16)0x0038) 95 | 96 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) ((PRESCALER == SPI_BaudRatePrescaler_2) || \ 97 | (PRESCALER == SPI_BaudRatePrescaler_4) || \ 98 | (PRESCALER == SPI_BaudRatePrescaler_8) || \ 99 | (PRESCALER == SPI_BaudRatePrescaler_16) || \ 100 | (PRESCALER == SPI_BaudRatePrescaler_32) || \ 101 | (PRESCALER == SPI_BaudRatePrescaler_64) || \ 102 | (PRESCALER == SPI_BaudRatePrescaler_128) || \ 103 | (PRESCALER == SPI_BaudRatePrescaler_256)) 104 | 105 | /* SPI MSB/LSB transmission */ 106 | #define SPI_FirstBit_MSB ((u16)0x0000) 107 | #define SPI_FirstBit_LSB ((u16)0x0080) 108 | 109 | #define IS_SPI_FIRST_BIT(BIT) ((BIT == SPI_FirstBit_MSB) || \ 110 | (BIT == SPI_FirstBit_LSB)) 111 | 112 | /* SPI DMA transfer requests */ 113 | #define SPI_DMAReq_Tx ((u16)0x0002) 114 | #define SPI_DMAReq_Rx ((u16)0x0001) 115 | 116 | #define IS_SPI_DMA_REQ(REQ) (((REQ & (u16)0xFFFC) == 0x00) && (REQ != 0x00)) 117 | 118 | /* SPI NSS internal software mangement */ 119 | #define SPI_NSSInternalSoft_Set ((u16)0x0100) 120 | #define SPI_NSSInternalSoft_Reset ((u16)0xFEFF) 121 | 122 | #define IS_SPI_NSS_INTERNAL(INTERNAL) ((INTERNAL == SPI_NSSInternalSoft_Set) || \ 123 | (INTERNAL == SPI_NSSInternalSoft_Reset)) 124 | 125 | /* SPI CRC Transmit/Receive */ 126 | #define SPI_CRC_Tx ((u8)0x00) 127 | #define SPI_CRC_Rx ((u8)0x01) 128 | 129 | #define IS_SPI_CRC(CRC) ((CRC == SPI_CRC_Tx) || (CRC == SPI_CRC_Rx)) 130 | 131 | /* SPI direction transmit/receive */ 132 | #define SPI_Direction_Rx ((u16)0xBFFF) 133 | #define SPI_Direction_Tx ((u16)0x4000) 134 | 135 | #define IS_SPI_DIRECTION(DIRECTION) ((DIRECTION == SPI_Direction_Rx) || \ 136 | (DIRECTION == SPI_Direction_Tx)) 137 | 138 | /* SPI interrupts definition */ 139 | #define SPI_IT_TXE ((u8)0x71) 140 | #define SPI_IT_RXNE ((u8)0x60) 141 | #define SPI_IT_ERR ((u8)0x50) 142 | 143 | #define IS_SPI_CONFIG_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \ 144 | (IT == SPI_IT_ERR)) 145 | 146 | #define SPI_IT_OVR ((u8)0x56) 147 | #define SPI_IT_MODF ((u8)0x55) 148 | #define SPI_IT_CRCERR ((u8)0x54) 149 | 150 | #define IS_SPI_CLEAR_IT(IT) ((IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \ 151 | (IT == SPI_IT_CRCERR)) 152 | 153 | #define IS_SPI_GET_IT(IT) ((IT == SPI_IT_TXE) || (IT == SPI_IT_RXNE) || \ 154 | (IT == SPI_IT_OVR) || (IT == SPI_IT_MODF) || \ 155 | (IT == SPI_IT_CRCERR)) 156 | 157 | /* SPI flags definition */ 158 | #define SPI_FLAG_RXNE ((u16)0x0001) 159 | #define SPI_FLAG_TXE ((u16)0x0002) 160 | #define SPI_FLAG_CRCERR ((u16)0x0010) 161 | #define SPI_FLAG_MODF ((u16)0x0020) 162 | #define SPI_FLAG_OVR ((u16)0x0040) 163 | #define SPI_FLAG_BSY ((u16)0x0080) 164 | 165 | #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG & (u16)0xFF8F) == 0x00) && (FLAG != 0x00)) 166 | #define IS_SPI_GET_FLAG(FLAG) ((FLAG == SPI_FLAG_BSY) || (FLAG == SPI_FLAG_OVR) || \ 167 | (FLAG == SPI_FLAG_MODF) || (FLAG == SPI_FLAG_CRCERR) || \ 168 | (FLAG == SPI_FLAG_TXE) || (FLAG == SPI_FLAG_RXNE)) 169 | 170 | /* SPI CRC polynomial --------------------------------------------------------*/ 171 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (POLYNOMIAL >= 0x1) 172 | 173 | /* Exported macro ------------------------------------------------------------*/ 174 | /* Exported functions ------------------------------------------------------- */ 175 | void SPI_DeInit(SPI_TypeDef* SPIx); 176 | void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 177 | void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 178 | void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 179 | void SPI_ITConfig(SPI_TypeDef* SPIx, u8 SPI_IT, FunctionalState NewState); 180 | void SPI_DMACmd(SPI_TypeDef* SPIx, u16 SPI_DMAReq, FunctionalState NewState); 181 | void SPI_SendData(SPI_TypeDef* SPIx, u16 Data); 182 | u16 SPI_ReceiveData(SPI_TypeDef* SPIx); 183 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, u16 SPI_NSSInternalSoft); 184 | void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 185 | void SPI_DataSizeConfig(SPI_TypeDef* SPIx, u16 SPI_DataSize); 186 | void SPI_TransmitCRC(SPI_TypeDef* SPIx); 187 | void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); 188 | u16 SPI_GetCRC(SPI_TypeDef* SPIx, u8 SPI_CRC); 189 | u16 SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); 190 | void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, u16 SPI_Direction); 191 | FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_FLAG); 192 | void SPI_ClearFlag(SPI_TypeDef* SPIx, u16 SPI_FLAG); 193 | ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_IT); 194 | void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, u8 SPI_IT); 195 | 196 | #endif /*__STM32F10x_SPI_H */ 197 | 198 | /******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ 199 | -------------------------------------------------------------------------------- /FWLib/inc/stm32f10x_type.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_type.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.3 5 | * Date : 09/22/2008 6 | * Description : This file contains all the common data types used for the 7 | * STM32F10x firmware library. 8 | ******************************************************************************** 9 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 13 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 15 | *******************************************************************************/ 16 | 17 | /* Define to prevent recursive inclusion -------------------------------------*/ 18 | #ifndef __STM32F10x_TYPE_H 19 | #define __STM32F10x_TYPE_H 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | /* Exported types ------------------------------------------------------------*/ 23 | typedef signed long s32; 24 | typedef signed short s16; 25 | typedef signed char s8; 26 | 27 | typedef signed long const sc32; /* Read Only */ 28 | typedef signed short const sc16; /* Read Only */ 29 | typedef signed char const sc8; /* Read Only */ 30 | 31 | typedef volatile signed long vs32; 32 | typedef volatile signed short vs16; 33 | typedef volatile signed char vs8; 34 | 35 | typedef volatile signed long const vsc32; /* Read Only */ 36 | typedef volatile signed short const vsc16; /* Read Only */ 37 | typedef volatile signed char const vsc8; /* Read Only */ 38 | 39 | typedef unsigned long u32; 40 | typedef unsigned short u16; 41 | typedef unsigned char u8; 42 | 43 | typedef unsigned long const uc32; /* Read Only */ 44 | typedef unsigned short const uc16; /* Read Only */ 45 | typedef unsigned char const uc8; /* Read Only */ 46 | 47 | typedef volatile unsigned long vu32; 48 | typedef volatile unsigned short vu16; 49 | typedef volatile unsigned char vu8; 50 | 51 | typedef volatile unsigned long const vuc32; /* Read Only */ 52 | typedef volatile unsigned short const vuc16; /* Read Only */ 53 | typedef volatile unsigned char const vuc8; /* Read Only */ 54 | 55 | typedef enum {FALSE = 0, TRUE = !FALSE} bool; 56 | 57 | typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 58 | 59 | typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 60 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 61 | 62 | typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 63 | 64 | #define U8_MAX ((u8)255) 65 | #define S8_MAX ((s8)127) 66 | #define S8_MIN ((s8)-128) 67 | #define U16_MAX ((u16)65535u) 68 | #define S16_MAX ((s16)32767) 69 | #define S16_MIN ((s16)-32768) 70 | #define U32_MAX ((u32)4294967295uL) 71 | #define S32_MAX ((s32)2147483647) 72 | #define S32_MIN ((s32)-2147483648) 73 | 74 | /* Exported constants --------------------------------------------------------*/ 75 | /* Exported macro ------------------------------------------------------------*/ 76 | /* Exported functions ------------------------------------------------------- */ 77 | 78 | #endif /* __STM32F10x_TYPE_H */ 79 | 80 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 81 | -------------------------------------------------------------------------------- /FWLib/inc/stm32f10x_usart.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_usart.h 3 | * Author : MCD Application Team 4 | * Version : V2.0.3 5 | * Date : 09/22/2008 6 | * Description : This file contains all the functions prototypes for the 7 | * USART firmware library. 8 | ******************************************************************************** 9 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 13 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 15 | *******************************************************************************/ 16 | 17 | /* Define to prevent recursive inclusion -------------------------------------*/ 18 | #ifndef __STM32F10x_USART_H 19 | #define __STM32F10x_USART_H 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_map.h" 23 | 24 | /* Exported types ------------------------------------------------------------*/ 25 | /* USART Init Structure definition */ 26 | typedef struct 27 | { 28 | u32 USART_BaudRate; 29 | u16 USART_WordLength; 30 | u16 USART_StopBits; 31 | u16 USART_Parity; 32 | u16 USART_Mode; 33 | u16 USART_HardwareFlowControl; 34 | } USART_InitTypeDef; 35 | 36 | /* USART Clock Init Structure definition */ 37 | typedef struct 38 | { 39 | u16 USART_Clock; 40 | u16 USART_CPOL; 41 | u16 USART_CPHA; 42 | u16 USART_LastBit; 43 | } USART_ClockInitTypeDef; 44 | 45 | /* Exported constants --------------------------------------------------------*/ 46 | #define IS_USART_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \ 47 | ((*(u32*)&(PERIPH)) == USART2_BASE) || \ 48 | ((*(u32*)&(PERIPH)) == USART3_BASE) || \ 49 | ((*(u32*)&(PERIPH)) == UART4_BASE) || \ 50 | ((*(u32*)&(PERIPH)) == UART5_BASE)) 51 | 52 | #define IS_USART_123_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \ 53 | ((*(u32*)&(PERIPH)) == USART2_BASE) || \ 54 | ((*(u32*)&(PERIPH)) == USART3_BASE)) 55 | 56 | #define IS_USART_1234_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == USART1_BASE) || \ 57 | ((*(u32*)&(PERIPH)) == USART2_BASE) || \ 58 | ((*(u32*)&(PERIPH)) == USART3_BASE) || \ 59 | ((*(u32*)&(PERIPH)) == UART4_BASE)) 60 | 61 | /* USART Word Length ---------------------------------------------------------*/ 62 | #define USART_WordLength_8b ((u16)0x0000) 63 | #define USART_WordLength_9b ((u16)0x1000) 64 | 65 | #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ 66 | ((LENGTH) == USART_WordLength_9b)) 67 | 68 | /* USART Stop Bits -----------------------------------------------------------*/ 69 | #define USART_StopBits_1 ((u16)0x0000) 70 | #define USART_StopBits_0_5 ((u16)0x1000) 71 | #define USART_StopBits_2 ((u16)0x2000) 72 | #define USART_StopBits_1_5 ((u16)0x3000) 73 | 74 | #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ 75 | ((STOPBITS) == USART_StopBits_0_5) || \ 76 | ((STOPBITS) == USART_StopBits_2) || \ 77 | ((STOPBITS) == USART_StopBits_1_5)) 78 | /* USART Parity --------------------------------------------------------------*/ 79 | #define USART_Parity_No ((u16)0x0000) 80 | #define USART_Parity_Even ((u16)0x0400) 81 | #define USART_Parity_Odd ((u16)0x0600) 82 | 83 | #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ 84 | ((PARITY) == USART_Parity_Even) || \ 85 | ((PARITY) == USART_Parity_Odd)) 86 | 87 | /* USART Mode ----------------------------------------------------------------*/ 88 | #define USART_Mode_Rx ((u16)0x0004) 89 | #define USART_Mode_Tx ((u16)0x0008) 90 | 91 | #define IS_USART_MODE(MODE) ((((MODE) & (u16)0xFFF3) == 0x00) && ((MODE) != (u16)0x00)) 92 | 93 | /* USART Hardware Flow Control -----------------------------------------------*/ 94 | #define USART_HardwareFlowControl_None ((u16)0x0000) 95 | #define USART_HardwareFlowControl_RTS ((u16)0x0100) 96 | #define USART_HardwareFlowControl_CTS ((u16)0x0200) 97 | #define USART_HardwareFlowControl_RTS_CTS ((u16)0x0300) 98 | 99 | #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ 100 | (((CONTROL) == USART_HardwareFlowControl_None) || \ 101 | ((CONTROL) == USART_HardwareFlowControl_RTS) || \ 102 | ((CONTROL) == USART_HardwareFlowControl_CTS) || \ 103 | ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) 104 | 105 | #define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \ 106 | ((*(u32*)&(PERIPH)) != UART5_BASE)) \ 107 | || ((HFC) == USART_HardwareFlowControl_None)) 108 | 109 | /* USART Clock ---------------------------------------------------------------*/ 110 | #define USART_Clock_Disable ((u16)0x0000) 111 | #define USART_Clock_Enable ((u16)0x0800) 112 | 113 | #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ 114 | ((CLOCK) == USART_Clock_Enable)) 115 | 116 | /* USART Clock Polarity ------------------------------------------------------*/ 117 | #define USART_CPOL_Low ((u16)0x0000) 118 | #define USART_CPOL_High ((u16)0x0400) 119 | 120 | #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) 121 | 122 | /* USART Clock Phase ---------------------------------------------------------*/ 123 | #define USART_CPHA_1Edge ((u16)0x0000) 124 | #define USART_CPHA_2Edge ((u16)0x0200) 125 | #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) 126 | 127 | /* USART Last Bit ------------------------------------------------------------*/ 128 | #define USART_LastBit_Disable ((u16)0x0000) 129 | #define USART_LastBit_Enable ((u16)0x0100) 130 | 131 | #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ 132 | ((LASTBIT) == USART_LastBit_Enable)) 133 | 134 | /* USART Interrupt definition ------------------------------------------------*/ 135 | #define USART_IT_PE ((u16)0x0028) 136 | #define USART_IT_TXE ((u16)0x0727) 137 | #define USART_IT_TC ((u16)0x0626) 138 | #define USART_IT_RXNE ((u16)0x0525) 139 | #define USART_IT_IDLE ((u16)0x0424) 140 | #define USART_IT_LBD ((u16)0x0846) 141 | #define USART_IT_CTS ((u16)0x096A) 142 | #define USART_IT_ERR ((u16)0x0060) 143 | #define USART_IT_ORE ((u16)0x0360) 144 | #define USART_IT_NE ((u16)0x0260) 145 | #define USART_IT_FE ((u16)0x0160) 146 | 147 | #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ 148 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ 149 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ 150 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) 151 | 152 | #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ 153 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ 154 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ 155 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ 156 | ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) 157 | 158 | #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ 159 | ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) 160 | 161 | #define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(u32*)&(PERIPH)) != UART4_BASE) && \ 162 | ((*(u32*)&(PERIPH)) != UART5_BASE)) \ 163 | || ((USART_IT) != USART_IT_CTS)) 164 | 165 | /* USART DMA Requests --------------------------------------------------------*/ 166 | #define USART_DMAReq_Tx ((u16)0x0080) 167 | #define USART_DMAReq_Rx ((u16)0x0040) 168 | 169 | #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (u16)0xFF3F) == 0x00) && ((DMAREQ) != (u16)0x00)) 170 | 171 | /* USART WakeUp methods ------------------------------------------------------*/ 172 | #define USART_WakeUp_IdleLine ((u16)0x0000) 173 | #define USART_WakeUp_AddressMark ((u16)0x0800) 174 | 175 | #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ 176 | ((WAKEUP) == USART_WakeUp_AddressMark)) 177 | 178 | /* USART LIN Break Detection Length ------------------------------------------*/ 179 | #define USART_LINBreakDetectLength_10b ((u16)0x0000) 180 | #define USART_LINBreakDetectLength_11b ((u16)0x0020) 181 | 182 | #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ 183 | (((LENGTH) == USART_LINBreakDetectLength_10b) || \ 184 | ((LENGTH) == USART_LINBreakDetectLength_11b)) 185 | 186 | /* USART IrDA Low Power ------------------------------------------------------*/ 187 | #define USART_IrDAMode_LowPower ((u16)0x0004) 188 | #define USART_IrDAMode_Normal ((u16)0x0000) 189 | 190 | #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ 191 | ((MODE) == USART_IrDAMode_Normal)) 192 | 193 | /* USART Flags ---------------------------------------------------------------*/ 194 | #define USART_FLAG_CTS ((u16)0x0200) 195 | #define USART_FLAG_LBD ((u16)0x0100) 196 | #define USART_FLAG_TXE ((u16)0x0080) 197 | #define USART_FLAG_TC ((u16)0x0040) 198 | #define USART_FLAG_RXNE ((u16)0x0020) 199 | #define USART_FLAG_IDLE ((u16)0x0010) 200 | #define USART_FLAG_ORE ((u16)0x0008) 201 | #define USART_FLAG_NE ((u16)0x0004) 202 | #define USART_FLAG_FE ((u16)0x0002) 203 | #define USART_FLAG_PE ((u16)0x0001) 204 | 205 | #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ 206 | ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ 207 | ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ 208 | ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ 209 | ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) 210 | 211 | #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (u16)0xFC9F) == 0x00) && ((FLAG) != (u16)0x00)) 212 | 213 | #define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(u32*)&(PERIPH)) != UART4_BASE) &&\ 214 | ((*(u32*)&(PERIPH)) != UART5_BASE)) \ 215 | || ((USART_FLAG) != USART_FLAG_CTS)) 216 | 217 | #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) 218 | #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) 219 | #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) 220 | 221 | /* Exported macro ------------------------------------------------------------*/ 222 | /* Exported functions ------------------------------------------------------- */ 223 | void USART_DeInit(USART_TypeDef* USARTx); 224 | void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); 225 | void USART_StructInit(USART_InitTypeDef* USART_InitStruct); 226 | void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); 227 | void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); 228 | void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); 229 | void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState); 230 | void USART_DMACmd(USART_TypeDef* USARTx, u16 USART_DMAReq, FunctionalState NewState); 231 | void USART_SetAddress(USART_TypeDef* USARTx, u8 USART_Address); 232 | void USART_WakeUpConfig(USART_TypeDef* USARTx, u16 USART_WakeUp); 233 | void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); 234 | void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, u16 USART_LINBreakDetectLength); 235 | void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); 236 | void USART_SendData(USART_TypeDef* USARTx, u16 Data); 237 | u16 USART_ReceiveData(USART_TypeDef* USARTx); 238 | void USART_SendBreak(USART_TypeDef* USARTx); 239 | void USART_SetGuardTime(USART_TypeDef* USARTx, u8 USART_GuardTime); 240 | void USART_SetPrescaler(USART_TypeDef* USARTx, u8 USART_Prescaler); 241 | void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); 242 | void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); 243 | void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); 244 | void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode); 245 | void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); 246 | FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, u16 USART_FLAG); 247 | void USART_ClearFlag(USART_TypeDef* USARTx, u16 USART_FLAG); 248 | ITStatus USART_GetITStatus(USART_TypeDef* USARTx, u16 USART_IT); 249 | void USART_ClearITPendingBit(USART_TypeDef* USARTx, u16 USART_IT); 250 | 251 | #endif /* __STM32F10x_USART_H */ 252 | 253 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 254 | -------------------------------------------------------------------------------- /Files.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/Files.c -------------------------------------------------------------------------------- /Function.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/Function.c -------------------------------------------------------------------------------- /Main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/Main.c -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | #Mods to get this to work with V2.51 original code: 2 | #add -mthumb to AFLAGS 3 | 4 | CROSS=arm-none-eabi- 5 | CC=$(CROSS)gcc 6 | OBJCOPY=$(CROSS)objcopy 7 | LD=$(CROSS)ld 8 | AS=$(CROSS)as 9 | STRIP=$(CROSS)strip 10 | 11 | STM_LIB=FWLib/inc 12 | 13 | #ORIGINAL >>>> CFLAGS = -Wall -Os -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -msoft-float -MD -I $(STM_LIB) 14 | #NEED AT LEAST >>>> CFLAGS = -Os -Iinc -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -I $(STM_LIB) 15 | 16 | #CFLAGS = -Wall -Os -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I $(STM_LIB) 17 | CFLAGS = -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I $(STM_LIB) 18 | 19 | #-os = optimise for size 20 | #-o2 = optimise for speed 21 | #-I = directories for header files 22 | #-Wall = turns on error warnings 23 | #-Werror = makes all warnings into errors 24 | 25 | #AFLAGS = -mcpu=cortex-m3 26 | AFLAGS = -mcpu=cortex-m3 -mthumb 27 | #LDFLAGS = -mcpu=cortex-m3 -lc -lnosys -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float -lstm32 -nostartfiles 28 | 29 | LDFLAGS = -mcpu=cortex-m3 -lc -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float -nostartfiles -Wl,-Map,$*.map 30 | 31 | # tried LDFLAGS = -mcpu=cortex-m3 -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float 32 | 33 | 34 | OBJS = Calibrat.o Draw.o Files.o Function.o Interrupt.o Main.o Menu.o Process.o BIOS.o startup.o stm32f10x_nvic.o 35 | OBJS +=cortexm3_macro.o 36 | #TARGETS = app1.hex app2.hex app3.hex 37 | #TARGETS = app1.hex app2.hex 38 | TARGETS = app1.hex 39 | 40 | 41 | all: $(OBJS) $(TARGETS) 42 | 43 | .PHONY: clean 44 | 45 | clean: 46 | rm -rf $(OBJS) $(TARGETS) 47 | 48 | .c.o: 49 | $(CC) $(CFLAGS) -c -o $@ $*.c 50 | 51 | .S.o: 52 | $(CC) $(AFLAGS) -c -o $@ $*.S 53 | 54 | %.elf: %.lds $(OBJS) 55 | $(CC) -o $@ $(OBJS) $(LDFLAGS) -T $< 56 | 57 | %.bin: %.elf 58 | $(OBJCOPY) -O binary $< $@ 59 | 60 | %.hex: %.elf 61 | $(OBJCOPY) -O ihex $< $@ 62 | -------------------------------------------------------------------------------- /README.TXT: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/README.TXT -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Wildcat V6.5 for hw2.81+ (not compatible with older devices) 2 | = 3 | 4 | How to compile on a Windows Machine 5 | =================================== 6 | 7 | Download the standalone compiler and extract 8 | - 9 | - https://sourcery.mentor.com/public/gnu_toolchain/arm-none-eabi/arm-2008q1-126-arm-none-eabi-i686-mingw32.tar.bz2 10 | - I used Winrar 5.21 to extract the .bz2 to C:\arm-2008q1\ (warning 7zip make some .exe 0 size) 11 | 12 | Add PATH to system 13 | - 14 | - C:\arm-2008q1\bin 15 | 16 | Download DS203 source and extract 17 | - 18 | - click the green [Clone or download] button on github, then [Download zip] 19 | - Extract the dso203-master.zip somewhere 20 | 21 | Open Command Prompt Window 22 | - 23 | - in Command Prompt CD into dso203-master directory with all the source files from above step 24 | 25 | Test the compiler 26 | - 27 | - type: arm-none-eabi-gcc.exe -v 28 | - output: 29 | - Using built-in specs. 30 | - Target: arm-none-eabi 31 | - Configured with: /scratch/sandra/lite/src/gcc-4.2/configure --build=i686-pc-linux-gnu --host=i686-mingw32 --target=arm-none-eabi --enable-threads --disable-libmudflap --disable-libssp --disable-libgomp --disable-libstdcxx-pch --with-gnu-as --with-gnu-ld --enable-languages=c,c++ - 32 | - -disable-shared --with-newlib --with-pkgversion=Sourcery G++ Lite 2008q1-126 --with-bugurl=https://support.codesourcery.com/GNUToolchain/ --disable-nls --prefix=/opt/codesourcery --with-headers=yes --with-sysroot=/opt/codesourcery/arm-none-eabi --with-build-sysroot=/scratch/sandr 33 | - a/lite/eabi/install/host-i686-mingw32/arm-none-eabi --with-libiconv-prefix=/scratch/sandra/lite/eabi/obj/host-libs-2008q1-126-arm-none-eabi-i686-mingw32/usr --enable-poison-system-directories --with-build-time-tools=/scratch/sandra/lite/eabi/obj/tools-i686-pc-linux-gnu-2008q1-126 34 | - -arm-none-eabi-i686-mingw32/arm-none-eabi/bin --with-build-time-tools=/scratch/sandra/lite/eabi/obj/tools-i686-pc-linux-gnu-2008q1-126-arm-none-eabi-i686-mingw32/arm-none-eabi/bin 35 | - Thread model: single 36 | - gcc version 4.2.3 (Sourcery G++ Lite 2008q1-126) 37 | 38 | Lets build the binary 39 | - 40 | - type: cs-make 41 | - output: 42 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o Calibrat.o Calibrat.c 43 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o Draw.o Draw.c 44 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o Files.o Files.c 45 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o Function.o Function.c 46 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o Interrupt.o Interrupt.c 47 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o Main.o Main.c 48 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o Menu.o Menu.c 49 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o Process.o Process.c 50 | - arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c -o BIOS.o BIOS.S 51 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o startup.o startup.c 52 | - arm-none-eabi-gcc -Wall -O2 -I. -Iinc -Werror -mcpu=cortex-m3 -mthumb -fno-common -fzero-initialized-in-bss -msoft-float -MD -I FWLib/inc -c -o stm32f10x_nvic.o stm32f10x_nvic.c 53 | - arm-none-eabi-as -o cortexm3_macro.o cortexm3_macro.s 54 | - arm-none-eabi-gcc -o app1.elf Calibrat.o Draw.o Files.o Function.o Interrupt.o Main.o Menu.o Process.o BIOS.o startup.o stm32f10x_nvic.o cortexm3_macro.o -mcpu=cortex-m3 -lc -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float -nostartfiles -Wl,-Map,app1.map -T app1.lds 55 | - arm-none-eabi-objcopy -O ihex app1.elf app1.hex 56 | - rm app1.elf 57 | 58 | You should find the compiled firmware file app1.hex (423,697 bytes) 59 | - 60 | - Put your DS203 into DFU mode (press and hold >|| button and power on) and copy the app1.hex to drive. 61 | 62 | Optional for hw2.81+ ONLY 63 | - 64 | -To get full speed oversampling, copy FPGA_281.ADR then FPGA_281.BIN in DFU mode to the device. 65 | 66 | Credits and contributors: 67 | ====================== 68 | - jakub.jelinek 69 | - Wildcat 70 | - Seeed-Studio 71 | - Marco Sinatti (marcosin) 72 | - Gabriel Valky (gabonator1) 73 | - pmoss69 74 | - JackTheVendicator 75 | - bobtidey 76 | - JPA 77 | - Jerson 78 | - original authors minidso 79 | -------------------------------------------------------------------------------- /User Guide V5.6-6.5.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/User Guide V5.6-6.5.pdf -------------------------------------------------------------------------------- /W1.1 FPGA/281_FPGA.BIN: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/W1.1 FPGA/281_FPGA.BIN -------------------------------------------------------------------------------- /W1.1 FPGA/AddrCtrl.v: -------------------------------------------------------------------------------- 1 | /********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ******************** 2 | Pre-sampling FIFO address counter and control module 3 | Version : FPGA CFG Ver 2.x Author : bure 4 | *******************************************************************************/ 5 | module AddrCtrl (Counter, OS_Size, FreeRun, ClrW, Wclk, Start, nRclk, RE, H_L, PerCnt, // Depth, PerCnt, Delay, 6 | Ready, Sampled, Full, Empty, Wptr, Rptr); 7 | 8 | input [15:0]Counter;// Oversampling mode OS sample counter 9 | input [15:0]OS_Size;// Oversampling mode OS factor 10 | input FreeRun; // Flag for non triggered synchronized free running AUTO timebase mode 11 | input ClrW; // Wr addr cnt rst -> Active high 12 | input Wclk; // Wr clock -> rising edge 13 | input Start; // Sync start -> active high 14 | input nRclk; // Rd clock -> falling edge 15 | input RE; // Rd cnt enable -> active high 16 | input H_L; // Data output select -> 1/0: [17:16]/[15: 0]Dout->[15:0]DB 17 | input [15:0]PerCnt; // Pre-sampling counter 18 | 19 | output Sampled; // Pre-sampling finish -> active high 20 | output Ready; // Sampling start -> active high 21 | output Full; // FIFO RAM is full -> active high 22 | output Empty; // FIFO RAM is empty -> active high 23 | output [11:0]Wptr; // written address pointer 24 | output [11:0]Rptr; // Read address pointer 25 | 26 | reg Full; 27 | reg Ready; 28 | reg Loaded; // marked the Start address loaded ok 29 | reg [11:0]Wptr; 30 | reg [11:0]Rptr; 31 | reg [12:0]Pcnt; 32 | reg [11:0]Bptr; 33 | reg [1:0]DelayCnt; 34 | reg Sampled; 35 | reg Empty; 36 | 37 | always@ ( posedge Wclk or posedge ClrW ) begin 38 | if ( ClrW ) begin 39 | Full <= 0; 40 | Pcnt <= 0; 41 | Sampled <= 0; 42 | DelayCnt <= 2'b00; 43 | Ready <= 0; 44 | end else begin 45 | 46 | if ((Empty)&&(!Start)&&(FreeRun)) begin 47 | Sampled <= 0; 48 | Full <= 0; 49 | Pcnt <= 0; 50 | Wptr <= 0; 51 | end 52 | 53 | if ((Start)&&(DelayCnt<3))begin 54 | if(Counter==0)DelayCnt <= DelayCnt+1; 55 | end 56 | 57 | if ( Pcnt >= PerCnt ) Sampled <= 1; 58 | 59 | if (!Full) begin 60 | if(OS_Size)begin 61 | if(Counter<2)Wptr <= Wptr + 1; 62 | end else Wptr <= Wptr + 1; 63 | end 64 | 65 | if(OS_Size)begin 66 | if(Pcnt>=2047)begin 67 | if ((FreeRun==0)||(Start==1)) Full <= Ready; else Full <= 1; 68 | end else if(Counter>=OS_Size)Pcnt <= Pcnt +1; 69 | end else begin 70 | if ( Pcnt >= 4095 )begin 71 | if ((FreeRun==0)||(Start==1)) Full <= Ready; else Full <= 1; 72 | end else Pcnt <= Pcnt +1; 73 | end 74 | 75 | if( (!Start )&&(FreeRun==0)&&(Pcnt >= PerCnt) ) Pcnt <= PerCnt; 76 | 77 | if ( DelayCnt == 1 ) begin 78 | if(Counter==0)begin 79 | Ready <= 1; 80 | Bptr <= Wptr; 81 | Pcnt <= PerCnt; 82 | end 83 | end 84 | 85 | end 86 | end 87 | 88 | always @ (Rptr or Wptr) if ( Rptr == Wptr ) Empty <= 1; else Empty <=0; //read/write "splice" 89 | 90 | always @( posedge nRclk or posedge ClrW ) begin 91 | if ( ClrW ) begin 92 | Loaded <= 0; 93 | Rptr <= 0; 94 | end else begin 95 | if ( ( H_L ) && RE && (~Loaded) && (Start) )begin 96 | Loaded <= 1; 97 | if(OS_Size)Rptr<=Bptr-(PerCnt*2); 98 | else Rptr<=Bptr-PerCnt; 99 | end else if ( H_L && RE ) Rptr <= Rptr + 1; 100 | end 101 | end 102 | 103 | endmodule 104 | 105 | 106 | 107 | -------------------------------------------------------------------------------- /W1.1 FPGA/DP_RAM.v: -------------------------------------------------------------------------------- 1 | /********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ******************** 2 | 4096 * 18Bits dual-port SRAM module 3 | Version : FPGA CFG Ver 2.x Author : bure 4 | *******************************************************************************/ 5 | 6 | module DP_RAM ( OS_Size, Din, Wclk, nRclk, Waddr, Raddr, Dout, Counter, A, B, CD ); 7 | 8 | input [15:0]OS_Size; // Oversampling factor control 9 | input Wclk; // Wr clock -> rising edge 10 | input nRclk; // Rd clock -> falling edge 11 | input [11:0]Waddr; // written address 12 | input [11:0]Raddr; // read address 13 | input [17:0]Din; // input data 14 | output [17:0]Dout; // output data 15 | output [15:0]Counter; 16 | output [7:0]A; // Output buffered input channel data to triggering (signal) section 17 | output [7:0]B; 18 | output [1:0]CD; 19 | reg [15:0] Counter; // Oversampling mode sample counter 20 | reg [7:0] ACC_A[1:0]; // Data accumulator/transfer 21 | reg [7:0] ACC_B[1:0]; // Data accumulator/transfer 22 | reg [17:0] Dout; // Data out/high level output 23 | reg [17:0] Mem_data [4095:0]; 24 | reg [17:0]TrigBuf[3:0] /* synthesis syn_noprune=1 */; // Trig buffer, holds 4 last ADC values 25 | reg [1:0]TrigBufAddr; // 2 bit Trig buffer address, holds index to 4 TrigBuf subscripts 26 | 27 | reg [1:0] Multi; // Holds either chC/D or Oversampling index flag 28 | reg [7:0]A; 29 | reg [7:0]B; 30 | reg [1:0]CD; 31 | 32 | always @( posedge Wclk ) begin 33 | TrigBuf[TrigBufAddr]<=Din; //load latest data from ADC into 4 sample buffer 34 | TrigBufAddr <= TrigBufAddr+1; 35 | A<=TrigBuf[TrigBufAddr-2][ 7:0]; //Used for both triggering and data transfer 36 | B<=TrigBuf[TrigBufAddr-2][15:8]; 37 | CD<=TrigBuf[TrigBufAddr-2][17:16]; 38 | 39 | if(Counter<2)begin //in OS mode, writes 0-1 data sequence, kept at 0 in non OS mode 40 | if(OS_Size)begin //OS_Size>0 denotes oversampling mode on 41 | Multi<= 2'b01; //Reset Multi synch flag for OS lo/hi data (active low) 42 | end else Multi<=CD; //if in non OS mode, use to carry ch C/D data 43 | Mem_data[Waddr]<= {Multi,ACC_B[Counter],ACC_A[Counter]}; //load low, high data sequentially 44 | end 45 | 46 | if(OS_Size)begin 47 | if(Counter>=OS_Size)begin //Load OS data 48 | Counter<=0; //Reset 49 | Multi<=2'b00; //Synch flag for program (low active) 50 | end else Counter<=Counter + 1; //Advance counter in OS mode 51 | end else begin 52 | Counter<=0; //Keep at 0 for non OS modes 53 | end 54 | 55 | if(Counter==0)begin //reset to first acquired samples 56 | ACC_A[0]<=A; //Also used for transfer in non OS modes 57 | ACC_B[0]<=B; 58 | end else begin 59 | if(Counter==1)begin 60 | if(A>ACC_A[0])ACC_A[1]<=A; //load highest of 2 first samples in high ACC as reset 61 | else ACC_A[1]<=ACC_A[0]; 62 | if(B>ACC_B[0])ACC_B[1]<=B; 63 | else ACC_B[1]<=ACC_B[0]; 64 | end else begin //Update accumulators 65 | if(A>ACC_A[1])ACC_A[1]<=A; 66 | if(B>ACC_B[1])ACC_B[1]<=B; 67 | end 68 | if(A Active high 10 | input nRD; // Databus read enable -> Active low 11 | input SCK; // Serial input clock -> rising edge 12 | input SDA; // Serial input data 13 | input [17:0]Dout; // Output data 14 | input Start; // Sync start -> active high 15 | input Ready; // Sampling start -> active high 16 | input Full; // FIFO RAM is full -> active high 17 | input Empty; // FIFO RAM is empty -> active high 18 | input H_L; // 0/1 = Status/[15:0]Din -> [15:0]DB 19 | input C_D; // 1 = [15:0]Data -> [15:0]DB 20 | 21 | output [15:0]PerCnt; // Per-sampling counter 22 | output nPD; // ADC power down -> Active low 23 | output [ 7:0]Trigg_Mode; // Trigger Mode 24 | output [ 7:0]Vthreshold; // Trigger voltage threshold 25 | output [ 31:0]XTthreshold; // Trigger time threshold 26 | output [ 7:0]CtrlReg; // bit0=nPD, bit1=Mode, 27 | inout [15:0]DB; // Data bus to MCU 28 | output FreeRun; 29 | output [15:0]OS_Size; 30 | 31 | reg [ 7:0]Trigg_Mode; // Trigger Mode 32 | reg [ 7:0]Vthreshold; // Trigger voltage threshold 33 | reg [ 31:0]XTthreshold; // Trigger time threshold 34 | reg [ 7:0]CtrlReg; 35 | reg [ 7:0]RegAddr; 36 | reg [ 7:0]DataBuff; 37 | wire [15:0]DB_Mux ; 38 | reg [ 7:0]Select; 39 | wire [15:0]CD_Mux ; 40 | reg [15:0]PerCnt; 41 | reg [15:0]Data/* synthesis syn_preserve=1 */; 42 | reg FreeRun; 43 | reg [15:0]OS_Size; 44 | 45 | assign nPD = CtrlReg[0]; 46 | assign CD_Mux = C_D ? Data[15:0] : { 10'h000, Start, Empty, Full, Ready, Dout[17:16] }; //Program uses Ready (2) as start flag 47 | assign DB_Mux = H_L ? Dout[15:0] : CD_Mux; 48 | assign DB = ( CE && !nRD ) ? DB_Mux : 16'hzzzz ; 49 | 50 | always @(posedge SCK) begin 51 | DataBuff = { DataBuff[6:0], SDA }; 52 | end 53 | 54 | always @( posedge SDA ) begin 55 | if ( !SCK ) begin 56 | if ( H_L ) begin 57 | RegAddr = DataBuff; 58 | case(Select) 59 | 8'h00: Data<={8'h57,8'h31}; //For FPGA version ID: Ascii chars "W1" identifies revised fpga 60 | 8'h01: Data<= 16'h0101; //Sub-version, identifies updates 61 | default: Data<=0; 62 | endcase 63 | 64 | end else begin 65 | case( RegAddr ) 66 | 8'h00: begin 67 | Trigg_Mode = DataBuff; 68 | PerCnt = 150; 69 | end 70 | 8'h01: Vthreshold[ 7:0] = DataBuff; 71 | 8'h02: XTthreshold[ 7:0] = DataBuff; 72 | 8'h03: XTthreshold[15:8] = DataBuff; 73 | 8'h04: CtrlReg [ 7:0] = DataBuff; 74 | 8'h05: Select [ 7:0] = DataBuff; 75 | 76 | 8'h08: PerCnt [ 7:0] = DataBuff; 77 | 8'h09: PerCnt [15:8] = DataBuff; 78 | 79 | 8'h0E: FreeRun = DataBuff[0]; 80 | 8'h0F: OS_Size [ 7:0] = DataBuff; 81 | 8'h10: OS_Size [15:8] = DataBuff; 82 | 8'h11: XTthreshold[23:16] = DataBuff; 83 | 8'h12: XTthreshold[31:24] = DataBuff; 84 | endcase 85 | end //if H_L, else 86 | end //if (!SCK) 87 | end //always @(posedge SDA) 88 | 89 | endmodule -------------------------------------------------------------------------------- /W1.1 FPGA/Pins.pcf: -------------------------------------------------------------------------------- 1 | set_io CE P1 2 | set_io nRD P10 3 | set_io DB\[2\] K12 4 | set_io DB\[1\] P2 5 | set_io DB\[0\] P3 6 | set_io DB\[15\] P4 7 | set_io DB\[14\] P5 8 | set_io DB\[13\] P7 9 | set_io DB\[11\] N14 10 | set_io DB\[12\] P14 11 | set_io DB\[10\] M12 12 | set_io DB\[9\] L12 13 | set_io Din\[17\] M3 14 | set_io Din\[16\] K3 15 | set_io DB\[8\] L14 16 | set_io DB\[7\] K14 17 | set_io DB\[6\] H12 18 | set_io DB\[5\] G12 19 | set_io DB\[3\] J12 20 | set_io DB\[4\] G14 21 | set_io MCI P8 22 | set_io ClrW E14 23 | set_io H_L E12 24 | set_io C_D D14 25 | set_io SDA C14 26 | set_io SCK D12 27 | set_io nPD N1 28 | set_io CKB L1 29 | set_io Din\[15\] J1 30 | set_io Din\[14\] H1 31 | set_io Din\[13\] G1 32 | set_io Din\[12\] E1 33 | set_io Din\[11\] D1 34 | set_io Din\[10\] C1 35 | set_io Din\[9\] B1 36 | set_io Din\[8\] A1 37 | set_io Din\[3\] D7 38 | set_io Din\[4\] A6 39 | set_io Din\[6\] A4 40 | set_io Din\[7\] A3 41 | set_io Din\[5\] A5 42 | set_io CKA A2 43 | set_io Din\[1\] A11 44 | set_io Din\[0\] A10 45 | set_io Din\[2\] A12 -------------------------------------------------------------------------------- /W1.1 FPGA/README.TXT: -------------------------------------------------------------------------------- 1 | FPGA version W1.1: 2 | Revised FPGA for HARDWARE VERSION 2.81 and later devices ONLY. 3 | >NOT compatible with previous HW versions 4 | 5 | Compatible with all SYS and program versions. 6 | Instal by first copying the FPGA_281.ADR file to DFU virtual disk. 7 | When volume reappears, copy 281_FPGA.BIN to DFU virtual disk. 8 | 9 | Based on an earlier published version (V2.50) 10 | 11 | 12 | CHANGELOG TO VERSION FPGA W1.1: 13 | 14 | -Added oversampling mode support, access by sending a >0 OS_Size to 15 | Set_ 0x0F and 0x10 addresses as lo/hi word bytes. Compatible with 16 | previous programs with OS_Size=0. 17 | 18 | -Moved triggering buffer to the RAM module and included data transfer 19 | to go through buffer as well. 20 | 21 | -Increased time trigger variable from 16 to 32 bits to work properly with 22 | oversampling mode. 2 most significant added bytes transfered with Set_ 0x11 23 | and 0x12. Value sent needs to be multiplied by OS_Size+1. 24 | 25 | -Removed unused set_ sampling depth and delay to improve timing performance. 26 | Any calls made to these will simply be disregarded. To my knowledge no 27 | program uses these. 28 | 29 | 30 | CHANGELOG TO VERSION FPGA W1: 31 | -Added triggering data buffer so that calculations can be made from a 32 | stable source rather than on the fly which requires critical timing, 33 | possibly resulting in read/write collisions and corruption of triggering 34 | data at the fastest timebases. 35 | 36 | -Extended time triggering accumulators from 12 bits to 32 bits, allows 37 | detection of much longer time intervals for proper triggering functions 38 | under these conditions. 39 | 40 | -Added freerun mode for more coherent waveform displays while untriggered 41 | in AUTO mode at the faster timebases. 42 | 43 | -Eliminated unused meter data accumulators. To my knowledge no program 44 | uses these, but rather performs the calculations externally. 45 | 46 | -Added ID string access so programs can indentify new version. -------------------------------------------------------------------------------- /W1.1 FPGA/Signal.v: -------------------------------------------------------------------------------- 1 | /********************* (C) COPYRIGHT 2011 e-Design Co.,Ltd. ******************** 2 | Sync signal select and control module 3 | Version : FPGA CFG Ver 2.x Author : bure 4 | *******************************************************************************/ 5 | module Signal( Reset, Mclk, Trigg_Mode, Vthreshold, XTthreshold, A, B, CD, 6 | Sampled, Start); 7 | 8 | input Reset; // Trigger status rst -> Active high 9 | input Mclk; // main clock 10 | input [ 7:0]Trigg_Mode; // Trigger Mode 11 | input [ 7:0]Vthreshold; // Trigger voltage threshold 12 | input [31:0]XTthreshold; // Trigger time threshold 13 | input [7:0]A; // Buffered inputs 14 | input [7:0]B; 15 | input [1:0]CD; 16 | input Sampled; // Signals end of pre-trigger sampling 17 | 18 | output Start; // Sync start -> Active high 19 | reg Start; 20 | 21 | wire [ 8:0]Delta_V1; 22 | wire [ 8:0]Delta_V2; 23 | wire [ 8:0]Delta_V3; 24 | wire [ 8:0]Delta_V4; 25 | 26 | reg A_Flag; 27 | reg A_Dt_L; 28 | reg A_Dt_H; 29 | reg A_Ut_L; 30 | reg A_Ut_H; 31 | reg [31:0]A_Cnt; //runs continuously while untriggered, using 32 bit reg instead of 12 bit to extend range 32 | 33 | reg B_Flag; 34 | reg B_Dt_L; 35 | reg B_Dt_H; 36 | reg B_Ut_L; 37 | reg B_Ut_H; 38 | reg [31:0]B_Cnt; 39 | 40 | reg C_Flag; 41 | reg C_Dt_L; 42 | reg C_Dt_H; 43 | reg C_Ut_L; 44 | reg C_Ut_H; 45 | reg [31:0]C_Cnt; 46 | 47 | reg D_Flag; 48 | reg D_Dt_L; 49 | reg D_Dt_H; 50 | reg D_Ut_L; 51 | reg D_Ut_H; 52 | reg [31:0]D_Cnt; 53 | 54 | reg A_Hi; 55 | reg A_Lo; 56 | reg B_Hi; 57 | reg B_Lo; 58 | reg A_Rise; 59 | reg A_Fall; 60 | reg B_Rise; 61 | reg B_Fall; 62 | 63 | assign Delta_V1[8:0] = (Vthreshold[7:0] + 12); 64 | assign Delta_V2[8:0] = (Vthreshold[7:0] - 12); 65 | assign Delta_V3[8:0] = (Vthreshold[7:0] + 1); 66 | assign Delta_V4[8:0] = (Vthreshold[7:0] - 1); 67 | 68 | always @( posedge Mclk or posedge Reset ) begin 69 | if ( Reset ) begin 70 | Start <= 0; 71 | A_Dt_L <= 0; 72 | A_Dt_H <= 0; 73 | A_Ut_L <= 0; 74 | A_Ut_H <= 0; 75 | B_Dt_L <= 0; 76 | B_Dt_H <= 0; 77 | B_Ut_L <= 0; 78 | B_Ut_H <= 0; 79 | C_Dt_L <= 0; 80 | C_Dt_H <= 0; 81 | C_Ut_L <= 0; 82 | C_Ut_H <= 0; 83 | D_Dt_L <= 0; 84 | D_Dt_H <= 0; 85 | D_Ut_L <= 0; 86 | D_Ut_H <= 0; 87 | A_Hi <= 0; 88 | A_Lo <= 0; 89 | A_Rise <= 0; 90 | A_Fall <= 0; 91 | B_Hi <= 0; 92 | B_Lo <= 0; 93 | B_Rise <= 0; 94 | B_Fall <= 0; 95 | end else begin 96 | 97 | // For CH_A Trigger 98 | if ( A > Delta_V3 )begin 99 | A_Hi <= Sampled; 100 | end 101 | if ( A < Delta_V4 )begin 102 | A_Lo <= Sampled; 103 | end 104 | if ( A > Delta_V1 )begin 105 | A_Rise <= Sampled; 106 | end 107 | if ( A < Delta_V2 )begin 108 | A_Fall <= Sampled; 109 | end 110 | 111 | if (( A > Delta_V3 )&&(~A_Flag )) begin 112 | if ( A_Cnt < XTthreshold) A_Dt_L <= Sampled; 113 | else A_Ut_L <= Sampled; 114 | A_Flag <= 1; 115 | A_Cnt <= 0; 116 | end else 117 | if (( A < Delta_V4 )&&( A_Flag )) begin 118 | if ( A_Cnt < XTthreshold ) A_Dt_H <= Sampled; 119 | else A_Ut_H <= Sampled; 120 | A_Flag <= 0; 121 | A_Cnt <= 0; 122 | end else A_Cnt <= A_Cnt + 1; 123 | 124 | 125 | // For CH_B Trigger 126 | if ( B > Delta_V3 )begin 127 | B_Hi <= Sampled; 128 | end 129 | if ( B < Delta_V4 )begin 130 | B_Lo <= Sampled; 131 | end 132 | if ( B > Delta_V1 )begin 133 | B_Rise <= Sampled; 134 | end 135 | if ( B < Delta_V2 )begin 136 | B_Fall <= Sampled; 137 | end 138 | 139 | if (( B > Delta_V3 )&&(~B_Flag )) begin 140 | if ( B_Cnt < XTthreshold ) B_Dt_L <= Sampled; 141 | else B_Ut_L <= Sampled; 142 | B_Flag <= 1; 143 | B_Cnt <= 0; 144 | end else 145 | if (( B < Delta_V4 )&&( B_Flag )) begin 146 | if ( B_Cnt < XTthreshold ) B_Dt_H <= Sampled; 147 | else B_Ut_H <= Sampled; 148 | B_Flag <= 0; 149 | B_Cnt <= 0; 150 | end else B_Cnt <= B_Cnt + 1; 151 | 152 | 153 | // For CH_C Trigger 154 | if ( CD[0] != C_Flag ) begin 155 | if ( C_Cnt < XTthreshold ) begin 156 | if ( CD[0] ) C_Dt_L <= Sampled; 157 | else C_Dt_H <= Sampled; 158 | end else begin 159 | if ( CD[0] ) C_Ut_L <= Sampled; 160 | else C_Ut_H <= Sampled; 161 | end 162 | C_Cnt <= 0; 163 | end else C_Cnt <= C_Cnt + 1; 164 | C_Flag <= CD[0]; 165 | 166 | // For CH_D Trigger 167 | if ( CD[1] != D_Flag ) begin 168 | if ( D_Cnt < XTthreshold ) begin 169 | if ( CD[1] ) D_Dt_L <= Sampled; 170 | else D_Dt_H <= Sampled; 171 | end else begin 172 | if ( CD[1] ) D_Ut_L <= Sampled; 173 | else D_Ut_H <= Sampled; 174 | end 175 | D_Cnt <= 0; 176 | end else D_Cnt <= D_Cnt + 1; 177 | D_Flag <= CD[1]; 178 | 179 | 180 | case( Trigg_Mode ) 181 | // For CH_A Trigger 182 | 8'h00: if ( A < Vthreshold ) Start <= A_Rise; // Negedge 183 | 8'h01: if ( A > Vthreshold ) Start <= A_Fall; // Posedge 184 | 8'h02: if ( A < Vthreshold ) Start <= A_Hi; // L Level 185 | 8'h03: if ( A > Vthreshold ) Start <= A_Lo; // H Level 186 | 8'h04: Start <= A_Dt_L; // Pulse 0 < ConfigDt 187 | 8'h05: Start <= A_Ut_L; // Pulse 0 > ConfigDt 188 | 8'h06: Start <= A_Dt_H; // Pulse 1 < ConfigDt 189 | 8'h07: Start <= A_Ut_H; // Pulse 1 > ConfigDt 190 | 191 | // For CH_B Trigger 192 | 8'h08: if ( B < Vthreshold ) Start <= B_Rise; // Negedge 193 | 8'h09: if ( B > Vthreshold ) Start <= B_Fall; // Posedge 194 | 8'h0A: if ( B < Vthreshold ) Start <= B_Hi; // L Level 195 | 8'h0B: if ( B > Vthreshold ) Start <= B_Lo; // H Level 196 | 8'h0C: Start <= B_Dt_L; // Pulse 0 < ConfigDt 197 | 8'h0D: Start <= B_Ut_L; // Pulse 0 > ConfigDt 198 | 8'h0E: Start <= B_Dt_H; // Pulse 1 < ConfigDt 199 | 8'h0F: Start <= B_Ut_H; // Pulse 1 > ConfigDt 200 | 201 | // For CH_C Trigger 202 | 8'h10: if (( ~CD[0] )&&( C_Flag )) Start <= Sampled; // Negedge 203 | 8'h11: if (( CD[0] )&&( ~C_Flag )) Start <= Sampled; // Posedge 204 | 8'h12: if (( ~CD[0] )&&( C_Flag )) Start <= Sampled; // L Level 205 | 8'h13: if (( CD[0] )&&( ~C_Flag )) Start <= Sampled; // H Level 206 | 8'h14: Start <= C_Dt_L; // Pulse 0 < ConfigDt 207 | 8'h15: Start <= C_Ut_L; // Pulse 0 > ConfigDt 208 | 8'h16: Start <= C_Dt_H; // Pulse 1 < ConfigDt 209 | 8'h17: Start <= C_Ut_H; // Pulse 1 > ConfigDt 210 | // For CH_D Trigger 211 | 8'h18: if (( ~CD[1] )&&( D_Flag )) Start <= Sampled; // Negedge 212 | 8'h19: if (( CD[1] )&&( ~D_Flag )) Start <= Sampled; // Posedge 213 | 8'h1A: if (( ~CD[1] )&&( D_Flag )) Start <= Sampled; // L Level 214 | 8'h1B: if (( CD[1] )&&( ~D_Flag )) Start <= Sampled; // H Level 215 | 8'h1C: Start <= D_Dt_L; // Pulse 0 < ConfigDt 216 | 8'h1D: Start <= D_Ut_L; // Pulse 0 > ConfigDt 217 | 8'h1E: Start <= D_Dt_H; // Pulse 1 < ConfigDt 218 | 8'h1F: Start <= D_Ut_H; // Pulse 1 > ConfigDt 219 | 8'h20: Start <= 1; //Uncondition trig mode 220 | 221 | endcase 222 | end 223 | end 224 | endmodule -------------------------------------------------------------------------------- /W1.1 FPGA/Time.sdc: -------------------------------------------------------------------------------- 1 | #Clock 2 | create_clock [get_ports {MCI} ] -name {MCI} -period 13.888 3 | create_clock [get_ports {nRD} ] -name {nRD} -period 100 4 | create_clock [get_ports {SCK} ] -name {SCK} -period 100 5 | create_clock [get_ports {SDA} ] -name {SDA} -period 100 6 | create_clock [get_ports {ClrW}] -name {ClrW} -period 100 7 | #Generated Clock 8 | #Input Delay 9 | #Output Delay 10 | #Max-delay 11 | #False Path 12 | #Multi-cycle 13 | -------------------------------------------------------------------------------- /app1.lds: -------------------------------------------------------------------------------- 1 | /* Define memory regions. */ 2 | MEMORY 3 | 4 | { 5 | rom (rx) : ORIGIN = 0x0800C000, LENGTH = 64K 6 | spare (rx) : ORIGIN = 0x0802c000, LENGTH = 80K 7 | extra (rx) : ORIGIN = 0x08047000, LENGTH = 65K 8 | /* total RAM 64kb, starts from 0x20000000; 9 | minus SYS memory 8kb in the beginning 10 | (actually less but original APP reserves 8kb); 11 | minus possible AlterBIOS memory 5kb in the end 12 | (original app reserves everything from 0x2000abe0); 13 | total = 51kb */ 14 | ram (rwx) : ORIGIN = 0x20002000, LENGTH = 51K 15 | } 16 | 17 | INCLUDE main.lds 18 | -------------------------------------------------------------------------------- /app2.lds: -------------------------------------------------------------------------------- 1 | /* Define memory regions. */ 2 | MEMORY 3 | { 4 | rom (rx) : ORIGIN = 0x08014000, LENGTH = 96K 5 | ram (rwx) : ORIGIN = 0x20003000, LENGTH = 48K 6 | } 7 | 8 | INCLUDE main.lds 9 | -------------------------------------------------------------------------------- /app3.lds: -------------------------------------------------------------------------------- 1 | /* Define memory regions. */ 2 | MEMORY 3 | { 4 | rom (rx) : ORIGIN = 0x0801C000, LENGTH = 64K 5 | ram (rwx) : ORIGIN = 0x20003000, LENGTH = 48K 6 | } 7 | 8 | INCLUDE main.lds 9 | -------------------------------------------------------------------------------- /app4.lds: -------------------------------------------------------------------------------- 1 | /* Define memory regions. */ 2 | MEMORY 3 | { 4 | rom (rx) : ORIGIN = 0x08024000, LENGTH = 32K 5 | ram (rwx) : ORIGIN = 0x20003000, LENGTH = 48K 6 | } 7 | 8 | INCLUDE main.lds 9 | -------------------------------------------------------------------------------- /cortexm3_macro.S: -------------------------------------------------------------------------------- 1 | /* ******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** */ 2 | /* * File Name : cortexm3_macro.s */ 3 | /* * Author : MCD Application Team */ 4 | /* * Version : V2.2.1 */ 5 | /* * Date : 09/22/2008 */ 6 | /* * Description : Instruction wrappers for special Cortex-M3 instructions. */ 7 | /* * to be used with EWARM4.x toolchain. */ 8 | /* ******************************************************************************* */ 9 | /* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS */ 10 | /* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. */ 11 | /* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, */ 12 | /* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE */ 13 | /* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING */ 14 | /* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. */ 15 | /* ******************************************************************************* */ 16 | 17 | .syntax unified 18 | .thumb 19 | .text 20 | 21 | /* Exported functions */ 22 | .globl __WFI 23 | .globl __WFE 24 | .globl __SEV 25 | .globl __ISB 26 | .globl __DSB 27 | .globl __DMB 28 | .globl __SVC 29 | .globl __MRS_CONTROL 30 | .globl __MSR_CONTROL 31 | .globl __MRS_PSP 32 | .globl __MSR_PSP 33 | .globl __MRS_MSP 34 | .globl __MSR_MSP 35 | .globl __RESETPRIMASK 36 | .globl __SETPRIMASK 37 | .globl __READ_PRIMASK 38 | .globl __RESETFAULTMASK 39 | .globl __SETFAULTMASK 40 | .globl __READ_FAULTMASK 41 | .globl __BASEPRICONFIG 42 | .globl __GetBASEPRI 43 | .globl __REV_HalfWord 44 | .globl __REV_Word 45 | 46 | /* ******************************************************************************* */ 47 | /* Function Name : __WFI */ 48 | /* Description : Assembler function for the WFI instruction. */ 49 | /* Input : None */ 50 | /* Return : None */ 51 | /* ******************************************************************************* */ 52 | __WFI: 53 | 54 | WFI 55 | BX r14 56 | 57 | /* ******************************************************************************* */ 58 | /* Function Name : __WFE */ 59 | /* Description : Assembler function for the WFE instruction. */ 60 | /* Input : None */ 61 | /* Return : None */ 62 | /* ******************************************************************************* */ 63 | __WFE: 64 | 65 | WFE 66 | BX r14 67 | 68 | /* ******************************************************************************* */ 69 | /* Function Name : __SEV */ 70 | /* Description : Assembler function for the SEV instruction. */ 71 | /* Input : None */ 72 | /* Return : None */ 73 | /* ******************************************************************************* */ 74 | __SEV: 75 | 76 | SEV 77 | BX r14 78 | 79 | /* ******************************************************************************* */ 80 | /* Function Name : __ISB */ 81 | /* Description : Assembler function for the ISB instruction. */ 82 | /* Input : None */ 83 | /* Return : None */ 84 | /* ******************************************************************************* */ 85 | __ISB: 86 | 87 | ISB 88 | BX r14 89 | 90 | /* ******************************************************************************* */ 91 | /* Function Name : __DSB */ 92 | /* Description : Assembler function for the DSB instruction. */ 93 | /* Input : None */ 94 | /* Return : None */ 95 | /* ******************************************************************************* */ 96 | __DSB: 97 | 98 | DSB 99 | BX r14 100 | 101 | /* ******************************************************************************* */ 102 | /* Function Name : __DMB */ 103 | /* Description : Assembler function for the DMB instruction. */ 104 | /* Input : None */ 105 | /* Return : None */ 106 | /* ******************************************************************************* */ 107 | __DMB: 108 | 109 | DMB 110 | BX r14 111 | 112 | /* ******************************************************************************* */ 113 | /* Function Name : __SVC */ 114 | /* Description : Assembler function for the SVC instruction. */ 115 | /* Input : None */ 116 | /* Return : None */ 117 | /* ******************************************************************************* */ 118 | __SVC: 119 | 120 | SVC 0x01 121 | BX r14 122 | 123 | /* ******************************************************************************* */ 124 | /* Function Name : __MRS_CONTROL */ 125 | /* Description : Assembler function for the MRS instruction. */ 126 | /* Input : None */ 127 | /* Return : - r0 : Cortex-M3 CONTROL register value. */ 128 | /* ******************************************************************************* */ 129 | __MRS_CONTROL: 130 | 131 | MRS r0, CONTROL 132 | BX r14 133 | 134 | /* ******************************************************************************* */ 135 | /* Function Name : __MSR_CONTROL */ 136 | /* Description : Assembler function for the MSR instruction. */ 137 | /* Input : - r0 : Cortex-M3 CONTROL register new value. */ 138 | /* Return : None */ 139 | /* ******************************************************************************* */ 140 | __MSR_CONTROL: 141 | 142 | MSR CONTROL, r0 143 | ISB 144 | BX r14 145 | 146 | /* ******************************************************************************* */ 147 | /* Function Name : __MRS_PSP */ 148 | /* Description : Assembler function for the MRS instruction. */ 149 | /* Input : None */ 150 | /* Return : - r0 : Process Stack value. */ 151 | /* ******************************************************************************* */ 152 | __MRS_PSP: 153 | 154 | MRS r0, PSP 155 | BX r14 156 | 157 | /* ******************************************************************************* */ 158 | /* Function Name : __MSR_PSP */ 159 | /* Description : Assembler function for the MSR instruction. */ 160 | /* Input : - r0 : Process Stack new value. */ 161 | /* Return : None */ 162 | /* ******************************************************************************* */ 163 | __MSR_PSP: 164 | 165 | MSR PSP, r0 /* set Process Stack value */ 166 | BX r14 167 | 168 | /* ******************************************************************************* */ 169 | /* Function Name : __MRS_MSP */ 170 | /* Description : Assembler function for the MRS instruction. */ 171 | /* Input : None */ 172 | /* Return : - r0 : Main Stack value. */ 173 | /* ******************************************************************************* */ 174 | __MRS_MSP: 175 | 176 | MRS r0, MSP 177 | BX r14 178 | 179 | /* ******************************************************************************* */ 180 | /* Function Name : __MSR_MSP */ 181 | /* Description : Assembler function for the MSR instruction. */ 182 | /* Input : - r0 : Main Stack new value. */ 183 | /* Return : None */ 184 | /* ******************************************************************************* */ 185 | __MSR_MSP: 186 | 187 | MSR MSP, r0 /* set Main Stack value */ 188 | BX r14 189 | 190 | /* ******************************************************************************* */ 191 | /* Function Name : __RESETPRIMASK */ 192 | /* Description : Assembler function to reset the PRIMASK. */ 193 | /* Input : None */ 194 | /* Return : None */ 195 | /* ******************************************************************************* */ 196 | __RESETPRIMASK: 197 | 198 | CPSIE i 199 | BX r14 200 | 201 | /* ******************************************************************************* */ 202 | /* Function Name : __SETPRIMASK */ 203 | /* Description : Assembler function to set the PRIMASK. */ 204 | /* Input : None */ 205 | /* Return : None */ 206 | /* ******************************************************************************* */ 207 | __SETPRIMASK: 208 | 209 | CPSID i 210 | BX r14 211 | 212 | /* ******************************************************************************* */ 213 | /* Function Name : __READ_PRIMASK */ 214 | /* Description : Assembler function to get the PRIMASK value. */ 215 | /* Input : None */ 216 | /* Return : - r0 : PRIMASK register value */ 217 | /* ******************************************************************************* */ 218 | __READ_PRIMASK: 219 | 220 | MRS r0, PRIMASK 221 | BX r14 222 | 223 | /* ******************************************************************************* */ 224 | /* Function Name : __RESETFAULTMASK */ 225 | /* Description : Assembler function to reset the FAULTMASK. */ 226 | /* Input : None */ 227 | /* Return : None */ 228 | /* ******************************************************************************* */ 229 | __RESETFAULTMASK: 230 | 231 | CPSIE f 232 | BX r14 233 | 234 | /* ******************************************************************************* */ 235 | /* Function Name : __SETFAULTMASK */ 236 | /* Description : Assembler function to set the FAULTMASK. */ 237 | /* Input : None */ 238 | /* Return : None */ 239 | /* ******************************************************************************* */ 240 | __SETFAULTMASK: 241 | 242 | CPSID f 243 | BX r14 244 | 245 | /* ******************************************************************************* */ 246 | /* Function Name : __READ_FAULTMASK */ 247 | /* Description : Assembler function to get the FAULTMASK value. */ 248 | /* Input : None */ 249 | /* Return : - r0 : FAULTMASK register value */ 250 | /* ******************************************************************************* */ 251 | __READ_FAULTMASK: 252 | 253 | MRS r0, FAULTMASK 254 | BX r14 255 | 256 | /* ******************************************************************************* */ 257 | /* Function Name : __BASEPRICONFIG */ 258 | /* Description : Assembler function to set the Base Priority. */ 259 | /* Input : - r0 : Base Priority new value */ 260 | /* Return : None */ 261 | /* ******************************************************************************* */ 262 | __BASEPRICONFIG: 263 | 264 | MSR BASEPRI, r0 265 | BX r14 266 | 267 | /* ******************************************************************************* */ 268 | /* Function Name : __GetBASEPRI */ 269 | /* Description : Assembler function to get the Base Priority value. */ 270 | /* Input : None */ 271 | /* Return : - r0 : Base Priority value */ 272 | /* ******************************************************************************* */ 273 | __GetBASEPRI: 274 | 275 | MRS r0, BASEPRI_MAX 276 | BX r14 277 | 278 | /* ******************************************************************************* */ 279 | /* Function Name : __REV_HalfWord */ 280 | /* Description : Reverses the byte order in HalfWord(16-bit) input variable. */ 281 | /* Input : - r0 : specifies the input variable */ 282 | /* Return : - r0 : holds tve variable value after byte reversing. */ 283 | /* ******************************************************************************* */ 284 | __REV_HalfWord: 285 | 286 | REV16 r0, r0 287 | BX r14 288 | 289 | /* ******************************************************************************* */ 290 | /* Function Name : __REV_Word */ 291 | /* Description : Reverses the byte order in Word(32-bit) input variable. */ 292 | /* Input : - r0 : specifies the input variable */ 293 | /* Return : - r0 : holds tve variable value after byte reversing. */ 294 | /* ******************************************************************************* */ 295 | __REV_Word: 296 | 297 | REV r0, r0 298 | BX r14 299 | 300 | .end 301 | 302 | /* ******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE***** */ 303 | -------------------------------------------------------------------------------- /inc/BIOS.h: -------------------------------------------------------------------------------- 1 | /********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** 2 | File Name : BIOS.h 3 | Version : DS203_APP Ver 2.5x Author : bure 4 | *******************************************************************************/ 5 | #ifndef __BIOS_H 6 | #define __BIOS_H 7 | 8 | #include "stm32f10x_lib.h" 9 | 10 | 11 | //============================= Flash space allocation ================================= 12 | 13 | #define BIN_BASE ((u32)(0x0802C000)) // Size < 68KB 14 | #define PRM_BASE BIN_BASE + 68*1024 // Size = 2KB 15 | #define INF_BASE BIN_BASE + 70*1024 // Size < 10KB 16 | #define APP4_BASE ((u32)(0x08024000)) // Size = 32KB 17 | #define APP3_BASE ((u32)(0x0801C000)) // Size = 32KB 18 | #define APP2_BASE ((u32)(0x08014000)) // Size = 32KB 19 | #define APP1_BASE ((u32)(0x0800C000)) // Size = 32KB 20 | #define SYS_BASE ((u32)(0x08004000)) // Size = 32KB 21 | #define DFU_BASE ((u32)(0x08000000)) // Size = 16KB 22 | 23 | //====================== Function Set Object and Value defined ====================== 24 | 25 | #define CH_A_OFFSET 0 // A channel vertical displacement Value = 0~200 26 | #define CH_B_OFFSET 1 // B channel vertical displacement Value = 0~200 27 | #define BACKLIGHT 2 // backlight brightness Value = 0~100 28 | #define BEEP_VOLUME 3 // buzzer volume Value = 0~100 29 | #define BETTERY_DT 4 // battery voltage detector Value = 1: start 30 | #define ADC_MODE 5 // ADC operating mode Value = 1/0 31 | #define FIFO_CLR 6 // FIFO pointer reset Value = 1/0: W_PTR/R_PTR 32 | #define R_PTR 0 // FIFO read address pointer reset 33 | #define W_PTR 1 // FIFO write address pointer is reset 34 | #define T_BASE_PSC 7 // prescaler value Value = 0~65535 35 | #define T_BASE_ARR 8 // frequency Value = 0~65535 36 | #define CH_A_COUPLE 9 // A channel coupling method Value = 1/0: AC/DC 37 | #define DC 0 38 | #define AC 1 39 | #define CH_A_RANGE 10 // A channel input range Value = 0~5 40 | #define CH_B_COUPLE 11 // B channel coupling method Value = 1/0: AC/DC 41 | #define CH_B_RANGE 12 // B channel input range Value = 0~5 42 | #define ANALOG_ARR 13 // analog output divider value Value = 0~65535 43 | #define ANALOG_PTR 14 // analog output pointer Value = 0~65535 44 | #define ANALOG_CNT 15 // synthetic points of a week Value = 0~65535 45 | #define DIGTAL_PSC 16 // pulse output prescaler value Value = 0~65535 46 | #define DIGTAL_ARR 17 // pulse output divider value Value = 0~65535 47 | #define DIGTAL_CCR 18 // pulse output duty cycle value Value = 0~65535 48 | #define KEY_IF_RST 19 // timer interrupt flag reset Value = 0 49 | #define STANDBY 20 // to enter the power-down waiting Value = 0 50 | #define ANALOG_PSC 21 // only implemented in Marcosin's sys version 51 | #define FPGA_RST 31 // FPGA Reset Value = 0 52 | 53 | #define TRIGG_MODE 32+0 // trigger mode Value = Mode 54 | #define V_THRESHOLD 32+1 // voltage trigger threshold Value = 0~200 55 | #define T_THRESHOLD 32+2 // pulse width trigger gate limit Value = 0~65535 56 | #define ADC_CTRL 32+4 // ADC status Value = 1/0 EN/DN 57 | #define A_POSITION 32+5 // the zero position of CH_A Value = 0~200 58 | #define B_POSITION 32+6 // the zero position of CH_B Value = 0~200 59 | #define REG_ADDR 32+7 // the address determines which set of registers in the FPGA, the data read into the MCU 60 | 61 | //==================== Function Set TRIGG_MODE of Value defined ===================== 62 | /* 63 | CH_A Trigger source & kind select => 64 | 0x00: by Negedge; 0x01: by Posedge; 0x02: by low level; 0x03: by high level 65 | 0x04: TL < Delta_T; 0x05: TL > Delta_T; 0x06: TH < Delta_T; 0x07: TH > Delta_T; 66 | 67 | CH_B Trigger source & kind select => 68 | 0x08: by Negedge; 0x09: by Posedge; 0x0A: by low level; 0x0B: by high level 69 | 0x0C: TL < Delta_T; 0x0D: TL > Delta_T; 0x0E: TH < Delta_T; 0x0F: TH > Delta_T; 70 | 71 | CH_C Trigger source & kind select => 72 | 0x10: by Negedge; 0x11: by Posedge; 0x12: by low level; 0x13: by high level 73 | 0x04: TL < Delta_T; 0x05: TL > Delta_T; 0x06: TH < Delta_T; 0x07: TH > Delta_T; 74 | 75 | CH_D Trigger source & kind select => 76 | 0x18: by Negedge; 0x19: by Posedge; 0x1A: by low level; 0x1B: by high level 77 | 0x1C: TL < Delta_T; 0x1D: TL > Delta_T; 0x1E: TH < Delta_T; 0x1F: TH > Delta_T; 78 | 79 | 0x20~0xFF => Unconditional trigger 80 | */ 81 | 82 | #define UNCONDITION 0x20 // unconditional trigger sampling 83 | 84 | //================ Function Set in ADC_CTRL the STANDBY Value defined ================ 85 | 86 | #define DN 0 87 | #define EN 1 88 | 89 | //===================== Function Set ADC_MODE of Value defined ===================== 90 | 91 | #define SEPARATE 0 // ADC sampling mode independently 92 | #define INTERLACE 1 // ADC Alternate Sampling mode 93 | 94 | //========================= Function Get Kind defined ============================ 95 | 96 | #define FIFO_DIGIT 0 // 16bits FIFO digital data 97 | #define FIFO_EMPTY 1 // FIFO empty flag: 1 = empty 98 | #define FIFO_START 2 // FIFO start flag: 1 = start 99 | #define FIFO_FULL 3 // FIFO full flag: 1 = Full 100 | #define KEY_STATUS 4 // Current keys status 101 | #define K_ITEM_D_STATUS 0x0008 // 0 = Key push on 102 | #define K_ITEM_S_STATUS 0x0040 // 0 = Key push on 103 | #define KEY3_STATUS 0x0100 // 0 = Key push on 104 | #define KEY4_STATUS 0x0200 // 0 = Key push on 105 | #define K_INDEX_D_STATUS 0x0400 // 0 = Key push on 106 | #define K_INDEX_I_STATUS 0x0800 // 0 = Key push on 107 | #define K_INDEX_S_STATUS 0x1000 // 0 = Key push on 108 | #define KEY2_STATUS 0x2000 // 0 = Key push on 109 | #define KEY1_STATUS 0x4000 // 0 = Key push on 110 | #define K_ITEM_I_STATUS 0x8000 // 0 = Key push on 111 | #define USB_POWER 5 // USB power status: 1 = Power ON 112 | #define V_BATTERY 6 // Battery voltage (mV) 113 | #define VERTICAL 7 // vertical channel attribute pointer 114 | #define HORIZONTAL 8 // horizontal channel attribute pointer 115 | #define GLOBAL 9 // pointer to the whole property 116 | #define TRIGGER 10 // trigger channel attribute pointer 117 | #define FPGA_OK 11 // FPGA configuration was successful 1 = the FPGA config the ok 118 | #define CHARGE 12 // battery charge status 119 | #define HDWVER 13 // device hardware version number 120 | #define DFUVER 14 // the DFU program module version number 121 | #define SYSVER 15 // the SYS program module version number 122 | #define FPGAVER 16 // version number of the FPGA configuration program 123 | #define DEVICEINFO 18 //DISK=7 (FLASH 2M,OR 8M) 124 | 125 | #define ADC_DATA 32+0 // 0~7:ADC_CH_A 8~15:ADC_CH_B 16~17:CH_C&CH_D 126 | #define PRE_SAMPLING 32+1 // 0~15:Pre-sampling depth 127 | #define ALL_SAMPLING 32+2 // 0~15:Total sampling depth 128 | #define CH_A_MIN_MAX 32+3 // 0~7:VMIN 8~15:VMAX 129 | #define CH_A_V_SUM 32+4 // 0~15:CH_A voltage sum 130 | #define CH_A_V_SSQ 32+5 // 0~15:CH_A voltage sum of squares 131 | #define CH_A_NEDGE 32+6 // 0~15:CH_A number of edge 132 | #define CH_A_FREQ 32+7 // 0~15:CH_A frequence 133 | #define CH_A_PHW_MAX 32+8 // 0~15:CH_A pulse high width MAX 134 | #define CH_A_PHW_MIN 32+9 // 0~15:CH_A pulse high width MIN 135 | #define CH_A_PLW_MAX 32+10 // 0~15:CH_A pulse low width MAX 136 | #define CH_A_PLW_MIN 32+11 // 0~15:CH_A pulse low width MIN 137 | 138 | // ============================================================================= 139 | 140 | typedef struct // hardware properties 141 | { 142 | u16 LCD_X; // horizontal screen display points 143 | u16 LCD_Y; // vertical screen display points 144 | u16 Yp_Max; // maximum vertical gear 145 | u16 Xp_Max; // maximum level stalls 146 | u16 Tg_Num; // trigger the stalls in the maximum 147 | u16 Yv_Max; // maximum vertical displacement 148 | u16 Xt_Max; // maximum horizontal displacement 149 | u16 Co_Max; // maximum coupling mode 150 | u8 Ya_Num; // the number of analog channels 151 | u8 Yd_Num; // the number of digital channels 152 | u8 INSERT; // start using the interpolated stalls 153 | u16 KpA1; // A channel shift compensation factor 154 | u16 KpA2; // A channel displacement compensation coefficient 155 | u16 KpB1; // B-channel displacement compensation coefficient 156 | u16 KpB2; // B channel displacement compensation coefficient 157 | } G_attr ; 158 | 159 | typedef struct // vertical channel properties 160 | { 161 | char STR[8]; // stall identification string 162 | s16 KA1; // A channel displacement error correction factor 1 163 | u16 KA2; // A channel slope error correction factor 164 | s16 KB1; // B-channel displacement error correction factor 1 165 | u16 KB2; // B channel slope error correction factor 166 | u32 SCALE; // vertical channel scale factor 167 | } Y_attr ; 168 | 169 | typedef struct // horizontal channel properties 170 | { 171 | char STR[8]; // stall identification string 172 | s16 PSC; // prescaler coefficient 173 | u16 ARR; // frequency coefficient 174 | u16 CCR; // duty cycle coefficient 175 | u16 KP; // interpolation coefficients 176 | u32 SCALE; // horizontal channel scale factor 177 | } X_attr ; 178 | 179 | typedef struct // chanel trigger properties 180 | { 181 | char STR[8]; // trigger identification string 182 | u8 CHx; // trigger channel number 183 | u8 CMD; // trigger control word 184 | } T_attr ; 185 | 186 | extern Y_attr *Y_Attr; 187 | extern X_attr *X_Attr; 188 | extern G_attr *G_Attr; 189 | extern T_attr *T_Attr; 190 | 191 | //============================================================================== 192 | // System function entrance 193 | //============================================================================== 194 | void __CTR_HP(void); //USB_HP_Interrupt 195 | void __USB_Istr(void); //USB_LP_Interrupt 196 | void __USB_Init(void); 197 | 198 | void __LCD_Initial(void); 199 | void __Clear_Screen(u16 Color); 200 | void __Point_SCR(u16 x0, u16 y0); 201 | void __LCD_SetPixl(u16 Color); 202 | u16 __LCD_GetPixl(void); 203 | u16 __Get_TAB_8x14(u8 Code, u16 Row); 204 | void __LCD_Set_Block(u16 x1, u16 x2, u16 y1, u16 y2); 205 | 206 | void __LCD_Copy(uc16 *pBuffer, u16 NumPixel); // Send a row data to LCD 207 | void __LCD_Fill(u16 *pBuffer,u16 NumPixel); // Fill number of pixel by DMA 208 | void __LCD_DMA_Ready(void); // Wait LCD data DMA ready 209 | 210 | void __Row_Copy(uc16 *S_Buffer,u16 *T_Buffer); // Copy one row base data to buffer 211 | void __Row_DMA_Ready(void); // Wait row base data DMA ready 212 | 213 | u32 __Read_FIFO(void); // Read data from FIFO & Ptr+1 214 | void __Display_Str(u16 x0, u16 y0, u16 Color, u8 Mode, char *s); 215 | 216 | u32 __Input_Lic(u16 x0, u8 y0); //Return: 32Bits Licence 217 | u32 __GetDev_SN(void); // Get 32bits Device Serial Number 218 | 219 | u8 __Ident(u32 Dev_ID, u32 Proj_ID, u32 Lic_No); 220 | 221 | void __Set_Param(u8 RegAddr, u8 Parameter); 222 | void __Set(u8 Object, u32 Value); 223 | u32 __Get(u8 Object); 224 | 225 | void __ExtFlash_PageRD(u8* pBuffer, u32 ReadAddr, u16 NumByteToRead); 226 | void __ExtFlash_PageWR(u8* pBuffer, u32 WriteAddr); 227 | u8 __ReadDiskData(u8* pBuffer, u32 ReadAddr, u16 Lenght); 228 | u8 __ProgDiskPage(u8* pBuffer, u32 ProgAddr); 229 | 230 | u8 __FLASH_Erase(u32 Address); 231 | u8 __FLASH_Prog(u32 Address, u16 Data); 232 | void __FLASH_Unlock(void); 233 | void __FLASH_Lock(void); 234 | 235 | u8 __Chk_SYS(u32 Licence); 236 | u8* __Chk_DFU(void); 237 | u8* __Chk_HDW(void); 238 | 239 | u8 __OpenFileWr(u8* Buffer, char* FileName, u16* Cluster, u32* pDirAddr); 240 | u8 __OpenFileRd(u8* Buffer, char* FileName, u16* Cluster, u32* pDirAddr); 241 | u8 __ReadFileSec(u8* Buffer, u16* Cluster); 242 | u8 __ProgFileSec(u8* Buffer, u16* Cluster); 243 | u8 __CloseFile(u8* Buffer, u32 Lenght, u16* Cluster, u32* pDirAddr); 244 | /**/ 245 | 246 | #endif 247 | /******************************* END OF FILE ********************************/ 248 | -------------------------------------------------------------------------------- /inc/Calibrat.h: -------------------------------------------------------------------------------- 1 | /********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** 2 | File Name : Calibrat.h 3 | Version : DS203_APP Ver 2.3x Author : bure 4 | *******************************************************************************/ 5 | #ifndef __CALIBRAT_H 6 | #define __CALIBRAT_H 7 | 8 | #include "stm32f10x_lib.h" 9 | 10 | #define _100uS 12 // T_BASE = 100uS/Div 11 | #define _2uS 17 // T_BASE = 2uS/Div 12 | 13 | extern s16 PPM_Comp; 14 | extern u8 CalibrateMode; 15 | 16 | void Calibrat(u8 Channel); 17 | 18 | 19 | 20 | #endif 21 | 22 | /******************************* END OF FILE ********************************/ 23 | -------------------------------------------------------------------------------- /inc/Draw.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/inc/Draw.h -------------------------------------------------------------------------------- /inc/File.h: -------------------------------------------------------------------------------- 1 | /********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** 2 | File Name : file.h 3 | Version : DS203_APP Ver 2.5x Author : bure 4 | *******************************************************************************/ 5 | #ifndef __FILE_H 6 | #define __FILE_H 7 | 8 | #include "stm32f10x_lib.h" 9 | 10 | //#define FLASH_WAIT_TIMEOUT 100000 11 | //#define PAGE_0 0 12 | //#define PAGE_1 1 13 | //#define PAGE_2 2 14 | //#define PAGE_3 3 15 | 16 | #define OK 0 // operation is completed 17 | //#define SEC_ERR 1 // sectors read and write errors 18 | //#define FAT_ERR 2 // FAT table to read and write errors 19 | #define OVER 3 // operations overflow 20 | #define NEW 4 // new directory entry 21 | #define EMPT 4 // file does not exist 22 | #define VER_ERR 5 // wrong version 23 | #define SUM_ERR 6 // checksum error 24 | #define RD_ERR 8 // sectors read error 25 | #define WR_ERR 9 // sector write error 26 | #define DISK_ERR 10 // disk error 27 | 28 | #define FLASH_8M 1 29 | #define FLASH_2M 0 30 | #define FLASH_2M_SECTOR_SIZE 512 31 | #define FLASH_8M_SECTOR_SIZE 4096 32 | #define LARGEST_SECTOR_SIZE 4096 33 | #define BUFFER_SIZE 16384 34 | extern u8 flash_mode; 35 | extern u16 SectorSize; 36 | extern u8 FileBuff[1600]; 37 | extern u8 SaveShortBuffXpos; 38 | extern u8 Versions; 39 | extern u16 TempPar[74]; 40 | extern u16 ArbtSampleNumber; 41 | extern u32 UartFileSize; 42 | extern u8 SecBuff[LARGEST_SECTOR_SIZE]; 43 | extern char Label[15][13]; 44 | extern char Ext[4]; 45 | extern u16 DirRange; 46 | extern char SelectedFileName[9]; 47 | extern char ConfigFileName[9]; 48 | extern char LastAccessedConfig[9]; 49 | extern u8 Edited; 50 | extern u8 BufferRestore; 51 | extern u16 CSVposition; 52 | 53 | u8 Save_Bmp(u8 FileNum); 54 | u8 Save_Dat(u8 FileNum); 55 | u8 Load_Dat(u8 FileNum); 56 | u8 Save_Buf(u8 FileNum); 57 | u8 Load_Buf(u8 FileNum); 58 | u8 Load_Bmp(u8 FileNum); 59 | u8 Save_Csv(u8 FileNum); 60 | u8 Make_Filename(u8 FileNum,char* FileName); 61 | void reset_parameter(void); 62 | u8 Load_Param(u8 FileNum); 63 | u8 Save_Param(u8 FileNum); 64 | u8 Load_Arbt(u8 FileNum); 65 | u8 Load_Uart(u8 FileNum); 66 | u8 Save_Img(void); 67 | u8 ReadDir(char *ext); 68 | void FileMessage(u8 i); 69 | void UpdateFileMenu(void); 70 | u8 DeleteFile(u8* pBuffer,char* FileName); 71 | void save_parameter(void); 72 | 73 | #endif 74 | /********************************* END OF FILE ********************************/ 75 | -------------------------------------------------------------------------------- /inc/Function.h: -------------------------------------------------------------------------------- 1 | /********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** 2 | File Name : Function.h 3 | Version : DS203_APP Ver 2.3x Author : bure 4 | *******************************************************************************/ 5 | #ifndef __Function_H__ 6 | #define __Function_H__ 7 | 8 | #include "stm32f10x_lib.h" 9 | 10 | /* 11 | #define NO_KEY 0 12 | #define KEY1 1 13 | #define KEY2 2 14 | #define KEY3 3 15 | #define KEY4 4 16 | #define K_INDEX_DEC 5 17 | #define K_INDEX_INC 6 18 | #define K_INDEX_S 7 19 | #define K_ITEM_INC 8 20 | #define K_ITEM_DEC 9 21 | #define K_ITEM_S 10 22 | */ 23 | 24 | #define NO_KEY 0 25 | #define KEY1 1 26 | #define KEY3 2 27 | #define KEY4 3 28 | #define K_ITEM_S 4 29 | #define K_INDEX_S 5 30 | #define KEY2 6 31 | #define K_ITEM_DEC 7 32 | #define K_ITEM_INC 8 33 | #define K_INDEX_DEC 9 34 | #define K_INDEX_INC 10 35 | 36 | 37 | #define SIGN 0 38 | #define UNSIGN 1 39 | #define STD 2 40 | 41 | u32 Power(u8 x, u8 y); 42 | void Delayms(u16 mS); 43 | void Int2Str(char *p, s32 n,const char *pUnit, u8 e, u8 Mode, s8 ShiftDigits); 44 | void u8ToDec3(char *p, u16 n,u8 service); 45 | void u8ToDec2(char *p, u8 n); 46 | void Word2Hex(char *p, u32 n); 47 | void s16ToDec3(char *p, s16 n); 48 | //void u16ToDec5(char *p, u16 n); 49 | u32 Int_sqrt(u32 n); 50 | u8 Read_Keys(void); 51 | void s8ToPercen(char *p, s8 n); 52 | void s8ToDec2(char *p, s8 n); 53 | void LoadNwave(void); 54 | u16 AsciiToU16(char *p,u8 n); 55 | void u32ToDec7(char*p,u32 n); 56 | void ProcessFileName(void); 57 | void Char2Hex(char *p, u8 n); 58 | void S32ToFloat3(char *p,s32 n); 59 | 60 | extern u8 SetLowVolume; 61 | 62 | #define N_WAVE 512 // full length of Sinewave[] 63 | #define LOG2_N_WAVE 9 // log2(N_WAVE) 64 | #define FFTSize 512 65 | #define FFTBins 256 66 | #define LOG2_FFTSize 9 67 | //extern void fix_fft(short fr[], short fi[], short m); 68 | extern void fix_fft(s32 fr[], s32 fi[], short m); 69 | 70 | #endif 71 | /********************************* END OF FILE ********************************/ 72 | -------------------------------------------------------------------------------- /inc/Interrupt.h: -------------------------------------------------------------------------------- 1 | /********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** 2 | File Name : Interrupt.h 3 | Version : DS203_APP Ver 2.3x Author : bure 4 | *******************************************************************************/ 5 | 6 | #ifndef __Interrupt_H 7 | #define __Interrupt_H 8 | 9 | #include "stm32f10x_lib.h" 10 | 11 | //extern vu8 Cursor_Cnt, Key_Wait_Cnt, Key_Repeat_Cnt, Key_Buffer, Cnt_mS, Cnt_20mS; 12 | extern vu8 Cursor_Cnt, Key_Wait_Cnt, Key_Repeat_Cnt, Key_Buffer, Cnt_20mS; 13 | extern vu16 Cnt_mS; 14 | extern vu32 LimitTransfer; 15 | 16 | extern vu8 Twink, Blink; 17 | extern u8 Volume, Light, LoBeepLevel; 18 | extern vu16 Delay_Cnt, Beep_mS, Key_Status_Last, Sec_Cnt, PD_Cnt, NotificationTimer,DelayLoopBreak,SpecFrameCount, 19 | PersHoldTimer,SecondsTick,ConfNameTimer, CursorDisplayTimer,AutoSetTimer; 20 | extern vu8 Tim2Factor; 21 | extern vu8 BurstLimit; 22 | extern vu8 FineAdjust; 23 | extern u8 FineAdjustLimit; 24 | extern vu16 FineAdjustFactor[17]; 25 | extern vu8 Key_Mid_Speed; 26 | 27 | extern vu32 Wait_Cnt; 28 | void NMIException(void); 29 | void HardFaultException(void); 30 | void MemManageException(void); 31 | void BusFaultException(void); 32 | void UsageFaultException(void); 33 | void DebugMonitor(void); 34 | void SVCHandler(void); 35 | void PendSVC(void); 36 | void SysTickHandler(void); 37 | void WWDG_IRQHandler(void); 38 | void PVD_IRQHandler(void); 39 | void TAMPER_IRQHandler(void); 40 | void RTC_IRQHandler(void); 41 | void FLASH_IRQHandler(void); 42 | void RCC_IRQHandler(void); 43 | void EXTI0_IRQHandler(void); 44 | void EXTI1_IRQHandler(void); 45 | void EXTI2_IRQHandler(void); 46 | void EXTI3_IRQHandler(void); 47 | void EXTI4_IRQHandler(void); 48 | void DMA1_Channel1_IRQHandler(void); 49 | void DMA1_Channel2_IRQHandler(void); 50 | void DMA1_Channel3_IRQHandler(void); 51 | void DMA1_Channel4_IRQHandler(void); 52 | void DMA1_Channel5_IRQHandler(void); 53 | void DMA1_Channel6_IRQHandler(void); 54 | void DMA1_Channel7_IRQHandler(void); 55 | void ADC1_2_IRQHandler(void); 56 | void USB_HP_CAN_TX_IRQHandler(void); 57 | void USB_LP_CAN_RX0_IRQHandler(void); 58 | void CAN_RX1_IRQHandler(void); 59 | void CAN_SCE_IRQHandler(void); 60 | void EXTI9_5_IRQHandler(void); 61 | void TIM1_BRK_IRQHandler(void); 62 | void TIM1_UP_IRQHandler(void); 63 | void TIM1_TRG_COM_IRQHandler(void); 64 | void TIM1_CC_IRQHandler(void); 65 | void TIM2_IRQHandler(void); 66 | void TIM3_IRQHandler(void); 67 | void TIM4_IRQHandler(void); 68 | void I2C1_EV_IRQHandler(void); 69 | void I2C1_ER_IRQHandler(void); 70 | void I2C2_EV_IRQHandler(void); 71 | void I2C2_ER_IRQHandler(void); 72 | void SPI1_IRQHandler(void); 73 | void SPI2_IRQHandler(void); 74 | void USART1_IRQHandler(void); 75 | void USART2_IRQHandler(void); 76 | void USART3_IRQHandler(void); 77 | void EXTI15_10_IRQHandler(void); 78 | void RTCAlarm_IRQHandler(void); 79 | void USBWakeUp_IRQHandler(void); 80 | void TIM8_BRK_IRQHandler(void); 81 | void TIM8_UP_IRQHandler(void); 82 | void TIM8_TRG_COM_IRQHandler(void); 83 | void TIM8_CC_IRQHandler(void); 84 | void ADC3_IRQHandler(void); 85 | void FSMC_IRQHandler(void); 86 | void SDIO_IRQHandler(void); 87 | void TIM5_IRQHandler(void); 88 | void SPI3_IRQHandler(void); 89 | void UART4_IRQHandler(void); 90 | void UART5_IRQHandler(void); 91 | void TIM6_IRQHandler(void); 92 | void TIM7_IRQHandler(void); 93 | void DMA2_Channel1_IRQHandler(void); 94 | void DMA2_Channel2_IRQHandler(void); 95 | void DMA2_Channel3_IRQHandler(void); 96 | void DMA2_Channel4_5_IRQHandler(void); 97 | void BackLight(s8 shift); 98 | 99 | 100 | #endif /* __Interrupt_H */ 101 | 102 | /********************************* END OF FILE ********************************/ 103 | -------------------------------------------------------------------------------- /inc/Menu.h: -------------------------------------------------------------------------------- 1 | /********************* (C) COPYRIGHT 2010 e-Design Co.,Ltd. ******************** 2 | File Name : Menu.h 3 | Version : DS203_APP Ver 2.4x Author : bure 4 | *******************************************************************************/ 5 | #ifndef __MENU_H 6 | #define __MENU_H 7 | 8 | #include "stm32f10x_lib.h" 9 | 10 | //----------- The Detail menu constants MARK defined ----------- 11 | #define NUM2 0x01 // display the Value of two values in the specified location 12 | #define NUM3 0x02 // in the specified location to display the floating point value of the Value of 3 13 | #define CIRC 0x10 // the Detail Value in the regulation of head circulation 14 | #define FIX 0x20 // the Detail Value change the identity of the corresponding string unchanged 15 | #define NOT 0x80 // skip the Detail item choice 16 | 17 | //----------- Flag of the definition of variables in the Detail menu ----------- 18 | #define HID 0x04 // display the Detail 19 | #define UPDAT 0x02 // refresh the display of the Detail entry 20 | #define BLINK 0x01 // the Detail display flashes 21 | 22 | #define BATTERY 4 23 | 24 | //=============== MENU Main Menu item is number defined =============== 25 | #define TRACK1 0 26 | #define TRACK2 1 27 | #define TRACK3 2 28 | #define TRACK4 3 29 | 30 | #define RUNNING 4 31 | #define OUTPUT 5 32 | 33 | #define T_BASE 6 34 | #define TRIGG 7 35 | #define V_VERNIE 8 36 | #define FILE 9 37 | #define T_VERNIE 10 38 | #define BK_LIGHT 11 39 | #define VOLUME 12 40 | 41 | //------------- TRACKn submenu item number defined -------------- Dettagli TRACK 42 | #define SOURCE 0 43 | #define COUPLE 1 44 | #define RANGE 2 45 | #define POSI 3 46 | 47 | //............ TRACKn SOURCE item number defined ........... 48 | #define HIDE 0 49 | #define CH_A 1 50 | #define CH_B 1 51 | #define CH_X10 2 52 | #define CH_C 1 53 | #define CH_D 1 54 | #define A_add_B 2 55 | #define A_sub_B 3 56 | #define C_and_D 4 57 | #define C_or_D 5 58 | #define REC_1 6 //FILE1,2..4 59 | #define REC_2 7 60 | #define REC_3 8 61 | #define REC_4 9 62 | #define SPEC_B 10 63 | #define SPEC_A 11 64 | #define FFT_B 12 65 | #define FFT_A 14 66 | 67 | 68 | //------------- RUNNING sub-menu item number defined ------------- 69 | #define STATE 0 70 | #define STATUS 1 71 | 72 | //.............. STATE sub-menu item number defined .............. 73 | #define RUN 0 74 | #define HOLD 1 75 | 76 | //-------------- T_BASE sub-menu item number defined ------------- 77 | #define MODE 0 78 | #define BASE 1 79 | #define XPOSI 2 80 | #define VIEW 3 81 | 82 | 83 | //............. T_BASE Mode number defined ............ 84 | #define SCAN 0 85 | #define AUTO 1 86 | #define NORH 2 87 | #define NORHLD 4 88 | #define NORC 3 89 | #define SGL 5 90 | #define X_Y 6 91 | 92 | 93 | 94 | //-------------- OUTPUT sub-menu item number defined ------------- 95 | #define KIND 0 96 | #define FRQN 1 97 | #define DUTYPWM 2 98 | #define OUTATT 3 99 | 100 | //--------------- TRIGG sub-menu item number defined ------------- 101 | #define SOURCE 0 102 | #define TR_KIND 1 103 | #define THRESHOLD 2 104 | 105 | //------------- T_VERNIE sub-menu item number defined ------------ 106 | #define T1 0 107 | #define T2 1 108 | 109 | //------------- V_VERNIE sub-menu item number defined ------------ 110 | #define V1 0 111 | #define V2 1 112 | 113 | //--------------- FILE sub-menu item number defined -------------- 114 | #define SAVE 0 115 | #define LOAD 1 116 | #define BMP 0 117 | #define DAT 1 118 | #define BUF 2 119 | #define CSV 3 120 | #define CFG 4 121 | #define DIR 3 122 | 123 | //--------- BK_LIGHT & VOLUME sub menu item number defined -------- 124 | #define CLASS 1 125 | 126 | //============== METER main menu items defined number ============== 127 | #define METER_0 13 128 | #define METER_1 14 129 | #define METER_2 15 130 | #define METER_3 16 131 | #define METER_4 17 132 | #define METER_5 18 133 | #define METER_6 19 134 | #define METER_7 20 135 | #define METER_8 21 136 | 137 | //------------- METER in Item number defined ------------- 138 | 139 | #define VBT 0 140 | #define FPS 1 141 | #define VDC 2 142 | #define RMS 3 143 | #define FRQ 4 144 | #define MAX 5 145 | #define MIN 6 146 | #define VPP 7 147 | #define CIR 8 148 | #define DUT 9 149 | #define TH 10 150 | #define TL 11 151 | 152 | 153 | #define _Meas_V_Track (Title[V_VERNIE][2].Value) //Sorgente Delta V 154 | #define _Meas_V_Range (Title[_Meas_V_Track][RANGE].Value) 155 | #define _Meas_V_Scale (Y_Attr[_Meas_V_Range].SCALE) 156 | #define _V1_Vernie (Title[V_VERNIE][0].Value) 157 | #define _V2_Vernie (Title[V_VERNIE][1].Value) 158 | #define _D_V_Source Title[V_VERNIE][2] 159 | #define _Delta_V Title[V_VERNIE][3] 160 | #define _Delta_T Title[T_VERNIE][3] 161 | #define _T_Range (Title[T_BASE][1].Value) 162 | #define _T_Scale (X_Attr[_T_Range].SCALE) 163 | #define _T_KP (X_Attr[_T_Range].KP) 164 | 165 | 166 | typedef struct 167 | { 168 | char *Str; 169 | u8 Track; 170 | u8 Item; 171 | uc16 XPOS1; 172 | uc16 XPOS2; 173 | uc8 YPOS; 174 | u8 Flag; // HID=0x04, UPD=0x02, BLINK=0x01, 175 | } meter; 176 | 177 | 178 | typedef struct 179 | { 180 | char *Str; 181 | u16 *Color; 182 | s16 Limit; // Max Value 183 | uc8 MARK; // NUM=0x04, FIX=0x02, CIR=0x01, 184 | u16 XPOS; 185 | uc8 YPOS; 186 | s16 Value; 187 | u8 Flag; // HID=0x04, UPD=0x02, BLINK=0x01, 188 | } menu; 189 | 190 | extern menu Title[13][4]; 191 | extern meter Meter[9]; 192 | extern u8 Current, Update,BTwink; 193 | extern u8 Detail[14]; 194 | extern char NumStr[12]; 195 | extern u16 Result_FPS; 196 | extern const char F_UNITSUB[12], F_UNIT[12], T_UNIT[12], S_UNIT[12], P_UNIT[12], V_UNIT[12]; 197 | extern const char H_UNIT[15], DD_UNIT[15], MM_UNIT[15], VV_UNIT[12]; 198 | extern char N_UNIT[12]; 199 | extern u8 ConfigFileNumber; 200 | extern s16 Ga_Max; 201 | extern s16 Gb_Max; 202 | extern s16 Ga_Min; 203 | extern s16 Gb_Min; 204 | extern s16 GHa_Max; 205 | extern s16 GHb_Max; 206 | extern s16 GHa_Min; 207 | extern s16 GHb_Min; 208 | extern s8 ShiftDigits; 209 | extern u8 AutoFFT; 210 | extern s8 GenFreqShift; 211 | extern u8 GenAdjustMode; 212 | extern uc16 Y_COLOR[5]; // Track Color 2 213 | extern uc8 TIM2Speed[10]; 214 | extern u8 SweepMod; 215 | extern u8 SweepStep; 216 | extern u8 SweepIndex; 217 | extern u8 Sweep; 218 | extern s8 PrevShift; 219 | extern u8 Det; 220 | extern u8 GenTrigColorFlag; 221 | extern u8 EnablePWM; 222 | extern u8 PWAdjustMode; 223 | extern u32 LastFreqReadout; 224 | extern u8 EnableMeterCalc; 225 | extern u8 T1Start; 226 | extern u8 GenBaudAdjSpeed; 227 | extern u32 GenBaudRate; 228 | extern u8 GenUartMode; 229 | extern u8 GenUartCont; 230 | extern u8 GenUartAdj; 231 | extern u16 GenBaudIndex; 232 | extern u8 GenUartStopBits; 233 | extern u8 FastDimAdjust; 234 | extern u8 FastDim; 235 | extern u8 AutoSaveBuf; 236 | extern u8 AutoSaveSelect; 237 | extern u8 AutoTrigSelect; 238 | extern s8 OS_Range; 239 | extern u8 OS_RateSelect; 240 | extern u8 HboldAdjust; 241 | extern u8 DETflag; 242 | extern const char F_EXT[8][10]; 243 | extern u8 ListOverride; 244 | extern char EditChar[8][2]; 245 | extern u8 CharIndex; 246 | extern char CharValue; 247 | extern u8 AdjBeepLevel; 248 | extern char CursorDisplayStr[12]; 249 | extern char CursorDisplayStrM[12]; 250 | extern char CursorDisplayStrH[12]; 251 | extern char VNumstr[12]; 252 | extern const char DELTA_V[2][10]; 253 | extern const char DELTA_T[2][4]; 254 | extern char VNumStr[12]; 255 | extern char TNumStr[12]; 256 | extern u8 MinBypass; 257 | extern u8 AutoSetFlag; 258 | extern u8 AutoSequence; 259 | extern u8 OldCurDefTime; 260 | extern u16 OldPosi; 261 | extern u8 MeterStatus; 262 | extern u8 OldMode; 263 | extern u8 Neg; 264 | extern u8 DownConvertMode; 265 | 266 | void EnableMeter(void); 267 | void DisableMeter(void); 268 | void Display_Value(u8 i); 269 | void Display_Title(void); 270 | void Display_Meter(void); 271 | void Load_Attr(void); 272 | void Update_Battery(void); 273 | void DisplayBigMeter(u8 MeterNum); 274 | void MeterDefaults(void); 275 | u32 UpScale(u32 Tmp, u16 limit); 276 | void DisplaySamples(void); 277 | void FFTlevel(u8 service); 278 | void OutputAdjust(void); 279 | void TIM_2IRQControl(void); 280 | void GenTrigColor(void); 281 | void UpdatePWMDuty(u8 service); 282 | void AlignTbaseSweep(u8 dir); 283 | u8 DetStatusLogic(u8 logic); 284 | u8 ChartLogic(void); 285 | void UpdateEditBox(u8 mode); 286 | u8 ListLogic(void); 287 | u8 EditListActive(u8 mode); 288 | void CalculateVvernier(u8 mode); 289 | void CalculateTvernier(u8 mode); 290 | void AutoSet(void); 291 | void UpdateMeterPage(void); 292 | u16 KpCompensation(void); 293 | u32 ClockAdjust(u32 Value); 294 | 295 | #endif 296 | 297 | /********************************* END OF FILE ********************************/ 298 | -------------------------------------------------------------------------------- /inc/Process.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/inc/Process.h -------------------------------------------------------------------------------- /inc/stm32f10x_conf.h: -------------------------------------------------------------------------------- 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** 2 | * File Name : stm32f10x_conf.h 3 | * Author : MCD Application Team 4 | * Version : V2.2.1 5 | * Date : 09/22/2008 6 | * Description : Library configuration file. 7 | ******************************************************************************** 8 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 9 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 10 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 11 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 12 | * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 13 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 14 | *******************************************************************************/ 15 | 16 | /* Define to prevent recursive inclusion -------------------------------------*/ 17 | #ifndef __STM32F10x_CONF_H 18 | #define __STM32F10x_CONF_H 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "stm32f10x_type.h" 22 | 23 | /* Exported types ------------------------------------------------------------*/ 24 | /* Exported constants --------------------------------------------------------*/ 25 | /* Uncomment the line below to compile the library in DEBUG mode, this will expanse 26 | the "assert_param" macro in the firmware library code (see "Exported macro" 27 | section below) */ 28 | /* #define DEBUG 1*/ 29 | 30 | /* Comment the line below to disable the specific peripheral inclusion */ 31 | /************************************* ADC ************************************/ 32 | //#define _ADC 33 | //#define _ADC1 34 | //#define _ADC2 35 | //#define _ADC3 36 | 37 | /************************************* BKP ************************************/ 38 | //#define _BKP 39 | 40 | /************************************* CAN ************************************/ 41 | //#define _CAN 42 | 43 | /************************************* CRC ************************************/ 44 | //#define _CRC 45 | 46 | /************************************* DAC ************************************/ 47 | #define _DAC 48 | 49 | /************************************* DBGMCU *********************************/ 50 | //#define _DBGMCU 51 | 52 | /************************************* DMA ************************************/ 53 | #define _DMA 54 | //#define _DMA1_Channel1 55 | //#define _DMA1_Channel2 56 | //#define _DMA1_Channel3 57 | #define _DMA1_Channel4 //used by USART1 58 | //#define _DMA1_Channel5 59 | //#define _DMA1_Channel6 60 | //#define _DMA1_Channel7 61 | //#define _DMA2_Channel1 62 | //#define _DMA2_Channel2 63 | //#define _DMA2_Channel3 64 | #define _DMA2_Channel4 65 | //#define _DMA2_Channel5 66 | 67 | /************************************* EXTI ***********************************/ 68 | //#define _EXTI 69 | 70 | /************************************* FLASH and Option Bytes *****************/ 71 | #define _FLASH 72 | /* Uncomment the line below to enable FLASH program/erase/protections functions, 73 | otherwise only FLASH configuration (latency, prefetch, half cycle) functions 74 | are enabled */ 75 | #define _FLASH_PROG 76 | 77 | /************************************* FSMC ***********************************/ 78 | #define _FSMC 79 | 80 | /************************************* GPIO ***********************************/ 81 | 82 | #define _GPIO 83 | #define _GPIOA 84 | #define _GPIOB 85 | #define _GPIOC 86 | #define _GPIOD 87 | #define _GPIOE 88 | #define _GPIOF 89 | #define _GPIOG 90 | #define _AFIO 91 | 92 | /************************************* I2C ************************************/ 93 | //#define _I2C 94 | //#define _I2C1 95 | //#define _I2C2 96 | 97 | /************************************* IWDG ***********************************/ 98 | //#define _IWDG 99 | 100 | /************************************* NVIC ***********************************/ 101 | #define _NVIC 102 | 103 | /************************************* PWR ************************************/ 104 | //#define _PWR 105 | 106 | /************************************* RCC ************************************/ 107 | #define _RCC 108 | 109 | /************************************* RTC ************************************/ 110 | //#define _RTC 111 | 112 | /************************************* SDIO ***********************************/ 113 | #define _SDIO 114 | 115 | /************************************* SPI ************************************/ 116 | #define _SPI 117 | #define _SPI1 118 | #define _SPI2 119 | #define _SPI3 120 | 121 | /************************************* SysTick ********************************/ 122 | //#define _SysTick 123 | 124 | /************************************* TIM ************************************/ 125 | //#define _TIM 126 | #define _TIM1 //enabled for experimental chart mode 127 | #define _TIM2 128 | #define _TIM3 129 | #define _TIM4 130 | //#define _TIM5 131 | #define _TIM6 132 | #define _TIM7 133 | //#define _TIM8 134 | 135 | /************************************* USART **********************************/ 136 | //#define _USART 137 | #define _USART1 138 | //#define _USART2 139 | //#define _USART3 140 | //#define _UART4 141 | //#define _UART5 142 | 143 | /************************************* WWDG ***********************************/ 144 | //#define _WWDG 145 | 146 | /* In the following line adjust the value of External High Speed oscillator (HSE) 147 | used in your application */ 148 | #define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ 149 | 150 | /* In the following line adjust the External High Speed oscillator (HSE) Startup 151 | Timeout value */ 152 | #define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */ 153 | 154 | /* Exported macro ------------------------------------------------------------*/ 155 | #ifdef DEBUG 156 | /******************************************************************************* 157 | * Macro Name : assert_param 158 | * Description : The assert_param macro is used for function's parameters check. 159 | * It is used only if the library is compiled in DEBUG mode. 160 | * Input : - expr: If expr is false, it calls assert_failed function 161 | * which reports the name of the source file and the source 162 | * line number of the call that failed. 163 | * If expr is true, it returns no value. 164 | * Return : None 165 | *******************************************************************************/ 166 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) 167 | /* Exported functions ------------------------------------------------------- */ 168 | void assert_failed(u8* file, u32 line); 169 | #else 170 | #define assert_param(expr) ((void)0) 171 | #endif /* DEBUG */ 172 | 173 | #endif /* __STM32F10x_CONF_H */ 174 | 175 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ 176 | -------------------------------------------------------------------------------- /main.lds: -------------------------------------------------------------------------------- 1 | /* stack pointer should point to the address ABOVE the available RAM */ 2 | _estack = ORIGIN(ram)+LENGTH(ram); 3 | /*_estack = ORIGIN(ram)+LENGTH(ram)-0x2000;*/ 4 | 5 | /* Linker script for Olimex STM32-H103 eval board. 6 | * 7 | * Version: 0.1 8 | * 9 | * Copyright 2007 CodeSourcery. 10 | * 11 | * The authors hereby grant permission to use, copy, modify, distribute, 12 | * and license this software and its documentation for any purpose, provided 13 | * that existing copyright notices are retained in all copies and that this 14 | * notice is included verbatim in any distributions. No written agreement, 15 | * license, or royalty fee is required for any of the authorized uses. 16 | * Modifications to this software may be copyrighted by their authors 17 | * and need not follow the licensing terms described here, provided that 18 | * the new terms are clearly indicated on the first page of each file where 19 | * they apply. 20 | * 21 | * Modified by Olimex 22 | * 2009-04-07: Modified by Piotr Esden-Tempski 23 | */ 24 | 25 | SECTIONS 26 | { 27 | . = 0x0; /* From 0x00000000 */ 28 | 29 | .bios 0x08004200 (NOLOAD) : { 30 | BIOS.o 31 | } 32 | 33 | .isr_vector : { 34 | _vectors = .; 35 | *(.isr_vectors) /* Vector table */ 36 | . = ALIGN(4); 37 | /* startup.o(.text) */ 38 | *(.text.startup) 39 | stm32f10x_nvic.o(.text) 40 | cortexm3_macro.o(.text) 41 | 42 | /* Main.o(.text) */ 43 | /* Files.o(.text) */ 44 | 45 | Function.o(.text) 46 | Calibrat.o(.text) 47 | Interrupt.o(.text) 48 | /* Draw.o(.text) */ 49 | /* Process.o(.text)*/ 50 | *(.rodata*) /* Read only data */ 51 | } >rom 52 | 53 | .spare : { /*Undocumented area*/ 54 | . = ALIGN(4); 55 | startup.o(.text) 56 | Draw.o(.text) 57 | /* Interrupt.o(.text) */ 58 | Main.o(.text) 59 | Menu.o(.text) 60 | } >spare 61 | 62 | 63 | .extra : { /*Undocumented area*/ 64 | . = ALIGN(4); 65 | *(.text*) /*Program code */ 66 | } >extra 67 | 68 | 69 | .text : { 70 | . = ALIGN(4); 71 | _etext = .; 72 | _sidata = _etext; 73 | } >rom 74 | 75 | .data : AT ( _sidata ) { 76 | _sdata = . ; 77 | *(.data*) /* Data memory */ 78 | . = ALIGN(4); 79 | _edata = .; 80 | } >ram 81 | 82 | .bss (NOLOAD) : { 83 | _sbss = .; 84 | *(.bss) /* Zero-filled run time allocate data memory */ 85 | . = ALIGN(4); 86 | _ebss = .; 87 | } >ram AT > rom 88 | } 89 | /*========== end of file ==========*/ 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | -------------------------------------------------------------------------------- /startup.c: -------------------------------------------------------------------------------- 1 | #include "stm32f10x_lib.h" 2 | #include "Interrupt.h" 3 | 4 | typedef void( *const intfunc )( void ); 5 | 6 | #define WEAK __attribute__ ((weak)) 7 | 8 | extern unsigned long _etext; 9 | extern unsigned long _sidata; 10 | extern unsigned long _sdata; 11 | extern unsigned long _edata; 12 | extern unsigned long _sbss; 13 | extern unsigned long _ebss; 14 | extern unsigned long _estack; 15 | 16 | void Reset_Handler(void) __attribute__((__interrupt__)); 17 | void __Init_Data(void); 18 | void Default_Handler(void); 19 | 20 | extern int main(void); 21 | extern void __libc_init_array(void); 22 | 23 | void WEAK NMI_Handler(void); 24 | void WEAK HardFault_Handler(void); 25 | void WEAK MemManage_Handler(void); 26 | void WEAK BusFault_Handler(void); 27 | void WEAK UsageFault_Handler(void); 28 | void WEAK MemManage_Handler(void); 29 | void WEAK SVC_Handler(void); 30 | void WEAK DebugMon_Handler(void); 31 | void WEAK PendSV_Handler(void); 32 | void WEAK SysTick_Handler(void); 33 | 34 | void WEAK WWDG_IRQHandler(void); 35 | void WEAK PVD_IRQHandler(void); 36 | void WEAK TAMPER_IRQHandler(void); 37 | void WEAK RTC_IRQHandler(void); 38 | void WEAK FLASH_IRQHandler(void); 39 | void WEAK RCC_IRQHandler(void); 40 | void WEAK EXTI0_IRQHandler(void); 41 | void WEAK EXTI1_IRQHandler(void); 42 | void WEAK EXTI2_IRQHandler(void); 43 | void WEAK EXTI3_IRQHandler(void); 44 | void WEAK EXTI4_IRQHandler(void); 45 | void WEAK DMA1_Channel1_IRQHandler(void); 46 | void WEAK DMA1_Channel2_IRQHandler(void); 47 | void WEAK DMA1_Channel3_IRQHandler(void); 48 | void WEAK DMA1_Channel4_IRQHandler(void); 49 | void WEAK DMA1_Channel5_IRQHandler(void); 50 | void WEAK DMA1_Channel6_IRQHandler(void); 51 | void WEAK DMA1_Channel7_IRQHandler(void); 52 | void WEAK ADC1_2_IRQHandler(void); 53 | void WEAK USB_HP_CAN1_TX_IRQHandler(void); 54 | void WEAK USB_LP_CAN1_RX0_IRQHandler(void); 55 | void WEAK CAN1_RX1_IRQHandler(void); 56 | void WEAK CAN1_SCE_IRQHandler(void); 57 | void WEAK EXTI9_5_IRQHandler(void); 58 | void WEAK TIM1_BRK_IRQHandler(void); 59 | void WEAK TIM1_UP_IRQHandler(void); 60 | void WEAK TIM1_TRG_COM_IRQHandler(void); 61 | void WEAK TIM1_CC_IRQHandler(void); 62 | void WEAK TIM2_IRQHandler(void); 63 | void WEAK TIM3_IRQHandler(void); 64 | void WEAK TIM4_IRQHandler(void); 65 | void WEAK I2C1_EV_IRQHandler(void); 66 | void WEAK I2C1_ER_IRQHandler(void); 67 | void WEAK I2C2_EV_IRQHandler(void); 68 | void WEAK I2C2_ER_IRQHandler(void); 69 | void WEAK SPI1_IRQHandler(void); 70 | void WEAK SPI2_IRQHandler(void); 71 | void WEAK USART1_IRQHandler(void); 72 | void WEAK USART2_IRQHandler(void); 73 | void WEAK USART3_IRQHandler(void); 74 | void WEAK EXTI15_10_IRQHandler(void); 75 | void WEAK RTCAlarm_IRQHandler(void); 76 | void WEAK USBWakeUp_IRQHandler(void); 77 | void WEAK TIM8_BRK_IRQHandler(void); 78 | void WEAK TIM8_UP_IRQHandler(void); 79 | void WEAK TIM8_TRG_COM_IRQHandler(void); 80 | void WEAK TIM8_CC_IRQHandler(void); 81 | void WEAK ADC3_IRQHandler(void); 82 | void WEAK FSMC_IRQHandler(void); 83 | void WEAK SDIO_IRQHandler(void); 84 | void WEAK TIM5_IRQHandler(void); 85 | void WEAK SPI3_IRQHandler(void); 86 | void WEAK UART4_IRQHandler(void); 87 | void WEAK UART5_IRQHandler(void); 88 | void WEAK TIM6_IRQHandler(void); 89 | void WEAK TIM7_IRQHandler(void); 90 | void WEAK DMA2_Channel1_IRQHandler(void); 91 | void WEAK DMA2_Channel2_IRQHandler(void); 92 | void WEAK DMA2_Channel3_IRQHandler(void); 93 | void WEAK DMA2_Channel4_5_IRQHandler(void); 94 | 95 | __attribute__ ((section(".isr_vectors"))) 96 | void (* const g_pfnVectors[])(void) = { 97 | (intfunc)((unsigned long)&_estack), /* The stack pointer after relocation */ 98 | #if 0 99 | Reset_Handler, /* Reset Handler */ 100 | NMI_Handler, /* NMI Handler */ 101 | HardFault_Handler, /* Hard Fault Handler */ 102 | MemManage_Handler, /* MPU Fault Handler */ 103 | BusFault_Handler, /* Bus Fault Handler */ 104 | UsageFault_Handler, /* Usage Fault Handler */ 105 | 0, /* Reserved */ 106 | 0, /* Reserved */ 107 | 0, /* Reserved */ 108 | 0, /* Reserved */ 109 | SVC_Handler, /* SVCall Handler */ 110 | DebugMon_Handler, /* Debug Monitor Handler */ 111 | 0, /* Reserved */ 112 | PendSV_Handler, /* PendSV Handler */ 113 | SysTick_Handler, /* SysTick Handler */ 114 | 115 | /* External Interrupts */ 116 | WWDG_IRQHandler, /* Window Watchdog */ 117 | PVD_IRQHandler, /* PVD through EXTI Line detect */ 118 | TAMPER_IRQHandler, /* Tamper */ 119 | RTC_IRQHandler, /* RTC */ 120 | FLASH_IRQHandler, /* Flash */ 121 | RCC_IRQHandler, /* RCC */ 122 | EXTI0_IRQHandler, /* EXTI Line 0 */ 123 | EXTI1_IRQHandler, /* EXTI Line 1 */ 124 | EXTI2_IRQHandler, /* EXTI Line 2 */ 125 | EXTI3_IRQHandler, /* EXTI Line 3 */ 126 | EXTI4_IRQHandler, /* EXTI Line 4 */ 127 | DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */ 128 | DMA1_Channel2_IRQHandler, /* DMA1 Channel 2 */ 129 | DMA1_Channel3_IRQHandler, /* DMA1 Channel 3 */ 130 | DMA1_Channel4_IRQHandler, /* DMA1 Channel 4 */ 131 | DMA1_Channel5_IRQHandler, /* DMA1 Channel 5 */ 132 | DMA1_Channel6_IRQHandler, /* DMA1 Channel 6 */ 133 | DMA1_Channel7_IRQHandler, /* DMA1 Channel 7 */ 134 | ADC1_2_IRQHandler, /* ADC1 & ADC2 */ 135 | USB_HP_CAN1_TX_IRQHandler, /* USB High Priority or CAN1 TX */ 136 | USB_LP_CAN1_RX0_IRQHandler, /* USB Low Priority or CAN1 RX0 */ 137 | CAN1_RX1_IRQHandler, /* CAN1 RX1 */ 138 | CAN1_SCE_IRQHandler, /* CAN1 SCE */ 139 | EXTI9_5_IRQHandler, /* EXTI Line 9..5 */ 140 | TIM1_BRK_IRQHandler, /* TIM1 Break */ 141 | TIM1_UP_IRQHandler, /* TIM1 Update */ 142 | TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation */ 143 | TIM1_CC_IRQHandler, /* TIM1 Capture Compare */ 144 | TIM2_IRQHandler, /* TIM2 */ 145 | TIM3_IRQHandler, /* TIM3 */ 146 | TIM4_IRQHandler, /* TIM4 */ 147 | I2C1_EV_IRQHandler, /* I2C1 Event */ 148 | I2C1_ER_IRQHandler, /* I2C1 Error */ 149 | I2C2_EV_IRQHandler, /* I2C2 Event */ 150 | I2C2_ER_IRQHandler, /* I2C2 Error */ 151 | SPI1_IRQHandler, /* SPI1 */ 152 | SPI2_IRQHandler, /* SPI2 */ 153 | USART1_IRQHandler, /* USART1 */ 154 | USART2_IRQHandler, /* USART2 */ 155 | USART3_IRQHandler, /* USART3 */ 156 | EXTI15_10_IRQHandler, /* EXTI Line 15..10 */ 157 | RTCAlarm_IRQHandler, /* RTC Alarm through EXTI Line */ 158 | USBWakeUp_IRQHandler, /* USB Wakeup from suspend */ 159 | TIM8_BRK_IRQHandler, 160 | TIM8_UP_IRQHandler, 161 | TIM8_TRG_COM_IRQHandler, 162 | TIM8_CC_IRQHandler, 163 | ADC3_IRQHandler, 164 | FSMC_IRQHandler, 165 | SDIO_IRQHandler, 166 | TIM5_IRQHandler, 167 | SPI3_IRQHandler, 168 | UART4_IRQHandler, 169 | UART5_IRQHandler, 170 | TIM6_IRQHandler, 171 | TIM7_IRQHandler, 172 | DMA2_Channel1_IRQHandler, 173 | DMA2_Channel2_IRQHandler, 174 | DMA2_Channel3_IRQHandler, 175 | DMA2_Channel4_5_IRQHandler, 176 | 0, 0, 0, 0, 0, 177 | 0, 0, 0, 0, 0, 178 | 0, 0, 0, 0, 0, 179 | 0, 0, 0, 0, 0, 180 | 0, 0, 0, 0, 0, 181 | 0, 0, 0, 0, 0, 182 | 0, 0, 0, 0, 0, 183 | 0, 0, 0, 0, 0, 184 | 0, 0, 0, 185 | (intfunc)0xF1E0F85F /* @0x1E0. This is for boot in RAM mode for STM32F10x High Density devices. */ 186 | #endif 187 | Reset_Handler, NMIException, HardFaultException, 188 | MemManageException, BusFaultException, UsageFaultException, 0, 0, 189 | 0, 0, SVCHandler, DebugMonitor, 0, PendSVC, SysTickHandler, 190 | WWDG_IRQHandler, PVD_IRQHandler, TAMPER_IRQHandler, RTC_IRQHandler, 191 | FLASH_IRQHandler, RCC_IRQHandler, EXTI0_IRQHandler, 192 | EXTI1_IRQHandler, EXTI2_IRQHandler, EXTI3_IRQHandler, 193 | EXTI4_IRQHandler, DMA1_Channel1_IRQHandler, 194 | DMA1_Channel2_IRQHandler, DMA1_Channel3_IRQHandler, 195 | DMA1_Channel4_IRQHandler, DMA1_Channel5_IRQHandler, 196 | DMA1_Channel6_IRQHandler, DMA1_Channel7_IRQHandler, 197 | ADC1_2_IRQHandler, USB_HP_CAN_TX_IRQHandler, 198 | USB_LP_CAN_RX0_IRQHandler, CAN_RX1_IRQHandler, CAN_SCE_IRQHandler, 199 | EXTI9_5_IRQHandler, TIM1_BRK_IRQHandler, TIM1_UP_IRQHandler, 200 | TIM1_TRG_COM_IRQHandler, TIM1_CC_IRQHandler, TIM2_IRQHandler, 201 | TIM3_IRQHandler, TIM4_IRQHandler, I2C1_EV_IRQHandler, 202 | I2C1_ER_IRQHandler, I2C2_EV_IRQHandler, I2C2_ER_IRQHandler, 203 | SPI1_IRQHandler, SPI2_IRQHandler, USART1_IRQHandler, 204 | USART2_IRQHandler, USART3_IRQHandler, EXTI15_10_IRQHandler, 205 | RTCAlarm_IRQHandler, USBWakeUp_IRQHandler, TIM8_BRK_IRQHandler, 206 | TIM8_UP_IRQHandler, TIM8_TRG_COM_IRQHandler, TIM8_CC_IRQHandler, 207 | ADC3_IRQHandler, FSMC_IRQHandler, SDIO_IRQHandler, TIM5_IRQHandler, 208 | SPI3_IRQHandler, UART4_IRQHandler, UART5_IRQHandler, 209 | TIM6_IRQHandler, TIM7_IRQHandler, DMA2_Channel1_IRQHandler, 210 | DMA2_Channel2_IRQHandler, DMA2_Channel3_IRQHandler, 211 | DMA2_Channel4_5_IRQHandler 212 | }; 213 | 214 | void __Init_Data(void) { 215 | unsigned long *src, *dst; 216 | /* copy the data segment into ram */ 217 | src = &_sidata; 218 | dst = &_sdata; 219 | if (src != dst) 220 | while(dst < &_edata) 221 | *(dst++) = *(src++); 222 | 223 | /* zero the bss segment */ 224 | dst = &_sbss; 225 | while(dst < &_ebss) 226 | *(dst++) = 0; 227 | } 228 | 229 | void Reset_Handler(void) { 230 | /* Initialize data and bss */ 231 | __Init_Data(); 232 | main(); 233 | while(1) {} 234 | } 235 | 236 | #pragma weak MMI_Handler = Default_Handler 237 | #pragma weak MemManage_Handler = Default_Handler 238 | #pragma weak BusFault_Handler = Default_Handler 239 | #pragma weak UsageFault_Handler = Default_Handler 240 | #pragma weak SVC_Handler = Default_Handler 241 | #pragma weak DebugMon_Handler = Default_Handler 242 | #pragma weak PendSV_Handler = Default_Handler 243 | #pragma weak SysTick_Handler = Default_Handler 244 | #pragma weak WWDG_IRQHandler = Default_Handler 245 | #pragma weak PVD_IRQHandler = Default_Handler 246 | #pragma weak TAMPER_IRQHandler = Default_Handler 247 | #pragma weak RTC_IRQHandler = Default_Handler 248 | #pragma weak FLASH_IRQHandler = Default_Handler 249 | #pragma weak RCC_IRQHandler = Default_Handler 250 | #pragma weak EXTI0_IRQHandler = Default_Handler 251 | #pragma weak EXTI1_IRQHandler = Default_Handler 252 | #pragma weak EXTI2_IRQHandler = Default_Handler 253 | #pragma weak EXTI3_IRQHandler = Default_Handler 254 | #pragma weak EXTI4_IRQHandler = Default_Handler 255 | #pragma weak DMA1_Channel1_IRQHandler = Default_Handler 256 | #pragma weak DMA1_Channel2_IRQHandler = Default_Handler 257 | #pragma weak DMA1_Channel3_IRQHandler = Default_Handler 258 | #pragma weak DMA1_Channel4_IRQHandler = Default_Handler 259 | #pragma weak DMA1_Channel5_IRQHandler = Default_Handler 260 | #pragma weak DMA1_Channel6_IRQHandler = Default_Handler 261 | #pragma weak DMA1_Channel7_IRQHandler = Default_Handler 262 | #pragma weak ADC1_2_IRQHandler = Default_Handler 263 | #pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler 264 | #pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler 265 | #pragma weak CAN1_RX1_IRQHandler = Default_Handler 266 | #pragma weak CAN1_SCE_IRQHandler = Default_Handler 267 | #pragma weak EXTI9_5_IRQHandler = Default_Handler 268 | #pragma weak TIM1_BRK_IRQHandler = Default_Handler 269 | #pragma weak TIM1_UP_IRQHandler = Default_Handler 270 | #pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler 271 | #pragma weak TIM1_CC_IRQHandler = Default_Handler 272 | #pragma weak TIM2_IRQHandler = Default_Handler 273 | #pragma weak TIM3_IRQHandler = Default_Handler 274 | #pragma weak TIM4_IRQHandler = Default_Handler 275 | #pragma weak I2C1_EV_IRQHandler = Default_Handler 276 | #pragma weak I2C1_ER_IRQHandler = Default_Handler 277 | #pragma weak I2C2_EV_IRQHandler = Default_Handler 278 | #pragma weak I2C2_ER_IRQHandler = Default_Handler 279 | #pragma weak SPI1_IRQHandler = Default_Handler 280 | #pragma weak SPI2_IRQHandler = Default_Handler 281 | #pragma weak USART1_IRQHandler = Default_Handler 282 | #pragma weak USART2_IRQHandler = Default_Handler 283 | #pragma weak USART3_IRQHandler = Default_Handler 284 | #pragma weak EXTI15_10_IRQHandler = Default_Handler 285 | #pragma weak RTCAlarm_IRQHandler = Default_Handler 286 | #pragma weak USBWakeUp_IRQHandler = Default_Handler 287 | #pragma weak TIM8_BRK_IRQHandler = Default_Handler 288 | #pragma weak TIM8_UP_IRQHandler = Default_Handler 289 | #pragma weak TIM8_TRG_COM_IRQHandler = Default_Handler 290 | #pragma weak TIM8_CC_IRQHandler = Default_Handler 291 | #pragma weak ADC3_IRQHandler = Default_Handler 292 | #pragma weak FSMC_IRQHandler = Default_Handler 293 | #pragma weak SDIO_IRQHandler = Default_Handler 294 | #pragma weak TIM5_IRQHandler = Default_Handler 295 | #pragma weak SPI3_IRQHandler = Default_Handler 296 | #pragma weak UART4_IRQHandler = Default_Handler 297 | #pragma weak UART5_IRQHandler = Default_Handler 298 | #pragma weak TIM6_IRQHandler = Default_Handler 299 | #pragma weak TIM7_IRQHandler = Default_Handler 300 | #pragma weak DMA2_Channel1_IRQHandler = Default_Handler 301 | #pragma weak DMA2_Channel2_IRQHandler = Default_Handler 302 | #pragma weak DMA2_Channel3_IRQHandler = Default_Handler 303 | #pragma weak DMA2_Channel4_5_IRQHandler = Default_Handler 304 | 305 | void Default_Handler(void) { 306 | while (1) {} 307 | } 308 | 309 | void _init(void) 310 | { 311 | } 312 | -------------------------------------------------------------------------------- /stm32f10x_nvic.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jelinj8/dso203/2952b73cfe4bc611df425a93fe688a5909d81c6e/stm32f10x_nvic.c --------------------------------------------------------------------------------