├── LICENSE.txt ├── README.md ├── RELEASE.txt ├── doc ├── images │ ├── image1.png │ ├── image2.jpg │ ├── image2.png │ ├── image3.png │ └── image4.jpg └── index.html ├── riscv_tests_hexgen ├── Makefile ├── build │ ├── add.hex │ ├── addi.hex │ ├── and.hex │ ├── andi.hex │ ├── auipc.hex │ ├── beq.hex │ ├── bge.hex │ ├── bgeu.hex │ ├── blt.hex │ ├── bltu.hex │ ├── bne.hex │ ├── fence_i.hex │ ├── hex_files.txt │ ├── jal.hex │ ├── jalr.hex │ ├── lb.hex │ ├── lbu.hex │ ├── lh.hex │ ├── lhu.hex │ ├── lui.hex │ ├── lw.hex │ ├── or.hex │ ├── ori.hex │ ├── sb.hex │ ├── sh.hex │ ├── simple.hex │ ├── sll.hex │ ├── slli.hex │ ├── slt.hex │ ├── slti.hex │ ├── sltiu.hex │ ├── sltu.hex │ ├── sra.hex │ ├── srai.hex │ ├── srl.hex │ ├── srli.hex │ ├── sub.hex │ ├── sw.hex │ ├── xor.hex │ └── xori.hex └── link.ld ├── scripts └── riscv_decode.rb └── src ├── Makefile ├── csrs.svh ├── csrs_unit_test.sv ├── decoder.svh ├── hex_file_analyzer.svh ├── hex_file_analyzer_unit_test.sv ├── inst_history.svh ├── inst_history_unit_test.sv ├── instruction.svh ├── instruction_unit_test.sv ├── reg_fetcher.svh ├── reg_fetcher_unit_test.sv ├── regfile.svh ├── regfile_unit_test.sv ├── riscv_vip.do ├── riscv_vip.f ├── riscv_vip_class_pkg.sv ├── riscv_vip_csr_if.sv ├── riscv_vip_defines.svh ├── riscv_vip_inst_if.sv ├── riscv_vip_pkg.sv ├── riscv_vip_regfile_if.sv └── uvm ├── Makefile ├── i32_agent.svh ├── i32_agent_unit_test.sv ├── i32_cov_subscriber.svh ├── i32_item.svh ├── i32_monitor.svh ├── inst_history_subscriber.svh ├── riscv_vip_uvc.f ├── riscv_vip_uvc_pkg.sv ├── test ├── Makefile ├── riscv_vip_base_test.svh ├── riscv_vip_base_test_unit_test.sv ├── riscv_vip_test.f └── riscv_vip_test_pkg.sv ├── uvc_env.svh └── uvc_env_unit_test.sv /README.md: -------------------------------------------------------------------------------- 1 | 2 | Licensed to the Apache Software Foundation (ASF) under one 3 | or more contributor license agreements. See the NOTICE file 4 | distributed with this work for additional information 5 | regarding copyright ownership. The ASF licenses this file 6 | to you under the Apache License, Version 2.0 (the 7 | "License"); you may not use this file except in compliance 8 | with the License. You may obtain a copy of the License at 9 | 10 | http://www.apache.org/licenses/LICENSE-2.0 11 | 12 | Unless required by applicable law or agreed to in writing, 13 | software distributed under the License is distributed on an 14 | "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 15 | KIND, either express or implied. See the License for the 16 | specific language governing permissions and limitations 17 | under the License. 18 | 19 | 20 | [ riscv-vip ] 21 | ====================== 22 | 23 | About 24 | ---------------------------- 25 | This repository hosts RISC-V related SystemVerilog Verification IP. 26 | 27 | See the riscv-vip users' guide for important user details. The users' guide source is in the doc/ directory and is browser viewable at https://jerralph.github.io/riscv-vip/doc/index.html 28 | 29 | Find the release notes in the RELEASE.txt file. 30 | 31 | Get riscv-vip 32 | ---------------------------- 33 | ``` 34 | $ git clone https://github.com/jerralph/riscv-vip.git 35 | $ cd riscv-vip 36 | ``` 37 | 38 | Poke around the code and [docs](https://jerralph.github.io/riscv-vip/doc/index.html). 39 | 40 | 41 | Run a unit test 42 | ---------------------------- 43 | 44 | 1. Download and install SVUnit from https://github.com/nosnhojn/svunit-code. Follow the instructions posted there to install. 45 | 2. Run the Hex file analyzer in the riscv-vip/src directory. 46 | 47 | * using the Mentor Questa Simulator. 48 | ``` 49 | $ make hex_ut 50 | ``` 51 | 52 | * Using the Cadence IUS Simulator 53 | ``` 54 | $make hex_ut SIMR=ius 55 | ``` 56 | Integrate into your verification environment 57 | ----------------------------------- 58 | See the [Users' Guide](https://jerralph.github.io/riscv-vip/doc/index.html) for information on how to integrate into your own verification environment. 59 | 60 | -------------------------------------------------------------------------------- /RELEASE.txt: -------------------------------------------------------------------------------- 1 | [riscv-vip] Release Notes 2 | 3 | 4 | pre-v0.1.0 - 2018-06-22 5 | --------- 6 | - files commited and later snapshots working 7 | 8 | v0.1.0 - 2018-07-03 9 | --------- 10 | - intial release. 11 | 12 | v0.1.1 - 2018-07-04 13 | -------- 14 | - added missing src/uvm/test*.sv files (thanks to my colleage Ram C. for finding this!) 15 | 16 | v0.1.2 - 2018-07-05 17 | ----------------- 18 | - updated some wrong paths/typos in the users' guide 19 | 20 | v0.1.3 - 2018-07-10 21 | ----------------- 22 | - updated/clarified docs, riscv-test hex_file_analyzer hex file gen section 23 | - beefed up i32_agent uvc_env unit tests 24 | - added uvm test unit test 25 | 26 | v0.2.0 27 | ----------------- 28 | - Integrated register file monitoring and rs1/2 value association with instructions. 29 | - Documentation updated accordingly and recommending that the instruction is tapped upon commit. 30 | 31 | v0.3.0 32 | ----------------- 33 | - instruction history and read-after-write hazard/forwarding cross coverage integrated and tested 34 | - updated docs to include instruction history and raw cross info 35 | -------------------------------------------------------------------------------- /doc/images/image1.png: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/jerralph/riscv-vip/eb0827fe15622b06f271c4094a954863a9133c98/doc/images/image3.png -------------------------------------------------------------------------------- /doc/images/image4.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jerralph/riscv-vip/eb0827fe15622b06f271c4094a954863a9133c98/doc/images/image4.jpg -------------------------------------------------------------------------------- /riscv_tests_hexgen/Makefile: -------------------------------------------------------------------------------- 1 | # This makefile generates HEX and Dump files for RV32UI tests 2 | # from the RISCV Foundation's riscv_tests project. 3 | # 4 | # This makefile requires that RISCV_TESTS be set to the location where the 5 | # riscv_test repository has been cloned and installed 6 | # (see https://github.com/riscv/riscv-tests). 7 | 8 | ARCH ?= i 9 | ABI ?= ilp32 10 | ROOT_DIR := $(shell pwd) 11 | RUNTIME_REL_BUILD_DIR := ../riscv_tests_hexgen/build 12 | BUILD_DIR := $(ROOT_DIR)/build 13 | OBJ_DIR := $(BUILD_DIR)/obj 14 | RISCV_ISA_SRC_DIR := $(RISCV_TESTS)/isa 15 | S_FILES := $(shell ls $$RISCV_TESTS/isa/rv32ui/*.S) 16 | TESTS := $(patsubst %.S, %, $(notdir $(S_FILES))) 17 | OBJ := $(addprefix $(OBJ_DIR)/,$(TESTS:%=%.o)) 18 | ELF := $(addprefix $(BUILD_DIR)/,$(TESTS:%=%.elf)) 19 | HEX := $(addprefix $(BUILD_DIR)/,$(TESTS:%=%.hex)) 20 | HEX_SIM := $(addprefix $(RUNTIME_REL_BUILD_DIR)/,$(TESTS:%=%.hex)) 21 | DUMP := $(addprefix $(BUILD_DIR)/,$(TESTS:%=%.dump)) 22 | 23 | RISCV_GCC_PREFIX ?= riscv32-unknown-elf- 24 | RISCV_GCC := $(RISCV_GCC_PREFIX)gcc 25 | RISCV_OBJDUMP ?= $(RISCV_GCC_PREFIX)objdump -D 26 | RISCV_OBJCOPY ?= $(RISCV_GCC__PREFIX)objcopy -O verilog 27 | RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles 28 | CFLAGS := -I$(RISCV_ISA_SRC_DIR)/../env/p -I$(RISCV_ISA_SRC_DIR)/macros/scalar -DASM -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI) -D__riscv_xlen=32 29 | #link file is a copy of $(RISCV_ISA_SRC_DIR)/../env/p/link.ld, with a 0 start address 30 | LDFLAGS := $(RISCV_GCC_OPTS) -Tlink.ld -march=rv32$(ARCH) -mabi=$(ABI) 31 | 32 | default: $(ELF) $(HEX) $(DUMP) hex_file_list 33 | 34 | hex_file_list: $(BUILD_DIR) 35 | @echo $(HEX_SIM) > $(BUILD_DIR)/hex_files.txt 36 | 37 | define compile_template 38 | $(OBJ_DIR)/$$(basename $(notdir $(SRC))).o: $$(SRC) | $(OBJ_DIR) 39 | $(RISCV_GCC) -c $$< $(CFLAGS) -o $$@ 40 | endef 41 | 42 | $(foreach SRC,$(S_FILES), $(eval $(compile_template))) 43 | 44 | $(BUILD_DIR): 45 | mkdir -p $(BUILD_DIR) 46 | 47 | $(OBJ_DIR) : $(BUILD_DIR) 48 | mkdir -p $(OBJ_DIR) 49 | 50 | $(BUILD_DIR)/%.elf: $(OBJ_DIR)/%.o | $(OBJ_DIR) 51 | $(RISCV_GCC) $^ $(LDFLAGS) -o $@ 52 | 53 | $(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf 54 | $(RISCV_OBJCOPY) $^ $@ 55 | 56 | $(BUILD_DIR)/%.dump: $(BUILD_DIR)/%.elf 57 | $(RISCV_OBJDUMP) $^ > $@ 58 | 59 | 60 | clean: 61 | rm -rf $(BUILD_DIR) 62 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/add.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 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01 40 02 63 18 D1 03 93 | B3 00 00 00 93 0E 00 00 93 01 50 02 63 90 D0 03 94 | 93 00 00 01 13 01 E0 01 33 80 20 00 93 0E 00 00 95 | 93 01 60 02 63 14 D0 01 63 1C 30 00 0F 00 F0 0F 96 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 97 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 98 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 99 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 101 | 00 00 00 00 00 102 | @00001000 103 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 104 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 105 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 106 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 107 | 00 00 00 00 00 00 00 00 108 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/addi.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 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01 10 00 60 | 73 00 00 00 73 10 00 C0 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 62 | @00001000 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 68 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/and.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 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12 00 93 02 20 00 E3 12 52 FE B7 1E 00 0F 68 | 93 8E 0E F0 93 01 20 01 63 16 DF 19 13 02 00 00 69 | 37 F1 F0 F0 13 01 01 0F B7 10 F0 0F 93 80 00 FF 70 | 13 00 00 00 33 FF 20 00 13 02 12 00 93 02 20 00 71 | E3 10 52 FE B7 0E F0 00 93 8E 0E 0F 93 01 30 01 72 | 63 1A DF 15 13 02 00 00 37 11 0F 0F 13 01 F1 F0 73 | B7 00 FF 00 93 80 F0 0F 13 00 00 00 13 00 00 00 74 | 33 FF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC 75 | B7 0E 0F 00 93 8E FE 00 93 01 40 01 63 1C DF 11 76 | 13 02 00 00 37 11 0F 0F 13 01 F1 F0 13 00 00 00 77 | B7 00 01 FF 93 80 00 F0 33 FF 20 00 13 02 12 00 78 | 93 02 20 00 E3 10 52 FE B7 1E 00 0F 93 8E 0E F0 79 | 93 01 50 01 63 10 DF 0F 13 02 00 00 37 F1 F0 F0 80 | 13 01 01 0F 13 00 00 00 B7 10 F0 0F 93 80 00 FF 81 | 13 00 00 00 33 FF 20 00 13 02 12 00 93 02 20 00 82 | E3 1E 52 FC B7 0E F0 00 93 8E 0E 0F 93 01 60 01 83 | 63 12 DF 0B 13 02 00 00 37 11 0F 0F 13 01 F1 F0 84 | 13 00 00 00 13 00 00 00 B7 00 FF 00 93 80 F0 0F 85 | 33 FF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC 86 | B7 0E 0F 00 93 8E FE 00 93 01 70 01 63 14 DF 07 87 | B7 00 01 FF 93 80 00 F0 33 71 10 00 93 0E 00 00 88 | 93 01 80 01 63 18 D1 05 B7 00 FF 00 93 80 F0 0F 89 | 33 F1 00 00 93 0E 00 00 93 01 90 01 63 1C D1 03 90 | B3 70 00 00 93 0E 00 00 93 01 A0 01 63 94 D0 03 91 | B7 10 11 11 93 80 10 11 37 21 22 22 13 01 21 22 92 | 33 F0 20 00 93 0E 00 00 93 01 B0 01 63 14 D0 01 93 | 63 1C 30 00 0F 00 F0 0F 63 80 01 00 93 91 11 00 94 | 93 E1 11 00 73 00 00 00 0F 00 F0 0F 93 01 10 00 95 | 73 00 00 00 73 10 00 C0 00 00 00 00 00 00 00 00 96 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 97 | 00 00 00 00 00 98 | @00001000 99 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 101 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 102 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 103 | 00 00 00 00 00 00 00 00 104 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/andi.hex: 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20 00 63 14 DF 1B B7 10 F0 0F 93 80 00 FF 20 | 13 FF 00 0F 93 0E 00 0F 93 01 30 00 63 18 DF 19 21 | B7 00 FF 00 93 80 F0 0F 13 FF F0 70 93 0E F0 00 22 | 93 01 40 00 63 1C DF 17 B7 F0 0F F0 93 80 F0 00 23 | 13 FF 00 0F 93 0E 00 00 93 01 50 00 63 10 DF 17 24 | B7 00 01 FF 93 80 00 F0 93 F0 00 0F 93 0E 00 00 25 | 93 01 60 00 63 94 D0 15 13 02 00 00 B7 10 F0 0F 26 | 93 80 00 FF 13 FF F0 70 13 03 0F 00 13 02 12 00 27 | 93 02 20 00 E3 14 52 FE 93 0E 00 70 93 01 70 00 28 | 63 1E D3 11 13 02 00 00 B7 00 FF 00 93 80 F0 0F 29 | 13 FF 00 0F 13 00 00 00 13 03 0F 00 13 02 12 00 30 | 93 02 20 00 E3 12 52 FE 93 0E 00 0F 93 01 80 00 31 | 63 16 D3 0F 13 02 00 00 B7 F0 0F F0 93 80 F0 00 32 | 13 FF F0 F0 13 00 00 00 13 00 00 00 13 03 0F 00 33 | 13 02 12 00 93 02 20 00 E3 10 52 FE B7 FE 0F F0 34 | 93 8E FE 00 93 01 90 00 63 1A D3 0B 13 02 00 00 35 | B7 10 F0 0F 93 80 00 FF 13 FF F0 70 13 02 12 00 36 | 93 02 20 00 E3 16 52 FE 93 0E 00 70 93 01 A0 00 37 | 63 16 DF 09 13 02 00 00 B7 00 FF 00 93 80 F0 0F 38 | 13 00 00 00 13 FF 00 0F 13 02 12 00 93 02 20 00 39 | E3 14 52 FE 93 0E 00 0F 93 01 B0 00 63 10 DF 07 40 | 13 02 00 00 B7 F0 0F F0 93 80 F0 00 13 00 00 00 41 | 13 00 00 00 13 FF F0 70 13 02 12 00 93 02 20 00 42 | E3 12 52 FE 93 0E F0 00 93 01 C0 00 63 18 DF 03 43 | 93 70 00 0F 93 0E 00 00 93 01 D0 00 63 90 D0 03 44 | B7 00 FF 00 93 80 F0 0F 13 F0 F0 70 93 0E 00 00 45 | 93 01 E0 00 63 14 D0 01 63 1C 30 00 0F 00 F0 0F 46 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 47 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 48 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 49 | 00 00 00 00 00 50 | @00001000 51 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 52 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 53 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 54 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 | 00 00 00 00 00 00 00 00 56 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/auipc.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 13 00 00 00 18 | 17 25 00 00 13 05 C5 71 EF 05 40 00 33 05 B5 40 19 | B7 2E 00 00 93 8E 0E 71 93 01 20 00 63 14 D5 03 20 | 17 E5 FF FF 13 05 C5 8F EF 05 40 00 33 05 B5 40 21 | B7 EE FF FF 93 8E 0E 8F 93 01 30 00 63 14 D5 01 22 | 63 1C 30 00 0F 00 F0 0F 63 80 01 00 93 91 11 00 23 | 93 E1 11 00 73 00 00 00 0F 00 F0 0F 93 01 10 00 24 | 73 00 00 00 73 10 00 C0 00 00 00 25 | @00001000 26 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 27 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 | 00 00 00 00 00 00 00 00 31 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/beq.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 01 20 00 18 | 93 00 00 00 13 01 00 00 63 86 20 00 63 18 30 2A 19 | 63 16 30 00 E3 8E 20 FE 63 12 30 2A 93 01 30 00 20 | 93 00 10 00 13 01 10 00 63 86 20 00 63 18 30 28 21 | 63 16 30 00 E3 8E 20 FE 63 12 30 28 93 01 40 00 22 | 93 00 F0 FF 13 01 F0 FF 63 86 20 00 63 18 30 26 23 | 63 16 30 00 E3 8E 20 FE 63 12 30 26 93 01 50 00 24 | 93 00 00 00 13 01 10 00 63 84 20 00 63 14 30 00 25 | 63 16 30 24 E3 8E 20 FE 93 01 60 00 93 00 10 00 26 | 13 01 00 00 63 84 20 00 63 14 30 00 63 18 30 22 27 | E3 8E 20 FE 93 01 70 00 93 00 F0 FF 13 01 10 00 28 | 63 84 20 00 63 14 30 00 63 1A 30 20 E3 8E 20 FE 29 | 93 01 80 00 93 00 10 00 13 01 F0 FF 63 84 20 00 30 | 63 14 30 00 63 1C 30 1E E3 8E 20 FE 93 01 90 00 31 | 13 02 00 00 93 00 00 00 13 01 F0 FF 63 80 20 1E 32 | 13 02 12 00 93 02 20 00 E3 16 52 FE 93 01 A0 00 33 | 13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 34 | 63 8E 20 1A 13 02 12 00 93 02 20 00 E3 14 52 FE 35 | 93 01 B0 00 13 02 00 00 93 00 00 00 13 01 F0 FF 36 | 13 00 00 00 13 00 00 00 63 8A 20 18 13 02 12 00 37 | 93 02 20 00 E3 12 52 FE 93 01 C0 00 13 02 00 00 38 | 93 00 00 00 13 00 00 00 13 01 F0 FF 63 88 20 16 39 | 13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 D0 00 40 | 13 02 00 00 93 00 00 00 13 00 00 00 13 01 F0 FF 41 | 13 00 00 00 63 84 20 14 13 02 12 00 93 02 20 00 42 | E3 12 52 FE 93 01 E0 00 13 02 00 00 93 00 00 00 43 | 13 00 00 00 13 00 00 00 13 01 F0 FF 63 80 20 12 44 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 F0 00 45 | 13 02 00 00 93 00 00 00 13 01 F0 FF 63 80 20 10 46 | 13 02 12 00 93 02 20 00 E3 16 52 FE 93 01 00 01 47 | 13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 48 | 63 8E 20 0C 13 02 12 00 93 02 20 00 E3 14 52 FE 49 | 93 01 10 01 13 02 00 00 93 00 00 00 13 01 F0 FF 50 | 13 00 00 00 13 00 00 00 63 8A 20 0A 13 02 12 00 51 | 93 02 20 00 E3 12 52 FE 93 01 20 01 13 02 00 00 52 | 93 00 00 00 13 00 00 00 13 01 F0 FF 63 88 20 08 53 | 13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 30 01 54 | 13 02 00 00 93 00 00 00 13 00 00 00 13 01 F0 FF 55 | 13 00 00 00 63 84 20 06 13 02 12 00 93 02 20 00 56 | E3 12 52 FE 93 01 40 01 13 02 00 00 93 00 00 00 57 | 13 00 00 00 13 00 00 00 13 01 F0 FF 63 80 20 04 58 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 00 10 00 59 | 63 0A 00 00 93 80 10 00 93 80 10 00 93 80 10 00 60 | 93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 61 | 93 01 50 01 63 94 D0 01 63 1C 30 00 0F 00 F0 0F 62 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 63 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 66 | @00001000 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 69 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 71 | 00 00 00 00 00 00 00 00 72 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/bge.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 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93 02 20 00 48 | E3 12 52 FE 93 01 10 01 13 02 00 00 93 00 F0 FF 49 | 13 00 00 00 13 00 00 00 13 01 00 00 63 D0 20 12 50 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 20 01 51 | 13 02 00 00 93 00 F0 FF 13 01 00 00 63 D0 20 10 52 | 13 02 12 00 93 02 20 00 E3 16 52 FE 93 01 30 01 53 | 13 02 00 00 93 00 F0 FF 13 01 00 00 13 00 00 00 54 | 63 DE 20 0C 13 02 12 00 93 02 20 00 E3 14 52 FE 55 | 93 01 40 01 13 02 00 00 93 00 F0 FF 13 01 00 00 56 | 13 00 00 00 13 00 00 00 63 DA 20 0A 13 02 12 00 57 | 93 02 20 00 E3 12 52 FE 93 01 50 01 13 02 00 00 58 | 93 00 F0 FF 13 00 00 00 13 01 00 00 63 D8 20 08 59 | 13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 60 01 60 | 13 02 00 00 93 00 F0 FF 13 00 00 00 13 01 00 00 61 | 13 00 00 00 63 D4 20 06 13 02 12 00 93 02 20 00 62 | E3 12 52 FE 93 01 70 01 13 02 00 00 93 00 F0 FF 63 | 13 00 00 00 13 00 00 00 13 01 00 00 63 D0 20 04 64 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 00 10 00 65 | 63 DA 00 00 93 80 10 00 93 80 10 00 93 80 10 00 66 | 93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 67 | 93 01 80 01 63 94 D0 01 63 1C 30 00 0F 00 F0 0F 68 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 69 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 71 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 72 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 73 | 00 00 00 00 00 74 | @00001000 75 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 76 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 77 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 78 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 79 | 00 00 00 00 00 00 00 00 80 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/bgeu.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 01 20 00 18 | 93 00 00 00 13 01 00 00 63 F6 20 00 63 12 30 34 19 | 63 16 30 00 E3 FE 20 FE 63 1C 30 32 93 01 30 00 20 | 93 00 10 00 13 01 10 00 63 F6 20 00 63 12 30 32 21 | 63 16 30 00 E3 FE 20 FE 63 1C 30 30 93 01 40 00 22 | 93 00 F0 FF 13 01 F0 FF 63 F6 20 00 63 12 30 30 23 | 63 16 30 00 E3 FE 20 FE 63 1C 30 2E 93 01 50 00 24 | 93 00 10 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62 | 93 02 20 00 E3 12 52 FE 93 01 60 01 13 02 00 00 63 | B7 00 00 F0 93 80 F0 FF 13 00 00 00 37 01 00 F0 64 | 13 00 00 00 63 F6 20 06 13 02 12 00 93 02 20 00 65 | E3 10 52 FE 93 01 70 01 13 02 00 00 B7 00 00 F0 66 | 93 80 F0 FF 13 00 00 00 13 00 00 00 37 01 00 F0 67 | 63 F0 20 04 13 02 12 00 93 02 20 00 E3 10 52 FE 68 | 93 00 10 00 63 FA 00 00 93 80 10 00 93 80 10 00 69 | 93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 70 | 93 0E 30 00 93 01 80 01 63 94 D0 01 63 1C 30 00 71 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 72 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 | 73 10 00 C0 00 74 | @00001000 75 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 76 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 77 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 78 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 79 | 00 00 00 00 00 00 00 00 80 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/blt.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 01 20 00 18 | 93 00 00 00 13 01 10 00 63 C6 20 00 63 18 30 2A 19 | 63 16 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00 57 | 13 00 00 00 13 00 00 00 13 01 F0 FF 63 C0 20 04 58 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 00 10 00 59 | 63 4A 10 00 93 80 10 00 93 80 10 00 93 80 10 00 60 | 93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 61 | 93 01 50 01 63 94 D0 01 63 1C 30 00 0F 00 F0 0F 62 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 63 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 66 | @00001000 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 69 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 71 | 00 00 00 00 00 00 00 00 72 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/bltu.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 01 20 00 18 | 93 00 00 00 13 01 10 00 63 E6 20 00 63 12 30 2E 19 | 63 16 30 00 E3 EE 20 FE 63 1C 30 2C 93 01 30 00 20 | 93 00 E0 FF 13 01 F0 FF 63 E6 20 00 63 12 30 2C 21 | 63 16 30 00 E3 EE 20 FE 63 1C 30 2A 93 01 40 00 22 | 93 00 00 00 13 01 F0 FF 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00 00 B7 00 00 F0 13 00 00 00 42 | 37 01 00 F0 13 01 F1 FF 13 00 00 00 63 E2 20 16 43 | 13 02 12 00 93 02 20 00 E3 10 52 FE 93 01 E0 00 44 | 13 02 00 00 B7 00 00 F0 13 00 00 00 13 00 00 00 45 | 37 01 00 F0 13 01 F1 FF 63 EC 20 12 13 02 12 00 46 | 93 02 20 00 E3 10 52 FE 93 01 F0 00 13 02 00 00 47 | B7 00 00 F0 37 01 00 F0 13 01 F1 FF 63 EA 20 10 48 | 13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 00 01 49 | 13 02 00 00 B7 00 00 F0 37 01 00 F0 13 01 F1 FF 50 | 13 00 00 00 63 E6 20 0E 13 02 12 00 93 02 20 00 51 | E3 12 52 FE 93 01 10 01 13 02 00 00 B7 00 00 F0 52 | 37 01 00 F0 13 01 F1 FF 13 00 00 00 13 00 00 00 53 | 63 E0 20 0C 13 02 12 00 93 02 20 00 E3 10 52 FE 54 | 93 01 20 01 13 02 00 00 B7 00 00 F0 13 00 00 00 55 | 37 01 00 F0 13 01 F1 FF 63 EC 20 08 13 02 12 00 56 | 93 02 20 00 E3 12 52 FE 93 01 30 01 13 02 00 00 57 | B7 00 00 F0 13 00 00 00 37 01 00 F0 13 01 F1 FF 58 | 13 00 00 00 63 E6 20 06 13 02 12 00 93 02 20 00 59 | E3 10 52 FE 93 01 40 01 13 02 00 00 B7 00 00 F0 60 | 13 00 00 00 13 00 00 00 37 01 00 F0 13 01 F1 FF 61 | 63 E0 20 04 13 02 12 00 93 02 20 00 E3 10 52 FE 62 | 93 00 10 00 63 6A 10 00 93 80 10 00 93 80 10 00 63 | 93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 64 | 93 0E 30 00 93 01 50 01 63 94 D0 01 63 1C 30 00 65 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 66 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 67 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 69 | 00 00 00 00 00 70 | @00001000 71 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 72 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 73 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 74 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 75 | 00 00 00 00 00 00 00 00 76 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/bne.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 01 20 00 18 | 93 00 00 00 13 01 10 00 63 96 20 00 63 1A 30 2A 19 | 63 16 30 00 E3 9E 20 FE 63 14 30 2A 93 01 30 00 20 | 93 00 10 00 13 01 00 00 63 96 20 00 63 1A 30 28 21 | 63 16 30 00 E3 9E 20 FE 63 14 30 28 93 01 40 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00 00 00 41 | 13 01 00 00 13 00 00 00 63 94 20 14 13 02 12 00 42 | 93 02 20 00 E3 12 52 FE 93 01 E0 00 13 02 00 00 43 | 93 00 00 00 13 00 00 00 13 00 00 00 13 01 00 00 44 | 63 90 20 12 13 02 12 00 93 02 20 00 E3 12 52 FE 45 | 93 01 F0 00 13 02 00 00 93 00 00 00 13 01 00 00 46 | 63 90 20 10 13 02 12 00 93 02 20 00 E3 16 52 FE 47 | 93 01 00 01 13 02 00 00 93 00 00 00 13 01 00 00 48 | 13 00 00 00 63 9E 20 0C 13 02 12 00 93 02 20 00 49 | E3 14 52 FE 93 01 10 01 13 02 00 00 93 00 00 00 50 | 13 01 00 00 13 00 00 00 13 00 00 00 63 9A 20 0A 51 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 20 01 52 | 13 02 00 00 93 00 00 00 13 00 00 00 13 01 00 00 53 | 63 98 20 08 13 02 12 00 93 02 20 00 E3 14 52 FE 54 | 93 01 30 01 13 02 00 00 93 00 00 00 13 00 00 00 55 | 13 01 00 00 13 00 00 00 63 94 20 06 13 02 12 00 56 | 93 02 20 00 E3 12 52 FE 93 01 40 01 13 02 00 00 57 | 93 00 00 00 13 00 00 00 13 00 00 00 13 01 00 00 58 | 63 90 20 04 13 02 12 00 93 02 20 00 E3 12 52 FE 59 | 93 00 10 00 63 9A 00 00 93 80 10 00 93 80 10 00 60 | 93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 61 | 93 0E 30 00 93 01 50 01 63 94 D0 01 63 1C 30 00 62 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 63 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 64 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 66 | @00001000 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 69 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 71 | 00 00 00 00 00 00 00 00 72 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/fence_i.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 06 F0 06 18 | 17 25 00 00 03 15 05 F0 97 25 00 00 83 95 A5 EF 19 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 20 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 21 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 22 | 97 02 00 00 23 9A A2 00 97 02 00 00 23 97 B2 00 23 | 0F 10 00 00 93 86 E6 0D 13 00 00 00 93 0E C0 1B 24 | 93 01 20 00 63 9A D6 07 13 07 40 06 13 07 F7 FF 25 | E3 1E 07 FE 97 02 00 00 23 96 A2 04 97 02 00 00 26 | 23 93 B2 04 0F 10 00 00 13 00 00 00 13 00 00 00 27 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 28 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 29 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 30 | 93 86 B6 22 13 00 00 00 93 0E 90 30 93 01 30 00 31 | 63 94 D6 01 63 1C 30 00 0F 00 F0 0F 63 80 01 00 32 | 93 91 11 00 93 E1 11 00 73 00 00 00 0F 00 F0 0F 33 | 93 01 10 00 73 00 00 00 73 10 00 C0 00 00 00 00 34 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 35 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 36 | @00001000 37 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 38 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 39 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 42 | @00002000 43 | 93 86 D6 14 00 00 00 00 00 00 00 00 00 00 00 00 44 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/hex_files.txt: -------------------------------------------------------------------------------- 1 | ../riscv_tests_hexgen/build/addi.hex ../riscv_tests_hexgen/build/add.hex ../riscv_tests_hexgen/build/andi.hex ../riscv_tests_hexgen/build/and.hex ../riscv_tests_hexgen/build/auipc.hex ../riscv_tests_hexgen/build/beq.hex ../riscv_tests_hexgen/build/bge.hex ../riscv_tests_hexgen/build/bgeu.hex ../riscv_tests_hexgen/build/blt.hex ../riscv_tests_hexgen/build/bltu.hex ../riscv_tests_hexgen/build/bne.hex ../riscv_tests_hexgen/build/fence_i.hex ../riscv_tests_hexgen/build/jalr.hex ../riscv_tests_hexgen/build/jal.hex ../riscv_tests_hexgen/build/lb.hex ../riscv_tests_hexgen/build/lbu.hex ../riscv_tests_hexgen/build/lh.hex ../riscv_tests_hexgen/build/lhu.hex ../riscv_tests_hexgen/build/lui.hex ../riscv_tests_hexgen/build/lw.hex ../riscv_tests_hexgen/build/ori.hex ../riscv_tests_hexgen/build/or.hex ../riscv_tests_hexgen/build/sb.hex ../riscv_tests_hexgen/build/sh.hex ../riscv_tests_hexgen/build/simple.hex ../riscv_tests_hexgen/build/slli.hex ../riscv_tests_hexgen/build/sll.hex ../riscv_tests_hexgen/build/slti.hex ../riscv_tests_hexgen/build/sltiu.hex ../riscv_tests_hexgen/build/slt.hex ../riscv_tests_hexgen/build/sltu.hex ../riscv_tests_hexgen/build/srai.hex ../riscv_tests_hexgen/build/sra.hex ../riscv_tests_hexgen/build/srli.hex ../riscv_tests_hexgen/build/srl.hex ../riscv_tests_hexgen/build/sub.hex ../riscv_tests_hexgen/build/sw.hex ../riscv_tests_hexgen/build/xori.hex ../riscv_tests_hexgen/build/xor.hex 2 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/jal.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 01 20 00 18 | 93 00 00 00 6F 02 00 01 13 00 00 00 13 00 00 00 19 | 6F 00 00 04 17 01 00 00 13 01 41 FF 63 1A 41 02 20 | 93 00 10 00 6F 00 40 01 93 80 10 00 93 80 10 00 21 | 93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 22 | 93 0E 30 00 93 01 30 00 63 94 D0 01 63 1C 30 00 23 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 24 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 25 | 73 10 00 C0 00 26 | @00001000 27 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 31 | 00 00 00 00 00 00 00 00 32 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/jalr.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 01 20 00 18 | 93 02 00 00 17 03 00 00 13 03 03 01 E7 02 03 00 19 | 6F 00 00 0C 17 03 00 00 13 03 C3 FF 63 9A 62 0A 20 | 93 01 40 00 13 02 00 00 17 03 00 00 13 03 03 01 21 | E7 09 03 00 63 1E 30 08 13 02 12 00 93 02 20 00 22 | E3 14 52 FE 93 01 50 00 13 02 00 00 17 03 00 00 23 | 13 03 43 01 13 00 00 00 E7 09 03 00 63 1A 30 06 24 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 60 00 25 | 13 02 00 00 17 03 00 00 13 03 83 01 13 00 00 00 26 | 13 00 00 00 E7 09 03 00 63 14 30 04 13 02 12 00 27 | 93 02 20 00 E3 10 52 FE 93 02 10 00 17 03 00 00 28 | 13 03 C3 01 67 00 C3 FF 93 82 12 00 93 82 12 00 29 | 93 82 12 00 93 82 12 00 93 82 12 00 93 82 12 00 30 | 93 0E 40 00 93 01 70 00 63 94 D2 01 63 1C 30 00 31 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 32 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 33 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 34 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 35 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 36 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 37 | 00 00 38 | @00001000 39 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 41 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 42 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 43 | 00 00 00 00 00 00 00 00 44 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/lb.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 97 20 00 00 18 | 93 80 40 F0 03 8F 00 00 93 0E F0 FF 93 01 20 00 19 | 63 1C DF 23 97 20 00 00 93 80 C0 EE 03 8F 10 00 20 | 93 0E 00 00 93 01 30 00 63 10 DF 23 97 20 00 00 21 | 93 80 40 ED 03 8F 20 00 93 0E 00 FF 93 01 40 00 22 | 63 14 DF 21 97 20 00 00 93 80 C0 EB 03 8F 30 00 23 | 93 0E F0 00 93 01 50 00 63 18 DF 1F 97 20 00 00 24 | 93 80 70 EA 03 8F D0 FF 93 0E F0 FF 93 01 60 00 25 | 63 1C DF 1D 97 20 00 00 93 80 F0 E8 03 8F E0 FF 26 | 93 0E 00 00 93 01 70 00 63 10 DF 1D 97 20 00 00 27 | 93 80 70 E7 03 8F F0 FF 93 0E 00 FF 93 01 80 00 28 | 63 14 DF 1B 97 20 00 00 93 80 F0 E5 03 8F 00 00 29 | 93 0E F0 00 93 01 90 00 63 18 DF 19 97 20 00 00 30 | 93 80 40 E4 93 80 00 FE 83 82 00 02 93 0E F0 FF 31 | 93 01 A0 00 63 9A D2 17 97 20 00 00 93 80 80 E2 32 | 93 80 A0 FF 83 82 70 00 93 0E 00 00 93 01 B0 00 33 | 63 9C D2 15 93 01 C0 00 13 02 00 00 97 20 00 00 34 | 93 80 50 E0 03 8F 10 00 13 03 0F 00 93 0E 00 FF 35 | 63 1C D3 13 13 02 12 00 93 02 20 00 E3 10 52 FE 36 | 93 01 D0 00 13 02 00 00 97 20 00 00 93 80 A0 DD 37 | 03 8F 10 00 13 00 00 00 13 03 0F 00 93 0E F0 00 38 | 63 14 D3 11 13 02 12 00 93 02 20 00 E3 1E 52 FC 39 | 93 01 E0 00 13 02 00 00 97 20 00 00 93 80 80 DA 40 | 03 8F 10 00 13 00 00 00 13 00 00 00 13 03 0F 00 41 | 93 0E 00 00 63 1A D3 0D 13 02 12 00 93 02 20 00 42 | E3 1C 52 FC 93 01 F0 00 13 02 00 00 97 20 00 00 43 | 93 80 50 D7 03 8F 10 00 93 0E 00 FF 63 16 DF 0B 44 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 00 01 45 | 13 02 00 00 97 20 00 00 93 80 E0 D4 13 00 00 00 46 | 03 8F 10 00 93 0E F0 00 63 10 DF 09 13 02 12 00 47 | 93 02 20 00 E3 10 52 FE 93 01 10 01 13 02 00 00 48 | 97 20 00 00 93 80 00 D2 13 00 00 00 13 00 00 00 49 | 03 8F 10 00 93 0E 00 00 63 18 DF 05 13 02 12 00 50 | 93 02 20 00 E3 1E 52 FC 97 22 00 00 93 82 82 CF 51 | 03 81 02 00 13 01 20 00 93 0E 20 00 93 01 20 01 52 | 63 14 D1 03 97 22 00 00 93 82 C2 CD 03 81 02 00 53 | 13 00 00 00 13 01 20 00 93 0E 20 00 93 01 30 01 54 | 63 14 D1 01 63 1C 30 00 0F 00 F0 0F 63 80 01 00 55 | 93 91 11 00 93 E1 11 00 73 00 00 00 0F 00 F0 0F 56 | 93 01 10 00 73 00 00 00 73 10 00 C0 00 00 00 00 57 | 00 00 00 00 00 58 | @00001000 59 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 63 | 00 00 00 00 00 00 00 00 64 | @00002000 65 | FF 00 F0 0F 00 00 00 00 00 00 00 00 00 00 00 00 66 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/lbu.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 97 20 00 00 18 | 93 80 40 F0 03 CF 00 00 93 0E F0 0F 93 01 20 00 19 | 63 1C DF 23 97 20 00 00 93 80 C0 EE 03 CF 10 00 20 | 93 0E 00 00 93 01 30 00 63 10 DF 23 97 20 00 00 21 | 93 80 40 ED 03 CF 20 00 93 0E 00 0F 93 01 40 00 22 | 63 14 DF 21 97 20 00 00 93 80 C0 EB 03 CF 30 00 23 | 93 0E F0 00 93 01 50 00 63 18 DF 1F 97 20 00 00 24 | 93 80 70 EA 03 CF D0 FF 93 0E F0 0F 93 01 60 00 25 | 63 1C DF 1D 97 20 00 00 93 80 F0 E8 03 CF E0 FF 26 | 93 0E 00 00 93 01 70 00 63 10 DF 1D 97 20 00 00 27 | 93 80 70 E7 03 CF F0 FF 93 0E 00 0F 93 01 80 00 28 | 63 14 DF 1B 97 20 00 00 93 80 F0 E5 03 CF 00 00 29 | 93 0E F0 00 93 01 90 00 63 18 DF 19 97 20 00 00 30 | 93 80 40 E4 93 80 00 FE 83 C2 00 02 93 0E F0 0F 31 | 93 01 A0 00 63 9A D2 17 97 20 00 00 93 80 80 E2 32 | 93 80 A0 FF 83 C2 70 00 93 0E 00 00 93 01 B0 00 33 | 63 9C D2 15 93 01 C0 00 13 02 00 00 97 20 00 00 34 | 93 80 50 E0 03 CF 10 00 13 03 0F 00 93 0E 00 0F 35 | 63 1C D3 13 13 02 12 00 93 02 20 00 E3 10 52 FE 36 | 93 01 D0 00 13 02 00 00 97 20 00 00 93 80 A0 DD 37 | 03 CF 10 00 13 00 00 00 13 03 0F 00 93 0E F0 00 38 | 63 14 D3 11 13 02 12 00 93 02 20 00 E3 1E 52 FC 39 | 93 01 E0 00 13 02 00 00 97 20 00 00 93 80 80 DA 40 | 03 CF 10 00 13 00 00 00 13 00 00 00 13 03 0F 00 41 | 93 0E 00 00 63 1A D3 0D 13 02 12 00 93 02 20 00 42 | E3 1C 52 FC 93 01 F0 00 13 02 00 00 97 20 00 00 43 | 93 80 50 D7 03 CF 10 00 93 0E 00 0F 63 16 DF 0B 44 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 00 01 45 | 13 02 00 00 97 20 00 00 93 80 E0 D4 13 00 00 00 46 | 03 CF 10 00 93 0E F0 00 63 10 DF 09 13 02 12 00 47 | 93 02 20 00 E3 10 52 FE 93 01 10 01 13 02 00 00 48 | 97 20 00 00 93 80 00 D2 13 00 00 00 13 00 00 00 49 | 03 CF 10 00 93 0E 00 00 63 18 DF 05 13 02 12 00 50 | 93 02 20 00 E3 1E 52 FC 97 22 00 00 93 82 82 CF 51 | 03 C1 02 00 13 01 20 00 93 0E 20 00 93 01 20 01 52 | 63 14 D1 03 97 22 00 00 93 82 C2 CD 03 C1 02 00 53 | 13 00 00 00 13 01 20 00 93 0E 20 00 93 01 30 01 54 | 63 14 D1 01 63 1C 30 00 0F 00 F0 0F 63 80 01 00 55 | 93 91 11 00 93 E1 11 00 73 00 00 00 0F 00 F0 0F 56 | 93 01 10 00 73 00 00 00 73 10 00 C0 00 00 00 00 57 | 00 00 00 00 00 58 | @00001000 59 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 62 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 63 | 00 00 00 00 00 00 00 00 64 | @00002000 65 | FF 00 F0 0F 00 00 00 00 00 00 00 00 00 00 00 00 66 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/lh.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 97 20 00 00 18 | 93 80 40 F0 03 9F 00 00 93 0E F0 0F 93 01 20 00 19 | 63 1C DF 25 97 20 00 00 93 80 C0 EE 03 9F 20 00 20 | 93 0E 00 F0 93 01 30 00 63 10 DF 25 97 20 00 00 21 | 93 80 40 ED 03 9F 40 00 B7 1E 00 00 93 8E 0E FF 22 | 93 01 40 00 63 12 DF 23 97 20 00 00 93 80 80 EB 23 | 03 9F 60 00 B7 FE FF FF 93 8E FE 00 93 01 50 00 24 | 63 14 DF 21 97 20 00 00 93 80 20 EA 03 9F A0 FF 25 | 93 0E F0 0F 93 01 60 00 63 18 DF 1F 97 20 00 00 26 | 93 80 A0 E8 03 9F C0 FF 93 0E 00 F0 93 01 70 00 27 | 63 1C DF 1D 97 20 00 00 93 80 20 E7 03 9F E0 FF 28 | B7 1E 00 00 93 8E 0E FF 93 01 80 00 63 1E DF 1B 29 | 97 20 00 00 93 80 60 E5 03 9F 00 00 B7 FE FF FF 30 | 93 8E FE 00 93 01 90 00 63 10 DF 1B 97 20 00 00 31 | 93 80 40 E3 93 80 00 FE 83 92 00 02 93 0E F0 0F 32 | 93 01 A0 00 63 92 D2 19 97 20 00 00 93 80 80 E1 33 | 93 80 B0 FF 83 92 70 00 93 0E 00 F0 93 01 B0 00 34 | 63 94 D2 17 93 01 C0 00 13 02 00 00 97 20 00 00 35 | 93 80 60 DF 03 9F 20 00 13 03 0F 00 B7 1E 00 00 36 | 93 8E 0E FF 63 12 D3 15 13 02 12 00 93 02 20 00 37 | E3 1E 52 FC 93 01 D0 00 13 02 00 00 97 20 00 00 38 | 93 80 80 DC 03 9F 20 00 13 00 00 00 13 03 0F 00 39 | B7 FE FF FF 93 8E FE 00 63 18 D3 11 13 02 12 00 40 | 93 02 20 00 E3 1C 52 FC 93 01 E0 00 13 02 00 00 41 | 97 20 00 00 93 80 00 D9 03 9F 20 00 13 00 00 00 42 | 13 00 00 00 13 03 0F 00 93 0E 00 F0 63 1E D3 0D 43 | 13 02 12 00 93 02 20 00 E3 1C 52 FC 93 01 F0 00 44 | 13 02 00 00 97 20 00 00 93 80 E0 D5 03 9F 20 00 45 | B7 1E 00 00 93 8E 0E FF 63 18 DF 0B 13 02 12 00 46 | 93 02 20 00 E3 10 52 FE 93 01 00 01 13 02 00 00 47 | 97 20 00 00 93 80 40 D3 13 00 00 00 03 9F 20 00 48 | B7 FE FF FF 93 8E FE 00 63 10 DF 09 13 02 12 00 49 | 93 02 20 00 E3 1E 52 FC 93 01 10 01 13 02 00 00 50 | 97 20 00 00 93 80 00 D0 13 00 00 00 13 00 00 00 51 | 03 9F 20 00 93 0E 00 F0 63 18 DF 05 13 02 12 00 52 | 93 02 20 00 E3 1E 52 FC 97 22 00 00 93 82 82 CD 53 | 03 91 02 00 13 01 20 00 93 0E 20 00 93 01 20 01 54 | 63 14 D1 03 97 22 00 00 93 82 C2 CB 03 91 02 00 55 | 13 00 00 00 13 01 20 00 93 0E 20 00 93 01 30 01 56 | 63 14 D1 01 63 1C 30 00 0F 00 F0 0F 63 80 01 00 57 | 93 91 11 00 93 E1 11 00 73 00 00 00 0F 00 F0 0F 58 | 93 01 10 00 73 00 00 00 73 10 00 C0 00 00 00 00 59 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 62 | @00001000 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 68 | @00002000 69 | FF 00 00 FF F0 0F 0F F0 00 00 00 00 00 00 00 00 70 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/lhu.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 97 20 00 00 18 | 93 80 40 F0 03 DF 00 00 93 0E F0 0F 93 01 20 00 19 | 63 16 DF 27 97 20 00 00 93 80 C0 EE 03 DF 20 00 20 | B7 0E 01 00 93 8E 0E F0 93 01 30 00 63 18 DF 25 21 | 97 20 00 00 93 80 00 ED 03 DF 40 00 B7 1E 00 00 22 | 93 8E 0E FF 93 01 40 00 63 1A DF 23 97 20 00 00 23 | 93 80 40 EB 03 DF 60 00 B7 FE 00 00 93 8E FE 00 24 | 93 01 50 00 63 1C DF 21 97 20 00 00 93 80 E0 E9 25 | 03 DF A0 FF 93 0E F0 0F 93 01 60 00 63 10 DF 21 26 | 97 20 00 00 93 80 60 E8 03 DF C0 FF B7 0E 01 00 27 | 93 8E 0E F0 93 01 70 00 63 12 DF 1F 97 20 00 00 28 | 93 80 A0 E6 03 DF E0 FF B7 1E 00 00 93 8E 0E FF 29 | 93 01 80 00 63 14 DF 1D 97 20 00 00 93 80 E0 E4 30 | 03 DF 00 00 B7 FE 00 00 93 8E FE 00 93 01 90 00 31 | 63 16 DF 1B 97 20 00 00 93 80 C0 E2 93 80 00 FE 32 | 83 D2 00 02 93 0E F0 0F 93 01 A0 00 63 98 D2 19 33 | 97 20 00 00 93 80 00 E1 93 80 B0 FF 83 D2 70 00 34 | B7 0E 01 00 93 8E 0E F0 93 01 B0 00 63 98 D2 17 35 | 93 01 C0 00 13 02 00 00 97 20 00 00 93 80 A0 DE 36 | 03 DF 20 00 13 03 0F 00 B7 1E 00 00 93 8E 0E FF 37 | 63 16 D3 15 13 02 12 00 93 02 20 00 E3 1E 52 FC 38 | 93 01 D0 00 13 02 00 00 97 20 00 00 93 80 C0 DB 39 | 03 DF 20 00 13 00 00 00 13 03 0F 00 B7 FE 00 00 40 | 93 8E FE 00 63 1C D3 11 13 02 12 00 93 02 20 00 41 | E3 1C 52 FC 93 01 E0 00 13 02 00 00 97 20 00 00 42 | 93 80 40 D8 03 DF 20 00 13 00 00 00 13 00 00 00 43 | 13 03 0F 00 B7 0E 01 00 93 8E 0E F0 63 10 D3 0F 44 | 13 02 12 00 93 02 20 00 E3 1A 52 FC 93 01 F0 00 45 | 13 02 00 00 97 20 00 00 93 80 E0 D4 03 DF 20 00 46 | B7 1E 00 00 93 8E 0E FF 63 1A DF 0B 13 02 12 00 47 | 93 02 20 00 E3 10 52 FE 93 01 00 01 13 02 00 00 48 | 97 20 00 00 93 80 40 D2 13 00 00 00 03 DF 20 00 49 | B7 FE 00 00 93 8E FE 00 63 12 DF 09 13 02 12 00 50 | 93 02 20 00 E3 1E 52 FC 93 01 10 01 13 02 00 00 51 | 97 20 00 00 93 80 00 CF 13 00 00 00 13 00 00 00 52 | 03 DF 20 00 B7 0E 01 00 93 8E 0E F0 63 18 DF 05 53 | 13 02 12 00 93 02 20 00 E3 1C 52 FC 97 22 00 00 54 | 93 82 42 CC 03 D1 02 00 13 01 20 00 93 0E 20 00 55 | 93 01 20 01 63 14 D1 03 97 22 00 00 93 82 82 CA 56 | 03 D1 02 00 13 00 00 00 13 01 20 00 93 0E 20 00 57 | 93 01 30 01 63 14 D1 01 63 1C 30 00 0F 00 F0 0F 58 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 59 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 62 | @00001000 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 68 | @00002000 69 | FF 00 00 FF F0 0F 0F F0 00 00 00 00 00 00 00 00 70 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/lui.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 B7 00 00 00 18 | 93 0E 00 00 93 01 20 00 63 9A D0 05 B7 F0 FF FF 19 | 93 D0 10 40 93 0E 00 80 93 01 30 00 63 90 D0 05 20 | B7 F0 FF 7F 93 D0 40 41 93 0E F0 7F 93 01 40 00 21 | 63 96 D0 03 B7 00 00 80 93 D0 40 41 93 0E 00 80 22 | 93 01 50 00 63 9C D0 01 37 00 00 80 93 0E 00 00 23 | 93 01 60 00 63 14 D0 01 63 1C 30 00 0F 00 F0 0F 24 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 25 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 26 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 27 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 29 | 00 00 00 00 00 30 | @00001000 31 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 32 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 33 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 34 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 35 | 00 00 00 00 00 00 00 00 36 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/lw.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 97 20 00 00 18 | 93 80 40 F0 03 AF 00 00 B7 0E FF 00 93 8E FE 0F 19 | 93 01 20 00 63 1A DF 27 97 20 00 00 93 80 80 EE 20 | 03 AF 40 00 B7 0E 01 FF 93 8E 0E F0 93 01 30 00 21 | 63 1C DF 25 97 20 00 00 93 80 C0 EC 03 AF 80 00 22 | B7 1E F0 0F 93 8E 0E FF 93 01 40 00 63 1E DF 23 23 | 97 20 00 00 93 80 00 EB 03 AF C0 00 B7 FE 0F F0 24 | 93 8E FE 00 93 01 50 00 63 10 DF 23 97 20 00 00 25 | 93 80 00 EA 03 AF 40 FF B7 0E FF 00 93 8E FE 0F 26 | 93 01 60 00 63 12 DF 21 97 20 00 00 93 80 40 E8 27 | 03 AF 80 FF B7 0E 01 FF 93 8E 0E F0 93 01 70 00 28 | 63 14 DF 1F 97 20 00 00 93 80 80 E6 03 AF C0 FF 29 | B7 1E F0 0F 93 8E 0E FF 93 01 80 00 63 16 DF 1D 30 | 97 20 00 00 93 80 C0 E4 03 AF 00 00 B7 FE 0F F0 31 | 93 8E FE 00 93 01 90 00 63 18 DF 1B 97 20 00 00 32 | 93 80 40 E2 93 80 00 FE 83 A2 00 02 B7 0E FF 00 33 | 93 8E FE 0F 93 01 A0 00 63 98 D2 19 97 20 00 00 34 | 93 80 40 E0 93 80 D0 FF 83 A2 70 00 B7 0E 01 FF 35 | 93 8E 0E F0 93 01 B0 00 63 98 D2 17 93 01 C0 00 36 | 13 02 00 00 97 20 00 00 93 80 00 DE 03 AF 40 00 37 | 13 03 0F 00 B7 1E F0 0F 93 8E 0E FF 63 16 D3 15 38 | 13 02 12 00 93 02 20 00 E3 1E 52 FC 93 01 D0 00 39 | 13 02 00 00 97 20 00 00 93 80 40 DB 03 AF 40 00 40 | 13 00 00 00 13 03 0F 00 B7 FE 0F F0 93 8E FE 00 41 | 63 1C D3 11 13 02 12 00 93 02 20 00 E3 1C 52 FC 42 | 93 01 E0 00 13 02 00 00 97 20 00 00 93 80 80 D7 43 | 03 AF 40 00 13 00 00 00 13 00 00 00 13 03 0F 00 44 | B7 0E 01 FF 93 8E 0E F0 63 10 D3 0F 13 02 12 00 45 | 93 02 20 00 E3 1A 52 FC 93 01 F0 00 13 02 00 00 46 | 97 20 00 00 93 80 40 D4 03 AF 40 00 B7 1E F0 0F 47 | 93 8E 0E FF 63 1A DF 0B 13 02 12 00 93 02 20 00 48 | E3 10 52 FE 93 01 00 01 13 02 00 00 97 20 00 00 49 | 93 80 C0 D1 13 00 00 00 03 AF 40 00 B7 FE 0F F0 50 | 93 8E FE 00 63 12 DF 09 13 02 12 00 93 02 20 00 51 | E3 1E 52 FC 93 01 10 01 13 02 00 00 97 20 00 00 52 | 93 80 40 CE 13 00 00 00 13 00 00 00 03 AF 40 00 53 | B7 0E 01 FF 93 8E 0E F0 63 18 DF 05 13 02 12 00 54 | 93 02 20 00 E3 1C 52 FC 97 22 00 00 93 82 82 CB 55 | 03 A1 02 00 13 01 20 00 93 0E 20 00 93 01 20 01 56 | 63 14 D1 03 97 22 00 00 93 82 C2 C9 03 A1 02 00 57 | 13 00 00 00 13 01 20 00 93 0E 20 00 93 01 30 01 58 | 63 14 D1 01 63 1C 30 00 0F 00 F0 0F 63 80 01 00 59 | 93 91 11 00 93 E1 11 00 73 00 00 00 0F 00 F0 0F 60 | 93 01 10 00 73 00 00 00 73 10 00 C0 00 00 00 00 61 | 00 00 00 00 00 62 | @00001000 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 68 | @00002000 69 | FF 00 FF 00 00 FF 00 FF F0 0F F0 0F 0F F0 0F F0 70 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/or.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 B7 00 01 FF 18 | 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 33 EF 20 00 19 | B7 0E 10 FF 93 8E FE F0 93 01 20 00 63 12 DF 4B 20 | B7 10 F0 0F 93 80 00 FF 37 F1 F0 F0 13 01 01 0F 21 | 33 EF 20 00 B7 0E F1 FF 93 8E 0E FF 93 01 30 00 22 | 63 10 DF 49 B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 23 | 13 01 F1 F0 33 EF 20 00 B7 1E FF 0F 93 8E FE FF 24 | 93 01 40 00 63 1E DF 45 B7 F0 0F F0 93 80 F0 00 25 | 37 F1 F0 F0 13 01 01 0F 33 EF 20 00 B7 FE FF F0 26 | 93 8E FE 0F 93 01 50 00 63 1C DF 43 B7 00 01 FF 27 | 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 B3 E0 20 00 28 | B7 0E 10 FF 93 8E FE F0 93 01 60 00 63 9A D0 41 29 | B7 00 01 FF 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 30 | 33 E1 20 00 B7 0E 10 FF 93 8E FE F0 93 01 70 00 31 | 63 18 D1 3F B7 00 01 FF 93 80 00 F0 B3 E0 10 00 32 | B7 0E 01 FF 93 8E 0E F0 93 01 80 00 63 9A D0 3D 33 | 13 02 00 00 B7 00 01 FF 93 80 00 F0 37 11 0F 0F 34 | 13 01 F1 F0 33 EF 20 00 13 03 0F 00 13 02 12 00 35 | 93 02 20 00 E3 10 52 FE B7 0E 10 FF 93 8E FE F0 36 | 93 01 90 00 63 1E D3 39 13 02 00 00 B7 10 F0 0F 37 | 93 80 00 FF 37 F1 F0 F0 13 01 01 0F 33 EF 20 00 38 | 13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 39 | E3 1E 52 FC B7 0E F1 FF 93 8E 0E FF 93 01 A0 00 40 | 63 10 D3 37 13 02 00 00 B7 00 FF 00 93 80 F0 0F 41 | 37 11 0F 0F 13 01 F1 F0 33 EF 20 00 13 00 00 00 42 | 13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 43 | E3 1C 52 FC B7 1E FF 0F 93 8E FE FF 93 01 B0 00 44 | 63 10 D3 33 13 02 00 00 B7 00 01 FF 93 80 00 F0 45 | 37 11 0F 0F 13 01 F1 F0 33 EF 20 00 13 02 12 00 46 | 93 02 20 00 E3 12 52 FE B7 0E 10 FF 93 8E FE F0 47 | 93 01 C0 00 63 16 DF 2F 13 02 00 00 B7 10 F0 0F 48 | 93 80 00 FF 37 F1 F0 F0 13 01 01 0F 13 00 00 00 49 | 33 EF 20 00 13 02 12 00 93 02 20 00 E3 10 52 FE 50 | B7 0E F1 FF 93 8E 0E FF 93 01 D0 00 63 1A DF 2B 51 | 13 02 00 00 B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 52 | 13 01 F1 F0 13 00 00 00 13 00 00 00 33 EF 20 00 53 | 13 02 12 00 93 02 20 00 E3 1E 52 FC B7 1E FF 0F 54 | 93 8E FE FF 93 01 E0 00 63 1C DF 27 13 02 00 00 55 | B7 00 01 FF 93 80 00 F0 13 00 00 00 37 11 0F 0F 56 | 13 01 F1 F0 33 EF 20 00 13 02 12 00 93 02 20 00 57 | E3 10 52 FE B7 0E 10 FF 93 8E FE F0 93 01 F0 00 58 | 63 10 DF 25 13 02 00 00 B7 10 F0 0F 93 80 00 FF 59 | 13 00 00 00 37 F1 F0 F0 13 01 01 0F 13 00 00 00 60 | 33 EF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC 61 | B7 0E F1 FF 93 8E 0E FF 93 01 00 01 63 12 DF 21 62 | 13 02 00 00 B7 00 FF 00 93 80 F0 0F 13 00 00 00 63 | 13 00 00 00 37 11 0F 0F 13 01 F1 F0 33 EF 20 00 64 | 13 02 12 00 93 02 20 00 E3 1E 52 FC B7 1E FF 0F 65 | 93 8E FE FF 93 01 10 01 63 14 DF 1D 13 02 00 00 66 | 37 11 0F 0F 13 01 F1 F0 B7 00 01 FF 93 80 00 F0 67 | 33 EF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE 68 | B7 0E 10 FF 93 8E FE F0 93 01 20 01 63 1A DF 19 69 | 13 02 00 00 37 F1 F0 F0 13 01 01 0F B7 10 F0 0F 70 | 93 80 00 FF 13 00 00 00 33 EF 20 00 13 02 12 00 71 | 93 02 20 00 E3 10 52 FE B7 0E F1 FF 93 8E 0E FF 72 | 93 01 30 01 63 1E DF 15 13 02 00 00 37 11 0F 0F 73 | 13 01 F1 F0 B7 00 FF 00 93 80 F0 0F 13 00 00 00 74 | 13 00 00 00 33 EF 20 00 13 02 12 00 93 02 20 00 75 | E3 1E 52 FC B7 1E FF 0F 93 8E FE FF 93 01 40 01 76 | 63 10 DF 13 13 02 00 00 37 11 0F 0F 13 01 F1 F0 77 | 13 00 00 00 B7 00 01 FF 93 80 00 F0 33 EF 20 00 78 | 13 02 12 00 93 02 20 00 E3 10 52 FE B7 0E 10 FF 79 | 93 8E FE F0 93 01 50 01 63 14 DF 0F 13 02 00 00 80 | 37 F1 F0 F0 13 01 01 0F 13 00 00 00 B7 10 F0 0F 81 | 93 80 00 FF 13 00 00 00 33 EF 20 00 13 02 12 00 82 | 93 02 20 00 E3 1E 52 FC B7 0E F1 FF 93 8E 0E FF 83 | 93 01 60 01 63 16 DF 0B 13 02 00 00 37 11 0F 0F 84 | 13 01 F1 F0 13 00 00 00 13 00 00 00 B7 00 FF 00 85 | 93 80 F0 0F 33 EF 20 00 13 02 12 00 93 02 20 00 86 | E3 1E 52 FC B7 1E FF 0F 93 8E FE FF 93 01 70 01 87 | 63 18 DF 07 B7 00 01 FF 93 80 00 F0 33 61 10 00 88 | B7 0E 01 FF 93 8E 0E F0 93 01 80 01 63 1A D1 05 89 | B7 00 FF 00 93 80 F0 0F 33 E1 00 00 B7 0E FF 00 90 | 93 8E FE 0F 93 01 90 01 63 1C D1 03 B3 60 00 00 91 | 93 0E 00 00 93 01 A0 01 63 94 D0 03 B7 10 11 11 92 | 93 80 10 11 37 21 22 22 13 01 21 22 33 E0 20 00 93 | 93 0E 00 00 93 01 B0 01 63 14 D0 01 63 1C 30 00 94 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 95 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 96 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 97 | 00 00 00 00 00 98 | @00001000 99 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 101 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 102 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 103 | 00 00 00 00 00 00 00 00 104 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/ori.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 B7 00 01 FF 18 | 93 80 00 F0 13 EF F0 F0 93 0E F0 F0 93 01 20 00 19 | 63 14 DF 1D B7 10 F0 0F 93 80 00 FF 13 EF 00 0F 20 | B7 1E F0 0F 93 8E 0E FF 93 01 30 00 63 16 DF 1B 21 | B7 00 FF 00 93 80 F0 0F 13 EF F0 70 B7 0E FF 00 22 | 93 8E FE 7F 93 01 40 00 63 18 DF 19 B7 F0 0F F0 23 | 93 80 F0 00 13 EF 00 0F B7 FE 0F F0 93 8E FE 0F 24 | 93 01 50 00 63 1A DF 17 B7 00 01 FF 93 80 00 F0 25 | 93 E0 00 0F B7 0E 01 FF 93 8E 0E FF 93 01 60 00 26 | 63 9C D0 15 13 02 00 00 B7 10 F0 0F 93 80 00 FF 27 | 13 EF 00 0F 13 03 0F 00 13 02 12 00 93 02 20 00 28 | E3 14 52 FE B7 1E F0 0F 93 8E 0E FF 93 01 70 00 29 | 63 14 D3 13 13 02 00 00 B7 00 FF 00 93 80 F0 0F 30 | 13 EF F0 70 13 00 00 00 13 03 0F 00 13 02 12 00 31 | 93 02 20 00 E3 12 52 FE B7 0E FF 00 93 8E FE 7F 32 | 93 01 80 00 63 1A D3 0F 13 02 00 00 B7 F0 0F F0 33 | 93 80 F0 00 13 EF 00 0F 13 00 00 00 13 00 00 00 34 | 13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE 35 | B7 FE 0F F0 93 8E FE 0F 93 01 90 00 63 1E D3 0B 36 | 13 02 00 00 B7 10 F0 0F 93 80 00 FF 13 EF 00 0F 37 | 13 02 12 00 93 02 20 00 E3 16 52 FE B7 1E F0 0F 38 | 93 8E 0E FF 93 01 A0 00 63 18 DF 09 13 02 00 00 39 | B7 00 FF 00 93 80 F0 0F 13 00 00 00 13 EF F0 F0 40 | 13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E F0 FF 41 | 93 01 B0 00 63 12 DF 07 13 02 00 00 B7 F0 0F F0 42 | 93 80 F0 00 13 00 00 00 13 00 00 00 13 EF 00 0F 43 | 13 02 12 00 93 02 20 00 E3 12 52 FE B7 FE 0F F0 44 | 93 8E FE 0F 93 01 C0 00 63 18 DF 03 93 60 00 0F 45 | 93 0E 00 0F 93 01 D0 00 63 90 D0 03 B7 00 FF 00 46 | 93 80 F0 0F 13 E0 F0 70 93 0E 00 00 93 01 E0 00 47 | 63 14 D0 01 63 1C 30 00 0F 00 F0 0F 63 80 01 00 48 | 93 91 11 00 93 E1 11 00 73 00 00 00 0F 00 F0 0F 49 | 93 01 10 00 73 00 00 00 73 10 00 C0 00 00 00 00 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 51 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 52 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 53 | 00 00 00 00 00 54 | @00001000 55 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 56 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 57 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 59 | 00 00 00 00 00 00 00 00 60 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/sb.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 97 20 00 00 18 | 93 80 40 F0 13 01 A0 FA 23 80 20 00 03 8F 00 00 19 | 93 0E A0 FA 93 01 20 00 63 1C DF 3D 97 20 00 00 20 | 93 80 40 EE 13 01 00 00 A3 80 20 00 03 8F 10 00 21 | 93 0E 00 00 93 01 30 00 63 1C DF 3B 97 20 00 00 22 | 93 80 40 EC 37 F1 FF FF 13 01 01 FA 23 81 20 00 23 | 03 9F 20 00 B7 FE FF FF 93 8E 0E FA 93 01 40 00 24 | 63 18 DF 39 97 20 00 00 93 80 C0 E9 13 01 A0 00 25 | A3 81 20 00 03 8F 30 00 93 0E A0 00 93 01 50 00 26 | 63 18 DF 37 97 20 00 00 93 80 30 E8 13 01 A0 FA 27 | A3 8E 20 FE 03 8F D0 FF 93 0E A0 FA 93 01 60 00 28 | 63 18 DF 35 97 20 00 00 93 80 30 E6 13 01 00 00 29 | 23 8F 20 FE 03 8F E0 FF 93 0E 00 00 93 01 70 00 30 | 63 18 DF 33 97 20 00 00 93 80 30 E4 13 01 00 FA 31 | A3 8F 20 FE 03 8F F0 FF 93 0E 00 FA 93 01 80 00 32 | 63 18 DF 31 97 20 00 00 93 80 30 E2 13 01 A0 00 33 | 23 80 20 00 03 8F 00 00 93 0E A0 00 93 01 90 00 34 | 63 18 DF 2F 97 20 00 00 93 80 40 E0 37 51 34 12 35 | 13 01 81 67 13 82 00 FE 23 00 22 02 83 82 00 00 36 | 93 0E 80 07 93 01 A0 00 63 94 D2 2D 97 20 00 00 37 | 93 80 C0 DD 37 31 00 00 13 01 81 09 93 80 A0 FF 38 | A3 83 20 00 17 22 00 00 13 02 52 DC 83 02 02 00 39 | 93 0E 80 F9 93 01 B0 00 63 9C D2 29 93 01 C0 00 40 | 13 02 00 00 93 00 D0 FD 17 21 00 00 13 01 81 D9 41 | 23 00 11 00 03 0F 01 00 93 0E D0 FD 63 1A DF 27 42 | 13 02 12 00 93 02 20 00 E3 1E 52 FC 93 01 D0 00 43 | 13 02 00 00 93 00 D0 FC 17 21 00 00 13 01 81 D6 44 | 13 00 00 00 A3 00 11 00 03 0F 11 00 93 0E D0 FC 45 | 63 10 DF 25 13 02 12 00 93 02 20 00 E3 1C 52 FC 46 | 93 01 E0 00 13 02 00 00 93 00 C0 FC 17 21 00 00 47 | 13 01 41 D3 13 00 00 00 13 00 00 00 23 01 11 00 48 | 03 0F 21 00 93 0E C0 FC 63 14 DF 21 13 02 12 00 49 | 93 02 20 00 E3 1A 52 FC 93 01 F0 00 13 02 00 00 50 | 93 00 C0 FB 13 00 00 00 17 21 00 00 13 01 81 CF 51 | A3 01 11 00 03 0F 31 00 93 0E C0 FB 63 1A DF 1D 52 | 13 02 12 00 93 02 20 00 E3 1C 52 FC 93 01 00 01 53 | 13 02 00 00 93 00 B0 FB 13 00 00 00 17 21 00 00 54 | 13 01 41 CC 13 00 00 00 23 02 11 00 03 0F 41 00 55 | 93 0E B0 FB 63 1E DF 19 13 02 12 00 93 02 20 00 56 | E3 1A 52 FC 93 01 10 01 13 02 00 00 93 00 B0 FA 57 | 13 00 00 00 13 00 00 00 17 21 00 00 13 01 81 C8 58 | A3 02 11 00 03 0F 51 00 93 0E B0 FA 63 12 DF 17 59 | 13 02 12 00 93 02 20 00 E3 1A 52 FC 93 01 20 01 60 | 13 02 00 00 17 21 00 00 13 01 C1 C5 93 00 30 03 61 | 23 00 11 00 03 0F 01 00 93 0E 30 03 63 1A DF 13 62 | 13 02 12 00 93 02 20 00 E3 1E 52 FC 93 01 30 01 63 | 13 02 00 00 17 21 00 00 13 01 C1 C2 93 00 30 02 64 | 13 00 00 00 A3 00 11 00 03 0F 11 00 93 0E 30 02 65 | 63 10 DF 11 13 02 12 00 93 02 20 00 E3 1C 52 FC 66 | 93 01 40 01 13 02 00 00 17 21 00 00 13 01 81 BF 67 | 93 00 20 02 13 00 00 00 13 00 00 00 23 01 11 00 68 | 03 0F 21 00 93 0E 20 02 63 14 DF 0D 13 02 12 00 69 | 93 02 20 00 E3 1A 52 FC 93 01 50 01 13 02 00 00 70 | 17 21 00 00 13 01 01 BC 13 00 00 00 93 00 20 01 71 | A3 01 11 00 03 0F 31 00 93 0E 20 01 63 1A DF 09 72 | 13 02 12 00 93 02 20 00 E3 1C 52 FC 93 01 60 01 73 | 13 02 00 00 17 21 00 00 13 01 C1 B8 13 00 00 00 74 | 93 00 10 01 13 00 00 00 23 02 11 00 03 0F 41 00 75 | 93 0E 10 01 63 1E DF 05 13 02 12 00 93 02 20 00 76 | E3 1A 52 FC 93 01 70 01 13 02 00 00 17 21 00 00 77 | 13 01 41 B5 13 00 00 00 13 00 00 00 93 00 10 00 78 | A3 02 11 00 03 0F 51 00 93 0E 10 00 63 12 DF 03 79 | 13 02 12 00 93 02 20 00 E3 1A 52 FC 13 05 F0 0E 80 | 97 25 00 00 93 85 05 B2 A3 81 A5 00 63 1C 30 00 81 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 82 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 83 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 84 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 85 | 00 00 00 00 00 86 | @00001000 87 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 89 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 91 | 00 00 00 00 00 00 00 00 92 | @00002000 93 | EF EF EF EF EF EF EF EF EF EF 00 00 00 00 00 00 94 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/sh.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 97 20 00 00 18 | 93 80 40 F0 13 01 A0 0A 23 90 20 00 03 9F 00 00 19 | 93 0E A0 0A 93 01 20 00 63 1E DF 45 97 20 00 00 20 | 93 80 40 EE 37 B1 FF FF 13 01 01 A0 23 91 20 00 21 | 03 9F 20 00 B7 BE FF FF 93 8E 0E A0 93 01 30 00 22 | 63 1A DF 43 97 20 00 00 93 80 C0 EB 37 11 EF BE 23 | 13 01 01 AA 23 92 20 00 03 AF 40 00 B7 1E EF BE 24 | 93 8E 0E AA 93 01 40 00 63 16 DF 41 97 20 00 00 25 | 93 80 40 E9 37 A1 FF FF 13 01 A1 00 23 93 20 00 26 | 03 9F 60 00 B7 AE FF FF 93 8E AE 00 93 01 50 00 27 | 63 12 DF 3F 97 20 00 00 93 80 A0 E7 13 01 A0 0A 28 | 23 9D 20 FE 03 9F A0 FF 93 0E A0 0A 93 01 60 00 29 | 63 12 DF 3D 97 20 00 00 93 80 A0 E5 37 B1 FF FF 30 | 13 01 01 A0 23 9E 20 FE 03 9F C0 FF B7 BE FF FF 31 | 93 8E 0E A0 93 01 70 00 63 1E DF 39 97 20 00 00 32 | 93 80 20 E3 37 11 00 00 13 01 01 AA 23 9F 20 FE 33 | 03 9F E0 FF B7 1E 00 00 93 8E 0E AA 93 01 80 00 34 | 63 1A DF 37 97 20 00 00 93 80 A0 E0 37 A1 FF FF 35 | 13 01 A1 00 23 90 20 00 03 9F 00 00 B7 AE FF FF 36 | 93 8E AE 00 93 01 90 00 63 16 DF 35 97 20 00 00 37 | 93 80 40 DE 37 51 34 12 13 01 81 67 13 82 00 FE 38 | 23 10 22 02 83 92 00 00 B7 5E 00 00 93 8E 8E 67 39 | 93 01 A0 00 63 90 D2 33 97 20 00 00 93 80 80 DB 40 | 37 31 00 00 13 01 81 09 93 80 B0 FF A3 93 20 00 41 | 17 22 00 00 13 02 22 DA 83 12 02 00 B7 3E 00 00 42 | 93 8E 8E 09 93 01 B0 00 63 96 D2 2F 93 01 C0 00 43 | 13 02 00 00 B7 D0 FF FF 93 80 D0 CD 17 21 00 00 44 | 13 01 41 D6 23 10 11 00 03 1F 01 00 B7 DE FF FF 45 | 93 8E DE CD 63 10 DF 2D 13 02 12 00 93 02 20 00 46 | E3 1A 52 FC 93 01 D0 00 13 02 00 00 B7 C0 FF FF 47 | 93 80 D0 CC 17 21 00 00 13 01 C1 D2 13 00 00 00 48 | 23 11 11 00 03 1F 21 00 B7 CE FF FF 93 8E DE CC 49 | 63 12 DF 29 13 02 12 00 93 02 20 00 E3 18 52 FC 50 | 93 01 E0 00 13 02 00 00 B7 C0 FF FF 93 80 C0 BC 51 | 17 21 00 00 13 01 01 CF 13 00 00 00 13 00 00 00 52 | 23 12 11 00 03 1F 41 00 B7 CE FF FF 93 8E CE BC 53 | 63 12 DF 25 13 02 12 00 93 02 20 00 E3 16 52 FC 54 | 93 01 F0 00 13 02 00 00 B7 B0 FF FF 93 80 C0 BB 55 | 13 00 00 00 17 21 00 00 13 01 C1 CA 23 13 11 00 56 | 03 1F 61 00 B7 BE FF FF 93 8E CE BB 63 14 DF 21 57 | 13 02 12 00 93 02 20 00 E3 18 52 FC 93 01 00 01 58 | 13 02 00 00 B7 B0 FF FF 93 80 B0 AB 13 00 00 00 59 | 17 21 00 00 13 01 01 C7 13 00 00 00 23 14 11 00 60 | 03 1F 81 00 B7 BE FF FF 93 8E BE AB 63 14 DF 1D 61 | 13 02 12 00 93 02 20 00 E3 16 52 FC 93 01 10 01 62 | 13 02 00 00 B7 E0 FF FF 93 80 B0 AA 13 00 00 00 63 | 13 00 00 00 17 21 00 00 13 01 C1 C2 23 15 11 00 64 | 03 1F A1 00 B7 EE FF FF 93 8E BE AA 63 14 DF 19 65 | 13 02 12 00 93 02 20 00 E3 16 52 FC 93 01 20 01 66 | 13 02 00 00 17 21 00 00 13 01 C1 BF B7 20 00 00 67 | 93 80 30 23 23 10 11 00 03 1F 01 00 B7 2E 00 00 68 | 93 8E 3E 23 63 18 DF 15 13 02 12 00 93 02 20 00 69 | E3 1A 52 FC 93 01 30 01 13 02 00 00 17 21 00 00 70 | 13 01 41 BC B7 10 00 00 93 80 30 22 13 00 00 00 71 | 23 11 11 00 03 1F 21 00 B7 1E 00 00 93 8E 3E 22 72 | 63 1A DF 11 13 02 12 00 93 02 20 00 E3 18 52 FC 73 | 93 01 40 01 13 02 00 00 17 21 00 00 13 01 81 B8 74 | B7 10 00 00 93 80 20 12 13 00 00 00 13 00 00 00 75 | 23 12 11 00 03 1F 41 00 B7 1E 00 00 93 8E 2E 12 76 | 63 1A DF 0D 13 02 12 00 93 02 20 00 E3 16 52 FC 77 | 93 01 50 01 13 02 00 00 17 21 00 00 13 01 81 B4 78 | 13 00 00 00 93 00 20 11 23 13 11 00 03 1F 61 00 79 | 93 0E 20 11 63 10 DF 0B 13 02 12 00 93 02 20 00 80 | E3 1C 52 FC 93 01 60 01 13 02 00 00 17 21 00 00 81 | 13 01 41 B1 13 00 00 00 93 00 10 01 13 00 00 00 82 | 23 14 11 00 03 1F 81 00 93 0E 10 01 63 14 DF 07 83 | 13 02 12 00 93 02 20 00 E3 1A 52 FC 93 01 70 01 84 | 13 02 00 00 17 21 00 00 13 01 C1 AD 13 00 00 00 85 | 13 00 00 00 B7 30 00 00 93 80 10 00 23 15 11 00 86 | 03 1F A1 00 B7 3E 00 00 93 8E 1E 00 63 14 DF 03 87 | 13 02 12 00 93 02 20 00 E3 16 52 FC 37 C5 00 00 88 | 13 05 F5 EE 97 25 00 00 93 85 C5 A9 23 93 A5 00 89 | 63 1C 30 00 0F 00 F0 0F 63 80 01 00 93 91 11 00 90 | 93 E1 11 00 73 00 00 00 0F 00 F0 0F 93 01 10 00 91 | 73 00 00 00 73 10 00 C0 00 00 00 00 00 00 00 00 92 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 93 | 00 00 00 00 00 94 | @00001000 95 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 96 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 97 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 98 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 99 | 00 00 00 00 00 00 00 00 100 | @00002000 101 | EF BE EF BE EF BE EF BE EF BE EF BE EF BE EF BE 102 | EF BE EF BE 00 00 00 00 00 00 00 00 00 00 00 00 103 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/simple.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 0F 00 F0 0F 18 | 93 01 10 00 73 00 00 00 73 10 00 C0 00 00 00 00 19 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 | 00 00 00 00 00 22 | @00001000 23 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 24 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 25 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 27 | 00 00 00 00 00 00 00 00 28 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/sll.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 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00 13 02 12 00 73 | 93 02 20 00 E3 14 52 FE 93 0E 00 08 93 01 F0 01 74 | 63 16 DF 1D 13 02 00 00 93 00 10 00 13 00 00 00 75 | 13 01 E0 00 13 00 00 00 33 9F 20 00 13 02 12 00 76 | 93 02 20 00 E3 12 52 FE B7 4E 00 00 93 01 00 02 77 | 63 1E DF 19 13 02 00 00 93 00 10 00 13 00 00 00 78 | 13 00 00 00 13 01 F0 01 33 9F 20 00 13 02 12 00 79 | 93 02 20 00 E3 12 52 FE B7 0E 00 80 93 01 10 02 80 | 63 16 DF 17 13 02 00 00 13 01 70 00 93 00 10 00 81 | 33 9F 20 00 13 02 12 00 93 02 20 00 E3 16 52 FE 82 | 93 0E 00 08 93 01 20 02 63 12 DF 15 13 02 00 00 83 | 13 01 E0 00 93 00 10 00 13 00 00 00 33 9F 20 00 84 | 13 02 12 00 93 02 20 00 E3 14 52 FE B7 4E 00 00 85 | 93 01 30 02 63 1C DF 11 13 02 00 00 13 01 F0 01 86 | 93 00 10 00 13 00 00 00 13 00 00 00 33 9F 20 00 87 | 13 02 12 00 93 02 20 00 E3 12 52 FE B7 0E 00 80 88 | 93 01 40 02 63 14 DF 0F 13 02 00 00 13 01 70 00 89 | 13 00 00 00 93 00 10 00 33 9F 20 00 13 02 12 00 90 | 93 02 20 00 E3 14 52 FE 93 0E 00 08 93 01 50 02 91 | 63 1E DF 0B 13 02 00 00 13 01 E0 00 13 00 00 00 92 | 93 00 10 00 13 00 00 00 33 9F 20 00 13 02 12 00 93 | 93 02 20 00 E3 12 52 FE B7 4E 00 00 93 01 60 02 94 | 63 16 DF 09 13 02 00 00 13 01 F0 01 13 00 00 00 95 | 13 00 00 00 93 00 10 00 33 9F 20 00 13 02 12 00 96 | 93 02 20 00 E3 12 52 FE B7 0E 00 80 93 01 70 02 97 | 63 1E DF 05 93 00 F0 00 33 11 10 00 93 0E 00 00 98 | 93 01 80 02 63 14 D1 05 93 00 00 02 33 91 00 00 99 | 93 0E 00 02 93 01 90 02 63 1A D1 03 B3 10 00 00 100 | 93 0E 00 00 93 01 A0 02 63 92 D0 03 93 00 00 40 101 | 37 11 00 00 13 01 01 80 33 90 20 00 93 0E 00 00 102 | 93 01 B0 02 63 14 D0 01 63 1C 30 00 0F 00 F0 0F 103 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 104 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 105 | 00 00 00 00 00 106 | @00001000 107 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 108 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 109 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 110 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 111 | 00 00 00 00 00 00 00 00 112 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/slli.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 00 10 00 18 | 13 9F 00 00 93 0E 10 00 93 01 20 00 63 1A DF 27 19 | 93 00 10 00 13 9F 10 00 93 0E 20 00 93 01 30 00 20 | 63 10 DF 27 93 00 10 00 13 9F 70 00 93 0E 00 08 21 | 93 01 40 00 63 16 DF 25 93 00 10 00 13 9F E0 00 22 | B7 4E 00 00 93 01 50 00 63 1C DF 23 93 00 10 00 23 | 13 9F F0 01 B7 0E 00 80 93 01 60 00 63 12 DF 23 24 | 93 00 F0 FF 13 9F 00 00 93 0E F0 FF 93 01 70 00 25 | 63 18 DF 21 93 00 F0 FF 13 9F 10 00 93 0E E0 FF 26 | 93 01 80 00 63 1E DF 1F 93 00 F0 FF 13 9F 70 00 27 | 93 0E 00 F8 93 01 90 00 63 14 DF 1F 93 00 F0 FF 28 | 13 9F E0 00 B7 CE FF FF 93 01 A0 00 63 1A DF 1D 29 | 93 00 F0 FF 13 9F F0 01 B7 0E 00 80 93 01 B0 00 30 | 63 10 DF 1D B7 20 21 21 93 80 10 12 13 9F 00 00 31 | B7 2E 21 21 93 8E 1E 12 93 01 C0 00 63 12 DF 1B 32 | B7 20 21 21 93 80 10 12 13 9F 10 00 B7 4E 42 42 33 | 93 8E 2E 24 93 01 D0 00 63 14 DF 19 B7 20 21 21 34 | 93 80 10 12 13 9F 70 00 B7 9E 90 90 93 8E 0E 08 35 | 93 01 E0 00 63 16 DF 17 B7 20 21 21 93 80 10 12 36 | 13 9F E0 00 B7 4E 48 48 93 01 F0 00 63 1A DF 15 37 | B7 20 21 21 93 80 10 12 13 9F F0 01 B7 0E 00 80 38 | 93 01 00 01 63 1E DF 13 93 00 10 00 93 90 70 00 39 | 93 0E 00 08 93 01 10 01 63 94 D0 13 13 02 00 00 40 | 93 00 10 00 13 9F 70 00 13 03 0F 00 13 02 12 00 41 | 93 02 20 00 E3 16 52 FE 93 0E 00 08 93 01 20 01 42 | 63 10 D3 11 13 02 00 00 93 00 10 00 13 9F E0 00 43 | 13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 44 | E3 14 52 FE B7 4E 00 00 93 01 30 01 63 1A D3 0D 45 | 13 02 00 00 93 00 10 00 13 9F F0 01 13 00 00 00 46 | 13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 47 | E3 12 52 FE B7 0E 00 80 93 01 40 01 63 12 D3 0B 48 | 13 02 00 00 93 00 10 00 13 9F 70 00 13 02 12 00 49 | 93 02 20 00 E3 18 52 FE 93 0E 00 08 93 01 50 01 50 | 63 10 DF 09 13 02 00 00 93 00 10 00 13 00 00 00 51 | 13 9F E0 00 13 02 12 00 93 02 20 00 E3 16 52 FE 52 | B7 4E 00 00 93 01 60 01 63 1C DF 05 13 02 00 00 53 | 93 00 10 00 13 00 00 00 13 00 00 00 13 9F F0 01 54 | 13 02 12 00 93 02 20 00 E3 14 52 FE B7 0E 00 80 55 | 93 01 70 01 63 16 DF 03 93 10 F0 01 93 0E 00 00 56 | 93 01 80 01 63 9E D0 01 93 00 10 02 13 90 40 01 57 | 93 0E 00 00 93 01 90 01 63 14 D0 01 63 1C 30 00 58 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 59 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 60 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 62 | @00001000 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 68 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/slt.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 00 00 00 18 | 13 01 00 00 33 AF 20 00 93 0E 00 00 93 01 20 00 19 | 63 1A DF 4B 93 00 10 00 13 01 10 00 33 AF 20 00 20 | 93 0E 00 00 93 01 30 00 63 1E DF 49 93 00 30 00 21 | 13 01 70 00 33 AF 20 00 93 0E 10 00 93 01 40 00 22 | 63 12 DF 49 93 00 70 00 13 01 30 00 33 AF 20 00 23 | 93 0E 00 00 93 01 50 00 63 16 DF 47 93 00 00 00 24 | 37 81 FF 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9A D0 33 93 00 B0 00 13 01 D0 00 33 A1 20 00 44 | 93 0E 10 00 93 01 20 01 63 1E D1 31 93 00 D0 00 45 | B3 A0 10 00 93 0E 00 00 93 01 30 01 63 94 D0 31 46 | 13 02 00 00 93 00 B0 00 13 01 D0 00 33 AF 20 00 47 | 13 03 0F 00 13 02 12 00 93 02 20 00 E3 14 52 FE 48 | 93 0E 10 00 93 01 40 01 63 1E D3 2D 13 02 00 00 49 | 93 00 E0 00 13 01 D0 00 33 AF 20 00 13 00 00 00 50 | 13 03 0F 00 13 02 12 00 93 02 20 00 E3 12 52 FE 51 | 93 0E 00 00 93 01 50 01 63 16 D3 2B 13 02 00 00 52 | 93 00 C0 00 13 01 D0 00 33 AF 20 00 13 00 00 00 53 | 13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 54 | E3 10 52 FE 93 0E 10 00 93 01 60 01 63 1C D3 27 55 | 13 02 00 00 93 00 E0 00 13 01 D0 00 33 AF 20 00 56 | 13 02 12 00 93 02 20 00 E3 16 52 FE 93 0E 00 00 57 | 93 01 70 01 63 18 DF 25 13 02 00 00 93 00 B0 00 58 | 13 01 D0 00 13 00 00 00 33 AF 20 00 13 02 12 00 59 | 93 02 20 00 E3 14 52 FE 93 0E 10 00 93 01 80 01 60 | 63 12 DF 23 13 02 00 00 93 00 F0 00 13 01 D0 00 61 | 13 00 00 00 13 00 00 00 33 AF 20 00 13 02 12 00 62 | 93 02 20 00 E3 12 52 FE 93 0E 00 00 93 01 90 01 63 | 63 1A DF 1F 13 02 00 00 93 00 A0 00 13 00 00 00 64 | 13 01 D0 00 33 AF 20 00 13 02 12 00 93 02 20 00 65 | E3 14 52 FE 93 0E 10 00 93 01 A0 01 63 14 DF 1D 66 | 13 02 00 00 93 00 00 01 13 00 00 00 13 01 D0 00 67 | 13 00 00 00 33 AF 20 00 13 02 12 00 93 02 20 00 68 | E3 12 52 FE 93 0E 00 00 93 01 B0 01 63 1C DF 19 69 | 13 02 00 00 93 00 90 00 13 00 00 00 13 00 00 00 70 | 13 01 D0 00 33 AF 20 00 13 02 12 00 93 02 20 00 71 | E3 12 52 FE 93 0E 10 00 93 01 C0 01 63 14 DF 17 72 | 13 02 00 00 13 01 D0 00 93 00 10 01 33 AF 20 00 73 | 13 02 12 00 93 02 20 00 E3 16 52 FE 93 0E 00 00 74 | 93 01 D0 01 63 10 DF 15 13 02 00 00 13 01 D0 00 75 | 93 00 80 00 13 00 00 00 33 AF 20 00 13 02 12 00 76 | 93 02 20 00 E3 14 52 FE 93 0E 10 00 93 01 E0 01 77 | 63 1A DF 11 13 02 00 00 13 01 D0 00 93 00 20 01 78 | 13 00 00 00 13 00 00 00 33 AF 20 00 13 02 12 00 79 | 93 02 20 00 E3 12 52 FE 93 0E 00 00 93 01 F0 01 80 | 63 12 DF 0F 13 02 00 00 13 01 D0 00 13 00 00 00 81 | 93 00 70 00 33 AF 20 00 13 02 12 00 93 02 20 00 82 | E3 14 52 FE 93 0E 10 00 93 01 00 02 63 1C DF 0B 83 | 13 02 00 00 13 01 D0 00 13 00 00 00 93 00 30 01 84 | 13 00 00 00 33 AF 20 00 13 02 12 00 93 02 20 00 85 | E3 12 52 FE 93 0E 00 00 93 01 10 02 63 14 DF 09 86 | 13 02 00 00 13 01 D0 00 13 00 00 00 13 00 00 00 87 | 93 00 60 00 33 AF 20 00 13 02 12 00 93 02 20 00 88 | E3 12 52 FE 93 0E 10 00 93 01 20 02 63 1C DF 05 89 | 93 00 F0 FF 33 21 10 00 93 0E 00 00 93 01 30 02 90 | 63 12 D1 05 93 00 F0 FF 33 A1 00 00 93 0E 10 00 91 | 93 01 40 02 63 18 D1 03 B3 20 00 00 93 0E 00 00 92 | 93 01 50 02 63 90 D0 03 93 00 00 01 13 01 E0 01 93 | 33 A0 20 00 93 0E 00 00 93 01 60 02 63 14 D0 01 94 | 63 1C 30 00 0F 00 F0 0F 63 80 01 00 93 91 11 00 95 | 93 E1 11 00 73 00 00 00 0F 00 F0 0F 93 01 10 00 96 | 73 00 00 00 73 10 00 C0 00 00 00 00 00 00 00 00 97 | 00 00 00 00 00 98 | @00001000 99 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 101 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 102 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 103 | 00 00 00 00 00 00 00 00 104 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/slti.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 00 00 00 18 | 13 AF 00 00 93 0E 00 00 93 01 20 00 63 12 DF 27 19 | 93 00 10 00 13 AF 10 00 93 0E 00 00 93 01 30 00 20 | 63 18 DF 25 93 00 30 00 13 AF 70 00 93 0E 10 00 21 | 93 01 40 00 63 1E DF 23 93 00 70 00 13 AF 30 00 22 | 93 0E 00 00 93 01 50 00 63 14 DF 23 93 00 00 00 23 | 13 AF 00 80 93 0E 00 00 93 01 60 00 63 1A DF 21 24 | B7 00 00 80 13 AF 00 00 93 0E 10 00 93 01 70 00 25 | 63 10 DF 21 B7 00 00 80 13 AF 00 80 93 0E 10 00 26 | 93 01 80 00 63 16 DF 1F 93 00 00 00 13 AF F0 7F 27 | 93 0E 10 00 93 01 90 00 63 1C DF 1D B7 00 00 80 28 | 93 80 F0 FF 13 AF 00 00 93 0E 00 00 93 01 A0 00 29 | 63 10 DF 1D B7 00 00 80 93 80 F0 FF 13 AF F0 7F 30 | 93 0E 00 00 93 01 B0 00 63 14 DF 1B B7 00 00 80 31 | 13 AF F0 7F 93 0E 10 00 93 01 C0 00 63 1A DF 19 32 | B7 00 00 80 93 80 F0 FF 13 AF 00 80 93 0E 00 00 33 | 93 01 D0 00 63 1E DF 17 93 00 00 00 13 AF F0 FF 34 | 93 0E 00 00 93 01 E0 00 63 14 DF 17 93 00 F0 FF 35 | 13 AF 10 00 93 0E 10 00 93 01 F0 00 63 1A DF 15 36 | 93 00 F0 FF 13 AF F0 FF 93 0E 00 00 93 01 00 01 37 | 63 10 DF 15 93 00 B0 00 93 A0 D0 00 93 0E 10 00 38 | 93 01 10 01 63 96 D0 13 13 02 00 00 93 00 F0 00 39 | 13 AF A0 00 13 03 0F 00 13 02 12 00 93 02 20 00 40 | E3 16 52 FE 93 0E 00 00 93 01 20 01 63 12 D3 11 41 | 13 02 00 00 93 00 A0 00 13 AF 00 01 13 00 00 00 42 | 13 03 0F 00 13 02 12 00 93 02 20 00 E3 14 52 FE 43 | 93 0E 10 00 93 01 30 01 63 1C D3 0D 13 02 00 00 44 | 93 00 00 01 13 AF 90 00 13 00 00 00 13 00 00 00 45 | 13 03 0F 00 13 02 12 00 93 02 20 00 E3 12 52 FE 46 | 93 0E 00 00 93 01 40 01 63 14 D3 0B 13 02 00 00 47 | 93 00 B0 00 13 AF F0 00 13 02 12 00 93 02 20 00 48 | E3 18 52 FE 93 0E 10 00 93 01 50 01 63 12 DF 09 49 | 13 02 00 00 93 00 10 01 13 00 00 00 13 AF 80 00 50 | 13 02 12 00 93 02 20 00 E3 16 52 FE 93 0E 00 00 51 | 93 01 60 01 63 1E DF 05 13 02 00 00 93 00 C0 00 52 | 13 00 00 00 13 00 00 00 13 AF E0 00 13 02 12 00 53 | 93 02 20 00 E3 14 52 FE 93 0E 10 00 93 01 70 01 54 | 63 18 DF 03 93 20 F0 FF 93 0E 00 00 93 01 80 01 55 | 63 90 D0 03 B7 00 FF 00 93 80 F0 0F 13 A0 F0 FF 56 | 93 0E 00 00 93 01 90 01 63 14 D0 01 63 1C 30 00 57 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 58 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 59 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 61 | 00 00 00 00 00 62 | @00001000 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 67 | 00 00 00 00 00 00 00 00 68 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/sltiu.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 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93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 B7 00 00 80 18 | 13 01 00 00 33 DF 20 00 B7 0E 00 80 93 01 20 00 19 | 63 18 DF 57 B7 00 00 80 13 01 10 00 33 DF 20 00 20 | B7 0E 00 40 93 01 30 00 63 1C DF 55 B7 00 00 80 21 | 13 01 70 00 33 DF 20 00 B7 0E 00 01 93 01 40 00 22 | 63 10 DF 55 B7 00 00 80 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12 00 93 02 20 00 E3 12 52 FE B7 0E 02 00 80 | 93 01 00 02 63 1E DF 19 13 02 00 00 B7 00 00 80 81 | 13 00 00 00 13 00 00 00 13 01 F0 01 33 DF 20 00 82 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 10 00 83 | 93 01 10 02 63 16 DF 17 13 02 00 00 13 01 70 00 84 | B7 00 00 80 33 DF 20 00 13 02 12 00 93 02 20 00 85 | E3 16 52 FE B7 0E 00 01 93 01 20 02 63 12 DF 15 86 | 13 02 00 00 13 01 E0 00 B7 00 00 80 13 00 00 00 87 | 33 DF 20 00 13 02 12 00 93 02 20 00 E3 14 52 FE 88 | B7 0E 02 00 93 01 30 02 63 1C DF 11 13 02 00 00 89 | 13 01 F0 01 B7 00 00 80 13 00 00 00 13 00 00 00 90 | 33 DF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE 91 | 93 0E 10 00 93 01 40 02 63 14 DF 0F 13 02 00 00 92 | 13 01 70 00 13 00 00 00 B7 00 00 80 33 DF 20 00 93 | 13 02 12 00 93 02 20 00 E3 14 52 FE B7 0E 00 01 94 | 93 01 50 02 63 1E DF 0B 13 02 00 00 13 01 E0 00 95 | 13 00 00 00 B7 00 00 80 13 00 00 00 33 DF 20 00 96 | 13 02 12 00 93 02 20 00 E3 12 52 FE B7 0E 02 00 97 | 93 01 60 02 63 16 DF 09 13 02 00 00 13 01 F0 01 98 | 13 00 00 00 13 00 00 00 B7 00 00 80 33 DF 20 00 99 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 10 00 100 | 93 01 70 02 63 1E DF 05 93 00 F0 00 33 51 10 00 101 | 93 0E 00 00 93 01 80 02 63 14 D1 05 93 00 00 02 102 | 33 D1 00 00 93 0E 00 02 93 01 90 02 63 1A D1 03 103 | B3 50 00 00 93 0E 00 00 93 01 A0 02 63 92 D0 03 104 | 93 00 00 40 37 11 00 00 13 01 01 80 33 D0 20 00 105 | 93 0E 00 00 93 01 B0 02 63 14 D0 01 63 1C 30 00 106 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 107 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 108 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 109 | 00 00 00 00 00 110 | @00001000 111 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 112 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 113 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 114 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 115 | 00 00 00 00 00 00 00 00 116 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/srli.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 B7 00 00 80 18 | 13 DF 00 00 B7 0E 00 80 93 01 20 00 63 18 DF 29 19 | B7 00 00 80 13 DF 10 00 B7 0E 00 40 93 01 30 00 20 | 63 1E DF 27 B7 00 00 80 13 DF 70 00 B7 0E 00 01 21 | 93 01 40 00 63 14 DF 27 B7 00 00 80 13 DF E0 00 22 | B7 0E 02 00 93 01 50 00 63 1A DF 25 B7 00 00 80 23 | 93 80 10 00 13 DF F0 01 93 0E 10 00 93 01 60 00 24 | 63 1E DF 23 93 00 F0 FF 13 DF 00 00 93 0E F0 FF 25 | 93 01 70 00 63 14 DF 23 93 00 F0 FF 13 DF 10 00 26 | B7 0E 00 80 93 8E FE FF 93 01 80 00 63 18 DF 21 27 | 93 00 F0 FF 13 DF 70 00 B7 0E 00 02 93 8E FE FF 28 | 93 01 90 00 63 1C DF 1F 93 00 F0 FF 13 DF E0 00 29 | B7 0E 04 00 93 8E FE FF 93 01 A0 00 63 10 DF 1F 30 | 93 00 F0 FF 13 DF F0 01 93 0E 10 00 93 01 B0 00 31 | 63 16 DF 1D B7 20 21 21 93 80 10 12 13 DF 00 00 32 | B7 2E 21 21 93 8E 1E 12 93 01 C0 00 63 18 DF 1B 33 | B7 20 21 21 93 80 10 12 13 DF 10 00 B7 9E 90 10 34 | 93 8E 0E 09 93 01 D0 00 63 1A DF 19 B7 20 21 21 35 | 93 80 10 12 13 DF 70 00 B7 4E 42 00 93 8E 2E 24 36 | 93 01 E0 00 63 1C DF 17 B7 20 21 21 93 80 10 12 37 | 13 DF E0 00 B7 8E 00 00 93 8E 4E 48 93 01 F0 00 38 | 63 1E DF 15 B7 20 21 21 93 80 10 12 13 DF F0 01 39 | 93 0E 00 00 93 01 00 01 63 12 DF 15 B7 00 00 80 40 | 93 D0 70 00 B7 0E 00 01 93 01 10 01 63 98 D0 13 41 | 13 02 00 00 B7 00 00 80 13 DF 70 00 13 03 0F 00 42 | 13 02 12 00 93 02 20 00 E3 16 52 FE B7 0E 00 01 43 | 93 01 20 01 63 14 D3 11 13 02 00 00 B7 00 00 80 44 | 13 DF E0 00 13 00 00 00 13 03 0F 00 13 02 12 00 45 | 93 02 20 00 E3 14 52 FE B7 0E 02 00 93 01 30 01 46 | 63 1E D3 0D 13 02 00 00 B7 00 00 80 93 80 10 00 47 | 13 DF F0 01 13 00 00 00 13 00 00 00 13 03 0F 00 48 | 13 02 12 00 93 02 20 00 E3 10 52 FE 93 0E 10 00 49 | 93 01 40 01 63 14 D3 0B 13 02 00 00 B7 00 00 80 50 | 13 DF 70 00 13 02 12 00 93 02 20 00 E3 18 52 FE 51 | B7 0E 00 01 93 01 50 01 63 12 DF 09 13 02 00 00 52 | B7 00 00 80 13 00 00 00 13 DF E0 00 13 02 12 00 53 | 93 02 20 00 E3 16 52 FE B7 0E 02 00 93 01 60 01 54 | 63 1E DF 05 13 02 00 00 B7 00 00 80 93 80 10 00 55 | 13 00 00 00 13 00 00 00 13 DF F0 01 13 02 12 00 56 | 93 02 20 00 E3 12 52 FE 93 0E 10 00 93 01 70 01 57 | 63 16 DF 03 93 50 40 00 93 0E 00 00 93 01 80 01 58 | 63 9E D0 01 93 00 10 02 13 D0 A0 00 93 0E 00 00 59 | 93 01 90 01 63 14 D0 01 63 1C 30 00 0F 00 F0 0F 60 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 61 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 62 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 63 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 | 00 00 00 00 00 66 | @00001000 67 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 69 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 71 | 00 00 00 00 00 00 00 00 72 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/sub.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 93 00 00 00 18 | 13 01 00 00 33 8F 20 40 93 0E 00 00 93 01 20 00 19 | 63 16 DF 4B 93 00 10 00 13 01 10 00 33 8F 20 40 20 | 93 0E 00 00 93 01 30 00 63 1A DF 49 93 00 30 00 21 | 13 01 70 00 33 8F 20 40 93 0E C0 FF 93 01 40 00 22 | 63 1E DF 47 93 00 00 00 37 81 FF FF 33 8F 20 40 23 | B7 8E 00 00 93 01 50 00 63 12 DF 47 B7 00 00 80 24 | 13 01 00 00 33 8F 20 40 B7 0E 00 80 93 01 60 00 25 | 63 16 DF 45 B7 00 00 80 37 81 FF FF 33 8F 20 40 26 | B7 8E 00 80 93 01 70 00 63 1A DF 43 93 00 00 00 27 | 37 81 00 00 13 01 F1 FF 33 8F 20 40 B7 8E FF FF 28 | 93 8E 1E 00 93 01 80 00 63 1A DF 41 B7 00 00 80 29 | 93 80 F0 FF 13 01 00 00 33 8F 20 40 B7 0E 00 80 30 | 93 8E FE FF 93 01 90 00 63 1A DF 3F B7 00 00 80 31 | 93 80 F0 FF 37 81 00 00 13 01 F1 FF 33 8F 20 40 32 | B7 8E FF 7F 93 01 A0 00 63 1A DF 3D B7 00 00 80 33 | 37 81 00 00 13 01 F1 FF 33 8F 20 40 B7 8E FF 7F 34 | 93 8E 1E 00 93 01 B0 00 63 1A DF 3B B7 00 00 80 35 | 93 80 F0 FF 37 81 FF FF 33 8F 20 40 B7 8E 00 80 36 | 93 8E FE FF 93 01 C0 00 63 1A DF 39 93 00 00 00 37 | 13 01 F0 FF 33 8F 20 40 93 0E 10 00 93 01 D0 00 38 | 63 1E DF 37 93 00 F0 FF 13 01 10 00 33 8F 20 40 39 | 93 0E E0 FF 93 01 E0 00 63 12 DF 37 93 00 F0 FF 40 | 13 01 F0 FF 33 8F 20 40 93 0E 00 00 93 01 F0 00 41 | 63 16 DF 35 93 00 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13 01 B0 00 13 00 00 00 13 00 00 00 61 | 33 8F 20 40 13 02 12 00 93 02 20 00 E3 12 52 FE 62 | 93 0E 40 00 93 01 80 01 63 1A DF 1F 13 02 00 00 63 | 93 00 D0 00 13 00 00 00 13 01 B0 00 33 8F 20 40 64 | 13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 20 00 65 | 93 01 90 01 63 14 DF 1D 13 02 00 00 93 00 E0 00 66 | 13 00 00 00 13 01 B0 00 13 00 00 00 33 8F 20 40 67 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 30 00 68 | 93 01 A0 01 63 1C DF 19 13 02 00 00 93 00 F0 00 69 | 13 00 00 00 13 00 00 00 13 01 B0 00 33 8F 20 40 70 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 40 00 71 | 93 01 B0 01 63 14 DF 17 13 02 00 00 13 01 B0 00 72 | 93 00 D0 00 33 8F 20 40 13 02 12 00 93 02 20 00 73 | E3 16 52 FE 93 0E 20 00 93 01 C0 01 63 10 DF 15 74 | 13 02 00 00 13 01 B0 00 93 00 E0 00 13 00 00 00 75 | 33 8F 20 40 13 02 12 00 93 02 20 00 E3 14 52 FE 76 | 93 0E 30 00 93 01 D0 01 63 1A DF 11 13 02 00 00 77 | 13 01 B0 00 93 00 F0 00 13 00 00 00 13 00 00 00 78 | 33 8F 20 40 13 02 12 00 93 02 20 00 E3 12 52 FE 79 | 93 0E 40 00 93 01 E0 01 63 12 DF 0F 13 02 00 00 80 | 13 01 B0 00 13 00 00 00 93 00 D0 00 33 8F 20 40 81 | 13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 20 00 82 | 93 01 F0 01 63 1C DF 0B 13 02 00 00 13 01 B0 00 83 | 13 00 00 00 93 00 E0 00 13 00 00 00 33 8F 20 40 84 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 30 00 85 | 93 01 00 02 63 14 DF 09 13 02 00 00 13 01 B0 00 86 | 13 00 00 00 13 00 00 00 93 00 F0 00 33 8F 20 40 87 | 13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 40 00 88 | 93 01 10 02 63 1C DF 05 93 00 10 FF 33 01 10 40 89 | 93 0E F0 00 93 01 20 02 63 12 D1 05 93 00 00 02 90 | 33 81 00 40 93 0E 00 02 93 01 30 02 63 18 D1 03 91 | B3 00 00 40 93 0E 00 00 93 01 40 02 63 90 D0 03 92 | 93 00 00 01 13 01 E0 01 33 80 20 40 93 0E 00 00 93 | 93 01 50 02 63 14 D0 01 63 1C 30 00 0F 00 F0 0F 94 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 95 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 96 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 97 | 00 00 00 00 00 98 | @00001000 99 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 101 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 102 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 103 | 00 00 00 00 00 00 00 00 104 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/sw.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 97 20 00 00 18 | 93 80 40 F0 37 01 AA 00 13 01 A1 0A 23 A0 20 00 19 | 03 AF 00 00 B7 0E AA 00 93 8E AE 0A 93 01 20 00 20 | 63 10 DF 47 97 20 00 00 93 80 C0 ED 37 B1 00 AA 21 | 13 01 01 A0 23 A2 20 00 03 AF 40 00 B7 BE 00 AA 22 | 93 8E 0E A0 93 01 30 00 63 1C DF 43 97 20 00 00 23 | 93 80 40 EB 37 11 A0 0A 13 01 01 AA 23 A4 20 00 24 | 03 AF 80 00 B7 1E A0 0A 93 8E 0E AA 93 01 40 00 25 | 63 18 DF 41 97 20 00 00 93 80 C0 E8 37 A1 0A A0 26 | 13 01 A1 00 23 A6 20 00 03 AF C0 00 B7 AE 0A A0 27 | 93 8E AE 00 93 01 50 00 63 14 DF 3F 97 20 00 00 28 | 93 80 00 E8 37 01 AA 00 13 01 A1 0A 23 AA 20 FE 29 | 03 AF 40 FF B7 0E AA 00 93 8E AE 0A 93 01 60 00 30 | 63 10 DF 3D 97 20 00 00 93 80 80 E5 37 B1 00 AA 31 | 13 01 01 A0 23 AC 20 FE 03 AF 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93 02 20 00 E3 18 52 FC 51 | 93 01 E0 00 13 02 00 00 B7 C0 AA DD 93 80 C0 BC 52 | 17 21 00 00 13 01 01 CE 13 00 00 00 13 00 00 00 53 | 23 24 11 00 03 2F 81 00 B7 CE AA DD 93 8E CE BC 54 | 63 10 DF 25 13 02 12 00 93 02 20 00 E3 16 52 FC 55 | 93 01 F0 00 13 02 00 00 B7 B0 DA CD 93 80 C0 BB 56 | 13 00 00 00 17 21 00 00 13 01 C1 C9 23 26 11 00 57 | 03 2F C1 00 B7 BE DA CD 93 8E CE BB 63 12 DF 21 58 | 13 02 12 00 93 02 20 00 E3 18 52 FC 93 01 00 01 59 | 13 02 00 00 B7 B0 DD CC 93 80 B0 AB 13 00 00 00 60 | 17 21 00 00 13 01 01 C6 13 00 00 00 23 28 11 00 61 | 03 2F 01 01 B7 BE DD CC 93 8E BE AB 63 12 DF 1D 62 | 13 02 12 00 93 02 20 00 E3 16 52 FC 93 01 10 01 63 | 13 02 00 00 B7 E0 CD BC 93 80 B0 AA 13 00 00 00 64 | 13 00 00 00 17 21 00 00 13 01 C1 C1 23 2A 11 00 65 | 03 2F 41 01 B7 EE CD BC 93 8E BE AA 63 12 DF 19 66 | 13 02 12 00 93 02 20 00 E3 16 52 FC 93 01 20 01 67 | 13 02 00 00 17 21 00 00 13 01 C1 BE B7 20 11 00 68 | 93 80 30 23 23 20 11 00 03 2F 01 00 B7 2E 11 00 69 | 93 8E 3E 23 63 16 DF 15 13 02 12 00 93 02 20 00 70 | E3 1A 52 FC 93 01 30 01 13 02 00 00 17 21 00 00 71 | 13 01 41 BB B7 10 01 30 93 80 30 22 13 00 00 00 72 | 23 22 11 00 03 2F 41 00 B7 1E 01 30 93 8E 3E 22 73 | 63 18 DF 11 13 02 12 00 93 02 20 00 E3 18 52 FC 74 | 93 01 40 01 13 02 00 00 17 21 00 00 13 01 81 B7 75 | B7 10 00 33 93 80 20 12 13 00 00 00 13 00 00 00 76 | 23 24 11 00 03 2F 81 00 B7 1E 00 33 93 8E 2E 12 77 | 63 18 DF 0D 13 02 12 00 93 02 20 00 E3 16 52 FC 78 | 93 01 50 01 13 02 00 00 17 21 00 00 13 01 81 B3 79 | 13 00 00 00 B7 00 30 23 93 80 20 11 23 26 11 00 80 | 03 2F C1 00 B7 0E 30 23 93 8E 2E 11 63 1A DF 09 81 | 13 02 12 00 93 02 20 00 E3 18 52 FC 93 01 60 01 82 | 13 02 00 00 17 21 00 00 13 01 C1 AF 13 00 00 00 83 | B7 00 33 22 93 80 10 01 13 00 00 00 23 28 11 00 84 | 03 2F 01 01 B7 0E 33 22 93 8E 1E 01 63 1A DF 05 85 | 13 02 12 00 93 02 20 00 E3 16 52 FC 93 01 70 01 86 | 13 02 00 00 17 21 00 00 13 01 C1 AB 13 00 00 00 87 | 13 00 00 00 B7 30 23 12 93 80 10 00 23 2A 11 00 88 | 03 2F 41 01 B7 3E 23 12 93 8E 1E 00 63 1A DF 01 89 | 13 02 12 00 93 02 20 00 E3 16 52 FC 63 1C 30 00 90 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 91 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 92 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 93 | 00 00 00 00 00 94 | @00001000 95 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 96 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 97 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 98 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 99 | 00 00 00 00 00 00 00 00 100 | @00002000 101 | EF BE AD DE EF BE AD DE EF BE AD DE EF BE AD DE 102 | EF BE AD DE EF BE AD DE EF BE AD DE EF BE AD DE 103 | EF BE AD DE EF BE AD DE 00 00 00 00 00 00 00 00 104 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/xor.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 B7 00 01 FF 18 | 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 33 CF 20 00 19 | B7 FE 0F F0 93 8E FE 00 93 01 20 00 63 10 DF 4B 20 | B7 10 F0 0F 93 80 00 FF 37 F1 F0 F0 13 01 01 0F 21 | 33 CF 20 00 B7 0E 01 FF 93 8E 0E F0 93 01 30 00 22 | 63 1E DF 47 B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 23 | 13 01 F1 F0 33 CF 20 00 B7 1E F0 0F 93 8E 0E FF 24 | 93 01 40 00 63 1C DF 45 B7 F0 0F F0 93 80 F0 00 25 | 37 F1 F0 F0 13 01 01 0F 33 CF 20 00 B7 0E FF 00 26 | 93 8E FE 0F 93 01 50 00 63 1A DF 43 B7 00 01 FF 27 | 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 B3 C0 20 00 28 | B7 FE 0F F0 93 8E FE 00 93 01 60 00 63 98 D0 41 29 | B7 00 01 FF 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 30 | 33 C1 20 00 B7 FE 0F F0 93 8E FE 00 93 01 70 00 31 | 63 16 D1 3F B7 00 01 FF 93 80 00 F0 B3 C0 10 00 32 | 93 0E 00 00 93 01 80 00 63 9A D0 3D 13 02 00 00 33 | B7 00 01 FF 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 34 | 33 CF 20 00 13 03 0F 00 13 02 12 00 93 02 20 00 35 | E3 10 52 FE B7 FE 0F F0 93 8E FE 00 93 01 90 00 36 | 63 1E D3 39 13 02 00 00 B7 10 F0 0F 93 80 00 FF 37 | 37 F1 F0 F0 13 01 01 0F 33 CF 20 00 13 00 00 00 38 | 13 03 0F 00 13 02 12 00 93 02 20 00 E3 1E 52 FC 39 | B7 0E 01 FF 93 8E 0E F0 93 01 A0 00 63 10 D3 37 40 | 13 02 00 00 B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 41 | 13 01 F1 F0 33 CF 20 00 13 00 00 00 13 00 00 00 42 | 13 03 0F 00 13 02 12 00 93 02 20 00 E3 1C 52 FC 43 | B7 1E F0 0F 93 8E 0E FF 93 01 B0 00 63 10 D3 33 44 | 13 02 00 00 B7 00 01 FF 93 80 00 F0 37 11 0F 0F 45 | 13 01 F1 F0 33 CF 20 00 13 02 12 00 93 02 20 00 46 | E3 12 52 FE B7 FE 0F F0 93 8E FE 00 93 01 C0 00 47 | 63 16 DF 2F 13 02 00 00 B7 10 F0 0F 93 80 00 FF 48 | 37 F1 F0 F0 13 01 01 0F 13 00 00 00 33 CF 20 00 49 | 13 02 12 00 93 02 20 00 E3 10 52 FE B7 0E 01 FF 50 | 93 8E 0E F0 93 01 D0 00 63 1A DF 2B 13 02 00 00 51 | B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 52 | 13 00 00 00 13 00 00 00 33 CF 20 00 13 02 12 00 53 | 93 02 20 00 E3 1E 52 FC B7 1E F0 0F 93 8E 0E FF 54 | 93 01 E0 00 63 1C DF 27 13 02 00 00 B7 00 01 FF 55 | 93 80 00 F0 13 00 00 00 37 11 0F 0F 13 01 F1 F0 56 | 33 CF 20 00 13 02 12 00 93 02 20 00 E3 10 52 FE 57 | B7 FE 0F F0 93 8E FE 00 93 01 F0 00 63 10 DF 25 58 | 13 02 00 00 B7 10 F0 0F 93 80 00 FF 13 00 00 00 59 | 37 F1 F0 F0 13 01 01 0F 13 00 00 00 33 CF 20 00 60 | 13 02 12 00 93 02 20 00 E3 1E 52 FC B7 0E 01 FF 61 | 93 8E 0E F0 93 01 00 01 63 12 DF 21 13 02 00 00 62 | B7 00 FF 00 93 80 F0 0F 13 00 00 00 13 00 00 00 63 | 37 11 0F 0F 13 01 F1 F0 33 CF 20 00 13 02 12 00 64 | 93 02 20 00 E3 1E 52 FC B7 1E F0 0F 93 8E 0E FF 65 | 93 01 10 01 63 14 DF 1D 13 02 00 00 37 11 0F 0F 66 | 13 01 F1 F0 B7 00 01 FF 93 80 00 F0 33 CF 20 00 67 | 13 02 12 00 93 02 20 00 E3 12 52 FE B7 FE 0F F0 68 | 93 8E FE 00 93 01 20 01 63 1A DF 19 13 02 00 00 69 | 37 F1 F0 F0 13 01 01 0F B7 10 F0 0F 93 80 00 FF 70 | 13 00 00 00 33 CF 20 00 13 02 12 00 93 02 20 00 71 | E3 10 52 FE B7 0E 01 FF 93 8E 0E F0 93 01 30 01 72 | 63 1E DF 15 13 02 00 00 37 11 0F 0F 13 01 F1 F0 73 | B7 00 FF 00 93 80 F0 0F 13 00 00 00 13 00 00 00 74 | 33 CF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC 75 | B7 1E F0 0F 93 8E 0E FF 93 01 40 01 63 10 DF 13 76 | 13 02 00 00 37 11 0F 0F 13 01 F1 F0 13 00 00 00 77 | B7 00 01 FF 93 80 00 F0 33 CF 20 00 13 02 12 00 78 | 93 02 20 00 E3 10 52 FE B7 FE 0F F0 93 8E FE 00 79 | 93 01 50 01 63 14 DF 0F 13 02 00 00 37 F1 F0 F0 80 | 13 01 01 0F 13 00 00 00 B7 10 F0 0F 93 80 00 FF 81 | 13 00 00 00 33 CF 20 00 13 02 12 00 93 02 20 00 82 | E3 1E 52 FC B7 0E 01 FF 93 8E 0E F0 93 01 60 01 83 | 63 16 DF 0B 13 02 00 00 37 11 0F 0F 13 01 F1 F0 84 | 13 00 00 00 13 00 00 00 B7 00 FF 00 93 80 F0 0F 85 | 33 CF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC 86 | B7 1E F0 0F 93 8E 0E FF 93 01 70 01 63 18 DF 07 87 | B7 00 01 FF 93 80 00 F0 33 41 10 00 B7 0E 01 FF 88 | 93 8E 0E F0 93 01 80 01 63 1A D1 05 B7 00 FF 00 89 | 93 80 F0 0F 33 C1 00 00 B7 0E FF 00 93 8E FE 0F 90 | 93 01 90 01 63 1C D1 03 B3 40 00 00 93 0E 00 00 91 | 93 01 A0 01 63 94 D0 03 B7 10 11 11 93 80 10 11 92 | 37 21 22 22 13 01 21 22 33 C0 20 00 93 0E 00 00 93 | 93 01 B0 01 63 14 D0 01 63 1C 30 00 0F 00 F0 0F 94 | 63 80 01 00 93 91 11 00 93 E1 11 00 73 00 00 00 95 | 0F 00 F0 0F 93 01 10 00 73 00 00 00 73 10 00 C0 96 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 97 | 00 00 00 00 00 98 | @00001000 99 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 101 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 102 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 103 | 00 00 00 00 00 00 00 00 104 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/build/xori.hex: -------------------------------------------------------------------------------- 1 | @00000000 2 | 6F 00 C0 04 73 2F 20 34 93 0F 80 00 63 0A FF 03 3 | 93 0F 90 00 63 06 FF 03 93 0F B0 00 63 02 FF 03 4 | 17 0F 00 00 13 0F 0F FE 63 04 0F 00 67 00 0F 00 5 | 73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 6 | 17 1F 00 00 23 20 3F FC 6F F0 9F FF 73 25 40 F1 7 | 63 10 05 00 97 02 00 00 93 82 02 01 73 90 52 30 8 | 73 50 00 18 97 02 00 00 93 82 C2 01 73 90 52 30 9 | 93 02 F0 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A 10 | 97 02 00 00 93 82 82 01 73 90 52 30 73 50 20 30 11 | 73 50 30 30 73 50 40 30 93 01 00 00 97 02 00 00 12 | 93 82 82 F6 73 90 52 30 13 05 10 00 13 15 F5 01 13 | 63 48 05 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 14 | 97 02 00 00 93 82 02 F4 63 8E 02 00 73 90 52 10 15 | B7 B2 00 00 93 82 92 10 73 90 22 30 73 23 20 30 16 | E3 9E 62 F4 73 50 00 30 97 02 00 00 93 82 42 01 17 | 73 90 12 34 73 25 40 F1 73 00 20 30 B7 10 FF 00 18 | 93 80 00 F0 13 CF F0 F0 B7 FE 00 FF 93 8E FE 00 19 | 93 01 20 00 63 16 DF 1D B7 10 F0 0F 93 80 00 FF 20 | 13 CF 00 0F B7 1E F0 0F 93 8E 0E F0 93 01 30 00 21 | 63 18 DF 1B B7 10 FF 00 93 80 F0 8F 13 CF F0 70 22 | B7 1E FF 00 93 8E 0E FF 93 01 40 00 63 1A DF 19 23 | B7 F0 0F F0 93 80 F0 00 13 CF 00 0F B7 FE 0F F0 24 | 93 8E FE 0F 93 01 50 00 63 1C DF 17 B7 F0 00 FF 25 | 93 80 00 70 93 C0 F0 70 B7 FE 00 FF 93 8E FE 00 26 | 93 01 60 00 63 9E D0 15 13 02 00 00 B7 10 F0 0F 27 | 93 80 00 FF 13 CF 00 0F 13 03 0F 00 13 02 12 00 28 | 93 02 20 00 E3 14 52 FE B7 1E F0 0F 93 8E 0E F0 29 | 93 01 70 00 63 16 D3 13 13 02 00 00 B7 10 FF 00 30 | 93 80 F0 8F 13 CF F0 70 13 00 00 00 13 03 0F 00 31 | 13 02 12 00 93 02 20 00 E3 12 52 FE B7 1E FF 00 32 | 93 8E 0E FF 93 01 80 00 63 1C D3 0F 13 02 00 00 33 | B7 F0 0F F0 93 80 F0 00 13 CF 00 0F 13 00 00 00 34 | 13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 35 | E3 10 52 FE B7 FE 0F F0 93 8E FE 0F 93 01 90 00 36 | 63 10 D3 0D 13 02 00 00 B7 10 F0 0F 93 80 00 FF 37 | 13 CF 00 0F 13 02 12 00 93 02 20 00 E3 16 52 FE 38 | B7 1E F0 0F 93 8E 0E F0 93 01 A0 00 63 1A DF 09 39 | 13 02 00 00 B7 10 FF 00 93 80 F0 FF 13 00 00 00 40 | 13 CF F0 00 13 02 12 00 93 02 20 00 E3 14 52 FE 41 | B7 1E FF 00 93 8E 0E FF 93 01 B0 00 63 12 DF 07 42 | 13 02 00 00 B7 F0 0F F0 93 80 F0 00 13 00 00 00 43 | 13 00 00 00 13 CF 00 0F 13 02 12 00 93 02 20 00 44 | E3 12 52 FE B7 FE 0F F0 93 8E FE 0F 93 01 C0 00 45 | 63 18 DF 03 93 40 00 0F 93 0E 00 0F 93 01 D0 00 46 | 63 90 D0 03 B7 00 FF 00 93 80 F0 0F 13 C0 F0 70 47 | 93 0E 00 00 93 01 E0 00 63 14 D0 01 63 1C 30 00 48 | 0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 49 | 73 00 00 00 0F 00 F0 0F 93 01 10 00 73 00 00 00 50 | 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 51 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 52 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 53 | 00 00 00 00 00 54 | @00001000 55 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 56 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 57 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 58 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 59 | 00 00 00 00 00 00 00 00 60 | -------------------------------------------------------------------------------- /riscv_tests_hexgen/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x00000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x1000); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x1000); 11 | .text : { *(.text) } 12 | . = ALIGN(0x1000); 13 | .data : { *(.data) } 14 | .bss : { *(.bss) } 15 | _end = .; 16 | } 17 | 18 | -------------------------------------------------------------------------------- /src/Makefile: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # 4 | # Licensed to the Apache Software Foundation (ASF) under one 5 | # or more contributor license agreements. See the NOTICE file 6 | # distributed with this work for additional information 7 | # regarding copyright ownership. The ASF licenses this file 8 | # to you under the Apache License, Version 2.0 (the 9 | # "License"); you may not use this file except in compliance 10 | # with the License. You may obtain a copy of the License at 11 | # 12 | # http://www.apache.org/licenses/LICENSE-2.0 13 | # 14 | # Unless required by applicable law or agreed to in writing, 15 | # software distributed under the License is distributed on an 16 | # "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | # KIND, either express or implied. See the License for the 18 | # specific language governing permissions and limitations 19 | # under the License. 20 | # 21 | ################################################################ 22 | 23 | 24 | # default, can be overriden at runtime: make inst_ut SIMR=ius 25 | SIMR ?= modelsim 26 | #SIMR ?= ius 27 | 28 | ifeq ($(SIMR), modelsim) 29 | SIMR_ARGS := -c_arg +cover -r "-do riscv_vip.do" 30 | endif 31 | ifeq ($(SIMR), ius) 32 | SIMR_ARGS := -c_arg "-coverage all -covoverwrite" 33 | endif 34 | 35 | 36 | inst_ut: 37 | runSVUnit -t instruction_unit_test.sv -s $(SIMR) -f riscv_vip.f $(SIMR_ARGS) 38 | 39 | hex_ut: 40 | runSVUnit -t hex_file_analyzer_unit_test.sv -s $(SIMR) -f riscv_vip.f $(SIMR_ARGS) 41 | 42 | csrs_ut: 43 | runSVUnit -t csrs_unit_test.sv -s $(SIMR) -f riscv_vip.f $(SIMR_ARGS) 44 | 45 | rf_ut: 46 | runSVUnit -t regfile_unit_test.sv -s $(SIMR) -f riscv_vip.f $(SIMR_ARGS) 47 | 48 | rfet_ut: 49 | runSVUnit -t reg_fetcher_unit_test.sv -s $(SIMR) -f riscv_vip.f $(SIMR_ARGS) 50 | 51 | ihist_ut: 52 | runSVUnit -t inst_history_unit_test.sv -s $(SIMR) -f riscv_vip.f $(SIMR_ARGS) 53 | 54 | 55 | 56 | cov: 57 | vsim -viewcov riscv_vip.ucdb 58 | 59 | doc: 60 | NaturalDocs 61 | 62 | clean: 63 | rm -Rf work/* 64 | rm -Rf riscv_vip 65 | 66 | 67 | 68 | -------------------------------------------------------------------------------- /src/csrs.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `ifndef _CSRS_INCLUDED_ 25 | `define _CSRS_INCLUDED_ 26 | 27 | class csrs; 28 | 29 | protected csrs_t m_csrs; 30 | 31 | // Get m_csrs 32 | virtual function csrs_t get_m_csrs(); 33 | return m_csrs; 34 | endfunction : get_m_csrs 35 | 36 | // Set m_csrs 37 | virtual function void set_m_csrs(csrs_t m_csrs); 38 | this.m_csrs = m_csrs; 39 | endfunction : set_m_csrs 40 | 41 | virtual function csr_t get_cycle(); 42 | return m_csrs.cycle; 43 | endfunction 44 | 45 | endclass 46 | 47 | //This class monitors the whitebox csrs and updates the model class. This 48 | //is intended for non UVM agent csr implementations and will be updated when/if 49 | //things change to full uvm. Keep it simple for now 'caus it's going to change 50 | class monitored_csrs extends csrs; 51 | typedef virtual riscv_vip_csr_if vif_t; 52 | virtual riscv_vip_csr_if m_vif; 53 | //protected mailbox#(.T(csr_id_t)) assigned_ids; //future, if needed 54 | 55 | virtual function void set_m_vif(vif_t csr_vif); 56 | m_vif = csr_vif; 57 | endfunction 58 | 59 | 60 | 61 | //task wait_for_csr_update(ref csr_id_t updated_ids[$]) //future, if needed... 62 | 63 | virtual task run_monitor(); 64 | do_monitor_thread : fork 65 | do_monitor(); 66 | join_none 67 | endtask 68 | 69 | virtual protected task do_monitor(); 70 | @(posedge m_vif.rstn); 71 | forever begin 72 | @(posedge m_vif.clk iff ( m_vif.csrs !== m_csrs)); 73 | m_csrs = m_vif.csrs; 74 | end 75 | endtask // do_monitor 76 | 77 | 78 | endclass 79 | 80 | `endif -------------------------------------------------------------------------------- /src/csrs_unit_test.sv: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `include "svunit_defines.svh" 25 | `include "riscv_vip_pkg.sv" 26 | 27 | module csrs_unit_test; 28 | import svunit_pkg::svunit_testcase; 29 | import riscv_vip_pkg::*; 30 | import riscv_vip_class_pkg::*; 31 | 32 | 33 | string name = "csrs_ut"; 34 | svunit_testcase svunit_ut; 35 | 36 | logic clk; 37 | logic rstn; 38 | riscv_vip_csr_if csr_if(.*); 39 | //Below needed to please simulator. Even if _if is not used the simulatore 40 | //needs to see that it gets assigned somewhere for the class that references it 41 | riscv_vip_regfile_if regfile_if(.*); 42 | monitored_regfile my_regfile = new(); 43 | 44 | 45 | //=================================== 46 | // This is the UUT that we're 47 | // running the Unit Tests on 48 | //=================================== 49 | csrs my_csrs; 50 | 51 | 52 | //=================================== 53 | // Build 54 | //=================================== 55 | function void build(); 56 | svunit_ut = new(name); 57 | endfunction 58 | 59 | 60 | //=================================== 61 | // Setup for running the Unit Tests 62 | //=================================== 63 | task setup(); 64 | svunit_ut.setup(); 65 | /* Place Setup Code Here */ 66 | my_regfile.set_m_vif(regfile_if); 67 | 68 | //Toggle reset 69 | clk = 0; 70 | rstn = 0; 71 | #1 72 | rstn = 1; 73 | 74 | endtask 75 | 76 | 77 | //=================================== 78 | // Here we deconstruct anything we 79 | // need after running the Unit Tests 80 | //=================================== 81 | task teardown(); 82 | svunit_ut.teardown(); 83 | /* Place Teardown Code Here */ 84 | 85 | endtask 86 | 87 | 88 | //=================================== 89 | // All tests are defined between the 90 | // SVUNIT_TESTS_BEGIN/END macros 91 | // 92 | // Each individual test must be 93 | // defined between `SVTEST(_NAME_) 94 | // `SVTEST_END 95 | // 96 | // i.e. 97 | // `SVTEST(mytest) 98 | // 99 | // `SVTEST_END 100 | //=================================== 101 | `SVUNIT_TESTS_BEGIN 102 | 103 | `SVTEST(test_interface) 104 | //Test that the interface to class works 105 | monitored_csrs uut = new(); 106 | 107 | uut.set_m_vif(csr_if); 108 | uut.run_monitor(); 109 | csr_if.csrs = {$bits(csr_if.csrs){1'bX}}; 110 | 111 | csr_if.csrs.cycle = 0; 112 | toggle_clock(); 113 | 114 | csr_if.csrs.cycle++; 115 | toggle_clock(); 116 | 117 | `FAIL_IF(uut.get_cycle() !== 1 ); 118 | 119 | csr_if.csrs.cycle++; 120 | toggle_clock(); 121 | `FAIL_IF(uut.get_cycle() !== 2 ); 122 | 123 | csr_if.csrs.cycle++; 124 | toggle_clock(); 125 | `FAIL_IF(uut.get_cycle() !== 3 ); 126 | 127 | `SVTEST_END 128 | 129 | 130 | `SVUNIT_TESTS_END 131 | 132 | task toggle_clock(); 133 | repeat (2) #5 clk = ~clk; 134 | endtask 135 | 136 | 137 | endmodule 138 | -------------------------------------------------------------------------------- /src/decoder.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `ifndef _DECODER_INCLUDE_ 25 | `define _DECODER_INCLUDE_ 26 | 27 | 28 | //Decode bits into a verif object model 29 | class decoder; 30 | 31 | bit[15:0] m_parcels[]; 32 | int unsigned m_parcel_index; 33 | int unsigned m_num_parcels; 34 | static bit m_strict = 0; 35 | static bit m_enable_c_type = 0; //Enable [C]ompressed instruction set 36 | 37 | static function int unsigned calc_num_parcels(bit[15:0] parcel0); 38 | if (parcel0[1:0] != 2'b11) begin 39 | return 1; 40 | end else if (parcel0[4:2] != 3'b111) begin 41 | return 2; 42 | end else if (m_strict) begin 43 | $fatal(1, $psprintf("UNUSPPORTED -- FUTURE, %016h",parcel0)); 44 | end 45 | endfunction // get_len 46 | 47 | //Decode how many parcels need to be fetched from the instruction length encoding 48 | //Returns the number of remaining parcels that need to be fetched and set (or use the 49 | //need_next_parcel()) 50 | virtual function int unsigned decode_len(bit[15:0] parcel0); 51 | m_num_parcels = decoder::calc_num_parcels(parcel0); 52 | m_parcels= new[m_num_parcels]; 53 | m_parcel_index = 0; 54 | m_parcels[m_parcel_index++] = parcel0; 55 | return m_num_parcels-1; 56 | endfunction 57 | 58 | virtual function bit need_next_parcel(); 59 | return (m_parcel_index < m_num_parcels); 60 | endfunction // has_next_parcel 61 | 62 | virtual function void set_next_parcel(bit[15:0] parcel); 63 | m_parcels[m_parcel_index++] = parcel; 64 | endfunction // set_next_parcel 65 | 66 | virtual function inst16 decode_inst16(bit[15:0] inst_arg); 67 | int more = decode_len(inst_arg); 68 | inst16 inst_item; 69 | 70 | //All zeros isn't an instruction, return null 71 | if (inst_arg == 0) begin 72 | return null; 73 | end 74 | 75 | if (more != 0) begin 76 | if (m_strict) begin 77 | $fatal(1,"undecodable inst"); 78 | end else begin 79 | return null; 80 | end 81 | end 82 | 83 | begin 84 | inst16_ciformat ci = new(); 85 | inst_item = ci; 86 | end 87 | return inst_item; //Null now.. 88 | 89 | endfunction // decode_inst16 90 | 91 | 92 | virtual function inst32 decode_inst32(bit[31:0] inst_arg); 93 | int remaining_parcels; 94 | inst_t inst; 95 | rvg_major_opcode_t rvg_major_opcode; 96 | rvg_format_t rvg_format; 97 | inst32 inst_item; 98 | 99 | //All zeros or F's isn't an instruction 100 | if (inst_arg == 0 || inst_arg == 'hffffffff) return null; 101 | 102 | //decode_len sets a bunch of m_ fields, remaining_parcels != 0 if 103 | //there are remaining_parcels parcels to the instruction 104 | remaining_parcels = decode_len(inst_arg[15:0]); 105 | 106 | if (remaining_parcels != 1) begin 107 | // this is not a 32 bit instruction... 108 | if (m_strict) begin 109 | $fatal(1,$psprintf("undecodable inst %h",inst_arg)); 110 | end else begin 111 | return null; 112 | end 113 | end 114 | 115 | while(need_next_parcel()) begin 116 | set_next_parcel(inst_arg[31:16]); //will need an update for >32 bit 117 | end 118 | 119 | if (m_num_parcels != 2) begin 120 | if (m_strict) begin 121 | $fatal(1,"num_parcels != 2"); 122 | end else begin 123 | return null; 124 | end 125 | end 126 | 127 | inst = {m_parcels[1],m_parcels[0]}; 128 | rvg_major_opcode = rvg_major_opcode_t'(inst[6:0]); 129 | rvg_format = rvg_format_by_major[rvg_major_opcode]; 130 | 131 | if (rvg_format == UNKNOWN) begin 132 | return null; 133 | end 134 | 135 | case (rvg_format) 136 | R: begin 137 | inst32_rformat r = new(inst); 138 | inst_item = r; 139 | end 140 | I: begin 141 | inst32_iformat i = new(inst); 142 | inst_item = i; 143 | end 144 | S: begin 145 | inst32_sformat s = new(inst); 146 | inst_item = s; 147 | end 148 | B: begin 149 | inst32_bformat b = new(inst); 150 | inst_item = b; 151 | end 152 | U: begin 153 | inst32_uformat u = new(inst); 154 | inst_item = u; 155 | end 156 | J: begin 157 | inst32_jformat j = new(inst); 158 | inst_item = j; 159 | end 160 | 161 | endcase 162 | 163 | return inst_item; 164 | 165 | endfunction // decode_inst 166 | 167 | endclass // decode 168 | 169 | `endif 170 | -------------------------------------------------------------------------------- /src/hex_file_analyzer.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | `ifndef _HEX_FILE_ANALYZER_INCLUDE_ 24 | `define _HEX_FILE_ANALYZER_INCLUDE_ 25 | 26 | /** 27 | * CLASS: hex_file_analyzer 28 | * 29 | * This class processes a RISCV HEX file or list of files. It decodes each 30 | * instruction in the file, prints out the derived instruction and samples 31 | * coverage for each instruction. 32 | * 33 | * This helps with testing/debugging the riscv-vip instruction and decode classes 34 | * (since the reverse decoded assembly can be compared to the *dump for the file). 35 | * This also provides an oportunity to analyze what is not possibly covered in the 36 | * execution of a hex file or a set of hex files. 37 | * 38 | * The coverage generated is more than what would be observed from the coverage of 39 | * executing the program since not every instruction in a hex file would normally 40 | * be executed. None-the-less, what is not covered using this analysis would not be 41 | * covered in the execution of the HEX file. 42 | * 43 | */ 44 | class hex_file_analyzer; 45 | parameter int unsigned NUM_MEM_BYTES = 2**20; 46 | logic [7:0] m_mem [0:NUM_MEM_BYTES-1]; //memory for the hex file 47 | decoder m_decoder; 48 | 49 | function new(); 50 | m_decoder = new(); 51 | endfunction // new 52 | 53 | //Zero the memory and load it from the given file name 54 | function automatic void load_mem_from_hex_file(string fn); 55 | m_mem = '{NUM_MEM_BYTES{'0}}; 56 | //$display("reading %s", fn); 57 | $readmemh(fn,m_mem); 58 | endfunction 59 | 60 | //file_list_fn is a list of space separatated paths to hex files 61 | virtual function void analyze_files(string file_list_fn); 62 | int unsigned file = $fopen(file_list_fn,"r"); 63 | int fscan_result; 64 | 65 | assert(file) else $fatal(-1, "bad file"); 66 | m_decoder.m_strict = 0; //Don't fatal on unsupported insts, get null instead 67 | 68 | while(!$feof(file)) begin 69 | string hex_fn; 70 | fscan_result = $fscanf(file, "%s ", hex_fn); 71 | if(hex_fn.len()>0) begin 72 | analyze_file(hex_fn); 73 | end 74 | end 75 | endfunction // analyze_files 76 | 77 | 78 | //Analyze a hex file 79 | virtual function void analyze_file(string hex_fn); 80 | load_mem_from_hex_file(hex_fn); 81 | 82 | for (int i=0;i<$size(m_mem);) begin 83 | bit [15:0] parcel; 84 | int unsigned rp; //remaining parcels 85 | inst32 i32; 86 | inst16 i16; 87 | int unsigned addr; 88 | 89 | parcel[7:0] = m_mem[i++]; 90 | parcel[15:8] = m_mem[i++]; 91 | rp = m_decoder.decode_len(parcel); 92 | 93 | if (rp == 0) begin 94 | i16= m_decoder.decode_inst16(parcel); 95 | addr = i-2; 96 | if (i16) begin 97 | $display("%H %04H 16bit instruction",addr,parcel); 98 | end 99 | end else if (rp == 1) begin 100 | inst_t inst_bits = {m_mem[i+1],m_mem[i],parcel}; 101 | addr = i-2; 102 | i+=2; 103 | i32 = m_decoder.decode_inst32(inst_bits); 104 | if (i32) begin 105 | $display("%H %s",addr, i32.to_string()); 106 | i32.sample_cov(); 107 | end 108 | end 109 | end 110 | endfunction // analyze_file 111 | 112 | 113 | endclass 114 | 115 | 116 | 117 | `endif 118 | -------------------------------------------------------------------------------- /src/hex_file_analyzer_unit_test.sv: -------------------------------------------------------------------------------- 1 | `include "svunit_defines.svh" 2 | 3 | module hex_file_analyzer_unit_test; 4 | import svunit_pkg::svunit_testcase; 5 | import riscv_vip_class_pkg::*; 6 | 7 | 8 | string name = "hex_file_analyzer_ut"; 9 | svunit_testcase svunit_ut; 10 | 11 | 12 | //simulator for some reason doesn't like a null virtual interfaces is classes at inital runtime. 13 | //this solves this... 14 | //regfile interface 15 | logic clk; 16 | logic rstn; 17 | 18 | riscv_vip_regfile_if regfile_if(.*); 19 | monitored_regfile my_regfile = new(); 20 | //CSR interface 21 | riscv_vip_csr_if csr_if(.*); 22 | monitored_csrs my_csrs = new(); 23 | 24 | 25 | //=================================== 26 | // This is the UUT that we're 27 | // running the Unit Tests on 28 | //=================================== 29 | hex_file_analyzer my_hex_file_analyzer; 30 | 31 | 32 | //=================================== 33 | // Build 34 | //=================================== 35 | function void build(); 36 | svunit_ut = new(name); 37 | 38 | my_hex_file_analyzer = new(/* New arguments if needed */); 39 | endfunction 40 | 41 | 42 | //=================================== 43 | // Setup for running the Unit Tests 44 | //=================================== 45 | task setup(); 46 | svunit_ut.setup(); 47 | /* Place Setup Code Here */ 48 | my_csrs.set_m_vif(csr_if); 49 | my_regfile.set_m_vif(regfile_if); 50 | 51 | endtask 52 | 53 | 54 | //=================================== 55 | // Here we deconstruct anything we 56 | // need after running the Unit Tests 57 | //=================================== 58 | task teardown(); 59 | svunit_ut.teardown(); 60 | /* Place Teardown Code Here */ 61 | 62 | endtask 63 | 64 | 65 | //=================================== 66 | // All tests are defined between the 67 | // SVUNIT_TESTS_BEGIN/END macros 68 | // 69 | // Each individual test must be 70 | // defined between `SVTEST(_NAME_) 71 | // `SVTEST_END 72 | // 73 | // i.e. 74 | // `SVTEST(mytest) 75 | // 76 | // `SVTEST_END 77 | //=================================== 78 | `SVUNIT_TESTS_BEGIN 79 | 80 | `SVTEST(analyze_hex_files) 81 | 82 | // Analyze all the HEX files generated from the RV32UI p assembly tests from the 83 | // RISC Foundation's riscv-tests project from github. The Makefile at 84 | // ../riscv_tests_hexgen generates these HEX files and also the DUMP files 85 | string HEX_FILES_FN = "../riscv_tests_hexgen/build/hex_files.txt"; 86 | my_hex_file_analyzer.analyze_files(HEX_FILES_FN); 87 | 88 | `SVTEST_END 89 | 90 | 91 | `SVUNIT_TESTS_END 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /src/reg_fetcher.svh: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | //############################################################### 5 | // 6 | // Licensed to the Apache Software Foundation (ASF) under one 7 | // or more contributor license agreements. See the NOTICE file 8 | // distributed with this work for additional information 9 | // regarding copyright ownership. The ASF licenses this file 10 | // to you under the Apache License, Version 2.0 (the 11 | // "License"); you may not use this file except in compliance 12 | // with the License. You may obtain a copy of the License at 13 | // 14 | // http://www.apache.org/licenses/LICENSE-2.0 15 | // 16 | // Unless required by applicable law or agreed to in writing, 17 | // software distributed under the License is distributed on an 18 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 19 | // KIND, either express or implied. See the License for the 20 | // specific language governing permissions and limitations 21 | // under the License. 22 | // 23 | //############################################################### 24 | 25 | `ifndef _REG_FETCHER_INCLUDED_ 26 | `define _REG_FETCHER_INCLUDED_ 27 | 28 | // This fetches the general purpose reg values for a given instruction 29 | // from the regfile 30 | class reg_fetcher; 31 | 32 | protected regfile m_regfile; 33 | 34 | virtual function void set_m_regfile(regfile rf); 35 | this.m_regfile = rf; 36 | endfunction : set_m_regfile 37 | 38 | virtual function void fetch_regs(inst32 i32); 39 | if (i32.has_rs1()) begin 40 | i32.set_rs1_val(m_regfile.get_x(i32.get_rs1())); 41 | end 42 | if (i32.has_rs2()) begin 43 | i32.set_rs2_val(m_regfile.get_x(i32.get_rs2())); 44 | end 45 | 46 | endfunction 47 | 48 | endclass 49 | 50 | `endif 51 | 52 | 53 | 54 | -------------------------------------------------------------------------------- /src/regfile.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `ifndef _REGFILE_INCLUDED_ 25 | `define _REGFILE_INCLUDED_ 26 | 27 | class regfile; 28 | 29 | protected x_regfile_array_t m_x_regfile_array; 30 | 31 | virtual function void set_m_x_regfile_array(x_regfile_array_t x); 32 | this.m_x_regfile_array = x; 33 | endfunction 34 | 35 | // Get m_reg_struct 36 | virtual function x_regfile_array_t get_m_x_regfile_array(); 37 | return m_x_regfile_array; 38 | endfunction 39 | 40 | virtual function xlen_t get_x(int unsigned i); 41 | //x[0] is always 0 42 | return ( i==0 ) ? 0 : m_x_regfile_array[i]; 43 | endfunction 44 | 45 | endclass 46 | 47 | //This class monitors the whitebox regfile and updates the model class. This 48 | //is intended for non UVM agent regfile implementations and will be updated when/if 49 | //things change to full uvm. Keep it simple for now 'caus it's going to change 50 | class monitored_regfile extends regfile; 51 | typedef virtual riscv_vip_regfile_if vif_t; 52 | 53 | vif_t m_vif; 54 | 55 | virtual function void set_m_vif(vif_t vif); 56 | m_vif = vif; 57 | endfunction 58 | 59 | virtual task run_monitor(); 60 | do_monitor_thread : fork 61 | do_monitor(); 62 | join_none 63 | endtask 64 | 65 | virtual protected task do_monitor(); 66 | @(posedge m_vif.rstn); 67 | forever begin 68 | @(posedge m_vif.clk iff m_x_regfile_array !== m_vif.x); 69 | //could just assign m_x_regfile_array to m_vif.x but may at some point 70 | //want to know exactly what changed.. 71 | foreach(m_vif.x[i]) begin 72 | if (m_x_regfile_array[i] !== m_vif.x[i]) begin 73 | m_x_regfile_array[i] = m_vif.x[i]; 74 | //do not break early, need to check all for changes 75 | end 76 | end 77 | end 78 | endtask // do_monitor 79 | 80 | 81 | endclass 82 | 83 | 84 | `endif -------------------------------------------------------------------------------- /src/regfile_unit_test.sv: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `include "svunit_defines.svh" 25 | `include "riscv_vip_pkg.sv" 26 | 27 | module regfile_unit_test; 28 | import svunit_pkg::svunit_testcase; 29 | import riscv_vip_pkg::*; 30 | import riscv_vip_class_pkg::*; 31 | 32 | 33 | string name = "regfile_ut"; 34 | svunit_testcase svunit_ut; 35 | 36 | logic clk; 37 | logic rstn; 38 | 39 | //UUT interface 40 | riscv_vip_regfile_if regfile_if(.*); 41 | 42 | //CSR interface 43 | //simulator for some reason doesn't like a null virtual interface in the csrs class 44 | //this solves this... 45 | riscv_vip_csr_if csr_if(.*); 46 | monitored_csrs my_csrs = new(); 47 | 48 | 49 | //=================================== 50 | // Build 51 | //=================================== 52 | function void build(); 53 | svunit_ut = new(name); 54 | endfunction 55 | 56 | 57 | //=================================== 58 | // Setup for running the Unit Tests 59 | //=================================== 60 | task setup(); 61 | svunit_ut.setup(); 62 | my_csrs.set_m_vif(csr_if); 63 | //Toggle reset 64 | clk = 0; 65 | rstn = 0; 66 | #1 67 | rstn = 1; 68 | 69 | endtask 70 | 71 | 72 | //=================================== 73 | // Here we deconstruct anything we 74 | // need after running the Unit Tests 75 | //=================================== 76 | task teardown(); 77 | svunit_ut.teardown(); 78 | /* Place Teardown Code Here */ 79 | 80 | endtask 81 | 82 | 83 | //=================================== 84 | // All tests are defined between the 85 | // SVUNIT_TESTS_BEGIN/END macros 86 | // 87 | // Each individual test must be 88 | // defined between `SVTEST(_NAME_) 89 | // `SVTEST_END 90 | // 91 | // i.e. 92 | // `SVTEST(mytest) 93 | // 94 | // `SVTEST_END 95 | //=================================== 96 | `SVUNIT_TESTS_BEGIN 97 | 98 | `SVTEST(test_interface) 99 | 100 | //Test that the wire interface to uut.get_x(i) works 101 | monitored_regfile uut = new(); 102 | 103 | uut.set_m_vif(regfile_if); 104 | 105 | 106 | uut.run_monitor(); 107 | 108 | //X out everything 109 | for(int i=1; i< 32; i++) begin 110 | regfile_if.x[i] = 'x; 111 | end 112 | 113 | //set reg 0 to all 1s... should fail at build time since this doesn't exist 114 | //Strangely with some simulators this seems a no-op... 115 | //regfile_if.x[0] = xlen_t'(-1); 116 | //toggle_clock(); 117 | 118 | `FAIL_IF(uut.get_x(0) !== 0); 119 | 120 | 121 | //set reg 1 to all 1s 122 | regfile_if.x[1] = xlen_t'(-1); 123 | toggle_clock(); 124 | 125 | `FAIL_IF(uut.get_x(1) !== {XLEN{1'b1}}) 126 | 127 | 128 | //set reg 31 and check it's what was set 129 | regfile_if.x[31] = xlen_t'('hCCCC_CCCC); 130 | toggle_clock(); 131 | 132 | `FAIL_IF(uut.get_x(31) !== 'hCCCC_CCCC); 133 | `FAIL_IF(uut.get_x(1) !== {XLEN{1'b1}}); 134 | 135 | for(int i=1; i< 32; i++) begin 136 | regfile_if.x[i] = i; 137 | toggle_clock(); 138 | end 139 | 140 | for(int i=1; i< 32; i++) begin 141 | `FAIL_IF_LOG(uut.get_x(i) !== i,$psprintf("x[%d]=%d",i,uut.get_x(i))) 142 | end 143 | 144 | `SVTEST_END 145 | 146 | 147 | `SVUNIT_TESTS_END 148 | 149 | task toggle_clock(); 150 | repeat (2) #5 clk = ~clk; 151 | endtask 152 | 153 | 154 | endmodule 155 | -------------------------------------------------------------------------------- /src/riscv_vip.do: -------------------------------------------------------------------------------- 1 | coverage save -onexit riscv_vip.ucdb -------------------------------------------------------------------------------- /src/riscv_vip.f: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | riscv_vip_csr_if.sv 24 | riscv_vip_regfile_if.sv 25 | riscv_vip_pkg.sv 26 | riscv_vip_class_pkg.sv 27 | 28 | 29 | -------------------------------------------------------------------------------- /src/riscv_vip_class_pkg.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | //############################################################### 4 | // 5 | // Licensed to the Apache Software Foundation (ASF) under one 6 | // or more contributor license agreements. See the NOTICE file 7 | // distributed with this work for additional information 8 | // regarding copyright ownership. The ASF licenses this file 9 | // to you under the Apache License, Version 2.0 (the 10 | // "License"); you may not use this file except in compliance 11 | // with the License. You may obtain a copy of the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in writing, 16 | // software distributed under the License is distributed on an 17 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 18 | // KIND, either express or implied. See the License for the 19 | // specific language governing permissions and limitations 20 | // under the License. 21 | // 22 | //############################################################### 23 | 24 | `ifndef _RISCV_VIP_CLASS_PKG_SV_ 25 | `define _RISCV_VIP_CLASS_PKG_SV_ 26 | 27 | package riscv_vip_class_pkg; 28 | 29 | import riscv_vip_pkg::*; 30 | `include "riscv_vip_defines.svh" 31 | 32 | 33 | //Forward class definitions 34 | typedef class decoder; 35 | typedef class inst16; 36 | typedef class inst16_ciformat; 37 | typedef class inst32; 38 | typedef class inst32_rformat; 39 | typedef class inst32_iformat; 40 | typedef class inst32_sformat; 41 | typedef class inst32_bformat; 42 | typedef class inst32_uformat; 43 | typedef class inst32_jformat; 44 | 45 | `include "instruction.svh" 46 | `include "decoder.svh" 47 | `include "regfile.svh" 48 | `include "reg_fetcher.svh" 49 | `include "csrs.svh" 50 | `include "inst_history.svh" 51 | `include "hex_file_analyzer.svh" 52 | 53 | endpackage 54 | 55 | `endif 56 | 57 | -------------------------------------------------------------------------------- /src/riscv_vip_csr_if.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | //############################################################### 4 | // 5 | // Licensed to the Apache Software Foundation (ASF) under one 6 | // or more contributor license agreements. See the NOTICE file 7 | // distributed with this work for additional information 8 | // regarding copyright ownership. The ASF licenses this file 9 | // to you under the Apache License, Version 2.0 (the 10 | // "License"); you may not use this file except in compliance 11 | // with the License. You may obtain a copy of the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in writing, 16 | // software distributed under the License is distributed on an 17 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 18 | // KIND, either express or implied. See the License for the 19 | // specific language governing permissions and limitations 20 | // under the License. 21 | // 22 | //############################################################### 23 | 24 | 25 | `ifndef _RISCV_VIP_CSR_IF_INCLUDED_ 26 | `define _RISCV_VIP_CSR_IF_INCLUDED_ 27 | 28 | `include "riscv_vip_pkg.sv" 29 | 30 | interface riscv_vip_csr_if (input clk, input rstn); 31 | 32 | riscv_vip_pkg::csrs_t csrs; 33 | 34 | endinterface 35 | 36 | `endif 37 | -------------------------------------------------------------------------------- /src/riscv_vip_defines.svh: -------------------------------------------------------------------------------- 1 | //############################################################### 2 | // 3 | // Licensed to the Apache Software Foundation (ASF) under one 4 | // or more contributor license agreements. See the NOTICE file 5 | // distributed with this work for additional information 6 | // regarding copyright ownership. The ASF licenses this file 7 | // to you under the Apache License, Version 2.0 (the 8 | // "License"); you may not use this file except in compliance 9 | // with the License. You may obtain a copy of the License at 10 | // 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | // 13 | // Unless required by applicable law or agreed to in writing, 14 | // software distributed under the License is distributed on an 15 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 16 | // KIND, either express or implied. See the License for the 17 | // specific language governing permissions and limitations 18 | // under the License. 19 | // 20 | //############################################################### 21 | 22 | //Some macros to limit duplicate code in creating coverage bins 23 | `define IMM_MAX_POS(x) {1'b0,{($bits(x)-1){1'b1}}} 24 | `define IMM_ALL_ONES(x) {$bits(x){1'b1}} 25 | `define IMM_MIN_NEG(x) {1'b1,{($bits(x)-1){1'b0}}} 26 | 27 | //Some defines to reduce duplicate code for a work around 28 | //wrt simulator support for set_covergroup_expression 29 | //(IEEE 1800-2012, 19.5.1.2) 30 | `define S_INSTS_LIST SB,SH,SW 31 | `define I_NONSPECIAL_INSTS_LIST JALR,LB,LH,LW,LBU,LHU,ADDI,SLTI,SLTIU,XORI,ANDI 32 | `define I_SHAMT_INSTS_LIST SLLI, SRLI, SRAI 33 | `define B_INSTS_LIST BEQ, BNE, BLT, BGE, BLTU, BGEU 34 | `define U_INSTS_LIST LUI,AUIPC 35 | `define J_INSTS_LIST JAL 36 | `define R_INSTS_LIST ADD,SUB,SLL,SLT,SLTU,XOR,SRL,SRA,OR,AND 37 | `define INSTS_WITH_NO_RS_LIST `U_INSTS_LIST,`J_INSTS_LIST,FENCE,FENCE_I,ECALL,EBREAK,CSRRWI,CSRRSI,CSRRCI 38 | `define INSTS_W_RS2_LIST `B_INSTS_LIST,`S_INSTS_LIST,`R_INSTS_LIST 39 | `define INSTS_W_NO_RD_LIST `B_INSTS_LIST,`S_INSTS_LIST, FENCE,ECALL,EBREAK 40 | `define INSTS_W_RD_RS1_RS2_LIST `R_INSTS_LIST 41 | 42 | `define BREADCRUMB(msg) $display("%m %s line %0d %s",`__FILE__,`__LINE__, msg) -------------------------------------------------------------------------------- /src/riscv_vip_inst_if.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | //############################################################### 4 | // 5 | // Licensed to the Apache Software Foundation (ASF) under one 6 | // or more contributor license agreements. See the NOTICE file 7 | // distributed with this work for additional information 8 | // regarding copyright ownership. The ASF licenses this file 9 | // to you under the Apache License, Version 2.0 (the 10 | // "License"); you may not use this file except in compliance 11 | // with the License. You may obtain a copy of the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in writing, 16 | // software distributed under the License is distributed on an 17 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 18 | // KIND, either express or implied. See the License for the 19 | // specific language governing permissions and limitations 20 | // under the License. 21 | // 22 | //############################################################### 23 | 24 | 25 | `ifndef _RISCV_VIP_INST_IF_INCLUDED_ 26 | `define _RISCV_VIP_INST_IF_INCLUDED_ 27 | 28 | interface riscv_vip_inst_if (input clk, input rstn); 29 | 30 | logic [31:0] curr_pc; 31 | logic [31:0] curr_inst; 32 | 33 | endinterface 34 | 35 | `endif 36 | -------------------------------------------------------------------------------- /src/riscv_vip_regfile_if.sv: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `ifndef _RISCV_VIP_REGFILE_IF_INCLUDED_ 25 | `define _RISCV_VIP_REGFILE_IF_INCLUDED_ 26 | 27 | import riscv_vip_pkg::*; 28 | 29 | /* This is a white box interface into the values of the register file. Making this 30 | * more transactional to use a rd/wr type memory i/f was considered but 31 | * different risc-v implementations may do it differently. Some may not even use 32 | * a regifile but simply use flip flops. The most flexible and simplist route for 33 | * now is to go with the raw values of the register values. At some point there 34 | * may be a need for a strobe or something to know when a given register is 35 | * read or written. 36 | */ 37 | interface riscv_vip_regfile_if (input clk, input rstn); 38 | 39 | //NOTE regfile is 1-31 and index 0 is not included since it's always zero 40 | riscv_vip_pkg::x_regfile_array_t x; 41 | 42 | endinterface 43 | 44 | `endif 45 | 46 | 47 | -------------------------------------------------------------------------------- /src/uvm/Makefile: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # 4 | # Licensed to the Apache Software Foundation (ASF) under one 5 | # or more contributor license agreements. See the NOTICE file 6 | # distributed with this work for additional information 7 | # regarding copyright ownership. The ASF licenses this file 8 | # to you under the Apache License, Version 2.0 (the 9 | # "License"); you may not use this file except in compliance 10 | # with the License. You may obtain a copy of the License at 11 | # 12 | # http://www.apache.org/licenses/LICENSE-2.0 13 | # 14 | # Unless required by applicable law or agreed to in writing, 15 | # software distributed under the License is distributed on an 16 | # "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | # KIND, either express or implied. See the License for the 18 | # specific language governing permissions and limitations 19 | # under the License. 20 | # 21 | ################################################################ 22 | 23 | 24 | 25 | SIMR := modelsim 26 | #SIMR := ius 27 | 28 | ifeq ($(SIMR), modelsim) 29 | SIMR_ARGS := -c_arg +cover -r "-do riscv_vip.do" 30 | endif 31 | ifeq ($(SIMR), ius) 32 | SIMR_ARGS := -c_arg "-coverage all -covoverwrite" 33 | endif 34 | 35 | 36 | agent_ut: 37 | runSVUnit -uvm -t i32_agent_unit_test.sv -s $(SIMR) -f riscv_vip_uvc.f $(SIMR_ARGS) 38 | 39 | env_ut: 40 | runSVUnit -uvm -t uvc_env_unit_test.sv -s $(SIMR) -f riscv_vip_uvc.f $(SIMR_ARGS) 41 | 42 | clean: 43 | rm -Rf work/* 44 | -------------------------------------------------------------------------------- /src/uvm/i32_agent.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `ifndef _I32_AGENT_INCLUDED_ 25 | `define _I32_AGENT_INCLUDED_ 26 | 27 | 28 | class i32_agent extends uvm_agent; 29 | 30 | protected uvm_active_passive_enum m_is_active = UVM_PASSIVE; 31 | i32_monitor m_monitor; 32 | virtual riscv_vip_inst_if m_vi; 33 | virtual riscv_vip_regfile_if m_rf_vi; 34 | virtual riscv_vip_csr_if m_csr_vi; 35 | monitored_regfile m_rf; //this is not a proper UVM monitor... whitebox... kind of hacked in for now 36 | monitored_csrs m_csr; //future... not really used (yet) 37 | int m_core_id = -1; 38 | 39 | uvm_analysis_port #(i32_item) m_mon_ap; 40 | 41 | `uvm_component_utils_begin(i32_agent) 42 | `uvm_component_utils_end 43 | 44 | function new(string name, uvm_component parent); 45 | super.new(name,parent); 46 | m_mon_ap = new("m_mon_ap", this); 47 | m_rf = new(); 48 | m_csr = new(); 49 | endfunction // new 50 | 51 | virtual function void build_phase(uvm_phase phase); 52 | bit has_vi; 53 | bit has_rf_vi; 54 | bit has_core_id; 55 | bit has_csr_vi; 56 | 57 | super.build_phase(phase); 58 | has_vi = uvm_config_db#(virtual riscv_vip_inst_if)::get(this, "", "m_vi", m_vi); 59 | has_rf_vi = uvm_config_db#(virtual riscv_vip_regfile_if)::get(this, "", "m_rf_vi", m_rf_vi); 60 | has_core_id = uvm_config_db#(int)::get(this, "", "m_core_id", m_core_id); 61 | has_csr_vi = uvm_config_db#(virtual riscv_vip_csr_if)::get(this, "", "m_csr_vi", m_csr_vi); 62 | 63 | `uvm_info("i32_agent"," build_phase() called",UVM_LOW); 64 | m_monitor = i32_monitor::type_id::create("m_monitor",this); 65 | assert(has_vi) else `uvm_fatal("i32_agent","!has_vi m_vi not in config_db"); 66 | assert (has_rf_vi) else `uvm_fatal("i32_agent","!has_rf_vi, m_rf_vi not in config_db"); 67 | assert (has_core_id) else `uvm_fatal("i32_agent","!has_core_id, m_core_id not in config_db"); 68 | assert (has_csr_vi) else `uvm_fatal("i32_agent","!has_csr_vi, m_csr_vi not in config_db"); 69 | 70 | m_monitor.m_core_id = m_core_id; 71 | m_monitor.m_vi = m_vi; 72 | m_rf.set_m_vif(m_rf_vi); 73 | m_csr.set_m_vif(m_csr_vi); 74 | 75 | endfunction // build_phase 76 | 77 | virtual function void connect_phase(uvm_phase phase); 78 | assert(m_mon_ap) else $fatal("missing m_mon_ap"); 79 | m_monitor.m_ap.connect(m_mon_ap); 80 | m_monitor.m_reg_fetcher.set_m_regfile(m_rf); 81 | endfunction // connect_phase 82 | 83 | virtual task run_phase(uvm_phase phase); 84 | `uvm_info("i32_agent"," run_phase() called",UVM_LOW); 85 | m_rf.run_monitor(); 86 | endtask // run_phase 87 | 88 | 89 | 90 | endclass 91 | 92 | 93 | `endif 94 | -------------------------------------------------------------------------------- /src/uvm/i32_cov_subscriber.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | `ifndef _I32_COV_SUB_INCLUDED_ 24 | `define _I32_COV_SUB_INCLUDED_ 25 | 26 | 27 | class i32_cov_subscriber extends uvm_subscriber#(i32_item); 28 | 29 | 30 | `uvm_component_utils_begin(i32_cov_subscriber) 31 | `uvm_component_utils_end 32 | 33 | //---------------------------------------------------------------------------- 34 | // new 35 | //------------------------------------------------------------------ 36 | function new(string name, uvm_component parent = null); 37 | super.new(name,parent); 38 | endfunction 39 | 40 | //---------------------------------------------------------------------------- 41 | // write 42 | //------------------------------------------------------------------ 43 | function void write(i32_item t); 44 | string inst_str; 45 | inst_str = (t.m_inst) ? 46 | t.m_inst.to_string() : 47 | $psprintf("%08H unknown",t.m_inst_bits); 48 | 49 | `uvm_info(get_full_name(), $sformatf("receiving %s",inst_str), UVM_HIGH) 50 | 51 | if (t.m_inst) begin 52 | t.m_inst.sample_cov(); 53 | end 54 | 55 | endfunction 56 | 57 | endclass : i32_cov_subscriber 58 | 59 | `endif // *_INCLUDED_ 60 | -------------------------------------------------------------------------------- /src/uvm/i32_item.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | `ifndef _I32_ITEM_INCLUDED_ 24 | `define _I32_ITEM_INCLUDED_ 25 | 26 | 27 | class i32_item extends uvm_sequence_item; 28 | inst32 m_inst; 29 | rv_addr_t m_addr; 30 | inst_t m_inst_bits; //31:0 31 | 32 | `uvm_object_utils_begin(i32_item) 33 | `uvm_object_utils_end 34 | 35 | function new(string name ="i32_item"); 36 | super.new(name); 37 | endfunction // new 38 | 39 | virtual function void do_print(uvm_printer printer); 40 | printer.print_int("m_addr",m_addr,$bits(m_addr)); 41 | printer.print_string("m_inst",m_inst.to_string()); 42 | endfunction 43 | 44 | 45 | endclass 46 | 47 | 48 | `endif 49 | -------------------------------------------------------------------------------- /src/uvm/i32_monitor.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `ifndef _I32_MONITOR_INCLUDED_ 25 | `define _I32_MONITOR_INCLUDED_ 26 | 27 | 28 | class i32_monitor extends uvm_monitor; 29 | 30 | const static string TRACKER_FN = "riscv_tracker_%0d.log"; 31 | int m_core_id = -1; 32 | virtual riscv_vip_inst_if m_vi; 33 | decoder m_decoder; 34 | reg_fetcher m_reg_fetcher; 35 | int m_tracker_file; 36 | logic [31:0] m_last_pc = 'hFFFFFFFE; 37 | i32_item m_item; 38 | int unsigned m_cycle = 0; 39 | 40 | uvm_analysis_port#(i32_item) m_ap; 41 | 42 | `uvm_component_utils_begin(i32_monitor) 43 | `uvm_component_utils_end 44 | 45 | function new(string name, uvm_component parent); 46 | super.new(name,parent); 47 | m_ap = new("m_item_aport", this); 48 | endfunction // new 49 | 50 | virtual function void build_phase(uvm_phase phase); 51 | super.build_phase(phase); 52 | m_decoder = new(); 53 | m_reg_fetcher = new(); 54 | init_tracker(); 55 | endfunction 56 | 57 | virtual task run_phase(uvm_phase phase); 58 | fork 59 | do_monitor(); 60 | join_none 61 | endtask // run_phase 62 | 63 | virtual protected task do_monitor(); 64 | event do_trasact_e; 65 | 66 | @(posedge m_vi.rstn); 67 | //Two processes synced with an event to overcome race possibility 68 | //between posedge clk for i32_monitor and monitored_regfile in 69 | //grabbing register file values for decoded instruction 70 | fork 71 | forever begin 72 | @(posedge m_vi.clk); 73 | m_cycle++; 74 | end 75 | forever begin 76 | @(posedge m_vi.clk iff m_vi.curr_pc !== m_last_pc); 77 | ->do_trasact_e; 78 | m_last_pc = m_vi.curr_pc; 79 | end 80 | forever begin 81 | @( do_trasact_e ); 82 | transact(); 83 | end 84 | join_none 85 | endtask // do_monitor 86 | 87 | virtual function void report_phase(uvm_phase phase); 88 | end_tracker(); 89 | endfunction 90 | 91 | virtual protected function void transact(); 92 | i32_item item = i32_item::type_id::create("item",this); 93 | item.m_inst = m_decoder.decode_inst32(m_vi.curr_inst); 94 | 95 | if( item.m_inst != null ) begin 96 | m_reg_fetcher.fetch_regs(item.m_inst); //associate the reg values w/ instruction 97 | item.m_inst.m_cycle = m_cycle; //needed by the inst_history 98 | end 99 | 100 | item.m_addr = m_vi.curr_pc; 101 | item.m_inst_bits = m_vi.curr_inst; 102 | m_item = item; 103 | track_item(); 104 | m_ap.write(item); 105 | endfunction // transact 106 | 107 | 108 | virtual function void init_tracker(); 109 | string tracker_fn; 110 | assert(m_core_id != -1) else `uvm_fatal("MON","m_core_id not set"); 111 | tracker_fn = $psprintf(TRACKER_FN,m_core_id); 112 | m_tracker_file = $fopen(tracker_fn); 113 | endfunction // init_tracker 114 | 115 | virtual function void end_tracker(); 116 | $fclose(m_tracker_file); 117 | endfunction 118 | 119 | virtual function void track_item(); 120 | string inst_str; 121 | inst_str = (m_item.m_inst) ? 122 | m_item.m_inst.to_string() : 123 | $psprintf("%08H unknown",m_item.m_inst_bits); 124 | $fdisplay(m_tracker_file, $psprintf("%0t %08H %s", $time, m_item.m_addr, inst_str)); 125 | endfunction 126 | 127 | endclass 128 | 129 | `endif 130 | -------------------------------------------------------------------------------- /src/uvm/inst_history_subscriber.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | `ifndef _INST_HISTORY_COV_SUB_INCLUDED_ 24 | `define _INST_HISTORY_COV_SUB_INCLUDED_ 25 | 26 | 27 | class inst_history_subscriber extends uvm_subscriber#(i32_item); 28 | 29 | inst_history m_inst_history; 30 | 31 | `uvm_component_utils_begin(inst_history_subscriber) 32 | `uvm_component_utils_end 33 | 34 | //---------------------------------------------------------------------------- 35 | // new 36 | //------------------------------------------------------------------ 37 | function new(string name, uvm_component parent = null); 38 | super.new(name,parent); 39 | endfunction 40 | 41 | virtual function void build_phase(uvm_phase phase); 42 | super.build_phase(phase); 43 | m_inst_history = new(); 44 | endfunction 45 | 46 | //---------------------------------------------------------------------------- 47 | // write 48 | //------------------------------------------------------------------ 49 | function void write(i32_item t); 50 | string inst_str; 51 | inst_str = (t.m_inst) ? 52 | t.m_inst.to_string() : 53 | $psprintf("%08H unknown",t.m_inst_bits); 54 | 55 | `uvm_info(get_full_name(), $sformatf("receiving %s",inst_str), UVM_HIGH) 56 | 57 | if (t.m_inst) begin 58 | m_inst_history.commit_inst(t.m_inst); 59 | end 60 | 61 | endfunction 62 | 63 | endclass : inst_history_subscriber 64 | 65 | `endif // *_INCLUDED_ 66 | -------------------------------------------------------------------------------- /src/uvm/riscv_vip_uvc.f: -------------------------------------------------------------------------------- 1 | +incdir+.. 2 | ../riscv_vip_pkg.sv 3 | ../riscv_vip_class_pkg.sv 4 | riscv_vip_uvc_pkg.sv 5 | 6 | 7 | -------------------------------------------------------------------------------- /src/uvm/riscv_vip_uvc_pkg.sv: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `ifndef _RISCV_VIP_UVC_PKG_SV_ 25 | `define _RISCV_VIP_UVC_PKG_SV_ 26 | 27 | `include "riscv_vip_inst_if.sv" 28 | `include "riscv_vip_regfile_if.sv" 29 | `include "riscv_vip_csr_if.sv" 30 | 31 | package riscv_vip_uvc_pkg; 32 | 33 | import uvm_pkg::*; 34 | `include "uvm_macros.svh" 35 | 36 | import riscv_vip_pkg::*; 37 | import riscv_vip_class_pkg::*; 38 | 39 | `include "i32_item.svh" 40 | `include "i32_monitor.svh" 41 | `include "i32_agent.svh" 42 | `include "i32_cov_subscriber.svh" 43 | `include "inst_history_subscriber.svh" 44 | `include "uvc_env.svh" 45 | 46 | endpackage 47 | 48 | `endif 49 | 50 | -------------------------------------------------------------------------------- /src/uvm/test/Makefile: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # 4 | # Licensed to the Apache Software Foundation (ASF) under one 5 | # or more contributor license agreements. See the NOTICE file 6 | # distributed with this work for additional information 7 | # regarding copyright ownership. The ASF licenses this file 8 | # to you under the Apache License, Version 2.0 (the 9 | # "License"); you may not use this file except in compliance 10 | # with the License. You may obtain a copy of the License at 11 | # 12 | # http://www.apache.org/licenses/LICENSE-2.0 13 | # 14 | # Unless required by applicable law or agreed to in writing, 15 | # software distributed under the License is distributed on an 16 | # "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | # KIND, either express or implied. See the License for the 18 | # specific language governing permissions and limitations 19 | # under the License. 20 | # 21 | ################################################################ 22 | 23 | 24 | 25 | SIMR := modelsim 26 | #SIMR := ius 27 | 28 | ifeq ($(SIMR), modelsim) 29 | SIMR_ARGS := -c_arg +cover -r "-do riscv_vip.do" 30 | endif 31 | ifeq ($(SIMR), ius) 32 | SIMR_ARGS := -c_arg "-coverage all -covoverwrite" 33 | endif 34 | 35 | 36 | test_ut: 37 | runSVUnit -uvm -t riscv_vip_base_test_unit_test.sv -s $(SIMR) -f riscv_vip_test.f $(SIMR_ARGS) 38 | 39 | clean: 40 | rm -Rf work/* 41 | -------------------------------------------------------------------------------- /src/uvm/test/riscv_vip_base_test.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | `ifndef _RISCV_VIP_BASE_TEST_INCLUDED_ 24 | `define _RISCV_VIP_BASE_TEST_INCLUDED_ 25 | 26 | class riscv_vip_base_test extends uvm_test; 27 | 28 | //------------------------------------------------------------------ 29 | // component sub-items / fields 30 | //-------------------------------------------------------- 31 | riscv_vip_uvc_pkg::uvc_env m_uvc_env; 32 | 33 | //------------------------------------------------------------------ 34 | // UVM macros 35 | //-------------------------------------------------------- 36 | `uvm_component_utils_begin(riscv_vip_base_test) 37 | `uvm_field_object(m_uvc_env, UVM_ALL_ON) 38 | `uvm_component_utils_end 39 | 40 | 41 | //---------------------------------------------------------------------------- 42 | // new 43 | //------------------------------------------------------------------ 44 | function new(string name, uvm_component parent=null); 45 | super.new(name, parent); 46 | endfunction 47 | 48 | //---------------------------------------------------------------------------- 49 | // build_phase 50 | //------------------------------------------------------------------ 51 | virtual function void build_phase(uvm_phase phase); 52 | super.build_phase(phase); 53 | m_uvc_env = uvc_env::type_id::create("m_uvc_env",this); 54 | endfunction : build_phase 55 | 56 | 57 | function void end_of_elaboration(); 58 | uvm_report_info(get_full_name(),"end_of_elaboration", UVM_LOW); 59 | print(); 60 | endfunction 61 | 62 | 63 | task run_phase(uvm_phase phase); 64 | phase.raise_objection(this); 65 | #5000000; 66 | phase.drop_objection(this); 67 | endtask : run_phase 68 | 69 | endclass : riscv_vip_base_test 70 | 71 | `endif // _RISCV_VIP_BASE_TEST_INCLUDED_ 72 | -------------------------------------------------------------------------------- /src/uvm/test/riscv_vip_test.f: -------------------------------------------------------------------------------- 1 | +incdir+../.. 2 | +incdir+.. 3 | ../../riscv_vip_pkg.sv 4 | ../../riscv_vip_class_pkg.sv 5 | ../riscv_vip_uvc_pkg.sv 6 | riscv_vip_test_pkg.sv 7 | 8 | 9 | -------------------------------------------------------------------------------- /src/uvm/test/riscv_vip_test_pkg.sv: -------------------------------------------------------------------------------- 1 | 2 | 3 | //############################################################### 4 | // 5 | // Licensed to the Apache Software Foundation (ASF) under one 6 | // or more contributor license agreements. See the NOTICE file 7 | // distributed with this work for additional information 8 | // regarding copyright ownership. The ASF licenses this file 9 | // to you under the Apache License, Version 2.0 (the 10 | // "License"); you may not use this file except in compliance 11 | // with the License. You may obtain a copy of the License at 12 | // 13 | // http://www.apache.org/licenses/LICENSE-2.0 14 | // 15 | // Unless required by applicable law or agreed to in writing, 16 | // software distributed under the License is distributed on an 17 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 18 | // KIND, either express or implied. See the License for the 19 | // specific language governing permissions and limitations 20 | // under the License. 21 | // 22 | //############################################################### 23 | 24 | `ifndef _RISCV_VIP_TEST_PKG_INCLUDED_ 25 | `define _RISCV_VIP_TEST_PKG_INCLUDED_ 26 | 27 | package riscv_vip_test_pkg; 28 | 29 | //------------------------------------------------------------------ 30 | // UVM packages and macros 31 | //-------------------------------------------------------- 32 | import uvm_pkg::*; 33 | `include "uvm_macros.svh" 34 | 35 | //------------------------------------------------------------------ 36 | // Packages used 37 | //-------------------------------------------------------- 38 | // design packages 39 | import riscv_vip_uvc_pkg::*; 40 | 41 | //-------------------------------------------------------- 42 | //System level components. 43 | 44 | //------------------------------------------------------------------ 45 | // Package components 46 | //-------------------------------------------------------- 47 | `include "riscv_vip_base_test.svh" 48 | 49 | 50 | endpackage : riscv_vip_test_pkg 51 | 52 | `endif // _RISCV_VIP_TEST_PKG_INCLUDED_ 53 | -------------------------------------------------------------------------------- /src/uvm/uvc_env.svh: -------------------------------------------------------------------------------- 1 | 2 | //############################################################### 3 | // 4 | // Licensed to the Apache Software Foundation (ASF) under one 5 | // or more contributor license agreements. See the NOTICE file 6 | // distributed with this work for additional information 7 | // regarding copyright ownership. The ASF licenses this file 8 | // to you under the Apache License, Version 2.0 (the 9 | // "License"); you may not use this file except in compliance 10 | // with the License. You may obtain a copy of the License at 11 | // 12 | // http://www.apache.org/licenses/LICENSE-2.0 13 | // 14 | // Unless required by applicable law or agreed to in writing, 15 | // software distributed under the License is distributed on an 16 | // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 17 | // KIND, either express or implied. See the License for the 18 | // specific language governing permissions and limitations 19 | // under the License. 20 | // 21 | //############################################################### 22 | 23 | 24 | `ifndef _UVC_ENV_INCLUDED_ 25 | `define _UVC_ENV_INCLUDED_ 26 | 27 | `ifndef NUM_CORES 28 | `define NUM_CORES 1 29 | `endif 30 | 31 | class uvc_env extends uvm_env; 32 | 33 | i32_agent m_i32_agent[`NUM_CORES]; 34 | i32_cov_subscriber m_cov; 35 | inst_history_subscriber m_hist; //need to eventually be per core 36 | 37 | //------------------------------------------------------------------ 38 | // environment UVM components 39 | //-------------------------------------------------------- 40 | uvm_table_printer printer; 41 | 42 | //------------------------------------------------------------------ 43 | // UVM macros 44 | //-------------------------------------------------------- 45 | `uvm_component_utils_begin(uvc_env) 46 | `uvm_field_sarray_object(m_i32_agent, UVM_ALL_ON) 47 | `uvm_field_object(m_cov, UVM_ALL_ON) 48 | `uvm_field_object(m_hist, UVM_ALL_ON) 49 | `uvm_component_utils_end 50 | 51 | //---------------------------------------------------------------------------- 52 | // new 53 | //------------------------------------------------------------------ 54 | function new (string name, uvm_component parent); 55 | super.new(name, parent); 56 | printer = new(); 57 | endfunction 58 | 59 | //---------------------------------------------------------------------------- 60 | // externally defined tasks and functions 61 | //------------------------------------------------------------------ 62 | extern virtual function void build_phase(uvm_phase phase); 63 | extern virtual function void connect_phase(uvm_phase phase); 64 | extern virtual task run_phase(uvm_phase phase); 65 | 66 | endclass : uvc_env 67 | 68 | //============================================================================== 69 | // externally defined tasks and functions 70 | //==================================================================== 71 | function void uvc_env::build_phase(uvm_phase phase); 72 | 73 | super.build_phase(phase); 74 | //Create coverage instantiation 75 | m_cov = i32_cov_subscriber::type_id::create("cov",this); 76 | m_hist = inst_history_subscriber::type_id::create("m_hist",this); 77 | for (int i = 0; i < `NUM_CORES; i++) begin : gen_cores 78 | //RISCV_VIP 79 | begin 80 | string i32_name = $psprintf("m_i32_agent[%0d]",i); 81 | if(uvm_config_db#(virtual riscv_vip_inst_if)::exists(this, i32_name, "m_vi")) begin 82 | m_i32_agent[i] = i32_agent::type_id::create(i32_name,this); 83 | `uvm_info("UVC_ENV", $sformatf("At Path: %s - Build Phase: Created i32 interface instance",get_full_name()), UVM_NONE) 84 | end else begin 85 | `uvm_error("build_phase", "Failed to find riscv_vip_if in factory") 86 | end 87 | end 88 | 89 | end : gen_cores 90 | 91 | 92 | endfunction : build_phase 93 | 94 | //==================================================================== 95 | function void uvc_env::connect_phase(uvm_phase phase); 96 | super.connect_phase(phase); 97 | for (int i = 0; i < `NUM_CORES; i++) begin : gen_cores 98 | m_i32_agent[i].m_monitor.m_ap.connect(m_cov.analysis_export); 99 | m_i32_agent[i].m_monitor.m_ap.connect(m_hist.analysis_export); 100 | end : gen_cores 101 | endfunction : connect_phase 102 | 103 | 104 | //==================================================================== 105 | task uvc_env::run_phase(uvm_phase phase); 106 | super.run_phase(phase); 107 | endtask : run_phase 108 | 109 | 110 | `endif // _UVC_ENV_INCLUDED_ 111 | --------------------------------------------------------------------------------