├── 1.getting started ├── 01.getting_started.v └── 02.output_zero.v ├── 2.verilog language ├── 03.simple_wire.v ├── 04.four_wires.v ├── 05.inverter.v ├── 06.and_gate.v ├── 07.nor_gate.v ├── 08.xnor_gate.v ├── 09.declaring_wires.v ├── 10.7458_chip.v ├── 11.vectors.v ├── 12.vectors_in_more_detail.v ├── 13.vector_part_select.v ├── 14.bitwise_operators.v ├── 15.four_input_gates.v ├── 16.vector_concatenation_operator.v ├── 17.vector_reversal_1.v ├── 18.replication_operator.v ├── 19.more_replication.v ├── 20.modules.v ├── 21.connecting_ports_by_position.v ├── 22.connecting_ports_by_name.v ├── 23.three_modules.v ├── 24.modules_and_vectors.v ├── 25.adder1.v ├── 26.adder2.v ├── 27.carry_selected_adder.v ├── 28.adder_substractor.v ├── 29.always_block_comb.v ├── 30.always_block_clk.v ├── 31.if_statement.v ├── 32.if_statement_latches.v ├── 33.case_statement.v ├── 34.priority_encoder.v ├── 35.priority_encoder_with_casez.v ├── 36.avoiding_latches.v ├── 37.conditional_ternary_operator.v ├── 38.reduction_operator.v ├── 39.even_wider_gates.v ├── 40.vector_reversal2.v ├── 41.255bit_population_count.v ├── 42.100-bit_binary_adder_2.v └── 43.100_digit_BCD_adder.v ├── 3.circuits ├── combinational logic │ ├── 44.wire.v │ ├── 45.gnd.v │ ├── 46.nor.v │ ├── 47.another_gate.v │ ├── 48.two_gates.v │ ├── 49.more_logic_gates.v │ ├── 50.7420chip.v │ ├── 51.truth_tables.v │ ├── 52.two-bit_equality.v │ ├── 53.simple_circuitA.v │ ├── 54.simple_circuitB.v │ ├── 55.combine_circuit_A_and_B.v │ ├── 56.ring_or_vibrate.v │ ├── 57.thermostat.v │ ├── 58.3-bit_population_count.v │ ├── 59.gates_and_vectors.v │ ├── 60.even_longer_vectors.v │ ├── 61.2-to-1_mux.v │ ├── 62.2-to-1_bus_mux.v │ ├── 63.9-to-1_mux.v │ ├── 64.256to1_mux.v │ ├── 65.256-to-1_4-bit_mux.v │ ├── 66.half_adder.v │ ├── 67.full_adder.v │ ├── 68.3-bit_binary_adder.v │ ├── 69.adder.v │ ├── 70.signed_addition_overflow.v │ ├── 71.100-bit_binary_adder.v │ ├── 72.4-digit_BCD_adder.v │ ├── 73.3-variable.v │ ├── 74.4-variable_1.v │ ├── 75.4-variable_2.v │ ├── 76.4-variable_3.v │ ├── 77.minimum_SOP_and_POS.v │ ├── 78.karnaugh_map_1.v │ ├── 79.karnaugh_map_2.v │ └── 80.k-map_with_mux.v └── sequential logic │ ├── 081.dff.v │ ├── 082.dffs.v │ ├── 083.dff_with_reset.v │ ├── 084.dff_with_reset_value.v │ ├── 085.dff_with_areset.v │ ├── 086.dff_with_byte_enable.v │ ├── 087.d-latch.v │ ├── 088.DFF_1.v │ ├── 089.DFF_2.v │ ├── 090.dff+gate.v │ ├── 091.mux_and_dff_1.v │ ├── 092.mux_and_dff_2.v │ ├── 093.dffs_and_gates.v │ ├── 094.create_circuit_from_truth_table.v │ ├── 095.detect_an_edge.v │ ├── 096.detect_both_edges.v │ ├── 097.edge_capture_register.v │ ├── 098.dual-edge_triggered_flipflop.v │ ├── 099.4-bit_binary_counter.v │ ├── 100.decade_counter.v │ ├── 101.decade_counter_again.v │ ├── 102.slow_decade_counter.v │ ├── 103.count1-12.v │ ├── 104.counter1000.v │ ├── 105.4-digit_decimal_counter.v │ ├── 106.12-hour_counter.v │ ├── 107.4-bit_shift-register.v │ ├── 108.left_right_rotator.v │ ├── 109.left_right_arith_shift_1-8.v │ ├── 110.5-bit_LFSR.v │ ├── 111.3-bit_LFSR.v │ ├── 112.32-bit_LFSR.v │ ├── 113.shift_register_1.v │ ├── 114.shift_register_2.v │ ├── 115.3-input_LUT.v │ ├── 116.rule_90.v │ ├── 117.rule_110.v │ ├── 118.conway's_game_of_life.v │ ├── 119.fsm1_1.v │ ├── 120.fsm1_2.v │ ├── 121.fsm2_1.v │ ├── 122.fsm2_2.v │ ├── 123.fsm3comb.v │ ├── 124.fsm3onehot.v │ ├── 125.fsm3_1.v │ ├── 126.fsm3_2.v │ ├── 127.design_a_moore_fsm.v │ ├── 128.lemmings1.v │ ├── 129.lemmings2.v │ ├── 130.lemmings3.v │ ├── 131.lemmings4.v │ ├── 132.one-hot_fsm.v │ ├── 133.PS2_packet_parser.v │ ├── 134.PS2_packet_parser_and_datapathe.v │ ├── 135.serial_receiver.v │ ├── 136.serial_receiver_and_datapathe.v │ ├── 137.serial_receiver_with_checking.v │ ├── 138.sequence_recognition.v │ ├── 139.design_a_mealy_fsm.v │ ├── 140.serial_two's_complementer_moore.v │ ├── 141.serial_two's_complementer_mealy.v │ ├── 142.Q3A_fsm.v │ ├── 143.Q3b_fsm.v │ ├── 144.Q3c_fsm.v │ ├── 145.Q6b.v │ ├── 146.Q6c.v │ ├── 147.Q6_fsm.v │ ├── 148.Q2a_fsm.v │ ├── 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