├── .gitignore ├── LICENSE ├── LatticeMico32ProcessorReferenceManual39.pdf ├── Module.manifest ├── README.md ├── build.gradle ├── certification.manifest └── data └── languages ├── lm32.cspec ├── lm32.ldefs ├── lm32.opinion ├── lm32.pspec ├── lm32.sinc ├── lm32_be.slaspec └── lm32_le.slaspec /.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | **/*.sla 3 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Jevin Sweval 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /LatticeMico32ProcessorReferenceManual39.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jevinskie/ghidra-lm32/5feb7bf29d4e25ba6cc6f2cc29c0deb042dc8612/LatticeMico32ProcessorReferenceManual39.pdf -------------------------------------------------------------------------------- /Module.manifest: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jevinskie/ghidra-lm32/5feb7bf29d4e25ba6cc6f2cc29c0deb042dc8612/Module.manifest -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ghidra-lm32 2 | LM32 processor module for Ghidra. Useful for AMD SMU reverse engineering. 3 | -------------------------------------------------------------------------------- /build.gradle: -------------------------------------------------------------------------------- 1 | /* ### 2 | * IP: GHIDRA 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" 17 | apply from: "$rootProject.projectDir/gradle/processorProject.gradle" 18 | apply plugin: 'eclipse' 19 | 20 | eclipse.project.name = 'Processors lm32' 21 | 22 | -------------------------------------------------------------------------------- /certification.manifest: -------------------------------------------------------------------------------- 1 | ##VERSION: 2.0 2 | Module.manifest||GHIDRA||||END| 3 | data/languages/lm32_be.slaspec||GHIDRA||||END| 4 | data/languages/lm32.cspec||GHIDRA||||END| 5 | data/languages/lm32.ldefs||GHIDRA||||END| 6 | data/languages/lm32_le.slaspec||GHIDRA||||END| 7 | data/languages/lm32.opinion||GHIDRA||||END| 8 | data/languages/lm32.pspec||GHIDRA||||END| 9 | data/languages/lm32.sinc||GHIDRA||||END| 10 | LatticeMico32ProcessorReferenceManual39.pdf||GHIDRA||||END| 11 | LICENSE||GHIDRA||||END| 12 | README.md||GHIDRA||||END| 13 | -------------------------------------------------------------------------------- /data/languages/lm32.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | -------------------------------------------------------------------------------- /data/languages/lm32.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 11 | LatticeMico32 BE 12 | 13 | 14 | 22 | LatticeMico32 LE 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /data/languages/lm32.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /data/languages/lm32.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /data/languages/lm32.sinc: -------------------------------------------------------------------------------- 1 | # sleigh specification file for LM32 2 | 3 | define endian=$(ENDIAN); 4 | define alignment=4; 5 | 6 | define space ram type=ram_space size=4 wordsize=1 default; 7 | define space register type=register_space size=4; 8 | 9 | # General Purpose Registers 10 | define register offset=0x1000 size=4 [ 11 | r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 12 | gp fp sp ra ea ba 13 | ]; 14 | 15 | # Control and Status Registers 16 | define register offset=0x2000 size=4 [ 17 | PC IE IM IP ICC DCC CC CFG EBA CFG2 18 | ]; 19 | 20 | # Debug Control and Status Registers 21 | define register offset=0x3000 size=4 [ 22 | DC DEBA JTX JRX BP0 BP1 BP2 BP3 WP0 WP1 WP2 WP3 23 | ]; 24 | 25 | define register offset=0x4000 size=4 contextreg; 26 | define context contextreg 27 | LRset = (1,1) noflow # 1 if the instruction before was a mov lr,pc 28 | ; 29 | 30 | define pcodeop software_interrupt; 31 | define pcodeop csr_write; 32 | define pcodeop csr_read; 33 | 34 | # 35 | # Tokens 36 | # 37 | 38 | define token opfields(32) 39 | b31 = (31, 31) 40 | op = (26, 31) 41 | op5 = (26, 30) 42 | reg0 = (21, 25) 43 | csr = (21, 25) 44 | reg1 = (16, 20) 45 | reg2 = (11, 15) 46 | imm16 = (0, 15) 47 | simm16 = (0, 15) signed 48 | imm26 = (0, 25) 49 | simm26 = (0, 25) signed 50 | imm5 = (0, 4) 51 | simm5 = (0, 4) signed 52 | z11 = (0, 10) 53 | z16 = (0, 16) 54 | ; 55 | 56 | attach variables [ reg0 reg1 reg2 ] [ 57 | r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 58 | gp fp sp ra ea ba 59 | ]; 60 | 61 | Rel16: reloc is simm16 [ reloc=inst_start+4*simm16; ] { 62 | export *:4 reloc; 63 | } 64 | 65 | Rel26: reloc is simm26 [ reloc=inst_start+4*simm26; ] { 66 | export *:4 reloc; 67 | } 68 | 69 | # RelSelf: reloc is b31=0 [ reloc=inst_start; ] { 70 | # export *:4 reloc; 71 | # } 72 | 73 | inst_fmt_ri: is_inst_fmt_ri is b31=0 [ is_inst_fmt_ri=1; ] { export *:1 is_inst_fmt_ri; } 74 | inst_fmt_i: is_inst_fmt_i is b31=1 & (op5=0x18 | op5=0x1e) [ is_inst_fmt_i=1; ] { export *:1 is_inst_fmt_i; } 75 | inst_fmt_cr: is_inst_fmt_cr is b31=1 & (op5=0x04 | op5=0x14) [ is_inst_fmt_cr=1; ] { export *:1 is_inst_fmt_cr; } 76 | inst_fmt_rr: is_inst_fmt_rr is b31=1 & (op5!=0x18 & op5!=0x1e & op5!=0x04 & op5!=0x14) [ is_inst_fmt_rr = 1; ] { export *:1 is_inst_fmt_rr; } 77 | 78 | # inst_fmt_ri: is_inst_fmt_ri is b31=1 [ is_inst_fmt_ri=0; ] { export *:1 is_inst_fmt_ri; } 79 | # inst_fmt_ri: is_inst_fmt_ri is b31=0 [ is_inst_fmt_ri=1; ] { export *:1 is_inst_fmt_ri; } 80 | # inst_fmt_ri: "ri1" is b31=0 { export 1:1; } 81 | # inst_fmt_i: { export 0:1; } 82 | # inst_fmt_i: is b31=1 & (op5=0x18 | op5=0x1e) { export 1:1; } 83 | # inst_fmt_cr: { export 0:1; } 84 | # inst_fmt_cr: is b31=1 & (op5=0x04 | op5=0x14) { export 1:1; } 85 | # inst_fmt_rr: { export zext(inst_fmt_ri | inst_fmt_i | inst_fmt_cr) == 0):1; } 86 | 87 | 88 | 89 | gpr0: reg0 is reg0 { export reg0; } 90 | gpr0: "0" is reg0=0 { export 0:4; } # Special case 91 | 92 | gpr1: reg1 is reg1 { export reg1; } 93 | gpr1: "0" is reg1=0 { export 0:4; } # Special case 94 | 95 | gpr2: reg2 is reg2 { export reg2; } 96 | gpr2: "0" is reg2=0 { export 0:4; } # Special case 97 | 98 | # inst_fmt_ri: "ri0" is inst_fmt_ri { export 0:1; } 99 | # inst_fmt_ri: "ri1" is b31=0 { export 1:1; } 100 | # inst_fmt_i: { export 0:1; } 101 | # inst_fmt_i: is b31=1 & (op5=0x18 | op5=0x1e) { export 1:1; } 102 | # inst_fmt_cr: { export 0:1; } 103 | # inst_fmt_cr: is b31=1 & (op5=0x04 | op5=0x14) { export 1:1; } 104 | # inst_fmt_rr: { export zext(inst_fmt_ri | inst_fmt_i | inst_fmt_cr) == 0):1; } 105 | 106 | # rX: reg2 is reg2 & inst_fmt_rr { export reg2; } 107 | # rY: reg0 is reg0 & inst_fmt_rr { export reg0; } 108 | # rZ: reg1 is reg1 & inst_fmt_rr { export reg1; } 109 | 110 | # rX: reg1 is reg1 & inst_fmt_ri { export reg1; } 111 | # rY: reg0 is reg0 & inst_fmt_ri { export reg0; } 112 | 113 | # rX: reg2 is reg1 & inst_fmt_cr { export reg2; } 114 | 115 | rX: reg2 is reg2 & inst_fmt_rr & op!=0x30 & op!=0x36 { export reg2; } 116 | rX: "0" is reg2=0 & inst_fmt_rr & op!=0x30 & op!=0x36 { export 0:4; } 117 | rX: reg0 is reg0 & inst_fmt_rr & (op=0x30 | op=0x36) { export reg0; } # b rX 118 | rX: "0" is reg0=0 & inst_fmt_rr & (op=0x30 | op=0x36) { export 0:4; } # b rX where rX = r0 119 | rY: reg0 is reg0 & inst_fmt_rr { export reg0; } 120 | rY: "0" is reg0=0 & inst_fmt_rr { export 0:4; } 121 | rZ: reg1 is reg1 & inst_fmt_rr { export reg1; } 122 | rZ: "0" is reg1=0 & inst_fmt_rr { export 0:4; } 123 | 124 | rX: reg1 is reg1 & inst_fmt_ri & op!=0x03 & op!=0x0C & op!=0x16 { export reg1; } 125 | rX: "0" is reg1=0 & inst_fmt_ri & op!=0x03 & op!=0x0C & op!=0x16 { export 0:4; } 126 | rY: reg0 is reg0 & inst_fmt_ri & op!=0x03 & op!=0x0C & op!=0x16 { export reg0; } 127 | rY: "0" is reg0=0 & inst_fmt_ri & op!=0x03 & op!=0x0C & op!=0x16 { export 0:4; } 128 | 129 | # store inst 130 | rX: reg0 is reg0 & inst_fmt_ri & (op=0x03 | op=0x0C | op=0x16) { export reg0; } 131 | rX: "0" is reg0=0 & inst_fmt_ri & (op=0x03 | op=0x0C | op=0x16) { export 0:4; } 132 | rY: reg1 is reg1 & inst_fmt_ri & (op=0x03 | op=0x0C | op=0x16) { export reg1; } 133 | rY: "0" is reg1=0 & inst_fmt_ri & (op=0x03 | op=0x0C | op=0x16) { export 0:4; } 134 | 135 | rX: reg2 is reg2 & inst_fmt_cr { export reg2; } 136 | rX: "0" is reg2=0 & inst_fmt_cr { export 0:4; } 137 | 138 | # 139 | # Instructions 140 | # 141 | 142 | :srui rX, rY, imm5 is op=0x00 & rX & rY & imm5 { 143 | rX = rY >> imm5; 144 | } 145 | 146 | :nori rX, rY, imm16 is op=0x01 & rX & rY & imm16 { 147 | rX = ~(rY | imm16); 148 | } 149 | 150 | :muli rX, rY, simm16 is op=0x02 & rX & rY & simm16 { 151 | rX = ((rY * simm16) & 0xFFFFFFFF); 152 | } 153 | 154 | :sh (rX+simm16), rY is op=0x03 & rX & rY & simm16 { 155 | local address = rX + simm16; 156 | *[ram]:2 address = rY:2; 157 | } 158 | 159 | :lb rX, (rY+simm16) is op=0x04 & rX & rY & simm16 { 160 | local address = rY + simm16; 161 | rX = sext(*[ram]:1 address); 162 | } 163 | 164 | :sri rX, rY, imm5 is op=0x05 & rX & rY & imm5 { 165 | rX = rY s>> imm5; 166 | } 167 | 168 | :xori rX, rY, imm16 is op=0x06 & rX & rY & imm16 { 169 | rX = rY ^ imm16; 170 | } 171 | 172 | :lh rX, (rY+simm16) is op=0x07 & rX & rY & simm16 { 173 | local address = rY + simm16; 174 | rX = sext(*[ram]:2 address); 175 | } 176 | 177 | :andi rX, rY, imm16 is op=0x08 & rX & rY & imm16 { 178 | rX = rY & imm16; 179 | } 180 | 181 | :xnori rX, rY, imm16 is op=0x09 & rX & rY & imm16 { 182 | rX = ~(rY ^ imm16); 183 | } 184 | 185 | :lw rX, (rY+simm16) is op=0x0A & rX & rY & simm16 { 186 | local address = rY + simm16; 187 | rX = *[ram]:4 address; 188 | } 189 | 190 | :lhu rX, (rY+simm16) is op=0x0B & rX & rY & simm16 { 191 | local address = rY + simm16; 192 | rX = zext(*[ram]:2 address); 193 | } 194 | 195 | :sb (rX+simm16), rY is op=0x0c & rX & rY & simm16 { 196 | local address = rX + simm16; 197 | *[ram]:1 address = rY:1; 198 | } 199 | 200 | # :addi rX, rY, simm16 is op=0x0D & rX & rY & simm16 { 201 | # # rX = rY + simm16; 202 | # # } 203 | 204 | # :addi rX, rY, simm16 is op=0x0D & rX & rY & simm16 { 205 | # # rX = rY + simm16; 206 | # # } 207 | 208 | :addi rX, rY, simm16 is op=0x0D & rX & rY & simm16 { 209 | rX = rY + simm16; 210 | } 211 | 212 | :mvi rX, simm16 is op=0x0D & rX & rY & simm16 & reg0=0 { 213 | rX = sext(simm16:2); 214 | } 215 | 216 | :nop is op=0x0D & rX & rY & reg0=0 & reg1=0 & simm16=0 { 217 | } 218 | 219 | :ori rX, rY, imm16 is op=0x0E & rX & rY & imm16 { 220 | rX = rY | imm16; 221 | } 222 | 223 | :sli rX, rY, imm5 is op=0x0F & rX & rY & imm5 { 224 | rX = rY << imm5; 225 | } 226 | 227 | :lbu rX, (rY+simm16) is op=0x10 & rX & rY & simm16 { 228 | local address = rY + simm16; 229 | rX = zext(*[ram]:1 address); 230 | } 231 | 232 | :be rY, rX Rel16 is op=0x11 & rX & rY & Rel16 { 233 | if (rY == rX) goto Rel16; 234 | } 235 | 236 | :bg rY, rX Rel16 is op=0x12 & rX & rY & Rel16 { 237 | if (rY s> rX) goto Rel16; 238 | } 239 | 240 | :bge rY, rX Rel16 is op=0x13 & rX & rY & Rel16 { 241 | if (rY s>= rX) goto Rel16; 242 | } 243 | 244 | :bgeu rY, rX Rel16 is op=0x14 & rX & rY & Rel16 { 245 | if (rY >= rX) goto Rel16; 246 | } 247 | 248 | :bgu rY, rX Rel16 is op=0x15 & rX & rY & Rel16 { 249 | if (rY > rX) goto Rel16; 250 | } 251 | 252 | :sw (rX+simm16), rY is op=0x16 & rX & rY & simm16 { 253 | local address = rX + simm16; 254 | *[ram]:4 address = rY; 255 | } 256 | 257 | :bne rY, rX Rel16 is op=0x17 & rX & rY & Rel16 { 258 | if (rY != rX) goto Rel16; 259 | } 260 | 261 | :andhi rX, rY, imm16 is op=0x18 & rX & rY & imm16 { 262 | rX = rY & (imm16 << 16); 263 | } 264 | 265 | 266 | :cmpei rX, rY, simm16 is op=0x19 & rX & rY & simm16 { 267 | rX = zext(rY:4 == sext(simm16:2)); 268 | } 269 | 270 | :cmpgi rX, rY, simm16 is op=0x1A & rX & rY & simm16 { 271 | rX = zext(rY:4 s> sext(simm16:2)); 272 | } 273 | 274 | :cmpgei rX, rY, simm16 is op=0x1B & rX & rY & simm16 { 275 | rX = zext(rY:4 s>= sext(simm16:2)); 276 | } 277 | 278 | :cmpgeui rX, rY, imm16 is op=0x1C & rX & rY & imm16 { 279 | rX = zext(rY:4 >= zext(imm16:2)); 280 | } 281 | 282 | :cmpgui rX, rY, imm16 is op=0x1D & rX & rY & imm16 { 283 | rX = zext(rY:4 > zext(imm16:2)); 284 | } 285 | 286 | :orhi rX, rY, imm16 is op=0x1E & rX & rY & imm16 { 287 | rX = rY | (imm16 << 16); 288 | } 289 | 290 | :mvhi rX, imm16 is op=0x1E & rX & rY & imm16 & reg0=0 { 291 | rX = imm16 << 16; 292 | } 293 | 294 | :cmpnei rX, rY, simm16 is op=0x1F & rX & rY & simm16 { 295 | rX = zext(rY:4 != sext(simm16:2)); 296 | } 297 | 298 | :sru rX, rY, rZ is op=0x20 & rX & rY & rZ { 299 | rX = rY >> rZ; 300 | } 301 | 302 | :nor rX, rY, rZ is op=0x21 & rX & rY & rZ { 303 | rX = ~(rY | rZ); 304 | } 305 | 306 | :mul rX, rY, rZ is op=0x22 & rX & rY & rZ { 307 | rX = (rY * rZ) & 0xFFFFFFFF; 308 | } 309 | 310 | :divu rX, rY, rZ is op=0x23 & rX & rY & rZ { 311 | rX = rY / rZ; 312 | } 313 | 314 | :rcsr reg2, csr is op=0x24 & csr & reg2 { 315 | local tmp_csr:4 = csr; 316 | reg2 = csr_read(tmp_csr); 317 | } 318 | 319 | :sr rX, rY, rZ is op=0x25 & rX & rY & rZ { 320 | rX = rY s>> rZ; 321 | } 322 | 323 | :xor rX, rY, rZ is op=0x26 & rX & rY & rZ { 324 | rX = rY ^ rZ; 325 | } 326 | 327 | :div rX, rY, rZ is op=0x27 & rX & rY & rZ { 328 | rX = rY s/ rZ; 329 | } 330 | 331 | :and rX, rY, rZ is op=0x28 & rX & rY & rZ { 332 | rX = rY & rZ; 333 | } 334 | 335 | :xnor rX, rY, rZ is op=0x29 & rX & rY & rZ { 336 | rX = ~(rY ^ rZ); 337 | } 338 | 339 | :not rX, rY is op=0x29 & rX & rY & rZ & reg1=0 { 340 | rX = ~rY; 341 | } 342 | 343 | # 0x2A is reserved 344 | 345 | :raise imm26 is op=0x2B & imm26 { 346 | 347 | local tmp:4 = imm26; 348 | software_interrupt(tmp); 349 | 350 | } 351 | 352 | :sextb rX, rY is op=0x2C & rX & rY { 353 | rX = (rY << 24) s>> 24; 354 | } 355 | 356 | # :add rX, rY, rZ is op=0x2D & rX & rY & rZ { 357 | # # rX = rY + rZ; 358 | # # } 359 | 360 | # :add rX, rY, rZ is op=0x2D & rX & rY & rZ { 361 | # # rX = rY + rZ; 362 | # # } 363 | 364 | :add rX, rY, rZ is op=0x2D & rX & rY & rZ { 365 | rX = rY + rZ; 366 | } 367 | 368 | :or rX, rY, rZ is op=0x2E & rX & rY & rZ { 369 | rX = rY | rZ; 370 | } 371 | 372 | :mov rX, rY is op=0x2E & rX & rY & rZ & reg1=0 { 373 | rX = rY; 374 | } 375 | 376 | :sl rX, rY, rZ is op=0x2F & rX & rY & rZ { 377 | rX = rY << rZ; 378 | } 379 | 380 | :b rX is op=0x30 & rX { 381 | goto [rX]; 382 | } 383 | 384 | :ret is op=0x30 & reg0=29 { 385 | return [ra]; 386 | } 387 | 388 | :modu rX, rY, rZ is op=0x31 & rX & rY & rZ { 389 | rX = rY % rZ; 390 | } 391 | 392 | :sub rX, rY, rZ is op=0x32 & rX & rY & rZ { 393 | rX = rY - rZ; 394 | } 395 | 396 | # 0x33 is reserved 397 | 398 | :wcsr csr, reg1 is op=0x34 & reg1 & csr { 399 | local tmp_csr:4 = csr; 400 | csr_write(tmp_csr, reg1); 401 | } 402 | 403 | :mod rX, rY, rZ is op=0x35 & rX & rY & rZ { 404 | rX = rY s% rZ; 405 | } 406 | 407 | :call rX is op=0x36 & rX { 408 | ra = inst_start + 4; 409 | call [rX]; 410 | } 411 | 412 | :sexth rX, rY is op=0x37 & rX & rY { 413 | rX = (rY << 16) s>> 16; 414 | } 415 | 416 | :bi Rel26 is op=0x38 & Rel26 { 417 | goto Rel26; 418 | } 419 | 420 | :cmpe rX, rY, rZ is op=0x39 & rX & rY & rZ { 421 | rX = zext(rY == rZ); 422 | } 423 | 424 | :cmpg rX, rY, rZ is op=0x3A & rX & rY & rZ { 425 | rX = zext(rY s> rZ); 426 | } 427 | 428 | :cmpge rX, rY, rZ is op=0x3B & rX & rY & rZ { 429 | rX = zext(rY s>= rZ); 430 | } 431 | 432 | :cmpgeu rX, rY, rZ is op=0x3C & rX & rY & rZ { 433 | rX = zext(rY >= rZ); 434 | } 435 | 436 | :cmpgu rX, rY, rZ is op=0x3D & rX & rY & rZ { 437 | rX = zext(rY > rZ); 438 | } 439 | 440 | :calli Rel26 is op=0x3E & Rel26 { 441 | ra = inst_start + 4; 442 | call Rel26; 443 | } 444 | 445 | :cmpne rX, rY, rZ is op=0x3F & rX & rY & rZ { 446 | rX = zext(rY != rZ); 447 | } 448 | -------------------------------------------------------------------------------- /data/languages/lm32_be.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "big" 2 | 3 | @include "lm32.sinc" 4 | 5 | -------------------------------------------------------------------------------- /data/languages/lm32_le.slaspec: -------------------------------------------------------------------------------- 1 | @define ENDIAN "little" 2 | 3 | @include "lm32.sinc" 4 | 5 | --------------------------------------------------------------------------------