├── A.inc ├── API.asm ├── B.inc ├── C.inc ├── D.inc ├── Dshotprog spec BLHeli_S.txt ├── E.inc ├── F.inc ├── G.inc ├── H.inc ├── HEX ├── JESC_AH0_24_2_3.HEX ├── JESC_AH0_48_2_3.HEX ├── JESC_AH0_96_2_3.HEX ├── JESC_AH10_24_2_3.HEX ├── JESC_AH10_48_2_3.HEX ├── JESC_AH10_96_2_3.HEX ├── JESC_AH120_24_2_3.HEX ├── JESC_AH120_48_2_3.HEX ├── JESC_AH120_96_2_3.HEX ├── JESC_AH15_24_2_3.HEX ├── JESC_AH15_48_2_3.HEX ├── JESC_AH15_96_2_3.HEX ├── JESC_AH20_24_2_3.HEX ├── JESC_AH20_48_2_3.HEX ├── JESC_AH20_96_2_3.HEX ├── JESC_AH25_24_2_3.HEX ├── JESC_AH25_48_2_3.HEX ├── JESC_AH25_96_2_3.HEX ├── JESC_AH30_24_2_3.HEX ├── JESC_AH30_48_2_3.HEX ├── JESC_AH30_96_2_3.HEX ├── JESC_AH40_24_2_3.HEX ├── JESC_AH40_48_2_3.HEX ├── JESC_AH40_96_2_3.HEX ├── JESC_AH50_24_2_3.HEX ├── JESC_AH50_48_2_3.HEX ├── JESC_AH50_96_2_3.HEX ├── JESC_AH5_24_2_3.HEX ├── JESC_AH5_48_2_3.HEX ├── JESC_AH5_96_2_3.HEX ├── JESC_AH70_24_2_3.HEX ├── JESC_AH70_48_2_3.HEX ├── JESC_AH70_96_2_3.HEX ├── JESC_AH90_24_2_3.HEX ├── JESC_AH90_48_2_3.HEX ├── JESC_AH90_96_2_3.HEX ├── JESC_AL0_24_2_3.HEX ├── JESC_AL0_48_2_3.HEX ├── JESC_AL10_24_2_3.HEX ├── JESC_AL10_48_2_3.HEX ├── JESC_AL120_24_2_3.HEX ├── JESC_AL120_48_2_3.HEX ├── JESC_AL15_24_2_3.HEX ├── JESC_AL15_48_2_3.HEX ├── JESC_AL20_24_2_3.HEX ├── JESC_AL20_48_2_3.HEX ├── JESC_AL25_24_2_3.HEX ├── JESC_AL25_48_2_3.HEX ├── JESC_AL30_24_2_3.HEX ├── JESC_AL30_48_2_3.HEX ├── JESC_AL40_24_2_3.HEX ├── JESC_AL40_48_2_3.HEX ├── JESC_AL50_24_2_3.HEX ├── JESC_AL50_48_2_3.HEX ├── JESC_AL5_24_2_3.HEX ├── JESC_AL5_48_2_3.HEX ├── JESC_AL70_24_2_3.HEX ├── JESC_AL70_48_2_3.HEX ├── JESC_AL90_24_2_3.HEX ├── JESC_AL90_48_2_3.HEX ├── JESC_BH0_24_2_3.HEX ├── JESC_BH0_48_2_3.HEX ├── JESC_BH0_96_2_3.HEX ├── JESC_BH10_24_2_3.HEX ├── JESC_BH10_48_2_3.HEX ├── JESC_BH10_96_2_3.HEX ├── JESC_BH120_24_2_3.HEX ├── JESC_BH120_48_2_3.HEX ├── JESC_BH120_96_2_3.HEX ├── JESC_BH15_24_2_3.HEX ├── JESC_BH15_48_2_3.HEX ├── JESC_BH15_96_2_3.HEX ├── JESC_BH20_24_2_3.HEX ├── JESC_BH20_48_2_3.HEX ├── JESC_BH20_96_2_3.HEX ├── JESC_BH25_24_2_3.HEX ├── JESC_BH25_48_2_3.HEX ├── JESC_BH25_96_2_3.HEX ├── JESC_BH30_24_2_3.HEX ├── JESC_BH30_48_2_3.HEX ├── JESC_BH30_96_2_3.HEX ├── JESC_BH40_24_2_3.HEX ├── JESC_BH40_48_2_3.HEX ├── JESC_BH40_96_2_3.HEX ├── JESC_BH50_24_2_3.HEX ├── JESC_BH50_48_2_3.HEX ├── JESC_BH50_96_2_3.HEX ├── JESC_BH5_24_2_3.HEX ├── JESC_BH5_48_2_3.HEX ├── JESC_BH5_96_2_3.HEX ├── JESC_BH70_24_2_3.HEX ├── JESC_BH70_48_2_3.HEX ├── JESC_BH70_96_2_3.HEX ├── JESC_BH90_24_2_3.HEX ├── JESC_BH90_48_2_3.HEX ├── JESC_BH90_96_2_3.HEX ├── JESC_BL0_24_2_3.HEX ├── JESC_BL0_48_2_3.HEX ├── JESC_BL10_24_2_3.HEX ├── JESC_BL10_48_2_3.HEX ├── JESC_BL120_24_2_3.HEX ├── JESC_BL120_48_2_3.HEX ├── JESC_BL15_24_2_3.HEX ├── JESC_BL15_48_2_3.HEX ├── JESC_BL20_24_2_3.HEX ├── JESC_BL20_48_2_3.HEX ├── JESC_BL25_24_2_3.HEX ├── JESC_BL25_48_2_3.HEX ├── JESC_BL30_24_2_3.HEX ├── JESC_BL30_48_2_3.HEX ├── JESC_BL40_24_2_3.HEX ├── JESC_BL40_48_2_3.HEX ├── JESC_BL50_24_2_3.HEX ├── JESC_BL50_48_2_3.HEX ├── JESC_BL5_24_2_3.HEX ├── JESC_BL5_48_2_3.HEX ├── JESC_BL70_24_2_3.HEX ├── JESC_BL70_48_2_3.HEX ├── JESC_BL90_24_2_3.HEX ├── JESC_BL90_48_2_3.HEX ├── JESC_CH0_24_2_3.HEX ├── JESC_CH0_48_2_3.HEX ├── JESC_CH0_96_2_3.HEX ├── JESC_CH10_24_2_3.HEX ├── JESC_CH10_48_2_3.HEX ├── JESC_CH10_96_2_3.HEX ├── JESC_CH120_24_2_3.HEX ├── JESC_CH120_48_2_3.HEX ├── JESC_CH120_96_2_3.HEX ├── JESC_CH15_24_2_3.HEX ├── JESC_CH15_48_2_3.HEX ├── JESC_CH15_96_2_3.HEX ├── JESC_CH20_24_2_3.HEX ├── JESC_CH20_48_2_3.HEX ├── JESC_CH20_96_2_3.HEX ├── JESC_CH25_24_2_3.HEX ├── JESC_CH25_48_2_3.HEX ├── JESC_CH25_96_2_3.HEX ├── JESC_CH30_24_2_3.HEX ├── JESC_CH30_48_2_3.HEX ├── JESC_CH30_96_2_3.HEX ├── JESC_CH40_24_2_3.HEX ├── JESC_CH40_48_2_3.HEX ├── JESC_CH40_96_2_3.HEX ├── JESC_CH50_24_2_3.HEX ├── JESC_CH50_48_2_3.HEX ├── JESC_CH50_96_2_3.HEX ├── JESC_CH5_24_2_3.HEX ├── JESC_CH5_48_2_3.HEX ├── JESC_CH5_96_2_3.HEX ├── JESC_CH70_24_2_3.HEX ├── JESC_CH70_48_2_3.HEX ├── JESC_CH70_96_2_3.HEX ├── JESC_CH90_24_2_3.HEX ├── JESC_CH90_48_2_3.HEX ├── JESC_CH90_96_2_3.HEX ├── JESC_CL0_24_2_3.HEX ├── JESC_CL0_48_2_3.HEX ├── JESC_CL10_24_2_3.HEX ├── JESC_CL10_48_2_3.HEX ├── JESC_CL120_24_2_3.HEX ├── JESC_CL120_48_2_3.HEX ├── JESC_CL15_24_2_3.HEX ├── JESC_CL15_48_2_3.HEX ├── JESC_CL20_24_2_3.HEX ├── JESC_CL20_48_2_3.HEX ├── JESC_CL25_24_2_3.HEX ├── JESC_CL25_48_2_3.HEX ├── JESC_CL30_24_2_3.HEX ├── JESC_CL30_48_2_3.HEX ├── JESC_CL40_24_2_3.HEX ├── JESC_CL40_48_2_3.HEX ├── JESC_CL50_24_2_3.HEX ├── JESC_CL50_48_2_3.HEX ├── JESC_CL5_24_2_3.HEX ├── JESC_CL5_48_2_3.HEX ├── JESC_CL70_24_2_3.HEX ├── JESC_CL70_48_2_3.HEX ├── JESC_CL90_24_2_3.HEX ├── JESC_CL90_48_2_3.HEX ├── JESC_DH0_24_2_3.HEX ├── JESC_DH0_48_2_3.HEX ├── JESC_DH0_96_2_3.HEX ├── JESC_DH10_24_2_3.HEX ├── JESC_DH10_48_2_3.HEX ├── JESC_DH10_96_2_3.HEX ├── JESC_DH120_24_2_3.HEX ├── JESC_DH120_48_2_3.HEX ├── JESC_DH120_96_2_3.HEX ├── JESC_DH15_24_2_3.HEX ├── JESC_DH15_48_2_3.HEX ├── JESC_DH15_96_2_3.HEX ├── JESC_DH20_24_2_3.HEX ├── JESC_DH20_48_2_3.HEX ├── JESC_DH20_96_2_3.HEX ├── JESC_DH25_24_2_3.HEX ├── JESC_DH25_48_2_3.HEX ├── JESC_DH25_96_2_3.HEX ├── JESC_DH30_24_2_3.HEX ├── JESC_DH30_48_2_3.HEX ├── JESC_DH30_96_2_3.HEX ├── JESC_DH40_24_2_3.HEX ├── JESC_DH40_48_2_3.HEX ├── JESC_DH40_96_2_3.HEX ├── JESC_DH50_24_2_3.HEX ├── JESC_DH50_48_2_3.HEX ├── JESC_DH50_96_2_3.HEX ├── JESC_DH5_24_2_3.HEX ├── JESC_DH5_48_2_3.HEX ├── JESC_DH5_96_2_3.HEX ├── JESC_DH70_24_2_3.HEX ├── JESC_DH70_48_2_3.HEX ├── JESC_DH70_96_2_3.HEX ├── JESC_DH90_24_2_3.HEX ├── JESC_DH90_48_2_3.HEX ├── JESC_DH90_96_2_3.HEX ├── JESC_DL0_24_2_3.HEX ├── JESC_DL0_48_2_3.HEX ├── JESC_DL10_24_2_3.HEX ├── JESC_DL10_48_2_3.HEX ├── JESC_DL120_24_2_3.HEX ├── JESC_DL120_48_2_3.HEX ├── JESC_DL15_24_2_3.HEX ├── JESC_DL15_48_2_3.HEX ├── JESC_DL20_24_2_3.HEX ├── JESC_DL20_48_2_3.HEX ├── JESC_DL25_24_2_3.HEX ├── JESC_DL25_48_2_3.HEX ├── JESC_DL30_24_2_3.HEX ├── JESC_DL30_48_2_3.HEX ├── JESC_DL40_24_2_3.HEX ├── JESC_DL40_48_2_3.HEX ├── JESC_DL50_24_2_3.HEX ├── JESC_DL50_48_2_3.HEX ├── JESC_DL5_24_2_3.HEX ├── JESC_DL5_48_2_3.HEX ├── JESC_DL70_24_2_3.HEX ├── JESC_DL70_48_2_3.HEX ├── JESC_DL90_24_2_3.HEX ├── JESC_DL90_48_2_3.HEX ├── JESC_EH0_24_2_3.HEX ├── JESC_EH0_48_2_3.HEX ├── JESC_EH0_96_2_3.HEX ├── JESC_EH10_24_2_3.HEX ├── JESC_EH10_48_2_3.HEX ├── JESC_EH10_96_2_3.HEX ├── JESC_EH120_24_2_3.HEX ├── JESC_EH120_48_2_3.HEX ├── JESC_EH120_96_2_3.HEX ├── JESC_EH15_24_2_3.HEX ├── JESC_EH15_48_2_3.HEX ├── JESC_EH15_96_2_3.HEX ├── JESC_EH20_24_2_3.HEX ├── JESC_EH20_48_2_3.HEX ├── JESC_EH20_96_2_3.HEX ├── JESC_EH25_24_2_3.HEX ├── JESC_EH25_48_2_3.HEX ├── JESC_EH25_96_2_3.HEX ├── JESC_EH30_24_2_3.HEX ├── JESC_EH30_48_2_3.HEX ├── JESC_EH30_96_2_3.HEX ├── JESC_EH40_24_2_3.HEX ├── JESC_EH40_48_2_3.HEX ├── JESC_EH40_96_2_3.HEX ├── JESC_EH50_24_2_3.HEX ├── JESC_EH50_48_2_3.HEX ├── JESC_EH50_96_2_3.HEX ├── JESC_EH5_24_2_3.HEX ├── JESC_EH5_48_2_3.HEX ├── JESC_EH5_96_2_3.HEX ├── JESC_EH70_24_2_3.HEX ├── JESC_EH70_48_2_3.HEX ├── JESC_EH70_96_2_3.HEX ├── JESC_EH90_24_2_3.HEX ├── JESC_EH90_48_2_3.HEX ├── JESC_EH90_96_2_3.HEX ├── JESC_EL0_24_2_3.HEX ├── JESC_EL0_48_2_3.HEX ├── JESC_EL10_24_2_3.HEX ├── JESC_EL10_48_2_3.HEX ├── JESC_EL120_24_2_3.HEX ├── JESC_EL120_48_2_3.HEX ├── JESC_EL15_24_2_3.HEX ├── JESC_EL15_48_2_3.HEX ├── JESC_EL20_24_2_3.HEX ├── JESC_EL20_48_2_3.HEX ├── JESC_EL25_24_2_3.HEX ├── JESC_EL25_48_2_3.HEX ├── JESC_EL30_24_2_3.HEX ├── JESC_EL30_48_2_3.HEX ├── JESC_EL40_24_2_3.HEX ├── JESC_EL40_48_2_3.HEX ├── JESC_EL50_24_2_3.HEX ├── JESC_EL50_48_2_3.HEX ├── JESC_EL5_24_2_3.HEX ├── JESC_EL5_48_2_3.HEX ├── JESC_EL70_24_2_3.HEX ├── JESC_EL70_48_2_3.HEX ├── JESC_EL90_24_2_3.HEX ├── JESC_EL90_48_2_3.HEX ├── JESC_FH0_24_2_3.HEX ├── JESC_FH0_48_2_3.HEX ├── JESC_FH0_96_2_3.HEX ├── JESC_FH10_24_2_3.HEX ├── JESC_FH10_48_2_3.HEX ├── JESC_FH10_96_2_3.HEX ├── JESC_FH120_24_2_3.HEX ├── JESC_FH120_48_2_3.HEX ├── JESC_FH120_96_2_3.HEX ├── JESC_FH15_24_2_3.HEX ├── JESC_FH15_48_2_3.HEX ├── JESC_FH15_96_2_3.HEX ├── JESC_FH20_24_2_3.HEX ├── JESC_FH20_48_2_3.HEX ├── JESC_FH20_96_2_3.HEX ├── JESC_FH25_24_2_3.HEX ├── JESC_FH25_48_2_3.HEX ├── JESC_FH25_96_2_3.HEX ├── JESC_FH30_24_2_3.HEX ├── JESC_FH30_48_2_3.HEX ├── JESC_FH30_96_2_3.HEX ├── JESC_FH40_24_2_3.HEX ├── JESC_FH40_48_2_3.HEX ├── JESC_FH40_96_2_3.HEX ├── JESC_FH50_24_2_3.HEX ├── JESC_FH50_48_2_3.HEX ├── JESC_FH50_96_2_3.HEX ├── JESC_FH5_24_2_3.HEX ├── JESC_FH5_48_2_3.HEX ├── JESC_FH5_96_2_3.HEX ├── JESC_FH70_24_2_3.HEX ├── JESC_FH70_48_2_3.HEX ├── JESC_FH70_96_2_3.HEX ├── JESC_FH90_24_2_3.HEX ├── JESC_FH90_48_2_3.HEX ├── JESC_FH90_96_2_3.HEX ├── JESC_FL0_24_2_3.HEX ├── JESC_FL0_48_2_3.HEX ├── JESC_FL10_24_2_3.HEX ├── JESC_FL10_48_2_3.HEX ├── JESC_FL120_24_2_3.HEX ├── JESC_FL120_48_2_3.HEX ├── JESC_FL15_24_2_3.HEX ├── JESC_FL15_48_2_3.HEX ├── JESC_FL20_24_2_3.HEX ├── JESC_FL20_48_2_3.HEX ├── JESC_FL25_24_2_3.HEX ├── JESC_FL25_48_2_3.HEX ├── JESC_FL30_24_2_3.HEX ├── JESC_FL30_48_2_3.HEX ├── JESC_FL40_24_2_3.HEX ├── JESC_FL40_48_2_3.HEX ├── JESC_FL50_24_2_3.HEX ├── JESC_FL50_48_2_3.HEX ├── JESC_FL5_24_2_3.HEX ├── JESC_FL5_48_2_3.HEX ├── JESC_FL70_24_2_3.HEX ├── JESC_FL70_48_2_3.HEX ├── JESC_FL90_24_2_3.HEX ├── JESC_FL90_48_2_3.HEX ├── JESC_GH0_24_2_3.HEX ├── JESC_GH0_48_2_3.HEX ├── JESC_GH0_96_2_3.HEX ├── JESC_GH10_24_2_3.HEX ├── JESC_GH10_48_2_3.HEX ├── JESC_GH10_96_2_3.HEX ├── JESC_GH120_24_2_3.HEX ├── JESC_GH120_48_2_3.HEX ├── JESC_GH120_96_2_3.HEX ├── JESC_GH15_24_2_3.HEX ├── JESC_GH15_48_2_3.HEX ├── JESC_GH15_96_2_3.HEX ├── JESC_GH20_24_2_3.HEX ├── JESC_GH20_48_2_3.HEX ├── JESC_GH20_96_2_3.HEX ├── JESC_GH25_24_2_3.HEX ├── JESC_GH25_48_2_3.HEX ├── JESC_GH25_96_2_3.HEX ├── JESC_GH30_24_2_3.HEX ├── JESC_GH30_48_2_3.HEX ├── JESC_GH30_96_2_3.HEX ├── JESC_GH40_24_2_3.HEX ├── JESC_GH40_48_2_3.HEX ├── JESC_GH40_96_2_3.HEX ├── JESC_GH50_24_2_3.HEX ├── JESC_GH50_48_2_3.HEX ├── JESC_GH50_96_2_3.HEX ├── JESC_GH5_24_2_3.HEX ├── JESC_GH5_48_2_3.HEX ├── JESC_GH5_96_2_3.HEX ├── JESC_GH70_24_2_3.HEX ├── JESC_GH70_48_2_3.HEX ├── JESC_GH70_96_2_3.HEX ├── JESC_GH90_24_2_3.HEX ├── JESC_GH90_48_2_3.HEX ├── JESC_GH90_96_2_3.HEX ├── JESC_GL0_24_2_3.HEX ├── JESC_GL0_48_2_3.HEX ├── JESC_GL10_24_2_3.HEX ├── JESC_GL10_48_2_3.HEX ├── JESC_GL120_24_2_3.HEX ├── JESC_GL120_48_2_3.HEX ├── JESC_GL15_24_2_3.HEX ├── JESC_GL15_48_2_3.HEX ├── JESC_GL20_24_2_3.HEX ├── JESC_GL20_48_2_3.HEX ├── JESC_GL25_24_2_3.HEX ├── JESC_GL25_48_2_3.HEX ├── JESC_GL30_24_2_3.HEX ├── JESC_GL30_48_2_3.HEX ├── JESC_GL40_24_2_3.HEX ├── JESC_GL40_48_2_3.HEX ├── JESC_GL50_24_2_3.HEX ├── JESC_GL50_48_2_3.HEX ├── JESC_GL5_24_2_3.HEX ├── JESC_GL5_48_2_3.HEX ├── JESC_GL70_24_2_3.HEX ├── JESC_GL70_48_2_3.HEX ├── JESC_GL90_24_2_3.HEX ├── JESC_GL90_48_2_3.HEX ├── JESC_HH0_24_2_3.HEX ├── JESC_HH0_48_2_3.HEX ├── JESC_HH0_96_2_3.HEX ├── JESC_HH10_24_2_3.HEX ├── JESC_HH10_48_2_3.HEX ├── JESC_HH10_96_2_3.HEX ├── JESC_HH120_24_2_3.HEX ├── JESC_HH120_48_2_3.HEX ├── JESC_HH120_96_2_3.HEX ├── JESC_HH15_24_2_3.HEX ├── JESC_HH15_48_2_3.HEX ├── JESC_HH15_96_2_3.HEX ├── JESC_HH20_24_2_3.HEX ├── JESC_HH20_48_2_3.HEX ├── JESC_HH20_96_2_3.HEX ├── JESC_HH25_24_2_3.HEX ├── JESC_HH25_48_2_3.HEX ├── JESC_HH25_96_2_3.HEX ├── JESC_HH30_24_2_3.HEX ├── JESC_HH30_48_2_3.HEX ├── JESC_HH30_96_2_3.HEX ├── JESC_HH40_24_2_3.HEX ├── JESC_HH40_48_2_3.HEX ├── JESC_HH40_96_2_3.HEX ├── JESC_HH50_24_2_3.HEX ├── JESC_HH50_48_2_3.HEX ├── JESC_HH50_96_2_3.HEX ├── JESC_HH5_24_2_3.HEX ├── JESC_HH5_48_2_3.HEX ├── JESC_HH5_96_2_3.HEX ├── JESC_HH70_24_2_3.HEX ├── JESC_HH70_48_2_3.HEX ├── JESC_HH70_96_2_3.HEX ├── JESC_HH90_24_2_3.HEX ├── JESC_HH90_48_2_3.HEX ├── JESC_HH90_96_2_3.HEX ├── JESC_HL0_24_2_3.HEX ├── JESC_HL0_48_2_3.HEX ├── JESC_HL10_24_2_3.HEX ├── JESC_HL10_48_2_3.HEX ├── JESC_HL120_24_2_3.HEX ├── JESC_HL120_48_2_3.HEX ├── JESC_HL15_24_2_3.HEX ├── JESC_HL15_48_2_3.HEX ├── JESC_HL20_24_2_3.HEX ├── JESC_HL20_48_2_3.HEX ├── JESC_HL25_24_2_3.HEX ├── JESC_HL25_48_2_3.HEX ├── JESC_HL30_24_2_3.HEX ├── JESC_HL30_48_2_3.HEX ├── JESC_HL40_24_2_3.HEX ├── JESC_HL40_48_2_3.HEX ├── JESC_HL50_24_2_3.HEX ├── JESC_HL50_48_2_3.HEX ├── JESC_HL5_24_2_3.HEX ├── JESC_HL5_48_2_3.HEX ├── JESC_HL70_24_2_3.HEX ├── JESC_HL70_48_2_3.HEX ├── JESC_HL90_24_2_3.HEX ├── JESC_HL90_48_2_3.HEX ├── JESC_IH0_24_2_3.HEX ├── JESC_IH0_48_2_3.HEX ├── JESC_IH0_96_2_3.HEX ├── JESC_IH10_24_2_3.HEX ├── JESC_IH10_48_2_3.HEX ├── JESC_IH10_96_2_3.HEX ├── JESC_IH120_24_2_3.HEX ├── JESC_IH120_48_2_3.HEX ├── JESC_IH120_96_2_3.HEX ├── JESC_IH15_24_2_3.HEX ├── JESC_IH15_48_2_3.HEX ├── JESC_IH15_96_2_3.HEX ├── JESC_IH20_24_2_3.HEX ├── JESC_IH20_48_2_3.HEX ├── JESC_IH20_96_2_3.HEX ├── JESC_IH25_24_2_3.HEX ├── JESC_IH25_48_2_3.HEX ├── JESC_IH25_96_2_3.HEX ├── JESC_IH30_24_2_3.HEX ├── JESC_IH30_48_2_3.HEX ├── JESC_IH30_96_2_3.HEX ├── JESC_IH40_24_2_3.HEX ├── JESC_IH40_48_2_3.HEX ├── JESC_IH40_96_2_3.HEX ├── JESC_IH50_24_2_3.HEX ├── JESC_IH50_48_2_3.HEX ├── JESC_IH50_96_2_3.HEX ├── JESC_IH5_24_2_3.HEX ├── JESC_IH5_48_2_3.HEX ├── JESC_IH5_96_2_3.HEX ├── JESC_IH70_24_2_3.HEX ├── JESC_IH70_48_2_3.HEX ├── JESC_IH70_96_2_3.HEX ├── JESC_IH90_24_2_3.HEX ├── JESC_IH90_48_2_3.HEX ├── JESC_IH90_96_2_3.HEX ├── JESC_IL0_24_2_3.HEX ├── JESC_IL0_48_2_3.HEX ├── JESC_IL10_24_2_3.HEX ├── JESC_IL10_48_2_3.HEX ├── JESC_IL120_24_2_3.HEX ├── JESC_IL120_48_2_3.HEX ├── JESC_IL15_24_2_3.HEX ├── JESC_IL15_48_2_3.HEX ├── JESC_IL20_24_2_3.HEX ├── JESC_IL20_48_2_3.HEX ├── JESC_IL25_24_2_3.HEX ├── JESC_IL25_48_2_3.HEX ├── JESC_IL30_24_2_3.HEX ├── JESC_IL30_48_2_3.HEX ├── JESC_IL40_24_2_3.HEX ├── JESC_IL40_48_2_3.HEX ├── JESC_IL50_24_2_3.HEX ├── JESC_IL50_48_2_3.HEX ├── JESC_IL5_24_2_3.HEX ├── JESC_IL5_48_2_3.HEX ├── JESC_IL70_24_2_3.HEX ├── JESC_IL70_48_2_3.HEX ├── JESC_IL90_24_2_3.HEX ├── JESC_IL90_48_2_3.HEX ├── JESC_JH0_24_2_3.HEX ├── JESC_JH0_48_2_3.HEX ├── JESC_JH0_96_2_3.HEX ├── JESC_JH10_24_2_3.HEX ├── JESC_JH10_48_2_3.HEX ├── JESC_JH10_96_2_3.HEX ├── JESC_JH120_24_2_3.HEX ├── JESC_JH120_48_2_3.HEX ├── JESC_JH120_96_2_3.HEX ├── JESC_JH15_24_2_3.HEX ├── JESC_JH15_48_2_3.HEX ├── JESC_JH15_96_2_3.HEX ├── JESC_JH20_24_2_3.HEX ├── JESC_JH20_48_2_3.HEX ├── JESC_JH20_96_2_3.HEX ├── JESC_JH25_24_2_3.HEX ├── JESC_JH25_48_2_3.HEX ├── JESC_JH25_96_2_3.HEX ├── JESC_JH30_24_2_3.HEX ├── JESC_JH30_48_2_3.HEX ├── JESC_JH30_96_2_3.HEX ├── JESC_JH40_24_2_3.HEX ├── JESC_JH40_48_2_3.HEX ├── JESC_JH40_96_2_3.HEX ├── JESC_JH50_24_2_3.HEX ├── JESC_JH50_48_2_3.HEX ├── JESC_JH50_96_2_3.HEX ├── JESC_JH5_24_2_3.HEX ├── JESC_JH5_48_2_3.HEX ├── JESC_JH5_96_2_3.HEX ├── JESC_JH70_24_2_3.HEX ├── JESC_JH70_48_2_3.HEX ├── JESC_JH70_96_2_3.HEX ├── JESC_JH90_24_2_3.HEX ├── JESC_JH90_48_2_3.HEX ├── JESC_JH90_96_2_3.HEX ├── JESC_JL0_24_2_3.HEX ├── JESC_JL0_48_2_3.HEX ├── JESC_JL10_24_2_3.HEX ├── JESC_JL10_48_2_3.HEX ├── JESC_JL120_24_2_3.HEX ├── JESC_JL120_48_2_3.HEX ├── JESC_JL15_24_2_3.HEX ├── JESC_JL15_48_2_3.HEX ├── JESC_JL20_24_2_3.HEX ├── JESC_JL20_48_2_3.HEX ├── JESC_JL25_24_2_3.HEX ├── JESC_JL25_48_2_3.HEX ├── JESC_JL30_24_2_3.HEX ├── JESC_JL30_48_2_3.HEX ├── JESC_JL40_24_2_3.HEX ├── JESC_JL40_48_2_3.HEX ├── JESC_JL50_24_2_3.HEX ├── JESC_JL50_48_2_3.HEX ├── JESC_JL5_24_2_3.HEX ├── JESC_JL5_48_2_3.HEX ├── JESC_JL70_24_2_3.HEX ├── JESC_JL70_48_2_3.HEX ├── JESC_JL90_24_2_3.HEX ├── JESC_JL90_48_2_3.HEX ├── JESC_KH0_24_2_3.HEX ├── JESC_KH0_48_2_3.HEX ├── JESC_KH0_96_2_3.HEX ├── JESC_KH10_24_2_3.HEX ├── JESC_KH10_48_2_3.HEX ├── JESC_KH10_96_2_3.HEX ├── JESC_KH120_24_2_3.HEX ├── JESC_KH120_48_2_3.HEX ├── JESC_KH120_96_2_3.HEX ├── JESC_KH15_24_2_3.HEX ├── JESC_KH15_48_2_3.HEX ├── JESC_KH15_96_2_3.HEX ├── JESC_KH20_24_2_3.HEX ├── JESC_KH20_48_2_3.HEX ├── JESC_KH20_96_2_3.HEX ├── JESC_KH25_24_2_3.HEX ├── JESC_KH25_48_2_3.HEX ├── JESC_KH25_96_2_3.HEX ├── JESC_KH30_24_2_3.HEX ├── JESC_KH30_48_2_3.HEX ├── JESC_KH30_96_2_3.HEX ├── JESC_KH40_24_2_3.HEX ├── JESC_KH40_48_2_3.HEX ├── JESC_KH40_96_2_3.HEX ├── JESC_KH50_24_2_3.HEX ├── JESC_KH50_48_2_3.HEX ├── JESC_KH50_96_2_3.HEX ├── JESC_KH5_24_2_3.HEX ├── JESC_KH5_48_2_3.HEX ├── JESC_KH5_96_2_3.HEX ├── JESC_KH70_24_2_3.HEX ├── JESC_KH70_48_2_3.HEX ├── JESC_KH70_96_2_3.HEX ├── JESC_KH90_24_2_3.HEX ├── JESC_KH90_48_2_3.HEX ├── JESC_KH90_96_2_3.HEX ├── JESC_KL0_24_2_3.HEX ├── JESC_KL0_48_2_3.HEX ├── JESC_KL10_24_2_3.HEX ├── JESC_KL10_48_2_3.HEX ├── JESC_KL120_24_2_3.HEX ├── JESC_KL120_48_2_3.HEX ├── JESC_KL15_24_2_3.HEX ├── JESC_KL15_48_2_3.HEX ├── JESC_KL20_24_2_3.HEX ├── JESC_KL20_48_2_3.HEX ├── JESC_KL25_24_2_3.HEX ├── JESC_KL25_48_2_3.HEX ├── JESC_KL30_24_2_3.HEX ├── JESC_KL30_48_2_3.HEX ├── JESC_KL40_24_2_3.HEX ├── JESC_KL40_48_2_3.HEX ├── JESC_KL50_24_2_3.HEX ├── JESC_KL50_48_2_3.HEX ├── JESC_KL5_24_2_3.HEX ├── JESC_KL5_48_2_3.HEX ├── JESC_KL70_24_2_3.HEX ├── JESC_KL70_48_2_3.HEX ├── JESC_KL90_24_2_3.HEX ├── JESC_KL90_48_2_3.HEX ├── JESC_LH0_24_2_3.HEX ├── JESC_LH0_48_2_3.HEX ├── JESC_LH0_96_2_3.HEX ├── JESC_LH10_24_2_3.HEX ├── JESC_LH10_48_2_3.HEX ├── JESC_LH10_96_2_3.HEX ├── JESC_LH120_24_2_3.HEX ├── JESC_LH120_48_2_3.HEX ├── JESC_LH120_96_2_3.HEX ├── JESC_LH15_24_2_3.HEX ├── JESC_LH15_48_2_3.HEX ├── JESC_LH15_96_2_3.HEX ├── JESC_LH20_24_2_3.HEX ├── JESC_LH20_48_2_3.HEX ├── JESC_LH20_96_2_3.HEX ├── JESC_LH25_24_2_3.HEX ├── JESC_LH25_48_2_3.HEX ├── JESC_LH25_96_2_3.HEX ├── JESC_LH30_24_2_3.HEX ├── JESC_LH30_48_2_3.HEX ├── JESC_LH30_96_2_3.HEX ├── JESC_LH40_24_2_3.HEX ├── JESC_LH40_48_2_3.HEX ├── JESC_LH40_96_2_3.HEX ├── JESC_LH50_24_2_3.HEX ├── JESC_LH50_48_2_3.HEX ├── JESC_LH50_96_2_3.HEX ├── JESC_LH5_24_2_3.HEX ├── JESC_LH5_48_2_3.HEX ├── JESC_LH5_96_2_3.HEX ├── JESC_LH70_24_2_3.HEX ├── JESC_LH70_48_2_3.HEX ├── JESC_LH70_96_2_3.HEX ├── JESC_LH90_24_2_3.HEX ├── JESC_LH90_48_2_3.HEX ├── JESC_LH90_96_2_3.HEX ├── JESC_LL0_24_2_3.HEX ├── JESC_LL0_48_2_3.HEX ├── JESC_LL10_24_2_3.HEX ├── JESC_LL10_48_2_3.HEX ├── JESC_LL120_24_2_3.HEX ├── JESC_LL120_48_2_3.HEX ├── JESC_LL15_24_2_3.HEX ├── JESC_LL15_48_2_3.HEX ├── JESC_LL20_24_2_3.HEX ├── JESC_LL20_48_2_3.HEX ├── JESC_LL25_24_2_3.HEX ├── JESC_LL25_48_2_3.HEX ├── JESC_LL30_24_2_3.HEX ├── JESC_LL30_48_2_3.HEX ├── JESC_LL40_24_2_3.HEX ├── JESC_LL40_48_2_3.HEX ├── JESC_LL50_24_2_3.HEX ├── JESC_LL50_48_2_3.HEX ├── JESC_LL5_24_2_3.HEX ├── JESC_LL5_48_2_3.HEX ├── JESC_LL70_24_2_3.HEX ├── JESC_LL70_48_2_3.HEX ├── JESC_LL90_24_2_3.HEX ├── JESC_LL90_48_2_3.HEX ├── JESC_MH0_24_2_3.HEX ├── JESC_MH0_48_2_3.HEX ├── JESC_MH0_96_2_3.HEX ├── JESC_MH10_24_2_3.HEX ├── JESC_MH10_48_2_3.HEX ├── JESC_MH10_96_2_3.HEX ├── JESC_MH120_24_2_3.HEX ├── JESC_MH120_48_2_3.HEX ├── JESC_MH120_96_2_3.HEX ├── JESC_MH15_24_2_3.HEX ├── JESC_MH15_48_2_3.HEX ├── JESC_MH15_96_2_3.HEX ├── JESC_MH20_24_2_3.HEX ├── JESC_MH20_48_2_3.HEX ├── JESC_MH20_96_2_3.HEX ├── JESC_MH25_24_2_3.HEX ├── JESC_MH25_48_2_3.HEX ├── JESC_MH25_96_2_3.HEX ├── JESC_MH30_24_2_3.HEX ├── JESC_MH30_48_2_3.HEX ├── JESC_MH30_96_2_3.HEX ├── JESC_MH40_24_2_3.HEX ├── JESC_MH40_48_2_3.HEX ├── JESC_MH40_96_2_3.HEX ├── JESC_MH50_24_2_3.HEX ├── JESC_MH50_48_2_3.HEX ├── JESC_MH50_96_2_3.HEX ├── JESC_MH5_24_2_3.HEX ├── JESC_MH5_48_2_3.HEX ├── JESC_MH5_96_2_3.HEX ├── JESC_MH70_24_2_3.HEX ├── JESC_MH70_48_2_3.HEX ├── JESC_MH70_96_2_3.HEX ├── JESC_MH90_24_2_3.HEX ├── JESC_MH90_48_2_3.HEX ├── JESC_MH90_96_2_3.HEX ├── JESC_ML0_24_2_3.HEX ├── JESC_ML0_48_2_3.HEX ├── JESC_ML10_24_2_3.HEX ├── JESC_ML10_48_2_3.HEX ├── JESC_ML120_24_2_3.HEX ├── JESC_ML120_48_2_3.HEX ├── JESC_ML15_24_2_3.HEX ├── JESC_ML15_48_2_3.HEX ├── JESC_ML20_24_2_3.HEX ├── JESC_ML20_48_2_3.HEX ├── JESC_ML25_24_2_3.HEX ├── JESC_ML25_48_2_3.HEX ├── JESC_ML30_24_2_3.HEX ├── JESC_ML30_48_2_3.HEX ├── JESC_ML40_24_2_3.HEX ├── JESC_ML40_48_2_3.HEX ├── JESC_ML50_24_2_3.HEX ├── JESC_ML50_48_2_3.HEX ├── JESC_ML5_24_2_3.HEX ├── JESC_ML5_48_2_3.HEX ├── JESC_ML70_24_2_3.HEX ├── JESC_ML70_48_2_3.HEX ├── JESC_ML90_24_2_3.HEX ├── JESC_ML90_48_2_3.HEX ├── JESC_NH0_24_2_3.HEX ├── JESC_NH0_48_2_3.HEX ├── JESC_NH0_96_2_3.HEX ├── JESC_NH10_24_2_3.HEX ├── JESC_NH10_48_2_3.HEX ├── JESC_NH10_96_2_3.HEX ├── JESC_NH120_24_2_3.HEX ├── JESC_NH120_48_2_3.HEX ├── JESC_NH120_96_2_3.HEX ├── JESC_NH15_24_2_3.HEX ├── JESC_NH15_48_2_3.HEX ├── JESC_NH15_96_2_3.HEX ├── JESC_NH20_24_2_3.HEX ├── JESC_NH20_48_2_3.HEX ├── JESC_NH20_96_2_3.HEX ├── JESC_NH25_24_2_3.HEX ├── JESC_NH25_48_2_3.HEX ├── JESC_NH25_96_2_3.HEX ├── JESC_NH30_24_2_3.HEX ├── JESC_NH30_48_2_3.HEX ├── JESC_NH30_96_2_3.HEX ├── JESC_NH40_24_2_3.HEX ├── JESC_NH40_48_2_3.HEX ├── JESC_NH40_96_2_3.HEX ├── JESC_NH50_24_2_3.HEX ├── JESC_NH50_48_2_3.HEX ├── JESC_NH50_96_2_3.HEX ├── JESC_NH5_24_2_3.HEX ├── JESC_NH5_48_2_3.HEX ├── JESC_NH5_96_2_3.HEX ├── JESC_NH70_24_2_3.HEX ├── JESC_NH70_48_2_3.HEX ├── JESC_NH70_96_2_3.HEX ├── JESC_NH90_24_2_3.HEX ├── JESC_NH90_48_2_3.HEX ├── JESC_NH90_96_2_3.HEX ├── JESC_NL0_24_2_3.HEX ├── JESC_NL0_48_2_3.HEX ├── JESC_NL10_24_2_3.HEX ├── JESC_NL10_48_2_3.HEX ├── JESC_NL120_24_2_3.HEX ├── JESC_NL120_48_2_3.HEX ├── JESC_NL15_24_2_3.HEX ├── JESC_NL15_48_2_3.HEX ├── JESC_NL20_24_2_3.HEX ├── JESC_NL20_48_2_3.HEX ├── JESC_NL25_24_2_3.HEX ├── JESC_NL25_48_2_3.HEX ├── JESC_NL30_24_2_3.HEX ├── JESC_NL30_48_2_3.HEX ├── JESC_NL40_24_2_3.HEX ├── JESC_NL40_48_2_3.HEX ├── JESC_NL50_24_2_3.HEX ├── JESC_NL50_48_2_3.HEX ├── JESC_NL5_24_2_3.HEX ├── JESC_NL5_48_2_3.HEX ├── JESC_NL70_24_2_3.HEX ├── JESC_NL70_48_2_3.HEX ├── JESC_NL90_24_2_3.HEX ├── JESC_NL90_48_2_3.HEX ├── JESC_OH0_24_2_3.HEX ├── JESC_OH0_48_2_3.HEX ├── JESC_OH0_96_2_3.HEX ├── JESC_OH10_24_2_3.HEX ├── JESC_OH10_48_2_3.HEX ├── JESC_OH10_96_2_3.HEX ├── JESC_OH120_24_2_3.HEX ├── JESC_OH120_48_2_3.HEX ├── JESC_OH120_96_2_3.HEX ├── JESC_OH15_24_2_3.HEX ├── JESC_OH15_48_2_3.HEX ├── JESC_OH15_96_2_3.HEX ├── JESC_OH20_24_2_3.HEX ├── JESC_OH20_48_2_3.HEX ├── JESC_OH20_96_2_3.HEX ├── JESC_OH25_24_2_3.HEX ├── JESC_OH25_48_2_3.HEX ├── JESC_OH25_96_2_3.HEX ├── JESC_OH30_24_2_3.HEX ├── JESC_OH30_48_2_3.HEX ├── JESC_OH30_96_2_3.HEX ├── JESC_OH40_24_2_3.HEX ├── JESC_OH40_48_2_3.HEX ├── JESC_OH40_96_2_3.HEX ├── JESC_OH50_24_2_3.HEX ├── JESC_OH50_48_2_3.HEX ├── JESC_OH50_96_2_3.HEX ├── JESC_OH5_24_2_3.HEX ├── JESC_OH5_48_2_3.HEX ├── JESC_OH5_96_2_3.HEX ├── JESC_OH70_24_2_3.HEX ├── JESC_OH70_48_2_3.HEX ├── JESC_OH70_96_2_3.HEX ├── JESC_OH90_24_2_3.HEX ├── JESC_OH90_48_2_3.HEX ├── JESC_OH90_96_2_3.HEX ├── JESC_OL0_24_2_3.HEX ├── JESC_OL0_48_2_3.HEX ├── JESC_OL10_24_2_3.HEX ├── JESC_OL10_48_2_3.HEX ├── JESC_OL120_24_2_3.HEX ├── JESC_OL120_48_2_3.HEX ├── JESC_OL15_24_2_3.HEX ├── JESC_OL15_48_2_3.HEX ├── JESC_OL20_24_2_3.HEX ├── JESC_OL20_48_2_3.HEX ├── JESC_OL25_24_2_3.HEX ├── JESC_OL25_48_2_3.HEX ├── JESC_OL30_24_2_3.HEX ├── JESC_OL30_48_2_3.HEX ├── JESC_OL40_24_2_3.HEX ├── JESC_OL40_48_2_3.HEX ├── JESC_OL50_24_2_3.HEX ├── JESC_OL50_48_2_3.HEX ├── JESC_OL5_24_2_3.HEX ├── JESC_OL5_48_2_3.HEX ├── JESC_OL70_24_2_3.HEX ├── JESC_OL70_48_2_3.HEX ├── JESC_OL90_24_2_3.HEX ├── JESC_OL90_48_2_3.HEX ├── JESC_PH0_24_2_3.HEX ├── JESC_PH0_48_2_3.HEX ├── JESC_PH0_96_2_3.HEX ├── JESC_PH10_24_2_3.HEX ├── JESC_PH10_48_2_3.HEX ├── JESC_PH10_96_2_3.HEX ├── JESC_PH120_24_2_3.HEX ├── JESC_PH120_48_2_3.HEX ├── JESC_PH120_96_2_3.HEX ├── JESC_PH15_24_2_3.HEX ├── JESC_PH15_48_2_3.HEX ├── JESC_PH15_96_2_3.HEX ├── JESC_PH20_24_2_3.HEX ├── JESC_PH20_48_2_3.HEX ├── JESC_PH20_96_2_3.HEX ├── JESC_PH25_24_2_3.HEX ├── JESC_PH25_48_2_3.HEX ├── JESC_PH25_96_2_3.HEX ├── JESC_PH30_24_2_3.HEX ├── JESC_PH30_48_2_3.HEX ├── JESC_PH30_96_2_3.HEX ├── JESC_PH40_24_2_3.HEX ├── JESC_PH40_48_2_3.HEX ├── JESC_PH40_96_2_3.HEX ├── JESC_PH50_24_2_3.HEX ├── JESC_PH50_48_2_3.HEX ├── JESC_PH50_96_2_3.HEX ├── JESC_PH5_24_2_3.HEX ├── JESC_PH5_48_2_3.HEX ├── JESC_PH5_96_2_3.HEX ├── JESC_PH70_24_2_3.HEX ├── JESC_PH70_48_2_3.HEX ├── JESC_PH70_96_2_3.HEX ├── JESC_PH90_24_2_3.HEX ├── JESC_PH90_48_2_3.HEX ├── JESC_PH90_96_2_3.HEX ├── JESC_PL0_24_2_3.HEX ├── JESC_PL0_48_2_3.HEX ├── JESC_PL10_24_2_3.HEX ├── JESC_PL10_48_2_3.HEX ├── JESC_PL120_24_2_3.HEX ├── JESC_PL120_48_2_3.HEX ├── JESC_PL15_24_2_3.HEX ├── JESC_PL15_48_2_3.HEX ├── JESC_PL20_24_2_3.HEX ├── JESC_PL20_48_2_3.HEX ├── JESC_PL25_24_2_3.HEX ├── JESC_PL25_48_2_3.HEX ├── JESC_PL30_24_2_3.HEX ├── JESC_PL30_48_2_3.HEX ├── JESC_PL40_24_2_3.HEX ├── JESC_PL40_48_2_3.HEX ├── JESC_PL50_24_2_3.HEX ├── JESC_PL50_48_2_3.HEX ├── JESC_PL5_24_2_3.HEX ├── JESC_PL5_48_2_3.HEX ├── JESC_PL70_24_2_3.HEX ├── JESC_PL70_48_2_3.HEX ├── JESC_PL90_24_2_3.HEX ├── JESC_PL90_48_2_3.HEX ├── JESC_QH0_24_2_3.HEX ├── JESC_QH0_48_2_3.HEX ├── JESC_QH0_96_2_3.HEX ├── JESC_QH10_24_2_3.HEX ├── JESC_QH10_48_2_3.HEX ├── JESC_QH10_96_2_3.HEX ├── JESC_QH120_24_2_3.HEX ├── JESC_QH120_48_2_3.HEX ├── JESC_QH120_96_2_3.HEX ├── JESC_QH15_24_2_3.HEX ├── JESC_QH15_48_2_3.HEX ├── JESC_QH15_96_2_3.HEX ├── JESC_QH20_24_2_3.HEX ├── JESC_QH20_48_2_3.HEX ├── JESC_QH20_96_2_3.HEX ├── JESC_QH25_24_2_3.HEX ├── JESC_QH25_48_2_3.HEX ├── JESC_QH25_96_2_3.HEX ├── JESC_QH30_24_2_3.HEX ├── JESC_QH30_48_2_3.HEX ├── JESC_QH30_96_2_3.HEX ├── JESC_QH40_24_2_3.HEX ├── JESC_QH40_48_2_3.HEX ├── JESC_QH40_96_2_3.HEX ├── JESC_QH50_24_2_3.HEX ├── JESC_QH50_48_2_3.HEX ├── JESC_QH50_96_2_3.HEX ├── JESC_QH5_24_2_3.HEX ├── JESC_QH5_48_2_3.HEX ├── JESC_QH5_96_2_3.HEX ├── JESC_QH70_24_2_3.HEX ├── JESC_QH70_48_2_3.HEX ├── JESC_QH70_96_2_3.HEX ├── JESC_QH90_24_2_3.HEX ├── JESC_QH90_48_2_3.HEX ├── JESC_QH90_96_2_3.HEX ├── JESC_QL0_24_2_3.HEX ├── JESC_QL0_48_2_3.HEX ├── JESC_QL10_24_2_3.HEX ├── JESC_QL10_48_2_3.HEX ├── JESC_QL120_24_2_3.HEX ├── JESC_QL120_48_2_3.HEX ├── JESC_QL15_24_2_3.HEX ├── JESC_QL15_48_2_3.HEX ├── JESC_QL20_24_2_3.HEX ├── JESC_QL20_48_2_3.HEX ├── JESC_QL25_24_2_3.HEX ├── JESC_QL25_48_2_3.HEX ├── JESC_QL30_24_2_3.HEX ├── JESC_QL30_48_2_3.HEX ├── JESC_QL40_24_2_3.HEX ├── JESC_QL40_48_2_3.HEX ├── JESC_QL50_24_2_3.HEX ├── JESC_QL50_48_2_3.HEX ├── JESC_QL5_24_2_3.HEX ├── JESC_QL5_48_2_3.HEX ├── JESC_QL70_24_2_3.HEX ├── JESC_QL70_48_2_3.HEX ├── JESC_QL90_24_2_3.HEX ├── JESC_QL90_48_2_3.HEX ├── JESC_RH0_24_2_3.HEX ├── JESC_RH0_48_2_3.HEX ├── JESC_RH0_96_2_3.HEX ├── JESC_RH10_24_2_3.HEX ├── JESC_RH10_48_2_3.HEX ├── JESC_RH10_96_2_3.HEX ├── JESC_RH120_24_2_3.HEX ├── JESC_RH120_48_2_3.HEX ├── JESC_RH120_96_2_3.HEX ├── JESC_RH15_24_2_3.HEX ├── JESC_RH15_48_2_3.HEX ├── JESC_RH15_96_2_3.HEX ├── JESC_RH20_24_2_3.HEX ├── JESC_RH20_48_2_3.HEX ├── JESC_RH20_96_2_3.HEX ├── JESC_RH25_24_2_3.HEX ├── JESC_RH25_48_2_3.HEX ├── JESC_RH25_96_2_3.HEX ├── JESC_RH30_24_2_3.HEX ├── JESC_RH30_48_2_3.HEX ├── JESC_RH30_96_2_3.HEX ├── JESC_RH40_24_2_3.HEX ├── JESC_RH40_48_2_3.HEX ├── JESC_RH40_96_2_3.HEX ├── JESC_RH50_24_2_3.HEX ├── JESC_RH50_48_2_3.HEX ├── JESC_RH50_96_2_3.HEX ├── JESC_RH5_24_2_3.HEX ├── JESC_RH5_48_2_3.HEX ├── JESC_RH5_96_2_3.HEX ├── JESC_RH70_24_2_3.HEX ├── JESC_RH70_48_2_3.HEX ├── JESC_RH70_96_2_3.HEX ├── JESC_RH90_24_2_3.HEX ├── JESC_RH90_48_2_3.HEX ├── JESC_RH90_96_2_3.HEX ├── JESC_RL0_24_2_3.HEX ├── JESC_RL0_48_2_3.HEX ├── JESC_RL10_24_2_3.HEX ├── JESC_RL10_48_2_3.HEX ├── JESC_RL120_24_2_3.HEX ├── JESC_RL120_48_2_3.HEX ├── JESC_RL15_24_2_3.HEX ├── JESC_RL15_48_2_3.HEX ├── JESC_RL20_24_2_3.HEX ├── JESC_RL20_48_2_3.HEX ├── JESC_RL25_24_2_3.HEX ├── JESC_RL25_48_2_3.HEX ├── JESC_RL30_24_2_3.HEX ├── JESC_RL30_48_2_3.HEX ├── JESC_RL40_24_2_3.HEX ├── JESC_RL40_48_2_3.HEX ├── JESC_RL50_24_2_3.HEX ├── JESC_RL50_48_2_3.HEX ├── JESC_RL5_24_2_3.HEX ├── JESC_RL5_48_2_3.HEX ├── JESC_RL70_24_2_3.HEX ├── JESC_RL70_48_2_3.HEX ├── JESC_RL90_24_2_3.HEX ├── JESC_RL90_48_2_3.HEX ├── JESC_SH0_24_2_3.HEX ├── JESC_SH0_48_2_3.HEX ├── JESC_SH0_96_2_3.HEX ├── JESC_SH10_24_2_3.HEX ├── JESC_SH10_48_2_3.HEX ├── JESC_SH10_96_2_3.HEX ├── JESC_SH120_24_2_3.HEX ├── JESC_SH120_48_2_3.HEX ├── JESC_SH120_96_2_3.HEX ├── JESC_SH15_24_2_3.HEX ├── JESC_SH15_48_2_3.HEX ├── JESC_SH15_96_2_3.HEX ├── JESC_SH20_24_2_3.HEX ├── JESC_SH20_48_2_3.HEX ├── JESC_SH20_96_2_3.HEX ├── JESC_SH25_24_2_3.HEX ├── JESC_SH25_48_2_3.HEX ├── JESC_SH25_96_2_3.HEX ├── JESC_SH30_24_2_3.HEX ├── JESC_SH30_48_2_3.HEX ├── JESC_SH30_96_2_3.HEX ├── JESC_SH40_24_2_3.HEX ├── JESC_SH40_48_2_3.HEX ├── JESC_SH40_96_2_3.HEX ├── JESC_SH50_24_2_3.HEX ├── JESC_SH50_48_2_3.HEX ├── JESC_SH50_96_2_3.HEX ├── JESC_SH5_24_2_3.HEX ├── JESC_SH5_48_2_3.HEX ├── JESC_SH5_96_2_3.HEX ├── JESC_SH70_24_2_3.HEX ├── JESC_SH70_48_2_3.HEX ├── JESC_SH70_96_2_3.HEX ├── JESC_SH90_24_2_3.HEX ├── JESC_SH90_48_2_3.HEX ├── JESC_SH90_96_2_3.HEX ├── JESC_SL0_24_2_3.HEX ├── JESC_SL0_48_2_3.HEX ├── JESC_SL10_24_2_3.HEX ├── JESC_SL10_48_2_3.HEX ├── JESC_SL120_24_2_3.HEX ├── JESC_SL120_48_2_3.HEX ├── JESC_SL15_24_2_3.HEX ├── JESC_SL15_48_2_3.HEX ├── JESC_SL20_24_2_3.HEX ├── JESC_SL20_48_2_3.HEX ├── JESC_SL25_24_2_3.HEX ├── JESC_SL25_48_2_3.HEX ├── JESC_SL30_24_2_3.HEX ├── JESC_SL30_48_2_3.HEX ├── JESC_SL40_24_2_3.HEX ├── JESC_SL40_48_2_3.HEX ├── JESC_SL50_24_2_3.HEX ├── JESC_SL50_48_2_3.HEX ├── JESC_SL5_24_2_3.HEX ├── JESC_SL5_48_2_3.HEX ├── JESC_SL70_24_2_3.HEX ├── JESC_SL70_48_2_3.HEX ├── JESC_SL90_24_2_3.HEX ├── JESC_SL90_48_2_3.HEX ├── JESC_TH0_24_2_3.HEX ├── JESC_TH0_48_2_3.HEX ├── JESC_TH0_96_2_3.HEX ├── JESC_TH10_24_2_3.HEX ├── JESC_TH10_48_2_3.HEX ├── JESC_TH10_96_2_3.HEX ├── JESC_TH120_24_2_3.HEX ├── JESC_TH120_48_2_3.HEX ├── JESC_TH120_96_2_3.HEX ├── JESC_TH15_24_2_3.HEX ├── JESC_TH15_48_2_3.HEX ├── JESC_TH15_96_2_3.HEX ├── JESC_TH20_24_2_3.HEX ├── JESC_TH20_48_2_3.HEX ├── JESC_TH20_96_2_3.HEX ├── JESC_TH25_24_2_3.HEX ├── JESC_TH25_48_2_3.HEX ├── JESC_TH25_96_2_3.HEX ├── JESC_TH30_24_2_3.HEX ├── JESC_TH30_48_2_3.HEX ├── JESC_TH30_96_2_3.HEX ├── JESC_TH40_24_2_3.HEX ├── JESC_TH40_48_2_3.HEX ├── JESC_TH40_96_2_3.HEX ├── JESC_TH50_24_2_3.HEX ├── JESC_TH50_48_2_3.HEX ├── JESC_TH50_96_2_3.HEX ├── JESC_TH5_24_2_3.HEX ├── JESC_TH5_48_2_3.HEX ├── JESC_TH5_96_2_3.HEX ├── JESC_TH70_24_2_3.HEX ├── JESC_TH70_48_2_3.HEX ├── JESC_TH70_96_2_3.HEX ├── JESC_TH90_24_2_3.HEX ├── JESC_TH90_48_2_3.HEX ├── JESC_TH90_96_2_3.HEX ├── JESC_TL0_24_2_3.HEX ├── JESC_TL0_48_2_3.HEX ├── JESC_TL10_24_2_3.HEX ├── JESC_TL10_48_2_3.HEX ├── JESC_TL120_24_2_3.HEX ├── JESC_TL120_48_2_3.HEX ├── JESC_TL15_24_2_3.HEX ├── JESC_TL15_48_2_3.HEX ├── JESC_TL20_24_2_3.HEX ├── JESC_TL20_48_2_3.HEX ├── JESC_TL25_24_2_3.HEX ├── JESC_TL25_48_2_3.HEX ├── JESC_TL30_24_2_3.HEX ├── JESC_TL30_48_2_3.HEX ├── JESC_TL40_24_2_3.HEX ├── JESC_TL40_48_2_3.HEX ├── JESC_TL50_24_2_3.HEX ├── JESC_TL50_48_2_3.HEX ├── JESC_TL5_24_2_3.HEX ├── JESC_TL5_48_2_3.HEX ├── JESC_TL70_24_2_3.HEX ├── JESC_TL70_48_2_3.HEX ├── JESC_TL90_24_2_3.HEX ├── JESC_TL90_48_2_3.HEX ├── JESC_UH0_24_2_3.HEX ├── JESC_UH0_48_2_3.HEX ├── JESC_UH0_96_2_3.HEX ├── JESC_UH10_24_2_3.HEX ├── JESC_UH10_48_2_3.HEX ├── JESC_UH10_96_2_3.HEX ├── JESC_UH120_24_2_3.HEX ├── JESC_UH120_48_2_3.HEX ├── JESC_UH120_96_2_3.HEX ├── JESC_UH15_24_2_3.HEX ├── JESC_UH15_48_2_3.HEX ├── JESC_UH15_96_2_3.HEX ├── JESC_UH20_24_2_3.HEX ├── JESC_UH20_48_2_3.HEX ├── JESC_UH20_96_2_3.HEX ├── JESC_UH25_24_2_3.HEX ├── JESC_UH25_48_2_3.HEX ├── JESC_UH25_96_2_3.HEX ├── JESC_UH30_24_2_3.HEX ├── JESC_UH30_48_2_3.HEX ├── JESC_UH30_96_2_3.HEX ├── JESC_UH40_24_2_3.HEX ├── JESC_UH40_48_2_3.HEX ├── JESC_UH40_96_2_3.HEX ├── JESC_UH50_24_2_3.HEX ├── JESC_UH50_48_2_3.HEX ├── JESC_UH50_96_2_3.HEX ├── JESC_UH5_24_2_3.HEX ├── JESC_UH5_48_2_3.HEX ├── JESC_UH5_96_2_3.HEX ├── JESC_UH70_24_2_3.HEX ├── JESC_UH70_48_2_3.HEX ├── JESC_UH70_96_2_3.HEX ├── JESC_UH90_24_2_3.HEX ├── JESC_UH90_48_2_3.HEX ├── JESC_UH90_96_2_3.HEX ├── JESC_UL0_24_2_3.HEX ├── JESC_UL0_48_2_3.HEX ├── JESC_UL10_24_2_3.HEX ├── JESC_UL10_48_2_3.HEX ├── JESC_UL120_24_2_3.HEX ├── JESC_UL120_48_2_3.HEX ├── JESC_UL15_24_2_3.HEX ├── JESC_UL15_48_2_3.HEX ├── JESC_UL20_24_2_3.HEX ├── JESC_UL20_48_2_3.HEX ├── JESC_UL25_24_2_3.HEX ├── JESC_UL25_48_2_3.HEX ├── JESC_UL30_24_2_3.HEX ├── JESC_UL30_48_2_3.HEX ├── JESC_UL40_24_2_3.HEX ├── JESC_UL40_48_2_3.HEX ├── JESC_UL50_24_2_3.HEX ├── JESC_UL50_48_2_3.HEX ├── JESC_UL5_24_2_3.HEX ├── JESC_UL5_48_2_3.HEX ├── JESC_UL70_24_2_3.HEX ├── JESC_UL70_48_2_3.HEX ├── JESC_UL90_24_2_3.HEX ├── JESC_UL90_48_2_3.HEX ├── JESC_VH0_24_2_3.HEX ├── JESC_VH0_48_2_3.HEX ├── JESC_VH0_96_2_3.HEX ├── JESC_VH10_24_2_3.HEX ├── JESC_VH10_48_2_3.HEX ├── JESC_VH10_96_2_3.HEX ├── JESC_VH120_24_2_3.HEX ├── JESC_VH120_48_2_3.HEX ├── JESC_VH120_96_2_3.HEX ├── JESC_VH15_24_2_3.HEX ├── JESC_VH15_48_2_3.HEX ├── JESC_VH15_96_2_3.HEX ├── JESC_VH20_24_2_3.HEX ├── JESC_VH20_48_2_3.HEX ├── JESC_VH20_96_2_3.HEX ├── JESC_VH25_24_2_3.HEX ├── JESC_VH25_48_2_3.HEX ├── JESC_VH25_96_2_3.HEX ├── JESC_VH30_24_2_3.HEX ├── JESC_VH30_48_2_3.HEX ├── JESC_VH30_96_2_3.HEX ├── JESC_VH40_24_2_3.HEX ├── JESC_VH40_48_2_3.HEX ├── JESC_VH40_96_2_3.HEX ├── JESC_VH50_24_2_3.HEX ├── JESC_VH50_48_2_3.HEX ├── JESC_VH50_96_2_3.HEX ├── JESC_VH5_24_2_3.HEX ├── JESC_VH5_48_2_3.HEX ├── JESC_VH5_96_2_3.HEX ├── JESC_VH70_24_2_3.HEX ├── JESC_VH70_48_2_3.HEX ├── JESC_VH70_96_2_3.HEX ├── JESC_VH90_24_2_3.HEX ├── JESC_VH90_48_2_3.HEX ├── JESC_VH90_96_2_3.HEX ├── JESC_VL0_24_2_3.HEX ├── JESC_VL0_48_2_3.HEX ├── JESC_VL10_24_2_3.HEX ├── JESC_VL10_48_2_3.HEX ├── JESC_VL120_24_2_3.HEX ├── JESC_VL120_48_2_3.HEX ├── JESC_VL15_24_2_3.HEX ├── JESC_VL15_48_2_3.HEX ├── JESC_VL20_24_2_3.HEX ├── JESC_VL20_48_2_3.HEX ├── JESC_VL25_24_2_3.HEX ├── JESC_VL25_48_2_3.HEX ├── JESC_VL30_24_2_3.HEX ├── JESC_VL30_48_2_3.HEX ├── JESC_VL40_24_2_3.HEX ├── JESC_VL40_48_2_3.HEX ├── JESC_VL50_24_2_3.HEX ├── JESC_VL50_48_2_3.HEX ├── JESC_VL5_24_2_3.HEX ├── JESC_VL5_48_2_3.HEX ├── JESC_VL70_24_2_3.HEX ├── JESC_VL70_48_2_3.HEX ├── JESC_VL90_24_2_3.HEX ├── JESC_VL90_48_2_3.HEX ├── JESC_WH0_24_2_3.HEX ├── JESC_WH0_48_2_3.HEX ├── JESC_WH0_96_2_3.HEX ├── JESC_WH10_24_2_3.HEX ├── JESC_WH10_48_2_3.HEX ├── JESC_WH10_96_2_3.HEX ├── JESC_WH120_24_2_3.HEX ├── JESC_WH120_48_2_3.HEX ├── JESC_WH120_96_2_3.HEX ├── JESC_WH15_24_2_3.HEX ├── JESC_WH15_48_2_3.HEX ├── JESC_WH15_96_2_3.HEX ├── JESC_WH20_24_2_3.HEX ├── JESC_WH20_48_2_3.HEX ├── JESC_WH20_96_2_3.HEX ├── JESC_WH25_24_2_3.HEX ├── JESC_WH25_48_2_3.HEX ├── JESC_WH25_96_2_3.HEX ├── JESC_WH30_24_2_3.HEX ├── JESC_WH30_48_2_3.HEX ├── JESC_WH30_96_2_3.HEX ├── JESC_WH40_24_2_3.HEX ├── JESC_WH40_48_2_3.HEX ├── JESC_WH40_96_2_3.HEX ├── JESC_WH50_24_2_3.HEX ├── JESC_WH50_48_2_3.HEX ├── JESC_WH50_96_2_3.HEX ├── JESC_WH5_24_2_3.HEX ├── JESC_WH5_48_2_3.HEX ├── JESC_WH5_96_2_3.HEX ├── JESC_WH70_24_2_3.HEX ├── JESC_WH70_48_2_3.HEX ├── JESC_WH70_96_2_3.HEX ├── JESC_WH90_24_2_3.HEX ├── JESC_WH90_48_2_3.HEX ├── JESC_WH90_96_2_3.HEX ├── JESC_WL0_24_2_3.HEX ├── JESC_WL0_48_2_3.HEX ├── JESC_WL10_24_2_3.HEX ├── JESC_WL10_48_2_3.HEX ├── JESC_WL120_24_2_3.HEX ├── JESC_WL120_48_2_3.HEX ├── JESC_WL15_24_2_3.HEX ├── JESC_WL15_48_2_3.HEX ├── JESC_WL20_24_2_3.HEX ├── JESC_WL20_48_2_3.HEX ├── JESC_WL25_24_2_3.HEX ├── JESC_WL25_48_2_3.HEX ├── JESC_WL30_24_2_3.HEX ├── JESC_WL30_48_2_3.HEX ├── JESC_WL40_24_2_3.HEX ├── JESC_WL40_48_2_3.HEX ├── JESC_WL50_24_2_3.HEX ├── JESC_WL50_48_2_3.HEX ├── JESC_WL5_24_2_3.HEX ├── JESC_WL5_48_2_3.HEX ├── JESC_WL70_24_2_3.HEX ├── JESC_WL70_48_2_3.HEX ├── JESC_WL90_24_2_3.HEX └── JESC_WL90_48_2_3.HEX ├── I.inc ├── J.inc ├── JEsc.asm ├── JEscBootLoad.inc ├── JEscPgm.inc ├── K.inc ├── L.inc ├── M.inc ├── Makefile ├── N.inc ├── O.inc ├── P.inc ├── Q.inc ├── R.inc ├── README.md ├── S.inc ├── SI_EFM8BB1_Defs.inc ├── SI_EFM8BB2_Defs.inc ├── T.inc ├── U.inc ├── V.inc └── W.inc /A.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "A" 26 | ; X X RC X MC MB MA CC X X Cc Cp Bc Bp Ac Ap 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | ; EQU 7 ;i 66 | ; EQU 6 ;i 67 | Rcp_In EQU 5 ;i 68 | ; EQU 4 ;i 69 | Mux_C EQU 3 ;i 70 | Mux_B EQU 2 ;i 71 | Mux_A EQU 1 ;i 72 | Comp_Com EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU 0FFh 76 | P0_PUSHPULL EQU 0 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | 116 | ;********************* 117 | ; PORT 1 definitions * 118 | ;********************* 119 | ; EQU 7 ;i 120 | ; EQU 6 ;i 121 | CcomFET EQU 5 ;o 122 | CpwmFET EQU 4 ;o 123 | BcomFET EQU 3 ;o 124 | BpwmFET EQU 2 ;o 125 | AcomFET EQU 1 ;o 126 | ApwmFET EQU 0 ;o 127 | 128 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 129 | P1_INIT EQU 00h 130 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_SKIP EQU 3Fh 132 | 133 | ApwmFET_on MACRO 134 | setb P1.ApwmFET 135 | IF FETON_DELAY == 0 136 | setb P1.AcomFET 137 | ENDIF 138 | ENDM 139 | ApwmFET_off MACRO 140 | IF FETON_DELAY != 0 141 | clr P1.ApwmFET 142 | ELSE 143 | clr P1.AcomFET 144 | ENDIF 145 | ENDM 146 | BpwmFET_on MACRO 147 | setb P1.BpwmFET 148 | IF FETON_DELAY == 0 149 | setb P1.BcomFET 150 | ENDIF 151 | ENDM 152 | BpwmFET_off MACRO 153 | IF FETON_DELAY != 0 154 | clr P1.BpwmFET 155 | ELSE 156 | clr P1.BcomFET 157 | ENDIF 158 | ENDM 159 | CpwmFET_on MACRO 160 | setb P1.CpwmFET 161 | IF FETON_DELAY == 0 162 | setb P1.CcomFET 163 | ENDIF 164 | ENDM 165 | CpwmFET_off MACRO 166 | IF FETON_DELAY != 0 167 | clr P1.CpwmFET 168 | ELSE 169 | clr P1.CcomFET 170 | ENDIF 171 | ENDM 172 | All_pwmFETs_Off MACRO 173 | IF FETON_DELAY != 0 174 | clr P1.ApwmFET 175 | clr P1.BpwmFET 176 | clr P1.CpwmFET 177 | ELSE 178 | clr P1.AcomFET 179 | clr P1.BcomFET 180 | clr P1.CcomFET 181 | ENDIF 182 | ENDM 183 | 184 | AcomFET_on MACRO 185 | IF FETON_DELAY == 0 186 | clr P1.ApwmFET 187 | ENDIF 188 | setb P1.AcomFET 189 | ENDM 190 | AcomFET_off MACRO 191 | clr P1.AcomFET 192 | ENDM 193 | BcomFET_on MACRO 194 | IF FETON_DELAY == 0 195 | clr P1.BpwmFET 196 | ENDIF 197 | setb P1.BcomFET 198 | ENDM 199 | BcomFET_off MACRO 200 | clr P1.BcomFET 201 | ENDM 202 | CcomFET_on MACRO 203 | IF FETON_DELAY == 0 204 | clr P1.CpwmFET 205 | ENDIF 206 | setb P1.CcomFET 207 | ENDM 208 | CcomFET_off MACRO 209 | clr P1.CcomFET 210 | ENDM 211 | All_comFETs_Off MACRO 212 | clr P1.AcomFET 213 | clr P1.BcomFET 214 | clr P1.CcomFET 215 | ENDM 216 | 217 | Set_Pwm_A MACRO 218 | IF FETON_DELAY == 0 219 | setb P1.AcomFET 220 | mov P1SKIP, #3Eh 221 | ELSE 222 | mov P1SKIP, #3Ch 223 | ENDIF 224 | ENDM 225 | Set_Pwm_B MACRO 226 | IF FETON_DELAY == 0 227 | setb P1.BcomFET 228 | mov P1SKIP, #3Bh 229 | ELSE 230 | mov P1SKIP, #33h 231 | ENDIF 232 | ENDM 233 | Set_Pwm_C MACRO 234 | IF FETON_DELAY == 0 235 | setb P1.CcomFET 236 | mov P1SKIP, #2Fh 237 | ELSE 238 | mov P1SKIP, #0Fh 239 | ENDIF 240 | ENDM 241 | Set_Pwms_Off MACRO 242 | mov P1SKIP, #3Fh 243 | ENDM 244 | 245 | Set_Comp_Phase_A MACRO 246 | mov CMP0MX, #10h ; Set comparator multiplexer to phase A 247 | ENDM 248 | Set_Comp_Phase_B MACRO 249 | mov CMP0MX, #20h ; Set comparator multiplexer to phase B 250 | ENDM 251 | Set_Comp_Phase_C MACRO 252 | mov CMP0MX, #30h ; Set comparator multiplexer to phase C 253 | ENDM 254 | Read_Comp_Out MACRO 255 | mov A, CMP0CN0 ; Read comparator output 256 | ENDM 257 | 258 | 259 | ;********************* 260 | ; PORT 2 definitions * 261 | ;********************* 262 | DebugPin EQU 0 ;o 263 | 264 | P2_PUSHPULL EQU (1 SHL DebugPin) 265 | 266 | 267 | ;********************** 268 | ; MCU specific macros * 269 | ;********************** 270 | Interrupt_Table_Definition MACRO 271 | CSEG AT 0 ; Code segment start 272 | jmp reset 273 | CSEG AT 03h ; Int0 interrupt 274 | jmp int0_int 275 | IF MCU_48MHZ == 1 276 | CSEG AT 0Bh ; Timer0 overflow interrupt 277 | jmp t0_int 278 | ENDIF 279 | CSEG AT 13h ; Int1 interrupt 280 | jmp int1_int 281 | CSEG AT 1Bh ; Timer1 overflow interrupt 282 | jmp t1_int 283 | CSEG AT 2Bh ; Timer2 overflow interrupt 284 | jmp t2_int 285 | CSEG AT 5Bh ; Pca interrupt 286 | jmp pca_int 287 | CSEG AT 73h ; Timer3 overflow/compare interrupt 288 | jmp t3_int 289 | ENDM 290 | 291 | Initialize_Xbar MACRO 292 | mov XBR2, #40h ; Xbar enabled 293 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 294 | ENDM 295 | 296 | Initialize_Comparator MACRO 297 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 298 | mov CMP0MD, #00h ; Comparator response time 100ns 299 | ENDM 300 | Initialize_Adc MACRO 301 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 302 | IF MCU_48MHZ == 0 303 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 304 | ELSE 305 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 306 | ENDIF 307 | mov ADC0MX, #10h ; Select temp sensor input 308 | mov ADC0CN0, #80h ; ADC enabled 309 | mov ADC0CN1, #01h ; Common mode buffer enabled 310 | ENDM 311 | Start_Adc MACRO 312 | mov ADC0CN0, #90h ; ADC start 313 | ENDM 314 | Read_Adc_Result MACRO 315 | mov Temp1, ADC0L 316 | mov Temp2, ADC0H 317 | ENDM 318 | Stop_Adc MACRO 319 | ENDM 320 | Set_RPM_Out MACRO 321 | ENDM 322 | Clear_RPM_Out MACRO 323 | ENDM 324 | Set_LED_0 MACRO 325 | ENDM 326 | Clear_LED_0 MACRO 327 | ENDM 328 | Set_LED_1 MACRO 329 | ENDM 330 | Clear_LED_1 MACRO 331 | ENDM 332 | Set_LED_2 MACRO 333 | ENDM 334 | Clear_LED_2 MACRO 335 | ENDM 336 | Set_LED_3 MACRO 337 | ENDM 338 | Clear_LED_3 MACRO 339 | ENDM 340 | -------------------------------------------------------------------------------- /API.asm: -------------------------------------------------------------------------------- 1 | // Copyright 2019 Thorsten Laux 2 | 3 | // This file defines constants to allow services to extend 8051 assembler based 4 | // applications. It's dual licensed under GPL3 and MIT licenses. 5 | 6 | // Service entry points for service detection, initialization, interrupts etc 7 | 8 | SERVICE_CURRENT_VERSION EQU 04h 9 | IF MCU_48MHZ == 1 10 | SERVICE_MAGIC EQU 03e00h 11 | SERVICE_VERSION EQU 03e04h 12 | SERVICE_START EQU 0f900h 13 | ELSE 14 | SERVICE_MAGIC EQU 01480h 15 | SERVICE_VERSION EQU 01484h 16 | SERVICE_START EQU 01500h 17 | ENDIF 18 | 19 | SERVICE_INIT EQU (SERVICE_START + 00h) 20 | SERVICE_NOTIFY_FRAME EQU (SERVICE_START + 30h) 21 | SERVICE_BEGIN_WAIT EQU (SERVICE_START + 50h) 22 | SERVICE_END_WAIT EQU (SERVICE_START + 70h) 23 | SERVICE_T4_INT EQU (SERVICE_START + 90h) 24 | SERVICE_T0_INT EQU (SERVICE_START + 0b0h) 25 | 26 | DSEG at 70h 27 | Period_L: DS 1 ; Low byte of commutation period 28 | Period_H: DS 1 ; High byte of commutation period 29 | Rtx_Mask: DS 1 ; RTX Pin Mask 30 | DShot_Frame_Thresh: DS 1 ; Dshot frame length threshold 31 | MemPtr: DS 1 32 | 33 | 34 | -------------------------------------------------------------------------------- /B.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "B". Equals "A", but with A and C fets swapped and pwm and com fets swapped 26 | ; X X RC X MC MB MA CC X X Ap Ac Bp Bc Cp Cc 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | 63 | ;********************* 64 | ; PORT 0 definitions * 65 | ;********************* 66 | ; EQU 7 ;i 67 | ; EQU 6 ;i 68 | Rcp_In EQU 5 ;i 69 | ; EQU 4 ;i 70 | Mux_C EQU 3 ;i 71 | Mux_B EQU 2 ;i 72 | Mux_A EQU 1 ;i 73 | Comp_Com EQU 0 ;i 74 | 75 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 76 | P0_INIT EQU 0FFh 77 | P0_PUSHPULL EQU 0 78 | P0_SKIP EQU 0FFh 79 | 80 | Set_Pwm_Polarity MACRO 81 | IF FETON_DELAY == 0 82 | mov PCA0POL, #00h ; Pwm noninverted 83 | ELSE 84 | mov PCA0POL, #01h ; Damping inverted, pwm noninverted 85 | ENDIF 86 | ENDM 87 | Enable_Power_Pwm_Module MACRO 88 | IF FETON_DELAY == 0 89 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 90 | ELSE 91 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 92 | ENDIF 93 | ENDM 94 | Enable_Damp_Pwm_Module MACRO 95 | IF FETON_DELAY == 0 96 | mov PCA0CPM1, #00h ; Disable 97 | ELSE 98 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 99 | ENDIF 100 | ENDM 101 | Clear_COVF_Interrupt MACRO 102 | anl PCA0PWM, #0DFh 103 | ENDM 104 | Clear_CCF_Interrupt MACRO ; CCF interrupt is only used for FETON_DELAY == 0 105 | anl PCA0CN0, #0FEh 106 | ENDM 107 | Enable_COVF_Interrupt MACRO 108 | orl PCA0PWM, #40h 109 | ENDM 110 | Enable_CCF_Interrupt MACRO 111 | orl PCA0CPM0,#01h 112 | ENDM 113 | Disable_COVF_Interrupt MACRO 114 | anl PCA0PWM, #0BFh 115 | ENDM 116 | Disable_CCF_Interrupt MACRO 117 | anl PCA0CPM0,#0FEh 118 | ENDM 119 | 120 | 121 | ;********************* 122 | ; PORT 1 definitions * 123 | ;********************* 124 | ; EQU 7 ;i 125 | ; EQU 6 ;i 126 | ApwmFET EQU 5 ;o 127 | AcomFET EQU 4 ;o 128 | BpwmFET EQU 3 ;o 129 | BcomFET EQU 2 ;o 130 | CpwmFET EQU 1 ;o 131 | CcomFET EQU 0 ;o 132 | 133 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 134 | P1_INIT EQU 00h 135 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 136 | P1_SKIP EQU 3Fh 137 | 138 | ApwmFET_on MACRO 139 | setb P1.ApwmFET 140 | IF FETON_DELAY == 0 141 | setb P1.AcomFET 142 | ENDIF 143 | ENDM 144 | ApwmFET_off MACRO 145 | IF FETON_DELAY != 0 146 | clr P1.ApwmFET 147 | ELSE 148 | clr P1.AcomFET 149 | ENDIF 150 | ENDM 151 | BpwmFET_on MACRO 152 | setb P1.BpwmFET 153 | IF FETON_DELAY == 0 154 | setb P1.BcomFET 155 | ENDIF 156 | ENDM 157 | BpwmFET_off MACRO 158 | IF FETON_DELAY != 0 159 | clr P1.BpwmFET 160 | ELSE 161 | clr P1.BcomFET 162 | ENDIF 163 | ENDM 164 | CpwmFET_on MACRO 165 | setb P1.CpwmFET 166 | IF FETON_DELAY == 0 167 | setb P1.CcomFET 168 | ENDIF 169 | ENDM 170 | CpwmFET_off MACRO 171 | IF FETON_DELAY != 0 172 | clr P1.CpwmFET 173 | ELSE 174 | clr P1.CcomFET 175 | ENDIF 176 | ENDM 177 | All_pwmFETs_Off MACRO 178 | IF FETON_DELAY != 0 179 | clr P1.ApwmFET 180 | clr P1.BpwmFET 181 | clr P1.CpwmFET 182 | ELSE 183 | clr P1.AcomFET 184 | clr P1.BcomFET 185 | clr P1.CcomFET 186 | ENDIF 187 | ENDM 188 | 189 | AcomFET_on MACRO 190 | IF FETON_DELAY == 0 191 | clr P1.ApwmFET 192 | ENDIF 193 | setb P1.AcomFET 194 | ENDM 195 | AcomFET_off MACRO 196 | clr P1.AcomFET 197 | ENDM 198 | BcomFET_on MACRO 199 | IF FETON_DELAY == 0 200 | clr P1.BpwmFET 201 | ENDIF 202 | setb P1.BcomFET 203 | ENDM 204 | BcomFET_off MACRO 205 | clr P1.BcomFET 206 | ENDM 207 | CcomFET_on MACRO 208 | IF FETON_DELAY == 0 209 | clr P1.CpwmFET 210 | ENDIF 211 | setb P1.CcomFET 212 | ENDM 213 | CcomFET_off MACRO 214 | clr P1.CcomFET 215 | ENDM 216 | All_comFETs_Off MACRO 217 | clr P1.AcomFET 218 | clr P1.BcomFET 219 | clr P1.CcomFET 220 | ENDM 221 | 222 | Set_Pwm_A MACRO 223 | IF FETON_DELAY == 0 224 | setb P1.AcomFET 225 | mov P1SKIP, #1Fh 226 | ELSE 227 | mov P1SKIP, #0Fh 228 | ENDIF 229 | ENDM 230 | Set_Pwm_B MACRO 231 | IF FETON_DELAY == 0 232 | setb P1.BcomFET 233 | mov P1SKIP, #37h 234 | ELSE 235 | mov P1SKIP, #33h 236 | ENDIF 237 | ENDM 238 | Set_Pwm_C MACRO 239 | IF FETON_DELAY == 0 240 | setb P1.CcomFET 241 | mov P1SKIP, #3Dh 242 | ELSE 243 | mov P1SKIP, #3Ch 244 | ENDIF 245 | ENDM 246 | Set_Pwms_Off MACRO 247 | mov P1SKIP, #3Fh 248 | ENDM 249 | 250 | Set_Comp_Phase_A MACRO 251 | mov CMP0MX, #10h ; Set comparator multiplexer to phase A 252 | ENDM 253 | Set_Comp_Phase_B MACRO 254 | mov CMP0MX, #20h ; Set comparator multiplexer to phase B 255 | ENDM 256 | Set_Comp_Phase_C MACRO 257 | mov CMP0MX, #30h ; Set comparator multiplexer to phase C 258 | ENDM 259 | Read_Comp_Out MACRO 260 | mov A, CMP0CN0 ; Read comparator output 261 | ENDM 262 | 263 | 264 | ;********************* 265 | ; PORT 2 definitions * 266 | ;********************* 267 | DebugPin EQU 0 ;o 268 | 269 | P2_PUSHPULL EQU (1 SHL DebugPin) 270 | 271 | 272 | Initialize_Xbar MACRO 273 | mov XBR2, #40h ; Xbar enabled 274 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 275 | ENDM 276 | 277 | Initialize_Comparator MACRO 278 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 279 | mov CMP0MD, #00h ; Comparator response time 100ns 280 | ENDM 281 | Initialize_Adc MACRO 282 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 283 | IF MCU_48MHZ == 0 284 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 285 | ELSE 286 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 287 | ENDIF 288 | mov ADC0MX, #10h ; Select temp sensor input 289 | mov ADC0CN0, #80h ; ADC enabled 290 | mov ADC0CN1, #01h ; Common mode buffer enabled 291 | ENDM 292 | Start_Adc MACRO 293 | mov ADC0CN0, #90h ; ADC start 294 | ENDM 295 | Read_Adc_Result MACRO 296 | mov Temp1, ADC0L 297 | mov Temp2, ADC0H 298 | ENDM 299 | Stop_Adc MACRO 300 | ENDM 301 | Set_RPM_Out MACRO 302 | ENDM 303 | Clear_RPM_Out MACRO 304 | ENDM 305 | Set_LED_0 MACRO 306 | ENDM 307 | Clear_LED_0 MACRO 308 | ENDM 309 | Set_LED_1 MACRO 310 | ENDM 311 | Clear_LED_1 MACRO 312 | ENDM 313 | Set_LED_2 MACRO 314 | ENDM 315 | Clear_LED_2 MACRO 316 | ENDM 317 | Set_LED_3 MACRO 318 | ENDM 319 | Clear_LED_3 MACRO 320 | ENDM 321 | -------------------------------------------------------------------------------- /C.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "C" 26 | ; Ac Ap MC MB MA CC X RC X X X X Cc Cp Bc Bp 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 0 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | AcomFET EQU 7 ;o 66 | ApwmFET EQU 6 ;o 67 | Mux_C EQU 5 ;i 68 | Mux_B EQU 4 ;i 69 | Mux_A EQU 3 ;i 70 | Comp_Com EQU 2 ;i 71 | ; EQU 1 ;i 72 | Rcp_In EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU NOT((1 SHL ApwmFET)+(1 SHL AcomFET)) 76 | P0_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL AcomFET) 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | 116 | ;********************* 117 | ; PORT 1 definitions * 118 | ;********************* 119 | ; EQU 7 ;i 120 | ; EQU 6 ;i 121 | ; EQU 5 ;i 122 | ; EQU 4 ;i 123 | CcomFET EQU 3 ;o 124 | CpwmFET EQU 2 ;o 125 | BcomFET EQU 1 ;o 126 | BpwmFET EQU 0 ;o 127 | 128 | P1_DIGITAL EQU (1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 129 | P1_INIT EQU 00h 130 | P1_PUSHPULL EQU (1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_SKIP EQU 0Fh 132 | 133 | ApwmFET_on MACRO 134 | setb P0.ApwmFET 135 | IF FETON_DELAY == 0 136 | setb P0.AcomFET 137 | ENDIF 138 | ENDM 139 | ApwmFET_off MACRO 140 | IF FETON_DELAY != 0 141 | clr P0.ApwmFET 142 | ELSE 143 | clr P0.AcomFET 144 | ENDIF 145 | ENDM 146 | BpwmFET_on MACRO 147 | setb P1.BpwmFET 148 | IF FETON_DELAY == 0 149 | setb P1.BcomFET 150 | ENDIF 151 | ENDM 152 | BpwmFET_off MACRO 153 | IF FETON_DELAY != 0 154 | clr P1.BpwmFET 155 | ELSE 156 | clr P1.BcomFET 157 | ENDIF 158 | ENDM 159 | CpwmFET_on MACRO 160 | setb P1.CpwmFET 161 | IF FETON_DELAY == 0 162 | setb P1.CcomFET 163 | ENDIF 164 | ENDM 165 | CpwmFET_off MACRO 166 | IF FETON_DELAY != 0 167 | clr P1.CpwmFET 168 | ELSE 169 | clr P1.CcomFET 170 | ENDIF 171 | ENDM 172 | All_pwmFETs_Off MACRO 173 | IF FETON_DELAY != 0 174 | clr P0.ApwmFET 175 | clr P1.BpwmFET 176 | clr P1.CpwmFET 177 | ELSE 178 | clr P0.AcomFET 179 | clr P1.BcomFET 180 | clr P1.CcomFET 181 | ENDIF 182 | ENDM 183 | 184 | AcomFET_on MACRO 185 | IF FETON_DELAY == 0 186 | clr P0.ApwmFET 187 | ENDIF 188 | setb P0.AcomFET 189 | ENDM 190 | AcomFET_off MACRO 191 | clr P0.AcomFET 192 | ENDM 193 | BcomFET_on MACRO 194 | IF FETON_DELAY == 0 195 | clr P1.BpwmFET 196 | ENDIF 197 | setb P1.BcomFET 198 | ENDM 199 | BcomFET_off MACRO 200 | clr P1.BcomFET 201 | ENDM 202 | CcomFET_on MACRO 203 | IF FETON_DELAY == 0 204 | clr P1.CpwmFET 205 | ENDIF 206 | setb P1.CcomFET 207 | ENDM 208 | CcomFET_off MACRO 209 | clr P1.CcomFET 210 | ENDM 211 | All_comFETs_Off MACRO 212 | clr P0.AcomFET 213 | clr P1.BcomFET 214 | clr P1.CcomFET 215 | ENDM 216 | 217 | Set_Pwm_A MACRO 218 | IF FETON_DELAY == 0 219 | setb P0.AcomFET 220 | mov P0SKIP, #0BFh 221 | mov P1SKIP, #0Fh 222 | ELSE 223 | mov P0SKIP, #03Fh 224 | mov P1SKIP, #0Fh 225 | ENDIF 226 | ENDM 227 | Set_Pwm_B MACRO 228 | IF FETON_DELAY == 0 229 | setb P1.BcomFET 230 | mov P0SKIP, #0FFh 231 | mov P1SKIP, #0Eh 232 | ELSE 233 | mov P0SKIP, #0FFh 234 | mov P1SKIP, #0Ch 235 | ENDIF 236 | ENDM 237 | Set_Pwm_C MACRO 238 | IF FETON_DELAY == 0 239 | setb P1.CcomFET 240 | mov P0SKIP, #0FFh 241 | mov P1SKIP, #0Bh 242 | ELSE 243 | mov P0SKIP, #0FFh 244 | mov P1SKIP, #03h 245 | ENDIF 246 | ENDM 247 | Set_Pwms_Off MACRO 248 | mov P0SKIP, #0FFh 249 | mov P1SKIP, #0Fh 250 | ENDM 251 | 252 | Set_Comp_Phase_A MACRO 253 | mov CMP0MX, #32h ; Set comparator multiplexer to phase A 254 | ENDM 255 | Set_Comp_Phase_B MACRO 256 | mov CMP0MX, #42h ; Set comparator multiplexer to phase B 257 | ENDM 258 | Set_Comp_Phase_C MACRO 259 | mov CMP0MX, #52h ; Set comparator multiplexer to phase C 260 | ENDM 261 | Read_Comp_Out MACRO 262 | mov A, CMP0CN0 ; Read comparator output 263 | ENDM 264 | 265 | 266 | ;********************* 267 | ; PORT 2 definitions * 268 | ;********************* 269 | DebugPin EQU 0 ;o 270 | 271 | P2_PUSHPULL EQU (1 SHL DebugPin) 272 | 273 | Initialize_Xbar MACRO 274 | mov XBR2, #40h ; Xbar enabled 275 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 276 | ENDM 277 | 278 | Initialize_Comparator MACRO 279 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 280 | mov CMP0MD, #00h ; Comparator response time 100ns 281 | ENDM 282 | Initialize_Adc MACRO 283 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 284 | IF MCU_48MHZ == 0 285 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 286 | ELSE 287 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 288 | ENDIF 289 | mov ADC0MX, #10h ; Select temp sensor input 290 | mov ADC0CN0, #80h ; ADC enabled 291 | mov ADC0CN1, #01h ; Common mode buffer enabled 292 | ENDM 293 | Start_Adc MACRO 294 | mov ADC0CN0, #90h ; ADC start 295 | ENDM 296 | Read_Adc_Result MACRO 297 | mov Temp1, ADC0L 298 | mov Temp2, ADC0H 299 | ENDM 300 | Stop_Adc MACRO 301 | ENDM 302 | Set_RPM_Out MACRO 303 | ENDM 304 | Clear_RPM_Out MACRO 305 | ENDM 306 | Set_LED_0 MACRO 307 | ENDM 308 | Clear_LED_0 MACRO 309 | ENDM 310 | Set_LED_1 MACRO 311 | ENDM 312 | Clear_LED_1 MACRO 313 | ENDM 314 | Set_LED_2 MACRO 315 | ENDM 316 | Clear_LED_2 MACRO 317 | ENDM 318 | Set_LED_3 MACRO 319 | ENDM 320 | Clear_LED_3 MACRO 321 | ENDM 322 | -------------------------------------------------------------------------------- /D.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "D". Com fets are active low for H/L_N driver and EN_N/PWM driver 26 | ; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | ; EQU 7 ;i 66 | ; EQU 6 ;i 67 | Rcp_In EQU 5 ;i 68 | ; EQU 4 ;i 69 | Comp_Com EQU 3 ;i 70 | Mux_A EQU 2 ;i 71 | Mux_C EQU 1 ;i 72 | Mux_B EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU 0FFh 76 | P0_PUSHPULL EQU 0 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #00h ; Damping noninverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | 116 | ;********************* 117 | ; PORT 1 definitions * 118 | ;********************* 119 | ; EQU 7 ;i 120 | ; EQU 6 ;i 121 | CcomFET EQU 5 ;o 122 | CpwmFET EQU 4 ;o 123 | BcomFET EQU 3 ;o 124 | BpwmFET EQU 2 ;o 125 | AcomFET EQU 1 ;o 126 | ApwmFET EQU 0 ;o 127 | 128 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 129 | P1_INIT EQU (1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 130 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_SKIP EQU 3Fh 132 | 133 | ApwmFET_on MACRO 134 | setb P1.ApwmFET 135 | IF FETON_DELAY == 0 136 | clr P1.AcomFET 137 | ENDIF 138 | ENDM 139 | ApwmFET_off MACRO 140 | IF FETON_DELAY != 0 141 | clr P1.ApwmFET 142 | ELSE 143 | setb P1.AcomFET 144 | ENDIF 145 | ENDM 146 | BpwmFET_on MACRO 147 | setb P1.BpwmFET 148 | IF FETON_DELAY == 0 149 | clr P1.BcomFET 150 | ENDIF 151 | ENDM 152 | BpwmFET_off MACRO 153 | IF FETON_DELAY != 0 154 | clr P1.BpwmFET 155 | ELSE 156 | setb P1.BcomFET 157 | ENDIF 158 | ENDM 159 | CpwmFET_on MACRO 160 | setb P1.CpwmFET 161 | IF FETON_DELAY == 0 162 | clr P1.CcomFET 163 | ENDIF 164 | ENDM 165 | CpwmFET_off MACRO 166 | IF FETON_DELAY != 0 167 | clr P1.CpwmFET 168 | ELSE 169 | setb P1.CcomFET 170 | ENDIF 171 | ENDM 172 | All_pwmFETs_Off MACRO 173 | IF FETON_DELAY != 0 174 | clr P1.ApwmFET 175 | clr P1.BpwmFET 176 | clr P1.CpwmFET 177 | ELSE 178 | setb P1.AcomFET 179 | setb P1.BcomFET 180 | setb P1.CcomFET 181 | ENDIF 182 | ENDM 183 | 184 | AcomFET_on MACRO 185 | IF FETON_DELAY == 0 186 | clr P1.ApwmFET 187 | ENDIF 188 | clr P1.AcomFET 189 | ENDM 190 | AcomFET_off MACRO 191 | setb P1.AcomFET 192 | ENDM 193 | BcomFET_on MACRO 194 | IF FETON_DELAY == 0 195 | clr P1.BpwmFET 196 | ENDIF 197 | clr P1.BcomFET 198 | ENDM 199 | BcomFET_off MACRO 200 | setb P1.BcomFET 201 | ENDM 202 | CcomFET_on MACRO 203 | IF FETON_DELAY == 0 204 | clr P1.CpwmFET 205 | ENDIF 206 | clr P1.CcomFET 207 | ENDM 208 | CcomFET_off MACRO 209 | setb P1.CcomFET 210 | ENDM 211 | All_comFETs_Off MACRO 212 | setb P1.AcomFET 213 | setb P1.BcomFET 214 | setb P1.CcomFET 215 | ENDM 216 | 217 | Set_Pwm_A MACRO 218 | IF FETON_DELAY == 0 219 | clr P1.AcomFET 220 | mov P1SKIP, #3Eh 221 | ELSE 222 | mov P1SKIP, #3Ch 223 | ENDIF 224 | ENDM 225 | Set_Pwm_B MACRO 226 | IF FETON_DELAY == 0 227 | clr P1.BcomFET 228 | mov P1SKIP, #3Bh 229 | ELSE 230 | mov P1SKIP, #33h 231 | ENDIF 232 | ENDM 233 | Set_Pwm_C MACRO 234 | IF FETON_DELAY == 0 235 | clr P1.CcomFET 236 | mov P1SKIP, #2Fh 237 | ELSE 238 | mov P1SKIP, #0Fh 239 | ENDIF 240 | ENDM 241 | Set_Pwms_Off MACRO 242 | mov P1SKIP, #3Fh 243 | ENDM 244 | 245 | Set_Comp_Phase_A MACRO 246 | mov CMP0MX, #23h ; Set comparator multiplexer to phase A 247 | ENDM 248 | Set_Comp_Phase_B MACRO 249 | mov CMP0MX, #03h ; Set comparator multiplexer to phase B 250 | ENDM 251 | Set_Comp_Phase_C MACRO 252 | mov CMP0MX, #13h ; Set comparator multiplexer to phase C 253 | ENDM 254 | Read_Comp_Out MACRO 255 | mov A, CMP0CN0 ; Read comparator output 256 | ENDM 257 | 258 | 259 | ;********************* 260 | ; PORT 2 definitions * 261 | ;********************* 262 | DebugPin EQU 0 ;o 263 | 264 | P2_PUSHPULL EQU (1 SHL DebugPin) 265 | 266 | 267 | ;********************** 268 | ; MCU specific macros * 269 | ;********************** 270 | Interrupt_Table_Definition MACRO 271 | CSEG AT 0 ; Code segment start 272 | jmp reset 273 | CSEG AT 03h ; Int0 interrupt 274 | jmp int0_int 275 | IF MCU_48MHZ == 1 276 | CSEG AT 0Bh ; Timer0 overflow interrupt 277 | jmp t0_int 278 | ENDIF 279 | CSEG AT 13h ; Int1 interrupt 280 | jmp int1_int 281 | CSEG AT 1Bh ; Timer1 overflow interrupt 282 | jmp t1_int 283 | CSEG AT 2Bh ; Timer2 overflow interrupt 284 | jmp t2_int 285 | CSEG AT 5Bh ; Pca interrupt 286 | jmp pca_int 287 | CSEG AT 73h ; Timer3 overflow/compare interrupt 288 | jmp t3_int 289 | ENDM 290 | 291 | Initialize_Xbar MACRO 292 | mov XBR2, #40h ; Xbar enabled 293 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 294 | ENDM 295 | 296 | Initialize_Comparator MACRO 297 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 298 | mov CMP0MD, #00h ; Comparator response time 100ns 299 | ENDM 300 | Initialize_Adc MACRO 301 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 302 | IF MCU_48MHZ == 0 303 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 304 | ELSE 305 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 306 | ENDIF 307 | mov ADC0MX, #10h ; Select temp sensor input 308 | mov ADC0CN0, #80h ; ADC enabled 309 | mov ADC0CN1, #01h ; Common mode buffer enabled 310 | ENDM 311 | Start_Adc MACRO 312 | mov ADC0CN0, #90h ; ADC start 313 | ENDM 314 | Read_Adc_Result MACRO 315 | mov Temp1, ADC0L 316 | mov Temp2, ADC0H 317 | ENDM 318 | Stop_Adc MACRO 319 | ENDM 320 | Set_RPM_Out MACRO 321 | ENDM 322 | Clear_RPM_Out MACRO 323 | ENDM 324 | Set_LED_0 MACRO 325 | ENDM 326 | Clear_LED_0 MACRO 327 | ENDM 328 | Set_LED_1 MACRO 329 | ENDM 330 | Clear_LED_1 MACRO 331 | ENDM 332 | Set_LED_2 MACRO 333 | ENDM 334 | Clear_LED_2 MACRO 335 | ENDM 336 | Set_LED_3 MACRO 337 | ENDM 338 | Clear_LED_3 MACRO 339 | ENDM 340 | -------------------------------------------------------------------------------- /Dshotprog spec BLHeli_S.txt: -------------------------------------------------------------------------------- 1 | 0 DSHOT_CMD_MOTOR_STOP, // Currently not implemented 2 | 1 DSHOT_CMD_BEEP1, // Wait at least length of beep (380ms) before next command 3 | 2 DSHOT_CMD_BEEP2, // Wait at least length of beep (380ms) before next command 4 | 3 DSHOT_CMD_BEEP3, // Wait at least length of beep (400ms) before next command 5 | 4 DSHOT_CMD_BEEP4, // Wait at least length of beep (400ms) before next command 6 | 5 DSHOT_CMD_BEEP5, // Wait at least length of beep (400ms) before next command 7 | 6 DSHOT_CMD_ESC_INFO, // Currently not implemented 8 | 7 DSHOT_CMD_SPIN_DIRECTION_1, // Need 6x, no wait required 9 | 8 DSHOT_CMD_SPIN_DIRECTION_2, // Need 6x, no wait required 10 | 9 DSHOT_CMD_3D_MODE_OFF, // Need 6x, no wait required 11 | 10 DSHOT_CMD_3D_MODE_ON, // Need 6x, no wait required 12 | 11 DSHOT_CMD_SETTINGS_REQUEST, // Currently not implemented 13 | 12 DSHOT_CMD_SAVE_SETTINGS, // Need 6x, wait at least 12ms before next command 14 | 20 DSHOT_CMD_SPIN_DIRECTION_NORMAL, // Need 6x, no wait required 15 | 21 DSHOT_CMD_SPIN_DIRECTION_REVERSED, // Need 6x, no wait required 16 | 22 DSHOT_CMD_LED0_ON, // Currently not implemented 17 | 23 DSHOT_CMD_LED1_ON, // Currently not implemented 18 | 24 DSHOT_CMD_LED2_ON, // Currently not implemented 19 | 25 DSHOT_CMD_LED3_ON, // Currently not implemented 20 | 26 DSHOT_CMD_LED0_OFF, // Currently not implemented 21 | 27 DSHOT_CMD_LED1_OFF, // Currently not implemented 22 | 28 DSHOT_CMD_LED2_OFF, // Currently not implemented 23 | 29 DSHOT_CMD_LED3_OFF, // Currently not implemented 24 | DSHOT_CMD_MAX = 47 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /E.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "E". Equals "A", but with LED control. And with HIP2103/4 driver initialization 26 | ; L1 L0 RC X MC MB MA CC X L2 Cc Cp Bc Bp Ac Ap 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | LED_1 EQU 7 ;o 66 | LED_0 EQU 6 ;o 67 | Rcp_In EQU 5 ;i 68 | ; EQU 4 ;i 69 | Mux_C EQU 3 ;i 70 | Mux_B EQU 2 ;i 71 | Mux_A EQU 1 ;i 72 | Comp_Com EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU NOT((1 SHL LED_0)+(1 SHL LED_1)) 76 | P0_PUSHPULL EQU (1 SHL LED_0)+(1 SHL LED_1) 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | 116 | ;********************* 117 | ; PORT 1 definitions * 118 | ;********************* 119 | ; EQU 7 ;i 120 | LED_2 EQU 6 ;o 121 | CcomFET EQU 5 ;o 122 | CpwmFET EQU 4 ;o 123 | BcomFET EQU 3 ;o 124 | BpwmFET EQU 2 ;o 125 | AcomFET EQU 1 ;o 126 | ApwmFET EQU 0 ;o 127 | 128 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)+(1 SHL LED_2) 129 | P1_INIT EQU 00h 130 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)+(1 SHL LED_2) 131 | P1_SKIP EQU 7Fh 132 | 133 | ApwmFET_on MACRO 134 | setb P1.ApwmFET 135 | IF FETON_DELAY == 0 136 | setb P1.AcomFET 137 | ENDIF 138 | ENDM 139 | ApwmFET_off MACRO 140 | IF FETON_DELAY != 0 141 | clr P1.ApwmFET 142 | ELSE 143 | clr P1.AcomFET 144 | ENDIF 145 | ENDM 146 | BpwmFET_on MACRO 147 | setb P1.BpwmFET 148 | IF FETON_DELAY == 0 149 | setb P1.BcomFET 150 | ENDIF 151 | ENDM 152 | BpwmFET_off MACRO 153 | IF FETON_DELAY != 0 154 | clr P1.BpwmFET 155 | ELSE 156 | clr P1.BcomFET 157 | ENDIF 158 | ENDM 159 | CpwmFET_on MACRO 160 | setb P1.CpwmFET 161 | IF FETON_DELAY == 0 162 | setb P1.CcomFET 163 | ENDIF 164 | ENDM 165 | CpwmFET_off MACRO 166 | IF FETON_DELAY != 0 167 | clr P1.CpwmFET 168 | ELSE 169 | clr P1.CcomFET 170 | ENDIF 171 | ENDM 172 | All_pwmFETs_Off MACRO 173 | IF FETON_DELAY != 0 174 | clr P1.ApwmFET 175 | clr P1.BpwmFET 176 | clr P1.CpwmFET 177 | ELSE 178 | clr P1.AcomFET 179 | clr P1.BcomFET 180 | clr P1.CcomFET 181 | ENDIF 182 | ENDM 183 | 184 | AcomFET_on MACRO 185 | IF FETON_DELAY == 0 186 | clr P1.ApwmFET 187 | ENDIF 188 | setb P1.AcomFET 189 | ENDM 190 | AcomFET_off MACRO 191 | clr P1.AcomFET 192 | ENDM 193 | BcomFET_on MACRO 194 | IF FETON_DELAY == 0 195 | clr P1.BpwmFET 196 | ENDIF 197 | setb P1.BcomFET 198 | ENDM 199 | BcomFET_off MACRO 200 | clr P1.BcomFET 201 | ENDM 202 | CcomFET_on MACRO 203 | IF FETON_DELAY == 0 204 | clr P1.CpwmFET 205 | ENDIF 206 | setb P1.CcomFET 207 | ENDM 208 | CcomFET_off MACRO 209 | clr P1.CcomFET 210 | ENDM 211 | All_comFETs_Off MACRO 212 | clr P1.AcomFET 213 | clr P1.BcomFET 214 | clr P1.CcomFET 215 | ENDM 216 | 217 | Set_Pwm_A MACRO 218 | IF FETON_DELAY == 0 219 | setb P1.AcomFET 220 | mov P1SKIP, #7Eh 221 | ELSE 222 | mov P1SKIP, #7Ch 223 | ENDIF 224 | ENDM 225 | Set_Pwm_B MACRO 226 | IF FETON_DELAY == 0 227 | setb P1.BcomFET 228 | mov P1SKIP, #7Bh 229 | ELSE 230 | mov P1SKIP, #73h 231 | ENDIF 232 | ENDM 233 | Set_Pwm_C MACRO 234 | IF FETON_DELAY == 0 235 | setb P1.CcomFET 236 | mov P1SKIP, #6Fh 237 | ELSE 238 | mov P1SKIP, #4Fh 239 | ENDIF 240 | ENDM 241 | Set_Pwms_Off MACRO 242 | mov P1SKIP, #7Fh 243 | ENDM 244 | 245 | Set_Comp_Phase_A MACRO 246 | mov CMP0MX, #10h ; Set comparator multiplexer to phase A 247 | ENDM 248 | Set_Comp_Phase_B MACRO 249 | mov CMP0MX, #20h ; Set comparator multiplexer to phase B 250 | ENDM 251 | Set_Comp_Phase_C MACRO 252 | mov CMP0MX, #30h ; Set comparator multiplexer to phase C 253 | ENDM 254 | Read_Comp_Out MACRO 255 | mov A, CMP0CN0 ; Read comparator output 256 | ENDM 257 | 258 | 259 | ;********************* 260 | ; PORT 2 definitions * 261 | ;********************* 262 | DebugPin EQU 0 ;o 263 | 264 | P2_PUSHPULL EQU (1 SHL DebugPin) 265 | 266 | Initialize_Xbar MACRO 267 | mov XBR2, #40h ; Xbar enabled 268 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 269 | All_pwmFETs_off ; For unlocking of HIP2103/4 driver circuits 270 | call wait100ms 271 | AcomFET_on 272 | BcomFET_on 273 | CcomFET_on 274 | call wait1ms 275 | All_comFETs_off 276 | ENDM 277 | 278 | Initialize_Comparator MACRO 279 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 280 | mov CMP0MD, #00h ; Comparator response time 100ns 281 | ENDM 282 | Initialize_Adc MACRO 283 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 284 | IF MCU_48MHZ == 0 285 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 286 | ELSE 287 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 288 | ENDIF 289 | mov ADC0MX, #10h ; Select temp sensor input 290 | mov ADC0CN0, #80h ; ADC enabled 291 | mov ADC0CN1, #01h ; Common mode buffer enabled 292 | ENDM 293 | Start_Adc MACRO 294 | mov ADC0CN0, #90h ; ADC start 295 | ENDM 296 | Read_Adc_Result MACRO 297 | mov Temp1, ADC0L 298 | mov Temp2, ADC0H 299 | ENDM 300 | Stop_Adc MACRO 301 | ENDM 302 | Set_RPM_Out MACRO 303 | ENDM 304 | Clear_RPM_Out MACRO 305 | ENDM 306 | Set_LED_0 MACRO 307 | setb P0.LED_0 308 | ENDM 309 | Clear_LED_0 MACRO 310 | clr P0.LED_0 311 | ENDM 312 | Set_LED_1 MACRO 313 | setb P0.LED_1 314 | ENDM 315 | Clear_LED_1 MACRO 316 | clr P0.LED_1 317 | ENDM 318 | Set_LED_2 MACRO 319 | setb P1.LED_2 320 | ENDM 321 | Clear_LED_2 MACRO 322 | clr P1.LED_2 323 | ENDM 324 | Set_LED_3 MACRO 325 | ENDM 326 | Clear_LED_3 MACRO 327 | ENDM 328 | -------------------------------------------------------------------------------- /F.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "F". Equals "A", but with Mux_A and Mux_C swapped 26 | ; X X RC X MA MB MC CC X X Cc Cp Bc Bp Ac Ap 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | 44 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 45 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 46 | 47 | ;**** **** **** **** **** 48 | ; Bootloader definitions 49 | ;**** **** **** **** **** 50 | RTX_PORT EQU P0 ; Receive/Transmit port 51 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 52 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 53 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 54 | RTX_PIN EQU 5 ; RTX pin 55 | 56 | SIGNATURE_001 EQU 0E8h ; Device signature 57 | IF MCU_48MHZ == 0 58 | SIGNATURE_002 EQU 0B1h 59 | ELSE 60 | SIGNATURE_002 EQU 0B2h 61 | ENDIF 62 | 63 | ;********************* 64 | ; PORT 0 definitions * 65 | ;********************* 66 | ; EQU 7 ;i 67 | ; EQU 6 ;i 68 | Rcp_In EQU 5 ;i 69 | ; EQU 4 ;i 70 | Mux_A EQU 3 ;i 71 | Mux_B EQU 2 ;i 72 | Mux_C EQU 1 ;i 73 | Comp_Com EQU 0 ;i 74 | 75 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 76 | P0_INIT EQU 0FFh 77 | P0_PUSHPULL EQU 0 78 | P0_SKIP EQU 0FFh 79 | 80 | Set_Pwm_Polarity MACRO 81 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 82 | ENDM 83 | Enable_Power_Pwm_Module MACRO 84 | IF FETON_DELAY == 0 85 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 86 | ELSE 87 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 88 | ENDIF 89 | ENDM 90 | Enable_Damp_Pwm_Module MACRO 91 | IF FETON_DELAY == 0 92 | mov PCA0CPM1, #00h ; Disable 93 | ELSE 94 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 95 | ENDIF 96 | ENDM 97 | Clear_COVF_Interrupt MACRO 98 | anl PCA0PWM, #0DFh 99 | ENDM 100 | Clear_CCF_Interrupt MACRO 101 | anl PCA0CN0, #0FEh 102 | ENDM 103 | Enable_COVF_Interrupt MACRO 104 | orl PCA0PWM, #40h 105 | ENDM 106 | Enable_CCF_Interrupt MACRO 107 | orl PCA0CPM0,#01h 108 | ENDM 109 | Disable_COVF_Interrupt MACRO 110 | anl PCA0PWM, #0BFh 111 | ENDM 112 | Disable_CCF_Interrupt MACRO 113 | anl PCA0CPM0,#0FEh 114 | ENDM 115 | 116 | 117 | ;********************* 118 | ; PORT 1 definitions * 119 | ;********************* 120 | ; EQU 7 ;i 121 | ; EQU 6 ;i 122 | CcomFET EQU 5 ;o 123 | CpwmFET EQU 4 ;o 124 | BcomFET EQU 3 ;o 125 | BpwmFET EQU 2 ;o 126 | AcomFET EQU 1 ;o 127 | ApwmFET EQU 0 ;o 128 | 129 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 130 | P1_INIT EQU 00h 131 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 132 | P1_SKIP EQU 3Fh 133 | 134 | ApwmFET_on MACRO 135 | setb P1.ApwmFET 136 | IF FETON_DELAY == 0 137 | setb P1.AcomFET 138 | ENDIF 139 | ENDM 140 | ApwmFET_off MACRO 141 | IF FETON_DELAY != 0 142 | clr P1.ApwmFET 143 | ELSE 144 | clr P1.AcomFET 145 | ENDIF 146 | ENDM 147 | BpwmFET_on MACRO 148 | setb P1.BpwmFET 149 | IF FETON_DELAY == 0 150 | setb P1.BcomFET 151 | ENDIF 152 | ENDM 153 | BpwmFET_off MACRO 154 | IF FETON_DELAY != 0 155 | clr P1.BpwmFET 156 | ELSE 157 | clr P1.BcomFET 158 | ENDIF 159 | ENDM 160 | CpwmFET_on MACRO 161 | setb P1.CpwmFET 162 | IF FETON_DELAY == 0 163 | setb P1.CcomFET 164 | ENDIF 165 | ENDM 166 | CpwmFET_off MACRO 167 | IF FETON_DELAY != 0 168 | clr P1.CpwmFET 169 | ELSE 170 | clr P1.CcomFET 171 | ENDIF 172 | ENDM 173 | All_pwmFETs_Off MACRO 174 | IF FETON_DELAY != 0 175 | clr P1.ApwmFET 176 | clr P1.BpwmFET 177 | clr P1.CpwmFET 178 | ELSE 179 | clr P1.AcomFET 180 | clr P1.BcomFET 181 | clr P1.CcomFET 182 | ENDIF 183 | ENDM 184 | 185 | AcomFET_on MACRO 186 | IF FETON_DELAY == 0 187 | clr P1.ApwmFET 188 | ENDIF 189 | setb P1.AcomFET 190 | ENDM 191 | AcomFET_off MACRO 192 | clr P1.AcomFET 193 | ENDM 194 | BcomFET_on MACRO 195 | IF FETON_DELAY == 0 196 | clr P1.BpwmFET 197 | ENDIF 198 | setb P1.BcomFET 199 | ENDM 200 | BcomFET_off MACRO 201 | clr P1.BcomFET 202 | ENDM 203 | CcomFET_on MACRO 204 | IF FETON_DELAY == 0 205 | clr P1.CpwmFET 206 | ENDIF 207 | setb P1.CcomFET 208 | ENDM 209 | CcomFET_off MACRO 210 | clr P1.CcomFET 211 | ENDM 212 | All_comFETs_Off MACRO 213 | clr P1.AcomFET 214 | clr P1.BcomFET 215 | clr P1.CcomFET 216 | ENDM 217 | 218 | Set_Pwm_A MACRO 219 | IF FETON_DELAY == 0 220 | setb P1.AcomFET 221 | mov P1SKIP, #3Eh 222 | ELSE 223 | mov P1SKIP, #3Ch 224 | ENDIF 225 | ENDM 226 | Set_Pwm_B MACRO 227 | IF FETON_DELAY == 0 228 | setb P1.BcomFET 229 | mov P1SKIP, #3Bh 230 | ELSE 231 | mov P1SKIP, #33h 232 | ENDIF 233 | ENDM 234 | Set_Pwm_C MACRO 235 | IF FETON_DELAY == 0 236 | setb P1.CcomFET 237 | mov P1SKIP, #2Fh 238 | ELSE 239 | mov P1SKIP, #0Fh 240 | ENDIF 241 | ENDM 242 | Set_Pwms_Off MACRO 243 | mov P1SKIP, #3Fh 244 | ENDM 245 | 246 | Set_Comp_Phase_A MACRO 247 | mov CMP0MX, #30h ; Set comparator multiplexer to phase A 248 | ENDM 249 | Set_Comp_Phase_B MACRO 250 | mov CMP0MX, #20h ; Set comparator multiplexer to phase B 251 | ENDM 252 | Set_Comp_Phase_C MACRO 253 | mov CMP0MX, #10h ; Set comparator multiplexer to phase C 254 | ENDM 255 | Read_Comp_Out MACRO 256 | mov A, CMP0CN0 ; Read comparator output 257 | ENDM 258 | 259 | 260 | ;********************* 261 | ; PORT 2 definitions * 262 | ;********************* 263 | DebugPin EQU 0 ;o 264 | 265 | 266 | P2_PUSHPULL EQU (1 SHL DebugPin) 267 | 268 | 269 | 270 | Initialize_Xbar MACRO 271 | mov XBR2, #40h ; Xbar enabled 272 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 273 | ENDM 274 | 275 | Initialize_Comparator MACRO 276 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 277 | mov CMP0MD, #00h ; Comparator response time 100ns 278 | ENDM 279 | Initialize_Adc MACRO 280 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 281 | IF MCU_48MHZ == 0 282 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 283 | ELSE 284 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 285 | ENDIF 286 | mov ADC0MX, #10h ; Select temp sensor input 287 | mov ADC0CN0, #80h ; ADC enabled 288 | mov ADC0CN1, #01h ; Common mode buffer enabled 289 | ENDM 290 | Start_Adc MACRO 291 | mov ADC0CN0, #90h ; ADC start 292 | ENDM 293 | Read_Adc_Result MACRO 294 | mov Temp1, ADC0L 295 | mov Temp2, ADC0H 296 | ENDM 297 | Stop_Adc MACRO 298 | ENDM 299 | Set_RPM_Out MACRO 300 | ENDM 301 | Clear_RPM_Out MACRO 302 | ENDM 303 | Set_LED_0 MACRO 304 | ENDM 305 | Clear_LED_0 MACRO 306 | ENDM 307 | Set_LED_1 MACRO 308 | ENDM 309 | Clear_LED_1 MACRO 310 | ENDM 311 | Set_LED_2 MACRO 312 | ENDM 313 | Clear_LED_2 MACRO 314 | ENDM 315 | Set_LED_3 MACRO 316 | ENDM 317 | Clear_LED_3 MACRO 318 | ENDM 319 | -------------------------------------------------------------------------------- /G.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "G" 26 | ; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | DbgWait EQU 7 ;i 66 | ; EQU 6 ;i 67 | Rcp_In EQU 5 ;i 68 | ; EQU 4 ;i 69 | Comp_Com EQU 3 ;i 70 | Mux_A EQU 2 ;i 71 | Mux_C EQU 1 ;i 72 | Mux_B EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU not(1 SHL DbgWait) 76 | P0_PUSHPULL EQU (1 SHL DbgWait) 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | 116 | ;********************* 117 | ; PORT 1 definitions * 118 | ;********************* 119 | ; EQU 7 ;i 120 | ; EQU 6 ;i 121 | CcomFET EQU 5 ;o 122 | CpwmFET EQU 4 ;o 123 | BcomFET EQU 3 ;o 124 | BpwmFET EQU 2 ;o 125 | AcomFET EQU 1 ;o 126 | ApwmFET EQU 0 ;o 127 | 128 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 129 | P1_INIT EQU 00h 130 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_SKIP EQU 3Fh 132 | 133 | ApwmFET_on MACRO 134 | setb P1.ApwmFET 135 | IF FETON_DELAY == 0 136 | setb P1.AcomFET 137 | ENDIF 138 | ENDM 139 | ApwmFET_off MACRO 140 | IF FETON_DELAY != 0 141 | clr P1.ApwmFET 142 | ELSE 143 | clr P1.AcomFET 144 | ENDIF 145 | ENDM 146 | BpwmFET_on MACRO 147 | setb P1.BpwmFET 148 | IF FETON_DELAY == 0 149 | setb P1.BcomFET 150 | ENDIF 151 | ENDM 152 | BpwmFET_off MACRO 153 | IF FETON_DELAY != 0 154 | clr P1.BpwmFET 155 | ELSE 156 | clr P1.BcomFET 157 | ENDIF 158 | ENDM 159 | CpwmFET_on MACRO 160 | setb P1.CpwmFET 161 | IF FETON_DELAY == 0 162 | setb P1.CcomFET 163 | ENDIF 164 | ENDM 165 | CpwmFET_off MACRO 166 | IF FETON_DELAY != 0 167 | clr P1.CpwmFET 168 | ELSE 169 | clr P1.CcomFET 170 | ENDIF 171 | ENDM 172 | All_pwmFETs_Off MACRO 173 | IF FETON_DELAY != 0 174 | clr P1.ApwmFET 175 | clr P1.BpwmFET 176 | clr P1.CpwmFET 177 | ELSE 178 | clr P1.AcomFET 179 | clr P1.BcomFET 180 | clr P1.CcomFET 181 | ENDIF 182 | ENDM 183 | 184 | AcomFET_on MACRO 185 | IF FETON_DELAY == 0 186 | clr P1.ApwmFET 187 | ENDIF 188 | setb P1.AcomFET 189 | ENDM 190 | AcomFET_off MACRO 191 | clr P1.AcomFET 192 | ENDM 193 | BcomFET_on MACRO 194 | IF FETON_DELAY == 0 195 | clr P1.BpwmFET 196 | ENDIF 197 | setb P1.BcomFET 198 | ENDM 199 | BcomFET_off MACRO 200 | clr P1.BcomFET 201 | ENDM 202 | CcomFET_on MACRO 203 | IF FETON_DELAY == 0 204 | clr P1.CpwmFET 205 | ENDIF 206 | setb P1.CcomFET 207 | ENDM 208 | CcomFET_off MACRO 209 | clr P1.CcomFET 210 | ENDM 211 | All_comFETs_Off MACRO 212 | clr P1.AcomFET 213 | clr P1.BcomFET 214 | clr P1.CcomFET 215 | ENDM 216 | 217 | Set_Pwm_A MACRO 218 | IF FETON_DELAY == 0 219 | setb P1.AcomFET 220 | mov P1SKIP, #3Eh 221 | ELSE 222 | mov P1SKIP, #3Ch 223 | ENDIF 224 | ENDM 225 | Set_Pwm_B MACRO 226 | IF FETON_DELAY == 0 227 | setb P1.BcomFET 228 | mov P1SKIP, #3Bh 229 | ELSE 230 | mov P1SKIP, #33h 231 | ENDIF 232 | ENDM 233 | Set_Pwm_C MACRO 234 | IF FETON_DELAY == 0 235 | setb P1.CcomFET 236 | mov P1SKIP, #2Fh 237 | ELSE 238 | mov P1SKIP, #0Fh 239 | ENDIF 240 | ENDM 241 | Set_Pwms_Off MACRO 242 | mov P1SKIP, #3Fh 243 | ENDM 244 | 245 | Set_Comp_Phase_A MACRO 246 | mov CMP0MX, #23h ; Set comparator multiplexer to phase A 247 | ENDM 248 | Set_Comp_Phase_B MACRO 249 | mov CMP0MX, #03h ; Set comparator multiplexer to phase B 250 | ENDM 251 | Set_Comp_Phase_C MACRO 252 | mov CMP0MX, #13h ; Set comparator multiplexer to phase C 253 | ENDM 254 | Read_Comp_Out MACRO 255 | mov A, CMP0CN0 ; Read comparator output 256 | ENDM 257 | 258 | 259 | ;********************* 260 | ; PORT 2 definitions * 261 | ;********************* 262 | DebugPin EQU 0 ;o 263 | DbgFrame EQU 0 264 | 265 | P2_PUSHPULL EQU ((1 SHL DebugPin)) 266 | 267 | Initialize_Xbar MACRO 268 | mov XBR2, #40h ; Xbar enabled 269 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 270 | ENDM 271 | 272 | Initialize_Comparator MACRO 273 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 274 | mov CMP0MD, #00h ; Comparator response time 100ns 275 | ENDM 276 | Initialize_Adc MACRO 277 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 278 | IF MCU_48MHZ == 0 279 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 280 | ELSE 281 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 282 | ENDIF 283 | mov ADC0MX, #10h ; Select temp sensor input 284 | mov ADC0CN0, #80h ; ADC enabled 285 | mov ADC0CN1, #01h ; Common mode buffer enabled 286 | ENDM 287 | Start_Adc MACRO 288 | mov ADC0CN0, #90h ; ADC start 289 | ENDM 290 | Read_Adc_Result MACRO 291 | mov Temp1, ADC0L 292 | mov Temp2, ADC0H 293 | ENDM 294 | Stop_Adc MACRO 295 | ENDM 296 | Set_RPM_Out MACRO 297 | ENDM 298 | Clear_RPM_Out MACRO 299 | ENDM 300 | Set_LED_0 MACRO 301 | ENDM 302 | Clear_LED_0 MACRO 303 | ENDM 304 | Set_LED_1 MACRO 305 | ENDM 306 | Clear_LED_1 MACRO 307 | ENDM 308 | Set_LED_2 MACRO 309 | ENDM 310 | Clear_LED_2 MACRO 311 | ENDM 312 | Set_LED_3 MACRO 313 | ENDM 314 | Clear_LED_3 MACRO 315 | ENDM 316 | -------------------------------------------------------------------------------- /H.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "H". 26 | ; RC X X X MA MB CC MC X Ap Bp Cp X Ac Bc Cc 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 7 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | 63 | ;********************* 64 | ; PORT 0 definitions * 65 | ;********************* 66 | Rcp_In EQU 7 ;i 67 | ; EQU 6 ;i 68 | ; EQU 5 ;i 69 | ; EQU 4 ;i 70 | Mux_A EQU 3 ;i 71 | Mux_B EQU 2 ;i 72 | Comp_Com EQU 1 ;i 73 | Mux_C EQU 0 ;i 74 | 75 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 76 | P0_INIT EQU 0FFh 77 | P0_PUSHPULL EQU 0 78 | P0_SKIP EQU 0FFh 79 | 80 | Set_Pwm_Polarity MACRO 81 | IF FETON_DELAY == 0 82 | mov PCA0POL, #00h ; Pwm noninverted 83 | ELSE 84 | mov PCA0POL, #01h ; Damping inverted, pwm noninverted 85 | ENDIF 86 | ENDM 87 | Enable_Power_Pwm_Module MACRO 88 | IF FETON_DELAY == 0 89 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 90 | ELSE 91 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 92 | ENDIF 93 | ENDM 94 | Enable_Damp_Pwm_Module MACRO 95 | IF FETON_DELAY == 0 96 | mov PCA0CPM1, #00h ; Disable 97 | ELSE 98 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 99 | ENDIF 100 | ENDM 101 | Clear_COVF_Interrupt MACRO 102 | anl PCA0PWM, #0DFh 103 | ENDM 104 | Clear_CCF_Interrupt MACRO ; CCF interrupt is only used for FETON_DELAY == 0 105 | anl PCA0CN0, #0FEh 106 | ENDM 107 | Enable_COVF_Interrupt MACRO 108 | orl PCA0PWM, #40h 109 | ENDM 110 | Enable_CCF_Interrupt MACRO 111 | orl PCA0CPM0,#01h 112 | ENDM 113 | Disable_COVF_Interrupt MACRO 114 | anl PCA0PWM, #0BFh 115 | ENDM 116 | Disable_CCF_Interrupt MACRO 117 | anl PCA0CPM0,#0FEh 118 | ENDM 119 | 120 | 121 | ;********************* 122 | ; PORT 1 definitions * 123 | ;********************* 124 | ; EQU 7 ;i 125 | ApwmFET EQU 6 ;o 126 | BpwmFET EQU 5 ;o 127 | CpwmFET EQU 4 ;o 128 | ; EQU 3 ;i 129 | AcomFET EQU 2 ;o 130 | BcomFET EQU 1 ;o 131 | CcomFET EQU 0 ;o 132 | 133 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 134 | P1_INIT EQU 00h 135 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 136 | P1_SKIP EQU 7Fh 137 | 138 | ApwmFET_on MACRO 139 | setb P1.ApwmFET 140 | IF FETON_DELAY == 0 141 | setb P1.AcomFET 142 | ENDIF 143 | ENDM 144 | ApwmFET_off MACRO 145 | IF FETON_DELAY != 0 146 | clr P1.ApwmFET 147 | ELSE 148 | clr P1.AcomFET 149 | ENDIF 150 | ENDM 151 | BpwmFET_on MACRO 152 | setb P1.BpwmFET 153 | IF FETON_DELAY == 0 154 | setb P1.BcomFET 155 | ENDIF 156 | ENDM 157 | BpwmFET_off MACRO 158 | IF FETON_DELAY != 0 159 | clr P1.BpwmFET 160 | ELSE 161 | clr P1.BcomFET 162 | ENDIF 163 | ENDM 164 | CpwmFET_on MACRO 165 | setb P1.CpwmFET 166 | IF FETON_DELAY == 0 167 | setb P1.CcomFET 168 | ENDIF 169 | ENDM 170 | CpwmFET_off MACRO 171 | IF FETON_DELAY != 0 172 | clr P1.CpwmFET 173 | ELSE 174 | clr P1.CcomFET 175 | ENDIF 176 | ENDM 177 | All_pwmFETs_Off MACRO 178 | IF FETON_DELAY != 0 179 | clr P1.ApwmFET 180 | clr P1.BpwmFET 181 | clr P1.CpwmFET 182 | ELSE 183 | clr P1.AcomFET 184 | clr P1.BcomFET 185 | clr P1.CcomFET 186 | ENDIF 187 | ENDM 188 | 189 | AcomFET_on MACRO 190 | IF FETON_DELAY == 0 191 | clr P1.ApwmFET 192 | ENDIF 193 | setb P1.AcomFET 194 | ENDM 195 | AcomFET_off MACRO 196 | clr P1.AcomFET 197 | ENDM 198 | BcomFET_on MACRO 199 | IF FETON_DELAY == 0 200 | clr P1.BpwmFET 201 | ENDIF 202 | setb P1.BcomFET 203 | ENDM 204 | BcomFET_off MACRO 205 | clr P1.BcomFET 206 | ENDM 207 | CcomFET_on MACRO 208 | IF FETON_DELAY == 0 209 | clr P1.CpwmFET 210 | ENDIF 211 | setb P1.CcomFET 212 | ENDM 213 | CcomFET_off MACRO 214 | clr P1.CcomFET 215 | ENDM 216 | All_comFETs_Off MACRO 217 | clr P1.AcomFET 218 | clr P1.BcomFET 219 | clr P1.CcomFET 220 | ENDM 221 | 222 | Set_Pwm_A MACRO 223 | IF FETON_DELAY == 0 224 | setb P1.AcomFET 225 | mov P1SKIP, #3Fh 226 | ELSE 227 | mov P1SKIP, #3Bh 228 | ENDIF 229 | ENDM 230 | Set_Pwm_B MACRO 231 | IF FETON_DELAY == 0 232 | setb P1.BcomFET 233 | mov P1SKIP, #5Fh 234 | ELSE 235 | mov P1SKIP, #5Dh 236 | ENDIF 237 | ENDM 238 | Set_Pwm_C MACRO 239 | IF FETON_DELAY == 0 240 | setb P1.CcomFET 241 | mov P1SKIP, #6Fh 242 | ELSE 243 | mov P1SKIP, #6Eh 244 | ENDIF 245 | ENDM 246 | Set_Pwms_Off MACRO 247 | mov P1SKIP, #7Fh 248 | ENDM 249 | 250 | Set_Comp_Phase_A MACRO 251 | mov CMP0MX, #31h ; Set comparator multiplexer to phase A 252 | ENDM 253 | Set_Comp_Phase_B MACRO 254 | mov CMP0MX, #21h ; Set comparator multiplexer to phase B 255 | ENDM 256 | Set_Comp_Phase_C MACRO 257 | mov CMP0MX, #01h ; Set comparator multiplexer to phase C 258 | ENDM 259 | Read_Comp_Out MACRO 260 | mov A, CMP0CN0 ; Read comparator output 261 | ENDM 262 | 263 | 264 | ;********************* 265 | ; PORT 2 definitions * 266 | ;********************* 267 | DebugPin EQU 0 ;o 268 | 269 | P2_PUSHPULL EQU (1 SHL DebugPin) 270 | 271 | 272 | ;********************** 273 | ; MCU specific macros * 274 | ;********************** 275 | 276 | Initialize_Xbar MACRO 277 | mov XBR2, #40h ; Xbar enabled 278 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 279 | ENDM 280 | 281 | Initialize_Comparator MACRO 282 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 283 | mov CMP0MD, #00h ; Comparator response time 100ns 284 | ENDM 285 | Initialize_Adc MACRO 286 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 287 | IF MCU_48MHZ == 0 288 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 289 | ELSE 290 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 291 | ENDIF 292 | mov ADC0MX, #10h ; Select temp sensor input 293 | mov ADC0CN0, #80h ; ADC enabled 294 | mov ADC0CN1, #01h ; Common mode buffer enabled 295 | ENDM 296 | Start_Adc MACRO 297 | mov ADC0CN0, #90h ; ADC start 298 | ENDM 299 | Read_Adc_Result MACRO 300 | mov Temp1, ADC0L 301 | mov Temp2, ADC0H 302 | ENDM 303 | Stop_Adc MACRO 304 | ENDM 305 | Set_RPM_Out MACRO 306 | ENDM 307 | Clear_RPM_Out MACRO 308 | ENDM 309 | Set_LED_0 MACRO 310 | ENDM 311 | Clear_LED_0 MACRO 312 | ENDM 313 | Set_LED_1 MACRO 314 | ENDM 315 | Clear_LED_1 MACRO 316 | ENDM 317 | Set_LED_2 MACRO 318 | ENDM 319 | Clear_LED_2 MACRO 320 | ENDM 321 | Set_LED_3 MACRO 322 | ENDM 323 | Clear_LED_3 MACRO 324 | ENDM 325 | -------------------------------------------------------------------------------- /I.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "I" 26 | ; X X RC X MC MB MA CC X X Ac Bc Cc Ap Bp Cp 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | ; EQU 7 ;i 66 | ; EQU 6 ;i 67 | Rcp_In EQU 5 ;i 68 | ; EQU 4 ;i 69 | Mux_C EQU 3 ;i 70 | Mux_B EQU 2 ;i 71 | Mux_A EQU 1 ;i 72 | Comp_Com EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU 0FFh 76 | P0_PUSHPULL EQU 0 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | ;********************* 116 | ; PORT 1 definitions * 117 | ;********************* 118 | ; EQU 7 ;i 119 | ; EQU 6 ;i 120 | AcomFET EQU 5 ;o 121 | BcomFET EQU 4 ;o 122 | CcomFET EQU 3 ;o 123 | ApwmFET EQU 2 ;o 124 | BpwmFET EQU 1 ;o 125 | CpwmFET EQU 0 ;o 126 | 127 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 128 | P1_INIT EQU 00h 129 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 130 | P1_SKIP EQU 3Fh 131 | 132 | ApwmFET_on MACRO 133 | setb P1.ApwmFET 134 | IF FETON_DELAY == 0 135 | setb P1.AcomFET 136 | ENDIF 137 | ENDM 138 | ApwmFET_off MACRO 139 | IF FETON_DELAY != 0 140 | clr P1.ApwmFET 141 | ELSE 142 | clr P1.AcomFET 143 | ENDIF 144 | ENDM 145 | BpwmFET_on MACRO 146 | setb P1.BpwmFET 147 | IF FETON_DELAY == 0 148 | setb P1.BcomFET 149 | ENDIF 150 | ENDM 151 | BpwmFET_off MACRO 152 | IF FETON_DELAY != 0 153 | clr P1.BpwmFET 154 | ELSE 155 | clr P1.BcomFET 156 | ENDIF 157 | ENDM 158 | CpwmFET_on MACRO 159 | setb P1.CpwmFET 160 | IF FETON_DELAY == 0 161 | setb P1.CcomFET 162 | ENDIF 163 | ENDM 164 | CpwmFET_off MACRO 165 | IF FETON_DELAY != 0 166 | clr P1.CpwmFET 167 | ELSE 168 | clr P1.CcomFET 169 | ENDIF 170 | ENDM 171 | All_pwmFETs_Off MACRO 172 | IF FETON_DELAY != 0 173 | clr P1.ApwmFET 174 | clr P1.BpwmFET 175 | clr P1.CpwmFET 176 | ELSE 177 | clr P1.AcomFET 178 | clr P1.BcomFET 179 | clr P1.CcomFET 180 | ENDIF 181 | ENDM 182 | 183 | AcomFET_on MACRO 184 | IF FETON_DELAY == 0 185 | clr P1.ApwmFET 186 | ENDIF 187 | setb P1.AcomFET 188 | ENDM 189 | AcomFET_off MACRO 190 | clr P1.AcomFET 191 | ENDM 192 | BcomFET_on MACRO 193 | IF FETON_DELAY == 0 194 | clr P1.BpwmFET 195 | ENDIF 196 | setb P1.BcomFET 197 | ENDM 198 | BcomFET_off MACRO 199 | clr P1.BcomFET 200 | ENDM 201 | CcomFET_on MACRO 202 | IF FETON_DELAY == 0 203 | clr P1.CpwmFET 204 | ENDIF 205 | setb P1.CcomFET 206 | ENDM 207 | CcomFET_off MACRO 208 | clr P1.CcomFET 209 | ENDM 210 | All_comFETs_Off MACRO 211 | clr P1.AcomFET 212 | clr P1.BcomFET 213 | clr P1.CcomFET 214 | ENDM 215 | 216 | Set_Pwm_A MACRO 217 | IF FETON_DELAY == 0 218 | setb P1.AcomFET 219 | mov P1SKIP, #3Bh 220 | ELSE 221 | mov P1SKIP, #1Bh 222 | ENDIF 223 | ENDM 224 | Set_Pwm_B MACRO 225 | IF FETON_DELAY == 0 226 | setb P1.BcomFET 227 | mov P1SKIP, #3Dh 228 | ELSE 229 | mov P1SKIP, #2Dh 230 | ENDIF 231 | ENDM 232 | Set_Pwm_C MACRO 233 | IF FETON_DELAY == 0 234 | setb P1.CcomFET 235 | mov P1SKIP, #3Eh 236 | ELSE 237 | mov P1SKIP, #36h 238 | ENDIF 239 | ENDM 240 | Set_Pwms_Off MACRO 241 | mov P1SKIP, #7Fh 242 | ENDM 243 | 244 | Set_Comp_Phase_A MACRO 245 | mov CMP0MX, #10h ; Set comparator multiplexer to phase A 246 | ENDM 247 | Set_Comp_Phase_B MACRO 248 | mov CMP0MX, #20h ; Set comparator multiplexer to phase B 249 | ENDM 250 | Set_Comp_Phase_C MACRO 251 | mov CMP0MX, #30h ; Set comparator multiplexer to phase C 252 | ENDM 253 | Read_Comp_Out MACRO 254 | mov A, CMP0CN0 ; Read comparator output 255 | ENDM 256 | 257 | 258 | ;********************* 259 | ; PORT 2 definitions * 260 | ;********************* 261 | DebugPin EQU 0 ;o 262 | 263 | P2_PUSHPULL EQU (1 SHL DebugPin) 264 | 265 | 266 | ;********************** 267 | ; MCU specific macros * 268 | ;********************** 269 | 270 | Initialize_Xbar MACRO 271 | mov XBR2, #40h ; Xbar enabled 272 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 273 | ENDM 274 | 275 | Initialize_Comparator MACRO 276 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 277 | mov CMP0MD, #00h ; Comparator response time 100ns 278 | ENDM 279 | Initialize_Adc MACRO 280 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 281 | IF MCU_48MHZ == 0 282 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 283 | ELSE 284 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 285 | ENDIF 286 | mov ADC0MX, #10h ; Select temp sensor input 287 | mov ADC0CN0, #80h ; ADC enabled 288 | mov ADC0CN1, #01h ; Common mode buffer enabled 289 | ENDM 290 | Start_Adc MACRO 291 | mov ADC0CN0, #90h ; ADC start 292 | ENDM 293 | Read_Adc_Result MACRO 294 | mov Temp1, ADC0L 295 | mov Temp2, ADC0H 296 | ENDM 297 | Stop_Adc MACRO 298 | ENDM 299 | Set_RPM_Out MACRO 300 | ENDM 301 | Clear_RPM_Out MACRO 302 | ENDM 303 | Set_LED_0 MACRO 304 | ENDM 305 | Clear_LED_0 MACRO 306 | ENDM 307 | Set_LED_1 MACRO 308 | ENDM 309 | Clear_LED_1 MACRO 310 | ENDM 311 | Set_LED_2 MACRO 312 | ENDM 313 | Clear_LED_2 MACRO 314 | ENDM 315 | Set_LED_3 MACRO 316 | ENDM 317 | Clear_LED_3 MACRO 318 | ENDM 319 | -------------------------------------------------------------------------------- /J.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "J" 26 | ; L2 L1 L0 RC CC MB MC MA X X Cc Bc Ac Cp Bp Ap 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 43 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 44 | 45 | ;**** **** **** **** **** 46 | ; Bootloader definitions 47 | ;**** **** **** **** **** 48 | RTX_PORT EQU P0 ; Receive/Transmit port 49 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 50 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 51 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 52 | RTX_PIN EQU 4 ; RTX pin 53 | 54 | SIGNATURE_001 EQU 0E8h ; Device signature 55 | IF MCU_48MHZ == 0 56 | SIGNATURE_002 EQU 0B1h 57 | ELSE 58 | SIGNATURE_002 EQU 0B2h 59 | ENDIF 60 | 61 | ;********************* 62 | ; PORT 0 definitions * 63 | ;********************* 64 | LED_2 EQU 7 ;o 65 | LED_1 EQU 6 ;o 66 | LED_0 EQU 5 ;o 67 | Rcp_In EQU 4 ;i 68 | Comp_Com EQU 3 ;i 69 | Mux_B EQU 2 ;i 70 | Mux_C EQU 1 ;i 71 | Mux_A EQU 0 ;i 72 | 73 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 74 | P0_INIT EQU 0FFh 75 | P0_PUSHPULL EQU (1 SHL LED_0)+(1 SHL LED_1)+(1 SHL LED_2) 76 | P0_SKIP EQU 0FFh 77 | 78 | Set_Pwm_Polarity MACRO 79 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 80 | ENDM 81 | Enable_Power_Pwm_Module MACRO 82 | IF FETON_DELAY == 0 83 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 84 | ELSE 85 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 86 | ENDIF 87 | ENDM 88 | Enable_Damp_Pwm_Module MACRO 89 | IF FETON_DELAY == 0 90 | mov PCA0CPM1, #00h ; Disable 91 | ELSE 92 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 93 | ENDIF 94 | ENDM 95 | Clear_COVF_Interrupt MACRO 96 | anl PCA0PWM, #0DFh 97 | ENDM 98 | Clear_CCF_Interrupt MACRO 99 | anl PCA0CN0, #0FEh 100 | ENDM 101 | Enable_COVF_Interrupt MACRO 102 | orl PCA0PWM, #40h 103 | ENDM 104 | Enable_CCF_Interrupt MACRO 105 | orl PCA0CPM0,#01h 106 | ENDM 107 | Disable_COVF_Interrupt MACRO 108 | anl PCA0PWM, #0BFh 109 | ENDM 110 | Disable_CCF_Interrupt MACRO 111 | anl PCA0CPM0,#0FEh 112 | ENDM 113 | 114 | ;********************* 115 | ; PORT 1 definitions * 116 | ;********************* 117 | ; EQU 7 ;i 118 | ; EQU 6 ;i 119 | CcomFET EQU 5 ;o 120 | BcomFET EQU 4 ;o 121 | AcomFET EQU 3 ;o 122 | CpwmFET EQU 2 ;o 123 | BpwmFET EQU 1 ;o 124 | ApwmFET EQU 0 ;o 125 | 126 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 127 | P1_INIT EQU 00h 128 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 129 | P1_SKIP EQU 3Fh 130 | 131 | ApwmFET_on MACRO 132 | setb P1.ApwmFET 133 | IF FETON_DELAY == 0 134 | setb P1.AcomFET 135 | ENDIF 136 | ENDM 137 | ApwmFET_off MACRO 138 | IF FETON_DELAY != 0 139 | clr P1.ApwmFET 140 | ELSE 141 | clr P1.AcomFET 142 | ENDIF 143 | ENDM 144 | BpwmFET_on MACRO 145 | setb P1.BpwmFET 146 | IF FETON_DELAY == 0 147 | setb P1.BcomFET 148 | ENDIF 149 | ENDM 150 | BpwmFET_off MACRO 151 | IF FETON_DELAY != 0 152 | clr P1.BpwmFET 153 | ELSE 154 | clr P1.BcomFET 155 | ENDIF 156 | ENDM 157 | CpwmFET_on MACRO 158 | setb P1.CpwmFET 159 | IF FETON_DELAY == 0 160 | setb P1.CcomFET 161 | ENDIF 162 | ENDM 163 | CpwmFET_off MACRO 164 | IF FETON_DELAY != 0 165 | clr P1.CpwmFET 166 | ELSE 167 | clr P1.CcomFET 168 | ENDIF 169 | ENDM 170 | All_pwmFETs_Off MACRO 171 | IF FETON_DELAY != 0 172 | clr P1.ApwmFET 173 | clr P1.BpwmFET 174 | clr P1.CpwmFET 175 | ELSE 176 | clr P1.AcomFET 177 | clr P1.BcomFET 178 | clr P1.CcomFET 179 | ENDIF 180 | ENDM 181 | 182 | AcomFET_on MACRO 183 | IF FETON_DELAY == 0 184 | clr P1.ApwmFET 185 | ENDIF 186 | setb P1.AcomFET 187 | ENDM 188 | AcomFET_off MACRO 189 | clr P1.AcomFET 190 | ENDM 191 | BcomFET_on MACRO 192 | IF FETON_DELAY == 0 193 | clr P1.BpwmFET 194 | ENDIF 195 | setb P1.BcomFET 196 | ENDM 197 | BcomFET_off MACRO 198 | clr P1.BcomFET 199 | ENDM 200 | CcomFET_on MACRO 201 | IF FETON_DELAY == 0 202 | clr P1.CpwmFET 203 | ENDIF 204 | setb P1.CcomFET 205 | ENDM 206 | CcomFET_off MACRO 207 | clr P1.CcomFET 208 | ENDM 209 | All_comFETs_Off MACRO 210 | clr P1.AcomFET 211 | clr P1.BcomFET 212 | clr P1.CcomFET 213 | ENDM 214 | 215 | Set_Pwm_A MACRO 216 | IF FETON_DELAY == 0 217 | setb P1.AcomFET 218 | mov P1SKIP, #3Eh 219 | ELSE 220 | mov P1SKIP, #36h 221 | ENDIF 222 | ENDM 223 | Set_Pwm_B MACRO 224 | IF FETON_DELAY == 0 225 | setb P1.BcomFET 226 | mov P1SKIP, #3Dh 227 | ELSE 228 | mov P1SKIP, #2Dh 229 | ENDIF 230 | ENDM 231 | Set_Pwm_C MACRO 232 | IF FETON_DELAY == 0 233 | setb P1.CcomFET 234 | mov P1SKIP, #3Bh 235 | ELSE 236 | mov P1SKIP, #1Bh 237 | ENDIF 238 | ENDM 239 | Set_Pwms_Off MACRO 240 | mov P1SKIP, #7Fh 241 | ENDM 242 | 243 | Set_Comp_Phase_A MACRO 244 | mov CMP0MX, #03h ; Set comparator multiplexer to phase A 245 | ENDM 246 | Set_Comp_Phase_B MACRO 247 | mov CMP0MX, #23h ; Set comparator multiplexer to phase B 248 | ENDM 249 | Set_Comp_Phase_C MACRO 250 | mov CMP0MX, #13h ; Set comparator multiplexer to phase C 251 | ENDM 252 | Read_Comp_Out MACRO 253 | mov A, CMP0CN0 ; Read comparator output 254 | ENDM 255 | 256 | 257 | ;********************* 258 | ; PORT 2 definitions * 259 | ;********************* 260 | DebugPin EQU 0 ;o 261 | 262 | P2_PUSHPULL EQU (1 SHL DebugPin) 263 | 264 | 265 | ;********************** 266 | ; MCU specific macros * 267 | ;********************** 268 | 269 | Initialize_Xbar MACRO 270 | mov XBR2, #40h ; Xbar enabled 271 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 272 | ENDM 273 | 274 | Initialize_Comparator MACRO 275 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 276 | mov CMP0MD, #00h ; Comparator response time 100ns 277 | ENDM 278 | Initialize_Adc MACRO 279 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 280 | IF MCU_48MHZ == 0 281 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 282 | ELSE 283 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 284 | ENDIF 285 | mov ADC0MX, #10h ; Select temp sensor input 286 | mov ADC0CN0, #80h ; ADC enabled 287 | mov ADC0CN1, #01h ; Common mode buffer enabled 288 | ENDM 289 | Start_Adc MACRO 290 | mov ADC0CN0, #90h ; ADC start 291 | ENDM 292 | Read_Adc_Result MACRO 293 | mov Temp1, ADC0L 294 | mov Temp2, ADC0H 295 | ENDM 296 | Stop_Adc MACRO 297 | ENDM 298 | Set_RPM_Out MACRO 299 | ENDM 300 | Clear_RPM_Out MACRO 301 | ENDM 302 | Set_LED_0 MACRO 303 | clr P0.LED_0 304 | ENDM 305 | Clear_LED_0 MACRO 306 | setb P0.LED_0 307 | ENDM 308 | Set_LED_1 MACRO 309 | clr P0.LED_1 310 | ENDM 311 | Clear_LED_1 MACRO 312 | setb P0.LED_1 313 | ENDM 314 | Set_LED_2 MACRO 315 | clr P0.LED_2 316 | ENDM 317 | Clear_LED_2 MACRO 318 | setb P0.LED_2 319 | ENDM 320 | Set_LED_3 MACRO 321 | ENDM 322 | Clear_LED_3 MACRO 323 | ENDM 324 | -------------------------------------------------------------------------------- /JEscBootLoad.inc: -------------------------------------------------------------------------------- 1 | ; BLHeli bootloader for SiLabs MCUs. Based upon AVRootloader (copyright HR) 2 | 3 | XTAL EQU 25000000 4 | 5 | BOOT_START EQU 1C00h ; Bootloader segment address 6 | BOOT_DELAY EQU XTAL/4 ; About 250ms (don't set to fast to avoid connection problems) 7 | BOOT_BAUDRATE EQU 19200 ; Only used if no baudrate detection activated, XTAL is than important 8 | BOOT_VERSION EQU 6 ; Version 6 (must be not changed) 9 | BOOT_PAGES EQU 1 ; Number of flash segments for bootloader 10 | 11 | UART_LOOP EQU 26 ; Depends upon timing of putc, getc 12 | BAUDTIME EQU ((XTAL/BOOT_BAUDRATE)/3)-UART_LOOP 13 | 14 | SUCCESS EQU 030h 15 | ERRORVERIFY EQU 0C0h 16 | ERRORCOMMAND EQU 0C1h 17 | ERRORCRC EQU 0C2h 18 | ERRORPROG EQU 0C5h 19 | 20 | POLYNOM EQU 0A001h ; CRC Polynom 21 | 22 | Xl EQU R0 ; Temporary X 23 | Xh EQU R1 24 | Paral EQU R2 ; Params for UART 25 | Parah EQU R3 26 | Cmdl EQU R4 ; Commands 27 | Cmdh EQU R5 28 | Cntl EQU R6 ; Baudtime 29 | Cnth EQU R7 30 | 31 | DSEG AT 20h 32 | Bit_Reg: DS 1 ; Bit storage register 33 | Byte_Reg: DS 1 ; Byte storage register 34 | Crcl: DS 1 ; CRC 16Bit 35 | Crch: DS 1 36 | Baudl: DS 1 ; Baudtime 37 | Baudh: DS 1 38 | Bit_Cnt: DS 1 ; Counter in UART loops 39 | Byte_Cntl: DS 1 ; Generic counter 40 | Byte_Cnth: DS 1 41 | BL_Flash_Key_1: DS 1 ; Flash keys 42 | BL_Flash_Key_2: DS 1 43 | 44 | CSEG AT BOOT_START ; Bootloader start 45 | init:clr IE_EA 46 | ; Select register bank 0 for main program routines 47 | clr PSW.3 ; Select register bank 0 for main program routines 48 | ; Disable the WDT. 49 | mov WDTCN, #0DEh ; Disable watchdog 50 | mov WDTCN, #0ADh 51 | ; Initialize stack 52 | mov SP, #0c0h ; Stack = 64 upper bytes of RAM 53 | ; Initialize clock 54 | mov CLKSEL, #00h ; Set clock divider to 1 55 | mov CLKSEL, #00h ; Set clock divider to 1 56 | 57 | ; Initialize VDD monitor 58 | orl VDM0CN, #080h ; Enable the VDD monitor 59 | mov Baudl, #38h ; Wait 100us 60 | mov Baudh, #03h 61 | acall waitf 62 | ; Initialize flash keys 63 | mov BL_Flash_Key_1, #0A5h ; First key code 64 | mov BL_Flash_Key_2, #0F1h ; Second key code 65 | ; Initialize ports 66 | orl RTX_MDIN, #(1 SHL RTX_PIN) ; Set digital 67 | anl RTX_MDOUT, #NOT(1 SHL RTX_PIN) ; Disable pushpull 68 | setb RTX_PORT.RTX_PIN ; Set data high 69 | mov RTX_SKIP, #0FFh 70 | mov XBR2, #40h; ; Enable crossbar 71 | ; Set number of connect attempts before exiting bootloader 72 | mov Cmdh, #250 73 | 74 | ; Identifier scanning 75 | abd: mov Xl, #(low(BOOT_DELAY / 6)+1) 76 | mov Xh, #(high(BOOT_DELAY / 6)+1) 77 | mov Cmdl, #(high((BOOT_DELAY / 6) SHR 8)+1) 78 | mov Crcl, #0 79 | mov Crch, #0 80 | mov DPTR, #BOOT_SIGN 81 | mov Parah, #(BOOT_MSG - BOOT_SIGN) 82 | mov Baudl, #low(BAUDTIME) 83 | mov Baudh, #high(BAUDTIME) 84 | 85 | wait_for_low: 86 | jnb RTX_PORT.RTX_PIN, ($+5) 87 | ajmp wait_for_low 88 | 89 | ; Identifier (BOOT_SIGN) scanning with timeout and checksum 90 | id1: jb RTX_PORT.RTX_PIN, id3 ; Look for high 91 | djnz Xl, id1 ; Subtract 1 from X (BOOT_DELAY) 92 | djnz Xh, id1 93 | djnz Cmdl, id1 94 | 95 | ajmp exit 96 | 97 | id3: jnb RTX_PORT.RTX_PIN, id4 ; Look for low 98 | djnz Xl, id3 ; Subtract 1 from X (BOOT_DELAY) 99 | djnz Xh, id3 100 | djnz Cmdl, id3 101 | 102 | ajmp exit 103 | 104 | id4: acall getx ; Read character 105 | clr A 106 | movc A, @A+DPTR ; Load BOOT_SIGN character 107 | inc DPTR 108 | clr C 109 | subb A, Paral ; Compare with read character 110 | jz id5 111 | djnz Cmdh, abd ; Retry if not last connect attempt 112 | ajmp exit 113 | 114 | id5: 115 | djnz Parah, id1 116 | 117 | acall getw ; Read CRC 118 | jz ($+4) ; Check CRC 119 | ajmp abd 120 | 121 | ; Send info about chip/bootloader (BOOT_MSG + BOOT_INFO) 122 | mov Parah, #((BOOT_INFO - BOOT_MSG) + 4) 123 | in1: clr A 124 | movc A, @A+DPTR ; Load character 125 | mov Paral, A 126 | inc DPTR 127 | acall putc 128 | djnz Parah, in1 129 | 130 | 131 | ; Main commandloop 132 | ; 0=Run/restart 133 | ; 1=Program flash, 2=Erase flash, 3=Read flash 134 | ; 0xFF=Set address, 0xFE=Set buffer, 0xFD=Keep alive 135 | main:mov Paral, #SUCCESS 136 | mai1:acall putc 137 | mov Crcl, #0 ; Reset CRC 138 | mov Crch, #0 139 | acall getw ; Get command 140 | mov A, Paral 141 | mov Cmdl, A 142 | mov A, Parah 143 | mov Cmdh, A 144 | clr C 145 | mov A, Cmdh 146 | subb A, #0FEh 147 | jc mai2 ; Jump if not set address or set buffer 148 | 149 | acall getw ; Address or number of bytes 150 | mov Byte_Cntl, Paral ; Store number of bytes for set buffer 151 | mov Byte_Cnth, Parah 152 | mov A, Cmdh 153 | jnb ACC.0, mai2 ; Jump if set buffer 154 | 155 | mov DPL, Paral ; Store flash address (for set address) 156 | mov DPH, Parah 157 | 158 | mai2:acall getw ; Get CRC 159 | mov Paral, #ERRORCRC 160 | jnz mai1 161 | clr C 162 | mov A, Cmdh 163 | subb A, #0FEh 164 | jz setbuf ; If command is set buffer, receive data 165 | jnc main 166 | 167 | cjne Cmdh, #0, mai4 ; Jump if command != 0 (and not set buffer) 168 | 169 | ; Run application/restart bootloader 170 | mov A, Cmdl 171 | jz rst 172 | exit:mov Bit_Access, #0 ; Clear variable used by flash lock detect 173 | mov Bit_Access_Int, #0FFh ; Set variable to indicate that program execution came from bootloader 174 | mov BL_Flash_Key_1, #0 ; Set flash keys to invalid values 175 | mov BL_Flash_Key_2, #0 176 | ljmp 0000h 177 | rst: ajmp init 178 | 179 | ; Set buffer 180 | setbuf:mov Xl, Byte_Cntl ; Set number of bytes 181 | mov Xh, Byte_Cnth 182 | inc Xl 183 | inc Xh 184 | set4:djnz Xl, set5 185 | djnz Xh, set5 186 | ajmp set6 187 | 188 | set5:acall getc ; Receive data 189 | mov A, Paral 190 | movx @Xl, A ; Store data in XRAM 191 | ajmp set4 192 | 193 | set6:inc Cmdh 194 | ajmp mai2 195 | 196 | mai4:clr C 197 | mov A, Cmdh 198 | subb A, #3 199 | jnc mai5 ; Jump if command >= 3 200 | 201 | ; Program/erase 202 | mov A, Cmdh 203 | mov C, ACC.0 204 | mov Bit_Reg.0, C 205 | mov Paral, #ERRORPROG 206 | clr C 207 | mov A, DPL 208 | subb A, #low(BOOT_START) 209 | mov A, DPH 210 | subb A, #high(BOOT_START) 211 | jnc mai1 ; Jump if in bootloader segment 212 | jb Bit_Reg.0, pro3 ; Jump if program command 213 | 214 | ; Erase flash 215 | orl PSCTL, #02h ; Set the PSEE bit 216 | orl PSCTL, #01h ; Set the PSWE bit 217 | mov FLKEY, BL_Flash_Key_1 ; First key code 218 | mov FLKEY, BL_Flash_Key_2 ; Second key code 219 | movx @DPTR, A 220 | jnb Bit_Reg.0, pro6 ; Jump if erase command 221 | 222 | ; Program flash 223 | pro3:mov Xl, Byte_Cntl ; Set number of bytes 224 | mov Xh, Byte_Cnth 225 | inc Xl 226 | inc Xh 227 | orl PSCTL, #01h ; Set the PSWE bit 228 | anl PSCTL, #0FDh ; Clear the PSEE bit 229 | pro4:djnz Xl, pro5 230 | djnz Xh, pro5 231 | ajmp pro6 232 | 233 | pro5: 234 | clr C 235 | mov A, DPH ; Check that address is not in bootloader area 236 | subb A, #1Ch 237 | jc ($+5) 238 | 239 | inc DPTR ; Increment flash address 240 | ajmp pro4 241 | 242 | movx A, @Xl ; Read from XRAM 243 | mov FLKEY, BL_Flash_Key_1 ; First key code 244 | mov FLKEY, BL_Flash_Key_2 ; Second key code 245 | movx @DPTR, A ; Write to flash 246 | inc DPTR ; Increment flash address 247 | ajmp pro4 248 | 249 | pro6:anl PSCTL, #0FCh ; Clear the PSEE and PSWE bits 250 | ajmp main ; Successfully done erase or program 251 | 252 | ; Read flash 253 | mai5:mov Paral, #ERRORCOMMAND ; Illegal command 254 | cjne Cmdh, #3, mai6 ; Jump if not read flash command 255 | 256 | rd1: clr A 257 | movc A, @A+DPTR ; Read from flash 258 | inc DPTR ; Increment flash address 259 | mov Paral, A 260 | acall putp 261 | djnz Cmdl, rd1 ; Decrement bytes to read 262 | 263 | acall putw ; CRC 264 | ajmp main 265 | 266 | mai6:ajmp mai1 267 | 268 | 269 | 270 | 271 | ; Send char with crc 272 | putw:mov Paral, Crcl 273 | mov Parah, Crch 274 | acall putc 275 | mov A, Parah 276 | mov Paral, A 277 | putp:mov A, Paral 278 | xrl Crcl, A 279 | mov Bit_Cnt, #8 280 | put1:clr C 281 | mov A, Crch 282 | rrc A 283 | mov Crch, A 284 | mov A, Crcl 285 | rrc A 286 | mov Crcl, A 287 | jnc put2 288 | 289 | xrl Crch, #high(POLYNOM) 290 | xrl Crcl, #low(POLYNOM) 291 | 292 | put2:djnz Bit_Cnt, put1 293 | 294 | 295 | ; Send char 296 | putc:acall waitf 297 | acall waitf 298 | mov Bit_Cnt, #10 299 | mov A, Paral 300 | cpl A 301 | put3:jb Bit_Reg.1, ($+5) 302 | setb RTX_PORT.RTX_PIN ; Set pin high 303 | jnb Bit_Reg.1, ($+5) 304 | clr RTX_PORT.RTX_PIN ; Set pin low 305 | acall waitf 306 | clr C 307 | rrc A 308 | jc put4 309 | 310 | clr Bit_Reg.1 311 | 312 | put4:djnz Bit_Cnt, put3 313 | 314 | ret 315 | 316 | 317 | ; Receive char/word 318 | getw:acall getc 319 | mov A, Paral 320 | mov Parah, A 321 | getc:jb RTX_PORT.RTX_PIN, ($+5) ; Wait for high 322 | ajmp getc 323 | 324 | get1:jnb RTX_PORT.RTX_PIN, ($+5) ; Wait for low 325 | ajmp get1 326 | 327 | getx:mov Bit_Cnt, #8 328 | mov Cntl, Baudl 329 | mov Cnth, Baudh 330 | clr C 331 | mov A, Cnth ; Wait half a baud 332 | rrc A 333 | mov Cnth, A 334 | mov A, Cntl 335 | rrc A 336 | mov Cntl, A 337 | acall waith 338 | get2:acall waitf ; Wait one baud 339 | clr C 340 | mov A, Paral 341 | rrc A 342 | jnb RTX_PORT.RTX_PIN, ($+5) 343 | orl A, #080h 344 | 345 | mov Paral, A 346 | jnb ACC.7, ($+6) 347 | xrl Crcl, #low(POLYNOM) 348 | 349 | clr C 350 | mov A, Crch 351 | rrc A 352 | mov Crch, A 353 | mov A, Crcl 354 | rrc A 355 | mov Crcl, A 356 | jnc get3 357 | 358 | xrl Crch, #high(POLYNOM) 359 | xrl Crcl, #low(POLYNOM) 360 | 361 | get3:djnz Bit_Cnt, get2 362 | 363 | mov A, Crcl 364 | xrl A, Crch 365 | xrl A, Crch 366 | mov Crcl, A 367 | ret 368 | 369 | 370 | ; UART delays 371 | waitf:mov Cntl, Baudl 372 | mov Cnth, Baudh 373 | waith:inc Cntl 374 | inc Cnth 375 | wait1:djnz Cntl, wait1 376 | djnz Cnth, wait1 377 | 378 | setb Bit_Reg.1 379 | ret 380 | 381 | 382 | BOOT_SIGN: DB "BLHeli" 383 | 384 | BOOT_MSG: DB "471d" ; Interface-MCU_BootlaoderRevision 385 | 386 | BOOT_INFO: DB SIGNATURE_001, SIGNATURE_002, BOOT_VERSION, BOOT_PAGES 387 | 388 | -------------------------------------------------------------------------------- /JEscPgm.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; BLHeliTxPgm SiLabs 26 | ; 27 | ; EEPROM is not available in SiLabs MCUs 28 | ; Therefore a segment of the flash is used as "EEPROM" 29 | ; 30 | ;**** **** **** **** **** 31 | 32 | 33 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 34 | ; 35 | ; Read all eeprom parameters routine 36 | ; 37 | ; No assumptions 38 | ; 39 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 40 | read_all_eeprom_parameters: 41 | ; Check initialized signature 42 | mov DPTR, #Eep_Initialized_L 43 | mov Temp1, #Bit_Access 44 | call read_eeprom_byte 45 | mov A, Bit_Access 46 | cjne A, #055h, read_eeprom_store_defaults 47 | inc DPTR ; Now Eep_Initialized_H 48 | call read_eeprom_byte 49 | mov A, Bit_Access 50 | cjne A, #0AAh, read_eeprom_store_defaults 51 | jmp read_eeprom_read 52 | 53 | 54 | read_eeprom_store_defaults: 55 | mov Flash_Key_1, #0A5h 56 | mov Flash_Key_2, #0F1h 57 | call set_default_parameters 58 | call erase_and_store_all_in_eeprom 59 | mov Flash_Key_1, #0 60 | mov Flash_Key_2, #0 61 | jmp read_eeprom_exit 62 | 63 | read_eeprom_read: 64 | ; Read eeprom 65 | mov DPTR, #_Eep_Pgm_Gov_P_Gain 66 | mov Temp1, #_Pgm_Gov_P_Gain 67 | mov Temp4, #10 68 | read_eeprom_block1: 69 | call read_eeprom_byte 70 | inc DPTR 71 | inc Temp1 72 | djnz Temp4, read_eeprom_block1 73 | 74 | mov DPTR, #Eep_Enable_TX_Program 75 | mov Temp1, #Pgm_Enable_TX_Program 76 | mov Temp4, #26 ; 26 parameters 77 | read_eeprom_block2: 78 | call read_eeprom_byte 79 | inc DPTR 80 | inc Temp1 81 | djnz Temp4, read_eeprom_block2 82 | 83 | mov DPTR, #Eep_Dummy ; Set pointer to uncritical area 84 | 85 | read_eeprom_exit: 86 | ret 87 | 88 | 89 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 90 | ; 91 | ; Erase flash and store all parameter value in EEPROM routine 92 | ; 93 | ; No assumptions 94 | ; 95 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 96 | erase_and_store_all_in_eeprom: 97 | clr IE_EA ; Disable interrupts 98 | call read_tags 99 | call erase_flash ; Erase flash 100 | 101 | mov DPTR, #Eep_FW_Main_Revision ; Store firmware main revision 102 | mov A, #EEPROM_FW_MAIN_REVISION 103 | call write_eeprom_byte_from_acc 104 | 105 | inc DPTR ; Now firmware sub revision 106 | mov A, #EEPROM_FW_SUB_REVISION 107 | call write_eeprom_byte_from_acc 108 | 109 | inc DPTR ; Now layout revision 110 | mov A, #EEPROM_LAYOUT_REVISION 111 | call write_eeprom_byte_from_acc 112 | 113 | ; Write eeprom 114 | mov DPTR, #_Eep_Pgm_Gov_P_Gain 115 | mov Temp1, #_Pgm_Gov_P_Gain 116 | mov Temp4, #10 117 | write_eeprom_block1: 118 | call write_eeprom_byte 119 | inc DPTR 120 | inc Temp1 121 | djnz Temp4, write_eeprom_block1 122 | 123 | mov DPTR, #Eep_Enable_TX_Program 124 | mov Temp1, #Pgm_Enable_TX_Program 125 | mov Temp4, #26 ; 26 parameters 126 | write_eeprom_block2: 127 | call write_eeprom_byte 128 | inc DPTR 129 | inc Temp1 130 | djnz Temp4, write_eeprom_block2 131 | 132 | call write_tags 133 | call write_eeprom_signature 134 | mov DPTR, #Eep_Dummy ; Set pointer to uncritical area 135 | ret 136 | 137 | 138 | 139 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 140 | ; 141 | ; Read eeprom byte routine 142 | ; 143 | ; Gives data in A and in address given by Temp1. Assumes address in DPTR 144 | ; Also assumes address high byte to be zero 145 | ; 146 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 147 | read_eeprom_byte: 148 | clr A 149 | movc A, @A+DPTR ; Read from flash 150 | mov @Temp1, A 151 | ret 152 | 153 | 154 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 155 | ; 156 | ; Write eeprom byte routine 157 | ; 158 | ; Assumes data in address given by Temp1, or in accumulator. Assumes address in DPTR 159 | ; Also assumes address high byte to be zero 160 | ; 161 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 162 | write_eeprom_byte: 163 | mov A, @Temp1 164 | write_eeprom_byte_from_acc: 165 | orl PSCTL, #01h ; Set the PSWE bit 166 | anl PSCTL, #0FDh ; Clear the PSEE bit 167 | mov Temp8, A 168 | clr C 169 | mov A, DPH ; Check that address is not in bootloader area 170 | subb A, #1Ch 171 | jc ($+3) 172 | 173 | ret 174 | 175 | mov A, Temp8 176 | mov FLKEY, Flash_Key_1 ; First key code 177 | mov FLKEY, Flash_Key_2 ; Second key code 178 | movx @DPTR, A ; Write to flash 179 | anl PSCTL, #0FEh ; Clear the PSWE bit 180 | ret 181 | 182 | 183 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 184 | ; 185 | ; Erase flash routine (erases the flash segment used for "eeprom" variables) 186 | ; 187 | ; No assumptions 188 | ; 189 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 190 | erase_flash: 191 | orl PSCTL, #02h ; Set the PSEE bit 192 | orl PSCTL, #01h ; Set the PSWE bit 193 | mov FLKEY, Flash_Key_1 ; First key code 194 | mov FLKEY, Flash_Key_2 ; Second key code 195 | mov DPTR, #Eep_Initialized_L 196 | movx @DPTR, A 197 | anl PSCTL, #0FCh ; Clear the PSEE and PSWE bits 198 | ret 199 | 200 | 201 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 202 | ; 203 | ; Write eeprom signature routine 204 | ; 205 | ; No assumptions 206 | ; 207 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 208 | write_eeprom_signature: 209 | mov DPTR, #Eep_Initialized_L 210 | mov A, #055h 211 | call write_eeprom_byte_from_acc 212 | 213 | mov DPTR, #Eep_Initialized_H 214 | mov A, #0AAh 215 | call write_eeprom_byte_from_acc 216 | ret 217 | 218 | 219 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 220 | ; 221 | ; Read all tags from flash and store in temporary storage 222 | ; 223 | ; No assumptions 224 | ; 225 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 226 | read_tags: 227 | mov Temp3, #48 ; Number of tags 228 | mov Temp2, #Temp_Storage ; Set RAM address 229 | mov Temp1, #Bit_Access 230 | mov DPTR, #Eep_ESC_Layout ; Set flash address 231 | read_tag: 232 | call read_eeprom_byte 233 | mov A, Bit_Access 234 | mov @Temp2, A ; Write to RAM 235 | inc Temp2 236 | inc DPTR 237 | djnz Temp3, read_tag 238 | ret 239 | 240 | 241 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 242 | ; 243 | ; Write all tags from temporary storage and store in flash 244 | ; 245 | ; No assumptions 246 | ; 247 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 248 | write_tags: 249 | mov Temp3, #48 ; Number of tags 250 | mov Temp2, #Temp_Storage ; Set RAM address 251 | mov DPTR, #Eep_ESC_Layout ; Set flash address 252 | write_tag: 253 | mov A, @Temp2 ; Read from RAM 254 | call write_eeprom_byte_from_acc 255 | inc Temp2 256 | inc DPTR 257 | djnz Temp3, write_tag 258 | ret 259 | 260 | 261 | ;**;**** **** **** **** **** **** **** **** **** **** **** **** **** 262 | ; 263 | ; Wait 1 second routine 264 | ; 265 | ; No assumptions 266 | ; 267 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 268 | wait1s: 269 | mov Temp5, #5 270 | wait1s_loop: 271 | call wait200ms 272 | djnz Temp5, wait1s_loop 273 | ret 274 | 275 | 276 | ;**;**** **** **** **** **** **** **** **** **** **** **** **** **** 277 | ; 278 | ; Success beep routine 279 | ; 280 | ; No assumptions 281 | ; 282 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 283 | success_beep: 284 | clr IE_EA ; Disable all interrupts 285 | call beep_f1 286 | // call beep_f2 287 | // call beep_f3 288 | // call beep_f4 289 | /// call wait10ms 290 | // call beep_f1 291 | // call beep_f2 292 | // call beep_f3 293 | // call beep_f4 294 | // call wait10ms 295 | ; call beep_f1 296 | ; call beep_f2 297 | ; call beep_f3 298 | ; call beep_f4 299 | setb IE_EA ; Enable all interrupts 300 | ret 301 | 302 | 303 | ;**;**** **** **** **** **** **** **** **** **** **** **** **** **** 304 | ; 305 | ; Success beep inverted routine 306 | ; 307 | ; No assumptions 308 | ; 309 | ;**** **** **** **** **** **** **** **** **** **** **** **** **** 310 | success_beep_inverted: 311 | // clr IE_EA ; Disable all interrupts 312 | 313 | // call beep_f4 314 | // call beep_f3 315 | // call beep_f2 316 | // call beep_f1 317 | // call wait10ms 318 | // call beep_f4 319 | // call beep_f3 320 | // call beep_f2 321 | // call beep_f1 322 | // call wait10ms 323 | // call beep_f4 324 | //// call beep_f3 325 | // call beep_f2 326 | // call beep_f1 327 | // setb IE_EA ; Enable all interrupts 328 | ret 329 | 330 | 331 | -------------------------------------------------------------------------------- /K.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "K". Com fets are active low for H/L_N driver and EN_N/PWM driver 26 | ; X X MC X MB CC MA RC X X Ap Bp Cp Cc Bc Ac Com fets inverted 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 0 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | 63 | ;********************* 64 | ; PORT 0 definitions * 65 | ;********************* 66 | ; EQU 7 ;i 67 | ; EQU 6 ;i 68 | Mux_C EQU 5 ;i 69 | ; EQU 4 ;i 70 | Mux_B EQU 3 ;i 71 | Comp_Com EQU 2 ;i 72 | Mux_A EQU 1 ;i 73 | Rcp_In EQU 0 ;i 74 | 75 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 76 | P0_INIT EQU 0FFh 77 | P0_PUSHPULL EQU 0 78 | P0_SKIP EQU 0FFh 79 | 80 | Set_Pwm_Polarity MACRO 81 | mov PCA0POL, #00h ; Damping noninverted, pwm noninverted 82 | ENDM 83 | Enable_Power_Pwm_Module MACRO 84 | IF FETON_DELAY == 0 85 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 86 | ELSE 87 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 88 | ENDIF 89 | ENDM 90 | Enable_Damp_Pwm_Module MACRO 91 | IF FETON_DELAY == 0 92 | mov PCA0CPM1, #00h ; Disable 93 | ELSE 94 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 95 | ENDIF 96 | ENDM 97 | Clear_COVF_Interrupt MACRO 98 | anl PCA0PWM, #0DFh 99 | ENDM 100 | Clear_CCF_Interrupt MACRO ; CCF interrupt is only used for FETON_DELAY == 0 101 | anl PCA0CN0, #0FEh 102 | ENDM 103 | Enable_COVF_Interrupt MACRO 104 | orl PCA0PWM, #40h 105 | ENDM 106 | Enable_CCF_Interrupt MACRO 107 | orl PCA0CPM0,#01h 108 | ENDM 109 | Disable_COVF_Interrupt MACRO 110 | anl PCA0PWM, #0BFh 111 | ENDM 112 | Disable_CCF_Interrupt MACRO 113 | anl PCA0CPM0,#0FEh 114 | ENDM 115 | 116 | 117 | ;********************* 118 | ; PORT 1 definitions * 119 | ;********************* 120 | ; EQU 7 ;i 121 | ; EQU 6 ;i 122 | ApwmFET EQU 5 ;o 123 | BpwmFET EQU 4 ;o 124 | CpwmFET EQU 3 ;o 125 | CcomFET EQU 2 ;o 126 | BcomFET EQU 1 ;o 127 | AcomFET EQU 0 ;o 128 | 129 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 130 | P1_INIT EQU (1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 132 | P1_SKIP EQU 3Fh 133 | 134 | ApwmFET_on MACRO 135 | setb P1.ApwmFET 136 | IF FETON_DELAY == 0 137 | clr P1.AcomFET 138 | ENDIF 139 | ENDM 140 | ApwmFET_off MACRO 141 | IF FETON_DELAY != 0 142 | clr P1.ApwmFET 143 | ELSE 144 | setb P1.AcomFET 145 | ENDIF 146 | ENDM 147 | BpwmFET_on MACRO 148 | setb P1.BpwmFET 149 | IF FETON_DELAY == 0 150 | clr P1.BcomFET 151 | ENDIF 152 | ENDM 153 | BpwmFET_off MACRO 154 | IF FETON_DELAY != 0 155 | clr P1.BpwmFET 156 | ELSE 157 | setb P1.BcomFET 158 | ENDIF 159 | ENDM 160 | CpwmFET_on MACRO 161 | setb P1.CpwmFET 162 | IF FETON_DELAY == 0 163 | clr P1.CcomFET 164 | ENDIF 165 | ENDM 166 | CpwmFET_off MACRO 167 | IF FETON_DELAY != 0 168 | clr P1.CpwmFET 169 | ELSE 170 | setb P1.CcomFET 171 | ENDIF 172 | ENDM 173 | All_pwmFETs_Off MACRO 174 | IF FETON_DELAY != 0 175 | clr P1.ApwmFET 176 | clr P1.BpwmFET 177 | clr P1.CpwmFET 178 | ELSE 179 | setb P1.AcomFET 180 | setb P1.BcomFET 181 | setb P1.CcomFET 182 | ENDIF 183 | ENDM 184 | 185 | AcomFET_on MACRO 186 | IF FETON_DELAY == 0 187 | clr P1.ApwmFET 188 | ENDIF 189 | clr P1.AcomFET 190 | ENDM 191 | AcomFET_off MACRO 192 | setb P1.AcomFET 193 | ENDM 194 | BcomFET_on MACRO 195 | IF FETON_DELAY == 0 196 | clr P1.BpwmFET 197 | ENDIF 198 | clr P1.BcomFET 199 | ENDM 200 | BcomFET_off MACRO 201 | setb P1.BcomFET 202 | ENDM 203 | CcomFET_on MACRO 204 | IF FETON_DELAY == 0 205 | clr P1.CpwmFET 206 | ENDIF 207 | clr P1.CcomFET 208 | ENDM 209 | CcomFET_off MACRO 210 | setb P1.CcomFET 211 | ENDM 212 | All_comFETs_Off MACRO 213 | setb P1.AcomFET 214 | setb P1.BcomFET 215 | setb P1.CcomFET 216 | ENDM 217 | 218 | Set_Pwm_A MACRO 219 | IF FETON_DELAY == 0 220 | clr P1.AcomFET 221 | mov P1SKIP, #1Fh 222 | ELSE 223 | mov P1SKIP, #1Eh 224 | ENDIF 225 | ENDM 226 | Set_Pwm_B MACRO 227 | IF FETON_DELAY == 0 228 | clr P1.BcomFET 229 | mov P1SKIP, #2Fh 230 | ELSE 231 | mov P1SKIP, #2Dh 232 | ENDIF 233 | ENDM 234 | Set_Pwm_C MACRO 235 | IF FETON_DELAY == 0 236 | clr P1.CcomFET 237 | mov P1SKIP, #37h 238 | ELSE 239 | mov P1SKIP, #33h 240 | ENDIF 241 | ENDM 242 | Set_Pwms_Off MACRO 243 | mov P1SKIP, #3Fh 244 | ENDM 245 | 246 | Set_Comp_Phase_A MACRO 247 | mov CMP0MX, #12h ; Set comparator multiplexer to phase A 248 | ENDM 249 | Set_Comp_Phase_B MACRO 250 | mov CMP0MX, #32h ; Set comparator multiplexer to phase B 251 | ENDM 252 | Set_Comp_Phase_C MACRO 253 | mov CMP0MX, #52h ; Set comparator multiplexer to phase C 254 | ENDM 255 | Read_Comp_Out MACRO 256 | mov A, CMP0CN0 ; Read comparator output 257 | ENDM 258 | 259 | 260 | ;********************* 261 | ; PORT 2 definitions * 262 | ;********************* 263 | DebugPin EQU 0 ;o 264 | 265 | P2_PUSHPULL EQU (1 SHL DebugPin) 266 | 267 | 268 | ;********************** 269 | ; MCU specific macros * 270 | ;********************** 271 | 272 | Initialize_Xbar MACRO 273 | mov XBR2, #40h ; Xbar enabled 274 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 275 | ENDM 276 | 277 | Initialize_Comparator MACRO 278 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 279 | mov CMP0MD, #00h ; Comparator response time 100ns 280 | ENDM 281 | Initialize_Adc MACRO 282 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 283 | IF MCU_48MHZ == 0 284 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 285 | ELSE 286 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 287 | ENDIF 288 | mov ADC0MX, #10h ; Select temp sensor input 289 | mov ADC0CN0, #80h ; ADC enabled 290 | mov ADC0CN1, #01h ; Common mode buffer enabled 291 | ENDM 292 | Start_Adc MACRO 293 | mov ADC0CN0, #90h ; ADC start 294 | ENDM 295 | Read_Adc_Result MACRO 296 | mov Temp1, ADC0L 297 | mov Temp2, ADC0H 298 | ENDM 299 | Stop_Adc MACRO 300 | ENDM 301 | Set_RPM_Out MACRO 302 | ENDM 303 | Clear_RPM_Out MACRO 304 | ENDM 305 | Set_LED_0 MACRO 306 | ENDM 307 | Clear_LED_0 MACRO 308 | ENDM 309 | Set_LED_1 MACRO 310 | ENDM 311 | Clear_LED_1 MACRO 312 | ENDM 313 | Set_LED_2 MACRO 314 | ENDM 315 | Clear_LED_2 MACRO 316 | ENDM 317 | Set_LED_3 MACRO 318 | ENDM 319 | Clear_LED_3 MACRO 320 | ENDM 321 | -------------------------------------------------------------------------------- /L.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "L" 26 | ; X X RC X CC MA MB MC X X Ac Bc Cc Ap Bp Cp 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | ; EQU 7 ;i 66 | ; EQU 6 ;i 67 | Rcp_In EQU 5 ;i 68 | ; EQU 4 ;i 69 | Comp_Com EQU 3 ;i 70 | Mux_A EQU 2 ;i 71 | Mux_B EQU 1 ;i 72 | Mux_C EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU 0FFh 76 | P0_PUSHPULL EQU 0 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | ;********************* 116 | ; PORT 1 definitions * 117 | ;********************* 118 | ; EQU 7 ;i 119 | ; EQU 6 ;i 120 | AcomFET EQU 5 ;o 121 | BcomFET EQU 4 ;o 122 | CcomFET EQU 3 ;o 123 | ApwmFET EQU 2 ;o 124 | BpwmFET EQU 1 ;o 125 | CpwmFET EQU 0 ;o 126 | 127 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 128 | P1_INIT EQU 00h 129 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 130 | P1_SKIP EQU 3Fh 131 | 132 | ApwmFET_on MACRO 133 | setb P1.ApwmFET 134 | IF FETON_DELAY == 0 135 | setb P1.AcomFET 136 | ENDIF 137 | ENDM 138 | ApwmFET_off MACRO 139 | IF FETON_DELAY != 0 140 | clr P1.ApwmFET 141 | ELSE 142 | clr P1.AcomFET 143 | ENDIF 144 | ENDM 145 | BpwmFET_on MACRO 146 | setb P1.BpwmFET 147 | IF FETON_DELAY == 0 148 | setb P1.BcomFET 149 | ENDIF 150 | ENDM 151 | BpwmFET_off MACRO 152 | IF FETON_DELAY != 0 153 | clr P1.BpwmFET 154 | ELSE 155 | clr P1.BcomFET 156 | ENDIF 157 | ENDM 158 | CpwmFET_on MACRO 159 | setb P1.CpwmFET 160 | IF FETON_DELAY == 0 161 | setb P1.CcomFET 162 | ENDIF 163 | ENDM 164 | CpwmFET_off MACRO 165 | IF FETON_DELAY != 0 166 | clr P1.CpwmFET 167 | ELSE 168 | clr P1.CcomFET 169 | ENDIF 170 | ENDM 171 | All_pwmFETs_Off MACRO 172 | IF FETON_DELAY != 0 173 | clr P1.ApwmFET 174 | clr P1.BpwmFET 175 | clr P1.CpwmFET 176 | ELSE 177 | clr P1.AcomFET 178 | clr P1.BcomFET 179 | clr P1.CcomFET 180 | ENDIF 181 | ENDM 182 | 183 | AcomFET_on MACRO 184 | IF FETON_DELAY == 0 185 | clr P1.ApwmFET 186 | ENDIF 187 | setb P1.AcomFET 188 | ENDM 189 | AcomFET_off MACRO 190 | clr P1.AcomFET 191 | ENDM 192 | BcomFET_on MACRO 193 | IF FETON_DELAY == 0 194 | clr P1.BpwmFET 195 | ENDIF 196 | setb P1.BcomFET 197 | ENDM 198 | BcomFET_off MACRO 199 | clr P1.BcomFET 200 | ENDM 201 | CcomFET_on MACRO 202 | IF FETON_DELAY == 0 203 | clr P1.CpwmFET 204 | ENDIF 205 | setb P1.CcomFET 206 | ENDM 207 | CcomFET_off MACRO 208 | clr P1.CcomFET 209 | ENDM 210 | All_comFETs_Off MACRO 211 | clr P1.AcomFET 212 | clr P1.BcomFET 213 | clr P1.CcomFET 214 | ENDM 215 | 216 | Set_Pwm_A MACRO 217 | IF FETON_DELAY == 0 218 | setb P1.AcomFET 219 | mov P1SKIP, #3Bh 220 | ELSE 221 | mov P1SKIP, #1Bh 222 | ENDIF 223 | ENDM 224 | Set_Pwm_B MACRO 225 | IF FETON_DELAY == 0 226 | setb P1.BcomFET 227 | mov P1SKIP, #3Dh 228 | ELSE 229 | mov P1SKIP, #2Dh 230 | ENDIF 231 | ENDM 232 | Set_Pwm_C MACRO 233 | IF FETON_DELAY == 0 234 | setb P1.CcomFET 235 | mov P1SKIP, #3Eh 236 | ELSE 237 | mov P1SKIP, #36h 238 | ENDIF 239 | ENDM 240 | Set_Pwms_Off MACRO 241 | mov P1SKIP, #7Fh 242 | ENDM 243 | 244 | Set_Comp_Phase_A MACRO 245 | mov CMP0MX, #23h ; Set comparator multiplexer to phase A 246 | ENDM 247 | Set_Comp_Phase_B MACRO 248 | mov CMP0MX, #13h ; Set comparator multiplexer to phase B 249 | ENDM 250 | Set_Comp_Phase_C MACRO 251 | mov CMP0MX, #03h ; Set comparator multiplexer to phase C 252 | ENDM 253 | Read_Comp_Out MACRO 254 | mov A, CMP0CN0 ; Read comparator output 255 | ENDM 256 | 257 | 258 | ;********************* 259 | ; PORT 2 definitions * 260 | ;********************* 261 | DebugPin EQU 0 ;o 262 | 263 | P2_PUSHPULL EQU (1 SHL DebugPin) 264 | 265 | 266 | ;********************** 267 | ; MCU specific macros * 268 | ;********************** 269 | 270 | Initialize_Xbar MACRO 271 | mov XBR2, #40h ; Xbar enabled 272 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 273 | ENDM 274 | 275 | Initialize_Comparator MACRO 276 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 277 | mov CMP0MD, #00h ; Comparator response time 100ns 278 | ENDM 279 | Initialize_Adc MACRO 280 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 281 | IF MCU_48MHZ == 0 282 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 283 | ELSE 284 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 285 | ENDIF 286 | mov ADC0MX, #10h ; Select temp sensor input 287 | mov ADC0CN0, #80h ; ADC enabled 288 | mov ADC0CN1, #01h ; Common mode buffer enabled 289 | ENDM 290 | Start_Adc MACRO 291 | mov ADC0CN0, #90h ; ADC start 292 | ENDM 293 | Read_Adc_Result MACRO 294 | mov Temp1, ADC0L 295 | mov Temp2, ADC0H 296 | ENDM 297 | Stop_Adc MACRO 298 | ENDM 299 | Set_RPM_Out MACRO 300 | ENDM 301 | Clear_RPM_Out MACRO 302 | ENDM 303 | Set_LED_0 MACRO 304 | ENDM 305 | Clear_LED_0 MACRO 306 | ENDM 307 | Set_LED_1 MACRO 308 | ENDM 309 | Clear_LED_1 MACRO 310 | ENDM 311 | Set_LED_2 MACRO 312 | ENDM 313 | Clear_LED_2 MACRO 314 | ENDM 315 | Set_LED_3 MACRO 316 | ENDM 317 | Clear_LED_3 MACRO 318 | ENDM 319 | -------------------------------------------------------------------------------- /M.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "M". 26 | ; MA MC CC MB RC L0 X X X Cc Bc Ac Cp Bp Ap X 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 3 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | 63 | ;********************* 64 | ; PORT 0 definitions * 65 | ;********************* 66 | Mux_A EQU 7 ;i 67 | Mux_C EQU 6 ;i 68 | Comp_Com EQU 5 ;i 69 | Mux_B EQU 4 ;i 70 | Rcp_In EQU 3 ;i 71 | LED_0 EQU 2 ;i 72 | ; EQU 1 ;i 73 | ; EQU 0 ;i 74 | 75 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 76 | P0_INIT EQU NOT(1 SHL LED_0) 77 | P0_PUSHPULL EQU (1 SHL LED_0) 78 | P0_SKIP EQU 0FFh 79 | 80 | Set_Pwm_Polarity MACRO 81 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 82 | ENDM 83 | Enable_Power_Pwm_Module MACRO 84 | IF FETON_DELAY == 0 85 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 86 | ELSE 87 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 88 | ENDIF 89 | ENDM 90 | Enable_Damp_Pwm_Module MACRO 91 | IF FETON_DELAY == 0 92 | mov PCA0CPM1, #00h ; Disable 93 | ELSE 94 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 95 | ENDIF 96 | ENDM 97 | Clear_COVF_Interrupt MACRO 98 | anl PCA0PWM, #0DFh 99 | ENDM 100 | Clear_CCF_Interrupt MACRO 101 | anl PCA0CN0, #0FEh 102 | ENDM 103 | Enable_COVF_Interrupt MACRO 104 | orl PCA0PWM, #40h 105 | ENDM 106 | Enable_CCF_Interrupt MACRO 107 | orl PCA0CPM0,#01h 108 | ENDM 109 | Disable_COVF_Interrupt MACRO 110 | anl PCA0PWM, #0BFh 111 | ENDM 112 | Disable_CCF_Interrupt MACRO 113 | anl PCA0CPM0,#0FEh 114 | ENDM 115 | 116 | 117 | 118 | ;********************* 119 | ; PORT 1 definitions * 120 | ;********************* 121 | ; EQU 7 ;i 122 | CcomFET EQU 6 ;o 123 | BcomFET EQU 5 ;o 124 | AcomFET EQU 4 ;o 125 | CpwmFET EQU 3 ;i 126 | BpwmFET EQU 2 ;o 127 | ApwmFET EQU 1 ;o 128 | ; EQU 0 ;o 129 | 130 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_INIT EQU 00h 132 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 133 | P1_SKIP EQU 7Fh 134 | 135 | ApwmFET_on MACRO 136 | setb P1.ApwmFET 137 | IF FETON_DELAY == 0 138 | setb P1.AcomFET 139 | ENDIF 140 | ENDM 141 | ApwmFET_off MACRO 142 | IF FETON_DELAY != 0 143 | clr P1.ApwmFET 144 | ELSE 145 | clr P1.AcomFET 146 | ENDIF 147 | ENDM 148 | BpwmFET_on MACRO 149 | setb P1.BpwmFET 150 | IF FETON_DELAY == 0 151 | setb P1.BcomFET 152 | ENDIF 153 | ENDM 154 | BpwmFET_off MACRO 155 | IF FETON_DELAY != 0 156 | clr P1.BpwmFET 157 | ELSE 158 | clr P1.BcomFET 159 | ENDIF 160 | ENDM 161 | CpwmFET_on MACRO 162 | setb P1.CpwmFET 163 | IF FETON_DELAY == 0 164 | setb P1.CcomFET 165 | ENDIF 166 | ENDM 167 | CpwmFET_off MACRO 168 | IF FETON_DELAY != 0 169 | clr P1.CpwmFET 170 | ELSE 171 | clr P1.CcomFET 172 | ENDIF 173 | ENDM 174 | All_pwmFETs_Off MACRO 175 | IF FETON_DELAY != 0 176 | clr P1.ApwmFET 177 | clr P1.BpwmFET 178 | clr P1.CpwmFET 179 | ELSE 180 | clr P1.AcomFET 181 | clr P1.BcomFET 182 | clr P1.CcomFET 183 | ENDIF 184 | ENDM 185 | 186 | AcomFET_on MACRO 187 | IF FETON_DELAY == 0 188 | clr P1.ApwmFET 189 | ENDIF 190 | setb P1.AcomFET 191 | ENDM 192 | AcomFET_off MACRO 193 | clr P1.AcomFET 194 | ENDM 195 | BcomFET_on MACRO 196 | IF FETON_DELAY == 0 197 | clr P1.BpwmFET 198 | ENDIF 199 | setb P1.BcomFET 200 | ENDM 201 | BcomFET_off MACRO 202 | clr P1.BcomFET 203 | ENDM 204 | CcomFET_on MACRO 205 | IF FETON_DELAY == 0 206 | clr P1.CpwmFET 207 | ENDIF 208 | setb P1.CcomFET 209 | ENDM 210 | CcomFET_off MACRO 211 | clr P1.CcomFET 212 | ENDM 213 | All_comFETs_Off MACRO 214 | clr P1.AcomFET 215 | clr P1.BcomFET 216 | clr P1.CcomFET 217 | ENDM 218 | 219 | Set_Pwm_A MACRO 220 | IF FETON_DELAY == 0 221 | setb P1.AcomFET 222 | mov P1SKIP, #7Dh 223 | ELSE 224 | mov P1SKIP, #6Dh 225 | ENDIF 226 | ENDM 227 | Set_Pwm_B MACRO 228 | IF FETON_DELAY == 0 229 | setb P1.BcomFET 230 | mov P1SKIP, #7Bh 231 | ELSE 232 | mov P1SKIP, #5Bh 233 | ENDIF 234 | ENDM 235 | Set_Pwm_C MACRO 236 | IF FETON_DELAY == 0 237 | setb P1.CcomFET 238 | mov P1SKIP, #77h 239 | ELSE 240 | mov P1SKIP, #37h 241 | ENDIF 242 | ENDM 243 | Set_Pwms_Off MACRO 244 | mov P1SKIP, #7Fh 245 | ENDM 246 | 247 | Set_Comp_Phase_A MACRO 248 | mov CMP0MX, #75h ; Set comparator multiplexer to phase A 249 | ENDM 250 | Set_Comp_Phase_B MACRO 251 | mov CMP0MX, #45h ; Set comparator multiplexer to phase B 252 | ENDM 253 | Set_Comp_Phase_C MACRO 254 | mov CMP0MX, #65h ; Set comparator multiplexer to phase C 255 | ENDM 256 | Read_Comp_Out MACRO 257 | mov A, CMP0CN0 ; Read comparator output 258 | ENDM 259 | 260 | 261 | ;********************* 262 | ; PORT 2 definitions * 263 | ;********************* 264 | DebugPin EQU 0 ;o 265 | 266 | P2_PUSHPULL EQU (1 SHL DebugPin) 267 | 268 | 269 | ;********************** 270 | ; MCU specific macros * 271 | ;********************** 272 | 273 | Initialize_Xbar MACRO 274 | mov XBR2, #40h ; Xbar enabled 275 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 276 | ENDM 277 | 278 | Initialize_Comparator MACRO 279 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 280 | mov CMP0MD, #00h ; Comparator response time 100ns 281 | ENDM 282 | Initialize_Adc MACRO 283 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 284 | IF MCU_48MHZ == 0 285 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 286 | ELSE 287 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 288 | ENDIF 289 | mov ADC0MX, #10h ; Select temp sensor input 290 | mov ADC0CN0, #80h ; ADC enabled 291 | mov ADC0CN1, #01h ; Common mode buffer enabled 292 | ENDM 293 | Start_Adc MACRO 294 | mov ADC0CN0, #90h ; ADC start 295 | ENDM 296 | Read_Adc_Result MACRO 297 | mov Temp1, ADC0L 298 | mov Temp2, ADC0H 299 | ENDM 300 | Stop_Adc MACRO 301 | ENDM 302 | Set_RPM_Out MACRO 303 | ENDM 304 | Clear_RPM_Out MACRO 305 | ENDM 306 | Set_LED_0 MACRO 307 | setb P0.LED_0 308 | ENDM 309 | Clear_LED_0 MACRO 310 | clr P0.LED_0 311 | ENDM 312 | Set_LED_1 MACRO 313 | ENDM 314 | Clear_LED_1 MACRO 315 | ENDM 316 | Set_LED_2 MACRO 317 | ENDM 318 | Clear_LED_2 MACRO 319 | ENDM 320 | Set_LED_3 MACRO 321 | ENDM 322 | Clear_LED_3 MACRO 323 | ENDM 324 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # set current revision 2 | MAJOR ?= 2 3 | MINOR ?= 3 4 | REVISION ?= $(MAJOR)_$(MINOR) 5 | 6 | # targets 7 | TARGETS = A B C D E F G H I J K L M N O P Q R S T U V W 8 | MCUS = H L 9 | FETON_DELAYS = 0 5 10 15 20 25 30 40 50 70 90 120 10 | PWMS_H = 24 48 96 11 | PWMS_L = 24 48 12 | 13 | # example single target 14 | VARIANT ?= F 15 | MCU ?= H 16 | FETON_DELAY ?= 0 17 | PWM ?= 24 18 | 19 | # configure the script to use the wine installation delivered with 20 | # SimplicityStudio. these wine settings are quite important. if you get 21 | # ERROR L250: CODE SIZE LIMIT IN RESTRICTED VERSION EXCEEDED 22 | # you messed up your simplicity studio install/path settins below: 23 | SIMPLICITY_PATH ?= /Applications/Simplicity\ Studio.app/Contents/Eclipse 24 | WINE_PREFIX ?= /Users/laux/Library/Application\ Support/SimplicityStudio/v4/studio-wine 25 | WINE_BIN ?= $(SIMPLICITY_PATH)/support/common/wine/opt/local/bin/wine 26 | WINE = export WINEPREFIX=`realpath $(WINE_PREFIX)`;$(WINE_BIN) 27 | 28 | # path to the keil binaries 29 | KEIL_PATH = $(SIMPLICITY_PATH)/developer/toolchains/keil_8051/9.53/BIN 30 | 31 | # some directory config 32 | OUTPUT_DIR ?= build 33 | OUTPUT_DIR_HEX ?= $(OUTPUT_DIR)/hex 34 | LOG_DIR ?= $(OUTPUT_DIR)/log 35 | 36 | # define the assembler/linker scripts 37 | AX51_BIN = $(KEIL_PATH)/AX51.exe 38 | LX51_BIN = $(KEIL_PATH)/LX51.exe 39 | OX51_BIN = $(KEIL_PATH)/Ohx51.exe 40 | AX51 = $(WINE) $(AX51_BIN) 41 | LX51 = $(WINE) $(LX51_BIN) 42 | OX51 = $(WINE) $(OX51_BIN) 43 | 44 | # set up flags 45 | AX51_FLAGS = ERRORPRINT DEBUG MACRO NOMOD51 COND SYMBOLS PAGEWIDTH(120) PAGELENGTH(65) GEN 46 | LX51_FLAGS = PAGEWIDTH (120) PAGELENGTH (65) 47 | 48 | # set up sources 49 | ASM_SRC = JEsc.asm 50 | ASM_INC = $(TARGETS:=.inc) JEscBootLoad.inc JEscPgm.inc SI_EFM8BB2_Defs.inc API.asm 51 | 52 | # check that wine/simplicity studio is available 53 | EXECUTABLES = $(WINE_BIN) $(AX51_BIN) $(LX51_BIN) $(OX51_BIN) 54 | #DUMMYVAR := $(foreach exec, $(EXECUTABLES), \ 55 | # $(if $(wildcard $(exec)),found, \ 56 | # $(error "Could not find $(exec). Make sure to set the correct paths to the simplicity install location"))) 57 | 58 | # make sure the list of obj files is expanded twice 59 | .SECONDEXPANSION: 60 | OBJS = 61 | 62 | , := , 63 | blank := 64 | space := $(blank) $(blank) 65 | $(space) := $(space) 66 | 67 | define MAKE_OBJ 68 | OBJS += $(OUTPUT_DIR)/JESC_$(1)$(2)$(3)_$(4)_$(REVISION).OBJ 69 | $(OUTPUT_DIR)/JESC_$(1)$(2)$(3)_$(4)_$(REVISION).OBJ : $(ASM_SRC) $(ASM_INC) 70 | $(eval _ESC := $(1)) 71 | $(eval _ESC_INT := $(shell printf "%d" "'${_ESC}")) 72 | $(eval _ESCNO := $(shell echo $$(( $(_ESC_INT) - 65 + 1)))) 73 | $(eval _MCU_48MHZ := $(subst L,0,$(subst H,1,$(2)))) 74 | $(eval _PWM := $(4)) 75 | $(eval _FETON_DELAY := $(3)) 76 | $(eval _LOG := $(LOG_DIR)/$(1)$(2)$(3)_$(4)_$(REVISION).log) 77 | @mkdir -p $(OUTPUT_DIR) 78 | @mkdir -p $(LOG_DIR) 79 | @echo "AX51 : $$<" 80 | $(AX51) $$< \ 81 | "DEFINE(ESCNO=$(_ESCNO)) " \ 82 | "DEFINE(MCU_48MHZ=$(_MCU_48MHZ)) "\ 83 | "DEFINE(NK1306=0) DEFINE(NO_DAMPING=0)"\ 84 | "DEFINE(PWM=$(_PWM)) "\ 85 | "DEFINE(FETON_DELAY=$(_FETON_DELAY)) "\ 86 | "DEFINE(MAJOR=$(MAJOR)) "\ 87 | "DEFINE(MINOR=$(MINOR)) "\ 88 | "OBJECT($$@) "\ 89 | "$(AX51_FLAGS)" >> $(_LOG) 2>&1; test $$$$? -lt 2 || cat $(_LOG) 90 | 91 | endef 92 | 93 | HEX_TARGETS = $(OBJS:.OBJ=.HEX) 94 | 95 | EFM8_LOAD_BIN ?= efm8load.py 96 | EFM8_LOAD_PORT ?= /dev/ttyUSB0 97 | EFM8_LOAD_BAUD ?= 57600 98 | 99 | SINGLE_TARGET_HEX = $(OUTPUT_DIR)/JESC_$(VARIANT)$(MCU)$(FETON_DELAY)_$(PWM)_$(REVISION).HEX 100 | 101 | single_target : $(SINGLE_TARGET_HEX) 102 | 103 | all : $$(HEX_TARGETS) 104 | @echo "\nbuild finished. built $(shell ls -l $(OUTPUT_DIR_HEX) | wc -l) hex targets\n" 105 | 106 | # create all obj targets using macro expansion 107 | $(foreach _e,$(TARGETS), \ 108 | $(foreach _m, $(MCUS), \ 109 | $(foreach _f, $(FETON_DELAYS), \ 110 | $(foreach _p, $(PWMS_$(_m)), \ 111 | $(eval $(call MAKE_OBJ,$(_e),$(_m),$(_f),$(_p))))))) 112 | 113 | 114 | $(OUTPUT_DIR)/%.OMF : $(OUTPUT_DIR)/%.OBJ 115 | $(eval LOG := $(LOG_DIR)/$(basename $(notdir $@)).log) 116 | @echo "LX51 : linking $(subst $( ),$(,) ,$^) to $@" 117 | @$(LX51) $(subst $( ),$(,) ,$^) TO "$@" "$(LX51_FLAGS)" >> $(LOG) 2>&1; test $$? -lt 2 || tail $(LOG) 118 | 119 | $(OUTPUT_DIR)/%.HEX : $(OUTPUT_DIR)/%.OMF 120 | $(eval LOG := $(LOG_DIR)/$(basename $(notdir $@)).log) 121 | @mkdir -p $(OUTPUT_DIR_HEX) 122 | @echo "OHX : generating hex file $@" 123 | @$(OX51) "$<" "HEXFILE ($@)" "H386" >> $(LOG) 2>&1; test $$? -lt 2 || tail $(LOG) 124 | @cp $@ $(OUTPUT_DIR_HEX)/$(notdir $@) 125 | 126 | help: 127 | @echo "" 128 | @echo "usage examples:" 129 | @echo "=================================================================" 130 | @echo "make all # build all targets" 131 | @echo "make VARIANT=A MCU=H FETON_DELAY=5 # to build a single target" 132 | @echo 133 | 134 | clean: 135 | @rm -rf $(LOG_DIR)/* 136 | @rm -rf $(OUTPUT_DIR)/* 137 | 138 | efm8load: single_target 139 | $(EFM8_LOAD_BIN) -p $(EFM8_LOAD_PORT) -b $(EFM8_LOAD_BAUD) -w $(SINGLE_TARGET_HEX) 140 | 141 | 142 | .PHONY: all clean help efm8load 143 | 144 | -------------------------------------------------------------------------------- /N.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "N" 26 | ; X X RC X MC MB MA CC X X Cp Cc Bp Bc Ap Ac 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | 63 | ;********************* 64 | ; PORT 0 definitions * 65 | ;********************* 66 | ; EQU 7 ;i 67 | ; EQU 6 ;i 68 | Rcp_In EQU 5 ;i 69 | ; EQU 4 ;i 70 | Mux_C EQU 3 ;i 71 | Mux_B EQU 2 ;i 72 | Mux_A EQU 1 ;i 73 | Comp_Com EQU 0 ;i 74 | 75 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 76 | P0_INIT EQU 0FFh 77 | P0_PUSHPULL EQU 0 78 | P0_SKIP EQU 0FFh 79 | 80 | Set_Pwm_Polarity MACRO 81 | IF FETON_DELAY == 0 82 | mov PCA0POL, #00h ; Pwm noninverted 83 | ELSE 84 | mov PCA0POL, #01h ; Damping inverted, pwm noninverted 85 | ENDIF 86 | ENDM 87 | Enable_Power_Pwm_Module MACRO 88 | IF FETON_DELAY == 0 89 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 90 | ELSE 91 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 92 | ENDIF 93 | ENDM 94 | Enable_Damp_Pwm_Module MACRO 95 | IF FETON_DELAY == 0 96 | mov PCA0CPM1, #00h ; Disable 97 | ELSE 98 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 99 | ENDIF 100 | ENDM 101 | Clear_COVF_Interrupt MACRO 102 | anl PCA0PWM, #0DFh 103 | ENDM 104 | Clear_CCF_Interrupt MACRO ; CCF interrupt is only used for FETON_DELAY == 0 105 | anl PCA0CN0, #0FEh 106 | ENDM 107 | Enable_COVF_Interrupt MACRO 108 | orl PCA0PWM, #40h 109 | ENDM 110 | Enable_CCF_Interrupt MACRO 111 | orl PCA0CPM0,#01h 112 | ENDM 113 | Disable_COVF_Interrupt MACRO 114 | anl PCA0PWM, #0BFh 115 | ENDM 116 | Disable_CCF_Interrupt MACRO 117 | anl PCA0CPM0,#0FEh 118 | ENDM 119 | 120 | 121 | ;********************* 122 | ; PORT 1 definitions * 123 | ;********************* 124 | ; EQU 7 ;i 125 | ; EQU 6 ;i 126 | CpwmFET EQU 5 ;o 127 | CcomFET EQU 4 ;o 128 | BpwmFET EQU 3 ;o 129 | BcomFET EQU 2 ;o 130 | ApwmFET EQU 1 ;o 131 | AcomFET EQU 0 ;o 132 | 133 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 134 | P1_INIT EQU 00h 135 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 136 | P1_SKIP EQU 3Fh 137 | 138 | ApwmFET_on MACRO 139 | setb P1.ApwmFET 140 | IF FETON_DELAY == 0 141 | setb P1.AcomFET 142 | ENDIF 143 | ENDM 144 | ApwmFET_off MACRO 145 | IF FETON_DELAY != 0 146 | clr P1.ApwmFET 147 | ELSE 148 | clr P1.AcomFET 149 | ENDIF 150 | ENDM 151 | BpwmFET_on MACRO 152 | setb P1.BpwmFET 153 | IF FETON_DELAY == 0 154 | setb P1.BcomFET 155 | ENDIF 156 | ENDM 157 | BpwmFET_off MACRO 158 | IF FETON_DELAY != 0 159 | clr P1.BpwmFET 160 | ELSE 161 | clr P1.BcomFET 162 | ENDIF 163 | ENDM 164 | CpwmFET_on MACRO 165 | setb P1.CpwmFET 166 | IF FETON_DELAY == 0 167 | setb P1.CcomFET 168 | ENDIF 169 | ENDM 170 | CpwmFET_off MACRO 171 | IF FETON_DELAY != 0 172 | clr P1.CpwmFET 173 | ELSE 174 | clr P1.CcomFET 175 | ENDIF 176 | ENDM 177 | All_pwmFETs_Off MACRO 178 | IF FETON_DELAY != 0 179 | clr P1.ApwmFET 180 | clr P1.BpwmFET 181 | clr P1.CpwmFET 182 | ELSE 183 | clr P1.AcomFET 184 | clr P1.BcomFET 185 | clr P1.CcomFET 186 | ENDIF 187 | ENDM 188 | 189 | AcomFET_on MACRO 190 | IF FETON_DELAY == 0 191 | clr P1.ApwmFET 192 | ENDIF 193 | setb P1.AcomFET 194 | ENDM 195 | AcomFET_off MACRO 196 | clr P1.AcomFET 197 | ENDM 198 | BcomFET_on MACRO 199 | IF FETON_DELAY == 0 200 | clr P1.BpwmFET 201 | ENDIF 202 | setb P1.BcomFET 203 | ENDM 204 | BcomFET_off MACRO 205 | clr P1.BcomFET 206 | ENDM 207 | CcomFET_on MACRO 208 | IF FETON_DELAY == 0 209 | clr P1.CpwmFET 210 | ENDIF 211 | setb P1.CcomFET 212 | ENDM 213 | CcomFET_off MACRO 214 | clr P1.CcomFET 215 | ENDM 216 | All_comFETs_Off MACRO 217 | clr P1.AcomFET 218 | clr P1.BcomFET 219 | clr P1.CcomFET 220 | ENDM 221 | 222 | Set_Pwm_A MACRO 223 | IF FETON_DELAY == 0 224 | setb P1.AcomFET 225 | mov P1SKIP, #3Dh 226 | ELSE 227 | mov P1SKIP, #3Ch 228 | ENDIF 229 | ENDM 230 | Set_Pwm_B MACRO 231 | IF FETON_DELAY == 0 232 | setb P1.BcomFET 233 | mov P1SKIP, #37h 234 | ELSE 235 | mov P1SKIP, #33h 236 | ENDIF 237 | ENDM 238 | Set_Pwm_C MACRO 239 | IF FETON_DELAY == 0 240 | setb P1.CcomFET 241 | mov P1SKIP, #1Fh 242 | ELSE 243 | mov P1SKIP, #0Fh 244 | ENDIF 245 | ENDM 246 | Set_Pwms_Off MACRO 247 | mov P1SKIP, #3Fh 248 | ENDM 249 | 250 | Set_Comp_Phase_A MACRO 251 | mov CMP0MX, #10h ; Set comparator multiplexer to phase A 252 | ENDM 253 | Set_Comp_Phase_B MACRO 254 | mov CMP0MX, #20h ; Set comparator multiplexer to phase B 255 | ENDM 256 | Set_Comp_Phase_C MACRO 257 | mov CMP0MX, #30h ; Set comparator multiplexer to phase C 258 | ENDM 259 | Read_Comp_Out MACRO 260 | mov A, CMP0CN0 ; Read comparator output 261 | ENDM 262 | 263 | 264 | ;********************* 265 | ; PORT 2 definitions * 266 | ;********************* 267 | DebugPin EQU 0 ;o 268 | 269 | P2_PUSHPULL EQU (1 SHL DebugPin) 270 | 271 | 272 | ;********************** 273 | ; MCU specific macros * 274 | ;********************** 275 | 276 | Initialize_Xbar MACRO 277 | mov XBR2, #40h ; Xbar enabled 278 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 279 | ENDM 280 | 281 | Initialize_Comparator MACRO 282 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 283 | mov CMP0MD, #00h ; Comparator response time 100ns 284 | ENDM 285 | Initialize_Adc MACRO 286 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 287 | IF MCU_48MHZ == 0 288 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 289 | ELSE 290 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 291 | ENDIF 292 | mov ADC0MX, #10h ; Select temp sensor input 293 | mov ADC0CN0, #80h ; ADC enabled 294 | mov ADC0CN1, #01h ; Common mode buffer enabled 295 | ENDM 296 | Start_Adc MACRO 297 | mov ADC0CN0, #90h ; ADC start 298 | ENDM 299 | Read_Adc_Result MACRO 300 | mov Temp1, ADC0L 301 | mov Temp2, ADC0H 302 | ENDM 303 | Stop_Adc MACRO 304 | ENDM 305 | Set_RPM_Out MACRO 306 | ENDM 307 | Clear_RPM_Out MACRO 308 | ENDM 309 | Set_LED_0 MACRO 310 | ENDM 311 | Clear_LED_0 MACRO 312 | ENDM 313 | Set_LED_1 MACRO 314 | ENDM 315 | Clear_LED_1 MACRO 316 | ENDM 317 | Set_LED_2 MACRO 318 | ENDM 319 | Clear_LED_2 MACRO 320 | ENDM 321 | Set_LED_3 MACRO 322 | ENDM 323 | Clear_LED_3 MACRO 324 | ENDM 325 | -------------------------------------------------------------------------------- /O.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "O". Com fets are active low for H/L_N driver and EN_N/PWM driver. Low side pwm and 1S flag set 26 | ; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | ; EQU 7 ;i 66 | ; EQU 6 ;i 67 | Rcp_In EQU 5 ;i 68 | ; EQU 4 ;i 69 | Comp_Com EQU 3 ;i 70 | Mux_A EQU 2 ;i 71 | Mux_C EQU 1 ;i 72 | Mux_B EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU 0FFh 76 | P0_PUSHPULL EQU 0 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #00h ; Damping noninverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | 116 | ;********************* 117 | ; PORT 1 definitions * 118 | ;********************* 119 | ; EQU 7 ;i 120 | ; EQU 6 ;i 121 | CcomFET EQU 5 ;o 122 | CpwmFET EQU 4 ;o 123 | BcomFET EQU 3 ;o 124 | BpwmFET EQU 2 ;o 125 | AcomFET EQU 1 ;o 126 | ApwmFET EQU 0 ;o 127 | 128 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 129 | P1_INIT EQU (1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 130 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_SKIP EQU 3Fh 132 | 133 | ApwmFET_on MACRO 134 | setb P1.ApwmFET 135 | IF FETON_DELAY == 0 136 | clr P1.AcomFET 137 | ENDIF 138 | ENDM 139 | ApwmFET_off MACRO 140 | IF FETON_DELAY != 0 141 | clr P1.ApwmFET 142 | ELSE 143 | setb P1.AcomFET 144 | ENDIF 145 | ENDM 146 | BpwmFET_on MACRO 147 | setb P1.BpwmFET 148 | IF FETON_DELAY == 0 149 | clr P1.BcomFET 150 | ENDIF 151 | ENDM 152 | BpwmFET_off MACRO 153 | IF FETON_DELAY != 0 154 | clr P1.BpwmFET 155 | ELSE 156 | setb P1.BcomFET 157 | ENDIF 158 | ENDM 159 | CpwmFET_on MACRO 160 | setb P1.CpwmFET 161 | IF FETON_DELAY == 0 162 | clr P1.CcomFET 163 | ENDIF 164 | ENDM 165 | CpwmFET_off MACRO 166 | IF FETON_DELAY != 0 167 | clr P1.CpwmFET 168 | ELSE 169 | setb P1.CcomFET 170 | ENDIF 171 | ENDM 172 | All_pwmFETs_Off MACRO 173 | IF FETON_DELAY != 0 174 | clr P1.ApwmFET 175 | clr P1.BpwmFET 176 | clr P1.CpwmFET 177 | ELSE 178 | setb P1.AcomFET 179 | setb P1.BcomFET 180 | setb P1.CcomFET 181 | ENDIF 182 | ENDM 183 | 184 | AcomFET_on MACRO 185 | IF FETON_DELAY == 0 186 | clr P1.ApwmFET 187 | ENDIF 188 | clr P1.AcomFET 189 | ENDM 190 | AcomFET_off MACRO 191 | setb P1.AcomFET 192 | ENDM 193 | BcomFET_on MACRO 194 | IF FETON_DELAY == 0 195 | clr P1.BpwmFET 196 | ENDIF 197 | clr P1.BcomFET 198 | ENDM 199 | BcomFET_off MACRO 200 | setb P1.BcomFET 201 | ENDM 202 | CcomFET_on MACRO 203 | IF FETON_DELAY == 0 204 | clr P1.CpwmFET 205 | ENDIF 206 | clr P1.CcomFET 207 | ENDM 208 | CcomFET_off MACRO 209 | setb P1.CcomFET 210 | ENDM 211 | All_comFETs_Off MACRO 212 | setb P1.AcomFET 213 | setb P1.BcomFET 214 | setb P1.CcomFET 215 | ENDM 216 | 217 | Set_Pwm_A MACRO 218 | IF FETON_DELAY == 0 219 | clr P1.AcomFET 220 | mov P1SKIP, #3Eh 221 | ELSE 222 | mov P1SKIP, #3Ch 223 | ENDIF 224 | ENDM 225 | Set_Pwm_B MACRO 226 | IF FETON_DELAY == 0 227 | clr P1.BcomFET 228 | mov P1SKIP, #3Bh 229 | ELSE 230 | mov P1SKIP, #33h 231 | ENDIF 232 | ENDM 233 | Set_Pwm_C MACRO 234 | IF FETON_DELAY == 0 235 | clr P1.CcomFET 236 | mov P1SKIP, #2Fh 237 | ELSE 238 | mov P1SKIP, #0Fh 239 | ENDIF 240 | ENDM 241 | Set_Pwms_Off MACRO 242 | mov P1SKIP, #3Fh 243 | ENDM 244 | 245 | Set_Comp_Phase_A MACRO 246 | mov CMP0MX, #23h ; Set comparator multiplexer to phase A 247 | ENDM 248 | Set_Comp_Phase_B MACRO 249 | mov CMP0MX, #03h ; Set comparator multiplexer to phase B 250 | ENDM 251 | Set_Comp_Phase_C MACRO 252 | mov CMP0MX, #13h ; Set comparator multiplexer to phase C 253 | ENDM 254 | Read_Comp_Out MACRO 255 | mov A, CMP0CN0 ; Read comparator output 256 | cpl A 257 | ENDM 258 | 259 | 260 | ;********************* 261 | ; PORT 2 definitions * 262 | ;********************* 263 | DebugPin EQU 0 ;o 264 | 265 | P2_PUSHPULL EQU (1 SHL DebugPin) 266 | 267 | 268 | ;********************** 269 | ; MCU specific macros * 270 | ;********************** 271 | 272 | Initialize_Xbar MACRO 273 | mov XBR2, #40h ; Xbar enabled 274 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 275 | ENDM 276 | 277 | Initialize_Comparator MACRO 278 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 279 | mov CMP0MD, #00h ; Comparator response time 100ns 280 | ENDM 281 | Initialize_Adc MACRO 282 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 283 | IF MCU_48MHZ == 0 284 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 285 | ELSE 286 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 287 | ENDIF 288 | mov ADC0MX, #10h ; Select temp sensor input 289 | mov ADC0CN0, #80h ; ADC enabled 290 | mov ADC0CN1, #01h ; Common mode buffer enabled 291 | ENDM 292 | Start_Adc MACRO 293 | mov ADC0CN0, #90h ; ADC start 294 | ENDM 295 | Read_Adc_Result MACRO 296 | mov Temp1, ADC0L 297 | mov Temp2, ADC0H 298 | ENDM 299 | Stop_Adc MACRO 300 | ENDM 301 | Set_RPM_Out MACRO 302 | ENDM 303 | Clear_RPM_Out MACRO 304 | ENDM 305 | Set_LED_0 MACRO 306 | ENDM 307 | Clear_LED_0 MACRO 308 | ENDM 309 | Set_LED_1 MACRO 310 | ENDM 311 | Clear_LED_1 MACRO 312 | ENDM 313 | Set_LED_2 MACRO 314 | ENDM 315 | Clear_LED_2 MACRO 316 | ENDM 317 | Set_LED_3 MACRO 318 | ENDM 319 | Clear_LED_3 MACRO 320 | ENDM 321 | -------------------------------------------------------------------------------- /P.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "P". 26 | ; X X RC MA CC MB MC X X Cc Bc Ac Cp Bp Ap X 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | 63 | ;********************* 64 | ; PORT 0 definitions * 65 | ;********************* 66 | ; EQU 7 ;i 67 | ; EQU 6 ;i 68 | Rcp_In EQU 5 ;i 69 | Mux_A EQU 4 ;i 70 | Comp_Com EQU 3 ;i 71 | Mux_B EQU 2 ;i 72 | Mux_C EQU 1 ;i 73 | ; EQU 0 ;i 74 | 75 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 76 | P0_INIT EQU 0FFh 77 | P0_PUSHPULL EQU 0 78 | P0_SKIP EQU 0FFh 79 | 80 | Set_Pwm_Polarity MACRO 81 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 82 | ENDM 83 | Enable_Power_Pwm_Module MACRO 84 | IF FETON_DELAY == 0 85 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 86 | ELSE 87 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 88 | ENDIF 89 | ENDM 90 | Enable_Damp_Pwm_Module MACRO 91 | IF FETON_DELAY == 0 92 | mov PCA0CPM1, #00h ; Disable 93 | ELSE 94 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 95 | ENDIF 96 | ENDM 97 | Clear_COVF_Interrupt MACRO 98 | anl PCA0PWM, #0DFh 99 | ENDM 100 | Clear_CCF_Interrupt MACRO 101 | anl PCA0CN0, #0FEh 102 | ENDM 103 | Enable_COVF_Interrupt MACRO 104 | orl PCA0PWM, #40h 105 | ENDM 106 | Enable_CCF_Interrupt MACRO 107 | orl PCA0CPM0,#01h 108 | ENDM 109 | Disable_COVF_Interrupt MACRO 110 | anl PCA0PWM, #0BFh 111 | ENDM 112 | Disable_CCF_Interrupt MACRO 113 | anl PCA0CPM0,#0FEh 114 | ENDM 115 | 116 | 117 | 118 | ;********************* 119 | ; PORT 1 definitions * 120 | ;********************* 121 | ; EQU 7 ;i 122 | CcomFET EQU 6 ;o 123 | BcomFET EQU 5 ;o 124 | AcomFET EQU 4 ;o 125 | CpwmFET EQU 3 ;i 126 | BpwmFET EQU 2 ;o 127 | ApwmFET EQU 1 ;o 128 | ; EQU 0 ;o 129 | 130 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_INIT EQU 00h 132 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 133 | P1_SKIP EQU 7Fh 134 | 135 | ApwmFET_on MACRO 136 | setb P1.ApwmFET 137 | IF FETON_DELAY == 0 138 | setb P1.AcomFET 139 | ENDIF 140 | ENDM 141 | ApwmFET_off MACRO 142 | IF FETON_DELAY != 0 143 | clr P1.ApwmFET 144 | ELSE 145 | clr P1.AcomFET 146 | ENDIF 147 | ENDM 148 | BpwmFET_on MACRO 149 | setb P1.BpwmFET 150 | IF FETON_DELAY == 0 151 | setb P1.BcomFET 152 | ENDIF 153 | ENDM 154 | BpwmFET_off MACRO 155 | IF FETON_DELAY != 0 156 | clr P1.BpwmFET 157 | ELSE 158 | clr P1.BcomFET 159 | ENDIF 160 | ENDM 161 | CpwmFET_on MACRO 162 | setb P1.CpwmFET 163 | IF FETON_DELAY == 0 164 | setb P1.CcomFET 165 | ENDIF 166 | ENDM 167 | CpwmFET_off MACRO 168 | IF FETON_DELAY != 0 169 | clr P1.CpwmFET 170 | ELSE 171 | clr P1.CcomFET 172 | ENDIF 173 | ENDM 174 | All_pwmFETs_Off MACRO 175 | IF FETON_DELAY != 0 176 | clr P1.ApwmFET 177 | clr P1.BpwmFET 178 | clr P1.CpwmFET 179 | ELSE 180 | clr P1.AcomFET 181 | clr P1.BcomFET 182 | clr P1.CcomFET 183 | ENDIF 184 | ENDM 185 | 186 | AcomFET_on MACRO 187 | IF FETON_DELAY == 0 188 | clr P1.ApwmFET 189 | ENDIF 190 | setb P1.AcomFET 191 | ENDM 192 | AcomFET_off MACRO 193 | clr P1.AcomFET 194 | ENDM 195 | BcomFET_on MACRO 196 | IF FETON_DELAY == 0 197 | clr P1.BpwmFET 198 | ENDIF 199 | setb P1.BcomFET 200 | ENDM 201 | BcomFET_off MACRO 202 | clr P1.BcomFET 203 | ENDM 204 | CcomFET_on MACRO 205 | IF FETON_DELAY == 0 206 | clr P1.CpwmFET 207 | ENDIF 208 | setb P1.CcomFET 209 | ENDM 210 | CcomFET_off MACRO 211 | clr P1.CcomFET 212 | ENDM 213 | All_comFETs_Off MACRO 214 | clr P1.AcomFET 215 | clr P1.BcomFET 216 | clr P1.CcomFET 217 | ENDM 218 | 219 | Set_Pwm_A MACRO 220 | IF FETON_DELAY == 0 221 | setb P1.AcomFET 222 | mov P1SKIP, #7Dh 223 | ELSE 224 | mov P1SKIP, #6Dh 225 | ENDIF 226 | ENDM 227 | Set_Pwm_B MACRO 228 | IF FETON_DELAY == 0 229 | setb P1.BcomFET 230 | mov P1SKIP, #7Bh 231 | ELSE 232 | mov P1SKIP, #5Bh 233 | ENDIF 234 | ENDM 235 | Set_Pwm_C MACRO 236 | IF FETON_DELAY == 0 237 | setb P1.CcomFET 238 | mov P1SKIP, #77h 239 | ELSE 240 | mov P1SKIP, #37h 241 | ENDIF 242 | ENDM 243 | Set_Pwms_Off MACRO 244 | mov P1SKIP, #7Fh 245 | ENDM 246 | 247 | Set_Comp_Phase_A MACRO 248 | mov CMP0MX, #43h ; Set comparator multiplexer to phase A 249 | ENDM 250 | Set_Comp_Phase_B MACRO 251 | mov CMP0MX, #23h ; Set comparator multiplexer to phase B 252 | ENDM 253 | Set_Comp_Phase_C MACRO 254 | mov CMP0MX, #13h ; Set comparator multiplexer to phase C 255 | ENDM 256 | Read_Comp_Out MACRO 257 | mov A, CMP0CN0 ; Read comparator output 258 | ENDM 259 | 260 | 261 | ;********************* 262 | ; PORT 2 definitions * 263 | ;********************* 264 | DebugPin EQU 0 ;o 265 | 266 | P2_PUSHPULL EQU (1 SHL DebugPin) 267 | 268 | 269 | ;********************** 270 | ; MCU specific macros * 271 | ;********************** 272 | 273 | 274 | Initialize_Xbar MACRO 275 | mov XBR2, #40h ; Xbar enabled 276 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 277 | ENDM 278 | 279 | Initialize_Comparator MACRO 280 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 281 | mov CMP0MD, #00h ; Comparator response time 100ns 282 | ENDM 283 | Initialize_Adc MACRO 284 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 285 | IF MCU_48MHZ == 0 286 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 287 | ELSE 288 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 289 | ENDIF 290 | mov ADC0MX, #10h ; Select temp sensor input 291 | mov ADC0CN0, #80h ; ADC enabled 292 | mov ADC0CN1, #01h ; Common mode buffer enabled 293 | ENDM 294 | Start_Adc MACRO 295 | mov ADC0CN0, #90h ; ADC start 296 | ENDM 297 | Read_Adc_Result MACRO 298 | mov Temp1, ADC0L 299 | mov Temp2, ADC0H 300 | ENDM 301 | Stop_Adc MACRO 302 | ENDM 303 | Set_RPM_Out MACRO 304 | ENDM 305 | Clear_RPM_Out MACRO 306 | ENDM 307 | Set_LED_0 MACRO 308 | ENDM 309 | Clear_LED_0 MACRO 310 | ENDM 311 | Set_LED_1 MACRO 312 | ENDM 313 | Clear_LED_1 MACRO 314 | ENDM 315 | Set_LED_2 MACRO 316 | ENDM 317 | Clear_LED_2 MACRO 318 | ENDM 319 | Set_LED_3 MACRO 320 | ENDM 321 | Clear_LED_3 MACRO 322 | ENDM 323 | -------------------------------------------------------------------------------- /Q.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "Q" 26 | ; Cp Bp Ap L1 L0 X RC X X MA MB MC CC Cc Bc Ac 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 1 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | CpwmFET EQU 7 ;o 66 | BpwmFET EQU 6 ;o 67 | ApwmFET EQU 5 ;o 68 | LED_1 EQU 4 ;i 69 | LED_0 EQU 3 ;i 70 | ; EQU 2 ;i 71 | Rcp_In EQU 1 ;i 72 | ; EQU 0 ;i 73 | 74 | P0_DIGITAL EQU 0FFh 75 | P0_INIT EQU (1 SHL Rcp_In) 76 | P0_PUSHPULL EQU (1 SHL LED_0)+(1 SHL LED_1)+(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET) 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | 116 | ;********************* 117 | ; PORT 1 definitions * 118 | ;********************* 119 | ; EQU 7 ;i 120 | Mux_A EQU 6 ;i 121 | Mux_B EQU 5 ;i 122 | Mux_C EQU 4 ;i 123 | Comp_Com EQU 3 ;o 124 | CcomFET EQU 2 ;o 125 | BcomFET EQU 1 ;o 126 | AcomFET EQU 0 ;o 127 | 128 | P1_DIGITAL EQU (1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 129 | P1_INIT EQU 00h 130 | P1_PUSHPULL EQU (1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_SKIP EQU 07h 132 | 133 | ApwmFET_on MACRO 134 | setb P0.ApwmFET 135 | IF FETON_DELAY == 0 136 | setb P1.AcomFET 137 | ENDIF 138 | ENDM 139 | ApwmFET_off MACRO 140 | IF FETON_DELAY != 0 141 | clr P0.ApwmFET 142 | ELSE 143 | clr P1.AcomFET 144 | ENDIF 145 | ENDM 146 | BpwmFET_on MACRO 147 | setb P0.BpwmFET 148 | IF FETON_DELAY == 0 149 | setb P1.BcomFET 150 | ENDIF 151 | ENDM 152 | BpwmFET_off MACRO 153 | IF FETON_DELAY != 0 154 | clr P0.BpwmFET 155 | ELSE 156 | clr P1.BcomFET 157 | ENDIF 158 | ENDM 159 | CpwmFET_on MACRO 160 | setb P0.CpwmFET 161 | IF FETON_DELAY == 0 162 | setb P1.CcomFET 163 | ENDIF 164 | ENDM 165 | CpwmFET_off MACRO 166 | IF FETON_DELAY != 0 167 | clr P0.CpwmFET 168 | ELSE 169 | clr P1.CcomFET 170 | ENDIF 171 | ENDM 172 | All_pwmFETs_Off MACRO 173 | IF FETON_DELAY != 0 174 | clr P0.ApwmFET 175 | clr P0.BpwmFET 176 | clr P0.CpwmFET 177 | ELSE 178 | clr P1.AcomFET 179 | clr P1.BcomFET 180 | clr P1.CcomFET 181 | ENDIF 182 | ENDM 183 | 184 | AcomFET_on MACRO 185 | IF FETON_DELAY == 0 186 | clr P0.ApwmFET 187 | ENDIF 188 | setb P1.AcomFET 189 | ENDM 190 | AcomFET_off MACRO 191 | clr P1.AcomFET 192 | ENDM 193 | BcomFET_on MACRO 194 | IF FETON_DELAY == 0 195 | clr P0.BpwmFET 196 | ENDIF 197 | setb P1.BcomFET 198 | ENDM 199 | BcomFET_off MACRO 200 | clr P1.BcomFET 201 | ENDM 202 | CcomFET_on MACRO 203 | IF FETON_DELAY == 0 204 | clr P0.CpwmFET 205 | ENDIF 206 | setb P1.CcomFET 207 | ENDM 208 | CcomFET_off MACRO 209 | clr P1.CcomFET 210 | ENDM 211 | All_comFETs_Off MACRO 212 | clr P1.AcomFET 213 | clr P1.BcomFET 214 | clr P1.CcomFET 215 | ENDM 216 | 217 | Set_Pwm_A MACRO 218 | IF FETON_DELAY == 0 219 | setb P1.AcomFET 220 | mov P0SKIP, #0DFh 221 | mov P1SKIP, #07h 222 | ELSE 223 | mov P0SKIP, #0DFh 224 | mov P1SKIP, #06h 225 | ENDIF 226 | ENDM 227 | Set_Pwm_B MACRO 228 | IF FETON_DELAY == 0 229 | setb P1.BcomFET 230 | mov P0SKIP, #0BFh 231 | mov P1SKIP, #07h 232 | ELSE 233 | mov P0SKIP, #0BFh 234 | mov P1SKIP, #05h 235 | ENDIF 236 | ENDM 237 | Set_Pwm_C MACRO 238 | IF FETON_DELAY == 0 239 | setb P1.CcomFET 240 | mov P0SKIP, #07Fh 241 | mov P1SKIP, #07h 242 | ELSE 243 | mov P0SKIP, #07Fh 244 | mov P1SKIP, #03h 245 | ENDIF 246 | ENDM 247 | Set_Pwms_Off MACRO 248 | mov P0SKIP, #0FFh 249 | mov P1SKIP, #07h 250 | ENDM 251 | 252 | Set_Comp_Phase_A MACRO 253 | mov CMP1MX, #63h ; Set comparator multiplexer to phase A 254 | ENDM 255 | Set_Comp_Phase_B MACRO 256 | mov CMP1MX, #53h ; Set comparator multiplexer to phase B 257 | ENDM 258 | Set_Comp_Phase_C MACRO 259 | mov CMP1MX, #43h ; Set comparator multiplexer to phase C 260 | ENDM 261 | Read_Comp_Out MACRO 262 | mov A, CMP1CN0 ; Read comparator output 263 | ENDM 264 | 265 | 266 | ;********************* 267 | ; PORT 2 definitions * 268 | ;********************* 269 | DebugPin EQU 0 ;o 270 | 271 | P2_PUSHPULL EQU (1 SHL DebugPin) 272 | 273 | 274 | ;********************** 275 | ; MCU specific macros * 276 | ;********************** 277 | 278 | Initialize_Xbar MACRO 279 | mov XBR2, #40h ; Xbar enabled 280 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 281 | ENDM 282 | 283 | Initialize_Comparator MACRO 284 | mov CMP1CN0, #80h ; Comparator enabled, no hysteresis 285 | mov CMP1MD, #00h ; Comparator response time 100ns 286 | ENDM 287 | Initialize_Adc MACRO 288 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 289 | IF MCU_48MHZ == 0 290 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 291 | ELSE 292 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 293 | ENDIF 294 | mov ADC0MX, #10h ; Select temp sensor input 295 | mov ADC0CN0, #80h ; ADC enabled 296 | mov ADC0CN1, #01h ; Common mode buffer enabled 297 | ENDM 298 | Start_Adc MACRO 299 | mov ADC0CN0, #90h ; ADC start 300 | ENDM 301 | Read_Adc_Result MACRO 302 | mov Temp1, ADC0L 303 | mov Temp2, ADC0H 304 | ENDM 305 | Stop_Adc MACRO 306 | ENDM 307 | Set_RPM_Out MACRO 308 | ENDM 309 | Clear_RPM_Out MACRO 310 | ENDM 311 | Set_LED_0 MACRO 312 | setb P0.LED_0 313 | ENDM 314 | Clear_LED_0 MACRO 315 | clr P0.LED_0 316 | ENDM 317 | Set_LED_1 MACRO 318 | setb P0.LED_1 319 | ENDM 320 | Clear_LED_1 MACRO 321 | clr P0.LED_1 322 | ENDM 323 | Set_LED_2 MACRO 324 | ENDM 325 | Clear_LED_2 MACRO 326 | ENDM 327 | Set_LED_3 MACRO 328 | ENDM 329 | Clear_LED_3 MACRO 330 | ENDM 331 | -------------------------------------------------------------------------------- /R.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "R". 26 | ; X X RC X MC MB MA CC X X Ac Bc Cc Ap Bp Cp 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | ; EQU 7 ;i 66 | ; EQU 6 ;i 67 | Rcp_In EQU 5 ;i 68 | ; EQU 4 ;i 69 | Mux_C EQU 3 ;i 70 | Mux_B EQU 2 ;i 71 | Mux_A EQU 1 ;i 72 | Comp_Com EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU 0FFh 76 | P0_PUSHPULL EQU 0 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 81 | ENDM 82 | Enable_Power_Pwm_Module MACRO 83 | IF FETON_DELAY == 0 84 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 85 | ELSE 86 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 87 | ENDIF 88 | ENDM 89 | Enable_Damp_Pwm_Module MACRO 90 | IF FETON_DELAY == 0 91 | mov PCA0CPM1, #00h ; Disable 92 | ELSE 93 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 94 | ENDIF 95 | ENDM 96 | Clear_COVF_Interrupt MACRO 97 | anl PCA0PWM, #0DFh 98 | ENDM 99 | Clear_CCF_Interrupt MACRO ; CCF interrupt is only used for FETON_DELAY == 0 100 | anl PCA0CN0, #0FEh 101 | ENDM 102 | Enable_COVF_Interrupt MACRO 103 | orl PCA0PWM, #40h 104 | ENDM 105 | Enable_CCF_Interrupt MACRO 106 | orl PCA0CPM0,#01h 107 | ENDM 108 | Disable_COVF_Interrupt MACRO 109 | anl PCA0PWM, #0BFh 110 | ENDM 111 | Disable_CCF_Interrupt MACRO 112 | anl PCA0CPM0,#0FEh 113 | ENDM 114 | 115 | ;********************* 116 | ; PORT 1 definitions * 117 | ;********************* 118 | ; EQU 7 ;i 119 | ; EQU 6 ;i 120 | AcomFET EQU 5 ;o 121 | BcomFET EQU 4 ;o 122 | CcomFET EQU 3 ;o 123 | ApwmFET EQU 2 ;o 124 | BpwmFET EQU 1 ;o 125 | CpwmFET EQU 0 ;o 126 | 127 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 128 | P1_INIT EQU 00h 129 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 130 | P1_SKIP EQU 3Fh 131 | 132 | ApwmFET_on MACRO 133 | setb P1.ApwmFET 134 | IF FETON_DELAY == 0 135 | setb P1.AcomFET 136 | ENDIF 137 | ENDM 138 | ApwmFET_off MACRO 139 | IF FETON_DELAY != 0 140 | clr P1.ApwmFET 141 | ELSE 142 | clr P1.AcomFET 143 | ENDIF 144 | ENDM 145 | BpwmFET_on MACRO 146 | setb P1.BpwmFET 147 | IF FETON_DELAY == 0 148 | setb P1.BcomFET 149 | ENDIF 150 | ENDM 151 | BpwmFET_off MACRO 152 | IF FETON_DELAY != 0 153 | clr P1.BpwmFET 154 | ELSE 155 | clr P1.BcomFET 156 | ENDIF 157 | ENDM 158 | CpwmFET_on MACRO 159 | setb P1.CpwmFET 160 | IF FETON_DELAY == 0 161 | setb P1.CcomFET 162 | ENDIF 163 | ENDM 164 | CpwmFET_off MACRO 165 | IF FETON_DELAY != 0 166 | clr P1.CpwmFET 167 | ELSE 168 | clr P1.CcomFET 169 | ENDIF 170 | ENDM 171 | All_pwmFETs_Off MACRO 172 | IF FETON_DELAY != 0 173 | clr P1.ApwmFET 174 | clr P1.BpwmFET 175 | clr P1.CpwmFET 176 | ELSE 177 | clr P1.AcomFET 178 | clr P1.BcomFET 179 | clr P1.CcomFET 180 | ENDIF 181 | ENDM 182 | 183 | AcomFET_on MACRO 184 | IF FETON_DELAY == 0 185 | clr P1.ApwmFET 186 | ENDIF 187 | setb P1.AcomFET 188 | ENDM 189 | AcomFET_off MACRO 190 | clr P1.AcomFET 191 | ENDM 192 | BcomFET_on MACRO 193 | IF FETON_DELAY == 0 194 | clr P1.BpwmFET 195 | ENDIF 196 | setb P1.BcomFET 197 | ENDM 198 | BcomFET_off MACRO 199 | clr P1.BcomFET 200 | ENDM 201 | CcomFET_on MACRO 202 | IF FETON_DELAY == 0 203 | clr P1.CpwmFET 204 | ENDIF 205 | setb P1.CcomFET 206 | ENDM 207 | CcomFET_off MACRO 208 | clr P1.CcomFET 209 | ENDM 210 | All_comFETs_Off MACRO 211 | clr P1.AcomFET 212 | clr P1.BcomFET 213 | clr P1.CcomFET 214 | ENDM 215 | 216 | Set_Pwm_A MACRO 217 | IF FETON_DELAY == 0 218 | setb P1.AcomFET 219 | mov P1SKIP, #3Bh 220 | ELSE 221 | mov P1SKIP, #1Bh 222 | ENDIF 223 | ENDM 224 | Set_Pwm_B MACRO 225 | IF FETON_DELAY == 0 226 | setb P1.BcomFET 227 | mov P1SKIP, #3Dh 228 | ELSE 229 | mov P1SKIP, #2Dh 230 | ENDIF 231 | ENDM 232 | Set_Pwm_C MACRO 233 | IF FETON_DELAY == 0 234 | setb P1.CcomFET 235 | mov P1SKIP, #3Eh 236 | ELSE 237 | mov P1SKIP, #36h 238 | ENDIF 239 | ENDM 240 | Set_Pwms_Off MACRO 241 | mov P1SKIP, #3Fh 242 | ENDM 243 | 244 | Set_Comp_Phase_A MACRO 245 | mov CMP0MX, #10h ; Set comparator multiplexer to phase A 246 | ENDM 247 | Set_Comp_Phase_B MACRO 248 | mov CMP0MX, #20h ; Set comparator multiplexer to phase B 249 | ENDM 250 | Set_Comp_Phase_C MACRO 251 | mov CMP0MX, #30h ; Set comparator multiplexer to phase C 252 | ENDM 253 | Read_Comp_Out MACRO 254 | mov A, CMP0CN0 ; Read comparator output 255 | ENDM 256 | 257 | 258 | ;********************* 259 | ; PORT 2 definitions * 260 | ;********************* 261 | DebugPin EQU 0 ;o 262 | 263 | P2_PUSHPULL EQU (1 SHL DebugPin) 264 | 265 | 266 | ;********************** 267 | ; MCU specific macros * 268 | ;********************** 269 | 270 | Initialize_Xbar MACRO 271 | mov XBR2, #40h ; Xbar enabled 272 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 273 | ENDM 274 | 275 | Initialize_Comparator MACRO 276 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 277 | mov CMP0MD, #00h ; Comparator response time 100ns 278 | ENDM 279 | Initialize_Adc MACRO 280 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 281 | IF MCU_48MHZ == 0 282 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 283 | ELSE 284 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 285 | ENDIF 286 | mov ADC0MX, #10h ; Select temp sensor input 287 | mov ADC0CN0, #80h ; ADC enabled 288 | mov ADC0CN1, #01h ; Common mode buffer enabled 289 | ENDM 290 | Start_Adc MACRO 291 | mov ADC0CN0, #90h ; ADC start 292 | ENDM 293 | Read_Adc_Result MACRO 294 | mov Temp1, ADC0L 295 | mov Temp2, ADC0H 296 | ENDM 297 | Stop_Adc MACRO 298 | ENDM 299 | Set_RPM_Out MACRO 300 | ENDM 301 | Clear_RPM_Out MACRO 302 | ENDM 303 | Set_LED_0 MACRO 304 | ENDM 305 | Clear_LED_0 MACRO 306 | ENDM 307 | Set_LED_1 MACRO 308 | ENDM 309 | Clear_LED_1 MACRO 310 | ENDM 311 | Set_LED_2 MACRO 312 | ENDM 313 | Clear_LED_2 MACRO 314 | ENDM 315 | Set_LED_3 MACRO 316 | ENDM 317 | Clear_LED_3 MACRO 318 | ENDM 319 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # jesc 2 | 3 | Learn more about JESC [Here](https://jflight.net). 4 | -------------------------------------------------------------------------------- /S.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "S". like "O" but Com fets are active high, Pwm fets are active low 26 | ; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 5 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | ; EQU 7 ;i 66 | ; EQU 6 ;i 67 | Rcp_In EQU 5 ;i 68 | ; EQU 4 ;i 69 | Comp_Com EQU 3 ;i 70 | Mux_A EQU 2 ;i 71 | Mux_C EQU 1 ;i 72 | Mux_B EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU 0FFh 76 | P0_PUSHPULL EQU 0 77 | P0_SKIP EQU 0FFh 78 | 79 | Set_Pwm_Polarity MACRO 80 | IF FETON_DELAY == 0 81 | mov PCA0POL, #00h ; Pwm noninverted 82 | ELSE 83 | mov PCA0POL, #01h ; Damping inverted, pwm noninverted 84 | ENDIF 85 | ENDM 86 | Enable_Power_Pwm_Module MACRO 87 | IF FETON_DELAY == 0 88 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 89 | ELSE 90 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 91 | ENDIF 92 | ENDM 93 | Enable_Damp_Pwm_Module MACRO 94 | IF FETON_DELAY == 0 95 | mov PCA0CPM1, #00h ; Disable 96 | ELSE 97 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 98 | ENDIF 99 | ENDM 100 | Clear_COVF_Interrupt MACRO 101 | anl PCA0PWM, #0DFh 102 | ENDM 103 | Clear_CCF_Interrupt MACRO 104 | anl PCA0CN0, #0FEh 105 | ENDM 106 | Enable_COVF_Interrupt MACRO 107 | orl PCA0PWM, #40h 108 | ENDM 109 | Enable_CCF_Interrupt MACRO 110 | orl PCA0CPM0,#01h 111 | ENDM 112 | Disable_COVF_Interrupt MACRO 113 | anl PCA0PWM, #0BFh 114 | ENDM 115 | Disable_CCF_Interrupt MACRO 116 | anl PCA0CPM0,#0FEh 117 | ENDM 118 | 119 | 120 | ;********************* 121 | ; PORT 1 definitions * 122 | ;********************* 123 | ; EQU 7 ;i 124 | ; EQU 6 ;i 125 | CpwmFET EQU 5 ;o 126 | CcomFET EQU 4 ;o 127 | BpwmFET EQU 3 ;o 128 | BcomFET EQU 2 ;o 129 | ApwmFET EQU 1 ;o 130 | AcomFET EQU 0 ;o 131 | 132 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 133 | P1_INIT EQU (0 SHL AcomFET)+(0 SHL BcomFET)+(0 SHL CcomFET) 134 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 135 | P1_SKIP EQU 3Fh 136 | 137 | ApwmFET_on MACRO 138 | setb P1.ApwmFET 139 | IF FETON_DELAY == 0 140 | setb P1.AcomFET 141 | ENDIF 142 | ENDM 143 | ApwmFET_off MACRO 144 | IF FETON_DELAY != 0 145 | clr P1.ApwmFET 146 | ELSE 147 | clr P1.AcomFET 148 | ENDIF 149 | ENDM 150 | BpwmFET_on MACRO 151 | setb P1.BpwmFET 152 | IF FETON_DELAY == 0 153 | setb P1.BcomFET 154 | ENDIF 155 | ENDM 156 | BpwmFET_off MACRO 157 | IF FETON_DELAY != 0 158 | clr P1.BpwmFET 159 | ELSE 160 | clr P1.BcomFET 161 | ENDIF 162 | ENDM 163 | CpwmFET_on MACRO 164 | setb P1.CpwmFET 165 | IF FETON_DELAY == 0 166 | setb P1.CcomFET 167 | ENDIF 168 | ENDM 169 | CpwmFET_off MACRO 170 | IF FETON_DELAY != 0 171 | clr P1.CpwmFET 172 | ELSE 173 | clr P1.CcomFET 174 | ENDIF 175 | ENDM 176 | All_pwmFETs_Off MACRO 177 | IF FETON_DELAY != 0 178 | clr P1.ApwmFET 179 | clr P1.BpwmFET 180 | clr P1.CpwmFET 181 | ELSE 182 | clr P1.AcomFET 183 | clr P1.BcomFET 184 | clr P1.CcomFET 185 | ENDIF 186 | ENDM 187 | 188 | AcomFET_on MACRO 189 | IF FETON_DELAY == 0 190 | clr P1.ApwmFET 191 | ENDIF 192 | setb P1.AcomFET 193 | ENDM 194 | AcomFET_off MACRO 195 | clr P1.AcomFET 196 | ENDM 197 | BcomFET_on MACRO 198 | IF FETON_DELAY == 0 199 | clr P1.BpwmFET 200 | ENDIF 201 | setb P1.BcomFET 202 | ENDM 203 | BcomFET_off MACRO 204 | clr P1.BcomFET 205 | ENDM 206 | CcomFET_on MACRO 207 | IF FETON_DELAY == 0 208 | clr P1.CpwmFET 209 | ENDIF 210 | setb P1.CcomFET 211 | ENDM 212 | CcomFET_off MACRO 213 | clr P1.CcomFET 214 | ENDM 215 | All_comFETs_Off MACRO 216 | clr P1.AcomFET 217 | clr P1.BcomFET 218 | clr P1.CcomFET 219 | ENDM 220 | 221 | Set_Pwm_A MACRO 222 | IF FETON_DELAY == 0 223 | setb P1.AcomFET 224 | mov P1SKIP, #3Dh 225 | ELSE 226 | mov P1SKIP, #3Ch 227 | ENDIF 228 | ENDM 229 | Set_Pwm_B MACRO 230 | IF FETON_DELAY == 0 231 | setb P1.BcomFET 232 | mov P1SKIP, #37h 233 | ELSE 234 | mov P1SKIP, #33h 235 | ENDIF 236 | ENDM 237 | Set_Pwm_C MACRO 238 | IF FETON_DELAY == 0 239 | setb P1.CcomFET 240 | mov P1SKIP, #1Fh 241 | ELSE 242 | mov P1SKIP, #0Fh 243 | ENDIF 244 | ENDM 245 | Set_Pwms_Off MACRO 246 | mov P1SKIP, #3Fh 247 | ENDM 248 | 249 | Set_Comp_Phase_A MACRO 250 | mov CMP0MX, #23h ; Set comparator multiplexer to phase A 251 | ENDM 252 | Set_Comp_Phase_B MACRO 253 | mov CMP0MX, #03h ; Set comparator multiplexer to phase B 254 | ENDM 255 | Set_Comp_Phase_C MACRO 256 | mov CMP0MX, #13h ; Set comparator multiplexer to phase C 257 | ENDM 258 | Read_Comp_Out MACRO 259 | mov A, CMP0CN0 ; Read comparator output 260 | ENDM 261 | 262 | 263 | ;********************* 264 | ; PORT 2 definitions * 265 | ;********************* 266 | DebugPin EQU 0 ;o 267 | 268 | P2_PUSHPULL EQU (1 SHL DebugPin) 269 | 270 | 271 | ;********************** 272 | ; MCU specific macros * 273 | ;********************** 274 | 275 | 276 | Initialize_Xbar MACRO 277 | mov XBR2, #40h ; Xbar enabled 278 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 279 | ENDM 280 | 281 | Initialize_Comparator MACRO 282 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 283 | mov CMP0MD, #00h ; Comparator response time 100ns 284 | ENDM 285 | Initialize_Adc MACRO 286 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 287 | IF MCU_48MHZ == 0 288 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 289 | ELSE 290 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 291 | ENDIF 292 | mov ADC0MX, #10h ; Select temp sensor input 293 | mov ADC0CN0, #80h ; ADC enabled 294 | mov ADC0CN1, #01h ; Common mode buffer enabled 295 | ENDM 296 | Start_Adc MACRO 297 | mov ADC0CN0, #90h ; ADC start 298 | ENDM 299 | Read_Adc_Result MACRO 300 | mov Temp1, ADC0L 301 | mov Temp2, ADC0H 302 | ENDM 303 | Stop_Adc MACRO 304 | ENDM 305 | Set_RPM_Out MACRO 306 | ENDM 307 | Clear_RPM_Out MACRO 308 | ENDM 309 | Set_LED_0 MACRO 310 | ENDM 311 | Clear_LED_0 MACRO 312 | ENDM 313 | Set_LED_1 MACRO 314 | ENDM 315 | Clear_LED_1 MACRO 316 | ENDM 317 | Set_LED_2 MACRO 318 | ENDM 319 | Clear_LED_2 MACRO 320 | ENDM 321 | Set_LED_3 MACRO 322 | ENDM 323 | Clear_LED_3 MACRO 324 | ENDM 325 | -------------------------------------------------------------------------------- /T.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "T". 26 | ; RC X MA X MB CC MC X X X Cp Bp Ap Ac Bc Cc 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 7 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | 63 | ;********************* 64 | ; PORT 0 definitions * 65 | ;********************* 66 | Rcp_In EQU 7 ;i 67 | ; EQU 6 ;i 68 | Mux_A EQU 5 ;i 69 | ; EQU 4 ;i 70 | Mux_B EQU 3 ;i 71 | Comp_Com EQU 2 ;i 72 | Mux_C EQU 1 ;i 73 | ; EQU 0 ;i 74 | 75 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 76 | P0_INIT EQU 0FFh 77 | P0_PUSHPULL EQU 0 78 | P0_SKIP EQU 0FFh 79 | 80 | Set_Pwm_Polarity MACRO 81 | IF FETON_DELAY == 0 82 | mov PCA0POL, #00h ; Pwm noninverted 83 | ELSE 84 | mov PCA0POL, #01h ; Damping inverted, pwm noninverted 85 | ENDIF 86 | ENDM 87 | Enable_Power_Pwm_Module MACRO 88 | IF FETON_DELAY == 0 89 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 90 | ELSE 91 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 92 | ENDIF 93 | ENDM 94 | Enable_Damp_Pwm_Module MACRO 95 | IF FETON_DELAY == 0 96 | mov PCA0CPM1, #00h ; Disable 97 | ELSE 98 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 99 | ENDIF 100 | ENDM 101 | Clear_COVF_Interrupt MACRO 102 | anl PCA0PWM, #0DFh 103 | ENDM 104 | Clear_CCF_Interrupt MACRO ; CCF interrupt is only used for FETON_DELAY == 0 105 | anl PCA0CN0, #0FEh 106 | ENDM 107 | Enable_COVF_Interrupt MACRO 108 | orl PCA0PWM, #40h 109 | ENDM 110 | Enable_CCF_Interrupt MACRO 111 | orl PCA0CPM0,#01h 112 | ENDM 113 | Disable_COVF_Interrupt MACRO 114 | anl PCA0PWM, #0BFh 115 | ENDM 116 | Disable_CCF_Interrupt MACRO 117 | anl PCA0CPM0,#0FEh 118 | ENDM 119 | 120 | 121 | ;********************* 122 | ; PORT 1 definitions * 123 | ;********************* 124 | ; EQU 7 ;i 125 | ; EQU 6 ;i 126 | CpwmFET EQU 5 ;o 127 | BpwmFET EQU 4 ;o 128 | ApwmFET EQU 3 ;o 129 | AcomFET EQU 2 ;o 130 | BcomFET EQU 1 ;o 131 | CcomFET EQU 0 ;o 132 | 133 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 134 | P1_INIT EQU 00h 135 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 136 | P1_SKIP EQU 3Fh 137 | 138 | ApwmFET_on MACRO 139 | setb P1.ApwmFET 140 | IF FETON_DELAY == 0 141 | setb P1.AcomFET 142 | ENDIF 143 | ENDM 144 | ApwmFET_off MACRO 145 | IF FETON_DELAY != 0 146 | clr P1.ApwmFET 147 | ELSE 148 | clr P1.AcomFET 149 | ENDIF 150 | ENDM 151 | BpwmFET_on MACRO 152 | setb P1.BpwmFET 153 | IF FETON_DELAY == 0 154 | setb P1.BcomFET 155 | ENDIF 156 | ENDM 157 | BpwmFET_off MACRO 158 | IF FETON_DELAY != 0 159 | clr P1.BpwmFET 160 | ELSE 161 | clr P1.BcomFET 162 | ENDIF 163 | ENDM 164 | CpwmFET_on MACRO 165 | setb P1.CpwmFET 166 | IF FETON_DELAY == 0 167 | setb P1.CcomFET 168 | ENDIF 169 | ENDM 170 | CpwmFET_off MACRO 171 | IF FETON_DELAY != 0 172 | clr P1.CpwmFET 173 | ELSE 174 | clr P1.CcomFET 175 | ENDIF 176 | ENDM 177 | All_pwmFETs_Off MACRO 178 | IF FETON_DELAY != 0 179 | clr P1.ApwmFET 180 | clr P1.BpwmFET 181 | clr P1.CpwmFET 182 | ELSE 183 | clr P1.AcomFET 184 | clr P1.BcomFET 185 | clr P1.CcomFET 186 | ENDIF 187 | ENDM 188 | 189 | AcomFET_on MACRO 190 | IF FETON_DELAY == 0 191 | clr P1.ApwmFET 192 | ENDIF 193 | setb P1.AcomFET 194 | ENDM 195 | AcomFET_off MACRO 196 | clr P1.AcomFET 197 | ENDM 198 | BcomFET_on MACRO 199 | IF FETON_DELAY == 0 200 | clr P1.BpwmFET 201 | ENDIF 202 | setb P1.BcomFET 203 | ENDM 204 | BcomFET_off MACRO 205 | clr P1.BcomFET 206 | ENDM 207 | CcomFET_on MACRO 208 | IF FETON_DELAY == 0 209 | clr P1.CpwmFET 210 | ENDIF 211 | setb P1.CcomFET 212 | ENDM 213 | CcomFET_off MACRO 214 | clr P1.CcomFET 215 | ENDM 216 | All_comFETs_Off MACRO 217 | clr P1.AcomFET 218 | clr P1.BcomFET 219 | clr P1.CcomFET 220 | ENDM 221 | 222 | Set_Pwm_A MACRO 223 | IF FETON_DELAY == 0 224 | setb P1.AcomFET 225 | mov P1SKIP, #37h 226 | ELSE 227 | mov P1SKIP, #33h 228 | ENDIF 229 | ENDM 230 | Set_Pwm_B MACRO 231 | IF FETON_DELAY == 0 232 | setb P1.BcomFET 233 | mov P1SKIP, #2Fh 234 | ELSE 235 | mov P1SKIP, #2Dh 236 | ENDIF 237 | ENDM 238 | Set_Pwm_C MACRO 239 | IF FETON_DELAY == 0 240 | setb P1.CcomFET 241 | mov P1SKIP, #1Fh 242 | ELSE 243 | mov P1SKIP, #1Eh 244 | ENDIF 245 | ENDM 246 | Set_Pwms_Off MACRO 247 | mov P1SKIP, #3Fh 248 | ENDM 249 | 250 | Set_Comp_Phase_A MACRO 251 | mov CMP0MX, #52h ; Set comparator multiplexer to phase A 252 | ENDM 253 | Set_Comp_Phase_B MACRO 254 | mov CMP0MX, #32h ; Set comparator multiplexer to phase B 255 | ENDM 256 | Set_Comp_Phase_C MACRO 257 | mov CMP0MX, #12h ; Set comparator multiplexer to phase C 258 | ENDM 259 | Read_Comp_Out MACRO 260 | mov A, CMP0CN0 ; Read comparator output 261 | ENDM 262 | 263 | 264 | ;********************* 265 | ; PORT 2 definitions * 266 | ;********************* 267 | DebugPin EQU 0 ;o 268 | 269 | P2_PUSHPULL EQU (1 SHL DebugPin) 270 | 271 | 272 | ;********************** 273 | ; MCU specific macros * 274 | ;********************** 275 | 276 | Initialize_Xbar MACRO 277 | mov XBR2, #40h ; Xbar enabled 278 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 279 | ENDM 280 | 281 | Initialize_Comparator MACRO 282 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 283 | mov CMP0MD, #00h ; Comparator response time 100ns 284 | ENDM 285 | Initialize_Adc MACRO 286 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 287 | IF MCU_48MHZ == 0 288 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 289 | ELSE 290 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 291 | ENDIF 292 | mov ADC0MX, #10h ; Select temp sensor input 293 | mov ADC0CN0, #80h ; ADC enabled 294 | mov ADC0CN1, #01h ; Common mode buffer enabled 295 | ENDM 296 | Start_Adc MACRO 297 | mov ADC0CN0, #90h ; ADC start 298 | ENDM 299 | Read_Adc_Result MACRO 300 | mov Temp1, ADC0L 301 | mov Temp2, ADC0H 302 | ENDM 303 | Stop_Adc MACRO 304 | ENDM 305 | Set_RPM_Out MACRO 306 | ENDM 307 | Clear_RPM_Out MACRO 308 | ENDM 309 | Set_LED_0 MACRO 310 | ENDM 311 | Clear_LED_0 MACRO 312 | ENDM 313 | Set_LED_1 MACRO 314 | ENDM 315 | Clear_LED_1 MACRO 316 | ENDM 317 | Set_LED_2 MACRO 318 | ENDM 319 | Clear_LED_2 MACRO 320 | ENDM 321 | Set_LED_3 MACRO 322 | ENDM 323 | Clear_LED_3 MACRO 324 | ENDM 325 | -------------------------------------------------------------------------------- /U.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "U". 26 | ; MA MC CC MB RC L0 L1 L2 X Cc Bc Ac Cp Bp Ap X 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | 43 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 44 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 45 | 46 | ;**** **** **** **** **** 47 | ; Bootloader definitions 48 | ;**** **** **** **** **** 49 | RTX_PORT EQU P0 ; Receive/Transmit port 50 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 51 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 52 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 53 | RTX_PIN EQU 3 ; RTX pin 54 | 55 | SIGNATURE_001 EQU 0E8h ; Device signature 56 | IF MCU_48MHZ == 0 57 | SIGNATURE_002 EQU 0B1h 58 | ELSE 59 | SIGNATURE_002 EQU 0B2h 60 | ENDIF 61 | 62 | 63 | ;********************* 64 | ; PORT 0 definitions * 65 | ;********************* 66 | Mux_A EQU 7 ;i 67 | Mux_C EQU 6 ;i 68 | Comp_Com EQU 5 ;i 69 | Mux_B EQU 4 ;i 70 | Rcp_In EQU 3 ;i 71 | LED_0 EQU 2 ;i 72 | LED_1 EQU 1 ;i 73 | LED_2 EQU 0 ;i 74 | 75 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 76 | P0_INIT EQU 0FFh 77 | P0_PUSHPULL EQU (1 SHL LED_0)+(1 SHL LED_1)+(1 SHL LED_2) 78 | P0_SKIP EQU 0FFh 79 | 80 | Set_Pwm_Polarity MACRO 81 | mov PCA0POL, #02h ; Damping inverted, pwm noninverted 82 | ENDM 83 | Enable_Power_Pwm_Module MACRO 84 | IF FETON_DELAY == 0 85 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 86 | ELSE 87 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 88 | ENDIF 89 | ENDM 90 | Enable_Damp_Pwm_Module MACRO 91 | IF FETON_DELAY == 0 92 | mov PCA0CPM1, #00h ; Disable 93 | ELSE 94 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 95 | ENDIF 96 | ENDM 97 | Clear_COVF_Interrupt MACRO 98 | anl PCA0PWM, #0DFh 99 | ENDM 100 | Clear_CCF_Interrupt MACRO 101 | anl PCA0CN0, #0FEh 102 | ENDM 103 | Enable_COVF_Interrupt MACRO 104 | orl PCA0PWM, #40h 105 | ENDM 106 | Enable_CCF_Interrupt MACRO 107 | orl PCA0CPM0,#01h 108 | ENDM 109 | Disable_COVF_Interrupt MACRO 110 | anl PCA0PWM, #0BFh 111 | ENDM 112 | Disable_CCF_Interrupt MACRO 113 | anl PCA0CPM0,#0FEh 114 | ENDM 115 | 116 | 117 | 118 | ;********************* 119 | ; PORT 1 definitions * 120 | ;********************* 121 | ; EQU 7 ;i 122 | CcomFET EQU 6 ;o 123 | BcomFET EQU 5 ;o 124 | AcomFET EQU 4 ;o 125 | CpwmFET EQU 3 ;i 126 | BpwmFET EQU 2 ;o 127 | ApwmFET EQU 1 ;o 128 | ; EQU 0 ;o 129 | 130 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 131 | P1_INIT EQU 00h 132 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET) 133 | P1_SKIP EQU 7Fh 134 | 135 | ApwmFET_on MACRO 136 | setb P1.ApwmFET 137 | IF FETON_DELAY == 0 138 | setb P1.AcomFET 139 | ENDIF 140 | ENDM 141 | ApwmFET_off MACRO 142 | IF FETON_DELAY != 0 143 | clr P1.ApwmFET 144 | ELSE 145 | clr P1.AcomFET 146 | ENDIF 147 | ENDM 148 | BpwmFET_on MACRO 149 | setb P1.BpwmFET 150 | IF FETON_DELAY == 0 151 | setb P1.BcomFET 152 | ENDIF 153 | ENDM 154 | BpwmFET_off MACRO 155 | IF FETON_DELAY != 0 156 | clr P1.BpwmFET 157 | ELSE 158 | clr P1.BcomFET 159 | ENDIF 160 | ENDM 161 | CpwmFET_on MACRO 162 | setb P1.CpwmFET 163 | IF FETON_DELAY == 0 164 | setb P1.CcomFET 165 | ENDIF 166 | ENDM 167 | CpwmFET_off MACRO 168 | IF FETON_DELAY != 0 169 | clr P1.CpwmFET 170 | ELSE 171 | clr P1.CcomFET 172 | ENDIF 173 | ENDM 174 | All_pwmFETs_Off MACRO 175 | IF FETON_DELAY != 0 176 | clr P1.ApwmFET 177 | clr P1.BpwmFET 178 | clr P1.CpwmFET 179 | ELSE 180 | clr P1.AcomFET 181 | clr P1.BcomFET 182 | clr P1.CcomFET 183 | ENDIF 184 | ENDM 185 | 186 | AcomFET_on MACRO 187 | IF FETON_DELAY == 0 188 | clr P1.ApwmFET 189 | ENDIF 190 | setb P1.AcomFET 191 | ENDM 192 | AcomFET_off MACRO 193 | clr P1.AcomFET 194 | ENDM 195 | BcomFET_on MACRO 196 | IF FETON_DELAY == 0 197 | clr P1.BpwmFET 198 | ENDIF 199 | setb P1.BcomFET 200 | ENDM 201 | BcomFET_off MACRO 202 | clr P1.BcomFET 203 | ENDM 204 | CcomFET_on MACRO 205 | IF FETON_DELAY == 0 206 | clr P1.CpwmFET 207 | ENDIF 208 | setb P1.CcomFET 209 | ENDM 210 | CcomFET_off MACRO 211 | clr P1.CcomFET 212 | ENDM 213 | All_comFETs_Off MACRO 214 | clr P1.AcomFET 215 | clr P1.BcomFET 216 | clr P1.CcomFET 217 | ENDM 218 | 219 | Set_Pwm_A MACRO 220 | IF FETON_DELAY == 0 221 | setb P1.AcomFET 222 | mov P1SKIP, #7Dh 223 | ELSE 224 | mov P1SKIP, #6Dh 225 | ENDIF 226 | ENDM 227 | Set_Pwm_B MACRO 228 | IF FETON_DELAY == 0 229 | setb P1.BcomFET 230 | mov P1SKIP, #7Bh 231 | ELSE 232 | mov P1SKIP, #5Bh 233 | ENDIF 234 | ENDM 235 | Set_Pwm_C MACRO 236 | IF FETON_DELAY == 0 237 | setb P1.CcomFET 238 | mov P1SKIP, #77h 239 | ELSE 240 | mov P1SKIP, #37h 241 | ENDIF 242 | ENDM 243 | Set_Pwms_Off MACRO 244 | mov P1SKIP, #7Fh 245 | ENDM 246 | 247 | Set_Comp_Phase_A MACRO 248 | mov CMP0MX, #75h ; Set comparator multiplexer to phase A 249 | ENDM 250 | Set_Comp_Phase_B MACRO 251 | mov CMP0MX, #45h ; Set comparator multiplexer to phase B 252 | ENDM 253 | Set_Comp_Phase_C MACRO 254 | mov CMP0MX, #65h ; Set comparator multiplexer to phase C 255 | ENDM 256 | Read_Comp_Out MACRO 257 | mov A, CMP0CN0 ; Read comparator output 258 | ENDM 259 | 260 | 261 | ;********************* 262 | ; PORT 2 definitions * 263 | ;********************* 264 | DebugPin EQU 0 ;o 265 | 266 | P2_PUSHPULL EQU (1 SHL DebugPin) 267 | 268 | 269 | ;********************** 270 | ; MCU specific macros * 271 | ;********************** 272 | 273 | Initialize_Xbar MACRO 274 | mov XBR2, #40h ; Xbar enabled 275 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 276 | ENDM 277 | 278 | Initialize_Comparator MACRO 279 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 280 | mov CMP0MD, #00h ; Comparator response time 100ns 281 | ENDM 282 | Initialize_Adc MACRO 283 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 284 | IF MCU_48MHZ == 0 285 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 286 | ELSE 287 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 288 | ENDIF 289 | mov ADC0MX, #10h ; Select temp sensor input 290 | mov ADC0CN0, #80h ; ADC enabled 291 | mov ADC0CN1, #01h ; Common mode buffer enabled 292 | ENDM 293 | Start_Adc MACRO 294 | mov ADC0CN0, #90h ; ADC start 295 | ENDM 296 | Read_Adc_Result MACRO 297 | mov Temp1, ADC0L 298 | mov Temp2, ADC0H 299 | ENDM 300 | Stop_Adc MACRO 301 | ENDM 302 | Set_RPM_Out MACRO 303 | ENDM 304 | Clear_RPM_Out MACRO 305 | ENDM 306 | Set_LED_0 MACRO 307 | clr P0.LED_0 308 | ENDM 309 | Clear_LED_0 MACRO 310 | setb P0.LED_0 311 | ENDM 312 | Set_LED_1 MACRO 313 | clr P0.LED_1 314 | ENDM 315 | Clear_LED_1 MACRO 316 | setb P0.LED_1 317 | ENDM 318 | Set_LED_2 MACRO 319 | clr P0.LED_2 320 | ENDM 321 | Clear_LED_2 MACRO 322 | setb P0.LED_2 323 | ENDM 324 | Set_LED_3 MACRO 325 | ENDM 326 | Clear_LED_3 MACRO 327 | ENDM 328 | 329 | -------------------------------------------------------------------------------- /V.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "V" 26 | ; Cc X RC X MC CC MB MA X Ap Ac Bp X X Bc Cp 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 43 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 44 | 45 | ;**** **** **** **** **** 46 | ; Bootloader definitions 47 | ;**** **** **** **** **** 48 | RTX_PORT EQU P0 ; Receive/Transmit port 49 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 50 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 51 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 52 | RTX_PIN EQU 5 ; RTX pin 53 | 54 | SIGNATURE_001 EQU 0E8h ; Device signature 55 | IF MCU_48MHZ == 0 56 | SIGNATURE_002 EQU 0B1h 57 | ELSE 58 | SIGNATURE_002 EQU 0B2h 59 | ENDIF 60 | 61 | ;********************* 62 | ; PORT 0 definitions * 63 | ;********************* 64 | CcomFET EQU 7 ;o 65 | ; EQU 6 ;i 66 | Rcp_In EQU 5 ;i 67 | ; EQU 4 ;i 68 | Mux_C EQU 3 ;i 69 | Comp_Com EQU 2 ;i 70 | Mux_B EQU 1 ;i 71 | Mux_A EQU 0 ;i 72 | 73 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 74 | P0_INIT EQU NOT(1 SHL CcomFET) 75 | P0_PUSHPULL EQU (1 SHL CcomFET) 76 | P0_SKIP EQU 0FFh 77 | 78 | Set_Pwm_Polarity MACRO 79 | IF FETON_DELAY == 0 80 | mov PCA0POL, #00h ; Pwm noninverted 81 | ELSE 82 | mov PCA0POL, #01h ; Damping inverted, pwm noninverted 83 | ENDIF 84 | ENDM 85 | Enable_Power_Pwm_Module MACRO 86 | IF FETON_DELAY == 0 87 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 88 | ELSE 89 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 90 | ENDIF 91 | ENDM 92 | Enable_Damp_Pwm_Module MACRO 93 | IF FETON_DELAY == 0 94 | mov PCA0CPM1, #00h ; Disable 95 | ELSE 96 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 97 | ENDIF 98 | ENDM 99 | Clear_COVF_Interrupt MACRO 100 | anl PCA0PWM, #0DFh 101 | ENDM 102 | Clear_CCF_Interrupt MACRO 103 | anl PCA0CN0, #0FEh 104 | ENDM 105 | Enable_COVF_Interrupt MACRO 106 | orl PCA0PWM, #40h 107 | ENDM 108 | Enable_CCF_Interrupt MACRO 109 | orl PCA0CPM0,#01h 110 | ENDM 111 | Disable_COVF_Interrupt MACRO 112 | anl PCA0PWM, #0BFh 113 | ENDM 114 | Disable_CCF_Interrupt MACRO 115 | anl PCA0CPM0,#0FEh 116 | ENDM 117 | 118 | 119 | ;********************* 120 | ; PORT 1 definitions * 121 | ;********************* 122 | ; EQU 7 ;i 123 | ApwmFET EQU 6 ;i 124 | AcomFET EQU 5 ;i 125 | BpwmFET EQU 4 ;o 126 | ; EQU 3 ;o 127 | ; EQU 2 ;o 128 | BcomFET EQU 1 ;o 129 | CpwmFET EQU 0 ;o 130 | 131 | P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET) 132 | P1_INIT EQU 00h 133 | P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET) 134 | P1_SKIP EQU 7Fh 135 | 136 | ApwmFET_on MACRO 137 | setb P1.ApwmFET 138 | IF FETON_DELAY == 0 139 | setb P1.AcomFET 140 | ENDIF 141 | ENDM 142 | ApwmFET_off MACRO 143 | IF FETON_DELAY != 0 144 | clr P1.ApwmFET 145 | ELSE 146 | clr P1.AcomFET 147 | ENDIF 148 | ENDM 149 | BpwmFET_on MACRO 150 | setb P1.BpwmFET 151 | IF FETON_DELAY == 0 152 | setb P1.BcomFET 153 | ENDIF 154 | ENDM 155 | BpwmFET_off MACRO 156 | IF FETON_DELAY != 0 157 | clr P1.BpwmFET 158 | ELSE 159 | clr P1.BcomFET 160 | ENDIF 161 | ENDM 162 | CpwmFET_on MACRO 163 | setb P1.CpwmFET 164 | IF FETON_DELAY == 0 165 | setb P0.CcomFET 166 | ENDIF 167 | ENDM 168 | CpwmFET_off MACRO 169 | IF FETON_DELAY != 0 170 | clr P1.CpwmFET 171 | ELSE 172 | clr P0.CcomFET 173 | ENDIF 174 | ENDM 175 | All_pwmFETs_Off MACRO 176 | IF FETON_DELAY != 0 177 | clr P1.ApwmFET 178 | clr P1.BpwmFET 179 | clr P1.CpwmFET 180 | ELSE 181 | clr P1.AcomFET 182 | clr P1.BcomFET 183 | clr P0.CcomFET 184 | ENDIF 185 | ENDM 186 | 187 | AcomFET_on MACRO 188 | IF FETON_DELAY == 0 189 | clr P1.ApwmFET 190 | ENDIF 191 | setb P1.AcomFET 192 | ENDM 193 | AcomFET_off MACRO 194 | clr P1.AcomFET 195 | ENDM 196 | BcomFET_on MACRO 197 | IF FETON_DELAY == 0 198 | clr P1.BpwmFET 199 | ENDIF 200 | setb P1.BcomFET 201 | ENDM 202 | BcomFET_off MACRO 203 | clr P1.BcomFET 204 | ENDM 205 | CcomFET_on MACRO 206 | IF FETON_DELAY == 0 207 | clr P1.CpwmFET 208 | ENDIF 209 | setb P0.CcomFET 210 | ENDM 211 | CcomFET_off MACRO 212 | clr P0.CcomFET 213 | ENDM 214 | All_comFETs_Off MACRO 215 | clr P1.AcomFET 216 | clr P1.BcomFET 217 | clr P0.CcomFET 218 | ENDM 219 | 220 | Set_Pwm_A MACRO 221 | IF FETON_DELAY == 0 222 | setb P1.AcomFET 223 | mov P0SKIP, #0FFh 224 | mov P1SKIP, #3Fh 225 | ELSE 226 | mov P0SKIP, #0FFh 227 | mov P1SKIP, #1Fh 228 | ENDIF 229 | ENDM 230 | Set_Pwm_B MACRO 231 | IF FETON_DELAY == 0 232 | setb P1.BcomFET 233 | mov P0SKIP, #0FFh 234 | mov P1SKIP, #6Fh 235 | ELSE 236 | mov P0SKIP, #0FFh 237 | mov P1SKIP, #6Dh 238 | endif 239 | ENDM 240 | Set_Pwm_C MACRO 241 | IF FETON_DELAY == 0 242 | setb P0.CcomFET 243 | mov P0SKIP, #0FFh 244 | mov P1SKIP, #7Fh 245 | ELSE 246 | mov P0SKIP, #7Fh 247 | mov P1SKIP, #7Eh 248 | endif 249 | ENDM 250 | Set_Pwms_Off MACRO 251 | mov P0SKIP, #0FFh 252 | mov P1SKIP, #7Fh 253 | ENDM 254 | 255 | Set_Comp_Phase_A MACRO 256 | mov CMP0MX, #02h ; Set comparator multiplexer to phase A 257 | ENDM 258 | Set_Comp_Phase_B MACRO 259 | mov CMP0MX, #12h ; Set comparator multiplexer to phase B 260 | ENDM 261 | Set_Comp_Phase_C MACRO 262 | mov CMP0MX, #32h ; Set comparator multiplexer to phase C 263 | ENDM 264 | Read_Comp_Out MACRO 265 | mov A, CMP0CN0 ; Read comparator output 266 | ENDM 267 | 268 | 269 | ;********************* 270 | ; PORT 2 definitions * 271 | ;********************* 272 | DebugPin EQU 0 ;o 273 | 274 | P2_PUSHPULL EQU (1 SHL DebugPin) 275 | 276 | 277 | ;********************** 278 | ; MCU specific macros * 279 | ;********************** 280 | 281 | Initialize_Xbar MACRO 282 | mov XBR2, #40h ; Xbar enabled 283 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 284 | ENDM 285 | 286 | Initialize_Comparator MACRO 287 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 288 | mov CMP0MD, #00h ; Comparator response time 100ns 289 | ENDM 290 | Initialize_Adc MACRO 291 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 292 | IF MCU_48MHZ == 0 293 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 294 | ELSE 295 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 296 | ENDIF 297 | mov ADC0MX, #10h ; Select temp sensor input 298 | mov ADC0CN0, #80h ; ADC enabled 299 | mov ADC0CN1, #01h ; Common mode buffer enabled 300 | ENDM 301 | Start_Adc MACRO 302 | mov ADC0CN0, #90h ; ADC start 303 | ENDM 304 | Read_Adc_Result MACRO 305 | mov Temp1, ADC0L 306 | mov Temp2, ADC0H 307 | ENDM 308 | Stop_Adc MACRO 309 | ENDM 310 | Set_RPM_Out MACRO 311 | ENDM 312 | Clear_RPM_Out MACRO 313 | ENDM 314 | Set_LED_0 MACRO 315 | ENDM 316 | Clear_LED_0 MACRO 317 | ENDM 318 | Set_LED_1 MACRO 319 | ENDM 320 | Clear_LED_1 MACRO 321 | ENDM 322 | Set_LED_2 MACRO 323 | ENDM 324 | Clear_LED_2 MACRO 325 | ENDM 326 | Set_LED_3 MACRO 327 | ENDM 328 | Clear_LED_3 MACRO 329 | ENDM 330 | -------------------------------------------------------------------------------- /W.inc: -------------------------------------------------------------------------------- 1 | ;**** **** **** **** **** 2 | ; 3 | ; BLHeli program for controlling brushless motors in helicopters and multirotors 4 | ; 5 | ; Copyright 2011, 2012 Steffen Skaug 6 | ; This program is distributed under the terms of the GNU General Public License 7 | ; 8 | ; This file is part of BLHeli. 9 | ; 10 | ; BLHeli is free software: you can redistribute it and/or modify 11 | ; it under the terms of the GNU General Public License as published by 12 | ; the Free Software Foundation, either version 3 of the License, or 13 | ; (at your option) any later version. 14 | ; 15 | ; BLHeli is distributed in the hope that it will be useful, 16 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of 17 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 | ; GNU General Public License for more details. 19 | ; 20 | ; You should have received a copy of the GNU General Public License 21 | ; along with BLHeli. If not, see . 22 | ; 23 | ;**** **** **** **** **** 24 | ; 25 | ; Hardware definition file "W". This is for tristate input style FET driver chips 26 | ; RC MC MB X CC MA X X X Ap Bp Cp X X X X 27 | ; 28 | ;**** **** **** **** **** 29 | 30 | 31 | 32 | ;********************* 33 | ; Device SiLabs EFM8BB1x/2x 34 | ;********************* 35 | IF MCU_48MHZ == 0 36 | $include (SI_EFM8BB1_Defs.inc) 37 | ELSE 38 | $include (SI_EFM8BB2_Defs.inc) 39 | ENDIF 40 | 41 | 42 | TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1) 43 | TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC 44 | 45 | ;**** **** **** **** **** 46 | ; Bootloader definitions 47 | ;**** **** **** **** **** 48 | RTX_PORT EQU P0 ; Receive/Transmit port 49 | RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL 50 | RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL 51 | RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP 52 | RTX_PIN EQU 7 ; RTX pin 53 | 54 | SIGNATURE_001 EQU 0E8h ; Device signature 55 | IF MCU_48MHZ == 0 56 | SIGNATURE_002 EQU 0B1h 57 | ELSE 58 | SIGNATURE_002 EQU 0B2h 59 | ENDIF 60 | 61 | 62 | ;********************* 63 | ; PORT 0 definitions * 64 | ;********************* 65 | Rcp_In EQU 7 ;i 66 | Mux_C EQU 6 ;i 67 | Mux_B EQU 5 ;i 68 | ; EQU 4 ;i 69 | Comp_Com EQU 3 ;i 70 | Mux_A EQU 2 ;i 71 | ; EQU 1 ;i 72 | ; EQU 0 ;i 73 | 74 | P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)) 75 | P0_INIT EQU 0FFh 76 | P0_PUSHPULL EQU 0 77 | P0_SKIP EQU 0FFh 78 | 79 | 80 | Set_Pwm_Polarity MACRO 81 | IF FETON_DELAY == 0 82 | mov PCA0POL, #00h ; Pwm noninverted 83 | ELSE 84 | mov PCA0POL, #01h ; Damping inverted, pwm noninverted 85 | ENDIF 86 | ENDM 87 | Enable_Power_Pwm_Module MACRO 88 | IF FETON_DELAY == 0 89 | mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode 90 | ELSE 91 | mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode 92 | ENDIF 93 | ENDM 94 | Enable_Damp_Pwm_Module MACRO 95 | IF FETON_DELAY == 0 96 | mov PCA0CPM1, #00h ; Disable 97 | ELSE 98 | mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode 99 | ENDIF 100 | ENDM 101 | Clear_COVF_Interrupt MACRO 102 | anl PCA0PWM, #0DFh 103 | ENDM 104 | Clear_CCF_Interrupt MACRO ; CCF interrupt is only used for FETON_DELAY == 0 105 | anl PCA0CN0, #0FEh 106 | ENDM 107 | Enable_COVF_Interrupt MACRO 108 | orl PCA0PWM, #40h 109 | ENDM 110 | Enable_CCF_Interrupt MACRO 111 | orl PCA0CPM0,#01h 112 | ENDM 113 | Disable_COVF_Interrupt MACRO 114 | anl PCA0PWM, #0BFh 115 | ENDM 116 | Disable_CCF_Interrupt MACRO 117 | anl PCA0CPM0,#0FEh 118 | ENDM 119 | 120 | 121 | ;********************* 122 | ; PORT 1 definitions * 123 | ;********************* 124 | ; EQU 7 ;i 125 | ApwmFET EQU 6 ;o 126 | BpwmFET EQU 5 ;o 127 | CpwmFET EQU 4 ;o 128 | ; EQU 3 ;i 129 | ; EQU 2 ;i 130 | ; EQU 1 ;i 131 | ; EQU 0 ;i 132 | ; pwm outputs start as analog in -> floating 133 | ; this ensures all mosfet drivers start with floating outputs 134 | P1_DIGITAL EQU NOT((1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)) 135 | P1_INIT EQU 00h 136 | P1_PUSHPULL EQU ((1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)) 137 | ; 138 | P1_SKIP EQU 0FFh 139 | 140 | 141 | ApwmFET_on MACRO 142 | setb P1.ApwmFET ; set pin to high 143 | orl P1MDIN, #(1 SHL ApwmFET) ; enable pin driver 144 | ENDM 145 | ApwmFET_off MACRO 146 | anl P1MDIN, #(NOT(1 SHL ApwmFET)) ; analog in -> pullup, driver and digital in is disable = floating 147 | ENDM 148 | BpwmFET_on MACRO 149 | setb P1.BpwmFET ; set pin to high 150 | orl P1MDIN, #(1 SHL BpwmFET) ; enable pin driver 151 | ENDM 152 | BpwmFET_off MACRO 153 | anl P1MDIN, #(NOT(1 SHL BpwmFET)) ; analog in -> pullup, driver and digital in is disable = floating 154 | ENDM 155 | CpwmFET_on MACRO 156 | setb P1.CpwmFET ; set pin to high 157 | orl P1MDIN, #(1 SHL CpwmFET) ; enable pin driver 158 | ENDM 159 | CpwmFET_off MACRO 160 | anl P1MDIN, #(NOT(1 SHL CpwmFET)) ; analog in -> pullup, driver and digital in is disable = floating 161 | ENDM 162 | All_pwmFETs_Off MACRO 163 | anl P1MDIN, #(NOT((1 SHL ApwmFET) + (1 SHL BpwmFET) + (1 SHL CpwmFET))) ; analog in -> pullup, driver and digital in is disable = floating 164 | ENDM 165 | 166 | AcomFET_on MACRO 167 | clr P1.ApwmFET ; set pin to low 168 | orl P1MDIN, #(1 SHL ApwmFET) ; enable pin driver 169 | ENDM 170 | AcomFET_off MACRO 171 | anl P1MDIN, #(NOT(1 SHL ApwmFET)) ; analog in -> pullup, driver and digital in is disable = floating 172 | ENDM 173 | BcomFET_on MACRO 174 | clr P1.BpwmFET ; set pin to low 175 | orl P1MDIN, #(1 SHL BpwmFET) ; enable pin driver 176 | ENDM 177 | BcomFET_off MACRO 178 | anl P1MDIN, #(NOT(1 SHL BpwmFET)) ; analog in -> pullup, driver and digital in is disable = floating 179 | ENDM 180 | CcomFET_on MACRO 181 | clr P1.CpwmFET ; set pin to low 182 | orl P1MDIN, #(1 SHL CpwmFET) ; enable pin driver 183 | ENDM 184 | CcomFET_off MACRO 185 | anl P1MDIN, #(NOT(1 SHL CpwmFET)) ; analog in -> pullup, driver and digital in is disable = floating 186 | ENDM 187 | All_comFETs_Off MACRO 188 | anl P1MDIN, #(NOT((1 SHL ApwmFET) + (1 SHL BpwmFET) + (1 SHL CpwmFET))) ; analog in -> pullup, driver and digital in is disable = floating 189 | ENDM 190 | Set_Pwm_A MACRO 191 | mov P1SKIP, #(NOT(1 SHL ApwmFET)); 192 | orl P1MDIN, #(1 SHL ApwmFET) ; enable pin driver 193 | ENDM 194 | Set_Pwm_B MACRO 195 | mov P1SKIP, #(NOT(1 SHL BpwmFET)); 196 | orl P1MDIN, #(1 SHL BpwmFET) ; enable pin driver 197 | ENDM 198 | Set_Pwm_C MACRO 199 | mov P1SKIP, #(NOT(1 SHL CpwmFET)); 200 | orl P1MDIN, #(1 SHL CpwmFET) ; enable pin driver 201 | ENDM 202 | Set_Pwms_Off MACRO 203 | mov P1SKIP, #P1_SKIP; 204 | ENDM 205 | 206 | 207 | 208 | Set_Comp_Phase_A MACRO 209 | mov CMP0MX, #((Mux_A) SHL 4)+((Comp_Com) SHL 0); 210 | ENDM 211 | Set_Comp_Phase_B MACRO 212 | mov CMP0MX, #((Mux_B) SHL 4)+((Comp_Com) SHL 0); 213 | ENDM 214 | Set_Comp_Phase_C MACRO 215 | mov CMP0MX, #((Mux_C) SHL 4)+((Comp_Com) SHL 0); 216 | ENDM 217 | Read_Comp_Out MACRO 218 | mov A, CMP0CN0 ; Read comparator output 219 | ENDM 220 | 221 | 222 | 223 | ;********************* 224 | ; PORT 2 definitions * 225 | ;********************* 226 | DebugPin EQU 0 ;o 227 | 228 | P2_PUSHPULL EQU (1 SHL DebugPin) 229 | 230 | 231 | ;********************** 232 | ; MCU specific macros * 233 | ;********************** 234 | 235 | Initialize_Xbar MACRO 236 | mov XBR2, #40h ; Xbar enabled 237 | mov XBR1, #02h ; CEX0 and CEX1 routed to pins 238 | ENDM 239 | 240 | Initialize_Comparator MACRO 241 | mov CMP0CN0, #80h ; Comparator enabled, no hysteresis 242 | mov CMP0MD, #00h ; Comparator response time 100ns 243 | ENDM 244 | Initialize_Adc MACRO 245 | mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias 246 | IF MCU_48MHZ == 0 247 | mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1 248 | ELSE 249 | mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1 250 | ENDIF 251 | mov ADC0MX, #10h ; Select temp sensor input 252 | mov ADC0CN0, #80h ; ADC enabled 253 | mov ADC0CN1, #01h ; Common mode buffer enabled 254 | ENDM 255 | Start_Adc MACRO 256 | mov ADC0CN0, #90h ; ADC start 257 | ENDM 258 | Read_Adc_Result MACRO 259 | mov Temp1, ADC0L 260 | mov Temp2, ADC0H 261 | ENDM 262 | Stop_Adc MACRO 263 | ENDM 264 | Set_RPM_Out MACRO 265 | ENDM 266 | Clear_RPM_Out MACRO 267 | ENDM 268 | Set_LED_0 MACRO 269 | ENDM 270 | Clear_LED_0 MACRO 271 | ENDM 272 | Set_LED_1 MACRO 273 | ENDM 274 | Clear_LED_1 MACRO 275 | ENDM 276 | Set_LED_2 MACRO 277 | ENDM 278 | Clear_LED_2 MACRO 279 | ENDM 280 | Set_LED_3 MACRO 281 | ENDM 282 | Clear_LED_3 MACRO 283 | ENDM 284 | --------------------------------------------------------------------------------