├── README.md ├── Vit_b213 ├── .synopsys_dc.setup ├── b213_build.script ├── b213_synth.script ├── chip │ ├── out │ │ ├── .chiptmp │ │ │ ├── bVITERBI_213.bgn │ │ │ ├── bVITERBI_213.bit │ │ │ ├── bVITERBI_213.bld │ │ │ ├── bVITERBI_213.dly │ │ │ ├── bVITERBI_213.msk │ │ │ ├── bVITERBI_213.ncd │ │ │ ├── bVITERBI_213.ngd │ │ │ ├── bVITERBI_213.pad │ │ │ ├── bVITERBI_213.par │ │ │ ├── bVITERBI_213.pcf │ │ │ ├── bVITERBI_213.rbt │ │ │ ├── bVITERBI_213.twr │ │ │ ├── bVITERBI_213.xpi │ │ │ ├── bVITERBI_213_jtag.bgn │ │ │ ├── bVITERBI_213_jtag.bit │ │ │ ├── bVITERBI_213_m.mrp │ │ │ ├── bVITERBI_213_m.ncd │ │ │ ├── bVITERBI_213_m.ngm │ │ │ ├── build_log │ │ │ ├── mail_log │ │ │ └── ngo │ │ │ │ ├── bVITERBI_213.ngo │ │ │ │ └── netlist.lst │ │ ├── bVITERBI_213.bld │ │ ├── bVITERBI_213.ncd │ │ ├── bVITERBI_213.ngd │ │ ├── bVITERBI_213.pad │ │ ├── bVITERBI_213.par │ │ ├── bVITERBI_213.pcf │ │ ├── bVITERBI_213.twr │ │ ├── bVITERBI_213_jtag.bit │ │ ├── bVITERBI_213_m.mrp │ │ ├── build_log │ │ └── mail_log │ └── scr │ │ ├── bVITERBI_213.ucf.old │ │ ├── bVITERBI_213_ngdbuild.nav │ │ └── make_chip ├── src │ ├── VIT_ENC.v │ ├── bACSU_213.v │ ├── bACS_213.v │ ├── bBMU_213.v │ ├── bCONTROL_213.v │ ├── bCONTROL_213.v~ │ ├── bSYNCERR_213.v │ ├── bTBDECISION_213.v │ ├── bVITERBI_213.v │ ├── lse.wrk │ ├── nWaveLog │ │ ├── nWave.cmd │ │ └── turbo.log │ ├── params_b213.inc.v │ ├── sig.rc │ ├── sim_b213.script │ ├── tb_b213.v │ ├── tb_b213.v~ │ ├── verilog.fsdb │ ├── verilog.log │ └── vreader.log └── syn │ ├── out │ ├── bVITERBI_213.edf │ ├── bVITERBI_213.v │ ├── bVITERBI_213_log │ ├── bVITERBI_213_proj │ │ ├── bVITERBI_213_proj.exp │ │ ├── chips │ │ │ ├── bVITERBI_213_syn-Optimized │ │ │ │ ├── bVITERBI_213_syn-Optimized.cst │ │ │ │ ├── bVITERBI_213_syn-Optimized.rpt │ │ │ │ └── bVITERBI_213_syn-Optimized.ws │ │ │ └── bVITERBI_213_syn │ │ │ │ ├── bVITERBI_213_syn.cst │ │ │ │ ├── bVITERBI_213_syn.rpt │ │ │ │ └── bVITERBI_213_syn.ws │ │ ├── files │ │ │ ├── L0.rpt │ │ │ ├── L1.rpt │ │ │ ├── L2.rpt │ │ │ ├── L3.rpt │ │ │ ├── L4.rpt │ │ │ ├── L5.rpt │ │ │ └── L6.rpt │ │ └── workdirs │ │ │ └── WORK │ │ │ ├── Anal.info │ │ │ ├── Anal.out │ │ │ ├── BACSU_213.mra │ │ │ ├── BACS_213.mra │ │ │ ├── BBMU_213.mra │ │ │ ├── BCONTROL_213.mra │ │ │ ├── BSYNCERR_213.mra │ │ │ ├── BTBDECISION_213.mra │ │ │ ├── BVITERBI_213.mra │ │ │ ├── bACSU_213%verilog.syn │ │ │ ├── bACSU_213%verilog__verilog.syn │ │ │ ├── bACSU_213.hnl │ │ │ ├── bACSU_213.out │ │ │ ├── bACSU_213.sts │ │ │ ├── bACS_213%verilog.syn │ │ │ ├── bACS_213%verilog__verilog.syn │ │ │ ├── bACS_213.hnl │ │ │ ├── bACS_213.out │ │ │ ├── bACS_213.sts │ │ │ ├── bBMU_213%verilog.syn │ │ │ ├── bBMU_213%verilog__verilog.syn │ │ │ ├── bBMU_213.hnl │ │ │ ├── bBMU_213.out │ │ │ ├── bBMU_213.sts │ │ │ ├── bCONTROL_213%verilog.syn │ │ │ ├── bCONTROL_213%verilog__verilog.syn │ │ │ ├── bCONTROL_213.hnl │ │ │ ├── bCONTROL_213.out │ │ │ ├── bCONTROL_213.sts │ │ │ ├── bSYNCERR_213%verilog.syn │ │ │ ├── bSYNCERR_213%verilog__verilog.syn │ │ │ ├── bSYNCERR_213.hnl │ │ │ ├── bSYNCERR_213.out │ │ │ ├── bSYNCERR_213.sts │ │ │ ├── bTBDECISION_213%verilog.syn │ │ │ ├── bTBDECISION_213%verilog__verilog.syn │ │ │ ├── bTBDECISION_213.hnl │ │ │ ├── bTBDECISION_213.out │ │ │ ├── bTBDECISION_213.sts │ │ │ ├── bVITERBI_213%verilog.syn │ │ │ ├── bVITERBI_213%verilog__verilog.syn │ │ │ ├── bVITERBI_213.hnl │ │ │ ├── bVITERBI_213.out │ │ │ └── bVITERBI_213.sts │ ├── bVITERBI_213_syn-Optimized.fc2 │ └── fc2_shell_command.log │ └── scr │ ├── bVITERBI_213_constraint.fc2 │ ├── bVITERBI_213_script │ └── bVITERBI_213_script~ ├── Vit_b322 ├── .synopsys_dc.setup ├── DecoderInput.dat ├── ENCODER_322.v ├── b322_build.script ├── b322_synth.script ├── src │ ├── bACSU_322.v │ ├── bACS_322.v │ ├── bBMU_322.v │ ├── bCONTROL_322.v │ ├── bSYNCERR_322.v │ ├── bTBDECISION_322.v │ ├── bVITERBI_322.v │ ├── nWaveLog │ │ ├── nWave.cmd │ │ └── turbo.log │ ├── params_b322.inc │ ├── sig.rc │ ├── sim_b322.script │ ├── tb_b322.v │ ├── verilog.fsdb │ └── verilog.log └── syn │ └── scr │ └── trace_script ├── Vit_e213 ├── .synopsys_dc.setup ├── New_Vit_e213 │ ├── VIT_ENC.v │ ├── eACSU_213.v │ ├── eACS_213.v │ ├── eBMU_213.v │ ├── eCONTROL_213.v │ ├── eSYNCERR_213.v │ ├── eTBDECISION_213.v │ ├── eVITERBI_213.v │ ├── nWaveLog │ │ ├── nWave.cmd │ │ └── turbo.log │ ├── params_e213.inc.v │ ├── sig.rc │ ├── sim_e213.script │ ├── tb_e213.v │ ├── testvectors_213.txt │ ├── verilog.fsdb │ └── verilog.log ├── VIT_ENC.v ├── chip │ ├── out │ │ ├── .chiptmp │ │ │ ├── build_log │ │ │ ├── eVITERBI_213.bgn │ │ │ ├── eVITERBI_213.bit │ │ │ ├── eVITERBI_213.bld │ │ │ ├── eVITERBI_213.dly │ │ │ ├── eVITERBI_213.msk │ │ │ ├── eVITERBI_213.ncd │ │ │ ├── eVITERBI_213.ngd │ │ │ ├── eVITERBI_213.pad │ │ │ ├── eVITERBI_213.par │ │ │ ├── eVITERBI_213.pcf │ │ │ ├── eVITERBI_213.rbt │ │ │ ├── eVITERBI_213.twr │ │ │ ├── eVITERBI_213.xpi │ │ │ ├── eVITERBI_213_jtag.bgn │ │ │ ├── eVITERBI_213_jtag.bit │ │ │ ├── eVITERBI_213_m.mrp │ │ │ ├── eVITERBI_213_m.ncd │ │ │ ├── eVITERBI_213_m.ngm │ │ │ ├── mail_log │ │ │ └── ngo │ │ │ │ ├── eVITERBI_213.ngo │ │ │ │ └── netlist.lst │ │ ├── build_log │ │ ├── eVITERBI_213.bld │ │ ├── eVITERBI_213.ncd │ │ ├── eVITERBI_213.ngd │ │ ├── eVITERBI_213.pad │ │ ├── eVITERBI_213.par │ │ ├── eVITERBI_213.pcf │ │ ├── eVITERBI_213.twr │ │ ├── eVITERBI_213_jtag.bit │ │ ├── eVITERBI_213_m.mrp │ │ └── mail_log │ └── scr │ │ ├── eVITERBI_213_ngdbuild.nav │ │ └── make_chip ├── command.log ├── e213_build.script ├── e213_synth.script ├── eACSU_213.v ├── eACS_213.v ├── eBMU_213.v ├── eCONTROL_213.v ├── eCONTROL_213.v.$$$ ├── eSYNCERR_213.v ├── eTBDECISION_213.v ├── eVITERBI_213.bld ├── eVITERBI_213.db ├── eVITERBI_213.mdf ├── eVITERBI_213.mrp ├── eVITERBI_213.ncd ├── eVITERBI_213.ngd ├── eVITERBI_213.ngm ├── eVITERBI_213.ngo ├── eVITERBI_213.pcf ├── eVITERBI_213.sedif ├── eVITERBI_213.v ├── eVITERBI_213_ngdbuild.nav ├── eVITERBI_r_213.dly ├── eVITERBI_r_213.ncd ├── eVITERBI_r_213.pad ├── eVITERBI_r_213.par ├── eVITERBI_r_213.xpi ├── netlist.lst ├── params_e213.inc ├── sig.rc ├── sim_e213.script ├── src │ ├── VIT_ENC.v │ ├── eACSU_213.v │ ├── eACS_213.v │ ├── eBMU_213.v │ ├── eCONTROL_213.v │ ├── eCONTROL_213.v~ │ ├── eSYNCERR_213.v │ ├── eTBDECISION_213.v │ ├── eVITERBI_213.v │ ├── lse.wrk │ ├── nWaveLog │ │ ├── nWave.cmd │ │ └── turbo.log │ ├── params_e213.inc.v │ ├── params_e213.inc.v~ │ ├── sig.rc │ ├── sim_e213.script │ ├── tb_e213.v │ ├── tb_e213.v~ │ ├── verilog.fsdb │ ├── verilog.log │ └── vreader.log ├── syn │ ├── out │ │ ├── eVITERBI_213.edf │ │ ├── eVITERBI_213.v │ │ ├── eVITERBI_213_log │ │ ├── eVITERBI_213_proj │ │ │ ├── chips │ │ │ │ ├── eVITERBI_213_syn-Optimized │ │ │ │ │ ├── eVITERBI_213_syn-Optimized.cst │ │ │ │ │ ├── eVITERBI_213_syn-Optimized.rpt │ │ │ │ │ └── eVITERBI_213_syn-Optimized.ws │ │ │ │ └── eVITERBI_213_syn │ │ │ │ │ ├── eVITERBI_213_syn.cst │ │ │ │ │ ├── eVITERBI_213_syn.rpt │ │ │ │ │ └── eVITERBI_213_syn.ws │ │ │ ├── eVITERBI_213_proj.exp │ │ │ ├── files │ │ │ │ ├── L0.rpt │ │ │ │ ├── L1.rpt │ │ │ │ ├── L2.rpt │ │ │ │ ├── L3.rpt │ │ │ │ ├── L4.rpt │ │ │ │ ├── L5.rpt │ │ │ │ └── L6.rpt │ │ │ └── workdirs │ │ │ │ └── WORK │ │ │ │ ├── Anal.info │ │ │ │ ├── Anal.out │ │ │ │ ├── EACSU_213.mra │ │ │ │ ├── EACS_213.mra │ │ │ │ ├── EBMU_213.mra │ │ │ │ ├── ECONTROL_213.mra │ │ │ │ ├── ESYNCERR_213.mra │ │ │ │ ├── ETBDECISION_213.mra │ │ │ │ ├── EVITERBI_213.mra │ │ │ │ ├── eACSU_213%verilog.syn │ │ │ │ ├── eACSU_213%verilog__verilog.syn │ │ │ │ ├── eACSU_213.hnl │ │ │ │ ├── eACSU_213.out │ │ │ │ ├── eACSU_213.sts │ │ │ │ ├── eACS_213%verilog.syn │ │ │ │ ├── eACS_213%verilog__verilog.syn │ │ │ │ ├── eACS_213.hnl │ │ │ │ ├── eACS_213.out │ │ │ │ ├── eACS_213.sts │ │ │ │ ├── eBMU_213%verilog.syn │ │ │ │ ├── eBMU_213%verilog__verilog.syn │ │ │ │ ├── eBMU_213.hnl │ │ │ │ ├── eBMU_213.out │ │ │ │ ├── eBMU_213.sts │ │ │ │ ├── eCONTROL_213%verilog.syn │ │ │ │ ├── eCONTROL_213%verilog__verilog.syn │ │ │ │ ├── eCONTROL_213.hnl │ │ │ │ ├── eCONTROL_213.out │ │ │ │ ├── eCONTROL_213.sts │ │ │ │ ├── eSYNCERR_213%verilog.syn │ │ │ │ ├── eSYNCERR_213%verilog__verilog.syn │ │ │ │ ├── eSYNCERR_213.hnl │ │ │ │ ├── eSYNCERR_213.out │ │ │ │ ├── eSYNCERR_213.sts │ │ │ │ ├── eTBDECISION_213%verilog.syn │ │ │ │ ├── eTBDECISION_213%verilog__verilog.syn │ │ │ │ ├── eTBDECISION_213.hnl │ │ │ │ ├── eTBDECISION_213.out │ │ │ │ ├── eTBDECISION_213.sts │ │ │ │ ├── eVITERBI_213%verilog.syn │ │ │ │ ├── eVITERBI_213%verilog__verilog.syn │ │ │ │ ├── eVITERBI_213.hnl │ │ │ │ ├── eVITERBI_213.out │ │ │ │ └── eVITERBI_213.sts │ │ ├── eVITERBI_213_syn-Optimized.fc2 │ │ └── fc2_shell_command.log │ └── scr │ │ ├── eVITERBI_213_constraint.fc2 │ │ ├── eVITERBI_213_script │ │ └── eVITERBI_213_script~ ├── tb_e213.v ├── testvectors_213.txt ├── verilog.fsdb ├── verilog.key └── verilog.log ├── Vit_e322 ├── .synopsys_dc.setup ├── src │ ├── eACSU_322.v │ ├── eACS_322.v │ ├── eBMU_322.v │ ├── eCONTROL_322.v │ ├── eSYNCERR_322.v │ ├── eTBDECISION_322.v │ ├── eVITERBI_322.v │ ├── nWaveLog │ │ ├── nWave.cmd │ │ └── turbo.log │ ├── params_e322.inc │ ├── sig.rc │ ├── sim_e322.script │ ├── tb_e322.v │ ├── verilog.fsdb │ └── verilog.log └── syn │ └── scr │ └── trace_script └── docs ├── FPGA Based Storage Efficient Viterbi Decoders.doc ├── FPGA Based Storage Efficient Viterbi Decoders.pdf ├── MastersThesis.doc ├── MastersThesis.pdf └── trellis.png /README.md: -------------------------------------------------------------------------------- 1 | # **Verilog/FPGA Efficient Viterbi Decoding Algorithm**. 2 | 3 | ## Overview 4 | The Viterbi algorithm is renowned as a maximum likelihood (ML) decoding technique for convolutional codes. The path memory unit in an (n,k,m) Viterbi Decoder is responsible for keeping track of the information bits associated with the surviving paths designated by the path metric unit. Viterbi decoders and binary convolutional codes are denoted by a three-tuple (n, k, m), where: 5 | - n output bits are generated whenever k input bits are received. 6 | - k is the number of input sequences (and hence, the encoder consists of k shift registers). 7 | - m designates the number of previous k-bit input blocks that must be memorized in the encoder. 8 | 9 | ## Trellis Diagram 10 | A trellis diagram is typically used to visualize how the Viterbi Algorithm make Maximum Likelihood (ML) decoding decisions. An example trellis with the final ML path is shown below 11 | 12 | ![Alt text](docs/trellis.png "Viterbi Trellis Diagram with ML Path hightligted in red") 13 | 14 | ## Novel Path Memory Savings Technique 15 | Viterbi decoders are typically FPGA/ASIC based and therefore have a upper bound on the size of the path memory. A novel approach to achieving path memory savings is proposed for Viterbi Decoders. A number of traceback Viterbi decoders using this path memory were successfully developed It is shown that Viterbi decoders using this storage efficient path memory unit require a smaller chip area and achieves a faster decoding time without loss of decoding performance. A Viterbi decoder utilizing this novel path memory achieves savings of 20% in storage for (n,1,m) codes, and <=20% for general (n,k,m) codes without loss of decoding performance. There is also a similar increase decoding performance with the novel path memory. 16 | 17 | |Efficient Viterbi Decoder Architecture Traceback Procedure| 18 | |---| 19 | |1. Initialize Data Structures| 20 | |1.1. Initialize the trellis stage pointer to zero. Initialize the path memory write pointer to zero. Initialize the traceback pointer to zero. Initialize the decoded symbol counter to zero. | 21 | |1.2. Initialize the path metric for the known initial state to zero, with the remaining 2M –1 path metrics to their maximum value. Go to step 2.| 22 | |---| 23 | |2. Compute Path Metrics and Survivors| 24 | |2.1. Increment the trellis stage pointer, and the path memory pointer.| 25 | |2.2. For every trellis node, compute 2k path metrics by summing the path metrics from nodes at the previous stage to the corresponding branch metrics computed at the present stage. | 26 | |2.3. Compare the 2k paths and select the path with the minimum path metric as the surviving path, all other incoming paths to the trellis node are no longer considered. If there is a tie between path metrics, the algorithm selects one path.| 27 | 1.1. Store the path metric. Update the surviving path by shifting in the surviving backward label to the left hand side of the path memory register where the surviving path currently terminates.| 28 | |2.4. If the path memory write pointer is < T then go to step 2.1, else if the path memory write pointer = T go to step 3 | 29 | |---| 30 | |3. Traceback and Output Decision 31 | |3.1. Set the traceback pointer equal to T. Determine the traceback start state number as the state that corresponds to the minimum path metric. | 32 | |3.2. The state number and the traceback pointer are combined into a row-column address used to index path memory. Use this address to read a backward label from path memory. A predecessor state on the surviving path is then determined by use of the traceback mapping function. Decrement the traceback pointer. If the traceback pointer >1 repeat step 3.2, else go to step 3.3.| 33 | |3.3. Produce a decoded symbol.| 34 | |3.3.1. Category 1 - A decoder decision is made for one symbol by selecting the rightmost elements of the traceback mapping register. | 35 | |3.3.2. Category 2 - A decoder decision is made for one symbol by selecting a combination of specific elements from the backward label read from path memory and the rightmost elements of the traceback mapping register4.| 36 | |3.4. Increment the decoded symbol counter. If the decoded symbol count < N, go to step 2.1, else finish.| 37 | 38 | -------------------------------------------------------------------------------- /Vit_b213/.synopsys_dc.setup: -------------------------------------------------------------------------------- 1 | /* =================================================== */ 2 | /* Template .synopsys_dc.setup file for Xilinx designs */ 3 | /* For use with Synopsys FPGA Compiler. */ 4 | /* =================================================== */ 5 | 6 | /* ================================================= */ 7 | /* The Synopsys search path should be set to point */ 8 | /* to the directories that contain the various */ 9 | /* synthesis libraries used by FPGA Compiler during */ 10 | /* synthesis. */ 11 | /* ================================================= */ 12 | 13 | XilinxInstall = get_unix_variable(XILINX); 14 | SynopsysInstall = get_unix_variable(SYNOPSYS); 15 | 16 | search_path = { . \ 17 | XilinxInstall + /synopsys/libraries/syn \ 18 | SynopsysInstall + /libraries/syn } 19 | 20 | /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ 21 | /* Ensure that your UNIX environment */ 22 | /* includes the two environment var- */ 23 | /* iables: $XILINX (points to the */ 24 | /* Xilinx installation directory) and*/ 25 | /* $SYNOPSYS (points to the Synopsys */ 26 | /* installation directory.) */ 27 | /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ 28 | 29 | /* ================================================= */ 30 | /* Define a work library in the current project dir */ 31 | /* to hold temporary files and keep the project area */ 32 | /* uncluttered. Note: You must create a subdirectory */ 33 | /* in your project directory called WORK. */ 34 | /* ================================================= */ 35 | 36 | 37 | define_design_lib WORK -path ./WORK 38 | 39 | 40 | bus_extraction_style = "%s<%d:%d>" 41 | bus_naming_style = "%s<%d>" 42 | bus_dimension_separator_style = "><" 43 | 44 | edifin_lib_logic_1_symbol = "VCC" 45 | edifin_lib_logic_0_symbol = "GND" 46 | edifout_ground_name = "GND" 47 | edifout_ground_pin_name = "G" 48 | edifout_power_name = "VCC" 49 | edifout_power_pin_name = "P" 50 | edifout_netlist_only = "true" 51 | edifout_no_array = "true" 52 | edifout_power_and_ground_representation = "cell" 53 | edifout_write_properties_list = {"CLK1X_DUTY" "INIT_00" "INIT_01" "INIT_02" "INIT_03" \ 54 | "INIT_04" "INIT_05" "INIT_06" "INIT_07" "INIT_08" "INIT_09" "INIT_0A" "INIT_0B" "INIT_0C" \ 55 | "INIT_0D" "INIT_0E" "INIT_0F" "INIT" "CLKDV_DIVIDE" "IOB" "EQN" "lut_function"} 56 | 57 | /* ================================================= */ 58 | /* Set the link, target and synthetic library */ 59 | /* variables. Use synlibs (with the -dc switch) to */ 60 | /* determine the link and target library settings. */ 61 | /* You may like to copy this file to your project */ 62 | /* directory, rename it ".synopsys_dc.setup" and */ 63 | /* append the output of synlibs. For example: */ 64 | /* synlibs xfpga_virtex-3 >> .synopsys_dc.setup */ 65 | /* ================================================= */ 66 | 67 | 68 | 69 | /*link_library = {xfpga_virtex-5.db xdw_virtex.sldb}*/ 70 | /*target_library = {xfpga_virtex-5.db }*/ 71 | /*symbol_library = {virtex.sdb}*/ 72 | /*define_design_lib xdw_virtex -path XilinxInstall + /synopsys/libraries/dw/lib/virtex*/ 73 | /*synthetic_library = {xdw_virtex.sldb standard.sldb}*/ 74 | 75 | 76 | link_library = {xprim_4028xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db xdw_4000xla.sldb} 77 | target_library = {xprim_4028xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db} 78 | define_design_lib xdw_4000xla -path XilinxInstall + /synopsys/libraries/dw/lib/xc4000xla 79 | symbol_library = {xc4000ex.sdb} 80 | synthetic_library = {xdw_4000xla.sldb standard.sldb} 81 | 82 | 83 | 84 | /*link_library = {xprim_4013xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db xdw_4000xla.sldb}*/ 85 | /*target_library = {xprim_4013xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db}*/ 86 | /*define_design_lib xdw_4000xla -path XilinxInstall + /synopsys/libraries/dw/lib/xc4000xla*/ 87 | /*symbol_library = {xc4000ex.sdb}*/ 88 | /*synthetic_library = {xdw_4000xla.sldb standard.sldb}*/ 89 | 90 | -------------------------------------------------------------------------------- /Vit_b213/b213_build.script: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | ngdbuild -p 4028XLABG256-09 bVITERBI_213.sedif 3 | map -oe high bVITERBI_213.ngd 4 | par -c 1 -d 1 bVITERBI_213.ncd -w bVITERBI_r_213.ncd 5 | 6 | -------------------------------------------------------------------------------- /Vit_b213/b213_synth.script: -------------------------------------------------------------------------------- 1 | /* =======================================================*/ 2 | /* Synopsys Script */ 3 | /* (2,1,3) Backward Label Viterbi Decoder */ 4 | /* Targets a Xilinx XC4028XLA-09 BG256 */ 5 | /* =======================================================*/ 6 | 7 | 8 | TOP = bVITERBI_213 9 | edifout_design_name = bVITERBI_213 10 | designer = "John O'Shea" 11 | company = "EMC Corporation" 12 | part = "XC4028XLABG256-09" 13 | 14 | sh "rm -rf WORK; mkdir WORK" 15 | 16 | read -format verilog "bBMU_213.v" 17 | read -format verilog "bACS_213.v" 18 | read -format verilog "bACSU_213.v" 19 | read -format verilog "bSYNCERR_213.v" 20 | read -format verilog "bTBDECISION_213.v" 21 | read -format verilog "bCONTROL_213.v" 22 | read -format verilog "bVITERBI_213.v" 23 | 24 | set_operating_conditions -library "xprim_4028xla-09" "WCCOM" 25 | current_design bVITERBI_213 26 | uniquify 27 | remove_constraint -all 28 | 29 | create_clock -name "clock" -period 50 {"clock"} 30 | set_input_delay 5.0 -clock clock all_inputs() - clock 31 | set_output_delay 5.0 -clock clock all_outputs() 32 | set_max_delay 100 -to find(port,Dx) 33 | 34 | 35 | set_port_is_pad "*" 36 | set_pad_type -no_clock {"clock"} 37 | set_pad_type -exact BUFGP_F{"clock"} 38 | set_pad_type -slewrate HIGH all_outputs() 39 | insert_pads 40 | 41 | compile -map_effort high 42 | 43 | set_attribute bVITERBI_213 "part" -type string part 44 | 45 | ungroup -all -flatten 46 | 47 | write -format edif -hierarchy -output bVITERBI_213.sedif 48 | 49 | write -format db -hierarchy -output bVITERBI_213.db 50 | 51 | exit 52 | 53 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213.bgn: -------------------------------------------------------------------------------- 1 | Release v3.3.07i - Bitgen D.26 2 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 3 | 4 | Loading design for application Bitgen from file 5 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ncd. 6 | 7 | Note: MYXILINX = "/hwapps/xilinx/2.1iV1000E-BG728" 8 | Any Xilinx data file(s) found in this area will override the equivalent file(s) 9 | in the XILINX area. 10 | 11 | "bVITERBI_213" is an NCD, version 2.35, device xcv50, package tq144, speed 12 | -4 13 | Loading device for application Bitgen from file 'v50.nph' in environment 14 | /hwapps/xilinx/3.3isp7. 15 | Opened constraints file 16 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.pcf. 17 | 18 | Sat Mar 24 18:49:00 2001 19 | 20 | bitgen -b -m -d -w /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ncd /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.rbt /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.pcf 21 | 22 | Creating bit map... 23 | Saving bit stream in 24 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.bit". 25 | Saving bit stream in 26 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.rbt". 27 | Creating bit mask... 28 | Saving mask bit stream in 29 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.msk". 30 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/.chiptmp/bVITERBI_213.bit -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213.bld: -------------------------------------------------------------------------------- 1 | Release v3.3.07i - ngdbuild D.26 2 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: ngdbuild -dd 5 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/ngo -nt timestamp -p 6 | V50TQ144-4 /emc/joshea/JOS/Verilog/Vit_b213/syn/out/bVITERBI_213.edf 7 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ngd 8 | 9 | Launcher: Executing edif2ngd 10 | "/emc/joshea/JOS/Verilog/Vit_b213/syn/out/bVITERBI_213.edf" 11 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/ngo/bVITERBI_213.ngo" 12 | Release v3.3.07i - edif2ngd D.26 13 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 14 | 15 | Note: MYXILINX = "/hwapps/xilinx/2.1iV1000E-BG728" 16 | Any Xilinx data file(s) found in this area will override the equivalent file(s) 17 | in the XILINX area. 18 | 19 | Writing the design to 20 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/ngo/bVITERBI_213.ngo"... 21 | Reading NGO file 22 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/ngo/bVITERBI_213.ngo" ... 23 | Reading component libraries for design expansion... 24 | 25 | Checking timing specifications ... 26 | 27 | Checking expanded design ... 28 | 29 | NGDBUILD Design Results Summary: 30 | Number of errors: 0 31 | Number of warnings: 0 32 | 33 | Writing NGD file 34 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ngd" ... 35 | 36 | Writing NGDBUILD log file 37 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.bld"... 38 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213.msk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/.chiptmp/bVITERBI_213.msk -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ncd -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213.ngd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ngd -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213.pcf: -------------------------------------------------------------------------------- 1 | SCHEMATIC START ; 2 | // created by map version D.26 on Sat Mar 24 18:48:15 2001 3 | SCHEMATIC END ; 4 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=PLACED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213_jtag.bgn: -------------------------------------------------------------------------------- 1 | Release v3.3.07i - Bitgen D.26 2 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 3 | 4 | Loading design for application Bitgen from file 5 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ncd. 6 | 7 | Note: MYXILINX = "/hwapps/xilinx/2.1iV1000E-BG728" 8 | Any Xilinx data file(s) found in this area will override the equivalent file(s) 9 | in the XILINX area. 10 | 11 | "bVITERBI_213" is an NCD, version 2.35, device xcv50, package tq144, speed 12 | -4 13 | Loading device for application Bitgen from file 'v50.nph' in environment 14 | /hwapps/xilinx/3.3isp7. 15 | Opened constraints file 16 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.pcf. 17 | 18 | Sat Mar 24 18:49:11 2001 19 | 20 | bitgen -d -g startupclk:jtagclk -w /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ncd /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213_jtag.bit /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.pcf 21 | 22 | Creating bit map... 23 | Saving bit stream in 24 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213_jtag.bit". 25 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213_jtag.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/.chiptmp/bVITERBI_213_jtag.bit -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213_m.mrp: -------------------------------------------------------------------------------- 1 | 2 | Xilinx Mapping Report File for Design 'bVITERBI_213' 3 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 4 | 5 | Design Information 6 | ------------------ 7 | Command Line : map -u -p V50TQ144-4 -pr b -o 8 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213_m.ncd 9 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ngd 10 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.pcf 11 | Target Device : xv50 12 | Target Package : tq144 13 | Target Speed : -4 14 | Mapper Version : virtex -- D.26 15 | Mapped Date : Sat Mar 24 18:48:07 2001 16 | 17 | Design Summary 18 | -------------- 19 | Number of errors: 0 20 | Number of warnings: 6 21 | Number of Slices: 317 out of 768 41% 22 | Number of Slices containing 23 | unrelated logic: 0 out of 317 0% 24 | Number of Slice Flip Flops: 280 out of 1,536 18% 25 | Number of 4 input LUTs: 458 out of 1,536 29% 26 | Number of Tbufs: 1 out of 832 1% 27 | Total equivalent gate count for design: 5,042 28 | 29 | Table of Contents 30 | ----------------- 31 | Section 1 - Errors 32 | Section 2 - Warnings 33 | Section 3 - Design Attributes 34 | Section 4 - Removed Logic Summary 35 | Section 5 - Removed Logic 36 | Section 6 - Added Logic 37 | Section 7 - Expanded Logic 38 | Section 8 - Signal Cross-Reference 39 | Section 9 - Symbol Cross-Reference 40 | Section 10 - IOB Properties 41 | Section 11 - RPMs 42 | Section 12 - Guide Report 43 | Section 13 - Area Group Summary 44 | Section 14 - Modular Design Summary 45 | 46 | Section 1 - Errors 47 | ------------------ 48 | 49 | Section 2 - Warnings 50 | -------------------- 51 | WARNING:DesignRules:367 - Netcheck: Loadless. Net Dx<0> has no load. 52 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net clock has no source. 53 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net reset has no source. 54 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net Rx<1> has no source. 55 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net Rx<0> has no source. 56 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net seq_ready has no source. 57 | 58 | Section 3 - Design Attributes 59 | ----------------------------- 60 | 61 | Section 4 - Removed Logic Summary 62 | --------------------------------- 63 | 4 block(s) optimized away 64 | 65 | Section 5 - Removed Logic 66 | ------------------------- 67 | 68 | Optimized Block(s): 69 | TYPE BLOCK 70 | VCC U3/C1862 71 | GND U3/C1863 72 | GND U3/SE_1/C35 73 | FDC U3/SE_1/error_reg 74 | 75 | To enable printing of redundant blocks removed and signals merged, set the 76 | detailed map report option and rerun map. 77 | 78 | Section 6 - Added Logic 79 | ----------------------- 80 | 81 | Section 7 - Expanded Logic 82 | -------------------------- 83 | To enable this section, set the detailed map report option and rerun map. 84 | 85 | Section 8 - Signal Cross-Reference 86 | ---------------------------------- 87 | To enable this section, set the detailed map report option and rerun map. 88 | 89 | Section 9 - Symbol Cross-Reference 90 | ---------------------------------- 91 | To enable this section, set the detailed map report option and rerun map. 92 | 93 | Section 10 - IOB Properties 94 | --------------------------- 95 | 96 | Section 11 - RPMs 97 | ----------------- 98 | 99 | Section 12 - Guide Report 100 | ------------------------- 101 | Guide not run on this design. 102 | 103 | Section 13 - Area Group Summary 104 | ------------------------------- 105 | No area groups were found in this design. 106 | 107 | Section 14 - Modular Design Summary 108 | ----------------------------------- 109 | Modular Design not used for this design. 110 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213_m.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/.chiptmp/bVITERBI_213_m.ncd -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/bVITERBI_213_m.ngm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/.chiptmp/bVITERBI_213_m.ngm -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/ngo/bVITERBI_213.ngo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/.chiptmp/ngo/bVITERBI_213.ngo -------------------------------------------------------------------------------- /Vit_b213/chip/out/.chiptmp/ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | /emc/joshea/JOS/Verilog/Vit_b213/syn/out/bVITERBI_213.edf 985477398 2 | OK 3 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/bVITERBI_213.bld: -------------------------------------------------------------------------------- 1 | Release v3.3.07i - ngdbuild D.26 2 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: ngdbuild -dd 5 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/ngo -nt timestamp -p 6 | V50TQ144-4 /emc/joshea/JOS/Verilog/Vit_b213/syn/out/bVITERBI_213.edf 7 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ngd 8 | 9 | Launcher: Executing edif2ngd 10 | "/emc/joshea/JOS/Verilog/Vit_b213/syn/out/bVITERBI_213.edf" 11 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/ngo/bVITERBI_213.ngo" 12 | Release v3.3.07i - edif2ngd D.26 13 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 14 | 15 | Note: MYXILINX = "/hwapps/xilinx/2.1iV1000E-BG728" 16 | Any Xilinx data file(s) found in this area will override the equivalent file(s) 17 | in the XILINX area. 18 | 19 | Writing the design to 20 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/ngo/bVITERBI_213.ngo"... 21 | Reading NGO file 22 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/ngo/bVITERBI_213.ngo" ... 23 | Reading component libraries for design expansion... 24 | 25 | Checking timing specifications ... 26 | 27 | Checking expanded design ... 28 | 29 | NGDBUILD Design Results Summary: 30 | Number of errors: 0 31 | Number of warnings: 0 32 | 33 | Writing NGD file 34 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ngd" ... 35 | 36 | Writing NGDBUILD log file 37 | "/emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.bld"... 38 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/bVITERBI_213.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/bVITERBI_213.ncd -------------------------------------------------------------------------------- /Vit_b213/chip/out/bVITERBI_213.ngd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/bVITERBI_213.ngd -------------------------------------------------------------------------------- /Vit_b213/chip/out/bVITERBI_213.pcf: -------------------------------------------------------------------------------- 1 | SCHEMATIC START ; 2 | // created by map version D.26 on Sat Mar 24 18:48:15 2001 3 | SCHEMATIC END ; 4 | -------------------------------------------------------------------------------- /Vit_b213/chip/out/bVITERBI_213_jtag.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/chip/out/bVITERBI_213_jtag.bit -------------------------------------------------------------------------------- /Vit_b213/chip/out/bVITERBI_213_m.mrp: -------------------------------------------------------------------------------- 1 | 2 | Xilinx Mapping Report File for Design 'bVITERBI_213' 3 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 4 | 5 | Design Information 6 | ------------------ 7 | Command Line : map -u -p V50TQ144-4 -pr b -o 8 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213_m.ncd 9 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.ngd 10 | /emc/joshea/JOS/Verilog/Vit_b213/chip/out/.chiptmp/bVITERBI_213.pcf 11 | Target Device : xv50 12 | Target Package : tq144 13 | Target Speed : -4 14 | Mapper Version : virtex -- D.26 15 | Mapped Date : Sat Mar 24 18:48:07 2001 16 | 17 | Design Summary 18 | -------------- 19 | Number of errors: 0 20 | Number of warnings: 6 21 | Number of Slices: 317 out of 768 41% 22 | Number of Slices containing 23 | unrelated logic: 0 out of 317 0% 24 | Number of Slice Flip Flops: 280 out of 1,536 18% 25 | Number of 4 input LUTs: 458 out of 1,536 29% 26 | Number of Tbufs: 1 out of 832 1% 27 | Total equivalent gate count for design: 5,042 28 | 29 | Table of Contents 30 | ----------------- 31 | Section 1 - Errors 32 | Section 2 - Warnings 33 | Section 3 - Design Attributes 34 | Section 4 - Removed Logic Summary 35 | Section 5 - Removed Logic 36 | Section 6 - Added Logic 37 | Section 7 - Expanded Logic 38 | Section 8 - Signal Cross-Reference 39 | Section 9 - Symbol Cross-Reference 40 | Section 10 - IOB Properties 41 | Section 11 - RPMs 42 | Section 12 - Guide Report 43 | Section 13 - Area Group Summary 44 | Section 14 - Modular Design Summary 45 | 46 | Section 1 - Errors 47 | ------------------ 48 | 49 | Section 2 - Warnings 50 | -------------------- 51 | WARNING:DesignRules:367 - Netcheck: Loadless. Net Dx<0> has no load. 52 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net clock has no source. 53 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net reset has no source. 54 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net Rx<1> has no source. 55 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net Rx<0> has no source. 56 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net seq_ready has no source. 57 | 58 | Section 3 - Design Attributes 59 | ----------------------------- 60 | 61 | Section 4 - Removed Logic Summary 62 | --------------------------------- 63 | 4 block(s) optimized away 64 | 65 | Section 5 - Removed Logic 66 | ------------------------- 67 | 68 | Optimized Block(s): 69 | TYPE BLOCK 70 | VCC U3/C1862 71 | GND U3/C1863 72 | GND U3/SE_1/C35 73 | FDC U3/SE_1/error_reg 74 | 75 | To enable printing of redundant blocks removed and signals merged, set the 76 | detailed map report option and rerun map. 77 | 78 | Section 6 - Added Logic 79 | ----------------------- 80 | 81 | Section 7 - Expanded Logic 82 | -------------------------- 83 | To enable this section, set the detailed map report option and rerun map. 84 | 85 | Section 8 - Signal Cross-Reference 86 | ---------------------------------- 87 | To enable this section, set the detailed map report option and rerun map. 88 | 89 | Section 9 - Symbol Cross-Reference 90 | ---------------------------------- 91 | To enable this section, set the detailed map report option and rerun map. 92 | 93 | Section 10 - IOB Properties 94 | --------------------------- 95 | 96 | Section 11 - RPMs 97 | ----------------- 98 | 99 | Section 12 - Guide Report 100 | ------------------------- 101 | Guide not run on this design. 102 | 103 | Section 13 - Area Group Summary 104 | ------------------------------- 105 | No area groups were found in this design. 106 | 107 | Section 14 - Modular Design Summary 108 | ----------------------------------- 109 | Modular Design not used for this design. 110 | -------------------------------------------------------------------------------- /Vit_b213/chip/scr/bVITERBI_213.ucf.old: -------------------------------------------------------------------------------- 1 | 2 | NET "clock" TNM_NET = CLKGRP; 3 | 4 | TIMESPEC TS_PERIOD = PERIOD : CLKGRP : 20: HIGH : 10; 5 | 6 | NET "oe" TNM = "TN_OE"; 7 | 8 | TIMESPEC "TS_FFS_TO_OE" = FROM "FFS" TO "TN_OE" TS_PERIOD * 2; 9 | 10 | -------------------------------------------------------------------------------- /Vit_b213/chip/scr/bVITERBI_213_ngdbuild.nav: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /Vit_b213/src/VIT_ENC.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module VIT_ENC.v 3 | 4 | Implements a (2,1,3) convolutional encoder 5 | 6 | ============================================================*/ 7 | 8 | `timescale 1 ns/1 ns 9 | 10 | module VIT_ENC (Vx,Ux,tb_en,clock,reset); 11 | 12 | `include "params_b213.inc.v" 13 | 14 | output [`n-1:0] Vx; 15 | input [`k-1:0] Ux; 16 | input tb_en; 17 | input clock; 18 | input reset; 19 | 20 | reg [`m:0] encoder_reg; 21 | 22 | always @(posedge clock or posedge reset) 23 | begin 24 | if(reset) 25 | encoder_reg <= 4'b0; 26 | 27 | if (tb_en==1'b0) 28 | encoder_reg <= {Ux, encoder_reg[3:1]}; 29 | end 30 | 31 | assign Vx[1] = encoder_reg[3]^encoder_reg[1]^encoder_reg[0]; 32 | assign Vx[0] = encoder_reg[3]^encoder_reg[2]^encoder_reg[1]^encoder_reg[0]; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Vit_b213/src/bACS_213.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module bACS_213.v 3 | 4 | ACS Block for (2,1,3) backward label decoder 5 | 6 | ============================================================*/ 7 | 8 | `timescale 1 ns/1 ns 9 | 10 | module bACS_213 (acs_ppm_out, acs_Bx_out, 11 | acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb, 12 | ae, clock, reset); 13 | 14 | 15 | 16 | `include "params_b213.inc.v" 17 | 18 | output [`W-1:0] acs_ppm_out; 19 | output [`k-1:0] acs_Bx_out; 20 | 21 | input [`W-1:0] acs_ppm_ina; 22 | input [`W-1:0] acs_ppm_inb; 23 | input [1:0] HD_ina; 24 | input [1:0] HD_inb; 25 | input ae; 26 | input clock; 27 | input reset; 28 | 29 | 30 | reg [`W-1:0] acs_ppm_out; 31 | reg [`k-1:0] acs_Bx_out; 32 | 33 | reg [`W-1:0] suma; 34 | reg [`W-1:0] sumb; 35 | 36 | 37 | 38 | always @(posedge clock or posedge reset) 39 | begin 40 | if (reset) 41 | suma <=0; 42 | else 43 | begin 44 | if (ae && acs_ppm_ina==4'b1111) 45 | suma <= acs_ppm_ina; 46 | else if (ae) 47 | suma <= acs_ppm_ina + HD_ina; 48 | end 49 | end 50 | 51 | always @(posedge clock or posedge reset) 52 | begin 53 | if (reset) 54 | sumb <=0; 55 | else 56 | begin 57 | if (ae && acs_ppm_inb ==4'b1111) 58 | sumb <=acs_ppm_inb; 59 | else if (ae) 60 | sumb <= acs_ppm_inb + HD_inb; 61 | end 62 | end 63 | 64 | 65 | 66 | always @(suma or sumb) 67 | begin 68 | if (suma <=sumb && ae) 69 | begin 70 | acs_ppm_out =suma; 71 | acs_Bx_out =1'b0; //Select Upper Backward Path 72 | end 73 | else 74 | begin 75 | acs_ppm_out =sumb; 76 | acs_Bx_out =1'b1; //Select Lower Backward Path 77 | end 78 | end 79 | 80 | 81 | 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /Vit_b213/src/bBMU_213.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module bBMU_213.v 3 | 4 | Branch Metric Computation Unit for (2,1,3) backward label Viterbi Decoder. 5 | 6 | ===========================================================================*/ 7 | 8 | module bBMU_213(HD1, HD2, HD3, HD4, 9 | HD5, HD6, HD7, HD8, 10 | HD9, HD10, HD11, HD12, 11 | HD13, HD14, HD15, HD16, 12 | Rx, le, clock, reset 13 | ); 14 | 15 | `include "params_b213.inc.v" 16 | 17 | output [1:0] HD1; 18 | output [1:0] HD2; 19 | output [1:0] HD3; 20 | output [1:0] HD4; 21 | output [1:0] HD5; 22 | output [1:0] HD6; 23 | output [1:0] HD7; 24 | output [1:0] HD8; 25 | output [1:0] HD9; 26 | output [1:0] HD10; 27 | output [1:0] HD11; 28 | output [1:0] HD12; 29 | output [1:0] HD13; 30 | output [1:0] HD14; 31 | output [1:0] HD15; 32 | output [1:0] HD16; 33 | 34 | 35 | input [1:0] Rx; 36 | input le; 37 | input clock; 38 | input reset; 39 | 40 | reg [1:0] HD1; 41 | reg [1:0] HD2; 42 | reg [1:0] HD3; 43 | reg [1:0] HD4; 44 | reg [1:0] HD5; 45 | reg [1:0] HD6; 46 | reg [1:0] HD7; 47 | reg [1:0] HD8; 48 | reg [1:0] HD9; 49 | reg [1:0] HD10; 50 | reg [1:0] HD11; 51 | reg [1:0] HD12; 52 | reg [1:0] HD13; 53 | reg [1:0] HD14; 54 | reg [1:0] HD15; 55 | reg [1:0] HD16; 56 | 57 | 58 | 59 | always @(posedge clock or posedge reset) 60 | begin 61 | if(reset) 62 | begin 63 | HD1 <=0; HD2 <=0; HD3 <=0; HD4 <=0; 64 | HD5 <=0; HD6 <=0; HD7 <=0; HD8 <=0; 65 | HD9 <=0; HD10<=0; HD11<=0; HD12<=0; 66 | HD13<=0; HD14<=0; HD15<=0; HD16<=0; 67 | end 68 | else if (le) 69 | begin 70 | case (Rx)//synopsys full_case 71 | 72 | 2'b00: begin 73 | HD1 <=2'b00; HD2 <=2'b10; HD3 <=2'b01; HD4 <=2'b01; 74 | HD5 <=2'b10; HD6 <=2'b00; HD7 <=2'b01; HD8 <=2'b01; 75 | HD9 <=2'b10; HD10<=2'b00; HD11<=2'b01; HD12<=2'b01; 76 | HD13<=2'b00; HD14<=2'b10; HD15<=2'b01; HD16<=2'b01; 77 | end 78 | 79 | 2'b01: begin 80 | HD1 <=2'b01; HD2 <=2'b01; HD3 <=2'b00; HD4 <=2'b10; 81 | HD5 <=2'b01; HD6 <=2'b01; HD7 <=2'b10; HD8 <=2'b00; 82 | HD9 <=2'b01; HD10<=2'b01; HD11<=2'b10; HD12<=2'b00; 83 | HD13<=2'b01; HD14<=2'b01; HD15<=2'b00; HD16<=2'b10; 84 | end 85 | 86 | 2'b10: begin 87 | HD1 <=2'b01; HD2 <=2'b01; HD3 <=2'b10; HD4 <=2'b00; 88 | HD5 <=2'b01; HD6 <=2'b01; HD7 <=2'b00; HD8 <=2'b10; 89 | HD9 <=2'b01; HD10<=2'b01; HD11<=2'b00; HD12<=2'b10; 90 | HD13<=2'b01; HD14<=2'b01; HD15<=2'b10; HD16<=2'b00; 91 | end 92 | 93 | 2'b11: begin 94 | HD1 <=2'b10; HD2 <=2'b00; HD3 <=2'b01; HD4 <=2'b01; 95 | HD5 <=2'b00; HD6 <=2'b10; HD7 <=2'b01; HD8 <=2'b01; 96 | HD9 <=2'b00; HD10<=2'b10; HD11<=2'b01; HD12<=2'b01; 97 | HD13<=2'b10; HD14<=2'b00; HD15<=2'b01; HD16<=2'b01; 98 | end 99 | endcase // case(Rx) 100 | end 101 | end 102 | 103 | 104 | endmodule 105 | -------------------------------------------------------------------------------- /Vit_b213/src/bSYNCERR_213.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module bSYNCERR_213.v 3 | 4 | Out of Synch Error Detector for (2,1,3) Viterbi decoder. 5 | 6 | ===========================================================================*/ 7 | `timescale 1 ns/1 ns 8 | 9 | 10 | module bSYNCERR_213 (error, stage, we, metric, reset, clock 11 | ); 12 | 13 | 14 | output error; 15 | 16 | input [3:0] stage; 17 | input [2:0] metric; 18 | input we; 19 | input reset; 20 | input clock; 21 | reg error; 22 | 23 | 24 | always @(posedge clock or posedge reset) 25 | begin 26 | if (reset) 27 | error <=1'b0; 28 | else 29 | begin 30 | if (we && stage >=4'b0011 && metric >4'b1000) 31 | error <=1'b1; 32 | else 33 | error <=1'b0; 34 | end 35 | end 36 | 37 | 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /Vit_b213/src/bTBDECISION_213.v: -------------------------------------------------------------------------------- 1 | /*================================================================= 2 | module bTBDECISION_213.v 3 | 4 | Traceback Decision Unit for (2,1,3) decoder 5 | 6 | Determine pointer to initial state for traceback 7 | by finding the state with minimum accumulated metric 8 | ==================================================================*/ 9 | 10 | `timescale 1 ns/1 ns 11 | 12 | module bTBDECISION_213 (best_state, 13 | in0, in1, in2, in3, in4, in5, in6, in7); 14 | 15 | 16 | `include "params_b213.inc.v" 17 | 18 | output [`m-1:0] best_state; 19 | 20 | input [`W-1:0] in0; 21 | input [`W-1:0] in1; 22 | input [`W-1:0] in2; 23 | input [`W-1:0] in3; 24 | input [`W-1:0] in4; 25 | input [`W-1:0] in5; 26 | input [`W-1:0] in6; 27 | input [`W-1:0] in7; 28 | 29 | reg [`m-1:0] best_state; 30 | reg [`W-1:0] min_01; 31 | reg [`W-1:0] min_23; 32 | reg [`W-1:0] min_45; 33 | reg [`W-1:0] min_67; 34 | reg [`W-1:0] min_0123; 35 | reg [`W-1:0] min_4567; 36 | reg [`W-1:0] min_metric; 37 | 38 | 39 | 40 | always @(in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) 41 | begin 42 | if (in0 <=in1) 43 | min_01=in0; 44 | else 45 | min_01=in1; 46 | 47 | if (in2 <=in3) 48 | min_23=in2; 49 | else 50 | min_23=in3; 51 | 52 | if (in4 <=in5) 53 | min_45=in4; 54 | else 55 | min_45=in5; 56 | 57 | if (in6 <=in7) 58 | min_67=in6; 59 | else 60 | min_67=in7; 61 | 62 | if (min_01 <= min_23) 63 | min_0123 = min_01; 64 | else 65 | min_0123 = min_23; 66 | 67 | if (min_45 <= min_67) 68 | min_4567 = min_45; 69 | else 70 | min_4567 = min_67; 71 | 72 | if (min_0123 <= min_4567) 73 | min_metric = min_0123; 74 | else 75 | min_metric = min_4567; 76 | end 77 | 78 | 79 | always @ (in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 or min_metric) 80 | begin 81 | if (in0==min_metric) 82 | best_state = 3'b000; 83 | else if (in1==min_metric) 84 | best_state = 3'b001; 85 | else if (in2==min_metric) 86 | best_state = 3'b010; 87 | else if (in3==min_metric) 88 | best_state = 3'b011; 89 | else if (in4==min_metric) 90 | best_state = 3'b100; 91 | else if (in5==min_metric) 92 | best_state = 3'b101; 93 | else if (in6==min_metric) 94 | best_state = 3'b110; 95 | else 96 | best_state = 3'b111; 97 | end 98 | 99 | endmodule 100 | 101 | 102 | -------------------------------------------------------------------------------- /Vit_b213/src/lse.wrk: -------------------------------------------------------------------------------- 1 | FILE_TYPE = LOGIC_DIR; 2 | END. 3 | -------------------------------------------------------------------------------- /Vit_b213/src/nWaveLog/turbo.log: -------------------------------------------------------------------------------- 1 | au time=4350 memory (delta=6570512:7970816 total=6642296:8060928) 2 | -------------------------------------------------------------------------------- /Vit_b213/src/params_b213.inc.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | params_b213.inc 3 | 4 | Constant Definitions for use in a (2,1,3) backward label Viterbi Decoder 5 | 6 | ===========================================================================*/ 7 | 8 | `define CLOCK_PERIOD 40 9 | `define BLOCK_LEN 20 10 | `define NUM_VECTORS 10 11 | 12 | `define N 20 13 | `define W 4 14 | `define T 15 15 | `define n 2 16 | `define k 1 17 | `define m 3 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /Vit_b213/src/sim_b213.script: -------------------------------------------------------------------------------- 1 | tb_b213.v 2 | bBMU_213.v 3 | bACS_213.v 4 | bACSU_213.v 5 | bTBDECISION_213.v 6 | bSYNCERR_213.v 7 | bCONTROL_213.v 8 | bVITERBI_213.v 9 | +libext+.v+.V 10 | -y /hwapps/xilinx/M.1.5.i/verilog/src/UNI4000X 11 | -------------------------------------------------------------------------------- /Vit_b213/src/verilog.fsdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/src/verilog.fsdb -------------------------------------------------------------------------------- /Vit_b213/src/vreader.log: -------------------------------------------------------------------------------- 1 | Host command: /hwapps/pe13.6/tools/bin/vreadern 2 | Command arguments: 3 | /emc/joshea/JOS/Verilog/Vit_b213/src/bCONTROL_213.v 4 | 5 | 6 | vreadern version 4.3 Tue Feb 1 23:52:00 PST 1994 (smcc11) 7 | Mar 24, 2001 17:40:04 8 | 9 | * Copyright Cadence Design Systems, Inc. 1991. * 10 | * All Rights Reserved. Licensed Software. * 11 | * Confidential and proprietary information which is the * 12 | * property of Cadence Design Systems, Inc. * 13 | 14 | Analyzing source file "/emc/joshea/JOS/Verilog/Vit_b213/src/bCONTROL_213.v" 15 | Analyzing included file "params_b213.inc.v" 16 | Continuing analyzing of source file "/emc/joshea/JOS/Verilog/Vit_b213/src/bCONTROL_213.v" 17 | 18 | Warning! Ignoring bit range on parameter declaration [Verilog Reader DS 19 | Builder-IROPD] 20 | "/emc/joshea/JOS/Verilog/Vit_b213/src/bCONTROL_21 21 | 3.v", 101: 22 | 300 cpu secs to build 23 | 1 warning 24 | 25 | End of vreadern version 4.3 Tue Feb 1 23:52:00 PST 1994 (smcc11) 26 | Mar 24, 2001 17:40:04 27 | 28 | -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/bVITERBI_213_proj.exp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/bVITERBI_213_proj.exp -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/chips/bVITERBI_213_syn-Optimized/bVITERBI_213_syn-Optimized.cst: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bACS_213.hnl -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bACS_213.out: -------------------------------------------------------------------------------- 1 | Warning: Variable 'ae' is being read 2 | in routine bACS_213 line 68 in file '/emc/joshea/JOS/Verilog/Vit_b213/src/bACS_213.v', 3 | but does not occur in the timing control of the block which begins 4 | there. (HDL-180) 5 | 6 | Inferred memory devices in process 7 | in routine bACS_213 line 40 in file 8 | '/emc/joshea/JOS/Verilog/Vit_b213/src/bACS_213.v'. 9 | =============================================================================== 10 | | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | 11 | =============================================================================== 12 | | suma_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | 13 | =============================================================================== 14 | 15 | suma_reg (width 4) 16 | ------------------ 17 | Async-reset: reset 18 | 19 | 20 | 21 | Inferred memory devices in process 22 | in routine bACS_213 line 53 in file 23 | '/emc/joshea/JOS/Verilog/Vit_b213/src/bACS_213.v'. 24 | =============================================================================== 25 | | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | 26 | =============================================================================== 27 | | sumb_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | 28 | =============================================================================== 29 | 30 | sumb_reg (width 4) 31 | ------------------ 32 | Async-reset: reset 33 | 34 | 35 | Writing to hnl file './bVITERBI_213_proj/workdirs/WORK/bACS_213.hnl' 36 | -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bACS_213.sts: -------------------------------------------------------------------------------- 1 | 3 -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bBMU_213%verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bBMU_213%verilog.syn -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bBMU_213%verilog__verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bBMU_213%verilog__verilog.syn -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bBMU_213.hnl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bBMU_213.hnl -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bBMU_213.out: -------------------------------------------------------------------------------- 1 | 2 | Statistics for case statements in always block at line 61 in file 3 | '/emc/joshea/JOS/Verilog/Vit_b213/src/bBMU_213.v' 4 | =============================================== 5 | | Line | full/ parallel | 6 | =============================================== 7 | | 74 | user/auto | 8 | =============================================== 9 | 10 | Inferred memory devices in process 11 | in routine bBMU_213 line 61 in file 12 | '/emc/joshea/JOS/Verilog/Vit_b213/src/bBMU_213.v'. 13 | =============================================================================== 14 | | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | 15 | =============================================================================== 16 | | HD1_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 17 | | HD2_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 18 | | HD3_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 19 | | HD4_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 20 | | HD5_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 21 | | HD6_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 22 | | HD7_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 23 | | HD8_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 24 | | HD9_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 25 | | HD10_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 26 | | HD11_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 27 | | HD12_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 28 | | HD13_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 29 | | HD14_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 30 | | HD15_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 31 | | HD16_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 32 | =============================================================================== 33 | 34 | HD1_reg (width 2) 35 | ----------------- 36 | Async-reset: reset 37 | 38 | 39 | HD2_reg (width 2) 40 | ----------------- 41 | Async-reset: reset 42 | 43 | 44 | HD3_reg (width 2) 45 | ----------------- 46 | Async-reset: reset 47 | 48 | 49 | HD4_reg (width 2) 50 | ----------------- 51 | Async-reset: reset 52 | 53 | 54 | HD5_reg (width 2) 55 | ----------------- 56 | Async-reset: reset 57 | 58 | 59 | HD6_reg (width 2) 60 | ----------------- 61 | Async-reset: reset 62 | 63 | 64 | HD7_reg (width 2) 65 | ----------------- 66 | Async-reset: reset 67 | 68 | 69 | HD8_reg (width 2) 70 | ----------------- 71 | Async-reset: reset 72 | 73 | 74 | HD9_reg (width 2) 75 | ----------------- 76 | Async-reset: reset 77 | 78 | 79 | HD10_reg (width 2) 80 | ------------------ 81 | Async-reset: reset 82 | 83 | 84 | HD11_reg (width 2) 85 | ------------------ 86 | Async-reset: reset 87 | 88 | 89 | HD12_reg (width 2) 90 | ------------------ 91 | Async-reset: reset 92 | 93 | 94 | HD13_reg (width 2) 95 | ------------------ 96 | Async-reset: reset 97 | 98 | 99 | HD14_reg (width 2) 100 | ------------------ 101 | Async-reset: reset 102 | 103 | 104 | HD15_reg (width 2) 105 | ------------------ 106 | Async-reset: reset 107 | 108 | 109 | HD16_reg (width 2) 110 | ------------------ 111 | Async-reset: reset 112 | 113 | 114 | Writing to hnl file './bVITERBI_213_proj/workdirs/WORK/bBMU_213.hnl' 115 | -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bBMU_213.sts: -------------------------------------------------------------------------------- 1 | 0 -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bCONTROL_213%verilog.syn: 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https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bCONTROL_213.hnl -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bCONTROL_213.sts: -------------------------------------------------------------------------------- 1 | 3 -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bSYNCERR_213%verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bSYNCERR_213%verilog.syn -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bSYNCERR_213%verilog__verilog.syn: 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'/emc/joshea/JOS/Verilog/Vit_b213/src/bSYNCERR_213.v'. 5 | =============================================================================== 6 | | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | 7 | =============================================================================== 8 | | error_reg | Flip-flop | 1 | - | - | Y | N | N | N | N | 9 | =============================================================================== 10 | 11 | error_reg 12 | --------- 13 | Async-reset: reset 14 | 15 | 16 | Writing to hnl file './bVITERBI_213_proj/workdirs/WORK/bSYNCERR_213.hnl' 17 | -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bSYNCERR_213.sts: -------------------------------------------------------------------------------- 1 | 0 -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bTBDECISION_213%verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bTBDECISION_213%verilog.syn -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bTBDECISION_213%verilog__verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bTBDECISION_213%verilog__verilog.syn -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bTBDECISION_213.hnl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bTBDECISION_213.hnl -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bTBDECISION_213.out: -------------------------------------------------------------------------------- 1 | Writing to hnl file './bVITERBI_213_proj/workdirs/WORK/bTBDECISION_213.hnl' 2 | -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bTBDECISION_213.sts: -------------------------------------------------------------------------------- 1 | 0 -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bVITERBI_213%verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bVITERBI_213%verilog.syn -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bVITERBI_213%verilog__verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bVITERBI_213%verilog__verilog.syn -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bVITERBI_213.hnl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bVITERBI_213.hnl -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bVITERBI_213.out: -------------------------------------------------------------------------------- 1 | Writing to hnl file './bVITERBI_213_proj/workdirs/WORK/bVITERBI_213.hnl' 2 | -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_proj/workdirs/WORK/bVITERBI_213.sts: -------------------------------------------------------------------------------- 1 | 0 -------------------------------------------------------------------------------- /Vit_b213/syn/out/bVITERBI_213_syn-Optimized.fc2: -------------------------------------------------------------------------------- 1 | create_project bVITERBI_213_proj 2 | 3 | add_file -library WORK -format Verilog ../../src/bVITERBI_213.v 4 | add_file -library WORK -format Verilog ../../src/bCONTROL_213.v 5 | add_file -library WORK -format Verilog ../../src/bBMU_213.v 6 | add_file -library WORK -format Verilog ../../src/bACS_213.v 7 | add_file -library WORK -format Verilog ../../src/bACSU_213.v 8 | add_file -library WORK -format Verilog ../../src/bSYNCERR_213.v 9 | add_file -library WORK -format Verilog ../../src/bTBDECISION_213.v 10 | 11 | analyze_file -progress 12 | 13 | create_chip -progress -name bVITERBI_213_syn -target VIRTEX -device V50TQ144 -speed -4 -frequency 25 -module -preserve bVITERBI_213 14 | current_chip bVITERBI_213_syn 15 | 16 | optimize_chip -name bVITERBI_213_syn-Optimized -progress 17 | 18 | export_chip 19 | 20 | list_message 21 | -------------------------------------------------------------------------------- /Vit_b213/syn/out/fc2_shell_command.log: -------------------------------------------------------------------------------- 1 | #@ # 2 | #@ # Running fc2_shell on Sat Mar 24 18:42:10 2001 3 | #@ 4 | 5 | source -echo -verbose ../scr/../scr/bVITERBI_213_script 6 | #@ # setup default variables 7 | #@ 8 | #@ 9 | #@ set top $env(SYN_TOP) 10 | #@ set quick $env(SYN_QUICK) 11 | #@ set preserve $env(SYN_PRESERVE) 12 | #@ set timing $env(SYN_TIMING_DRIVEN) 13 | #@ set target VIRTEX 14 | #@ set chip ${top}_syn 15 | #@ set device V50TQ144 16 | #@ set speed -4 17 | #@ set frequency 25 18 | #@ set constraints $env(CONSTRAINTS) 19 | #@ 20 | #@ # create project 21 | #@ create_project $env(SYN_PROJECT) 22 | #@ 23 | #@ # proj_export_timing_constraint = "yes" 24 | #@ 25 | #@ puts "proj_enable_vpp = yes (turns on verilog pre-processor for `ifdefs)" 26 | #@ proj_enable_vpp = "yes" 27 | #@ 28 | #@ # identify design source files 29 | #@ 30 | #@ add_file -library WORK -format Verilog ../../src/bVITERBI_213.v 31 | #@ add_file -library WORK -format Verilog ../../src/bCONTROL_213.v 32 | #@ add_file -library WORK -format Verilog ../../src/bBMU_213.v 33 | #@ add_file -library WORK -format Verilog ../../src/bACS_213.v 34 | #@ add_file -library WORK -format Verilog ../../src/bACSU_213.v 35 | #@ add_file -library WORK -format Verilog ../../src/bSYNCERR_213.v 36 | #@ add_file -library WORK -format Verilog ../../src/bTBDECISION_213.v 37 | #@ 38 | #@ # analyze all source files and list progress 39 | #@ analyze_file -progress 40 | #@ 41 | #@ set option $quick 42 | #@ append option $preserve 43 | #@ puts $option 44 | #@ 45 | #@ switch -exact -- $option { 46 | #@ "-normal-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top} 47 | #@ "-normal-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $preserve} 48 | #@ "-quick_mode-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick} 49 | #@ "-quick_mode-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick $preserve} 50 | #@ 51 | #@ } 52 | #@ 53 | #@ 54 | #@ #if {$preserve=="-preserve"} { 55 | #@ # create_chip -preserve -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 56 | #@ #} else { 57 | #@ #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 58 | #@ #} 59 | #@ 60 | #@ #if {$quick=="-quick_mode"} { 61 | #@ # create_chip -quick_mode -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 62 | #@ #} else { 63 | #@ #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 64 | #@ #} 65 | #@ current_chip $chip 66 | #@ 67 | #@ puts "set_chip_constraint_driven $timing" 68 | #@ set_chip_constraint_driven $timing 69 | #@ 70 | #@ 71 | #@ # read fc2 timing constraints if they exist 72 | #@ if {$timing=="-enable"} { 73 | #@ source ../scr/$constraints 74 | #@ } 75 | #@ 76 | #@ set opt_chip [format "%s-Optimized" $chip] 77 | #@ optimize_chip -name $opt_chip -progress 78 | #@ 79 | #@ export_chip -progress -s "Verilog" -pri 80 | #@ export_chip -progress 81 | #@ 82 | #@ # write out script of commands that were used. 83 | #@ script_chip 84 | #@ 85 | #@ # create a timing report 86 | #@ report_timing 87 | #@ 88 | #@ 89 | #@ 90 | #@ list_message 91 | #@ close_project 92 | #@ quit 93 | -------------------------------------------------------------------------------- /Vit_b213/syn/scr/bVITERBI_213_constraint.fc2: -------------------------------------------------------------------------------- 1 | # 2 | # constraints.fst 3 | # 4 | # This script sets constraints. It is called by the 5 | # am2910_xx.fst scripts. 6 | # 7 | # It will run under either the NT or UNIX environments. 8 | # 9 | # This script and the design can be found in the samples/Synopsys 10 | # sub-directory of the FPGA Express installation. 11 | # 12 | 13 | # 14 | # Specify the clock waveform 15 | # 16 | set_clock -period 20 -rise 0 -fall 10 CLOCK 17 | 18 | # 19 | # Create a subpath 20 | # 21 | create_subpath -from_name my_from -to_name my_to -from_list /AM2910/U1\/STACK_TOP_reg<3> -to_list /AM2910/U1\/STACK_TOP_reg<1> -maxd 10 (RC,CLOCK):(RC,CLOCK) 22 | 23 | # 24 | # Specify delay for path groups 25 | # 26 | set_max_delay -path my_from:my_to 77 27 | 28 | # 29 | # Specify input delay relative to input pad timing group 30 | # 31 | set_input_delay -group "(I)" 21 "/AM2910/D<1>" 32 | 33 | # 34 | # Specify input delay relative to default group 35 | # 36 | set_input_delay 22 "/AM2910/D<2>" 37 | 38 | # 39 | # Specify output delay relative to output pad timing group 40 | # 41 | set_output_delay -group "(O)" 23 "/AM2910/Y_OUTPUT<1>" 42 | 43 | # 44 | # Specify output delay relative to default group 45 | # 46 | set_output_delay 24 "/AM2910/Y_OUTPUT<2>" 47 | 48 | 49 | # 50 | # Preserve the hierarchy for the module U4 51 | # 52 | set_module_primitive preserve "/AM2910/U4" 53 | 54 | -------------------------------------------------------------------------------- /Vit_b213/syn/scr/bVITERBI_213_script: -------------------------------------------------------------------------------- 1 | # setup default variables 2 | 3 | 4 | set top $env(SYN_TOP) 5 | set quick $env(SYN_QUICK) 6 | set preserve $env(SYN_PRESERVE) 7 | set timing $env(SYN_TIMING_DRIVEN) 8 | set target VIRTEX 9 | set chip ${top}_syn 10 | set device V50TQ144 11 | set speed -4 12 | set frequency 25 13 | set constraints $env(CONSTRAINTS) 14 | 15 | # create project 16 | create_project $env(SYN_PROJECT) 17 | 18 | # proj_export_timing_constraint = "yes" 19 | 20 | puts "proj_enable_vpp = yes (turns on verilog pre-processor for `ifdefs)" 21 | proj_enable_vpp = "yes" 22 | 23 | # identify design source files 24 | 25 | add_file -library WORK -format Verilog ../../src/bVITERBI_213.v 26 | add_file -library WORK -format Verilog ../../src/bCONTROL_213.v 27 | add_file -library WORK -format Verilog ../../src/bBMU_213.v 28 | add_file -library WORK -format Verilog ../../src/bACS_213.v 29 | add_file -library WORK -format Verilog ../../src/bACSU_213.v 30 | add_file -library WORK -format Verilog ../../src/bSYNCERR_213.v 31 | add_file -library WORK -format Verilog ../../src/bTBDECISION_213.v 32 | 33 | # analyze all source files and list progress 34 | analyze_file -progress 35 | 36 | set option $quick 37 | append option $preserve 38 | puts $option 39 | 40 | switch -exact -- $option { 41 | "-normal-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top} 42 | "-normal-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $preserve} 43 | "-quick_mode-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick} 44 | "-quick_mode-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick $preserve} 45 | 46 | } 47 | 48 | 49 | #if {$preserve=="-preserve"} { 50 | # create_chip -preserve -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 51 | #} else { 52 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 53 | #} 54 | 55 | #if {$quick=="-quick_mode"} { 56 | # create_chip -quick_mode -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 57 | #} else { 58 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 59 | #} 60 | current_chip $chip 61 | 62 | puts "set_chip_constraint_driven $timing" 63 | set_chip_constraint_driven $timing 64 | 65 | 66 | # read fc2 timing constraints if they exist 67 | if {$timing=="-enable"} { 68 | source ../scr/$constraints 69 | } 70 | 71 | set opt_chip [format "%s-Optimized" $chip] 72 | optimize_chip -name $opt_chip -progress 73 | 74 | export_chip -progress -s "Verilog" -pri 75 | export_chip -progress 76 | 77 | # write out script of commands that were used. 78 | script_chip 79 | 80 | # create a timing report 81 | report_timing 82 | 83 | 84 | 85 | list_message 86 | close_project 87 | quit 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | -------------------------------------------------------------------------------- /Vit_b213/syn/scr/bVITERBI_213_script~: -------------------------------------------------------------------------------- 1 | # setup default variables 2 | 3 | 4 | set top $env(SYN_TOP) 5 | set quick $env(SYN_QUICK) 6 | set preserve $env(SYN_PRESERVE) 7 | set timing $env(SYN_TIMING_DRIVEN) 8 | set target XC4000XLA 9 | set chip ${top}_syn 10 | set device XC4028XLABG256 11 | set speed -09 12 | set frequency 25 13 | set constraints $env(CONSTRAINTS) 14 | 15 | # create project 16 | create_project $env(SYN_PROJECT) 17 | 18 | # proj_export_timing_constraint = "yes" 19 | 20 | puts "proj_enable_vpp = yes (turns on verilog pre-processor for `ifdefs)" 21 | proj_enable_vpp = "yes" 22 | 23 | # identify design source files 24 | 25 | add_file -library WORK -format Verilog ../../src/bVITERBI_213.v 26 | add_file -library WORK -format Verilog ../../src/bCONTROL_213.v 27 | add_file -library WORK -format Verilog ../../src/bBMU_213.v 28 | add_file -library WORK -format Verilog ../../src/bACS_213.v 29 | add_file -library WORK -format Verilog ../../src/bACSU_213.v 30 | add_file -library WORK -format Verilog ../../src/bSYNCERR_213.v 31 | add_file -library WORK -format Verilog ../../src/bTBDECISION_213.v 32 | 33 | # analyze all source files and list progress 34 | analyze_file -progress 35 | 36 | set option $quick 37 | append option $preserve 38 | puts $option 39 | 40 | switch -exact -- $option { 41 | "-normal-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top} 42 | "-normal-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $preserve} 43 | "-quick_mode-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick} 44 | "-quick_mode-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick $preserve} 45 | 46 | } 47 | 48 | 49 | #if {$preserve=="-preserve"} { 50 | # create_chip -preserve -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 51 | #} else { 52 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 53 | #} 54 | 55 | #if {$quick=="-quick_mode"} { 56 | # create_chip -quick_mode -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 57 | #} else { 58 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 59 | #} 60 | current_chip $chip 61 | 62 | puts "set_chip_constraint_driven $timing" 63 | set_chip_constraint_driven $timing 64 | 65 | 66 | # read fc2 timing constraints if they exist 67 | if {$timing=="-enable"} { 68 | source ../scr/$constraints 69 | } 70 | 71 | set opt_chip [format "%s-Optimized" $chip] 72 | optimize_chip -name $opt_chip -progress 73 | 74 | export_chip -progress -s "Verilog" -pri 75 | export_chip -progress 76 | 77 | # write out script of commands that were used. 78 | script_chip 79 | 80 | # create a timing report 81 | report_timing 82 | 83 | 84 | 85 | list_message 86 | close_project 87 | quit 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | -------------------------------------------------------------------------------- /Vit_b322/.synopsys_dc.setup: -------------------------------------------------------------------------------- 1 | /* =================================================== */ 2 | /* Template .synopsys_dc.setup file for Xilinx designs */ 3 | /* For use with Synopsys FPGA Compiler. */ 4 | /* =================================================== */ 5 | 6 | /* ================================================= */ 7 | /* The Synopsys search path should be set to point */ 8 | /* to the directories that contain the various */ 9 | /* synthesis libraries used by FPGA Compiler during */ 10 | /* synthesis. */ 11 | /* ================================================= */ 12 | 13 | XilinxInstall = get_unix_variable(XILINX); 14 | SynopsysInstall = get_unix_variable(SYNOPSYS); 15 | 16 | search_path = { . \ 17 | XilinxInstall + /synopsys/libraries/syn \ 18 | SynopsysInstall + /libraries/syn } 19 | 20 | /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ 21 | /* Ensure that your UNIX environment */ 22 | /* includes the two environment var- */ 23 | /* iables: $XILINX (points to the */ 24 | /* Xilinx installation directory) and*/ 25 | /* $SYNOPSYS (points to the Synopsys */ 26 | /* installation directory.) */ 27 | /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ 28 | 29 | /* ================================================= */ 30 | /* Define a work library in the current project dir */ 31 | /* to hold temporary files and keep the project area */ 32 | /* uncluttered. Note: You must create a subdirectory */ 33 | /* in your project directory called WORK. */ 34 | /* ================================================= */ 35 | 36 | 37 | define_design_lib WORK -path ./WORK 38 | 39 | 40 | bus_extraction_style = "%s<%d:%d>" 41 | bus_naming_style = "%s<%d>" 42 | bus_dimension_separator_style = "><" 43 | 44 | edifin_lib_logic_1_symbol = "VCC" 45 | edifin_lib_logic_0_symbol = "GND" 46 | edifout_ground_name = "GND" 47 | edifout_ground_pin_name = "G" 48 | edifout_power_name = "VCC" 49 | edifout_power_pin_name = "P" 50 | edifout_netlist_only = "true" 51 | edifout_no_array = "true" 52 | edifout_power_and_ground_representation = "cell" 53 | edifout_write_properties_list = {"CLK1X_DUTY" "INIT_00" "INIT_01" "INIT_02" "INIT_03" \ 54 | "INIT_04" "INIT_05" "INIT_06" "INIT_07" "INIT_08" "INIT_09" "INIT_0A" "INIT_0B" "INIT_0C" \ 55 | "INIT_0D" "INIT_0E" "INIT_0F" "INIT" "CLKDV_DIVIDE" "IOB" "EQN" "lut_function"} 56 | 57 | /* ================================================= */ 58 | /* Set the link, target and synthetic library */ 59 | /* variables. Use synlibs (with the -dc switch) to */ 60 | /* determine the link and target library settings. */ 61 | /* You may like to copy this file to your project */ 62 | /* directory, rename it ".synopsys_dc.setup" and */ 63 | /* append the output of synlibs. For example: */ 64 | /* synlibs xfpga_virtex-3 >> .synopsys_dc.setup */ 65 | /* ================================================= */ 66 | 67 | 68 | 69 | /*link_library = {xfpga_virtex-5.db xdw_virtex.sldb}*/ 70 | /*target_library = {xfpga_virtex-5.db }*/ 71 | /*symbol_library = {virtex.sdb}*/ 72 | /*define_design_lib xdw_virtex -path XilinxInstall + /synopsys/libraries/dw/lib/virtex*/ 73 | /*synthetic_library = {xdw_virtex.sldb standard.sldb}*/ 74 | 75 | 76 | link_library = {xprim_4028xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db xdw_4000xla.sldb} 77 | target_library = {xprim_4028xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db} 78 | define_design_lib xdw_4000xla -path XilinxInstall + /synopsys/libraries/dw/lib/xc4000xla 79 | symbol_library = {xc4000ex.sdb} 80 | synthetic_library = {xdw_4000xla.sldb standard.sldb} 81 | 82 | 83 | 84 | /*link_library = {xprim_4013xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db xdw_4000xla.sldb}*/ 85 | /*target_library = {xprim_4013xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db}*/ 86 | /*define_design_lib xdw_4000xla -path XilinxInstall + /synopsys/libraries/dw/lib/xc4000xla*/ 87 | /*symbol_library = {xc4000ex.sdb}*/ 88 | /*synthetic_library = {xdw_4000xla.sldb standard.sldb}*/ 89 | 90 | -------------------------------------------------------------------------------- /Vit_b322/DecoderInput.dat: -------------------------------------------------------------------------------- 1 | 000 2 | 011 3 | 111 4 | 011 5 | 100 6 | 110 7 | 010 8 | 000 9 | 100 10 | 011 11 | 100 12 | 011 13 | 001 14 | 000 15 | 100 16 | 110 17 | 010 18 | 000 19 | 100 20 | 011 21 | 001 22 | 110 23 | -------------------------------------------------------------------------------- /Vit_b322/ENCODER_322.v: -------------------------------------------------------------------------------- 1 | /*========================================================= 2 | module ENCODER_322.v 3 | 4 | Implements a (3,2,2) convolutional encoder 5 | 6 | Generator Matrix g=[110;010;010;101;100;101] 7 | 8 | John O'Shea, jfoshea@gmail.com 9 | 10 | ============================================================*/ 11 | 12 | `timescale 1 ns/1 ns 13 | 14 | module ENCODER_322 (Vx,Ux,tb_en,clock,reset); 15 | 16 | output [2:0] Vx; 17 | 18 | input [1:0] Ux; 19 | input tb_en; 20 | input clock; 21 | input reset; 22 | 23 | reg [1:0] enc_reg_s11; 24 | reg [2:0] enc_reg_s21s22; 25 | 26 | 27 | always @(posedge clock or posedge reset) 28 | begin 29 | if(reset) 30 | begin 31 | enc_reg_s11 <=0; 32 | enc_reg_s21s22 <=0; 33 | end 34 | else 35 | begin 36 | if (!tb_en) 37 | begin 38 | enc_reg_s11 <={Ux[0], enc_reg_s11[1]}; 39 | enc_reg_s21s22 <={Ux[1], enc_reg_s21s22[2:1]}; 40 | end 41 | end 42 | end 43 | 44 | assign Vx[0] = enc_reg_s11[1] ^ enc_reg_s21s22[1] ^ enc_reg_s11[0]; 45 | assign Vx[1] = enc_reg_s11[0] ^ enc_reg_s21s22[2] ^ enc_reg_s21s22[0]; 46 | assign Vx[2] = enc_reg_s11[1] ^ enc_reg_s21s22[0] ^ enc_reg_s21s22[2]; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /Vit_b322/b322_build.script: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | ngdbuild -p 4028XLABG256-09 bVITERBI_322.sedif 3 | map -oe high bVITERBI_322.ngd 4 | par -c 1 -d 1 bVITERBI_322.ncd -w bVITERBI_r_322.ncd 5 | 6 | -------------------------------------------------------------------------------- /Vit_b322/b322_synth.script: -------------------------------------------------------------------------------- 1 | /* =======================================================*/ 2 | /* Synopsys Script */ 3 | /* (3,2,2) Backward Label Viterbi Decoder */ 4 | /* Targets a Xilinx XC4028XLA-09 BG256 */ 5 | /* =======================================================*/ 6 | 7 | 8 | TOP = bVITERBI_322 9 | edifout_design_name = bVITERBI_322 10 | designer = "John O'Shea" 11 | company = "EMC Corporation" 12 | part = "XC4028XLABG256-09" 13 | 14 | sh "rm -rf WORK; mkdir WORK" 15 | 16 | read -format verilog "bBMU_322.v" 17 | read -format verilog "bACS_322.v" 18 | read -format verilog "bACSU_322.v" 19 | read -format verilog "bSYNCERR_322.v" 20 | read -format verilog "bTBDECISION_322.v" 21 | read -format verilog "bCONTROL_322.v" 22 | read -format verilog "bVITERBI_322.v" 23 | 24 | set_operating_conditions -library "xprim_4028xla-09" "WCCOM" 25 | current_design bVITERBI_322 26 | uniquify 27 | remove_constraint -all 28 | 29 | create_clock -name "clock" -period 50 {"clock"} 30 | set_input_delay 5.0 -clock clock all_inputs() - clock 31 | set_output_delay 5.0 -clock clock all_outputs() 32 | set_max_delay 100 -to find(port,Dx) 33 | 34 | 35 | set_port_is_pad "*" 36 | set_pad_type -no_clock {"clock"} 37 | set_pad_type -exact BUFGP_F{"clock"} 38 | set_pad_type -slewrate HIGH all_outputs() 39 | insert_pads 40 | 41 | compile -map_effort high 42 | 43 | set_attribute bVITERBI_322 "part" -type string part 44 | 45 | ungroup -all -flatten 46 | 47 | write -format edif -hierarchy -output bVITERBI_322.sedif 48 | 49 | write -format db -hierarchy -output bVITERBI_322.db 50 | 51 | exit 52 | 53 | -------------------------------------------------------------------------------- /Vit_b322/src/bACS_322.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module bACS_322.v 3 | 4 | ACS Block for (3,2,2) backward label decoder 5 | 6 | ============================================================*/ 7 | 8 | `timescale 1 ns/1 ns 9 | 10 | module bACS_322 (acs_ppm_out, acs_Bx_out, 11 | acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb, 12 | acs_ppm_inc, HD_inc, acs_ppm_ind, HD_ind, 13 | ae, reset, clock); 14 | 15 | 16 | 17 | `include "params_b322.inc" 18 | 19 | output [`W-1:0] acs_ppm_out; 20 | output [`k-1:0] acs_Bx_out; 21 | 22 | input [`W-1:0] acs_ppm_ina; 23 | input [`W-1:0] acs_ppm_inb; 24 | input [`W-1:0] acs_ppm_inc; 25 | input [`W-1:0] acs_ppm_ind; 26 | 27 | input [`W-1:0] HD_ina; 28 | input [`W-1:0] HD_inb; 29 | input [`W-1:0] HD_inc; 30 | input [`W-1:0] HD_ind; 31 | input ae; 32 | input reset; 33 | input clock; 34 | 35 | 36 | reg [`W-1:0] acs_ppm_out; 37 | reg [`W-1:0] acs_ppm_ab; 38 | reg [`W-1:0] acs_ppm_cd; 39 | 40 | 41 | reg [`k-1:0] acs_Bx_out; 42 | reg [`k-1:0] acs_Bx_ab; 43 | reg [`k-1:0] acs_Bx_cd; 44 | 45 | 46 | reg [`W-1:0] suma; 47 | reg [`W-1:0] sumb; 48 | reg [`W-1:0] sumc; 49 | reg [`W-1:0] sumd; 50 | 51 | 52 | 53 | always @(posedge clock or posedge reset) 54 | begin 55 | if (reset) 56 | suma <=0; 57 | else 58 | begin 59 | if (ae && acs_ppm_ina==4'b1111) 60 | suma <= acs_ppm_ina; 61 | else if (ae) 62 | suma <= acs_ppm_ina + HD_ina; 63 | end 64 | end 65 | 66 | 67 | always @(posedge clock or posedge reset) 68 | begin 69 | if (reset) 70 | sumb <=0; 71 | else 72 | begin 73 | if (ae && acs_ppm_inb==4'b1111) 74 | sumb <= acs_ppm_inb; 75 | else if (ae) 76 | sumb <= acs_ppm_inb + HD_inb; 77 | end 78 | end 79 | 80 | always @(posedge clock or posedge reset) 81 | begin 82 | if (reset) 83 | sumc <=0; 84 | else 85 | begin 86 | if (ae && acs_ppm_inc==4'b1111) 87 | sumc <= acs_ppm_inc; 88 | else if (ae) 89 | sumc <= acs_ppm_inc + HD_inc; 90 | end 91 | end 92 | 93 | 94 | always @(posedge clock or posedge reset) 95 | begin 96 | if (reset) 97 | sumd <=0; 98 | else 99 | begin 100 | if (ae && acs_ppm_ind==4'b1111) 101 | sumd <= acs_ppm_ind; 102 | else if (ae) 103 | sumd <= acs_ppm_ind + HD_ind; 104 | end 105 | end 106 | 107 | 108 | 109 | always @(suma or sumb or sumc or sumd) 110 | begin 111 | if (suma <=sumb) 112 | begin 113 | acs_ppm_ab =suma; 114 | acs_Bx_ab =2'b00; 115 | end 116 | else 117 | begin 118 | acs_ppm_ab =sumb; 119 | acs_Bx_ab =2'b01; 120 | end 121 | if (sumc <=sumd) 122 | begin 123 | acs_ppm_cd =sumc; 124 | acs_Bx_cd =2'b10; 125 | end 126 | else 127 | begin 128 | acs_ppm_cd =sumd; 129 | acs_Bx_cd =2'b11; 130 | end 131 | end 132 | 133 | 134 | 135 | always @(acs_ppm_ab or acs_ppm_cd) 136 | begin 137 | if (acs_ppm_ab <= acs_ppm_cd) 138 | begin 139 | acs_ppm_out = acs_ppm_ab; 140 | acs_Bx_out = acs_Bx_ab; 141 | end 142 | else 143 | begin 144 | acs_ppm_out = acs_ppm_cd; 145 | acs_Bx_out = acs_Bx_cd; 146 | end 147 | end 148 | 149 | 150 | endmodule 151 | -------------------------------------------------------------------------------- /Vit_b322/src/bSYNCERR_322.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module bSYNCERR_322.v 3 | 4 | Out of Synch Error Detector for (3,2,2) Viterbi decoder. 5 | 6 | ===========================================================================*/ 7 | `timescale 1 ns/1 ns 8 | 9 | 10 | module bSYNCERR_322 (error, stage, we, metric, reset, clock); 11 | 12 | 13 | output error; 14 | 15 | input [3:0] stage; 16 | input [2:0] metric; 17 | input we; 18 | input reset; 19 | input clock; 20 | reg error; 21 | 22 | 23 | always @(posedge clock or posedge reset) 24 | begin 25 | if (reset) 26 | error <=1'b0; 27 | else 28 | begin 29 | if (we && stage >=4'b0011 && metric >4'b1000) 30 | error <=1'b1; 31 | else 32 | error <=1'b0; 33 | end 34 | end 35 | 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /Vit_b322/src/bTBDECISION_322.v: -------------------------------------------------------------------------------- 1 | /*================================================================= 2 | module bTBDECISION_322.v 3 | 4 | Traceback Decision Unit for (3,2,2) decoder 5 | 6 | Determine pointer to initial state for traceback 7 | by finding the state with minimum accumulated metric 8 | 9 | ==================================================================*/ 10 | 11 | `timescale 1 ns/1 ns 12 | 13 | module bTBDECISION_322 (best_state, 14 | in0, in1, in2, in3, in4, in5, in6, in7); 15 | 16 | 17 | `include "params_b322.inc" 18 | 19 | output [2:0] best_state; 20 | 21 | input [`W-1:0] in0; 22 | input [`W-1:0] in1; 23 | input [`W-1:0] in2; 24 | input [`W-1:0] in3; 25 | input [`W-1:0] in4; 26 | input [`W-1:0] in5; 27 | input [`W-1:0] in6; 28 | input [`W-1:0] in7; 29 | 30 | reg [2:0] best_state; 31 | reg [`W-1:0] min_01; 32 | reg [`W-1:0] min_23; 33 | reg [`W-1:0] min_45; 34 | reg [`W-1:0] min_67; 35 | reg [`W-1:0] min_0123; 36 | reg [`W-1:0] min_4567; 37 | reg [`W-1:0] min_metric; 38 | 39 | 40 | 41 | always @(in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) 42 | begin 43 | if (in0 <=in1) 44 | min_01=in0; 45 | else 46 | min_01=in1; 47 | 48 | if (in2 <=in3) 49 | min_23=in2; 50 | else 51 | min_23=in3; 52 | 53 | if (in4 <=in5) 54 | min_45=in4; 55 | else 56 | min_45=in5; 57 | 58 | if (in6 <=in7) 59 | min_67=in6; 60 | else 61 | min_67=in7; 62 | 63 | if (min_01 <= min_23) 64 | min_0123 = min_01; 65 | else 66 | min_0123 = min_23; 67 | 68 | if (min_45 <= min_67) 69 | min_4567 = min_45; 70 | else 71 | min_4567 = min_67; 72 | 73 | if (min_0123 <= min_4567) 74 | min_metric = min_0123; 75 | else 76 | min_metric = min_4567; 77 | end 78 | 79 | 80 | always @ (in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 or min_metric) 81 | begin 82 | if (in0==min_metric) 83 | best_state = 3'b000; 84 | else if (in1==min_metric) 85 | best_state = 3'b001; 86 | else if (in2==min_metric) 87 | best_state = 3'b010; 88 | else if (in3==min_metric) 89 | best_state = 3'b011; 90 | else if (in4==min_metric) 91 | best_state = 3'b100; 92 | else if (in5==min_metric) 93 | best_state = 3'b101; 94 | else if (in6==min_metric) 95 | best_state = 3'b110; 96 | else 97 | best_state = 3'b111; 98 | end 99 | 100 | endmodule 101 | 102 | 103 | -------------------------------------------------------------------------------- /Vit_b322/src/nWaveLog/nWave.cmd: -------------------------------------------------------------------------------- 1 | wvOpenFile -win $_nWave1 {/emc/joshea/JOS/Verilog/Vit_b322/src/verilog.fsdb} 2 | wvSetPosition -win $_nWave1 {(G1 0)} 3 | wvReloadFile -win $_nWave1 4 | wvRestoreSignal -win $_nWave1 {/emc/joshea/JOS/Verilog/Vit_b322/src/sig.rc} 5 | wvSetCursor -win $_nWave1 1300.000000 6 | wvExit 7 | -------------------------------------------------------------------------------- /Vit_b322/src/nWaveLog/turbo.log: -------------------------------------------------------------------------------- 1 | au time=310 memory (delta=6610096:7872512 total=6681880:7962624) 2 | -------------------------------------------------------------------------------- /Vit_b322/src/params_b322.inc: -------------------------------------------------------------------------------- 1 | `define CLOCK_PERIOD 40 2 | `define NUM_VECTORS 10 3 | 4 | `define W 4 5 | `define N 20 6 | `define T 10 7 | `define n 3 8 | `define k 2 9 | `define m 2 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /Vit_b322/src/sim_b322.script: -------------------------------------------------------------------------------- 1 | tb_b322.v 2 | bBMU_322.v 3 | bACS_322.v 4 | bACSU_322.v 5 | bTBDECISION_322.v 6 | bSYNCERR_322.v 7 | bCONTROL_322.v 8 | bVITERBI_322.v 9 | +libext+.v+.V 10 | -y /hwapps/xilinx/M.1.5.i/verilog/src/UNI4000X 11 | -------------------------------------------------------------------------------- /Vit_b322/src/verilog.fsdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_b322/src/verilog.fsdb -------------------------------------------------------------------------------- /Vit_b322/syn/scr/trace_script: -------------------------------------------------------------------------------- 1 | # setup default variables 2 | 3 | 4 | set top $env(SYN_TOP) 5 | set quick $env(SYN_QUICK) 6 | set preserve $env(SYN_PRESERVE) 7 | set timing $env(SYN_TIMING_DRIVEN) 8 | set target VIRTEX 9 | set chip ${top}_syn 10 | set device V1000FG680 11 | set speed -6 12 | set frequency 75 13 | set constraints $env(CONSTRAINTS) 14 | 15 | # create project 16 | create_project $env(SYN_PROJECT) 17 | 18 | # proj_export_timing_constraint = "yes" 19 | 20 | puts "proj_enable_vpp = yes (turns on verilog pre-processor for `ifdefs)" 21 | proj_enable_vpp = "yes" 22 | 23 | # identify design source files 24 | 25 | add_file -library WORK -format Verilog ../../src/trace.v 26 | add_file -library WORK -format Verilog ../../src/RAM16X128.v 27 | add_file -library WORK -format Verilog ../../src/register_if.v 28 | 29 | 30 | 31 | 32 | # analyze all source files and list progress 33 | analyze_file -progress 34 | 35 | set option $quick 36 | append option $preserve 37 | puts $option 38 | 39 | switch -exact -- $option { 40 | "-normal-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top} 41 | "-normal-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $preserve} 42 | "-quick_mode-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick} 43 | "-quick_mode-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick $preserve} 44 | 45 | } 46 | 47 | 48 | #if {$preserve=="-preserve"} { 49 | # create_chip -preserve -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 50 | #} else { 51 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 52 | #} 53 | 54 | #if {$quick=="-quick_mode"} { 55 | # create_chip -quick_mode -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 56 | #} else { 57 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 58 | #} 59 | current_chip $chip 60 | 61 | puts "set_chip_constraint_driven $timing" 62 | set_chip_constraint_driven $timing 63 | 64 | 65 | # read fc2 timing constraints if they exist 66 | if {$timing=="-enable"} { 67 | source ../scr/$constraints 68 | } 69 | 70 | set opt_chip [format "%s-Optimized" $chip] 71 | optimize_chip -name $opt_chip -progress 72 | 73 | export_chip -progress -s "Verilog" -pri 74 | export_chip -progress 75 | 76 | # write out script of commands that were used. 77 | script_chip 78 | 79 | # create a timing report 80 | report_timing 81 | 82 | 83 | 84 | list_message 85 | close_project 86 | quit 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | -------------------------------------------------------------------------------- /Vit_e213/.synopsys_dc.setup: -------------------------------------------------------------------------------- 1 | /* =================================================== */ 2 | /* Template .synopsys_dc.setup file for Xilinx designs */ 3 | /* For use with Synopsys FPGA Compiler. */ 4 | /* =================================================== */ 5 | 6 | /* ================================================= */ 7 | /* The Synopsys search path should be set to point */ 8 | /* to the directories that contain the various */ 9 | /* synthesis libraries used by FPGA Compiler during */ 10 | /* synthesis. */ 11 | /* ================================================= */ 12 | 13 | XilinxInstall = get_unix_variable(XILINX); 14 | SynopsysInstall = get_unix_variable(SYNOPSYS); 15 | 16 | search_path = { . \ 17 | XilinxInstall + /synopsys/libraries/syn \ 18 | SynopsysInstall + /libraries/syn } 19 | 20 | /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ 21 | /* Ensure that your UNIX environment */ 22 | /* includes the two environment var- */ 23 | /* iables: $XILINX (points to the */ 24 | /* Xilinx installation directory) and*/ 25 | /* $SYNOPSYS (points to the Synopsys */ 26 | /* installation directory.) */ 27 | /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ 28 | 29 | /* ================================================= */ 30 | /* Define a work library in the current project dir */ 31 | /* to hold temporary files and keep the project area */ 32 | /* uncluttered. Note: You must create a subdirectory */ 33 | /* in your project directory called WORK. */ 34 | /* ================================================= */ 35 | 36 | 37 | define_design_lib WORK -path ./WORK 38 | 39 | 40 | bus_extraction_style = "%s<%d:%d>" 41 | bus_naming_style = "%s<%d>" 42 | bus_dimension_separator_style = "><" 43 | 44 | edifin_lib_logic_1_symbol = "VCC" 45 | edifin_lib_logic_0_symbol = "GND" 46 | edifout_ground_name = "GND" 47 | edifout_ground_pin_name = "G" 48 | edifout_power_name = "VCC" 49 | edifout_power_pin_name = "P" 50 | edifout_netlist_only = "true" 51 | edifout_no_array = "true" 52 | edifout_power_and_ground_representation = "cell" 53 | edifout_write_properties_list = {"CLK1X_DUTY" "INIT_00" "INIT_01" "INIT_02" "INIT_03" \ 54 | "INIT_04" "INIT_05" "INIT_06" "INIT_07" "INIT_08" "INIT_09" "INIT_0A" "INIT_0B" "INIT_0C" \ 55 | "INIT_0D" "INIT_0E" "INIT_0F" "INIT" "CLKDV_DIVIDE" "IOB" "EQN" "lut_function"} 56 | 57 | /* ================================================= */ 58 | /* Set the link, target and synthetic library */ 59 | /* variables. Use synlibs (with the -dc switch) to */ 60 | /* determine the link and target library settings. */ 61 | /* You may like to copy this file to your project */ 62 | /* directory, rename it ".synopsys_dc.setup" and */ 63 | /* append the output of synlibs. For example: */ 64 | /* synlibs xfpga_virtex-3 >> .synopsys_dc.setup */ 65 | /* ================================================= */ 66 | 67 | 68 | 69 | /*link_library = {xfpga_virtex-5.db xdw_virtex.sldb}*/ 70 | /*target_library = {xfpga_virtex-5.db }*/ 71 | /*symbol_library = {virtex.sdb}*/ 72 | /*define_design_lib xdw_virtex -path XilinxInstall + /synopsys/libraries/dw/lib/virtex*/ 73 | /*synthetic_library = {xdw_virtex.sldb standard.sldb}*/ 74 | 75 | 76 | link_library = {xprim_4028xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db xdw_4000xla.sldb} 77 | target_library = {xprim_4028xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db} 78 | define_design_lib xdw_4000xla -path XilinxInstall + /synopsys/libraries/dw/lib/xc4000xla 79 | symbol_library = {xc4000ex.sdb} 80 | synthetic_library = {xdw_4000xla.sldb standard.sldb} 81 | 82 | 83 | 84 | /*link_library = {xprim_4013xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db xdw_4000xla.sldb}*/ 85 | /*target_library = {xprim_4013xla-09.db xprim_4000xla-09.db xgen_4000xla.db xdc_4000xla-09.db xio_4000xla-09.db}*/ 86 | /*define_design_lib xdw_4000xla -path XilinxInstall + /synopsys/libraries/dw/lib/xc4000xla*/ 87 | /*symbol_library = {xc4000ex.sdb}*/ 88 | /*synthetic_library = {xdw_4000xla.sldb standard.sldb}*/ 89 | 90 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/VIT_ENC.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module VIT_ENC.v 3 | 4 | Implements a (2,1,3) convolutional encoder 5 | 6 | John O'Shea, joshea@emc.com 7 | ============================================================*/ 8 | 9 | `timescale 1 ns/1 ns 10 | 11 | module VIT_ENC (Vx,Ux,tb_en,clock,reset); 12 | 13 | `include "params_b213.inc.v" 14 | 15 | output [`n-1:0] Vx; 16 | input [`k-1:0] Ux; 17 | input tb_en; 18 | input clock; 19 | input reset; 20 | 21 | reg [`m:0] encoder_reg; 22 | 23 | always @(posedge clock or posedge reset) 24 | begin 25 | if(reset) 26 | encoder_reg <= 4'b0; 27 | 28 | if (tb_en==1'b0) 29 | encoder_reg <= {Ux, encoder_reg[3:1]}; 30 | end 31 | 32 | assign Vx[1] = encoder_reg[3]^encoder_reg[1]^encoder_reg[0]; 33 | assign Vx[0] = encoder_reg[3]^encoder_reg[2]^encoder_reg[1]^encoder_reg[0]; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/eACS_213.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module eACS_213.v 3 | 4 | ACS Block for efficient (2,1,3) backward label decoder 5 | 6 | John O'Shea, joshea@emc.com 7 | 8 | ============================================================*/ 9 | 10 | `timescale 1 ns/1 ns 11 | 12 | module eACS_213 (acs_ppm_out, acs_Bx_out, 13 | acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb, 14 | ae, clock, reset); 15 | 16 | 17 | 18 | `include "params_e213.inc.v" 19 | 20 | output [`W-1:0] acs_ppm_out; 21 | output [`k-1:0] acs_Bx_out; 22 | 23 | input [`W-1:0] acs_ppm_ina; 24 | input [`W-1:0] acs_ppm_inb; 25 | input [1:0] HD_ina; 26 | input [1:0] HD_inb; 27 | input ae; 28 | input clock; 29 | input reset; 30 | 31 | 32 | reg [`W-1:0] acs_ppm_out; 33 | reg [`k-1:0] acs_Bx_out; 34 | 35 | reg [`W-1:0] suma; 36 | reg [`W-1:0] sumb; 37 | 38 | 39 | 40 | always @(posedge clock or posedge reset) 41 | begin 42 | if (reset) 43 | suma <=0; 44 | else 45 | begin 46 | if (ae && acs_ppm_ina==4'b1111) 47 | suma <= acs_ppm_ina; 48 | else if (ae) 49 | suma <= acs_ppm_ina + HD_ina; 50 | end 51 | end 52 | 53 | always @(posedge clock or posedge reset) 54 | begin 55 | if (reset) 56 | sumb <=0; 57 | else 58 | begin 59 | if (ae && acs_ppm_inb ==4'b1111) 60 | sumb <=acs_ppm_inb; 61 | else if (ae) 62 | sumb <= acs_ppm_inb + HD_inb; 63 | end 64 | end 65 | 66 | always @(suma or sumb) 67 | begin 68 | if (suma <=sumb && ae) 69 | begin 70 | acs_ppm_out =suma; 71 | acs_Bx_out =1'b0; //Select Upper Backward Path 72 | end 73 | else 74 | begin 75 | acs_ppm_out =sumb; 76 | acs_Bx_out =1'b1; //Select Lower Backward Path 77 | end 78 | end 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/eBMU_213.v: -------------------------------------------------------------------------------- 1 | /*=========================================================== 2 | module eBMU_213.v 3 | 4 | Branch Metric Computation Unit for efficient 5 | (2,1,3) backward label Viterbi Decoder. 6 | 7 | John O'Shea, joshea@emc.com. 8 | 9 | ============================================================*/ 10 | 11 | module eBMU_213(HD1, HD2, HD3, HD4, 12 | HD5, HD6, HD7, HD8, 13 | HD9, HD10, HD11, HD12, 14 | HD13, HD14, HD15, HD16, 15 | Rx, le, clock, reset 16 | ); 17 | 18 | `include "params_e213.inc.v" 19 | 20 | output [1:0] HD1; 21 | output [1:0] HD2; 22 | output [1:0] HD3; 23 | output [1:0] HD4; 24 | output [1:0] HD5; 25 | output [1:0] HD6; 26 | output [1:0] HD7; 27 | output [1:0] HD8; 28 | output [1:0] HD9; 29 | output [1:0] HD10; 30 | output [1:0] HD11; 31 | output [1:0] HD12; 32 | output [1:0] HD13; 33 | output [1:0] HD14; 34 | output [1:0] HD15; 35 | output [1:0] HD16; 36 | 37 | 38 | input [1:0] Rx; 39 | input le; 40 | input clock; 41 | input reset; 42 | 43 | reg [1:0] HD1; 44 | reg [1:0] HD2; 45 | reg [1:0] HD3; 46 | reg [1:0] HD4; 47 | reg [1:0] HD5; 48 | reg [1:0] HD6; 49 | reg [1:0] HD7; 50 | reg [1:0] HD8; 51 | reg [1:0] HD9; 52 | reg [1:0] HD10; 53 | reg [1:0] HD11; 54 | reg [1:0] HD12; 55 | reg [1:0] HD13; 56 | reg [1:0] HD14; 57 | reg [1:0] HD15; 58 | reg [1:0] HD16; 59 | 60 | 61 | 62 | always @(posedge clock or posedge reset) 63 | begin 64 | if(reset) 65 | begin 66 | HD1 <=0; HD2 <=0; HD3 <=0; HD4 <=0; 67 | HD5 <=0; HD6 <=0; HD7 <=0; HD8 <=0; 68 | HD9 <=0; HD10<=0; HD11<=0; HD12<=0; 69 | HD13<=0; HD14<=0; HD15<=0; HD16<=0; 70 | end 71 | else if (le) 72 | begin 73 | case (Rx)//synopsys full_case 74 | 75 | 2'b00: begin 76 | HD1 <=2'b00; HD2 <=2'b10; HD3 <=2'b01; HD4 <=2'b01; 77 | HD5 <=2'b10; HD6 <=2'b00; HD7 <=2'b01; HD8 <=2'b01; 78 | HD9 <=2'b10; HD10<=2'b00; HD11<=2'b01; HD12<=2'b01; 79 | HD13<=2'b00; HD14<=2'b10; HD15<=2'b01; HD16<=2'b01; 80 | end 81 | 82 | 2'b01: begin 83 | HD1 <=2'b01; HD2 <=2'b01; HD3 <=2'b00; HD4 <=2'b10; 84 | HD5 <=2'b01; HD6 <=2'b01; HD7 <=2'b10; HD8 <=2'b00; 85 | HD9 <=2'b01; HD10<=2'b01; HD11<=2'b10; HD12<=2'b00; 86 | HD13<=2'b01; HD14<=2'b01; HD15<=2'b00; HD16<=2'b10; 87 | end 88 | 89 | 2'b10: begin 90 | HD1 <=2'b01; HD2 <=2'b01; HD3 <=2'b10; HD4 <=2'b00; 91 | HD5 <=2'b01; HD6 <=2'b01; HD7 <=2'b00; HD8 <=2'b10; 92 | HD9 <=2'b01; HD10<=2'b01; HD11<=2'b00; HD12<=2'b10; 93 | HD13<=2'b01; HD14<=2'b01; HD15<=2'b10; HD16<=2'b00; 94 | end 95 | 96 | 2'b11: begin 97 | HD1 <=2'b10; HD2 <=2'b00; HD3 <=2'b01; HD4 <=2'b01; 98 | HD5 <=2'b00; HD6 <=2'b10; HD7 <=2'b01; HD8 <=2'b01; 99 | HD9 <=2'b00; HD10<=2'b10; HD11<=2'b01; HD12<=2'b01; 100 | HD13<=2'b10; HD14<=2'b00; HD15<=2'b01; HD16<=2'b01; 101 | end 102 | endcase // case(Rx) 103 | end 104 | end 105 | 106 | 107 | endmodule 108 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/eSYNCERR_213.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module eSYNCERR_213.v 3 | 4 | Out of Synch Error Detector for (2,1,3) Viterbi decoder. 5 | 6 | John O'Shea, joshea@emc.com 7 | 8 | ===========================================================================*/ 9 | `timescale 1 ns/1 ns 10 | 11 | 12 | module eSYNCERR_213 (error, stage, we, metric, reset, clock 13 | ); 14 | 15 | 16 | output error; 17 | 18 | input [3:0] stage; 19 | input [2:0] metric; 20 | input we; 21 | input reset; 22 | input clock; 23 | reg error; 24 | 25 | 26 | always @(posedge clock or posedge reset) 27 | begin 28 | if (reset) 29 | error <=1'b0; 30 | else 31 | begin 32 | if (we && stage >=4'b0011 && metric >4'b1000) 33 | error <=1'b1; 34 | else 35 | error <=1'b0; 36 | end 37 | end 38 | 39 | 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/eTBDECISION_213.v: -------------------------------------------------------------------------------- 1 | /*================================================================= 2 | module eTBDECISION_213.v 3 | 4 | Traceback Decision Unit for (2,1,3) decoder 5 | 6 | Determine pointer to initial state for traceback 7 | by finding the state with minimum accumulated metric 8 | 9 | John O'Shea, joshea@emc.com 10 | ==================================================================*/ 11 | 12 | `timescale 1 ns/1 ns 13 | 14 | module eTBDECISION_213 (best_state, 15 | in0, in1, in2, in3, in4, in5, in6, in7, 16 | be, clock, reset); 17 | 18 | 19 | `include "params_e213.inc.v" 20 | 21 | output [`m-1:0] best_state; 22 | 23 | input [`W-1:0] in0; 24 | input [`W-1:0] in1; 25 | input [`W-1:0] in2; 26 | input [`W-1:0] in3; 27 | input [`W-1:0] in4; 28 | input [`W-1:0] in5; 29 | input [`W-1:0] in6; 30 | input [`W-1:0] in7; 31 | input be; 32 | input clock; 33 | input reset; 34 | 35 | reg [`m-1:0] best_state; 36 | reg [`m-1:0] min_state; 37 | reg [`W-1:0] min_01; 38 | reg [`W-1:0] min_23; 39 | reg [`W-1:0] min_45; 40 | reg [`W-1:0] min_67; 41 | reg [`W-1:0] min_0123; 42 | reg [`W-1:0] min_4567; 43 | reg [`W-1:0] min_metric; 44 | 45 | 46 | 47 | always @(in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) 48 | begin 49 | if (in0 <=in1) 50 | min_01=in0; 51 | else 52 | min_01=in1; 53 | 54 | if (in2 <=in3) 55 | min_23=in2; 56 | else 57 | min_23=in3; 58 | 59 | if (in4 <=in5) 60 | min_45=in4; 61 | else 62 | min_45=in5; 63 | 64 | if (in6 <=in7) 65 | min_67=in6; 66 | else 67 | min_67=in7; 68 | 69 | if (min_01 <= min_23) 70 | min_0123 = min_01; 71 | else 72 | min_0123 = min_23; 73 | 74 | if (min_45 <= min_67) 75 | min_4567 = min_45; 76 | else 77 | min_4567 = min_67; 78 | 79 | if (min_0123 <= min_4567) 80 | min_metric = min_0123; 81 | else 82 | min_metric = min_4567; 83 | end 84 | 85 | 86 | always @ (in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 or min_metric) 87 | begin 88 | if (in0==min_metric) 89 | min_state = 3'b000; 90 | else if (in1==min_metric) 91 | min_state = 3'b001; 92 | else if (in2==min_metric) 93 | min_state = 3'b010; 94 | else if (in3==min_metric) 95 | min_state = 3'b011; 96 | else if (in4==min_metric) 97 | min_state = 3'b100; 98 | else if (in5==min_metric) 99 | min_state = 3'b101; 100 | else if (in6==min_metric) 101 | min_state = 3'b110; 102 | else 103 | min_state = 3'b111; 104 | end 105 | 106 | always @(posedge clock or posedge reset) 107 | begin 108 | if (reset) 109 | best_state <=0; 110 | else if (be) 111 | best_state <=min_state; 112 | end 113 | 114 | 115 | endmodule 116 | 117 | 118 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/nWaveLog/nWave.cmd: -------------------------------------------------------------------------------- 1 | wvExit 2 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/nWaveLog/turbo.log: -------------------------------------------------------------------------------- 1 | au time=5 memory (delta=3721576:5357568 total=3793376:5447680) 2 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/params_e213.inc.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | params_b213.inc 3 | 4 | Constant Definitions for use in a (2,1,3) backward label Viterbi Decoder 5 | 6 | John O'Shea, joshea@emc.com 7 | 8 | ===========================================================================*/ 9 | 10 | `define CLOCK_PERIOD 40 11 | `define BLOCK_LEN 20 12 | `define NUM_VECTORS 10 13 | 14 | `define W 4 15 | `define T 15 16 | `define n 2 17 | `define k 1 18 | `define m 3 19 | 20 | 21 | 22 | 23 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/sim_e213.script: -------------------------------------------------------------------------------- 1 | tb_e213.v 2 | eBMU_213.v 3 | eACS_213.v 4 | eACSU_213.v 5 | eTBDECISION_213.v 6 | eSYNCERR_213.v 7 | eCONTROL_213.v 8 | eVITERBI_213.v 9 | +libext+.v+.V 10 | -y /hwapps/xilinx/M.1.5.i/verilog/src/UNI4000X 11 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/tb_e213.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module tb_e213.v 3 | 4 | Test bench for efficient (2,1,3) backward label Viterbi Decoder. 5 | 6 | John O'Shea, joshea@emc.com 7 | 8 | ===========================================================================*/ 9 | 10 | `timescale 1 ns/1 ns 11 | 12 | module tb_b213; 13 | 14 | `include "params_e213.inc.v" 15 | 16 | reg [`n-1:0] Rx_data [0:22]; 17 | reg [`n-1:0] Rx; 18 | 19 | reg clock; 20 | reg reset; 21 | 22 | wire [`k-1:0] Dx; 23 | wire [63:0] HD; 24 | wire sync_error; 25 | wire oe; 26 | 27 | integer i; 28 | 29 | 30 | /*=== Instantiate efficient (2,1,3) decoder ===*/ 31 | eVITERBI_213 TB_U2 (.Dx(Dx), .oe(oe), .sync_error(sync_error), .Rx(Rx), .clock(clock), .reset(reset)); 32 | 33 | 34 | /*=== Create Free Running Clock ===*/ 35 | 36 | always 37 | begin 38 | #(0.5*`CLOCK_PERIOD); 39 | clock=~clock; 40 | end 41 | 42 | /*=== Load Test Vectors ===*/ 43 | initial 44 | begin 45 | Rx_data[0] = 2'b00; 46 | Rx_data[1] = 2'b11; 47 | Rx_data[2] = 2'b10; 48 | Rx_data[3] = 2'b10; 49 | Rx_data[4] = 2'b11; 50 | Rx_data[5] = 2'b01; 51 | Rx_data[6] = 2'b10; 52 | Rx_data[7] = 2'b00; 53 | Rx_data[8] = 2'b00; 54 | Rx_data[9] = 2'b01; 55 | Rx_data[10] = 2'b00; 56 | Rx_data[11] = 2'b10; 57 | Rx_data[12] = 2'b11; 58 | Rx_data[13] = 2'b11; 59 | Rx_data[14] = 2'b11; 60 | Rx_data[15] = 2'b10; 61 | Rx_data[16] = 2'b10; 62 | Rx_data[17] = 2'b00; 63 | Rx_data[18] = 2'b00; 64 | Rx_data[19] = 2'b01; 65 | Rx_data[20] = 2'b11; 66 | Rx_data[21] = 2'b11; 67 | Rx_data[22] = 2'b00; 68 | end 69 | 70 | /*=== Clock data into the decoder ===*/ 71 | initial 72 | begin 73 | clock = 0; 74 | reset = 1; //Apply reset 75 | #`CLOCK_PERIOD reset =0; //Disable reset after one clock period 76 | 77 | for (i=0; i<23; i=i+1) 78 | begin 79 | Rx=Rx_data[i]; 80 | #(`CLOCK_PERIOD*3); 81 | end 82 | 83 | end 84 | 85 | 86 | /*=== Create Simulation Waveforms ===*/ 87 | 88 | initial 89 | begin 90 | $fsdbDumpfile("verilog.fsdb");// debussy dump format 91 | $fsdbDumpStrength; 92 | $fsdbDumpvars; 93 | end 94 | 95 | 96 | initial 97 | #3000 $finish; 98 | 99 | 100 | 101 | /*=== Monitor Viterbi Decoder Responses ===*/ 102 | initial 103 | $monitor("time=%4g, clock=%b, reset=%b, Rx=%b, le=%b,ae=%b,we=%b,be=%b,te=%b, oe=%b, wptr=%h, tptr=%h, CNT=%g, min_state=%b, tb_reg=%b, A_in=%h, P_in=%b, Dx=%b, error=%b, BC=%g,ns=%b", 104 | $time, 105 | clock, 106 | reset, 107 | Rx, 108 | TB_U2.U3.le, 109 | TB_U2.U3.ae, 110 | TB_U2.U3.we, 111 | TB_U2.U3.be, 112 | TB_U2.U3.te, 113 | TB_U2.U3.oe, 114 | TB_U2.U3.write_ptr, 115 | TB_U2.U3.trace_ptr, 116 | TB_U2.U3.block_count, 117 | TB_U2.U3.min_state, 118 | 119 | TB_U2.U3.tb_reg, 120 | 121 | {TB_U2.U3.A0_in, 122 | TB_U2.U3.A1_in, 123 | TB_U2.U3.A2_in, 124 | TB_U2.U3.A3_in, 125 | TB_U2.U3.A4_in, 126 | TB_U2.U3.A5_in, 127 | TB_U2.U3.A6_in, 128 | TB_U2.U3.A7_in}, 129 | 130 | 131 | {TB_U2.U3.P0_in, 132 | TB_U2.U3.P1_in, 133 | TB_U2.U3.P2_in, 134 | TB_U2.U3.P3_in, 135 | TB_U2.U3.P4_in, 136 | TB_U2.U3.P5_in, 137 | TB_U2.U3.P6_in, 138 | TB_U2.U3.P7_in}, 139 | 140 | 141 | TB_U2.U3.Dx, 142 | TB_U2.sync_error, 143 | TB_U2.U3.block_count, 144 | TB_U2.U3.NEXT_STATE 145 | ); 146 | 147 | 148 | endmodule 149 | 150 | 151 | 152 | 153 | 154 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/testvectors_213.txt: -------------------------------------------------------------------------------- 1 | 0110_1100_1010_0011_0010 //0 {6,c,a,3,2} 2 | 0101_0101_0101_0101_0101 //1 {5,5,5,5,5} 3 | 1010_1010_1010_1010_1010 //2 {a,a,a,a,a} 4 | 0000_0000_0000_0000_0000 //3 {0,0,0,0,0} 5 | 0001_1011_0001_1011_0001 //4 {1,b,1,b,1} 6 | 0010_0011_1010_1100_0110 //5 {2,3,a,c,6} 7 | 0001_0010_0011_0100_0101 //6 {1,2,3,4,5} 8 | 0110_1100_1010_0011_0010 //7 {6,c,a,3,2} 9 | 0101_0100_0011_0010_0001 //8 {5,4,3,2,1} 10 | 1111_1111_1111_1111_1111 //9 {f,f,f,f,f} 11 | -------------------------------------------------------------------------------- /Vit_e213/New_Vit_e213/verilog.fsdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/New_Vit_e213/verilog.fsdb -------------------------------------------------------------------------------- /Vit_e213/VIT_ENC.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module VIT_ENC.v 3 | 4 | Implements a (2,1,3) convolutional encoder 5 | 6 | ============================================================*/ 7 | 8 | `timescale 1 ns/1 ns 9 | 10 | module VIT_ENC (Vx,Ux,tb_en,clock,reset); 11 | 12 | `include "params_e213.inc" 13 | 14 | output [`n-1:0] Vx; 15 | input [`k-1:0] Ux; 16 | input tb_en; 17 | input clock; 18 | input reset; 19 | 20 | reg [`m:0] encoder_reg; 21 | 22 | always @(posedge clock or posedge reset) 23 | begin 24 | if(reset) 25 | encoder_reg <= 4'b0; 26 | 27 | if (tb_en==1'b0) 28 | encoder_reg <= {Ux, encoder_reg[3:1]}; 29 | end 30 | 31 | assign Vx[1] = encoder_reg[3]^encoder_reg[1]^encoder_reg[0]; 32 | assign Vx[0] = encoder_reg[3]^encoder_reg[2]^encoder_reg[1]^encoder_reg[0]; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213.bgn: -------------------------------------------------------------------------------- 1 | Release v3.3.07i - Bitgen D.26 2 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 3 | 4 | Loading design for application Bitgen from file 5 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ncd. 6 | 7 | Note: MYXILINX = "/hwapps/xilinx/2.1iV1000E-BG728" 8 | Any Xilinx data file(s) found in this area will override the equivalent file(s) 9 | in the XILINX area. 10 | 11 | "eVITERBI_213" is an NCD, version 2.35, device xcv50, package tq144, speed 12 | -4 13 | Loading device for application Bitgen from file 'v50.nph' in environment 14 | /hwapps/xilinx/3.3isp7. 15 | Opened constraints file 16 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.pcf. 17 | 18 | Sat Mar 24 22:53:09 2001 19 | 20 | bitgen -b -m -d -w /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ncd /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.rbt /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.pcf 21 | 22 | Creating bit map... 23 | Saving bit stream in 24 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.bit". 25 | Saving bit stream in 26 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.rbt". 27 | Creating bit mask... 28 | Saving mask bit stream in 29 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.msk". 30 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/.chiptmp/eVITERBI_213.bit -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213.bld: -------------------------------------------------------------------------------- 1 | Release v3.3.07i - ngdbuild D.26 2 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: ngdbuild -dd 5 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/ngo -nt timestamp -p 6 | V50TQ144-4 /emc/joshea/JOS/Verilog/Vit_e213/syn/out/eVITERBI_213.edf 7 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ngd 8 | 9 | Launcher: Executing edif2ngd 10 | "/emc/joshea/JOS/Verilog/Vit_e213/syn/out/eVITERBI_213.edf" 11 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/ngo/eVITERBI_213.ngo" 12 | Release v3.3.07i - edif2ngd D.26 13 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 14 | 15 | Note: MYXILINX = "/hwapps/xilinx/2.1iV1000E-BG728" 16 | Any Xilinx data file(s) found in this area will override the equivalent file(s) 17 | in the XILINX area. 18 | 19 | Writing the design to 20 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/ngo/eVITERBI_213.ngo"... 21 | Reading NGO file 22 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/ngo/eVITERBI_213.ngo" ... 23 | Reading component libraries for design expansion... 24 | 25 | Checking timing specifications ... 26 | 27 | Checking expanded design ... 28 | 29 | NGDBUILD Design Results Summary: 30 | Number of errors: 0 31 | Number of warnings: 0 32 | 33 | Writing NGD file 34 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ngd" ... 35 | 36 | Writing NGDBUILD log file 37 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.bld"... 38 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213.msk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/.chiptmp/eVITERBI_213.msk -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ncd -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213.ngd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ngd -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213.pcf: -------------------------------------------------------------------------------- 1 | SCHEMATIC START ; 2 | // created by map version D.26 on Sat Mar 24 22:52:30 2001 3 | SCHEMATIC END ; 4 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=PLACED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213_jtag.bgn: -------------------------------------------------------------------------------- 1 | Release v3.3.07i - Bitgen D.26 2 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 3 | 4 | Loading design for application Bitgen from file 5 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ncd. 6 | 7 | Note: MYXILINX = "/hwapps/xilinx/2.1iV1000E-BG728" 8 | Any Xilinx data file(s) found in this area will override the equivalent file(s) 9 | in the XILINX area. 10 | 11 | "eVITERBI_213" is an NCD, version 2.35, device xcv50, package tq144, speed 12 | -4 13 | Loading device for application Bitgen from file 'v50.nph' in environment 14 | /hwapps/xilinx/3.3isp7. 15 | Opened constraints file 16 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.pcf. 17 | 18 | Sat Mar 24 22:53:19 2001 19 | 20 | bitgen -d -g startupclk:jtagclk -w /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ncd /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213_jtag.bit /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.pcf 21 | 22 | Creating bit map... 23 | Saving bit stream in 24 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213_jtag.bit". 25 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213_jtag.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/.chiptmp/eVITERBI_213_jtag.bit -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213_m.mrp: -------------------------------------------------------------------------------- 1 | 2 | Xilinx Mapping Report File for Design 'eVITERBI_213' 3 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 4 | 5 | Design Information 6 | ------------------ 7 | Command Line : map -u -p V50TQ144-4 -pr b -o 8 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213_m.ncd 9 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ngd 10 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.pcf 11 | Target Device : xv50 12 | Target Package : tq144 13 | Target Speed : -4 14 | Mapper Version : virtex -- D.26 15 | Mapped Date : Sat Mar 24 22:52:23 2001 16 | 17 | Design Summary 18 | -------------- 19 | Number of errors: 0 20 | Number of warnings: 6 21 | Number of Slices: 295 out of 768 38% 22 | Number of Slices containing 23 | unrelated logic: 0 out of 295 0% 24 | Number of Slice Flip Flops: 256 out of 1,536 16% 25 | Number of 4 input LUTs: 443 out of 1,536 28% 26 | Number of Tbufs: 1 out of 832 1% 27 | Total equivalent gate count for design: 4,760 28 | 29 | Table of Contents 30 | ----------------- 31 | Section 1 - Errors 32 | Section 2 - Warnings 33 | Section 3 - Design Attributes 34 | Section 4 - Removed Logic Summary 35 | Section 5 - Removed Logic 36 | Section 6 - Added Logic 37 | Section 7 - Expanded Logic 38 | Section 8 - Signal Cross-Reference 39 | Section 9 - Symbol Cross-Reference 40 | Section 10 - IOB Properties 41 | Section 11 - RPMs 42 | Section 12 - Guide Report 43 | Section 13 - Area Group Summary 44 | Section 14 - Modular Design Summary 45 | 46 | Section 1 - Errors 47 | ------------------ 48 | 49 | Section 2 - Warnings 50 | -------------------- 51 | WARNING:DesignRules:367 - Netcheck: Loadless. Net Dx<0> has no load. 52 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net clock has no source. 53 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net reset has no source. 54 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net Rx<1> has no source. 55 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net Rx<0> has no source. 56 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net seq_ready has no source. 57 | 58 | Section 3 - Design Attributes 59 | ----------------------------- 60 | 61 | Section 4 - Removed Logic Summary 62 | --------------------------------- 63 | 4 block(s) optimized away 64 | 65 | Section 5 - Removed Logic 66 | ------------------------- 67 | 68 | Optimized Block(s): 69 | TYPE BLOCK 70 | VCC U3/C1810 71 | GND U3/C1811 72 | GND U3/SE_1/C35 73 | FDC U3/SE_1/error_reg 74 | 75 | To enable printing of redundant blocks removed and signals merged, set the 76 | detailed map report option and rerun map. 77 | 78 | Section 6 - Added Logic 79 | ----------------------- 80 | 81 | Section 7 - Expanded Logic 82 | -------------------------- 83 | To enable this section, set the detailed map report option and rerun map. 84 | 85 | Section 8 - Signal Cross-Reference 86 | ---------------------------------- 87 | To enable this section, set the detailed map report option and rerun map. 88 | 89 | Section 9 - Symbol Cross-Reference 90 | ---------------------------------- 91 | To enable this section, set the detailed map report option and rerun map. 92 | 93 | Section 10 - IOB Properties 94 | --------------------------- 95 | 96 | Section 11 - RPMs 97 | ----------------- 98 | 99 | Section 12 - Guide Report 100 | ------------------------- 101 | Guide not run on this design. 102 | 103 | Section 13 - Area Group Summary 104 | ------------------------------- 105 | No area groups were found in this design. 106 | 107 | Section 14 - Modular Design Summary 108 | ----------------------------------- 109 | Modular Design not used for this design. 110 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213_m.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/.chiptmp/eVITERBI_213_m.ncd -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/eVITERBI_213_m.ngm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/.chiptmp/eVITERBI_213_m.ngm -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/ngo/eVITERBI_213.ngo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/.chiptmp/ngo/eVITERBI_213.ngo -------------------------------------------------------------------------------- /Vit_e213/chip/out/.chiptmp/ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | /emc/joshea/JOS/Verilog/Vit_e213/syn/out/eVITERBI_213.edf 985492278 2 | OK 3 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/eVITERBI_213.bld: -------------------------------------------------------------------------------- 1 | Release v3.3.07i - ngdbuild D.26 2 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: ngdbuild -dd 5 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/ngo -nt timestamp -p 6 | V50TQ144-4 /emc/joshea/JOS/Verilog/Vit_e213/syn/out/eVITERBI_213.edf 7 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ngd 8 | 9 | Launcher: Executing edif2ngd 10 | "/emc/joshea/JOS/Verilog/Vit_e213/syn/out/eVITERBI_213.edf" 11 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/ngo/eVITERBI_213.ngo" 12 | Release v3.3.07i - edif2ngd D.26 13 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 14 | 15 | Note: MYXILINX = "/hwapps/xilinx/2.1iV1000E-BG728" 16 | Any Xilinx data file(s) found in this area will override the equivalent file(s) 17 | in the XILINX area. 18 | 19 | Writing the design to 20 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/ngo/eVITERBI_213.ngo"... 21 | Reading NGO file 22 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/ngo/eVITERBI_213.ngo" ... 23 | Reading component libraries for design expansion... 24 | 25 | Checking timing specifications ... 26 | 27 | Checking expanded design ... 28 | 29 | NGDBUILD Design Results Summary: 30 | Number of errors: 0 31 | Number of warnings: 0 32 | 33 | Writing NGD file 34 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ngd" ... 35 | 36 | Writing NGDBUILD log file 37 | "/emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.bld"... 38 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/eVITERBI_213.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/eVITERBI_213.ncd -------------------------------------------------------------------------------- /Vit_e213/chip/out/eVITERBI_213.ngd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/eVITERBI_213.ngd -------------------------------------------------------------------------------- /Vit_e213/chip/out/eVITERBI_213.pcf: -------------------------------------------------------------------------------- 1 | SCHEMATIC START ; 2 | // created by map version D.26 on Sat Mar 24 22:52:30 2001 3 | SCHEMATIC END ; 4 | -------------------------------------------------------------------------------- /Vit_e213/chip/out/eVITERBI_213_jtag.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/chip/out/eVITERBI_213_jtag.bit -------------------------------------------------------------------------------- /Vit_e213/chip/out/eVITERBI_213_m.mrp: -------------------------------------------------------------------------------- 1 | 2 | Xilinx Mapping Report File for Design 'eVITERBI_213' 3 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 4 | 5 | Design Information 6 | ------------------ 7 | Command Line : map -u -p V50TQ144-4 -pr b -o 8 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213_m.ncd 9 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.ngd 10 | /emc/joshea/JOS/Verilog/Vit_e213/chip/out/.chiptmp/eVITERBI_213.pcf 11 | Target Device : xv50 12 | Target Package : tq144 13 | Target Speed : -4 14 | Mapper Version : virtex -- D.26 15 | Mapped Date : Sat Mar 24 22:52:23 2001 16 | 17 | Design Summary 18 | -------------- 19 | Number of errors: 0 20 | Number of warnings: 6 21 | Number of Slices: 295 out of 768 38% 22 | Number of Slices containing 23 | unrelated logic: 0 out of 295 0% 24 | Number of Slice Flip Flops: 256 out of 1,536 16% 25 | Number of 4 input LUTs: 443 out of 1,536 28% 26 | Number of Tbufs: 1 out of 832 1% 27 | Total equivalent gate count for design: 4,760 28 | 29 | Table of Contents 30 | ----------------- 31 | Section 1 - Errors 32 | Section 2 - Warnings 33 | Section 3 - Design Attributes 34 | Section 4 - Removed Logic Summary 35 | Section 5 - Removed Logic 36 | Section 6 - Added Logic 37 | Section 7 - Expanded Logic 38 | Section 8 - Signal Cross-Reference 39 | Section 9 - Symbol Cross-Reference 40 | Section 10 - IOB Properties 41 | Section 11 - RPMs 42 | Section 12 - Guide Report 43 | Section 13 - Area Group Summary 44 | Section 14 - Modular Design Summary 45 | 46 | Section 1 - Errors 47 | ------------------ 48 | 49 | Section 2 - Warnings 50 | -------------------- 51 | WARNING:DesignRules:367 - Netcheck: Loadless. Net Dx<0> has no load. 52 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net clock has no source. 53 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net reset has no source. 54 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net Rx<1> has no source. 55 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net Rx<0> has no source. 56 | WARNING:DesignRules:368 - Netcheck: Sourceless. Net seq_ready has no source. 57 | 58 | Section 3 - Design Attributes 59 | ----------------------------- 60 | 61 | Section 4 - Removed Logic Summary 62 | --------------------------------- 63 | 4 block(s) optimized away 64 | 65 | Section 5 - Removed Logic 66 | ------------------------- 67 | 68 | Optimized Block(s): 69 | TYPE BLOCK 70 | VCC U3/C1810 71 | GND U3/C1811 72 | GND U3/SE_1/C35 73 | FDC U3/SE_1/error_reg 74 | 75 | To enable printing of redundant blocks removed and signals merged, set the 76 | detailed map report option and rerun map. 77 | 78 | Section 6 - Added Logic 79 | ----------------------- 80 | 81 | Section 7 - Expanded Logic 82 | -------------------------- 83 | To enable this section, set the detailed map report option and rerun map. 84 | 85 | Section 8 - Signal Cross-Reference 86 | ---------------------------------- 87 | To enable this section, set the detailed map report option and rerun map. 88 | 89 | Section 9 - Symbol Cross-Reference 90 | ---------------------------------- 91 | To enable this section, set the detailed map report option and rerun map. 92 | 93 | Section 10 - IOB Properties 94 | --------------------------- 95 | 96 | Section 11 - RPMs 97 | ----------------- 98 | 99 | Section 12 - Guide Report 100 | ------------------------- 101 | Guide not run on this design. 102 | 103 | Section 13 - Area Group Summary 104 | ------------------------------- 105 | No area groups were found in this design. 106 | 107 | Section 14 - Modular Design Summary 108 | ----------------------------------- 109 | Modular Design not used for this design. 110 | -------------------------------------------------------------------------------- /Vit_e213/chip/scr/eVITERBI_213_ngdbuild.nav: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /Vit_e213/e213_build.script: -------------------------------------------------------------------------------- 1 | #!/bin/csh -f 2 | ngdbuild -p 4028XLABG256-09 eVITERBI_213.sedif 3 | map -oe high eVITERBI_213.ngd 4 | par -c 1 -d 1 eVITERBI_213.ncd -w eVITERBI_r_213.ncd 5 | 6 | -------------------------------------------------------------------------------- /Vit_e213/e213_synth.script: -------------------------------------------------------------------------------- 1 | /* =======================================================*/ 2 | /* Synopsys Script */ 3 | /* (2,1,3) Efficient Backward Label Viterbi Decoder */ 4 | /* Targets a Xilinx XC4028XLA-09 BG256 */ 5 | /* =======================================================*/ 6 | 7 | 8 | TOP = eVITERBI_213 9 | edifout_design_name = eVITERBI_213 10 | designer = "John O'Shea" 11 | company = "EMC Corporation" 12 | part = "XC4028XLABG256-09" 13 | 14 | sh "rm -rf WORK; mkdir WORK" 15 | 16 | read -format verilog "eBMU_213.v" 17 | read -format verilog "eACS_213.v" 18 | read -format verilog "eACSU_213.v" 19 | read -format verilog "eSYNCERR_213.v" 20 | read -format verilog "eTBDECISION_213.v" 21 | read -format verilog "eCONTROL_213.v" 22 | read -format verilog "eVITERBI_213.v" 23 | 24 | set_operating_conditions -library "xprim_4028xla-09" "WCCOM" 25 | current_design eVITERBI_213 26 | uniquify 27 | remove_constraint -all 28 | 29 | create_clock -name "clock" -period 50 {"clock"} 30 | set_input_delay 5.0 -clock clock all_inputs() - clock 31 | set_output_delay 5.0 -clock clock all_outputs() 32 | set_max_delay 100 -to find(port,Dx) 33 | 34 | 35 | set_port_is_pad "*" 36 | set_pad_type -no_clock {"clock"} 37 | set_pad_type -exact BUFGP_F{"clock"} 38 | set_pad_type -slewrate HIGH all_outputs() 39 | insert_pads 40 | 41 | compile -map_effort high 42 | 43 | set_attribute eVITERBI_213 "part" -type string part 44 | 45 | ungroup -all -flatten 46 | 47 | write -format edif -hierarchy -output eVITERBI_213.sedif 48 | 49 | write -format db -hierarchy -output eVITERBI_213.db 50 | 51 | exit 52 | 53 | -------------------------------------------------------------------------------- /Vit_e213/eACS_213.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module eACS_213.v 3 | 4 | ACS Block for (2,1,3) backward label decoder 5 | 6 | ============================================================*/ 7 | 8 | `timescale 1 ns/1 ns 9 | 10 | module eACS_213 (acs_ppm_out, acs_Bx_out, 11 | acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb); 12 | 13 | 14 | 15 | `include "params_e213.inc" 16 | 17 | output [`W-1:0] acs_ppm_out; 18 | output [`k-1:0] acs_Bx_out; 19 | 20 | input [`W-1:0] acs_ppm_ina; 21 | input [`W-1:0] acs_ppm_inb; 22 | input [`W-1:0] HD_ina; 23 | input [`W-1:0] HD_inb; 24 | 25 | 26 | reg [`W-1:0] acs_ppm_out; 27 | reg [`k-1:0] acs_Bx_out; 28 | 29 | reg [`W-1:0] suma; 30 | reg [`W-1:0] sumb; 31 | 32 | 33 | 34 | always @(acs_ppm_ina or HD_ina) 35 | begin 36 | if (acs_ppm_ina==4'b1111) 37 | suma = acs_ppm_ina; 38 | else 39 | suma = acs_ppm_ina + HD_ina; 40 | end 41 | 42 | 43 | 44 | 45 | always @(acs_ppm_inb or HD_inb) 46 | begin 47 | if (acs_ppm_inb==4'b1111) 48 | sumb = acs_ppm_inb; 49 | else 50 | sumb = acs_ppm_inb + HD_inb; 51 | 52 | end 53 | 54 | 55 | 56 | always @(suma or sumb) 57 | begin 58 | if (suma <=sumb) 59 | begin 60 | acs_ppm_out =suma; 61 | acs_Bx_out =1'b0; //Select Upper Backward Path 62 | end 63 | else 64 | begin 65 | acs_ppm_out =sumb; 66 | acs_Bx_out =1'b1; //Select Lower Backward Path 67 | end 68 | end 69 | 70 | 71 | 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /Vit_e213/eBMU_213.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module eBMU_213.v 3 | 4 | Branch Metric Computation Unit for (2,1,3) backward label Viterbi Decoder. 5 | 6 | ===========================================================================*/ 7 | 8 | module eBMU_213(HD1, HD2, HD3, HD4, 9 | HD5, HD6, HD7, HD8, 10 | HD9, HD10, HD11, HD12, 11 | HD13, HD14, HD15, HD16, 12 | Rx 13 | ); 14 | 15 | `include "params_e213.inc" 16 | 17 | output [1:0] HD1; 18 | output [1:0] HD2; 19 | output [1:0] HD3; 20 | output [1:0] HD4; 21 | output [1:0] HD5; 22 | output [1:0] HD6; 23 | output [1:0] HD7; 24 | output [1:0] HD8; 25 | output [1:0] HD9; 26 | output [1:0] HD10; 27 | output [1:0] HD11; 28 | output [1:0] HD12; 29 | output [1:0] HD13; 30 | output [1:0] HD14; 31 | output [1:0] HD15; 32 | output [1:0] HD16; 33 | 34 | 35 | input [1:0] Rx; 36 | 37 | reg [1:0] HD1; 38 | reg [1:0] HD2; 39 | reg [1:0] HD3; 40 | reg [1:0] HD4; 41 | reg [1:0] HD5; 42 | reg [1:0] HD6; 43 | reg [1:0] HD7; 44 | reg [1:0] HD8; 45 | reg [1:0] HD9; 46 | reg [1:0] HD10; 47 | reg [1:0] HD11; 48 | reg [1:0] HD12; 49 | reg [1:0] HD13; 50 | reg [1:0] HD14; 51 | reg [1:0] HD15; 52 | reg [1:0] HD16; 53 | 54 | 55 | 56 | always @(Rx) 57 | begin 58 | 59 | case (Rx)//synopsys full_case 60 | 61 | 2'b00: begin 62 | HD1 <=2'b00; HD2 <=2'b10; HD3 <=2'b01; HD4 <=2'b01; 63 | HD5 <=2'b10; HD6 <=2'b00; HD7 <=2'b01; HD8 <=2'b01; 64 | HD9 <=2'b10; HD10<=2'b00; HD11<=2'b01; HD12<=2'b01; 65 | HD13<=2'b00; HD14<=2'b10; HD15<=2'b01; HD16<=2'b01; 66 | end 67 | 68 | 2'b01: begin 69 | HD1 <=2'b01; HD2 <=2'b01; HD3 <=2'b00; HD4 <=2'b10; 70 | HD5 <=2'b01; HD6 <=2'b01; HD7 <=2'b10; HD8 <=2'b00; 71 | HD9 <=2'b01; HD10<=2'b01; HD11<=2'b10; HD12<=2'b00; 72 | HD13<=2'b01; HD14<=2'b01; HD15<=2'b00; HD16<=2'b10; 73 | end 74 | 75 | 2'b10: begin 76 | HD1 <=2'b01; HD2 <=2'b01; HD3 <=2'b10; HD4 <=2'b00; 77 | HD5 <=2'b01; HD6 <=2'b01; HD7 <=2'b00; HD8 <=2'b10; 78 | HD9 <=2'b01; HD10<=2'b01; HD11<=2'b00; HD12<=2'b10; 79 | HD13<=2'b01; HD14<=2'b01; HD15<=2'b10; HD16<=2'b00; 80 | end 81 | 82 | 2'b11: begin 83 | HD1 <=2'b10; HD2 <=2'b00; HD3 <=2'b01; HD4 <=2'b01; 84 | HD5 <=2'b00; HD6 <=2'b10; HD7 <=2'b01; HD8 <=2'b01; 85 | HD9 <=2'b00; HD10<=2'b10; HD11<=2'b01; HD12<=2'b01; 86 | HD13<=2'b10; HD14<=2'b00; HD15<=2'b01; HD16<=2'b01; 87 | end 88 | endcase // case(Rx) 89 | end 90 | 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /Vit_e213/eSYNCERR_213.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module eSYNCERR_213.v 3 | 4 | Out of Synch Error Detector for (2,1,3) Viterbi decoder. 5 | 6 | ===========================================================================*/ 7 | `timescale 1 ns/1 ns 8 | 9 | 10 | module eSYNCERR_213 (error, stage, we, metric, reset, clock 11 | ); 12 | 13 | 14 | output error; 15 | 16 | input [3:0] stage; 17 | input [2:0] metric; 18 | input we; 19 | input reset; 20 | input clock; 21 | reg error; 22 | 23 | 24 | always @(posedge clock or posedge reset) 25 | begin 26 | if (reset) 27 | error <=1'b0; 28 | else 29 | begin 30 | if (we && stage >=4'b0011 && metric >4'b1000) 31 | error <=1'b1; 32 | else 33 | error <=1'b0; 34 | end 35 | end 36 | 37 | 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /Vit_e213/eTBDECISION_213.v: -------------------------------------------------------------------------------- 1 | /*================================================================= 2 | module eTBDECISION_213.v 3 | 4 | Traceback Decision Unit for (2,1,3) decoder 5 | 6 | Determine pointer to initial state for traceback 7 | by finding the state with minimum accumulated metric 8 | 9 | John O'Shea, joshea@emc.com 10 | ==================================================================*/ 11 | 12 | `timescale 1 ns/1 ns 13 | 14 | module eTBDECISION_213 (min_state,in0,in1,in2,in3,in4,in5,in6,in7); 15 | 16 | 17 | `include "params_e213.inc" 18 | 19 | output [`m-1:0] min_state; 20 | 21 | 22 | input [`W-1:0] in0; 23 | input [`W-1:0] in1; 24 | input [`W-1:0] in2; 25 | input [`W-1:0] in3; 26 | input [`W-1:0] in4; 27 | input [`W-1:0] in5; 28 | input [`W-1:0] in6; 29 | input [`W-1:0] in7; 30 | 31 | reg [`m-1:0] min_state; 32 | reg [`W-1:0] min_01; 33 | reg [`W-1:0] min_23; 34 | reg [`W-1:0] min_45; 35 | reg [`W-1:0] min_67; 36 | reg [`W-1:0] min_0123; 37 | reg [`W-1:0] min_4567; 38 | reg [`W-1:0] min_metric; 39 | 40 | 41 | 42 | always @(in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) 43 | begin 44 | if (in0 <=in1) 45 | min_01=in0; 46 | else 47 | min_01=in1; 48 | 49 | if (in2 <=in3) 50 | min_23=in2; 51 | else 52 | min_23=in3; 53 | 54 | if (in4 <=in5) 55 | min_45=in4; 56 | else 57 | min_45=in5; 58 | 59 | if (in6 <=in7) 60 | min_67=in6; 61 | else 62 | min_67=in7; 63 | 64 | if (min_01 <= min_23) 65 | min_0123 = min_01; 66 | else 67 | min_0123 = min_23; 68 | 69 | if (min_45 <= min_67) 70 | min_4567 = min_45; 71 | else 72 | min_4567 = min_67; 73 | 74 | if (min_0123 <= min_4567) 75 | min_metric = min_0123; 76 | else 77 | min_metric = min_4567; 78 | end 79 | 80 | 81 | always @ (in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 or min_metric) 82 | begin 83 | if (in0==min_metric) 84 | min_state = 3'b000; 85 | else if (in1==min_metric) 86 | min_state = 3'b001; 87 | else if (in2==min_metric) 88 | min_state = 3'b010; 89 | else if (in3==min_metric) 90 | min_state = 3'b011; 91 | else if (in4==min_metric) 92 | min_state = 3'b100; 93 | else if (in5==min_metric) 94 | min_state = 3'b101; 95 | else if (in6==min_metric) 96 | min_state = 3'b110; 97 | else 98 | min_state = 3'b111; 99 | end 100 | 101 | endmodule 102 | 103 | 104 | -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_213.bld: -------------------------------------------------------------------------------- 1 | Release v3.1.02i - ngdbuild D.19 2 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: ngdbuild -p 4028XLABG256-09 eVITERBI_213.sedif 5 | 6 | Launcher: Executing edif2ngd -l synopsys "eVITERBI_213.sedif" 7 | "eVITERBI_213.ngo" 8 | Release v3.1.02i - edif2ngd D.19 9 | Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. 10 | 11 | Note: MYXILINX = "/hwapps/xilinx/2.1iV1000E-BG728" 12 | Any Xilinx data file(s) found in this area will override the equivalent file(s) 13 | in the XILINX area. 14 | 15 | Writing the design to "eVITERBI_213.ngo"... 16 | Reading NGO file "/emc/joshea/Files/Verilog/Vit_e213/eVITERBI_213.ngo" ... 17 | Reading component libraries for design expansion... 18 | 19 | Checking timing specifications ... 20 | 21 | Checking expanded design ... 22 | 23 | NGDBUILD Design Results Summary: 24 | Number of errors: 0 25 | Number of warnings: 0 26 | 27 | Writing NGD file "eVITERBI_213.ngd" ... 28 | 29 | Writing NGDBUILD log file "eVITERBI_213.bld"... 30 | -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_213.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/eVITERBI_213.db -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_213.mdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/eVITERBI_213.mdf -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_213.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/eVITERBI_213.ncd -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_213.ngd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/eVITERBI_213.ngd -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_213.ngm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/eVITERBI_213.ngm -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_213.ngo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/eVITERBI_213.ngo -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_213.pcf: -------------------------------------------------------------------------------- 1 | SCHEMATIC START ; 2 | // created by map version D.19 on Sat Feb 10 19:00:23 2001 3 | SCHEMATIC END ; 4 | -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_213_ngdbuild.nav: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_r_213.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/eVITERBI_r_213.ncd -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_r_213.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /Vit_e213/netlist.lst: -------------------------------------------------------------------------------- 1 | /emc/joshea/Files/Verilog/Vit_e213/eVITERBI_213.sedif 981849530 2 | OK 3 | -------------------------------------------------------------------------------- /Vit_e213/params_e213.inc: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | params_e213.inc 3 | 4 | Constant Definitions for use in efficient 5 | (2,1,3) backward label Viterbi Decoder 6 | 7 | John O'Shea, joshea@emc.com 8 | 9 | ===========================================================================*/ 10 | 11 | `define CLOCK_PERIOD 40 12 | `define BLOCK_LEN 20 13 | `define NUM_VECTORS 10 14 | 15 | `define W 4 16 | `define T 12 17 | `define n 2 18 | `define k 1 19 | `define m 3 20 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /Vit_e213/sig.rc: -------------------------------------------------------------------------------- 1 | Magic 271485 2 | Revision 1.0 3 | 4 | ; Window Layout 5 | viewPort 2 8 1908 1164 148 134 6 | 7 | ; File list: 8 | ; openDirFile [-d delimiter] [-s time_offset] path_name file_name 9 | openDirFile -d / "/emc/joshea/Files/Verilog/Vit_e213" "verilog.fsdb" 10 | 11 | ; file time scale: 12 | ; fileTimeScale ### s|ms|us|ns|ps 13 | 14 | ; signal spacing: 15 | signalSpacing 3 16 | 17 | ; windowTimeUnit is used for zoom, cursor & marker 18 | ; waveform viewport range 19 | zoom 0.000000 500.000000 20 | cursor 2660.000000 21 | marker 0.000000 22 | 23 | ; user define markers 24 | ; userMarker time_pos marker_name 25 | ; visible top row signal index 26 | top 0 27 | ; marker line index 28 | markerPos 6 29 | 30 | ; Run Time Signal and Member 31 | ; addRunTimeSig 32 | activeDirFile "/emc/joshea/Files/Verilog/Vit_e213" "verilog.fsdb" 33 | 34 | userBusMem /tb_e213/TB_U2/U3/A0_in[3:0] 35 | userBusMem /tb_e213/TB_U2/U3/A1_in[3:0] 36 | userBusMem /tb_e213/TB_U2/U3/A2_in[3:0] 37 | userBusMem /tb_e213/TB_U2/U3/A3_in[3:0] 38 | userBusMem /tb_e213/TB_U2/U3/A4_in[3:0] 39 | userBusMem /tb_e213/TB_U2/U3/A5_in[3:0] 40 | userBusMem /tb_e213/TB_U2/U3/A6_in[3:0] 41 | userBusMem /tb_e213/TB_U2/U3/A7_in[3:0] 42 | saveRunSig A_in[31:0] 43 | userBusMem /tb_e213/TB_U2/U3/A0_out[3:0] 44 | userBusMem /tb_e213/TB_U2/U3/A1_out[3:0] 45 | userBusMem /tb_e213/TB_U2/U3/A2_out[3:0] 46 | userBusMem /tb_e213/TB_U2/U3/A3_out[3:0] 47 | userBusMem /tb_e213/TB_U2/U3/A4_out[3:0] 48 | userBusMem /tb_e213/TB_U2/U3/A5_out[3:0] 49 | userBusMem /tb_e213/TB_U2/U3/A6_out[3:0] 50 | userBusMem /tb_e213/TB_U2/U3/A7_out[3:0] 51 | saveRunSig A_out[31:0] 52 | userBusMem /tb_e213/TB_U2/U3/P0_in[0:0] 53 | userBusMem /tb_e213/TB_U2/U3/P1_in[0:0] 54 | userBusMem /tb_e213/TB_U2/U3/P2_in[0:0] 55 | userBusMem /tb_e213/TB_U2/U3/P3_in[0:0] 56 | userBusMem /tb_e213/TB_U2/U3/P4_in[0:0] 57 | userBusMem /tb_e213/TB_U2/U3/P5_in[0:0] 58 | userBusMem /tb_e213/TB_U2/U3/P6_in[0:0] 59 | userBusMem /tb_e213/TB_U2/U3/P7_in[0:0] 60 | saveRunSig P_in[7:0] 61 | 62 | ; analog to digital list 63 | ; allAtoD sig_name low_threshold high_threshold member_sig_name 64 | 65 | ; logical expression list 66 | ; addExprSig expr_name expression_string 67 | 68 | ; analog expression list 69 | ; addAnaExprSig expr_name expression_string 70 | 71 | ; event list 72 | ; addEvent event_name event_expression 73 | ; curEvent event_name 74 | 75 | 76 | 77 | SEQUENCE_BEGIN 78 | 79 | 80 | SEQUENCE_END 81 | 82 | 83 | 84 | ; toolbar current search type 85 | ; curSTATUS search_type 86 | curSTATUS ByChange 87 | 88 | 89 | addGroup "G1" 90 | addSignal -h 15 /tb_e213/TB_U2/clock 91 | addSignal -h 15 /tb_e213/TB_U2/reset 92 | addSignal -h 15 /tb_e213/TB_U2/U3/clr 93 | addSignal -h 15 /tb_e213/TB_U2/error 94 | addSignal -h 15 /tb_e213/TB_U1/Ux[0:0] 95 | addSignal -h 15 /tb_e213/TB_U1/Vx[1:0] 96 | addGroup "G2" 97 | addSignal -h 15 /tb_e213/TB_U2/U1/HD[31:0] 98 | addGroup "G3" 99 | addUserBus -h 15 A_in[31:0] 100 | addUserBus -h 15 P_in[7:0] 101 | addUserBus -h 15 A_out[31:0] 102 | addGroup "G4" 103 | addSignal -h 15 /tb_e213/TB_U2/U3/write_ptr[3:0] 104 | addSignal -h 15 /tb_e213/TB_U2/U3/we 105 | addSignal -h 15 /tb_e213/TB_U2/U3/min_state[2:0] 106 | addSignal -h 15 /tb_e213/TB_U2/U3/best_state[2:0] 107 | addSignal -h 15 /tb_e213/TB_U2/U3/te 108 | addSignal -h 15 /tb_e213/TB_U2/U3/trace_ptr[3:0] 109 | addSignal -h 15 /tb_e213/TB_U2/U3/P_1/tb_reg[2:0] 110 | addGroup "G5" 111 | addSignal -h 15 /tb_e213/TB_U2/U3/NEXT_STATE[4:0] 112 | addSignal -h 15 /tb_e213/TB_U2/U3/block_count[4:0] 113 | addSignal -h 15 /tb_e213/TB_U2/U3/oe 114 | addSignal -h 15 /tb_e213/TB_U2/U3/Dx[0:0] 115 | addGroup "G6" 116 | 117 | ; grid status 118 | ; gridSignal signal_name 119 | ; gridEdge 0 | 1 120 | 121 | -------------------------------------------------------------------------------- /Vit_e213/sim_e213.script: -------------------------------------------------------------------------------- 1 | tb_e213.v 2 | VIT_ENC.v 3 | eBMU_213.v 4 | eACS_213.v 5 | eACSU_213.v 6 | eTBDECISION_213.v 7 | eSYNCERR_213.v 8 | eCONTROL_213.v 9 | eVITERBI_213.v 10 | +libext+.v+.V 11 | -y /hwapps/xilinx/M.1.5.i/verilog/src/UNI4000X 12 | -------------------------------------------------------------------------------- /Vit_e213/src/VIT_ENC.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module VIT_ENC.v 3 | 4 | Implements a (2,1,3) convolutional encoder 5 | 6 | John O'Shea, joshea@emc.com 7 | ============================================================*/ 8 | 9 | `timescale 1 ns/1 ns 10 | 11 | module VIT_ENC (Vx,Ux,tb_en,clock,reset); 12 | 13 | `include "params_b213.inc.v" 14 | 15 | output [`n-1:0] Vx; 16 | input [`k-1:0] Ux; 17 | input tb_en; 18 | input clock; 19 | input reset; 20 | 21 | reg [`m:0] encoder_reg; 22 | 23 | always @(posedge clock or posedge reset) 24 | begin 25 | if(reset) 26 | encoder_reg <= 4'b0; 27 | 28 | if (tb_en==1'b0) 29 | encoder_reg <= {Ux, encoder_reg[3:1]}; 30 | end 31 | 32 | assign Vx[1] = encoder_reg[3]^encoder_reg[1]^encoder_reg[0]; 33 | assign Vx[0] = encoder_reg[3]^encoder_reg[2]^encoder_reg[1]^encoder_reg[0]; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /Vit_e213/src/eACS_213.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module eACS_213.v 3 | 4 | ACS Block for (2,1,3) backward label decoder 5 | 6 | John O'Shea, joshea@emc.com 7 | 8 | ============================================================*/ 9 | 10 | `timescale 1 ns/1 ns 11 | 12 | module eACS_213 (acs_ppm_out, acs_Bx_out, 13 | acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb, 14 | ae, clock, reset); 15 | 16 | 17 | 18 | `include "params_e213.inc.v" 19 | 20 | output [`W-1:0] acs_ppm_out; 21 | output [`k-1:0] acs_Bx_out; 22 | 23 | input [`W-1:0] acs_ppm_ina; 24 | input [`W-1:0] acs_ppm_inb; 25 | input [1:0] HD_ina; 26 | input [1:0] HD_inb; 27 | input ae; 28 | input clock; 29 | input reset; 30 | 31 | 32 | reg [`W-1:0] acs_ppm_out; 33 | reg [`k-1:0] acs_Bx_out; 34 | 35 | reg [`W-1:0] suma; 36 | reg [`W-1:0] sumb; 37 | 38 | 39 | 40 | always @(posedge clock or posedge reset) 41 | begin 42 | if (reset) 43 | suma <=0; 44 | else 45 | begin 46 | if (ae && acs_ppm_ina==4'b1111) 47 | suma <= acs_ppm_ina; 48 | else if (ae) 49 | suma <= acs_ppm_ina + HD_ina; 50 | end 51 | end 52 | 53 | always @(posedge clock or posedge reset) 54 | begin 55 | if (reset) 56 | sumb <=0; 57 | else 58 | begin 59 | if (ae && acs_ppm_inb ==4'b1111) 60 | sumb <=acs_ppm_inb; 61 | else if (ae) 62 | sumb <= acs_ppm_inb + HD_inb; 63 | end 64 | end 65 | 66 | 67 | 68 | always @(suma or sumb) 69 | begin 70 | if (suma <=sumb && ae) 71 | begin 72 | acs_ppm_out =suma; 73 | acs_Bx_out =1'b0; //Select Upper Backward Path 74 | end 75 | else 76 | begin 77 | acs_ppm_out =sumb; 78 | acs_Bx_out =1'b1; //Select Lower Backward Path 79 | end 80 | end 81 | 82 | 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /Vit_e213/src/eBMU_213.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module eBMU_213.v 3 | 4 | Branch Metric Computation Unit for (2,1,3) backward label Viterbi Decoder. 5 | 6 | John O'Shea, joshea@emc.com. 7 | 8 | ===========================================================================*/ 9 | 10 | module eBMU_213(HD1, HD2, HD3, HD4, 11 | HD5, HD6, HD7, HD8, 12 | HD9, HD10, HD11, HD12, 13 | HD13, HD14, HD15, HD16, 14 | Rx, le, clock, reset 15 | ); 16 | 17 | `include "params_e213.inc.v" 18 | 19 | output [1:0] HD1; 20 | output [1:0] HD2; 21 | output [1:0] HD3; 22 | output [1:0] HD4; 23 | output [1:0] HD5; 24 | output [1:0] HD6; 25 | output [1:0] HD7; 26 | output [1:0] HD8; 27 | output [1:0] HD9; 28 | output [1:0] HD10; 29 | output [1:0] HD11; 30 | output [1:0] HD12; 31 | output [1:0] HD13; 32 | output [1:0] HD14; 33 | output [1:0] HD15; 34 | output [1:0] HD16; 35 | 36 | 37 | input [1:0] Rx; 38 | input le; 39 | input clock; 40 | input reset; 41 | 42 | reg [1:0] HD1; 43 | reg [1:0] HD2; 44 | reg [1:0] HD3; 45 | reg [1:0] HD4; 46 | reg [1:0] HD5; 47 | reg [1:0] HD6; 48 | reg [1:0] HD7; 49 | reg [1:0] HD8; 50 | reg [1:0] HD9; 51 | reg [1:0] HD10; 52 | reg [1:0] HD11; 53 | reg [1:0] HD12; 54 | reg [1:0] HD13; 55 | reg [1:0] HD14; 56 | reg [1:0] HD15; 57 | reg [1:0] HD16; 58 | 59 | 60 | 61 | always @(posedge clock or posedge reset) 62 | begin 63 | if(reset) 64 | begin 65 | HD1 <=0; HD2 <=0; HD3 <=0; HD4 <=0; 66 | HD5 <=0; HD6 <=0; HD7 <=0; HD8 <=0; 67 | HD9 <=0; HD10<=0; HD11<=0; HD12<=0; 68 | HD13<=0; HD14<=0; HD15<=0; HD16<=0; 69 | end 70 | else if (le) 71 | begin 72 | case (Rx)//synopsys full_case 73 | 74 | 2'b00: begin 75 | HD1 <=2'b00; HD2 <=2'b10; HD3 <=2'b01; HD4 <=2'b01; 76 | HD5 <=2'b10; HD6 <=2'b00; HD7 <=2'b01; HD8 <=2'b01; 77 | HD9 <=2'b10; HD10<=2'b00; HD11<=2'b01; HD12<=2'b01; 78 | HD13<=2'b00; HD14<=2'b10; HD15<=2'b01; HD16<=2'b01; 79 | end 80 | 81 | 2'b01: begin 82 | HD1 <=2'b01; HD2 <=2'b01; HD3 <=2'b00; HD4 <=2'b10; 83 | HD5 <=2'b01; HD6 <=2'b01; HD7 <=2'b10; HD8 <=2'b00; 84 | HD9 <=2'b01; HD10<=2'b01; HD11<=2'b10; HD12<=2'b00; 85 | HD13<=2'b01; HD14<=2'b01; HD15<=2'b00; HD16<=2'b10; 86 | end 87 | 88 | 2'b10: begin 89 | HD1 <=2'b01; HD2 <=2'b01; HD3 <=2'b10; HD4 <=2'b00; 90 | HD5 <=2'b01; HD6 <=2'b01; HD7 <=2'b00; HD8 <=2'b10; 91 | HD9 <=2'b01; HD10<=2'b01; HD11<=2'b00; HD12<=2'b10; 92 | HD13<=2'b01; HD14<=2'b01; HD15<=2'b10; HD16<=2'b00; 93 | end 94 | 95 | 2'b11: begin 96 | HD1 <=2'b10; HD2 <=2'b00; HD3 <=2'b01; HD4 <=2'b01; 97 | HD5 <=2'b00; HD6 <=2'b10; HD7 <=2'b01; HD8 <=2'b01; 98 | HD9 <=2'b00; HD10<=2'b10; HD11<=2'b01; HD12<=2'b01; 99 | HD13<=2'b10; HD14<=2'b00; HD15<=2'b01; HD16<=2'b01; 100 | end 101 | endcase // case(Rx) 102 | end 103 | end 104 | 105 | 106 | endmodule 107 | -------------------------------------------------------------------------------- /Vit_e213/src/eSYNCERR_213.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module eSYNCERR_213.v 3 | 4 | Out of Synch Error Detector for (2,1,3) Viterbi decoder. 5 | 6 | John O'Shea, joshea@emc.com 7 | 8 | ===========================================================================*/ 9 | `timescale 1 ns/1 ns 10 | 11 | 12 | module eSYNCERR_213 (error, stage, we, metric, reset, clock 13 | ); 14 | 15 | 16 | output error; 17 | 18 | input [3:0] stage; 19 | input [2:0] metric; 20 | input we; 21 | input reset; 22 | input clock; 23 | reg error; 24 | 25 | 26 | always @(posedge clock or posedge reset) 27 | begin 28 | if (reset) 29 | error <=1'b0; 30 | else 31 | begin 32 | if (we && stage >=4'b0011 && metric >4'b1000) 33 | error <=1'b1; 34 | else 35 | error <=1'b0; 36 | end 37 | end 38 | 39 | 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /Vit_e213/src/eTBDECISION_213.v: -------------------------------------------------------------------------------- 1 | /*================================================================= 2 | module eTBDECISION_213.v 3 | 4 | Traceback Decision Unit for (2,1,3) decoder 5 | 6 | Determine pointer to initial state for traceback 7 | by finding the state with minimum accumulated metric 8 | 9 | John O'Shea, joshea@emc.com 10 | ==================================================================*/ 11 | 12 | `timescale 1 ns/1 ns 13 | 14 | module eTBDECISION_213 (best_state, 15 | in0, in1, in2, in3, in4, in5, in6, in7); 16 | 17 | 18 | `include "params_e213.inc.v" 19 | 20 | output [`m-1:0] best_state; 21 | 22 | input [`W-1:0] in0; 23 | input [`W-1:0] in1; 24 | input [`W-1:0] in2; 25 | input [`W-1:0] in3; 26 | input [`W-1:0] in4; 27 | input [`W-1:0] in5; 28 | input [`W-1:0] in6; 29 | input [`W-1:0] in7; 30 | 31 | reg [`m-1:0] best_state; 32 | reg [`W-1:0] min_01; 33 | reg [`W-1:0] min_23; 34 | reg [`W-1:0] min_45; 35 | reg [`W-1:0] min_67; 36 | reg [`W-1:0] min_0123; 37 | reg [`W-1:0] min_4567; 38 | reg [`W-1:0] min_metric; 39 | 40 | 41 | 42 | always @(in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) 43 | begin 44 | if (in0 <=in1) 45 | min_01=in0; 46 | else 47 | min_01=in1; 48 | 49 | if (in2 <=in3) 50 | min_23=in2; 51 | else 52 | min_23=in3; 53 | 54 | if (in4 <=in5) 55 | min_45=in4; 56 | else 57 | min_45=in5; 58 | 59 | if (in6 <=in7) 60 | min_67=in6; 61 | else 62 | min_67=in7; 63 | 64 | if (min_01 <= min_23) 65 | min_0123 = min_01; 66 | else 67 | min_0123 = min_23; 68 | 69 | if (min_45 <= min_67) 70 | min_4567 = min_45; 71 | else 72 | min_4567 = min_67; 73 | 74 | if (min_0123 <= min_4567) 75 | min_metric = min_0123; 76 | else 77 | min_metric = min_4567; 78 | end 79 | 80 | 81 | always @ (in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 or min_metric) 82 | begin 83 | if (in0==min_metric) 84 | best_state = 3'b000; 85 | else if (in1==min_metric) 86 | best_state = 3'b001; 87 | else if (in2==min_metric) 88 | best_state = 3'b010; 89 | else if (in3==min_metric) 90 | best_state = 3'b011; 91 | else if (in4==min_metric) 92 | best_state = 3'b100; 93 | else if (in5==min_metric) 94 | best_state = 3'b101; 95 | else if (in6==min_metric) 96 | best_state = 3'b110; 97 | else 98 | best_state = 3'b111; 99 | end 100 | 101 | endmodule 102 | 103 | 104 | -------------------------------------------------------------------------------- /Vit_e213/src/lse.wrk: -------------------------------------------------------------------------------- 1 | FILE_TYPE = LOGIC_DIR; 2 | END. 3 | -------------------------------------------------------------------------------- /Vit_e213/src/nWaveLog/turbo.log: -------------------------------------------------------------------------------- 1 | au time=135350 memory (delta=6525168:8863744 total=6596952:8953856) 2 | -------------------------------------------------------------------------------- /Vit_e213/src/params_e213.inc.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | params_e213.inc 3 | 4 | Constant Definitions for use in a 5 | (2,1,3) efficient backward label Viterbi Decoder 6 | 7 | John O'Shea, joshea@emc.com 8 | 9 | ===========================================================================*/ 10 | 11 | `define CLOCK_PERIOD 40 12 | `define BLOCK_LEN 20 13 | `define NUM_VECTORS 10 14 | 15 | `define N 20 16 | `define W 4 17 | `define n 2 18 | `define k 1 19 | `define m 3 20 | `define T 12 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /Vit_e213/src/params_e213.inc.v~: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | params_e213.inc 3 | 4 | Constant Definitions for use in a 5 | (2,1,3) efficient backward label Viterbi Decoder 6 | 7 | John O'Shea, joshea@emc.com 8 | 9 | ===========================================================================*/ 10 | 11 | `define CLOCK_PERIOD 40 12 | `define BLOCK_LEN 20 13 | `define NUM_VECTORS 10 14 | 15 | `define N 20 16 | `define W 4 17 | `define T 13 18 | `define n 2 19 | `define k 1 20 | `define m 3 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /Vit_e213/src/sim_e213.script: -------------------------------------------------------------------------------- 1 | tb_e213.v 2 | eBMU_213.v 3 | eACS_213.v 4 | eACSU_213.v 5 | eTBDECISION_213.v 6 | eSYNCERR_213.v 7 | eCONTROL_213.v 8 | eVITERBI_213.v 9 | +libext+.v+.V 10 | -y /hwapps/xilinx/M.1.5.i/verilog/src/UNI4000X 11 | -------------------------------------------------------------------------------- /Vit_e213/src/verilog.fsdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/src/verilog.fsdb -------------------------------------------------------------------------------- /Vit_e213/src/vreader.log: -------------------------------------------------------------------------------- 1 | Host command: /hwapps/pe13.6/tools/bin/vreadern 2 | Command arguments: 3 | /emc/joshea/JOS/Verilog/Vit_e213/src/eCONTROL_213.v 4 | 5 | 6 | vreadern version 4.3 Tue Feb 1 23:52:00 PST 1994 (smcc11) 7 | Mar 24, 2001 22:44:47 8 | 9 | * Copyright Cadence Design Systems, Inc. 1991. * 10 | * All Rights Reserved. Licensed Software. * 11 | * Confidential and proprietary information which is the * 12 | * property of Cadence Design Systems, Inc. * 13 | 14 | Analyzing source file "/emc/joshea/JOS/Verilog/Vit_e213/src/eCONTROL_213.v" 15 | Analyzing included file "params_e213.inc.v" 16 | Continuing analyzing of source file "/emc/joshea/JOS/Verilog/Vit_e213/src/eCONTROL_213.v" 17 | 18 | Warning! Ignoring bit range on parameter declaration [Verilog Reader DS 19 | Builder-IROPD] 20 | "/emc/joshea/JOS/Verilog/Vit_e213/src/eCONTROL_21 21 | 3.v", 107: 22 | 100 cpu secs to build 23 | 1 warning 24 | 25 | End of vreadern version 4.3 Tue Feb 1 23:52:00 PST 1994 (smcc11) 26 | Mar 24, 2001 22:44:47 27 | 28 | -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/chips/eVITERBI_213_syn-Optimized/eVITERBI_213_syn-Optimized.cst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/syn/out/eVITERBI_213_proj/chips/eVITERBI_213_syn-Optimized/eVITERBI_213_syn-Optimized.cst -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/chips/eVITERBI_213_syn-Optimized/eVITERBI_213_syn-Optimized.rpt: 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(HDL-180) 5 | 6 | Inferred memory devices in process 7 | in routine eACS_213 line 40 in file 8 | '/emc/joshea/JOS/Verilog/Vit_e213/src/eACS_213.v'. 9 | =============================================================================== 10 | | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | 11 | =============================================================================== 12 | | suma_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | 13 | =============================================================================== 14 | 15 | suma_reg (width 4) 16 | ------------------ 17 | Async-reset: reset 18 | 19 | 20 | 21 | Inferred memory devices in process 22 | in routine eACS_213 line 53 in file 23 | '/emc/joshea/JOS/Verilog/Vit_e213/src/eACS_213.v'. 24 | =============================================================================== 25 | | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | 26 | =============================================================================== 27 | | sumb_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | 28 | =============================================================================== 29 | 30 | sumb_reg (width 4) 31 | ------------------ 32 | Async-reset: reset 33 | 34 | 35 | Writing to hnl file './eVITERBI_213_proj/workdirs/WORK/eACS_213.hnl' 36 | -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eACS_213.sts: -------------------------------------------------------------------------------- 1 | 3 -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eBMU_213%verilog.syn: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eBMU_213.hnl -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eBMU_213.out: -------------------------------------------------------------------------------- 1 | 2 | Statistics for case statements in always block at line 61 in file 3 | '/emc/joshea/JOS/Verilog/Vit_e213/src/eBMU_213.v' 4 | =============================================== 5 | | Line | full/ parallel | 6 | =============================================== 7 | | 74 | user/auto | 8 | =============================================== 9 | 10 | Inferred memory devices in process 11 | in routine eBMU_213 line 61 in file 12 | '/emc/joshea/JOS/Verilog/Vit_e213/src/eBMU_213.v'. 13 | =============================================================================== 14 | | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | 15 | =============================================================================== 16 | | HD1_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 17 | | HD2_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 18 | | HD3_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 19 | | HD4_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 20 | | HD5_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 21 | | HD6_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 22 | | HD7_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 23 | | HD8_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 24 | | HD9_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 25 | | HD10_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 26 | | HD11_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 27 | | HD12_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 28 | | HD13_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 29 | | HD14_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 30 | | HD15_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 31 | | HD16_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N | 32 | =============================================================================== 33 | 34 | HD1_reg (width 2) 35 | ----------------- 36 | Async-reset: reset 37 | 38 | 39 | HD2_reg (width 2) 40 | ----------------- 41 | Async-reset: reset 42 | 43 | 44 | HD3_reg (width 2) 45 | ----------------- 46 | Async-reset: reset 47 | 48 | 49 | HD4_reg (width 2) 50 | ----------------- 51 | Async-reset: reset 52 | 53 | 54 | HD5_reg (width 2) 55 | ----------------- 56 | Async-reset: reset 57 | 58 | 59 | HD6_reg (width 2) 60 | ----------------- 61 | Async-reset: reset 62 | 63 | 64 | HD7_reg (width 2) 65 | ----------------- 66 | Async-reset: reset 67 | 68 | 69 | HD8_reg (width 2) 70 | ----------------- 71 | Async-reset: reset 72 | 73 | 74 | HD9_reg (width 2) 75 | ----------------- 76 | Async-reset: reset 77 | 78 | 79 | HD10_reg (width 2) 80 | ------------------ 81 | Async-reset: reset 82 | 83 | 84 | HD11_reg (width 2) 85 | ------------------ 86 | Async-reset: reset 87 | 88 | 89 | HD12_reg (width 2) 90 | ------------------ 91 | Async-reset: reset 92 | 93 | 94 | HD13_reg (width 2) 95 | ------------------ 96 | Async-reset: reset 97 | 98 | 99 | HD14_reg (width 2) 100 | ------------------ 101 | Async-reset: reset 102 | 103 | 104 | HD15_reg (width 2) 105 | ------------------ 106 | Async-reset: reset 107 | 108 | 109 | HD16_reg (width 2) 110 | ------------------ 111 | Async-reset: reset 112 | 113 | 114 | Writing to hnl file './eVITERBI_213_proj/workdirs/WORK/eBMU_213.hnl' 115 | -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eBMU_213.sts: -------------------------------------------------------------------------------- 1 | 0 -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eCONTROL_213%verilog.syn: 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'/emc/joshea/JOS/Verilog/Vit_e213/src/eSYNCERR_213.v'. 5 | =============================================================================== 6 | | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | 7 | =============================================================================== 8 | | error_reg | Flip-flop | 1 | - | - | Y | N | N | N | N | 9 | =============================================================================== 10 | 11 | error_reg 12 | --------- 13 | Async-reset: reset 14 | 15 | 16 | Writing to hnl file './eVITERBI_213_proj/workdirs/WORK/eSYNCERR_213.hnl' 17 | -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eSYNCERR_213.sts: -------------------------------------------------------------------------------- 1 | 0 -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eTBDECISION_213%verilog.syn: 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https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eVITERBI_213.hnl -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eVITERBI_213.out: -------------------------------------------------------------------------------- 1 | Writing to hnl file './eVITERBI_213_proj/workdirs/WORK/eVITERBI_213.hnl' 2 | -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_proj/workdirs/WORK/eVITERBI_213.sts: -------------------------------------------------------------------------------- 1 | 0 -------------------------------------------------------------------------------- /Vit_e213/syn/out/eVITERBI_213_syn-Optimized.fc2: -------------------------------------------------------------------------------- 1 | create_project eVITERBI_213_proj 2 | 3 | add_file -library WORK -format Verilog ../../src/eVITERBI_213.v 4 | add_file -library WORK -format Verilog ../../src/eCONTROL_213.v 5 | add_file -library WORK -format Verilog ../../src/eBMU_213.v 6 | add_file -library WORK -format Verilog ../../src/eACS_213.v 7 | add_file -library WORK -format Verilog ../../src/eACSU_213.v 8 | add_file -library WORK -format Verilog ../../src/eSYNCERR_213.v 9 | add_file -library WORK -format Verilog ../../src/eTBDECISION_213.v 10 | 11 | analyze_file -progress 12 | 13 | create_chip -progress -name eVITERBI_213_syn -target VIRTEX -device V50TQ144 -speed -4 -frequency 25 -module -preserve eVITERBI_213 14 | current_chip eVITERBI_213_syn 15 | 16 | optimize_chip -name eVITERBI_213_syn-Optimized -progress 17 | 18 | export_chip 19 | 20 | list_message 21 | -------------------------------------------------------------------------------- /Vit_e213/syn/out/fc2_shell_command.log: -------------------------------------------------------------------------------- 1 | #@ # 2 | #@ # Running fc2_shell on Sat Mar 24 22:50:10 2001 3 | #@ 4 | 5 | source -echo -verbose ../scr/../scr/eVITERBI_213_script 6 | #@ # setup default variables 7 | #@ 8 | #@ 9 | #@ set top $env(SYN_TOP) 10 | #@ set quick $env(SYN_QUICK) 11 | #@ set preserve $env(SYN_PRESERVE) 12 | #@ set timing $env(SYN_TIMING_DRIVEN) 13 | #@ set target VIRTEX 14 | #@ set chip ${top}_syn 15 | #@ set device V50TQ144 16 | #@ set speed -4 17 | #@ set frequency 25 18 | #@ set constraints $env(CONSTRAINTS) 19 | #@ 20 | #@ # create project 21 | #@ create_project $env(SYN_PROJECT) 22 | #@ 23 | #@ # proj_export_timing_constraint = "yes" 24 | #@ 25 | #@ puts "proj_enable_vpp = yes (turns on verilog pre-processor for `ifdefs)" 26 | #@ proj_enable_vpp = "yes" 27 | #@ 28 | #@ # identify design source files 29 | #@ 30 | #@ add_file -library WORK -format Verilog ../../src/eVITERBI_213.v 31 | #@ add_file -library WORK -format Verilog ../../src/eCONTROL_213.v 32 | #@ add_file -library WORK -format Verilog ../../src/eBMU_213.v 33 | #@ add_file -library WORK -format Verilog ../../src/eACS_213.v 34 | #@ add_file -library WORK -format Verilog ../../src/eACSU_213.v 35 | #@ add_file -library WORK -format Verilog ../../src/eSYNCERR_213.v 36 | #@ add_file -library WORK -format Verilog ../../src/eTBDECISION_213.v 37 | #@ 38 | #@ # analyze all source files and list progress 39 | #@ analyze_file -progress 40 | #@ 41 | #@ set option $quick 42 | #@ append option $preserve 43 | #@ puts $option 44 | #@ 45 | #@ switch -exact -- $option { 46 | #@ "-normal-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top} 47 | #@ "-normal-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $preserve} 48 | #@ "-quick_mode-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick} 49 | #@ "-quick_mode-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick $preserve} 50 | #@ 51 | #@ } 52 | #@ 53 | #@ 54 | #@ #if {$preserve=="-preserve"} { 55 | #@ # create_chip -preserve -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 56 | #@ #} else { 57 | #@ #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 58 | #@ #} 59 | #@ 60 | #@ #if {$quick=="-quick_mode"} { 61 | #@ # create_chip -quick_mode -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 62 | #@ #} else { 63 | #@ #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 64 | #@ #} 65 | #@ current_chip $chip 66 | #@ 67 | #@ puts "set_chip_constraint_driven $timing" 68 | #@ set_chip_constraint_driven $timing 69 | #@ 70 | #@ 71 | #@ # read fc2 timing constraints if they exist 72 | #@ if {$timing=="-enable"} { 73 | #@ source ../scr/$constraints 74 | #@ } 75 | #@ 76 | #@ set opt_chip [format "%s-Optimized" $chip] 77 | #@ optimize_chip -name $opt_chip -progress 78 | #@ 79 | #@ export_chip -progress -s "Verilog" -pri 80 | #@ export_chip -progress 81 | #@ 82 | #@ # write out script of commands that were used. 83 | #@ script_chip 84 | #@ 85 | #@ # create a timing report 86 | #@ report_timing 87 | #@ 88 | #@ 89 | #@ 90 | #@ list_message 91 | #@ close_project 92 | #@ quit 93 | -------------------------------------------------------------------------------- /Vit_e213/syn/scr/eVITERBI_213_constraint.fc2: -------------------------------------------------------------------------------- 1 | # 2 | # constraints.fst 3 | # 4 | # This script sets constraints. It is called by the 5 | # am2910_xx.fst scripts. 6 | # 7 | # It will run under either the NT or UNIX environments. 8 | # 9 | # This script and the design can be found in the samples/Synopsys 10 | # sub-directory of the FPGA Express installation. 11 | # 12 | 13 | # 14 | # Specify the clock waveform 15 | # 16 | set_clock -period 20 -rise 0 -fall 10 CLOCK 17 | 18 | # 19 | # Create a subpath 20 | # 21 | create_subpath -from_name my_from -to_name my_to -from_list /AM2910/U1\/STACK_TOP_reg<3> -to_list /AM2910/U1\/STACK_TOP_reg<1> -maxd 10 (RC,CLOCK):(RC,CLOCK) 22 | 23 | # 24 | # Specify delay for path groups 25 | # 26 | set_max_delay -path my_from:my_to 77 27 | 28 | # 29 | # Specify input delay relative to input pad timing group 30 | # 31 | set_input_delay -group "(I)" 21 "/AM2910/D<1>" 32 | 33 | # 34 | # Specify input delay relative to default group 35 | # 36 | set_input_delay 22 "/AM2910/D<2>" 37 | 38 | # 39 | # Specify output delay relative to output pad timing group 40 | # 41 | set_output_delay -group "(O)" 23 "/AM2910/Y_OUTPUT<1>" 42 | 43 | # 44 | # Specify output delay relative to default group 45 | # 46 | set_output_delay 24 "/AM2910/Y_OUTPUT<2>" 47 | 48 | 49 | # 50 | # Preserve the hierarchy for the module U4 51 | # 52 | set_module_primitive preserve "/AM2910/U4" 53 | 54 | -------------------------------------------------------------------------------- /Vit_e213/syn/scr/eVITERBI_213_script: -------------------------------------------------------------------------------- 1 | # setup default variables 2 | 3 | 4 | set top $env(SYN_TOP) 5 | set quick $env(SYN_QUICK) 6 | set preserve $env(SYN_PRESERVE) 7 | set timing $env(SYN_TIMING_DRIVEN) 8 | set target VIRTEX 9 | set chip ${top}_syn 10 | set device V50TQ144 11 | set speed -4 12 | set frequency 25 13 | set constraints $env(CONSTRAINTS) 14 | 15 | # create project 16 | create_project $env(SYN_PROJECT) 17 | 18 | # proj_export_timing_constraint = "yes" 19 | 20 | puts "proj_enable_vpp = yes (turns on verilog pre-processor for `ifdefs)" 21 | proj_enable_vpp = "yes" 22 | 23 | # identify design source files 24 | 25 | add_file -library WORK -format Verilog ../../src/eVITERBI_213.v 26 | add_file -library WORK -format Verilog ../../src/eCONTROL_213.v 27 | add_file -library WORK -format Verilog ../../src/eBMU_213.v 28 | add_file -library WORK -format Verilog ../../src/eACS_213.v 29 | add_file -library WORK -format Verilog ../../src/eACSU_213.v 30 | add_file -library WORK -format Verilog ../../src/eSYNCERR_213.v 31 | add_file -library WORK -format Verilog ../../src/eTBDECISION_213.v 32 | 33 | # analyze all source files and list progress 34 | analyze_file -progress 35 | 36 | set option $quick 37 | append option $preserve 38 | puts $option 39 | 40 | switch -exact -- $option { 41 | "-normal-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top} 42 | "-normal-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $preserve} 43 | "-quick_mode-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick} 44 | "-quick_mode-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick $preserve} 45 | 46 | } 47 | 48 | 49 | #if {$preserve=="-preserve"} { 50 | # create_chip -preserve -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 51 | #} else { 52 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 53 | #} 54 | 55 | #if {$quick=="-quick_mode"} { 56 | # create_chip -quick_mode -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 57 | #} else { 58 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 59 | #} 60 | current_chip $chip 61 | 62 | puts "set_chip_constraint_driven $timing" 63 | set_chip_constraint_driven $timing 64 | 65 | 66 | # read fc2 timing constraints if they exist 67 | if {$timing=="-enable"} { 68 | source ../scr/$constraints 69 | } 70 | 71 | set opt_chip [format "%s-Optimized" $chip] 72 | optimize_chip -name $opt_chip -progress 73 | 74 | export_chip -progress -s "Verilog" -pri 75 | export_chip -progress 76 | 77 | # write out script of commands that were used. 78 | script_chip 79 | 80 | # create a timing report 81 | report_timing 82 | 83 | 84 | 85 | list_message 86 | close_project 87 | quit 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | -------------------------------------------------------------------------------- /Vit_e213/syn/scr/eVITERBI_213_script~: -------------------------------------------------------------------------------- 1 | # setup default variables 2 | 3 | 4 | set top $env(SYN_TOP) 5 | set quick $env(SYN_QUICK) 6 | set preserve $env(SYN_PRESERVE) 7 | set timing $env(SYN_TIMING_DRIVEN) 8 | set target VIRTEX 9 | set chip ${top}_syn 10 | set device V50TQ144 11 | set speed -4 12 | set frequency 25 13 | set constraints $env(CONSTRAINTS) 14 | 15 | # create project 16 | create_project $env(SYN_PROJECT) 17 | 18 | # proj_export_timing_constraint = "yes" 19 | 20 | puts "proj_enable_vpp = yes (turns on verilog pre-processor for `ifdefs)" 21 | proj_enable_vpp = "yes" 22 | 23 | # identify design source files 24 | 25 | add_file -library WORK -format Verilog ../../src/bVITERBI_213.v 26 | add_file -library WORK -format Verilog ../../src/bCONTROL_213.v 27 | add_file -library WORK -format Verilog ../../src/bBMU_213.v 28 | add_file -library WORK -format Verilog ../../src/bACS_213.v 29 | add_file -library WORK -format Verilog ../../src/bACSU_213.v 30 | add_file -library WORK -format Verilog ../../src/bSYNCERR_213.v 31 | add_file -library WORK -format Verilog ../../src/bTBDECISION_213.v 32 | 33 | # analyze all source files and list progress 34 | analyze_file -progress 35 | 36 | set option $quick 37 | append option $preserve 38 | puts $option 39 | 40 | switch -exact -- $option { 41 | "-normal-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top} 42 | "-normal-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $preserve} 43 | "-quick_mode-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick} 44 | "-quick_mode-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick $preserve} 45 | 46 | } 47 | 48 | 49 | #if {$preserve=="-preserve"} { 50 | # create_chip -preserve -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 51 | #} else { 52 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 53 | #} 54 | 55 | #if {$quick=="-quick_mode"} { 56 | # create_chip -quick_mode -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 57 | #} else { 58 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 59 | #} 60 | current_chip $chip 61 | 62 | puts "set_chip_constraint_driven $timing" 63 | set_chip_constraint_driven $timing 64 | 65 | 66 | # read fc2 timing constraints if they exist 67 | if {$timing=="-enable"} { 68 | source ../scr/$constraints 69 | } 70 | 71 | set opt_chip [format "%s-Optimized" $chip] 72 | optimize_chip -name $opt_chip -progress 73 | 74 | export_chip -progress -s "Verilog" -pri 75 | export_chip -progress 76 | 77 | # write out script of commands that were used. 78 | script_chip 79 | 80 | # create a timing report 81 | report_timing 82 | 83 | 84 | 85 | list_message 86 | close_project 87 | quit 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | -------------------------------------------------------------------------------- /Vit_e213/testvectors_213.txt: -------------------------------------------------------------------------------- 1 | 0110_1100_1010_0011_0010 //0 {6,c,a,3,2} 2 | 0101_0101_0101_0101_0101 //1 {5,5,5,5,5} 3 | 1010_1010_1010_1010_1010 //2 {a,a,a,a,a} 4 | 0000_0000_0000_0000_0000 //3 {0,0,0,0,0} 5 | 0001_1011_0001_1011_0001 //4 {1,b,1,b,1} 6 | 0010_0011_1010_1100_0110 //5 {2,3,a,c,6} 7 | 0001_0010_0011_0100_0101 //6 {1,2,3,4,5} 8 | 0110_1100_1010_0011_0010 //7 {6,c,a,3,2} 9 | 0101_0100_0011_0010_0001 //8 {5,4,3,2,1} 10 | 1111_1111_1111_1111_1111 //9 {f,f,f,f,f} 11 | -------------------------------------------------------------------------------- /Vit_e213/verilog.fsdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e213/verilog.fsdb -------------------------------------------------------------------------------- /Vit_e213/verilog.key: -------------------------------------------------------------------------------- 1 | ^0 (interrupt at time 1464500) 2 | $finish; 3 | -------------------------------------------------------------------------------- /Vit_e322/src/eACS_322.v: -------------------------------------------------------------------------------- 1 | /*========================================================== 2 | module eACS_322.v 3 | 4 | ACS Block for efficient (3,2,2) backward label decoder 5 | 6 | ============================================================*/ 7 | 8 | `timescale 1 ns/1 ns 9 | 10 | module eACS_322 (acs_ppm_out, acs_Bx_out, 11 | acs_ppm_ina, HD_ina, acs_ppm_inb, HD_inb, 12 | acs_ppm_inc, HD_inc, acs_ppm_ind, HD_ind, 13 | ae, reset, clock); 14 | 15 | 16 | 17 | `include "params_e322.inc" 18 | 19 | output [`W-1:0] acs_ppm_out; 20 | output [`k-1:0] acs_Bx_out; 21 | 22 | input [`W-1:0] acs_ppm_ina; 23 | input [`W-1:0] acs_ppm_inb; 24 | input [`W-1:0] acs_ppm_inc; 25 | input [`W-1:0] acs_ppm_ind; 26 | 27 | input [`W-1:0] HD_ina; 28 | input [`W-1:0] HD_inb; 29 | input [`W-1:0] HD_inc; 30 | input [`W-1:0] HD_ind; 31 | input ae; 32 | input reset; 33 | input clock; 34 | 35 | 36 | reg [`W-1:0] acs_ppm_out; 37 | reg [`W-1:0] acs_ppm_ab; 38 | reg [`W-1:0] acs_ppm_cd; 39 | 40 | 41 | reg [`k-1:0] acs_Bx_out; 42 | reg [`k-1:0] acs_Bx_ab; 43 | reg [`k-1:0] acs_Bx_cd; 44 | 45 | 46 | reg [`W-1:0] suma; 47 | reg [`W-1:0] sumb; 48 | reg [`W-1:0] sumc; 49 | reg [`W-1:0] sumd; 50 | 51 | 52 | 53 | always @(posedge clock or posedge reset) 54 | begin 55 | if (reset) 56 | suma <=0; 57 | else 58 | begin 59 | if (ae && acs_ppm_ina==4'b1111) 60 | suma <= acs_ppm_ina; 61 | else if (ae) 62 | suma <= acs_ppm_ina + HD_ina; 63 | end 64 | end 65 | 66 | 67 | always @(posedge clock or posedge reset) 68 | begin 69 | if (reset) 70 | sumb <=0; 71 | else 72 | begin 73 | if (ae && acs_ppm_inb==4'b1111) 74 | sumb <= acs_ppm_inb; 75 | else if (ae) 76 | sumb <= acs_ppm_inb + HD_inb; 77 | end 78 | end 79 | 80 | always @(posedge clock or posedge reset) 81 | begin 82 | if (reset) 83 | sumc <=0; 84 | else 85 | begin 86 | if (ae && acs_ppm_inc==4'b1111) 87 | sumc <= acs_ppm_inc; 88 | else if (ae) 89 | sumc <= acs_ppm_inc + HD_inc; 90 | end 91 | end 92 | 93 | 94 | always @(posedge clock or posedge reset) 95 | begin 96 | if (reset) 97 | sumd <=0; 98 | else 99 | begin 100 | if (ae && acs_ppm_ind==4'b1111) 101 | sumd <= acs_ppm_ind; 102 | else if (ae) 103 | sumd <= acs_ppm_ind + HD_ind; 104 | end 105 | end 106 | 107 | 108 | 109 | always @(suma or sumb or sumc or sumd) 110 | begin 111 | if (suma <=sumb) 112 | begin 113 | acs_ppm_ab =suma; 114 | acs_Bx_ab =2'b00; 115 | end 116 | else 117 | begin 118 | acs_ppm_ab =sumb; 119 | acs_Bx_ab =2'b01; 120 | end 121 | if (sumc <=sumd) 122 | begin 123 | acs_ppm_cd =sumc; 124 | acs_Bx_cd =2'b10; 125 | end 126 | else 127 | begin 128 | acs_ppm_cd =sumd; 129 | acs_Bx_cd =2'b11; 130 | end 131 | end 132 | 133 | 134 | 135 | always @(acs_ppm_ab or acs_ppm_cd) 136 | begin 137 | if (acs_ppm_ab <= acs_ppm_cd) 138 | begin 139 | acs_ppm_out = acs_ppm_ab; 140 | acs_Bx_out = acs_Bx_ab; 141 | end 142 | else 143 | begin 144 | acs_ppm_out = acs_ppm_cd; 145 | acs_Bx_out = acs_Bx_cd; 146 | end 147 | end 148 | 149 | 150 | endmodule 151 | -------------------------------------------------------------------------------- /Vit_e322/src/eSYNCERR_322.v: -------------------------------------------------------------------------------- 1 | /*============================================================================ 2 | module eSYNCERR_322.v 3 | 4 | Out of Synch Error Detector for (3,2,2) Viterbi decoder. 5 | 6 | ===========================================================================*/ 7 | `timescale 1 ns/1 ns 8 | 9 | 10 | module eSYNCERR_322 (error, stage, we, metric, reset, clock); 11 | 12 | 13 | output error; 14 | 15 | input [3:0] stage; 16 | input [2:0] metric; 17 | input we; 18 | input reset; 19 | input clock; 20 | reg error; 21 | 22 | 23 | always @(posedge clock or posedge reset) 24 | begin 25 | if (reset) 26 | error <=1'b0; 27 | else 28 | begin 29 | if (we && stage >=4'b0011 && metric >4'b1000) 30 | error <=1'b1; 31 | else 32 | error <=1'b0; 33 | end 34 | end 35 | 36 | 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /Vit_e322/src/eTBDECISION_322.v: -------------------------------------------------------------------------------- 1 | /*================================================================= 2 | module eTBDECISION_322.v 3 | 4 | Traceback Decision Unit for (3,2,2) decoder 5 | 6 | Determine pointer to initial state for traceback 7 | by finding the state with minimum accumulated metric 8 | 9 | ==================================================================*/ 10 | 11 | `timescale 1 ns/1 ns 12 | 13 | module eTBDECISION_322 (best_state, 14 | in0, in1, in2, in3, in4, in5, in6, in7); 15 | 16 | 17 | `include "params_e322.inc" 18 | 19 | output [2:0] best_state; 20 | 21 | input [`W-1:0] in0; 22 | input [`W-1:0] in1; 23 | input [`W-1:0] in2; 24 | input [`W-1:0] in3; 25 | input [`W-1:0] in4; 26 | input [`W-1:0] in5; 27 | input [`W-1:0] in6; 28 | input [`W-1:0] in7; 29 | 30 | reg [2:0] best_state; 31 | reg [`W-1:0] min_01; 32 | reg [`W-1:0] min_23; 33 | reg [`W-1:0] min_45; 34 | reg [`W-1:0] min_67; 35 | reg [`W-1:0] min_0123; 36 | reg [`W-1:0] min_4567; 37 | reg [`W-1:0] min_metric; 38 | 39 | 40 | 41 | always @(in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) 42 | begin 43 | if (in0 <=in1) 44 | min_01=in0; 45 | else 46 | min_01=in1; 47 | 48 | if (in2 <=in3) 49 | min_23=in2; 50 | else 51 | min_23=in3; 52 | 53 | if (in4 <=in5) 54 | min_45=in4; 55 | else 56 | min_45=in5; 57 | 58 | if (in6 <=in7) 59 | min_67=in6; 60 | else 61 | min_67=in7; 62 | 63 | if (min_01 <= min_23) 64 | min_0123 = min_01; 65 | else 66 | min_0123 = min_23; 67 | 68 | if (min_45 <= min_67) 69 | min_4567 = min_45; 70 | else 71 | min_4567 = min_67; 72 | 73 | if (min_0123 <= min_4567) 74 | min_metric = min_0123; 75 | else 76 | min_metric = min_4567; 77 | end 78 | 79 | 80 | always @ (in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 or min_metric) 81 | begin 82 | if (in0==min_metric) 83 | best_state = 3'b000; 84 | else if (in1==min_metric) 85 | best_state = 3'b001; 86 | else if (in2==min_metric) 87 | best_state = 3'b010; 88 | else if (in3==min_metric) 89 | best_state = 3'b011; 90 | else if (in4==min_metric) 91 | best_state = 3'b100; 92 | else if (in5==min_metric) 93 | best_state = 3'b101; 94 | else if (in6==min_metric) 95 | best_state = 3'b110; 96 | else 97 | best_state = 3'b111; 98 | end 99 | 100 | endmodule 101 | 102 | 103 | -------------------------------------------------------------------------------- /Vit_e322/src/nWaveLog/turbo.log: -------------------------------------------------------------------------------- 1 | au time=75403 memory (delta=6620944:7954432 total=6692728:8044544) 2 | -------------------------------------------------------------------------------- /Vit_e322/src/params_e322.inc: -------------------------------------------------------------------------------- 1 | `define CLOCK_PERIOD 40 2 | `define NUM_VECTORS 10 3 | 4 | `define W 4 5 | `define N 20 6 | `define T 9 7 | `define n 3 8 | `define k 2 9 | `define m 2 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /Vit_e322/src/sim_e322.script: -------------------------------------------------------------------------------- 1 | tb_e322.v 2 | eBMU_322.v 3 | eACS_322.v 4 | eACSU_322.v 5 | eTBDECISION_322.v 6 | eSYNCERR_322.v 7 | eCONTROL_322.v 8 | eVITERBI_322.v 9 | +libext+.v+.V 10 | -y /hwapps/xilinx/M.1.5.i/verilog/src/UNI4000X 11 | -------------------------------------------------------------------------------- /Vit_e322/src/verilog.fsdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/Vit_e322/src/verilog.fsdb -------------------------------------------------------------------------------- /Vit_e322/syn/scr/trace_script: -------------------------------------------------------------------------------- 1 | # setup default variables 2 | 3 | 4 | set top $env(SYN_TOP) 5 | set quick $env(SYN_QUICK) 6 | set preserve $env(SYN_PRESERVE) 7 | set timing $env(SYN_TIMING_DRIVEN) 8 | set target VIRTEX 9 | set chip ${top}_syn 10 | set device V1000FG680 11 | set speed -6 12 | set frequency 75 13 | set constraints $env(CONSTRAINTS) 14 | 15 | # create project 16 | create_project $env(SYN_PROJECT) 17 | 18 | # proj_export_timing_constraint = "yes" 19 | 20 | puts "proj_enable_vpp = yes (turns on verilog pre-processor for `ifdefs)" 21 | proj_enable_vpp = "yes" 22 | 23 | # identify design source files 24 | 25 | add_file -library WORK -format Verilog ../../src/trace.v 26 | add_file -library WORK -format Verilog ../../src/RAM16X128.v 27 | add_file -library WORK -format Verilog ../../src/register_if.v 28 | 29 | 30 | 31 | 32 | # analyze all source files and list progress 33 | analyze_file -progress 34 | 35 | set option $quick 36 | append option $preserve 37 | puts $option 38 | 39 | switch -exact -- $option { 40 | "-normal-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top} 41 | "-normal-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $preserve} 42 | "-quick_mode-no_preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick} 43 | "-quick_mode-preserve" {create_chip -module -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top $quick $preserve} 44 | 45 | } 46 | 47 | 48 | #if {$preserve=="-preserve"} { 49 | # create_chip -preserve -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 50 | #} else { 51 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 52 | #} 53 | 54 | #if {$quick=="-quick_mode"} { 55 | # create_chip -quick_mode -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 56 | #} else { 57 | #create_chip -progress -name $chip -target $target -device $device -speed $speed -frequency $frequency $top 58 | #} 59 | current_chip $chip 60 | 61 | puts "set_chip_constraint_driven $timing" 62 | set_chip_constraint_driven $timing 63 | 64 | 65 | # read fc2 timing constraints if they exist 66 | if {$timing=="-enable"} { 67 | source ../scr/$constraints 68 | } 69 | 70 | set opt_chip [format "%s-Optimized" $chip] 71 | optimize_chip -name $opt_chip -progress 72 | 73 | export_chip -progress -s "Verilog" -pri 74 | export_chip -progress 75 | 76 | # write out script of commands that were used. 77 | script_chip 78 | 79 | # create a timing report 80 | report_timing 81 | 82 | 83 | 84 | list_message 85 | close_project 86 | quit 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | -------------------------------------------------------------------------------- /docs/FPGA Based Storage Efficient Viterbi Decoders.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/0f8e1f2f5a85a5fba2a6f9fc793f784f50fde3fb/docs/FPGA Based Storage Efficient Viterbi Decoders.doc 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