├── README.md ├── Vit_b213 ├── .synopsys_dc.setup ├── b213_build.script ├── b213_synth.script ├── chip │ ├── out │ │ ├── .chiptmp │ │ │ ├── bVITERBI_213.bgn │ │ │ ├── bVITERBI_213.bit │ │ │ ├── bVITERBI_213.bld │ │ │ ├── bVITERBI_213.dly │ │ │ ├── bVITERBI_213.msk │ │ │ ├── bVITERBI_213.ncd │ │ │ ├── bVITERBI_213.ngd │ │ │ ├── bVITERBI_213.pad │ │ │ ├── bVITERBI_213.par │ │ │ ├── bVITERBI_213.pcf │ │ │ ├── bVITERBI_213.rbt │ │ │ ├── bVITERBI_213.twr │ │ │ ├── bVITERBI_213.xpi │ │ │ ├── bVITERBI_213_jtag.bgn │ │ │ ├── bVITERBI_213_jtag.bit │ │ │ ├── bVITERBI_213_m.mrp │ │ │ ├── bVITERBI_213_m.ncd │ │ │ ├── bVITERBI_213_m.ngm │ │ │ ├── build_log │ │ │ ├── mail_log │ │ │ └── ngo │ │ │ │ ├── bVITERBI_213.ngo │ │ │ │ └── netlist.lst │ │ ├── bVITERBI_213.bld │ │ ├── bVITERBI_213.ncd │ │ ├── bVITERBI_213.ngd │ │ ├── bVITERBI_213.pad │ │ ├── bVITERBI_213.par │ │ ├── bVITERBI_213.pcf │ │ ├── bVITERBI_213.twr │ │ ├── bVITERBI_213_jtag.bit │ │ ├── bVITERBI_213_m.mrp │ │ ├── build_log │ │ └── mail_log │ └── scr │ │ ├── bVITERBI_213.ucf.old │ │ ├── bVITERBI_213_ngdbuild.nav │ │ └── make_chip ├── src │ ├── VIT_ENC.v │ ├── bACSU_213.v │ ├── bACS_213.v │ ├── bBMU_213.v │ ├── bCONTROL_213.v │ ├── bCONTROL_213.v~ │ ├── bSYNCERR_213.v │ ├── bTBDECISION_213.v │ ├── bVITERBI_213.v │ ├── lse.wrk │ ├── nWaveLog │ │ ├── nWave.cmd │ │ └── turbo.log │ ├── params_b213.inc.v │ ├── sig.rc │ ├── sim_b213.script │ ├── tb_b213.v │ ├── tb_b213.v~ │ ├── verilog.fsdb │ ├── verilog.log │ └── vreader.log └── syn │ ├── out │ ├── bVITERBI_213.edf │ ├── bVITERBI_213.v │ ├── bVITERBI_213_log │ ├── bVITERBI_213_proj │ │ ├── bVITERBI_213_proj.exp │ │ ├── chips │ │ │ ├── bVITERBI_213_syn-Optimized │ │ │ │ ├── bVITERBI_213_syn-Optimized.cst │ │ │ │ ├── bVITERBI_213_syn-Optimized.rpt │ │ │ │ └── bVITERBI_213_syn-Optimized.ws │ │ │ └── bVITERBI_213_syn │ │ │ │ ├── bVITERBI_213_syn.cst │ │ │ │ ├── bVITERBI_213_syn.rpt │ │ │ │ └── bVITERBI_213_syn.ws │ │ ├── files │ │ │ ├── L0.rpt │ │ │ ├── L1.rpt │ │ │ ├── L2.rpt │ │ │ ├── L3.rpt │ │ │ ├── L4.rpt │ │ │ ├── L5.rpt │ │ │ └── L6.rpt │ │ └── workdirs │ │ │ └── WORK │ │ │ ├── Anal.info │ │ │ ├── Anal.out │ │ │ ├── BACSU_213.mra │ │ │ ├── BACS_213.mra │ │ │ ├── BBMU_213.mra │ │ │ ├── BCONTROL_213.mra │ │ │ ├── BSYNCERR_213.mra │ │ │ ├── BTBDECISION_213.mra │ │ │ ├── BVITERBI_213.mra │ │ │ ├── bACSU_213%verilog.syn │ │ │ ├── bACSU_213%verilog__verilog.syn │ │ │ ├── bACSU_213.hnl │ │ │ ├── bACSU_213.out │ │ │ ├── bACSU_213.sts │ │ │ ├── bACS_213%verilog.syn │ │ │ ├── bACS_213%verilog__verilog.syn │ │ │ ├── bACS_213.hnl │ │ │ ├── bACS_213.out │ │ │ ├── bACS_213.sts │ │ │ ├── bBMU_213%verilog.syn │ │ │ ├── bBMU_213%verilog__verilog.syn │ │ │ ├── bBMU_213.hnl │ │ │ ├── bBMU_213.out │ │ │ ├── bBMU_213.sts │ │ │ ├── bCONTROL_213%verilog.syn │ │ │ ├── bCONTROL_213%verilog__verilog.syn │ │ │ ├── bCONTROL_213.hnl │ │ │ ├── bCONTROL_213.out │ │ │ ├── bCONTROL_213.sts │ │ │ ├── bSYNCERR_213%verilog.syn │ │ │ ├── bSYNCERR_213%verilog__verilog.syn │ │ │ ├── bSYNCERR_213.hnl │ │ │ ├── bSYNCERR_213.out │ │ │ ├── bSYNCERR_213.sts │ │ │ ├── bTBDECISION_213%verilog.syn │ │ │ ├── bTBDECISION_213%verilog__verilog.syn │ │ │ ├── bTBDECISION_213.hnl │ │ │ ├── bTBDECISION_213.out │ │ │ ├── bTBDECISION_213.sts │ │ │ ├── bVITERBI_213%verilog.syn │ │ │ ├── bVITERBI_213%verilog__verilog.syn │ │ │ ├── bVITERBI_213.hnl │ │ │ ├── bVITERBI_213.out │ │ │ └── bVITERBI_213.sts │ ├── bVITERBI_213_syn-Optimized.fc2 │ └── fc2_shell_command.log │ └── scr │ ├── bVITERBI_213_constraint.fc2 │ ├── bVITERBI_213_script │ └── bVITERBI_213_script~ ├── Vit_b322 ├── .synopsys_dc.setup ├── DecoderInput.dat ├── ENCODER_322.v ├── b322_build.script ├── b322_synth.script ├── src │ ├── bACSU_322.v │ ├── bACS_322.v │ ├── bBMU_322.v │ ├── bCONTROL_322.v │ ├── bSYNCERR_322.v │ ├── bTBDECISION_322.v │ ├── bVITERBI_322.v │ ├── nWaveLog │ │ ├── nWave.cmd │ │ └── turbo.log │ ├── params_b322.inc │ ├── sig.rc │ ├── sim_b322.script │ ├── tb_b322.v │ ├── verilog.fsdb │ └── verilog.log └── syn │ └── scr │ └── trace_script ├── Vit_e213 ├── .synopsys_dc.setup ├── New_Vit_e213 │ ├── VIT_ENC.v │ ├── eACSU_213.v │ ├── eACS_213.v │ ├── eBMU_213.v │ ├── eCONTROL_213.v │ ├── eSYNCERR_213.v │ ├── eTBDECISION_213.v │ ├── eVITERBI_213.v │ ├── nWaveLog │ │ ├── nWave.cmd │ │ └── turbo.log │ ├── params_e213.inc.v │ ├── sig.rc │ ├── sim_e213.script │ ├── tb_e213.v │ ├── testvectors_213.txt │ ├── verilog.fsdb │ └── verilog.log ├── VIT_ENC.v ├── chip │ ├── out │ │ ├── .chiptmp │ │ │ ├── build_log │ │ │ ├── eVITERBI_213.bgn │ │ │ ├── eVITERBI_213.bit │ │ │ ├── eVITERBI_213.bld │ │ │ ├── eVITERBI_213.dly │ │ │ ├── eVITERBI_213.msk │ │ │ ├── eVITERBI_213.ncd │ │ │ ├── eVITERBI_213.ngd │ │ │ ├── eVITERBI_213.pad │ │ │ ├── eVITERBI_213.par │ │ │ ├── eVITERBI_213.pcf │ │ │ ├── eVITERBI_213.rbt │ │ │ ├── eVITERBI_213.twr │ │ │ ├── eVITERBI_213.xpi │ │ │ ├── eVITERBI_213_jtag.bgn │ │ │ ├── eVITERBI_213_jtag.bit │ │ │ ├── eVITERBI_213_m.mrp │ │ │ ├── eVITERBI_213_m.ncd │ │ │ ├── eVITERBI_213_m.ngm │ │ │ ├── mail_log │ │ │ └── ngo │ │ │ │ ├── eVITERBI_213.ngo │ │ │ │ └── netlist.lst │ │ ├── build_log │ │ ├── eVITERBI_213.bld │ │ ├── eVITERBI_213.ncd │ │ ├── eVITERBI_213.ngd │ │ ├── eVITERBI_213.pad │ │ ├── eVITERBI_213.par │ │ ├── eVITERBI_213.pcf │ │ ├── eVITERBI_213.twr │ │ ├── eVITERBI_213_jtag.bit │ │ ├── eVITERBI_213_m.mrp │ │ └── mail_log │ └── scr │ │ ├── eVITERBI_213_ngdbuild.nav │ │ └── make_chip ├── command.log ├── e213_build.script ├── e213_synth.script ├── eACSU_213.v ├── eACS_213.v ├── eBMU_213.v ├── eCONTROL_213.v ├── eCONTROL_213.v.$$$ ├── eSYNCERR_213.v ├── eTBDECISION_213.v ├── eVITERBI_213.bld ├── eVITERBI_213.db ├── eVITERBI_213.mdf ├── eVITERBI_213.mrp ├── eVITERBI_213.ncd ├── eVITERBI_213.ngd ├── eVITERBI_213.ngm ├── eVITERBI_213.ngo ├── eVITERBI_213.pcf ├── eVITERBI_213.sedif ├── eVITERBI_213.v ├── eVITERBI_213_ngdbuild.nav ├── eVITERBI_r_213.dly ├── eVITERBI_r_213.ncd ├── eVITERBI_r_213.pad ├── eVITERBI_r_213.par ├── eVITERBI_r_213.xpi ├── netlist.lst ├── params_e213.inc ├── sig.rc ├── sim_e213.script ├── src │ ├── VIT_ENC.v │ ├── eACSU_213.v │ ├── eACS_213.v │ ├── eBMU_213.v │ ├── eCONTROL_213.v │ ├── eCONTROL_213.v~ │ ├── eSYNCERR_213.v │ ├── eTBDECISION_213.v │ ├── eVITERBI_213.v │ ├── lse.wrk │ ├── nWaveLog │ │ ├── nWave.cmd │ │ └── turbo.log │ ├── params_e213.inc.v │ ├── params_e213.inc.v~ │ ├── sig.rc │ ├── sim_e213.script │ ├── tb_e213.v │ ├── tb_e213.v~ │ ├── verilog.fsdb │ ├── verilog.log │ └── vreader.log ├── syn │ ├── out │ │ ├── eVITERBI_213.edf │ │ ├── eVITERBI_213.v │ │ ├── eVITERBI_213_log │ │ ├── eVITERBI_213_proj │ │ │ ├── chips │ │ │ │ ├── eVITERBI_213_syn-Optimized │ │ │ │ │ ├── eVITERBI_213_syn-Optimized.cst │ │ │ │ │ ├── eVITERBI_213_syn-Optimized.rpt │ │ │ │ │ └── eVITERBI_213_syn-Optimized.ws │ │ │ │ └── eVITERBI_213_syn │ │ │ │ │ ├── eVITERBI_213_syn.cst │ │ │ │ │ ├── eVITERBI_213_syn.rpt │ │ │ │ │ └── eVITERBI_213_syn.ws │ │ │ ├── eVITERBI_213_proj.exp │ │ │ ├── files │ │ │ │ ├── L0.rpt │ │ │ │ ├── L1.rpt │ │ │ │ ├── L2.rpt │ │ │ │ ├── L3.rpt │ │ │ │ ├── L4.rpt │ │ │ │ ├── L5.rpt │ │ │ │ └── L6.rpt │ │ │ └── workdirs │ │ │ │ └── WORK │ │ │ │ ├── Anal.info │ │ │ │ ├── Anal.out │ │ │ │ ├── EACSU_213.mra │ │ │ │ ├── EACS_213.mra │ │ │ │ ├── EBMU_213.mra │ │ │ │ ├── ECONTROL_213.mra │ │ │ │ ├── ESYNCERR_213.mra │ │ │ │ ├── ETBDECISION_213.mra │ │ │ │ ├── EVITERBI_213.mra │ │ │ │ ├── eACSU_213%verilog.syn │ │ │ │ ├── eACSU_213%verilog__verilog.syn │ │ │ │ ├── eACSU_213.hnl │ │ │ │ ├── eACSU_213.out │ │ │ │ ├── eACSU_213.sts │ │ │ │ ├── eACS_213%verilog.syn │ │ │ │ ├── eACS_213%verilog__verilog.syn │ │ │ │ ├── eACS_213.hnl │ │ │ │ ├── eACS_213.out │ │ │ │ ├── eACS_213.sts │ │ │ │ ├── eBMU_213%verilog.syn │ │ │ │ ├── eBMU_213%verilog__verilog.syn │ │ │ │ ├── eBMU_213.hnl │ │ │ │ ├── eBMU_213.out │ │ │ │ ├── eBMU_213.sts │ │ │ │ ├── eCONTROL_213%verilog.syn │ │ │ │ ├── eCONTROL_213%verilog__verilog.syn │ │ │ │ ├── eCONTROL_213.hnl │ │ │ │ ├── eCONTROL_213.out │ │ │ │ ├── eCONTROL_213.sts │ │ │ │ ├── eSYNCERR_213%verilog.syn │ │ │ │ ├── eSYNCERR_213%verilog__verilog.syn │ │ │ │ ├── eSYNCERR_213.hnl │ │ │ │ ├── eSYNCERR_213.out │ │ │ │ ├── eSYNCERR_213.sts │ │ │ │ ├── eTBDECISION_213%verilog.syn │ │ │ │ ├── eTBDECISION_213%verilog__verilog.syn │ │ │ │ ├── eTBDECISION_213.hnl │ │ │ │ ├── eTBDECISION_213.out │ │ │ │ ├── eTBDECISION_213.sts │ │ │ │ ├── eVITERBI_213%verilog.syn │ │ │ │ ├── eVITERBI_213%verilog__verilog.syn │ │ │ │ ├── eVITERBI_213.hnl │ │ │ │ ├── eVITERBI_213.out │ │ │ │ └── eVITERBI_213.sts │ │ ├── eVITERBI_213_syn-Optimized.fc2 │ │ └── fc2_shell_command.log │ └── scr │ │ ├── eVITERBI_213_constraint.fc2 │ │ ├── eVITERBI_213_script │ │ └── eVITERBI_213_script~ ├── tb_e213.v ├── testvectors_213.txt ├── verilog.fsdb ├── verilog.key └── verilog.log ├── Vit_e322 ├── .synopsys_dc.setup ├── src │ ├── eACSU_322.v │ ├── eACS_322.v │ ├── eBMU_322.v │ ├── eCONTROL_322.v │ ├── eSYNCERR_322.v │ ├── eTBDECISION_322.v │ ├── eVITERBI_322.v │ ├── nWaveLog │ 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https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/eVITERBI_r_213.dly -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_r_213.ncd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/eVITERBI_r_213.ncd -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_r_213.pad: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/eVITERBI_r_213.pad -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_r_213.par: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/eVITERBI_r_213.par -------------------------------------------------------------------------------- /Vit_e213/eVITERBI_r_213.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /Vit_e213/netlist.lst: -------------------------------------------------------------------------------- 1 | /emc/joshea/Files/Verilog/Vit_e213/eVITERBI_213.sedif 981849530 2 | OK 3 | -------------------------------------------------------------------------------- /Vit_e213/params_e213.inc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/params_e213.inc -------------------------------------------------------------------------------- /Vit_e213/sig.rc: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /Vit_e213/src/eACS_213.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/src/eACS_213.v -------------------------------------------------------------------------------- /Vit_e213/src/eBMU_213.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/src/eBMU_213.v -------------------------------------------------------------------------------- /Vit_e213/src/eCONTROL_213.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/src/eCONTROL_213.v -------------------------------------------------------------------------------- /Vit_e213/src/eCONTROL_213.v~: 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https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/src/eVITERBI_213.v -------------------------------------------------------------------------------- /Vit_e213/src/lse.wrk: -------------------------------------------------------------------------------- 1 | FILE_TYPE = LOGIC_DIR; 2 | END. 3 | -------------------------------------------------------------------------------- /Vit_e213/src/nWaveLog/nWave.cmd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/src/nWaveLog/nWave.cmd -------------------------------------------------------------------------------- /Vit_e213/src/nWaveLog/turbo.log: -------------------------------------------------------------------------------- 1 | au time=135350 memory (delta=6525168:8863744 total=6596952:8953856) 2 | -------------------------------------------------------------------------------- /Vit_e213/src/params_e213.inc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/src/params_e213.inc.v -------------------------------------------------------------------------------- /Vit_e213/src/params_e213.inc.v~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/src/params_e213.inc.v~ -------------------------------------------------------------------------------- /Vit_e213/src/sig.rc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jfoshea/Viterbi-Decoder-in-Verilog/HEAD/Vit_e213/src/sig.rc -------------------------------------------------------------------------------- /Vit_e213/src/sim_e213.script: -------------------------------------------------------------------------------- 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