├── .gitignore ├── LICENSE ├── README.md ├── common └── dac_sdc.py ├── images ├── 0.jpg └── 1.jpg ├── result └── sample_team │ └── results.xml ├── sample_team ├── dac_sdc.bit ├── dac_sdc.hwh ├── dac_sdc.ipynb └── hw │ ├── .gitignore │ ├── Makefile │ ├── constraints.xdc │ ├── dac_sdc.tcl │ └── dac_sdc_wrapper.v └── scripts └── score.py /.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__ 2 | *.dat 3 | *-checkpoint.ipynb 4 | *-checkpoint.py -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Jeffrey Goeders 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # DAC 2022 Design Contest 2 | 3 | For full contest details, please see the [2022 DAC System Design Contest](https://byuccl.github.io/dac_sdc_2022/) page. 4 | 5 | For general questions regarding this contest, please use the Piazza page: piazza.com/dac_2018/winterterm12021/dacsdc2021 6 | 7 | ## Setup PYNQ on your Ultra96v2 board 8 | 9 | * Download the PYNQ 2.7 Ultra96v2 board image from 10 | * Follow the instructions to image the SD card at . 11 | * Follow the instructions to setup and connect to the board at . 12 | 13 | ## Usage 14 | The get started, users have to run the following command on the Ultra96 board: 15 | 16 | ```shell 17 | cd /home/xilinx/jupyter_notebooks 18 | git clone https://github.com/jgoeders/dac_sdc_2022.git 19 | ``` 20 | Remember the user name and password are both `xilinx` for super user. 21 | 22 | After the above step is completed successfully, you will see a folder `dac_sdc_2022` under your 23 | jupyter notebook dashboard. Open the `sample_team/dac_sdc.ipynb` notebook for directions on where to begin. 24 | 25 | ## Folder Structure 26 | 27 | 1. sample_team: This folder contains files for a sample team. This includes a .bit and .tcl file that defines the hardware, and a `.ipynb` jupyter notebook, and a `hw` folder that is used to create a Vivado project. You should create a new folder for your team, where you will keep all of your files. 28 | 29 | 2. images: All the test images are stored in this folder. Replace the example images in this directory with the full training set. 30 | 31 | 3. result: The results contain the output xml produced when execution is complete, and contains the runtime, energy usage, and predicted location of each object in each image. 32 | 33 | 34 | -------------------------------------------------------------------------------- /common/dac_sdc.py: -------------------------------------------------------------------------------- 1 | # import os 2 | import time 3 | import xml.dom.minidom 4 | import pathlib 5 | import pynq 6 | import cv2 7 | import sys 8 | 9 | DAC_CONTEST = pathlib.Path("/home/xilinx/jupyter_notebooks/dac_sdc_2022/") 10 | IMG_DIR = DAC_CONTEST / "images" 11 | RESULT_DIR = DAC_CONTEST / "result" 12 | 13 | BATCH_SIZE = 1000 14 | 15 | # Return a batch of image dir when `send` is called 16 | class Team: 17 | def __init__(self, team_name): 18 | self._result_path = RESULT_DIR / team_name 19 | self.team_dir = DAC_CONTEST / team_name 20 | 21 | folder_list = [self.team_dir, self._result_path] 22 | for folder in folder_list: 23 | if not folder.is_dir(): 24 | folder.mkdir() 25 | 26 | self.img_list = self.get_image_paths() 27 | self.current_batch_idx = 0 28 | 29 | def get_image_paths(self): 30 | names_temp = [f for f in IMG_DIR.iterdir() if f.suffix == ".jpg"] 31 | names_temp.sort(key=lambda x: int(x.stem)) 32 | return names_temp 33 | 34 | # Returns list of images paths for next batch of images 35 | def get_next_batch(self): 36 | start_idx = self.current_batch_idx * BATCH_SIZE 37 | self.current_batch_idx += 1 38 | end_idx = self.current_batch_idx * BATCH_SIZE 39 | return self.img_list[start_idx:end_idx] 40 | 41 | def get_bitstream_path(self): 42 | return str(self.team_dir / "dac_sdc.bit") 43 | 44 | def reset_batch_count(self): 45 | self.current_batch_idx = 0 46 | 47 | def load_images_to_memory(self): 48 | # Read all images in this batch from the SD card. 49 | # This part doesn't count toward your time/energy usage. 50 | image_paths = self.get_next_batch() 51 | 52 | rgb_imgs = [] 53 | for image_path in image_paths: 54 | bgr_img = cv2.imread(str(image_path)) 55 | rgb_img = cv2.cvtColor(bgr_img, cv2.COLOR_BGR2RGB) 56 | rgb_imgs.append((image_path, rgb_img)) 57 | 58 | return rgb_imgs 59 | 60 | def run(self, callback, debug=True): 61 | self.__total_time = 0 62 | self.__total_energy = 0 63 | self.__result_rectangles = [] 64 | 65 | rails = pynq.get_rails() 66 | rails_to_monitor = ["1V2", "PSDDR", "INT", "PSINT_LP", "PSINT_FP", "PSPLL"] 67 | 68 | while True: 69 | # Load images to memory 70 | rgb_imgs = self.load_images_to_memory() 71 | if not rgb_imgs: 72 | break 73 | 74 | if debug: 75 | print("Batch", self.current_batch_idx, "starting.", len(rgb_imgs), "images.") 76 | 77 | # Run user callback, recording runtime and power usage 78 | start = time.time() 79 | recorder = pynq.DataRecorder(*[rails[r].power for r in rails_to_monitor]) 80 | with recorder.record(0.05): 81 | object_locations = callback(rgb_imgs) 82 | end = time.time() 83 | 84 | if len(object_locations) != len(rgb_imgs): 85 | raise ValueError( 86 | str(len(rgb_imgs)) 87 | + " images provided, but " 88 | + str(len(object_locations)) 89 | + " object locations returned." 90 | ) 91 | self.__result_rectangles.extend(object_locations) 92 | 93 | runtime = end - start 94 | energy = ( 95 | sum([recorder.frame[r + "_power"].mean() for r in rails_to_monitor]) 96 | * runtime 97 | ) 98 | 99 | if debug: 100 | print( 101 | "Batch", 102 | self.current_batch_idx, 103 | "done. Runtime =", 104 | runtime, 105 | "seconds. Energy =", 106 | energy, 107 | "J.", 108 | ) 109 | 110 | self.__total_time += runtime 111 | self.__total_energy += energy 112 | 113 | # Delete images from memory 114 | del rgb_imgs[:] 115 | del rgb_imgs 116 | 117 | print( 118 | "Done all batches. Total runtime =", 119 | self.__total_time, 120 | "seconds. Total energy =", 121 | self.__total_energy, 122 | "J.", 123 | ) 124 | 125 | print("Savings results to XML...") 126 | self.save_results_xml() 127 | print("XML results written successfully.") 128 | 129 | def save_results_xml(self): 130 | if len(self.__result_rectangles) != len(self.img_list): 131 | raise ValueError("Result length not equal to number of images.") 132 | 133 | doc = xml.dom.minidom.Document() 134 | root = doc.createElement("results") 135 | 136 | perf_e = doc.createElement("performance") 137 | 138 | # Runtime 139 | runtime_e = doc.createElement("runtime") 140 | runtime_e.appendChild(doc.createTextNode(str(self.__total_time))) 141 | perf_e.appendChild(runtime_e) 142 | root.appendChild(runtime_e) 143 | 144 | # Energy 145 | energy_e = doc.createElement("energy") 146 | energy_e.appendChild(doc.createTextNode(str(self.__total_energy))) 147 | perf_e.appendChild(energy_e) 148 | root.appendChild(energy_e) 149 | 150 | for i, rectangle in enumerate(self.__result_rectangles): 151 | image_e = root.appendChild(doc.createElement("image")) 152 | 153 | doc.appendChild(root) 154 | name_e = doc.createElement("filename") 155 | name_t = doc.createTextNode(self.img_list[i].name) 156 | name_e.appendChild(name_t) 157 | image_e.appendChild(name_e) 158 | 159 | size_e = doc.createElement("size") 160 | node_width = doc.createElement("width") 161 | node_width.appendChild(doc.createTextNode("640")) 162 | node_length = doc.createElement("length") 163 | node_length.appendChild(doc.createTextNode("360")) 164 | size_e.appendChild(node_width) 165 | size_e.appendChild(node_length) 166 | image_e.appendChild(size_e) 167 | 168 | object_node = doc.createElement("object") 169 | node_bnd_box = doc.createElement("bndbox") 170 | node_bnd_box_xmin = doc.createElement("xmin") 171 | node_bnd_box_xmin.appendChild(doc.createTextNode(str(rectangle[0]))) 172 | node_bnd_box_xmax = doc.createElement("xmax") 173 | node_bnd_box_xmax.appendChild(doc.createTextNode(str(rectangle[1]))) 174 | node_bnd_box_ymin = doc.createElement("ymin") 175 | node_bnd_box_ymin.appendChild(doc.createTextNode(str(rectangle[2]))) 176 | node_bnd_box_ymax = doc.createElement("ymax") 177 | node_bnd_box_ymax.appendChild(doc.createTextNode(str(rectangle[3]))) 178 | node_bnd_box.appendChild(node_bnd_box_xmin) 179 | node_bnd_box.appendChild(node_bnd_box_xmax) 180 | node_bnd_box.appendChild(node_bnd_box_ymin) 181 | node_bnd_box.appendChild(node_bnd_box_ymax) 182 | 183 | object_node.appendChild(node_bnd_box) 184 | image_e.appendChild(object_node) 185 | 186 | file_name = self._result_path / "results.xml" 187 | with open(file_name, "w") as fp: 188 | doc.writexml(fp, indent="\t", addindent="\t", newl="\n", encoding="utf-8") 189 | -------------------------------------------------------------------------------- /images/0.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jgoeders/dac_sdc_2022/d904bff54f29bbba4c9f44d091dcb30ab75c0180/images/0.jpg -------------------------------------------------------------------------------- /images/1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jgoeders/dac_sdc_2022/d904bff54f29bbba4c9f44d091dcb30ab75c0180/images/1.jpg -------------------------------------------------------------------------------- /result/sample_team/results.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 1.9738342761993408 4 | 2.9607514142990112 5 | 6 | 0.jpg 7 | 8 | 640 9 | 360 10 | 11 | 12 | 13 | 50 14 | 90 15 | 70 16 | 130 17 | 18 | 19 | 20 | 21 | 1.jpg 22 | 23 | 640 24 | 360 25 | 26 | 27 | 28 | 50 29 | 90 30 | 70 31 | 130 32 | 33 | 34 | 35 | 36 | -------------------------------------------------------------------------------- /sample_team/dac_sdc.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jgoeders/dac_sdc_2022/d904bff54f29bbba4c9f44d091dcb30ab75c0180/sample_team/dac_sdc.bit -------------------------------------------------------------------------------- /sample_team/dac_sdc.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "markdown", 5 | "metadata": {}, 6 | "source": [ 7 | "# DAC Contest\n", 8 | "This reference design will help you walk through a design flow of DAC SDC 2022. This is a simplified design to help users get started on the FPGA platform and to understand the overall flow. It does not contain any object detection hardware.\n", 9 | "\n", 10 | "If you have any questions, please post on the [Piazza page](piazza.com/dac_2018/summer2022/dacsdc2022).\n", 11 | "\n", 12 | "### Hardware\n", 13 | "The base hardware design contains the Zynq MPSoC processor (A53) with a DMA and FIFO implemented in the PL.\n", 14 | "Note that in this starting hardware, no actual image processing/detection is done. Pictures are:\n", 15 | " * Sent from PS to DMA, then DMA to FIFO\n", 16 | " * Sent back from FIFO to DMA, then DMA to PS.\n", 17 | "\n", 18 | "Note that the FIFO should be replaced with meaningful hardware to process the pictures.\n", 19 | "\n", 20 | "You can create a Vivado project by opening Vivado 2019.1, changing to the hw directory, and running `source dac_sdc.tcl`. This will create and open a project that you can edit. On the final submission you are required to submit the sources files of your design, and you should run `File->Project->Write Tcl...` to generate a new tcl file to submit. Be sure to check the `Recreate Block Designs using Tcl` box, and include any custom IP modules you use.\n", 21 | "\n", 22 | "### Software\n", 23 | "Note:\n", 24 | " * You will not submit your `dac_sdc.py` file, so any changes you make to this file will not be considered during evluation. \n", 25 | " * You can use both PS and PL side to do inference.\n", 26 | "\n", 27 | "### Object Detection\n", 28 | "\n", 29 | "Object detection will be done on images in batches:\n", 30 | " * You will provide a Python callback function that will perform object detection on batch of images. This callback function wile be called many times.\n", 31 | " * The callback function should return the locations of all images in the batch.\n", 32 | " * Runtime and energy usage will be recorded during your callback function.\n", 33 | " * Images will be loaded from SD card before each batch is run, and this does not count toward your energy usage or runtime.\n", 34 | " \n", 35 | "### Notebook\n", 36 | "Your notebook should contain 4 code cells:\n", 37 | "\n", 38 | "1. Importing all libraries and creating your Team object.\n", 39 | "1. Downloading the overlay, and performany any one-time configuration.\n", 40 | "1. Python callback function and any other Python helper functions.\n", 41 | "1. Running object detection\n", 42 | "1. Cleanup\n", 43 | "\n" 44 | ] 45 | }, 46 | { 47 | "cell_type": "markdown", 48 | "metadata": {}, 49 | "source": [ 50 | "## 1. Imports and Create Team" 51 | ] 52 | }, 53 | { 54 | "cell_type": "code", 55 | "execution_count": 1, 56 | "metadata": {}, 57 | "outputs": [ 58 | { 59 | "data": { 60 | "application/javascript": [ 61 | "\n", 62 | "try {\n", 63 | "require(['notebook/js/codecell'], function(codecell) {\n", 64 | " codecell.CodeCell.options_default.highlight_modes[\n", 65 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 66 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 67 | " Jupyter.notebook.get_cells().map(function(cell){\n", 68 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 69 | " });\n", 70 | "});\n", 71 | "} catch (e) {};\n" 72 | ] 73 | }, 74 | "metadata": {}, 75 | "output_type": "display_data" 76 | }, 77 | { 78 | "data": { 79 | "application/javascript": [ 80 | "\n", 81 | "try {\n", 82 | "require(['notebook/js/codecell'], function(codecell) {\n", 83 | " codecell.CodeCell.options_default.highlight_modes[\n", 84 | " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n", 85 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 86 | " Jupyter.notebook.get_cells().map(function(cell){\n", 87 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 88 | " });\n", 89 | "});\n", 90 | "} catch (e) {};\n" 91 | ] 92 | }, 93 | "metadata": {}, 94 | "output_type": "display_data" 95 | } 96 | ], 97 | "source": [ 98 | "import sys\n", 99 | "import os\n", 100 | "\n", 101 | "sys.path.append(os.path.abspath(\"../common\"))\n", 102 | "\n", 103 | "import math\n", 104 | "import time\n", 105 | "import numpy as np\n", 106 | "from PIL import Image\n", 107 | "from matplotlib import pyplot\n", 108 | "import cv2\n", 109 | "from datetime import datetime\n", 110 | "\n", 111 | "import pynq\n", 112 | "import dac_sdc\n", 113 | "from IPython.display import display\n", 114 | "\n", 115 | "team_name = 'sample_team'\n", 116 | "team = dac_sdc.Team(team_name)" 117 | ] 118 | }, 119 | { 120 | "cell_type": "markdown", 121 | "metadata": {}, 122 | "source": [ 123 | "**Your team directory where you can access your bitstream, notebook, and any other files you submit, is available as `team.team_dir`.**" 124 | ] 125 | }, 126 | { 127 | "cell_type": "markdown", 128 | "metadata": {}, 129 | "source": [ 130 | "## 2. Preparing the overlay/bitstream and weight loading\n", 131 | "Overlay/bitstream loading must be executed in this cell.\n", 132 | "\n", 133 | "In this sample hardware, the DMA instance is exposed as an attribute of the overlay object. You aren't required to use DMA for your hardware solution." 134 | ] 135 | }, 136 | { 137 | "cell_type": "code", 138 | "execution_count": 2, 139 | "metadata": {}, 140 | "outputs": [], 141 | "source": [ 142 | "overlay = pynq.Overlay(team.get_bitstream_path())\n", 143 | "dma = overlay.axi_dma_0" 144 | ] 145 | }, 146 | { 147 | "cell_type": "markdown", 148 | "metadata": {}, 149 | "source": [ 150 | "## 3. Python Callback Function and Helper Functions\n" 151 | ] 152 | }, 153 | { 154 | "cell_type": "markdown", 155 | "metadata": {}, 156 | "source": [ 157 | "### Pushing the picture through the pipeline\n", 158 | "In this example, we use contiguous memory arrays for sending and receiving data via DMA.\n", 159 | "\n", 160 | "The size of the buffer depends on the size of the input or output data. The example images are 640x360 (same size as training and test data), and we will use `pynq.allocate` to allocate contiguous memory.\n", 161 | "\n", 162 | "### Callback function\n", 163 | "The callback function:\n", 164 | " - Will be called on each batch of images (will be called many times)\n", 165 | " - Is prvided with a list of tuples of (image path, RGB image)\n", 166 | " - It should return a list of object locations, where each location is a tuple (xmin, xmax, ymin, ymax) indicating the bounding box. This list should have the same number of elements as images provided to you. The first element in the list will correspond to the first image in the rgb_imgs list, etc.\n" 167 | ] 168 | }, 169 | { 170 | "cell_type": "code", 171 | "execution_count": 3, 172 | "metadata": {}, 173 | "outputs": [], 174 | "source": [ 175 | "in_buffer = pynq.allocate(shape=(360, 640, 3), dtype=np.uint8, cacheable = 1)\n", 176 | "out_buffer = pynq.allocate(shape=(360, 640, 3), dtype=np.uint8, cacheable = 1)\n", 177 | "\n", 178 | "def dma_transfer():\n", 179 | " dma.sendchannel.transfer(in_buffer)\n", 180 | " dma.recvchannel.transfer(out_buffer) \n", 181 | " dma.sendchannel.wait()\n", 182 | " dma.recvchannel.wait()\n", 183 | " \n", 184 | "def my_callback(rgb_imgs):\n", 185 | " img_locations = []\n", 186 | " for (img_path, img) in rgb_imgs:\n", 187 | " print(\"Loading image\", img_path, \"into buffer for DMA transfer\")\n", 188 | " in_buffer[:] = img \n", 189 | " dma_transfer()\n", 190 | " print(\"\\tDMA transfer complete\")\n", 191 | " \n", 192 | " # Show image (notebook will only show latest image)\n", 193 | " pyplot.imshow(out_buffer)\n", 194 | " \n", 195 | " # Appending fake image location, since this example doesn't actually perform object detection \n", 196 | " img_locations.append([50,90,70,130])\n", 197 | " \n", 198 | " return img_locations" 199 | ] 200 | }, 201 | { 202 | "cell_type": "markdown", 203 | "metadata": {}, 204 | "source": [ 205 | "## 4. Running Object Detection\n", 206 | "\n", 207 | "Call the following function to run the object detection. Extra debug output is enabled when `debug` is `True`." 208 | ] 209 | }, 210 | { 211 | "cell_type": "code", 212 | "execution_count": 4, 213 | "metadata": {}, 214 | "outputs": [ 215 | { 216 | "name": "stdout", 217 | "output_type": "stream", 218 | "text": [ 219 | "Batch 1 starting. 2 images.\n", 220 | "Loading image /home/xilinx/jupyter_notebooks/dac_sdc_2022/images/0.jpg into buffer for DMA transfer\n", 221 | "\tDMA transfer complete\n", 222 | "Loading image /home/xilinx/jupyter_notebooks/dac_sdc_2022/images/1.jpg into buffer for DMA transfer\n", 223 | "\tDMA transfer complete\n", 224 | "Batch 1 done. Runtime = 1.9738342761993408 seconds. Energy = 2.9607514142990112 J.\n", 225 | "Done all batches. Total runtime = 1.9738342761993408 seconds. Total energy = 2.9607514142990112 J.\n", 226 | "Savings results to XML...\n", 227 | "XML results written successfully.\n" 228 | ] 229 | }, 230 | { 231 | "data": { 232 | "image/png": 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2pVUGlrQ7E02HrGd69KoePXqEtLJNmzZt4naVIC/r27ev7c1N998ffzfRjR49Ouht3V76MV4FM1pmtKp2UdVUVe2mqn9R1TGqeoaqnqmqV6tqpd/201W1t6r2VdU3Ixt+bOTeOQaHPgs8z7qV1PZtsWaM9ax0XhbKyjahTAZF7jp+xMnx5s6dG6VIgvPiiy8Gve3w4Ql7+01IOP2AA4OemYbvNW1FXXWwI0SPJSKoKfgIJbO9/9XQTFMQI49WrVqFm266KQrRkJlevXpZ3ukJALfffnsUowlMRDBkSOBR188991wUookPTO5huPj9hWioPQjfgKDQHqKKommzsL+0LBahx1RSUlLAM/hIzk1DwVm8eLFtfWZmZpQiCc6aNWsCbnPLLbdEIZL4wOQehg5nn4lBs6cjBUeQIqE/MjJT8d651wI4EuumRJ3d1ARXXXVVFCMhO3V11teGDh06hOeffz6K0YTn9NNPj3UIUcWJw8LU5vFxGNo9w9H8YhDBkerPcSL+jZ09e7Zl3dKlS+NuwqoTVXp6Or797W9b3sH64x//OG7Ohu3ulQB8d6PW1NTYTvvrJSdeVnFRzcCTkZSZCVVHs76jcU81OhR/FetmRF3btm0DbtOuXbu4m0/8RPXhhx/a1sfLtBB290o0y87OjnwgcYLJ3aH9k++EZLZ1vGh2Y2kJsj/5wuWo4t+qVauCmgCsoaEBp512WhQiomBs2LDBsu7gwYP405/+FMVoWrK7s/Z48TiUMxKY3B2o6ixoXLUS4nBKMd3/JTqWnHiJfcaMGTj//PND2udnP/tZhKKhUAwYMAAjRphNDuvz05/+FEeOxOba0YcffoiqquBvLnzyySeDGrGV6JjcQ1Qz4GSknpoLZ53sgB5pQtbaMiS1C22haC+47777Qt7n6aef9uRCConozTffxNNPP21Zn5wcm9m9rUZWdezYEenp6aZ1KSnev9zI5B6CLy4bjKQ2gfuLrWhjA1pPmwnJiL8FECLtnHPOsaybP38+XnvtNcv6pCT+mMaLCRMm2C7gMX/+/ChG4/vGYGXPnj22o328fqcqf2uCtP9nY4GDBxz3sUOSkHrOd5A+PPAivl60dq31FEM//OEPAy5uvGXLFrdDIocOHjxoWfejH/0oeoEAln39/t15VguyX3755RGJKV4wuQepftmrzhM7gKY9u9H2D39zMaLEYXfn4MSJE4++tltC75577nE1JgqP3bcpq0U03PbHP/7Rsm7WrFlHX9uNxbdaxMMLmNyDUJPbBsmdTdccCcqR2lpkffipixEljrq6Oqxbt86yfubMmUdf2802+Pbbb6O2ttbV2Mg5uwuSDz74YFRimDBhgmn58WfkQ4YMsRzbbrf8XqJjcg9gT/9OSOp0suP9G7aXov3id5HcMb4XJImU9u2tLxybjWO36wdt06aNKzGRO+wmD0tPT8enn0buhMZqgWwAWLZsWYsyu2mB7frtExmTu419V5+HZJvkFEjTnmp02nUEyb37uhhV4li7di3q6+tN69q1a4e+fVv+uwSasc/uzlaKrp/85CeWdYcPHzb9/3VDeXm55dTRdjOJWvWxx3qMfqQwuVvYP/EW6F7na7s2Ve9GdvGJN5bdn90ImS+//NKyzm7oo91yfRR9gYaput3tUVxcbLvo+rhx4yzrzM7om8XbClNuYHI3UffiPMh/VyJNGpGW1BTyI+XwfnRctTnWzYgpu1ET3bp1C7i/3XSzwexP0fPAAw9Y1lVUVLjaPfOtb33Lsq6oqCjg/nPmzLGsa9eunaOY4hWTu4mMm3+C5esz8e7OLnh3R+iP96tPxeoJ0yMSW36Pb+PjX8wMvGGM2Y13Li8vD7j/4sWLMWbMGNO6zz77LKQ7EimynnjiCdv6vn372o6ND9bYsWMt60TEcsijvzvuuMOybv/+/XjhhRccxRaPgllmr7uI/EtEtohIkYjcbZR3EJEVIlJiPGf57TNFREpFpFhEEnLZk2v3bUTjVwcggpAfUMXetR+7vhjHO8NuQFJSErbNewl7128KvEOM2A2TC2Wx67/9zXroaChziVDkBeqeOXToUNifYffzEMrUBxs3brSsszqhSETBnLk3ArhXVU8DMBTAeBHpB2AygJWqmgtgpfEeRt0oAP0BjAAwW0Ric19yGJJbZWBE0VtoOOj0h1Kx+bGnsevN91yJZ8O901H32W5AgeSMdKy6/Ba8kprryrHd9NJLL1n+ohcUFODxxx8P6XirV6+2rJs3b15Ix6LI+v3vfx+xY9v1idt1C5k566yzbPvtg/kGkAiCWUO1UlXXG6/3A9gCoCuAkQCav3vPB3CN8XokgIWqWq+q2wGUAgi8/lUcanVyZwz6w1Sow2styWlpWD3qLrzZ/7Kw4ti7fhN2vvj6MTdRJWekI+PkzvjP9+8K69hus1sab/DgwSEfb+jQoZZ9oXYXzyj67r777ogc991337WtD9QtZGbHjh2WdVu2bEF1tfPBFPEipD53EekJYCCANQA6Ny+MbTw3r5vWFYB/p2qFUXb8scaJSIGIFMTzP+Qpo0ei1uYHIZD0rPY4uGNXWDG8MfhcJKentSgXADsW5Yd17Gixu0EpELv1Ol966SXHxyX3zZgxw/Vj+t9tGi1eGHIbdHIXkTYAFgO4R1XtVpgwO89t8T1dVeeqap6q5uXkxPcNPjfWbUX93n3OdlZFesf2eFl6Odr9naHXomOPsyzr2/bo7vjYbrP76mw3tUAgv/3tby3ruIh2fJk0aZLtjWtO5Odbn8CEM2NocXGxZV0wC38cPHgQ3//+99GtW7e4WY3KX1DJXURS4UvsL6rqEqN4t4h0Meq7AGgevlABwH9wazcA4Z26xlhyehqu378JjbXOLwq17tEVi9L6hLTPmh9MRN3ngb/VtO7RFYvbxnZ9yKeeesqyzupGplC89957lnV5eXlhH9+JWE1xG++++MK9+zvsThjuvPPOsI7dp08f23H4ubnW17REBK1bt8bLL7+MiooKPP/88xAR22tE0RZwUmPx/ev+BcAWVfUfg5cPYCyAx43n1/3KF4jITAAnA8gFYD0lYAIZMv9JrLv156ZdJMHIPLkz3uhxHr6784OA25a/sgxV/14b9M0V6R2zsPK87+GSDxY5ii1ckyZNMi3v3Lkz0tKc/Xv5u+CCC5CZmWk6I2FhYSFOPfVUlJaWhv05objuuutcX6CiVatWWLQoNv+Hbnr00UcxderUsI6xcOFC23q7icOCtXPnTsvfsdLSUpSUlLRI8uPHj8ejjz6Khx9+GCKClJQUnHTSSVBViEjcrD8QzIz1wwCMAfCxiDSPIXoQvqS+SERuBbATwI0AoKpFIrIIwGb4RtqMV1VPLHty8pUXofcdo1H2/GJnB1CFJAne7H8ZLi9623KzA1vLsWHCNCRlhJAUVXGoohIb752OATMechafQx06dLCs+/zzz137nNraWstfxK1bt2LDhg0YOHCga58XiF13gVNZWVmBN0oADz/8MC666CJ85zvfcXyM0aNHW9Zt27bN8XGPN2vWLMuLwX369GmRrGfPno2Ghoaj7xsaGo7+XMbTRGTBjJb5QFVFVc9U1QHGY5mq1qjqJaqaazzv9dtnuqr2VtW+qvpmZJsQXadPm4isvDNxqNLhTTSqaPzqADbebz4t6uF9X2HFoCtCS+x+xy5ftAw7Fy11FpsD2dnZll/DL774Ytc/z+7O10GDBrn+eeTceeedZzvk0M65555rWderVy/06uXedaZASzmaTXnh/41t1qxZR2/Siqfl+3iHqgPDFs/G9bVFaNjvbApaSUpC+aJ/omrVsb1VGyY+hlezvoXU9ic5jk2SBOvvnIqatdY3arhl3bp1qKmpsaxfuXKl659pNzc3ANx8882ufyY5Zzfk0EpFRQX++9//mtb17NnT1bP2ZnY3Wc2ePRuHDx8++v6RRx45JuHffffdR5ft27Urfi4vMrk7lJSairx5v0HT4YbAG5sQAB+OvAN1Vb6pSMtf+ScqFi9Hux7fDDu2lNaZ+NcF1l9p3WK3CEckbzBautT6m8mCBQuO+cpMsbdmzZqQtrfr2ti+fXu44ZjKyMiwnRbDfy3WqVOn4tlnn4WIHP3WWlZWBhGJq8U/vL9KbAR1v34EDpSUoeTpv8J8BKi95FbpeKP7MFy6finW3TYFyZkZrsWW2r4tFsopGKXOx+jbuemmm9C6dWvTurq6Otx2220R+VwAuPLKKwHA8vPT0tKO6Sdtamoy3baxsTHgZzWPiLH6LLfZzcFyfAyqGlQ3QHp6eot9m5qaXL8YbGXIkCHo378/ysrKjik3u/C4YMEC039rVcUzzzwTqRAB+Caku+CCC1BQUNCirqmpCQsXLsSoUaOOxgMAZ599Nvbs2YNevXrFzYXUZhIPAeXl5anZPygREVkTkUJVNR0LzG4ZIiIPYnInIvIgJnciIg9icici8iAmdyIiD2JyJyLyICZ3IiIPYnInIvIgJnciIg9icici8iAmdyIiD2JyJyLyICZ3IiIPCpjcRaS7iPxLRLaISJGI3G2UTxORz0Rko/G4wm+fKSJSKiLFIjI8kg0gIqKWgpnPvRHAvaq6XkTaAigUkRVG3VOq+qT/xiLSD8AoAP3hWyD7HRHp45V1VImIEkEwa6hWqup64/V+AFsAdLXZZSSAhapar6rbAZQCsF6yh4iIXBdSn7uI9AQwEEDzulkTROQjEXlORJqXbe8KwH+9qgrY/zEgIiKXBZ3cRaQNgMUA7lHVrwDMAdAbwAAAlQBmNG9qsnuL5Z5EZJyIFIhIQXV1dciBExGRtaCSu4ikwpfYX1TVJQCgqrtVtUlVjwCYh6+7XioA+K9w2w1AiyXBVXWuquapal5OTk44bSAiouMEM1pGAPwFwBZVnelX3sVvs2sBbDJe5wMYJSLpItILQC6Ate6FTEREgQQzWmYYgDEAPhaRjUbZgwBGi8gA+LpcygDcDgCqWiQiiwBshm+kzXiOlCEiiq6AyV1VP4B5P/oym32mA5geRlxERBQG3qFKRORBTO5ERB7E5E5E5EFM7kREHsTkTkTkQUzuREQexORORORBTO5ERB7E5E5E5EFM7kREHsTkTkTkQUzuREQexORORORBTO5ERB7E5E5E5EFM7kREHsTkTkTkQcGsoZohImtF5H8iUiQijxjlHURkhYiUGM9ZfvtMEZFSESkWkeGRbAAREbUUzJl7PYCLVfUsAAMAjBCRoQAmA1ipqrkAVhrvISL9AIwC0B/ACACzRSQ5EsETEZG5gMldfQ4Yb1ONhwIYCWC+UT4fwDXG65EAFqpqvapuB1AKYIirURMRka2g+txFJFlENgKoArBCVdcA6KyqlQBgPHcyNu8KoNxv9wqjjIiIoiSo5K6qTao6AEA3AENE5HSbzcXsEC02EhknIgUiUlBdXR1ctEREFJSQRsuo6j4A78HXl75bRLoAgPFcZWxWAaC7327dAOwyOdZcVc1T1bycnBwHoRMRkZVgRsvkiEh743UrAP8H4BMA+QDGGpuNBfC68TofwCgRSReRXgByAax1O3AiIrKWEsQ2XQDMN0a8JAFYpKpLRWQ1gEUiciuAnQBuBABVLRKRRQA2A2gEMF5VmyITPhERmRHVFt3hUZeXl6cFBQWxDoOIKKGISKGq5pnV8Q5VIiIPYnInIvIgJnciIg9icici8iAmdyIiD2JyJyLyICZ3IiIPYnInIvIgJnciIg9icici8iAmdyIiD2JyJyLyICZ3IiIPYnInIvIgJnciIg9icici8iAmdyIiDwpmDdUMEVkrIv8TkSIRecQonyYin4nIRuNxhd8+U0SkVESKRWR4JBtAREQtBbOGaj2Ai1X1gIikAvhARN406p5S1Sf9NxaRfgBGAegP4GQA74hIH66jSkQUPQHP3NXngPE21XjYLbw6EsBCVa1X1e0ASgEMCTtSIiIKWlB97iKSLCIbAVQBWKGqa4yqCSLykYg8JyJZRllXAOV+u1cYZUREFCVBJXdVbVLVAQC6ARgiIqcDmAOgN4ABACoBzDA2F7NDHF8gIuNEpEBECqqrqx0FT0RE5kIaLaOq+wC8B2CEqu42kv4RAPPwdddLBYDufrt1A7DL5FhzVTVPVXT6oyoAAAQ6SURBVPNycnIcBU9EROaCGS2TIyLtjdetAPwfgE9EpIvfZtcC2GS8zgcwSkTSRaQXgFwAa90Nm4iI7AQzWqYLgPkikgzfH4NFqrpURP4uIgPg63IpA3A7AKhqkYgsArAZQCOA8RwpQ0QUXaJqN/AlOvLy8rSgoCDWYRARJRQRKVTVPNO6eEjuIlINoBbAnljH4qJssD3xzmttYnviWyTac4qqml60jIvkDgAiUmD1FygRsT3xz2ttYnviW7Tbw7lliIg8iMmdiMiD4im5z411AC5je+Kf19rE9sS3qLYnbvrciYjIPfF05k5ERC6JeXIXkRHGvO+lIjI51vEEw5gorUpENvmVdRCRFSJSYjxn+dXF9fz2ItJdRP4lIluMOfvvNsoTuU1W6xAkbJuAo5P4bRCRpcb7hG2PiJSJyMfGehAFRlnCtgcARKS9iLwqIp8Yv0/nxqxNqhqzB4BkAFsBfBNAGoD/AegXy5iCjPt8AIMAbPIr+y2AycbryQCeMF73M9qVDqCX0d7kWLfhuPZ0ATDIeN0WwKdG3IncJgHQxnidCmANgKGJ3CYjzkkAFgBY6oGfuzIA2ceVJWx7jDjnA7jNeJ0GoH2s2hTrM/chAEpVdZuqHgawEL754OOaqv4bwN7jikfC9x8L4/kav/K4nt9eVStVdb3xej+ALfBN05zIbVI1X4cgYdskIt0AXAngWb/ihG2PhYRtj4i0g+/E7y8AoKqH1TfZYkzaFOvk7qW53zuraiXgS5YAOhnlCdVGEekJYCB8Z7oJ3SaLdQgSuU2/B/AAgCN+ZYncHgXwtogUisg4oyyR2/NNANUAnje6zp4VkdaIUZtindyDmvs9wSVMG0WkDYDFAO5R1a/sNjUpi7s2qfk6BFbiuk0ichWAKlUtDHYXk7K4aY9hmKoOAnA5gPEicr7NtonQnhT4umvnqOpA+KZUsbuOGNE2xTq5BzX3e4LY3TwNsvFcZZQnRBvFtz7uYgAvquoSozih29RM/dYhQOK2aRiAq0WkDL7uy4tF5AUkbnugqruM5yoA/4CvSyJh2wNfjBX69Up1r8KX7GPSplgn93UAckWkl4ikwbewdn6MY3IqH8BY4/VYAK/7lcf1/PYiIvD1E25R1Zl+VYncJtN1CJCgbVLVKaraTVV7wvd78q6q/gAJ2h4RaS0ibZtfA7gMvjUhErI9AKCqnwMoF5G+RtEl8E19Hps2xcHV5SvgG52xFcBDsY4nyJhfgm9pwQb4/vreCqAjgJUASoznDn7bP2S0rxjA5bGO36Q958H3dfAjABuNxxUJ3qYzAWww2rQJwFSjPGHb5Bfnhfh6tExCtge+/un/GY+i5t/9RG2PX4wDABQYP3evAciKVZt4hyoRkQfFuluGiIgigMmdiMiDmNyJiDyIyZ2IyIOY3ImIPIjJnYjIg5jciYg8iMmdiMiD/h//jDG4CEIuxAAAAABJRU5ErkJggg==\n", 233 | "text/plain": [ 234 | "
" 235 | ] 236 | }, 237 | "metadata": { 238 | "needs_background": "light" 239 | }, 240 | "output_type": "display_data" 241 | } 242 | ], 243 | "source": [ 244 | "team.run(my_callback, debug=True)" 245 | ] 246 | }, 247 | { 248 | "cell_type": "markdown", 249 | "metadata": {}, 250 | "source": [ 251 | "## 5. Cleanup" 252 | ] 253 | }, 254 | { 255 | "cell_type": "code", 256 | "execution_count": 5, 257 | "metadata": {}, 258 | "outputs": [], 259 | "source": [ 260 | "# Remember to free the contiguous memory after usage.\n", 261 | "del in_buffer\n", 262 | "del out_buffer" 263 | ] 264 | } 265 | ], 266 | "metadata": { 267 | "kernelspec": { 268 | "display_name": "Python 3", 269 | "language": "python", 270 | "name": "python3" 271 | }, 272 | "language_info": { 273 | "codemirror_mode": { 274 | "name": "ipython", 275 | "version": 3 276 | }, 277 | "file_extension": ".py", 278 | "mimetype": "text/x-python", 279 | "name": "python", 280 | "nbconvert_exporter": "python", 281 | "pygments_lexer": "ipython3", 282 | "version": "3.8.2" 283 | } 284 | }, 285 | "nbformat": 4, 286 | "nbformat_minor": 4 287 | } 288 | -------------------------------------------------------------------------------- /sample_team/hw/.gitignore: -------------------------------------------------------------------------------- 1 | /project_1 2 | *.jou 3 | *.str 4 | *.log 5 | /dac_sdc -------------------------------------------------------------------------------- /sample_team/hw/Makefile: -------------------------------------------------------------------------------- 1 | proj: 2 | vivado -source dac_sdc.tcl 3 | 4 | clean: 5 | rm -rf dac_sdc 6 | 7 | copy_hw: ../dac_sdc.bit ../dac_sdc.hwh 8 | 9 | ../dac_sdc.bit: dac_sdc/dac_sdc.runs/impl_1/dac_sdc_wrapper.bit 10 | cp $< $@ 11 | 12 | ../dac_sdc.hwh: dac_sdc/dac_sdc.srcs/sources_1/bd/sensors96b/hw_handoff/sensors96b.hwh 13 | cp $< $@ -------------------------------------------------------------------------------- /sample_team/hw/constraints.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # Copyright (c) 2017, Xilinx, Inc. 3 | # All rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are met: 7 | # 8 | # 1. Redistributions of source code must retain the above copyright notice, 9 | # this list of conditions and the following disclaimer. 10 | # 11 | # 2. Redistributions in binary form must reproduce the above copyright 12 | # notice, this list of conditions and the following disclaimer in the 13 | # documentation and/or other materials provided with the distribution. 14 | # 15 | # 3. Neither the name of the copyright holder nor the names of its 16 | # contributors may be used to endorse or promote products derived from 17 | # this software without specific prior written permission. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 | # CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 | # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 | # PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 | # OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 | # WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 | # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 | # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | # 31 | ############################################################################### 32 | 33 | set_property IOSTANDARD LVCMOS18 [get_ports UART*] 34 | set_property IOSTANDARD LVCMOS18 [get_ports GPIO_SENSORS_tri_io*] 35 | #set_property IOSTANDARD LVCMOS18 [get_ports loopback_out*] 36 | 37 | #HD_GPIO_2 on FPGA / Connector pin 7 / UART0_rxd 38 | set_property PACKAGE_PIN F7 [get_ports UART0_rxd] 39 | #HD_GPIO_1 on FPGA / Connector pin 5 / UART0_txd 40 | set_property PACKAGE_PIN F8 [get_ports UART0_txd] 41 | #HD_GPIO_3 on FPGA / Connector pin 9 / UART0_rts 42 | set_property PACKAGE_PIN G7 [get_ports UART0_rtsn] 43 | #HD_GPIO_0 on FPGA / Connector pin 3 / UART0_cts 44 | set_property PACKAGE_PIN D7 [get_ports UART0_ctsn] 45 | 46 | #HD_GPIO_5 on FPGA / Connector pin 13 / UART1_rxd 47 | set_property PACKAGE_PIN G5 [get_ports UART1_rxd] 48 | #HD_GPIO_4 on FPGA / Connector pin 11 / UART1_txd 49 | set_property PACKAGE_PIN F6 [get_ports UART1_txd] 50 | 51 | 52 | #HD_GPIO_6 on FPGA / Connector pin 29 / GPIO-G on 96Boards 53 | set_property PACKAGE_PIN A6 [get_ports {GPIO_SENSORS_tri_io[0]}] 54 | #HD_GPIO_13 on FPGA/ Connector pin 30 / GPIO-H on 96Boards 55 | set_property PACKAGE_PIN C7 [get_ports {GPIO_SENSORS_tri_io[1]}] 56 | #HD_GPIO_7 on FPGA / Connector pin 31 / GPIO-I on 96Boards 57 | set_property PACKAGE_PIN A7 [get_ports {GPIO_SENSORS_tri_io[2]}] 58 | #HD_GPIO_14 on FPGA/ Connector pin 32 / GPIO-J on 96Boards 59 | set_property PACKAGE_PIN B6 [get_ports {GPIO_SENSORS_tri_io[3]}] 60 | #HD_GPIO_8 on FPGA / Connector pin 33 / GPIO-K on 96Boards 61 | set_property PACKAGE_PIN G6 [get_ports {GPIO_SENSORS_tri_io[4]}] 62 | #HD_GPIO_15 on FPGA/ Connector pin 34 / GPIO-L on 96Boards 63 | set_property PACKAGE_PIN C5 [get_ports {GPIO_SENSORS_tri_io[5]}] 64 | 65 | 66 | set_property IOSTANDARD LVCMOS18 [get_ports BT*] 67 | 68 | #BT_HCI_RTS on FPGA / emio_uart0_ctsn connect to 69 | set_property PACKAGE_PIN B7 [get_ports BT_ctsn] 70 | #BT_HCI_CTS on FPGA / emio_uart0_rtsn 71 | set_property PACKAGE_PIN B5 [get_ports BT_rtsn] 72 | -------------------------------------------------------------------------------- /sample_team/hw/dac_sdc.tcl: -------------------------------------------------------------------------------- 1 | #***************************************************************************************** 2 | # Vivado (TM) v2019.1 (64-bit) 3 | # 4 | # dac_sdc.tcl: Tcl script for re-creating project 'dac_sdc' 5 | # 6 | # Generated by Vivado on Mon Jan 13 15:44:47 MST 2020 7 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 8 | # 9 | # This file contains the Vivado Tcl commands for re-creating the project to the state* 10 | # when this script was generated. In order to re-create the project, please source this 11 | # file in the Vivado Tcl Shell. 12 | # 13 | # * Note that the runs in the created project will be configured the same way as the 14 | # original project, however they will not be launched automatically. To regenerate the 15 | # run results please launch the synthesis/implementation runs as needed. 16 | # 17 | #***************************************************************************************** 18 | # NOTE: In order to use this script for source control purposes, please make sure that the 19 | # following files are added to the source control system:- 20 | # 21 | # 1. This project restoration tcl script (dac_sdc.tcl) that was generated. 22 | # 23 | # 2. The following source(s) files that were local or imported into the original project. 24 | # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) 25 | # 26 | # 27 | # 28 | # 3. The following remote source files that were added to the original project:- 29 | # 30 | # "/home/jgoeders/dac_sdc/dac_sdc_2020/sample_team/hw/dac_sdc_wrapper.v" 31 | # "/home/jgoeders/dac_sdc/dac_sdc_2020/sample_team/hw/constraints.xdc" 32 | # 33 | #***************************************************************************************** 34 | 35 | # Set the reference directory for source file relative paths (by default the value is script directory path) 36 | set origin_dir "." 37 | 38 | # Use origin directory path location variable, if specified in the tcl shell 39 | if { [info exists ::origin_dir_loc] } { 40 | set origin_dir $::origin_dir_loc 41 | } 42 | 43 | # Set the project name 44 | set _xil_proj_name_ "dac_sdc" 45 | 46 | # Use project name variable, if specified in the tcl shell 47 | if { [info exists ::user_project_name] } { 48 | set _xil_proj_name_ $::user_project_name 49 | } 50 | 51 | variable script_file 52 | set script_file "dac_sdc.tcl" 53 | 54 | # Help information for this script 55 | proc print_help {} { 56 | variable script_file 57 | puts "\nDescription:" 58 | puts "Recreate a Vivado project from this script. The created project will be" 59 | puts "functionally equivalent to the original project for which this script was" 60 | puts "generated. The script contains commands for creating a project, filesets," 61 | puts "runs, adding/importing sources and setting properties on various objects.\n" 62 | puts "Syntax:" 63 | puts "$script_file" 64 | puts "$script_file -tclargs \[--origin_dir \]" 65 | puts "$script_file -tclargs \[--project_name \]" 66 | puts "$script_file -tclargs \[--help\]\n" 67 | puts "Usage:" 68 | puts "Name Description" 69 | puts "-------------------------------------------------------------------------" 70 | puts "\[--origin_dir \] Determine source file paths wrt this path. Default" 71 | puts " origin_dir path value is \".\", otherwise, the value" 72 | puts " that was set with the \"-paths_relative_to\" switch" 73 | puts " when this script was generated.\n" 74 | puts "\[--project_name \] Create project with the specified name. Default" 75 | puts " name is the name of the project from where this" 76 | puts " script was generated.\n" 77 | puts "\[--help\] Print help information for this script" 78 | puts "-------------------------------------------------------------------------\n" 79 | exit 0 80 | } 81 | 82 | if { $::argc > 0 } { 83 | for {set i 0} {$i < $::argc} {incr i} { 84 | set option [string trim [lindex $::argv $i]] 85 | switch -regexp -- $option { 86 | "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } 87 | "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } 88 | "--help" { print_help } 89 | default { 90 | if { [regexp {^-} $option] } { 91 | puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" 92 | return 1 93 | } 94 | } 95 | } 96 | } 97 | } 98 | 99 | # Set the directory path for the original project from where this script was exported 100 | set orig_proj_dir "[file normalize "$origin_dir/dac_sdc"]" 101 | 102 | # Create project 103 | create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu3eg-sbva484-1-i 104 | 105 | # Set the directory path for the new project 106 | set proj_dir [get_property directory [current_project]] 107 | 108 | # Set project properties 109 | set obj [current_project] 110 | set_property -name "default_lib" -value "xil_defaultlib" -objects $obj 111 | set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj 112 | set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj 113 | set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj 114 | set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj 115 | set_property -name "dsa.emu_dir" -value "emu" -objects $obj 116 | set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj 117 | set_property -name "dsa.flash_offset_address" -value "0" -objects $obj 118 | set_property -name "dsa.flash_size" -value "1024" -objects $obj 119 | set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj 120 | set_property -name "dsa.host_interface" -value "pcie" -objects $obj 121 | set_property -name "dsa.num_compute_units" -value "60" -objects $obj 122 | set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj 123 | set_property -name "dsa.vendor" -value "xilinx" -objects $obj 124 | set_property -name "dsa.version" -value "0.0" -objects $obj 125 | set_property -name "enable_vhdl_2008" -value "1" -objects $obj 126 | set_property -name "ip_cache_permissions" -value "read write" -objects $obj 127 | set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj 128 | set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj 129 | set_property -name "part" -value "xczu3eg-sbva484-1-i" -objects $obj 130 | set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj 131 | set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj 132 | set_property -name "simulator_language" -value "Mixed" -objects $obj 133 | set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj 134 | 135 | # Create 'sources_1' fileset (if not found) 136 | if {[string equal [get_filesets -quiet sources_1] ""]} { 137 | create_fileset -srcset sources_1 138 | } 139 | 140 | # Set 'sources_1' fileset object 141 | set obj [get_filesets sources_1] 142 | set files [list \ 143 | [file normalize "${origin_dir}/dac_sdc_wrapper.v"] \ 144 | ] 145 | add_files -norecurse -fileset $obj $files 146 | 147 | # Set 'sources_1' fileset file properties for remote files 148 | # None 149 | 150 | # Set 'sources_1' fileset file properties for local files 151 | # None 152 | 153 | # Set 'sources_1' fileset properties 154 | set obj [get_filesets sources_1] 155 | set_property -name "top" -value "dac_sdc_wrapper" -objects $obj 156 | set_property -name "top_auto_set" -value "0" -objects $obj 157 | 158 | # Create 'constrs_1' fileset (if not found) 159 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 160 | create_fileset -constrset constrs_1 161 | } 162 | 163 | # Set 'constrs_1' fileset object 164 | set obj [get_filesets constrs_1] 165 | 166 | # Add/Import constrs file and set constrs file properties 167 | set file "[file normalize "$origin_dir/constraints.xdc"]" 168 | set file_added [add_files -norecurse -fileset $obj [list $file]] 169 | set file "$origin_dir/constraints.xdc" 170 | set file [file normalize $file] 171 | set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] 172 | set_property -name "file_type" -value "XDC" -objects $file_obj 173 | 174 | # Set 'constrs_1' fileset properties 175 | set obj [get_filesets constrs_1] 176 | set_property -name "target_part" -value "xczu3eg-sbva484-1-i" -objects $obj 177 | 178 | # Create 'sim_1' fileset (if not found) 179 | if {[string equal [get_filesets -quiet sim_1] ""]} { 180 | create_fileset -simset sim_1 181 | } 182 | 183 | # Set 'sim_1' fileset object 184 | set obj [get_filesets sim_1] 185 | # Empty (no sources present) 186 | 187 | # Set 'sim_1' fileset properties 188 | set obj [get_filesets sim_1] 189 | set_property -name "top" -value "dac_sdc_wrapper" -objects $obj 190 | set_property -name "top_auto_set" -value "0" -objects $obj 191 | set_property -name "top_lib" -value "xil_defaultlib" -objects $obj 192 | 193 | # Set 'utils_1' fileset object 194 | set obj [get_filesets utils_1] 195 | # Empty (no sources present) 196 | 197 | # Set 'utils_1' fileset properties 198 | set obj [get_filesets utils_1] 199 | 200 | 201 | # Adding sources referenced in BDs, if not already added 202 | 203 | 204 | # Proc to create BD sensors96b 205 | proc cr_bd_sensors96b { parentCell } { 206 | 207 | # CHANGE DESIGN NAME HERE 208 | set design_name sensors96b 209 | 210 | common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." 211 | 212 | create_bd_design $design_name 213 | 214 | set bCheckIPsPassed 1 215 | ################################################################## 216 | # CHECK IPs 217 | ################################################################## 218 | set bCheckIPs 1 219 | if { $bCheckIPs == 1 } { 220 | set list_check_ips "\ 221 | xilinx.com:ip:axi_dma:7.1\ 222 | xilinx.com:ip:axi_uart16550:2.0\ 223 | xilinx.com:ip:axis_data_fifo:2.0\ 224 | xilinx.com:ip:proc_sys_reset:5.0\ 225 | xilinx.com:ip:xlconcat:2.1\ 226 | xilinx.com:ip:zynq_ultra_ps_e:3.3\ 227 | " 228 | 229 | set list_ips_missing "" 230 | common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." 231 | 232 | foreach ip_vlnv $list_check_ips { 233 | set ip_obj [get_ipdefs -all $ip_vlnv] 234 | if { $ip_obj eq "" } { 235 | lappend list_ips_missing $ip_vlnv 236 | } 237 | } 238 | 239 | if { $list_ips_missing ne "" } { 240 | catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } 241 | set bCheckIPsPassed 0 242 | } 243 | 244 | } 245 | 246 | if { $bCheckIPsPassed != 1 } { 247 | common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." 248 | return 3 249 | } 250 | 251 | variable script_folder 252 | 253 | if { $parentCell eq "" } { 254 | set parentCell [get_bd_cells /] 255 | } 256 | 257 | # Get object for parentCell 258 | set parentObj [get_bd_cells $parentCell] 259 | if { $parentObj == "" } { 260 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 261 | return 262 | } 263 | 264 | # Make sure parentObj is hier blk 265 | set parentType [get_property TYPE $parentObj] 266 | if { $parentType ne "hier" } { 267 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 268 | return 269 | } 270 | 271 | # Save current instance; Restore later 272 | set oldCurInst [current_bd_instance .] 273 | 274 | # Set parent object as current 275 | current_bd_instance $parentObj 276 | 277 | 278 | # Create interface ports 279 | set GPIO_SENSORS [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_SENSORS ] 280 | 281 | 282 | # Create ports 283 | set BT_ctsn [ create_bd_port -dir I BT_ctsn ] 284 | set BT_rtsn [ create_bd_port -dir O BT_rtsn ] 285 | set UART0_ctsn [ create_bd_port -dir I -type data UART0_ctsn ] 286 | set UART0_rtsn [ create_bd_port -dir O -type data UART0_rtsn ] 287 | set UART0_rxd [ create_bd_port -dir I UART0_rxd ] 288 | set UART0_txd [ create_bd_port -dir O UART0_txd ] 289 | set UART1_rxd [ create_bd_port -dir I UART1_rxd ] 290 | set UART1_txd [ create_bd_port -dir O UART1_txd ] 291 | 292 | # Create instance: axi_dma_0, and set properties 293 | set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] 294 | set_property -dict [ list \ 295 | CONFIG.c_include_sg {0} \ 296 | CONFIG.c_mm2s_burst_size {256} \ 297 | CONFIG.c_s2mm_burst_size {256} \ 298 | CONFIG.c_sg_include_stscntrl_strm {0} \ 299 | CONFIG.c_sg_length_width {23} \ 300 | ] $axi_dma_0 301 | 302 | # Create instance: axi_interconnect_0, and set properties 303 | set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] 304 | set_property -dict [ list \ 305 | CONFIG.NUM_MI {1} \ 306 | CONFIG.NUM_SI {2} \ 307 | ] $axi_interconnect_0 308 | 309 | # Create instance: axi_uart16550_0, and set properties 310 | set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ] 311 | set_property -dict [ list \ 312 | CONFIG.C_S_AXI_ACLK_FREQ_HZ {99999901} \ 313 | ] $axi_uart16550_0 314 | 315 | # Create instance: axi_uart16550_1, and set properties 316 | set axi_uart16550_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_1 ] 317 | set_property -dict [ list \ 318 | CONFIG.C_S_AXI_ACLK_FREQ_HZ {99999901} \ 319 | ] $axi_uart16550_1 320 | 321 | # Create instance: axis_data_fifo_0, and set properties 322 | set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ] 323 | set_property -dict [ list \ 324 | CONFIG.FIFO_DEPTH {32768} \ 325 | ] $axis_data_fifo_0 326 | 327 | # Create instance: proc_sys_reset_0, and set properties 328 | set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] 329 | 330 | # Create instance: ps8_0_axi_periph, and set properties 331 | set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] 332 | set_property -dict [ list \ 333 | CONFIG.NUM_MI {3} \ 334 | ] $ps8_0_axi_periph 335 | 336 | # Create instance: xlconcat_0, and set properties 337 | set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] 338 | set_property -dict [ list \ 339 | CONFIG.NUM_PORTS {2} \ 340 | ] $xlconcat_0 341 | 342 | # Create instance: zynq_ultra_ps_e_0, and set properties 343 | set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] 344 | set_property -dict [ list \ 345 | CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ 346 | CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ 347 | CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ 348 | CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ 349 | CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \ 350 | CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \ 351 | CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ 352 | CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ 353 | CONFIG.PSU_MIO_0_DIRECTION {out} \ 354 | CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ 355 | CONFIG.PSU_MIO_0_POLARITY {Default} \ 356 | CONFIG.PSU_MIO_10_DIRECTION {inout} \ 357 | CONFIG.PSU_MIO_10_POLARITY {Default} \ 358 | CONFIG.PSU_MIO_11_DIRECTION {inout} \ 359 | CONFIG.PSU_MIO_11_POLARITY {Default} \ 360 | CONFIG.PSU_MIO_12_DIRECTION {inout} \ 361 | CONFIG.PSU_MIO_12_POLARITY {Default} \ 362 | CONFIG.PSU_MIO_13_DIRECTION {inout} \ 363 | CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \ 364 | CONFIG.PSU_MIO_13_POLARITY {Default} \ 365 | CONFIG.PSU_MIO_14_DIRECTION {inout} \ 366 | CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \ 367 | CONFIG.PSU_MIO_14_POLARITY {Default} \ 368 | CONFIG.PSU_MIO_15_DIRECTION {inout} \ 369 | CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \ 370 | CONFIG.PSU_MIO_15_POLARITY {Default} \ 371 | CONFIG.PSU_MIO_16_DIRECTION {inout} \ 372 | CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \ 373 | CONFIG.PSU_MIO_16_POLARITY {Default} \ 374 | CONFIG.PSU_MIO_17_DIRECTION {inout} \ 375 | CONFIG.PSU_MIO_17_POLARITY {Default} \ 376 | CONFIG.PSU_MIO_18_DIRECTION {inout} \ 377 | CONFIG.PSU_MIO_18_POLARITY {Default} \ 378 | CONFIG.PSU_MIO_19_DIRECTION {inout} \ 379 | CONFIG.PSU_MIO_19_POLARITY {Default} \ 380 | CONFIG.PSU_MIO_1_DIRECTION {in} \ 381 | CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ 382 | CONFIG.PSU_MIO_1_POLARITY {Default} \ 383 | CONFIG.PSU_MIO_1_SLEW {fast} \ 384 | CONFIG.PSU_MIO_20_DIRECTION {inout} \ 385 | CONFIG.PSU_MIO_20_POLARITY {Default} \ 386 | CONFIG.PSU_MIO_21_DIRECTION {inout} \ 387 | CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \ 388 | CONFIG.PSU_MIO_21_POLARITY {Default} \ 389 | CONFIG.PSU_MIO_22_DIRECTION {out} \ 390 | CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \ 391 | CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ 392 | CONFIG.PSU_MIO_22_POLARITY {Default} \ 393 | CONFIG.PSU_MIO_23_DIRECTION {inout} \ 394 | CONFIG.PSU_MIO_23_POLARITY {Default} \ 395 | CONFIG.PSU_MIO_24_DIRECTION {in} \ 396 | CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ 397 | CONFIG.PSU_MIO_24_POLARITY {Default} \ 398 | CONFIG.PSU_MIO_24_SLEW {fast} \ 399 | CONFIG.PSU_MIO_25_DIRECTION {inout} \ 400 | CONFIG.PSU_MIO_25_POLARITY {Default} \ 401 | CONFIG.PSU_MIO_26_DIRECTION {in} \ 402 | CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ 403 | CONFIG.PSU_MIO_26_POLARITY {Default} \ 404 | CONFIG.PSU_MIO_26_SLEW {fast} \ 405 | CONFIG.PSU_MIO_27_DIRECTION {out} \ 406 | CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ 407 | CONFIG.PSU_MIO_27_POLARITY {Default} \ 408 | CONFIG.PSU_MIO_28_DIRECTION {in} \ 409 | CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ 410 | CONFIG.PSU_MIO_28_POLARITY {Default} \ 411 | CONFIG.PSU_MIO_28_SLEW {fast} \ 412 | CONFIG.PSU_MIO_29_DIRECTION {out} \ 413 | CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ 414 | CONFIG.PSU_MIO_29_POLARITY {Default} \ 415 | CONFIG.PSU_MIO_2_DIRECTION {in} \ 416 | CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ 417 | CONFIG.PSU_MIO_2_POLARITY {Default} \ 418 | CONFIG.PSU_MIO_2_SLEW {fast} \ 419 | CONFIG.PSU_MIO_30_DIRECTION {in} \ 420 | CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ 421 | CONFIG.PSU_MIO_30_POLARITY {Default} \ 422 | CONFIG.PSU_MIO_30_SLEW {fast} \ 423 | CONFIG.PSU_MIO_31_DIRECTION {inout} \ 424 | CONFIG.PSU_MIO_31_POLARITY {Default} \ 425 | CONFIG.PSU_MIO_32_DIRECTION {out} \ 426 | CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ 427 | CONFIG.PSU_MIO_32_POLARITY {Default} \ 428 | CONFIG.PSU_MIO_33_DIRECTION {out} \ 429 | CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ 430 | CONFIG.PSU_MIO_33_POLARITY {Default} \ 431 | CONFIG.PSU_MIO_34_DIRECTION {out} \ 432 | CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ 433 | CONFIG.PSU_MIO_34_POLARITY {Default} \ 434 | CONFIG.PSU_MIO_35_DIRECTION {inout} \ 435 | CONFIG.PSU_MIO_35_POLARITY {Default} \ 436 | CONFIG.PSU_MIO_36_DIRECTION {inout} \ 437 | CONFIG.PSU_MIO_36_POLARITY {Default} \ 438 | CONFIG.PSU_MIO_37_DIRECTION {inout} \ 439 | CONFIG.PSU_MIO_37_POLARITY {Default} \ 440 | CONFIG.PSU_MIO_38_DIRECTION {inout} \ 441 | CONFIG.PSU_MIO_38_POLARITY {Default} \ 442 | CONFIG.PSU_MIO_39_DIRECTION {inout} \ 443 | CONFIG.PSU_MIO_39_POLARITY {Default} \ 444 | CONFIG.PSU_MIO_3_DIRECTION {out} \ 445 | CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ 446 | CONFIG.PSU_MIO_3_POLARITY {Default} \ 447 | CONFIG.PSU_MIO_40_DIRECTION {inout} \ 448 | CONFIG.PSU_MIO_40_POLARITY {Default} \ 449 | CONFIG.PSU_MIO_41_DIRECTION {inout} \ 450 | CONFIG.PSU_MIO_41_POLARITY {Default} \ 451 | CONFIG.PSU_MIO_42_DIRECTION {inout} \ 452 | CONFIG.PSU_MIO_42_POLARITY {Default} \ 453 | CONFIG.PSU_MIO_43_DIRECTION {inout} \ 454 | CONFIG.PSU_MIO_43_POLARITY {Default} \ 455 | CONFIG.PSU_MIO_44_DIRECTION {inout} \ 456 | CONFIG.PSU_MIO_44_POLARITY {Default} \ 457 | CONFIG.PSU_MIO_45_DIRECTION {inout} \ 458 | CONFIG.PSU_MIO_45_POLARITY {Default} \ 459 | CONFIG.PSU_MIO_46_DIRECTION {inout} \ 460 | CONFIG.PSU_MIO_46_POLARITY {Default} \ 461 | CONFIG.PSU_MIO_47_DIRECTION {inout} \ 462 | CONFIG.PSU_MIO_47_POLARITY {Default} \ 463 | CONFIG.PSU_MIO_48_DIRECTION {inout} \ 464 | CONFIG.PSU_MIO_48_POLARITY {Default} \ 465 | CONFIG.PSU_MIO_49_DIRECTION {inout} \ 466 | CONFIG.PSU_MIO_49_POLARITY {Default} \ 467 | CONFIG.PSU_MIO_4_DIRECTION {inout} \ 468 | CONFIG.PSU_MIO_4_POLARITY {Default} \ 469 | CONFIG.PSU_MIO_50_DIRECTION {inout} \ 470 | CONFIG.PSU_MIO_50_POLARITY {Default} \ 471 | CONFIG.PSU_MIO_51_DIRECTION {out} \ 472 | CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ 473 | CONFIG.PSU_MIO_51_POLARITY {Default} \ 474 | CONFIG.PSU_MIO_52_DIRECTION {in} \ 475 | CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ 476 | CONFIG.PSU_MIO_52_POLARITY {Default} \ 477 | CONFIG.PSU_MIO_52_SLEW {fast} \ 478 | CONFIG.PSU_MIO_53_DIRECTION {in} \ 479 | CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ 480 | CONFIG.PSU_MIO_53_POLARITY {Default} \ 481 | CONFIG.PSU_MIO_53_SLEW {fast} \ 482 | CONFIG.PSU_MIO_54_DIRECTION {inout} \ 483 | CONFIG.PSU_MIO_54_POLARITY {Default} \ 484 | CONFIG.PSU_MIO_55_DIRECTION {in} \ 485 | CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ 486 | CONFIG.PSU_MIO_55_POLARITY {Default} \ 487 | CONFIG.PSU_MIO_55_SLEW {fast} \ 488 | CONFIG.PSU_MIO_56_DIRECTION {inout} \ 489 | CONFIG.PSU_MIO_56_POLARITY {Default} \ 490 | CONFIG.PSU_MIO_57_DIRECTION {inout} \ 491 | CONFIG.PSU_MIO_57_POLARITY {Default} \ 492 | CONFIG.PSU_MIO_58_DIRECTION {out} \ 493 | CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ 494 | CONFIG.PSU_MIO_58_POLARITY {Default} \ 495 | CONFIG.PSU_MIO_59_DIRECTION {inout} \ 496 | CONFIG.PSU_MIO_59_POLARITY {Default} \ 497 | CONFIG.PSU_MIO_5_DIRECTION {inout} \ 498 | CONFIG.PSU_MIO_5_POLARITY {Default} \ 499 | CONFIG.PSU_MIO_60_DIRECTION {inout} \ 500 | CONFIG.PSU_MIO_60_POLARITY {Default} \ 501 | CONFIG.PSU_MIO_61_DIRECTION {inout} \ 502 | CONFIG.PSU_MIO_61_POLARITY {Default} \ 503 | CONFIG.PSU_MIO_62_DIRECTION {inout} \ 504 | CONFIG.PSU_MIO_62_POLARITY {Default} \ 505 | CONFIG.PSU_MIO_63_DIRECTION {inout} \ 506 | CONFIG.PSU_MIO_63_POLARITY {Default} \ 507 | CONFIG.PSU_MIO_64_DIRECTION {in} \ 508 | CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ 509 | CONFIG.PSU_MIO_64_POLARITY {Default} \ 510 | CONFIG.PSU_MIO_64_SLEW {fast} \ 511 | CONFIG.PSU_MIO_65_DIRECTION {in} \ 512 | CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ 513 | CONFIG.PSU_MIO_65_POLARITY {Default} \ 514 | CONFIG.PSU_MIO_65_SLEW {fast} \ 515 | CONFIG.PSU_MIO_66_DIRECTION {inout} \ 516 | CONFIG.PSU_MIO_66_POLARITY {Default} \ 517 | CONFIG.PSU_MIO_67_DIRECTION {in} \ 518 | CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ 519 | CONFIG.PSU_MIO_67_POLARITY {Default} \ 520 | CONFIG.PSU_MIO_67_SLEW {fast} \ 521 | CONFIG.PSU_MIO_68_DIRECTION {inout} \ 522 | CONFIG.PSU_MIO_68_POLARITY {Default} \ 523 | CONFIG.PSU_MIO_69_DIRECTION {inout} \ 524 | CONFIG.PSU_MIO_69_POLARITY {Default} \ 525 | CONFIG.PSU_MIO_6_DIRECTION {inout} \ 526 | CONFIG.PSU_MIO_6_POLARITY {Default} \ 527 | CONFIG.PSU_MIO_70_DIRECTION {out} \ 528 | CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ 529 | CONFIG.PSU_MIO_70_POLARITY {Default} \ 530 | CONFIG.PSU_MIO_71_DIRECTION {inout} \ 531 | CONFIG.PSU_MIO_71_POLARITY {Default} \ 532 | CONFIG.PSU_MIO_72_DIRECTION {inout} \ 533 | CONFIG.PSU_MIO_72_POLARITY {Default} \ 534 | CONFIG.PSU_MIO_73_DIRECTION {inout} \ 535 | CONFIG.PSU_MIO_73_POLARITY {Default} \ 536 | CONFIG.PSU_MIO_74_DIRECTION {inout} \ 537 | CONFIG.PSU_MIO_74_POLARITY {Default} \ 538 | CONFIG.PSU_MIO_75_DIRECTION {inout} \ 539 | CONFIG.PSU_MIO_75_POLARITY {Default} \ 540 | CONFIG.PSU_MIO_76_DIRECTION {inout} \ 541 | CONFIG.PSU_MIO_76_POLARITY {Default} \ 542 | CONFIG.PSU_MIO_77_DIRECTION {inout} \ 543 | CONFIG.PSU_MIO_77_POLARITY {Default} \ 544 | CONFIG.PSU_MIO_7_DIRECTION {inout} \ 545 | CONFIG.PSU_MIO_7_POLARITY {Default} \ 546 | CONFIG.PSU_MIO_8_DIRECTION {inout} \ 547 | CONFIG.PSU_MIO_8_POLARITY {Default} \ 548 | CONFIG.PSU_MIO_9_DIRECTION {inout} \ 549 | CONFIG.PSU_MIO_9_POLARITY {Default} \ 550 | CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ 551 | CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ 552 | CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ 553 | CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \ 554 | CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ 555 | CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.332825} \ 556 | CONFIG.PSU__AFI0_COHERENCY {0} \ 557 | CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.998901} \ 558 | CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ 559 | CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ 560 | CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ 561 | CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ 562 | CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \ 563 | CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ 564 | CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ 565 | CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ 566 | CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999756} \ 567 | CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ 568 | CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ 569 | CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \ 570 | CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ 571 | CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999756} \ 572 | CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ 573 | CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ 574 | CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666412} \ 575 | CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \ 576 | CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \ 577 | CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ 578 | CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999451} \ 579 | CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ 580 | CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ 581 | CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ 582 | CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ 583 | CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \ 584 | CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ 585 | CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ 586 | CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \ 587 | CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576017} \ 588 | CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \ 589 | CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ 590 | CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ 591 | CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \ 592 | CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214418} \ 593 | CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \ 594 | CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ 595 | CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ 596 | CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029297} \ 597 | CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \ 598 | CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ 599 | CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ 600 | CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \ 601 | CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999451} \ 602 | CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ 603 | CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ 604 | CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.999512} \ 605 | CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \ 606 | CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ 607 | CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \ 608 | CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ 609 | CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ 610 | CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ 611 | CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999901} \ 612 | CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ 613 | CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ 614 | CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.332825} \ 615 | CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ 616 | CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ 617 | CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ 618 | CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \ 619 | CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \ 620 | CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \ 621 | CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ 622 | CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \ 623 | CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ 624 | CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.999512} \ 625 | CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ 626 | CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ 627 | CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ 628 | CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724087} \ 629 | CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \ 630 | CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ 631 | CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ 632 | CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ 633 | CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ 634 | CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ 635 | CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ 636 | CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ 637 | CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ 638 | CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999512} \ 639 | CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ 640 | CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ 641 | CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \ 642 | CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \ 643 | CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \ 644 | CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \ 645 | CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999756} \ 646 | CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ 647 | CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ 648 | CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.998535} \ 649 | CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ 650 | CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ 651 | CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ 652 | CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ 653 | CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ 654 | CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ 655 | CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ 656 | CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ 657 | CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ 658 | CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ 659 | CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ 660 | CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ 661 | CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ 662 | CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ 663 | CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ 664 | CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ 665 | CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ 666 | CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ 667 | CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999901} \ 668 | CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ 669 | CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ 670 | CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ 671 | CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \ 672 | CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \ 673 | CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \ 674 | CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ 675 | CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ 676 | CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ 677 | CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.999756} \ 678 | CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ 679 | CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ 680 | CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999901} \ 681 | CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ 682 | CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ 683 | CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.999512} \ 684 | CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ 685 | CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ 686 | CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ 687 | CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ 688 | CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ 689 | CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499817} \ 690 | CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ 691 | CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ 692 | CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999901} \ 693 | CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ 694 | CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ 695 | CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ 696 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \ 697 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \ 698 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \ 699 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ 700 | CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ 701 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999695} \ 702 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \ 703 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ 704 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ 705 | CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \ 706 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999634} \ 707 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ 708 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ 709 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ 710 | CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {IOPLL} \ 711 | CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ 712 | CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ 713 | CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ 714 | CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ 715 | CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \ 716 | CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \ 717 | CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \ 718 | CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ 719 | CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \ 720 | CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \ 721 | CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.499817} \ 722 | CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \ 723 | CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ 724 | CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \ 725 | CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.499817} \ 726 | CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ 727 | CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ 728 | CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ 729 | CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.499817} \ 730 | CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \ 731 | CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ 732 | CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \ 733 | CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.499817} \ 734 | CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \ 735 | CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ 736 | CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \ 737 | CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999901} \ 738 | CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ 739 | CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ 740 | CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999901} \ 741 | CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ 742 | CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ 743 | CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ 744 | CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999901} \ 745 | CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ 746 | CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ 747 | CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ 748 | CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.999756} \ 749 | CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ 750 | CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ 751 | CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ 752 | CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {249.999756} \ 753 | CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ 754 | CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ 755 | CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ 756 | CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999979} \ 757 | CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \ 758 | CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \ 759 | CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ 760 | CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ 761 | CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ 762 | CONFIG.PSU__DDRC__ADDR_MIRROR {1} \ 763 | CONFIG.PSU__DDRC__AL {0} \ 764 | CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \ 765 | CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \ 766 | CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \ 767 | CONFIG.PSU__DDRC__CL {NA} \ 768 | CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ 769 | CONFIG.PSU__DDRC__COMPONENTS {Components} \ 770 | CONFIG.PSU__DDRC__CWL {NA} \ 771 | CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ 772 | CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ 773 | CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \ 774 | CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \ 775 | CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \ 776 | CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \ 777 | CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \ 778 | CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \ 779 | CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ 780 | CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \ 781 | CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ 782 | CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ 783 | CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ 784 | CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ 785 | CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ 786 | CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ 787 | CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ 788 | CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ 789 | CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ 790 | CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ 791 | CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ 792 | CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ 793 | CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ 794 | CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ 795 | CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ 796 | CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ 797 | CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ 798 | CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ 799 | CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ 800 | CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ 801 | CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \ 802 | CONFIG.PSU__DDRC__ENABLE {1} \ 803 | CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ 804 | CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \ 805 | CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ 806 | CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ 807 | CONFIG.PSU__DDRC__FGRM {NA} \ 808 | CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ 809 | CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \ 810 | CONFIG.PSU__DDRC__LP_ASR {NA} \ 811 | CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \ 812 | CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \ 813 | CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ 814 | CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ 815 | CONFIG.PSU__DDRC__SB_TARGET {NA} \ 816 | CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \ 817 | CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \ 818 | CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ 819 | CONFIG.PSU__DDRC__T_FAW {40} \ 820 | CONFIG.PSU__DDRC__T_RAS_MIN {42} \ 821 | CONFIG.PSU__DDRC__T_RC {64} \ 822 | CONFIG.PSU__DDRC__T_RCD {10} \ 823 | CONFIG.PSU__DDRC__T_RP {12} \ 824 | CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ 825 | CONFIG.PSU__DDRC__VREF {0} \ 826 | CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \ 827 | CONFIG.PSU__DDR_QOS_ENABLE {1} \ 828 | CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \ 829 | CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \ 830 | CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \ 831 | CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \ 832 | CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \ 833 | CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \ 834 | CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \ 835 | CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \ 836 | CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \ 837 | CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \ 838 | CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \ 839 | CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \ 840 | CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \ 841 | CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \ 842 | CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \ 843 | CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \ 844 | CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \ 845 | CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \ 846 | CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \ 847 | CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \ 848 | CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \ 849 | CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \ 850 | CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \ 851 | CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \ 852 | CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \ 853 | CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \ 854 | CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \ 855 | CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \ 856 | CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ 857 | CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ 858 | CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ 859 | CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ 860 | CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ 861 | CONFIG.PSU__DLL__ISUSED {1} \ 862 | CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ 863 | CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ 864 | CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ 865 | CONFIG.PSU__DP__REF_CLK_FREQ {27} \ 866 | CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ 867 | CONFIG.PSU__FPGA_PL0_ENABLE {1} \ 868 | CONFIG.PSU__FPGA_PL1_ENABLE {1} \ 869 | CONFIG.PSU__FPGA_PL2_ENABLE {1} \ 870 | CONFIG.PSU__FPGA_PL3_ENABLE {1} \ 871 | CONFIG.PSU__GEN_IPI__TRUSTZONE {