├── .gitignore ├── PROJECT.md ├── README.md ├── report.pdf ├── thinpad_top.srcs ├── constrs_1 │ └── new │ │ └── thinpad_top.xdc ├── sim_1 │ ├── imports │ │ ├── CFImemory64Mb_bottom.mem │ │ └── CFImemory64Mb_top.mem │ └── new │ │ ├── 28F640P30.v │ │ ├── clock.v │ │ ├── cpld_model.v │ │ ├── flag_sync_cpld.v │ │ ├── include │ │ ├── BankLib.h │ │ ├── CUIcommandData.h │ │ ├── TimingData.h │ │ ├── UserData.h │ │ ├── data.h │ │ └── def.h │ │ ├── sram_model.v │ │ ├── tb.sv │ │ ├── tb │ │ ├── lab2_tb.sv │ │ ├── lab3_tb.sv │ │ ├── lab4_tb.sv │ │ └── lab5_tb.sv │ │ └── uart_model.sv └── sources_1 │ ├── ip │ └── pll_example │ │ ├── pll_example.xci │ │ └── pll_example.xml │ └── new │ ├── SEG7_LUT.v │ ├── async.v │ ├── common │ ├── arbiter │ │ ├── arbiter.v │ │ ├── priority_encoder.v │ │ ├── wb_arbiter_2.v │ │ └── wb_arbiter_4.v │ ├── lfsr.v │ ├── lfsr_prng.sv │ ├── trigger.sv │ └── wb_mux_4.v │ ├── lab2 │ ├── counter.sv │ └── lab2_top.sv │ ├── lab3 │ └── lab3_top.sv │ ├── lab4 │ ├── lab4_top.sv │ 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