├── .gitignore
├── JLink_x64.dll
├── LICENSE
├── README.md
├── ReadmeFig
├── AddDir.png
├── AddDirPS.png
├── MCU_Recv.png
├── MCU_Send.png
├── RTT_Init.png
├── RTT_RAM.png
├── SEGGER_MCU.png
├── SimCoJLink.png
├── SimCoJLink_Lib.png
├── SimCoJLink_LibPS.png
├── SimCoJLink_Receive.png
├── SimCoJLink_SET.png
└── SimCoJLink_Transmit.png
├── SEGGER_MCU
├── CRC16.c
├── CRC16.h
├── SEGGER_RTT.c
├── SEGGER_RTT.h
├── SEGGER_RTT_Conf.h
└── SEGGER_RTT_printf.c
├── SimCoJLink_Example
├── NUM1_NUCLEO_G071RB_Cortex_M0
│ ├── KeilMDK_NUCLEOG071RB
│ │ ├── .mxproject
│ │ ├── Core
│ │ │ ├── Inc
│ │ │ │ ├── main.h
│ │ │ │ ├── stm32g0xx_hal_conf.h
│ │ │ │ └── stm32g0xx_it.h
│ │ │ └── Src
│ │ │ │ ├── main.c
│ │ │ │ ├── stm32g0xx_hal_msp.c
│ │ │ │ ├── stm32g0xx_it.c
│ │ │ │ └── system_stm32g0xx.c
│ │ ├── Drivers
│ │ │ └── STM32G0xx_HAL_Driver
│ │ │ │ ├── Inc
│ │ │ │ ├── Legacy
│ │ │ │ │ └── stm32_hal_legacy.h
│ │ │ │ ├── stm32_assert_template.h
│ │ │ │ ├── stm32g0xx_hal.h
│ │ │ │ ├── stm32g0xx_hal_adc.h
│ │ │ │ ├── stm32g0xx_hal_adc_ex.h
│ │ │ │ ├── stm32g0xx_hal_cec.h
│ │ │ │ ├── stm32g0xx_hal_comp.h
│ │ │ │ ├── stm32g0xx_hal_conf_template.h
│ │ │ │ ├── stm32g0xx_hal_cortex.h
│ │ │ │ ├── stm32g0xx_hal_crc.h
│ │ │ │ ├── stm32g0xx_hal_crc_ex.h
│ │ │ │ ├── stm32g0xx_hal_cryp.h
│ │ │ │ ├── stm32g0xx_hal_cryp_ex.h
│ │ │ │ ├── stm32g0xx_hal_dac.h
│ │ │ │ ├── stm32g0xx_hal_dac_ex.h
│ │ │ │ ├── stm32g0xx_hal_def.h
│ │ │ │ ├── stm32g0xx_hal_dma.h
│ │ │ │ ├── stm32g0xx_hal_dma_ex.h
│ │ │ │ ├── stm32g0xx_hal_exti.h
│ │ │ │ ├── stm32g0xx_hal_fdcan.h
│ │ │ │ ├── stm32g0xx_hal_flash.h
│ │ │ │ ├── stm32g0xx_hal_flash_ex.h
│ │ │ │ ├── stm32g0xx_hal_gpio.h
│ │ │ │ ├── stm32g0xx_hal_gpio_ex.h
│ │ │ │ ├── stm32g0xx_hal_hcd.h
│ │ │ │ ├── stm32g0xx_hal_i2c.h
│ │ │ │ ├── stm32g0xx_hal_i2c_ex.h
│ │ │ │ ├── stm32g0xx_hal_i2s.h
│ │ │ │ ├── stm32g0xx_hal_irda.h
│ │ │ │ ├── stm32g0xx_hal_irda_ex.h
│ │ │ │ ├── stm32g0xx_hal_iwdg.h
│ │ │ │ ├── stm32g0xx_hal_lptim.h
│ │ │ │ ├── stm32g0xx_hal_pcd.h
│ │ │ │ ├── stm32g0xx_hal_pcd_ex.h
│ │ │ │ ├── stm32g0xx_hal_pwr.h
│ │ │ │ ├── stm32g0xx_hal_pwr_ex.h
│ │ │ │ ├── stm32g0xx_hal_rcc.h
│ │ │ │ ├── stm32g0xx_hal_rcc_ex.h
│ │ │ │ ├── stm32g0xx_hal_rng.h
│ │ │ │ ├── stm32g0xx_hal_rtc.h
│ │ │ │ ├── stm32g0xx_hal_rtc_ex.h
│ │ │ │ ├── stm32g0xx_hal_smartcard.h
│ │ │ │ ├── stm32g0xx_hal_smartcard_ex.h
│ │ │ │ ├── stm32g0xx_hal_smbus.h
│ │ │ │ ├── stm32g0xx_hal_smbus_ex.h
│ │ │ │ ├── stm32g0xx_hal_spi.h
│ │ │ │ ├── stm32g0xx_hal_spi_ex.h
│ │ │ │ ├── stm32g0xx_hal_tim.h
│ │ │ │ ├── stm32g0xx_hal_tim_ex.h
│ │ │ │ ├── stm32g0xx_hal_uart.h
│ │ │ │ ├── stm32g0xx_hal_uart_ex.h
│ │ │ │ ├── stm32g0xx_hal_usart.h
│ │ │ │ ├── stm32g0xx_hal_usart_ex.h
│ │ │ │ ├── stm32g0xx_hal_wwdg.h
│ │ │ │ ├── stm32g0xx_ll_adc.h
│ │ │ │ ├── stm32g0xx_ll_bus.h
│ │ │ │ ├── stm32g0xx_ll_comp.h
│ │ │ │ ├── stm32g0xx_ll_cortex.h
│ │ │ │ ├── stm32g0xx_ll_crc.h
│ │ │ │ ├── stm32g0xx_ll_crs.h
│ │ │ │ ├── stm32g0xx_ll_dac.h
│ │ │ │ ├── stm32g0xx_ll_dma.h
│ │ │ │ ├── stm32g0xx_ll_dmamux.h
│ │ │ │ ├── stm32g0xx_ll_exti.h
│ │ │ │ ├── stm32g0xx_ll_gpio.h
│ │ │ │ ├── stm32g0xx_ll_i2c.h
│ │ │ │ ├── stm32g0xx_ll_iwdg.h
│ │ │ │ ├── stm32g0xx_ll_lptim.h
│ │ │ │ ├── stm32g0xx_ll_lpuart.h
│ │ │ │ ├── stm32g0xx_ll_pwr.h
│ │ │ │ ├── stm32g0xx_ll_rcc.h
│ │ │ │ ├── stm32g0xx_ll_rng.h
│ │ │ │ ├── stm32g0xx_ll_rtc.h
│ │ │ │ ├── stm32g0xx_ll_spi.h
│ │ │ │ ├── stm32g0xx_ll_system.h
│ │ │ │ ├── stm32g0xx_ll_tim.h
│ │ │ │ ├── stm32g0xx_ll_ucpd.h
│ │ │ │ ├── stm32g0xx_ll_usart.h
│ │ │ │ ├── stm32g0xx_ll_usb.h
│ │ │ │ ├── stm32g0xx_ll_utils.h
│ │ │ │ └── stm32g0xx_ll_wwdg.h
│ │ │ │ └── Src
│ │ │ │ ├── stm32g0xx_hal.c
│ │ │ │ ├── stm32g0xx_hal_adc.c
│ │ │ │ ├── stm32g0xx_hal_adc_ex.c
│ │ │ │ ├── stm32g0xx_hal_cec.c
│ │ │ │ ├── stm32g0xx_hal_comp.c
│ │ │ │ ├── stm32g0xx_hal_cortex.c
│ │ │ │ ├── stm32g0xx_hal_crc.c
│ │ │ │ ├── stm32g0xx_hal_crc_ex.c
│ │ │ │ ├── stm32g0xx_hal_cryp.c
│ │ │ │ ├── stm32g0xx_hal_cryp_ex.c
│ │ │ │ ├── stm32g0xx_hal_dac.c
│ │ │ │ ├── stm32g0xx_hal_dac_ex.c
│ │ │ │ ├── stm32g0xx_hal_dma.c
│ │ │ │ ├── stm32g0xx_hal_dma_ex.c
│ │ │ │ ├── stm32g0xx_hal_exti.c
│ │ │ │ ├── stm32g0xx_hal_fdcan.c
│ │ │ │ ├── stm32g0xx_hal_flash.c
│ │ │ │ ├── stm32g0xx_hal_flash_ex.c
│ │ │ │ ├── stm32g0xx_hal_gpio.c
│ │ │ │ ├── stm32g0xx_hal_hcd.c
│ │ │ │ ├── stm32g0xx_hal_i2c.c
│ │ │ │ ├── stm32g0xx_hal_i2c_ex.c
│ │ │ │ ├── stm32g0xx_hal_i2s.c
│ │ │ │ ├── stm32g0xx_hal_irda.c
│ │ │ │ ├── stm32g0xx_hal_iwdg.c
│ │ │ │ ├── stm32g0xx_hal_lptim.c
│ │ │ │ ├── stm32g0xx_hal_msp_template.c
│ │ │ │ ├── stm32g0xx_hal_pcd.c
│ │ │ │ ├── stm32g0xx_hal_pcd_ex.c
│ │ │ │ ├── stm32g0xx_hal_pwr.c
│ │ │ │ ├── stm32g0xx_hal_pwr_ex.c
│ │ │ │ ├── stm32g0xx_hal_rcc.c
│ │ │ │ ├── stm32g0xx_hal_rcc_ex.c
│ │ │ │ ├── stm32g0xx_hal_rng.c
│ │ │ │ ├── stm32g0xx_hal_rtc.c
│ │ │ │ ├── stm32g0xx_hal_rtc_ex.c
│ │ │ │ ├── stm32g0xx_hal_smartcard.c
│ │ │ │ ├── stm32g0xx_hal_smartcard_ex.c
│ │ │ │ ├── stm32g0xx_hal_smbus.c
│ │ │ │ ├── stm32g0xx_hal_smbus_ex.c
│ │ │ │ ├── stm32g0xx_hal_spi.c
│ │ │ │ ├── stm32g0xx_hal_spi_ex.c
│ │ │ │ ├── stm32g0xx_hal_tim.c
│ │ │ │ ├── stm32g0xx_hal_tim_ex.c
│ │ │ │ ├── stm32g0xx_hal_timebase_rtc_alarm_template.c
│ │ │ │ ├── stm32g0xx_hal_timebase_rtc_wakeup_template.c
│ │ │ │ ├── stm32g0xx_hal_timebase_tim_template.c
│ │ │ │ ├── stm32g0xx_hal_uart.c
│ │ │ │ ├── stm32g0xx_hal_uart_ex.c
│ │ │ │ ├── stm32g0xx_hal_usart.c
│ │ │ │ ├── stm32g0xx_hal_usart_ex.c
│ │ │ │ ├── stm32g0xx_hal_wwdg.c
│ │ │ │ ├── stm32g0xx_ll_adc.c
│ │ │ │ ├── stm32g0xx_ll_comp.c
│ │ │ │ ├── stm32g0xx_ll_crc.c
│ │ │ │ ├── stm32g0xx_ll_crs.c
│ │ │ │ ├── stm32g0xx_ll_dac.c
│ │ │ │ ├── stm32g0xx_ll_dma.c
│ │ │ │ ├── stm32g0xx_ll_exti.c
│ │ │ │ ├── stm32g0xx_ll_gpio.c
│ │ │ │ ├── stm32g0xx_ll_i2c.c
│ │ │ │ ├── stm32g0xx_ll_lptim.c
│ │ │ │ ├── stm32g0xx_ll_lpuart.c
│ │ │ │ ├── stm32g0xx_ll_pwr.c
│ │ │ │ ├── stm32g0xx_ll_rcc.c
│ │ │ │ ├── stm32g0xx_ll_rng.c
│ │ │ │ ├── stm32g0xx_ll_rtc.c
│ │ │ │ ├── stm32g0xx_ll_spi.c
│ │ │ │ ├── stm32g0xx_ll_tim.c
│ │ │ │ ├── stm32g0xx_ll_ucpd.c
│ │ │ │ ├── stm32g0xx_ll_usart.c
│ │ │ │ ├── stm32g0xx_ll_usb.c
│ │ │ │ └── stm32g0xx_ll_utils.c
│ │ ├── MDK-ARM
│ │ │ ├── DebugConfig
│ │ │ │ └── STM32G071_Cortex_M0_RTT_STM32G071RBTx_1.0.0.dbgconf
│ │ │ ├── EventRecorderStub.scvd
│ │ │ ├── JLinkLog.txt
│ │ │ ├── JLinkSettings.ini
│ │ │ ├── RTE
│ │ │ │ └── _STM32G071_Cortex_M0_RTT
│ │ │ │ │ └── RTE_Components.h
│ │ │ ├── STM32G071_Cortex_M0_RTT.uvguix.beau_
│ │ │ ├── STM32G071_Cortex_M0_RTT.uvoptx
│ │ │ ├── STM32G071_Cortex_M0_RTT.uvprojx
│ │ │ └── startup_stm32g071xx.s
│ │ ├── SEGGER
│ │ │ ├── CRC16.c
│ │ │ ├── CRC16.h
│ │ │ ├── SEGGER_RTT.c
│ │ │ ├── SEGGER_RTT.h
│ │ │ ├── SEGGER_RTT_Conf.h
│ │ │ └── SEGGER_RTT_printf.c
│ │ └── STM32G071RB_Cortex_M0.ioc
│ └── SimulinkHostModel
│ │ └── SimCoJLinkExample_G071.slx
└── NUM2_NUCLEO_G474RE_Cortex_M4
│ ├── KeilMDK_NUCLEOG474RE
│ ├── .mxproject
│ ├── Core
│ │ ├── Inc
│ │ │ ├── BspUtils.h
│ │ │ ├── bsp.h
│ │ │ ├── main.h
│ │ │ ├── stm32g4xx_hal_conf.h
│ │ │ └── stm32g4xx_it.h
│ │ └── Src
│ │ │ ├── BspUtils.c
│ │ │ ├── BspUtils_new.c
│ │ │ ├── bsp.c
│ │ │ ├── main.c
│ │ │ ├── stm32g4xx_hal_msp.c
│ │ │ ├── stm32g4xx_it.c
│ │ │ └── system_stm32g4xx.c
│ ├── Drivers
│ │ └── STM32G4xx_HAL_Driver
│ │ │ ├── Inc
│ │ │ ├── Legacy
│ │ │ │ └── stm32_hal_legacy.h
│ │ │ ├── stm32_assert_template.h
│ │ │ ├── stm32g4xx_hal.h
│ │ │ ├── stm32g4xx_hal_adc.h
│ │ │ ├── stm32g4xx_hal_adc_ex.h
│ │ │ ├── stm32g4xx_hal_comp.h
│ │ │ ├── stm32g4xx_hal_conf_template.h
│ │ │ ├── stm32g4xx_hal_cordic.h
│ │ │ ├── stm32g4xx_hal_cortex.h
│ │ │ ├── stm32g4xx_hal_crc.h
│ │ │ ├── stm32g4xx_hal_crc_ex.h
│ │ │ ├── stm32g4xx_hal_cryp.h
│ │ │ ├── stm32g4xx_hal_cryp_ex.h
│ │ │ ├── stm32g4xx_hal_dac.h
│ │ │ ├── stm32g4xx_hal_dac_ex.h
│ │ │ ├── stm32g4xx_hal_def.h
│ │ │ ├── stm32g4xx_hal_dma.h
│ │ │ ├── stm32g4xx_hal_dma_ex.h
│ │ │ ├── stm32g4xx_hal_exti.h
│ │ │ ├── stm32g4xx_hal_fdcan.h
│ │ │ ├── stm32g4xx_hal_flash.h
│ │ │ ├── stm32g4xx_hal_flash_ex.h
│ │ │ ├── stm32g4xx_hal_flash_ramfunc.h
│ │ │ ├── stm32g4xx_hal_fmac.h
│ │ │ ├── stm32g4xx_hal_gpio.h
│ │ │ ├── stm32g4xx_hal_gpio_ex.h
│ │ │ ├── stm32g4xx_hal_hrtim.h
│ │ │ ├── stm32g4xx_hal_i2c.h
│ │ │ ├── stm32g4xx_hal_i2c_ex.h
│ │ │ ├── stm32g4xx_hal_i2s.h
│ │ │ ├── stm32g4xx_hal_irda.h
│ │ │ ├── stm32g4xx_hal_irda_ex.h
│ │ │ ├── stm32g4xx_hal_iwdg.h
│ │ │ ├── stm32g4xx_hal_lptim.h
│ │ │ ├── stm32g4xx_hal_nand.h
│ │ │ ├── stm32g4xx_hal_nor.h
│ │ │ ├── stm32g4xx_hal_opamp.h
│ │ │ ├── stm32g4xx_hal_opamp_ex.h
│ │ │ ├── stm32g4xx_hal_pcd.h
│ │ │ ├── stm32g4xx_hal_pcd_ex.h
│ │ │ ├── stm32g4xx_hal_pwr.h
│ │ │ ├── stm32g4xx_hal_pwr_ex.h
│ │ │ ├── stm32g4xx_hal_qspi.h
│ │ │ ├── stm32g4xx_hal_rcc.h
│ │ │ ├── stm32g4xx_hal_rcc_ex.h
│ │ │ ├── stm32g4xx_hal_rng.h
│ │ │ ├── stm32g4xx_hal_rtc.h
│ │ │ ├── stm32g4xx_hal_rtc_ex.h
│ │ │ ├── stm32g4xx_hal_sai.h
│ │ │ ├── stm32g4xx_hal_sai_ex.h
│ │ │ ├── stm32g4xx_hal_smartcard.h
│ │ │ ├── stm32g4xx_hal_smartcard_ex.h
│ │ │ ├── stm32g4xx_hal_smbus.h
│ │ │ ├── stm32g4xx_hal_spi.h
│ │ │ ├── stm32g4xx_hal_spi_ex.h
│ │ │ ├── stm32g4xx_hal_sram.h
│ │ │ ├── stm32g4xx_hal_tim.h
│ │ │ ├── stm32g4xx_hal_tim_ex.h
│ │ │ ├── stm32g4xx_hal_uart.h
│ │ │ ├── stm32g4xx_hal_uart_ex.h
│ │ │ ├── stm32g4xx_hal_usart.h
│ │ │ ├── stm32g4xx_hal_usart_ex.h
│ │ │ ├── stm32g4xx_hal_wwdg.h
│ │ │ ├── stm32g4xx_ll_adc.h
│ │ │ ├── stm32g4xx_ll_bus.h
│ │ │ ├── stm32g4xx_ll_comp.h
│ │ │ ├── stm32g4xx_ll_cordic.h
│ │ │ ├── stm32g4xx_ll_cortex.h
│ │ │ ├── stm32g4xx_ll_crc.h
│ │ │ ├── stm32g4xx_ll_crs.h
│ │ │ ├── stm32g4xx_ll_dac.h
│ │ │ ├── stm32g4xx_ll_dma.h
│ │ │ ├── stm32g4xx_ll_dmamux.h
│ │ │ ├── stm32g4xx_ll_exti.h
│ │ │ ├── stm32g4xx_ll_fmac.h
│ │ │ ├── stm32g4xx_ll_fmc.h
│ │ │ ├── stm32g4xx_ll_gpio.h
│ │ │ ├── stm32g4xx_ll_hrtim.h
│ │ │ ├── stm32g4xx_ll_i2c.h
│ │ │ ├── stm32g4xx_ll_iwdg.h
│ │ │ ├── stm32g4xx_ll_lptim.h
│ │ │ ├── stm32g4xx_ll_lpuart.h
│ │ │ ├── stm32g4xx_ll_opamp.h
│ │ │ ├── stm32g4xx_ll_pwr.h
│ │ │ ├── stm32g4xx_ll_rcc.h
│ │ │ ├── stm32g4xx_ll_rng.h
│ │ │ ├── stm32g4xx_ll_rtc.h
│ │ │ ├── stm32g4xx_ll_spi.h
│ │ │ ├── stm32g4xx_ll_system.h
│ │ │ ├── stm32g4xx_ll_tim.h
│ │ │ ├── stm32g4xx_ll_ucpd.h
│ │ │ ├── stm32g4xx_ll_usart.h
│ │ │ ├── stm32g4xx_ll_usb.h
│ │ │ ├── stm32g4xx_ll_utils.h
│ │ │ └── stm32g4xx_ll_wwdg.h
│ │ │ └── Src
│ │ │ ├── stm32g4xx_hal.c
│ │ │ ├── stm32g4xx_hal_adc.c
│ │ │ ├── stm32g4xx_hal_adc_ex.c
│ │ │ ├── stm32g4xx_hal_comp.c
│ │ │ ├── stm32g4xx_hal_cordic.c
│ │ │ ├── stm32g4xx_hal_cortex.c
│ │ │ ├── stm32g4xx_hal_crc.c
│ │ │ ├── stm32g4xx_hal_crc_ex.c
│ │ │ ├── stm32g4xx_hal_cryp.c
│ │ │ ├── stm32g4xx_hal_cryp_ex.c
│ │ │ ├── stm32g4xx_hal_dac.c
│ │ │ ├── stm32g4xx_hal_dac_ex.c
│ │ │ ├── stm32g4xx_hal_dma.c
│ │ │ ├── stm32g4xx_hal_dma_ex.c
│ │ │ ├── stm32g4xx_hal_exti.c
│ │ │ ├── stm32g4xx_hal_fdcan.c
│ │ │ ├── stm32g4xx_hal_flash.c
│ │ │ ├── stm32g4xx_hal_flash_ex.c
│ │ │ ├── stm32g4xx_hal_flash_ramfunc.c
│ │ │ ├── stm32g4xx_hal_fmac.c
│ │ │ ├── stm32g4xx_hal_gpio.c
│ │ │ ├── stm32g4xx_hal_hrtim.c
│ │ │ ├── stm32g4xx_hal_i2c.c
│ │ │ ├── stm32g4xx_hal_i2c_ex.c
│ │ │ ├── stm32g4xx_hal_i2s.c
│ │ │ ├── stm32g4xx_hal_irda.c
│ │ │ ├── stm32g4xx_hal_iwdg.c
│ │ │ ├── stm32g4xx_hal_lptim.c
│ │ │ ├── stm32g4xx_hal_msp_template.c
│ │ │ ├── stm32g4xx_hal_nand.c
│ │ │ ├── stm32g4xx_hal_nor.c
│ │ │ ├── stm32g4xx_hal_opamp.c
│ │ │ ├── stm32g4xx_hal_opamp_ex.c
│ │ │ ├── stm32g4xx_hal_pcd.c
│ │ │ ├── stm32g4xx_hal_pcd_ex.c
│ │ │ ├── stm32g4xx_hal_pwr.c
│ │ │ ├── stm32g4xx_hal_pwr_ex.c
│ │ │ ├── stm32g4xx_hal_qspi.c
│ │ │ ├── stm32g4xx_hal_rcc.c
│ │ │ ├── stm32g4xx_hal_rcc_ex.c
│ │ │ ├── stm32g4xx_hal_rng.c
│ │ │ ├── stm32g4xx_hal_rtc.c
│ │ │ ├── stm32g4xx_hal_rtc_ex.c
│ │ │ ├── stm32g4xx_hal_sai.c
│ │ │ ├── stm32g4xx_hal_sai_ex.c
│ │ │ ├── stm32g4xx_hal_smartcard.c
│ │ │ ├── stm32g4xx_hal_smartcard_ex.c
│ │ │ ├── stm32g4xx_hal_smbus.c
│ │ │ ├── stm32g4xx_hal_spi.c
│ │ │ ├── stm32g4xx_hal_spi_ex.c
│ │ │ ├── stm32g4xx_hal_sram.c
│ │ │ ├── stm32g4xx_hal_tim.c
│ │ │ ├── stm32g4xx_hal_tim_ex.c
│ │ │ ├── stm32g4xx_hal_timebase_tim_template.c
│ │ │ ├── stm32g4xx_hal_uart.c
│ │ │ ├── stm32g4xx_hal_uart_ex.c
│ │ │ ├── stm32g4xx_hal_usart.c
│ │ │ ├── stm32g4xx_hal_usart_ex.c
│ │ │ ├── stm32g4xx_hal_wwdg.c
│ │ │ ├── stm32g4xx_ll_adc.c
│ │ │ ├── stm32g4xx_ll_comp.c
│ │ │ ├── stm32g4xx_ll_cordic.c
│ │ │ ├── stm32g4xx_ll_crc.c
│ │ │ ├── stm32g4xx_ll_crs.c
│ │ │ ├── stm32g4xx_ll_dac.c
│ │ │ ├── stm32g4xx_ll_dma.c
│ │ │ ├── stm32g4xx_ll_exti.c
│ │ │ ├── stm32g4xx_ll_fmac.c
│ │ │ ├── stm32g4xx_ll_fmc.c
│ │ │ ├── stm32g4xx_ll_gpio.c
│ │ │ ├── stm32g4xx_ll_hrtim.c
│ │ │ ├── stm32g4xx_ll_i2c.c
│ │ │ ├── stm32g4xx_ll_lptim.c
│ │ │ ├── stm32g4xx_ll_lpuart.c
│ │ │ ├── stm32g4xx_ll_opamp.c
│ │ │ ├── stm32g4xx_ll_pwr.c
│ │ │ ├── stm32g4xx_ll_rcc.c
│ │ │ ├── stm32g4xx_ll_rng.c
│ │ │ ├── stm32g4xx_ll_rtc.c
│ │ │ ├── stm32g4xx_ll_spi.c
│ │ │ ├── stm32g4xx_ll_tim.c
│ │ │ ├── stm32g4xx_ll_ucpd.c
│ │ │ ├── stm32g4xx_ll_usart.c
│ │ │ ├── stm32g4xx_ll_usb.c
│ │ │ └── stm32g4xx_ll_utils.c
│ ├── MDK-ARM
│ │ ├── DebugConfig
│ │ │ ├── STM32G474RET_ESC_STM32G474RETx.dbgconf
│ │ │ └── STM32G474RE_Cortex_M4_STM32G474RETx.dbgconf
│ │ ├── EventRecorderStub.scvd
│ │ ├── JLinkLog.txt
│ │ ├── JLinkSettings.ini
│ │ ├── RTE
│ │ │ └── _STM32G474RE_Cortex_M4
│ │ │ │ └── RTE_Components.h
│ │ ├── STM32G474RE_Cortex_M4.uvguix.beau_
│ │ ├── STM32G474RE_Cortex_M4.uvoptx
│ │ ├── STM32G474RE_Cortex_M4.uvprojx
│ │ └── startup_stm32g474xx.s
│ ├── SEGGER
│ │ ├── CRC16.c
│ │ ├── CRC16.h
│ │ ├── SEGGER_RTT.c
│ │ ├── SEGGER_RTT.h
│ │ ├── SEGGER_RTT_Conf.h
│ │ └── SEGGER_RTT_printf.c
│ └── STM32G474RE_Cortex_M4.ioc
│ └── SimulinkHostModel
│ └── SimCoJLinkExample_G474.slx
├── SimCoJLink_SimulinkLib
├── SimCoJLink.slx
├── SimCoJLink_Receive.mexw64
├── SimCoJLink_Set.mexw64
├── SimCoJLink_Transmit.mexw64
└── slblocks.m
└── SimCoJLink使用说明.pdf
/.gitignore:
--------------------------------------------------------------------------------
1 | *.o
2 | *.log
3 | *.crf
4 | *.d
5 | *.axf
6 | *.map
7 | *.hex
8 | NUM4*/*
9 | SimCoJLink_Example/*
10 | SimCoJLink_SimulinkLib/*
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/JLink_x64.dll:
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/SEGGER_MCU/CRC16.c:
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1 | static const unsigned char aucCRCHi[] = {
2 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
3 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
4 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
5 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
6 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
7 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
8 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
9 | 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
10 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
11 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
12 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
13 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
14 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
15 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
16 | 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
17 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
18 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
19 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
20 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
21 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
22 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
23 | 0x00, 0xC1, 0x81, 0x40
24 | };
25 |
26 | static const unsigned char aucCRCLo[] = {
27 | 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
28 | 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
29 | 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
30 | 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
31 | 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
32 | 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
33 | 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
34 | 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
35 | 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
36 | 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
37 | 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
38 | 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
39 | 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
40 | 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
41 | 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
42 | 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
43 | 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
44 | 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
45 | 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
46 | 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
47 | 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
48 | 0x41, 0x81, 0x80, 0x40
49 | };
50 |
51 | unsigned short usMBCRC16(unsigned char * pucFrame, unsigned short usLen)
52 | {
53 | unsigned char ucCRCHi = 0xFF;
54 | unsigned char ucCRCLo = 0xFF;
55 | int iIndex;
56 |
57 | while (usLen--)
58 | {
59 | iIndex = ucCRCLo ^ *(pucFrame++);
60 | ucCRCLo = (unsigned char)(ucCRCHi ^ aucCRCHi[iIndex]);
61 | ucCRCHi = aucCRCLo[iIndex];
62 | }
63 | return (unsigned short)(ucCRCHi << 8 | ucCRCLo);
64 | }
65 |
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/SEGGER_MCU/CRC16.h:
--------------------------------------------------------------------------------
1 |
2 | extern unsigned short usMBCRC16(unsigned char * pucFrame, unsigned short usLen);
3 |
4 |
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Core/Inc/main.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.h
5 | * @brief : Header for main.c file.
6 | * This file contains the common defines of the application.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2022 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __MAIN_H
24 | #define __MAIN_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32g0xx_hal.h"
32 |
33 | /* Private includes ----------------------------------------------------------*/
34 | /* USER CODE BEGIN Includes */
35 |
36 | /* USER CODE END Includes */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* USER CODE BEGIN ET */
40 |
41 | /* USER CODE END ET */
42 |
43 | /* Exported constants --------------------------------------------------------*/
44 | /* USER CODE BEGIN EC */
45 |
46 | /* USER CODE END EC */
47 |
48 | /* Exported macro ------------------------------------------------------------*/
49 | /* USER CODE BEGIN EM */
50 |
51 | /* USER CODE END EM */
52 |
53 | /* Exported functions prototypes ---------------------------------------------*/
54 | void Error_Handler(void);
55 |
56 | /* USER CODE BEGIN EFP */
57 |
58 | /* USER CODE END EFP */
59 |
60 | /* Private defines -----------------------------------------------------------*/
61 | /* USER CODE BEGIN Private defines */
62 |
63 | /* USER CODE END Private defines */
64 |
65 | #ifdef __cplusplus
66 | }
67 | #endif
68 |
69 | #endif /* __MAIN_H */
70 |
71 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
72 |
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Core/Inc/stm32g0xx_it.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32g0xx_it.h
5 | * @brief This file contains the headers of the interrupt handlers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2022 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32G0xx_IT_H
23 | #define __STM32G0xx_IT_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Private includes ----------------------------------------------------------*/
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 | /* USER CODE BEGIN ET */
36 |
37 | /* USER CODE END ET */
38 |
39 | /* Exported constants --------------------------------------------------------*/
40 | /* USER CODE BEGIN EC */
41 |
42 | /* USER CODE END EC */
43 |
44 | /* Exported macro ------------------------------------------------------------*/
45 | /* USER CODE BEGIN EM */
46 |
47 | /* USER CODE END EM */
48 |
49 | /* Exported functions prototypes ---------------------------------------------*/
50 | void NMI_Handler(void);
51 | void HardFault_Handler(void);
52 | void SVC_Handler(void);
53 | void PendSV_Handler(void);
54 | void SysTick_Handler(void);
55 | void TIM1_BRK_UP_TRG_COM_IRQHandler(void);
56 | /* USER CODE BEGIN EFP */
57 |
58 | /* USER CODE END EFP */
59 |
60 | #ifdef __cplusplus
61 | }
62 | #endif
63 |
64 | #endif /* __STM32G0xx_IT_H */
65 |
66 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
67 |
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Core/Src/stm32g0xx_hal_msp.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32g0xx_hal_msp.c
5 | * @brief This file provides code for the MSP Initialization
6 | * and de-Initialization codes.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2022 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "main.h"
24 | /* USER CODE BEGIN Includes */
25 |
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN Define */
35 |
36 | /* USER CODE END Define */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN Macro */
40 |
41 | /* USER CODE END Macro */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* External functions --------------------------------------------------------*/
54 | /* USER CODE BEGIN ExternalFunctions */
55 |
56 | /* USER CODE END ExternalFunctions */
57 |
58 | /* USER CODE BEGIN 0 */
59 |
60 | /* USER CODE END 0 */
61 | /**
62 | * Initializes the Global MSP.
63 | */
64 | void HAL_MspInit(void)
65 | {
66 | /* USER CODE BEGIN MspInit 0 */
67 |
68 | /* USER CODE END MspInit 0 */
69 |
70 | __HAL_RCC_SYSCFG_CLK_ENABLE();
71 | __HAL_RCC_PWR_CLK_ENABLE();
72 |
73 | /* System interrupt init*/
74 |
75 | /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
76 | */
77 | HAL_SYSCFG_StrobeDBattpinsConfig(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
78 |
79 | /* USER CODE BEGIN MspInit 1 */
80 |
81 | /* USER CODE END MspInit 1 */
82 | }
83 |
84 | /**
85 | * @brief TIM_Base MSP Initialization
86 | * This function configures the hardware resources used in this example
87 | * @param htim_base: TIM_Base handle pointer
88 | * @retval None
89 | */
90 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
91 | {
92 | if(htim_base->Instance==TIM1)
93 | {
94 | /* USER CODE BEGIN TIM1_MspInit 0 */
95 |
96 | /* USER CODE END TIM1_MspInit 0 */
97 | /* Peripheral clock enable */
98 | __HAL_RCC_TIM1_CLK_ENABLE();
99 | /* TIM1 interrupt Init */
100 | HAL_NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn, 0, 0);
101 | HAL_NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn);
102 | /* USER CODE BEGIN TIM1_MspInit 1 */
103 |
104 | /* USER CODE END TIM1_MspInit 1 */
105 | }
106 |
107 | }
108 |
109 | /**
110 | * @brief TIM_Base MSP De-Initialization
111 | * This function freeze the hardware resources used in this example
112 | * @param htim_base: TIM_Base handle pointer
113 | * @retval None
114 | */
115 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
116 | {
117 | if(htim_base->Instance==TIM1)
118 | {
119 | /* USER CODE BEGIN TIM1_MspDeInit 0 */
120 |
121 | /* USER CODE END TIM1_MspDeInit 0 */
122 | /* Peripheral clock disable */
123 | __HAL_RCC_TIM1_CLK_DISABLE();
124 |
125 | /* TIM1 interrupt DeInit */
126 | HAL_NVIC_DisableIRQ(TIM1_BRK_UP_TRG_COM_IRQn);
127 | /* USER CODE BEGIN TIM1_MspDeInit 1 */
128 |
129 | /* USER CODE END TIM1_MspDeInit 1 */
130 | }
131 |
132 | }
133 |
134 | /* USER CODE BEGIN 1 */
135 |
136 | /* USER CODE END 1 */
137 |
138 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
139 |
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Core/Src/stm32g0xx_it.c:
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1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32g0xx_it.c
5 | * @brief Interrupt Service Routines.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2022 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 | #include "stm32g0xx_it.h"
24 | /* Private includes ----------------------------------------------------------*/
25 | /* USER CODE BEGIN Includes */
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN PD */
35 |
36 | /* USER CODE END PD */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN PM */
40 |
41 | /* USER CODE END PM */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* Private user code ---------------------------------------------------------*/
54 | /* USER CODE BEGIN 0 */
55 |
56 | /* USER CODE END 0 */
57 |
58 | /* External variables --------------------------------------------------------*/
59 | extern TIM_HandleTypeDef htim1;
60 | /* USER CODE BEGIN EV */
61 |
62 | /* USER CODE END EV */
63 |
64 | /******************************************************************************/
65 | /* Cortex-M0+ Processor Interruption and Exception Handlers */
66 | /******************************************************************************/
67 | /**
68 | * @brief This function handles Non maskable interrupt.
69 | */
70 | void NMI_Handler(void)
71 | {
72 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
73 |
74 | /* USER CODE END NonMaskableInt_IRQn 0 */
75 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
76 | while (1)
77 | {
78 | }
79 | /* USER CODE END NonMaskableInt_IRQn 1 */
80 | }
81 |
82 | /**
83 | * @brief This function handles Hard fault interrupt.
84 | */
85 | void HardFault_Handler(void)
86 | {
87 | /* USER CODE BEGIN HardFault_IRQn 0 */
88 |
89 | /* USER CODE END HardFault_IRQn 0 */
90 | while (1)
91 | {
92 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */
93 | /* USER CODE END W1_HardFault_IRQn 0 */
94 | }
95 | }
96 |
97 | /**
98 | * @brief This function handles System service call via SWI instruction.
99 | */
100 | void SVC_Handler(void)
101 | {
102 | /* USER CODE BEGIN SVC_IRQn 0 */
103 |
104 | /* USER CODE END SVC_IRQn 0 */
105 | /* USER CODE BEGIN SVC_IRQn 1 */
106 |
107 | /* USER CODE END SVC_IRQn 1 */
108 | }
109 |
110 | /**
111 | * @brief This function handles Pendable request for system service.
112 | */
113 | void PendSV_Handler(void)
114 | {
115 | /* USER CODE BEGIN PendSV_IRQn 0 */
116 |
117 | /* USER CODE END PendSV_IRQn 0 */
118 | /* USER CODE BEGIN PendSV_IRQn 1 */
119 |
120 | /* USER CODE END PendSV_IRQn 1 */
121 | }
122 |
123 | /**
124 | * @brief This function handles System tick timer.
125 | */
126 | void SysTick_Handler(void)
127 | {
128 | /* USER CODE BEGIN SysTick_IRQn 0 */
129 |
130 | /* USER CODE END SysTick_IRQn 0 */
131 | HAL_IncTick();
132 | /* USER CODE BEGIN SysTick_IRQn 1 */
133 |
134 | /* USER CODE END SysTick_IRQn 1 */
135 | }
136 |
137 | /******************************************************************************/
138 | /* STM32G0xx Peripheral Interrupt Handlers */
139 | /* Add here the Interrupt Handlers for the used peripherals. */
140 | /* For the available peripheral interrupt handler names, */
141 | /* please refer to the startup file (startup_stm32g0xx.s). */
142 | /******************************************************************************/
143 |
144 | /**
145 | * @brief This function handles TIM1 break, update, trigger and commutation interrupts.
146 | */
147 | void TIM1_BRK_UP_TRG_COM_IRQHandler(void)
148 | {
149 | /* USER CODE BEGIN TIM1_BRK_UP_TRG_COM_IRQn 0 */
150 |
151 | /* USER CODE END TIM1_BRK_UP_TRG_COM_IRQn 0 */
152 | HAL_TIM_IRQHandler(&htim1);
153 | /* USER CODE BEGIN TIM1_BRK_UP_TRG_COM_IRQn 1 */
154 |
155 | /* USER CODE END TIM1_BRK_UP_TRG_COM_IRQn 1 */
156 | }
157 |
158 | /* USER CODE BEGIN 1 */
159 |
160 | /* USER CODE END 1 */
161 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
162 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Inc/stm32_assert_template.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32_assert.h
4 | * @author MCD Application Team
5 | * @brief STM32 assert template file.
6 | * This file should be copied to the application folder and renamed
7 | * to stm32_assert.h.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © Copyright (c) 2018 STMicroelectronics.
12 | * All rights reserved.
13 | *
14 | * This software component is licensed by ST under BSD 3-Clause license,
15 | * the "License"; You may not use this file except in compliance with the
16 | * License. You may obtain a copy of the License at:
17 | * opensource.org/licenses/BSD-3-Clause
18 | *
19 | ******************************************************************************
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef STM32_ASSERT_H
24 | #define STM32_ASSERT_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Exported types ------------------------------------------------------------*/
31 | /* Exported constants --------------------------------------------------------*/
32 | /* Includes ------------------------------------------------------------------*/
33 | /* Exported macro ------------------------------------------------------------*/
34 | #ifdef USE_FULL_ASSERT
35 | /**
36 | * @brief The assert_param macro is used for functions parameters check.
37 | * @param expr: If expr is false, it calls assert_failed function
38 | * which reports the name of the source file and the source
39 | * line number of the call that failed.
40 | * If expr is true, it returns no value.
41 | * @retval None
42 | */
43 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
44 | /* Exported functions ------------------------------------------------------- */
45 | void assert_failed(uint8_t *file, uint32_t line);
46 | #else
47 | #define assert_param(expr) ((void)0U)
48 | #endif /* USE_FULL_ASSERT */
49 |
50 | #ifdef __cplusplus
51 | }
52 | #endif
53 |
54 | #endif /* STM32_ASSERT_H */
55 |
56 |
57 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
58 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_crc_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_crc_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of CRC HAL extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_CRC_EX_H
22 | #define STM32G0xx_HAL_CRC_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G0xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup CRCEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
42 | * @{
43 | */
44 |
45 | /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
46 | * @{
47 | */
48 | #define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
49 | #define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
50 | #define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
51 | #define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
52 | /**
53 | * @}
54 | */
55 |
56 | /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
57 | * @{
58 | */
59 | #define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
60 | #define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
61 | /**
62 | * @}
63 | */
64 |
65 | /**
66 | * @}
67 | */
68 |
69 | /* Exported macro ------------------------------------------------------------*/
70 | /** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
71 | * @{
72 | */
73 |
74 | /**
75 | * @brief Set CRC output reversal
76 | * @param __HANDLE__ CRC handle
77 | * @retval None
78 | */
79 | #define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
80 |
81 | /**
82 | * @brief Unset CRC output reversal
83 | * @param __HANDLE__ CRC handle
84 | * @retval None
85 | */
86 | #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
87 |
88 | /**
89 | * @brief Set CRC non-default polynomial
90 | * @param __HANDLE__ CRC handle
91 | * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
92 | * @retval None
93 | */
94 | #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
95 |
96 | /**
97 | * @}
98 | */
99 |
100 | /* Private macros --------------------------------------------------------*/
101 | /** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
102 | * @{
103 | */
104 |
105 | #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
106 | ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
107 | ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
108 | ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
109 |
110 | #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
111 | ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | /* Exported functions --------------------------------------------------------*/
118 |
119 | /** @addtogroup CRCEx_Exported_Functions
120 | * @{
121 | */
122 |
123 | /** @addtogroup CRCEx_Exported_Functions_Group1
124 | * @{
125 | */
126 | /* Initialization and de-initialization functions ****************************/
127 | HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
128 | HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
129 | HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
130 |
131 | /**
132 | * @}
133 | */
134 |
135 | /**
136 | * @}
137 | */
138 |
139 | /**
140 | * @}
141 | */
142 |
143 | /**
144 | * @}
145 | */
146 |
147 | #ifdef __cplusplus
148 | }
149 | #endif
150 |
151 | #endif /* STM32G0xx_HAL_CRC_EX_H */
152 |
153 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
154 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_cryp_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of CRYPEx HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_CRYP_EX_H
22 | #define STM32G0xx_HAL_CRYP_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G0xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | #if defined(AES)
36 |
37 | /** @defgroup CRYPEx CRYPEx
38 | * @brief CRYP Extension HAL module driver.
39 | * @{
40 | */
41 |
42 | /* Exported types ------------------------------------------------------------*/
43 | /* Exported constants --------------------------------------------------------*/
44 | /* Private types -------------------------------------------------------------*/
45 | /** @defgroup CRYPEx_Private_Types CRYPEx Private Types
46 | * @{
47 | */
48 |
49 | /**
50 | * @}
51 | */
52 |
53 | /* Private variables ---------------------------------------------------------*/
54 | /** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
55 | * @{
56 | */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /* Private constants ---------------------------------------------------------*/
63 | /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
64 | * @{
65 | */
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /* Private macros ------------------------------------------------------------*/
72 | /** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
73 | * @{
74 | */
75 |
76 | /**
77 | * @}
78 | */
79 |
80 | /* Private functions ---------------------------------------------------------*/
81 | /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
82 | * @{
83 | */
84 |
85 | /**
86 | * @}
87 | */
88 |
89 | /* Exported functions --------------------------------------------------------*/
90 | /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
91 | * @{
92 | */
93 |
94 | /** @addtogroup CRYPEx_Exported_Functions_Group1
95 | * @{
96 | */
97 | HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
98 | HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
99 |
100 | /**
101 | * @}
102 | */
103 |
104 | /** @addtogroup CRYPEx_Exported_Functions_Group2
105 | * @{
106 | */
107 | void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
108 | void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
109 |
110 | /**
111 | * @}
112 | */
113 |
114 | /**
115 | * @}
116 | */
117 |
118 | /**
119 | * @}
120 | */
121 | #endif /* AES */
122 |
123 | /**
124 | * @}
125 | */
126 |
127 | #ifdef __cplusplus
128 | }
129 | #endif
130 |
131 | #endif /* STM32G0xx_HAL_CRYP_EX_H */
132 |
133 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
134 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_flash_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of FLASH HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_FLASH_EX_H
22 | #define STM32G0xx_HAL_FLASH_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G0xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup FLASHEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
42 | * @{
43 | */
44 | /** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check
45 | * @{
46 | */
47 | #define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */
48 | #define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */
49 | /**
50 | * @}
51 | */
52 | /**
53 | * @}
54 | */
55 |
56 | /* Exported macro ------------------------------------------------------------*/
57 | /* Exported functions --------------------------------------------------------*/
58 | /** @addtogroup FLASHEx_Exported_Functions
59 | * @{
60 | */
61 |
62 | /* Extended Program operation functions *************************************/
63 | /** @addtogroup FLASHEx_Exported_Functions_Group1
64 | * @{
65 | */
66 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
67 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
68 | void HAL_FLASHEx_EnableDebugger(void);
69 | void HAL_FLASHEx_DisableDebugger(void);
70 | uint32_t HAL_FLASHEx_FlashEmptyCheck(void);
71 | void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
72 | #if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
73 | void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks);
74 | #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */
75 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
76 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
77 | /**
78 | * @}
79 | */
80 |
81 | /**
82 | * @}
83 | */
84 |
85 | /* Private macros ------------------------------------------------------------*/
86 | /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
87 | * @{
88 | */
89 | #define FLASH_PCROP_GRANULARITY_OFFSET 9u /*!< FLASH Code Readout Protection granularity offset */
90 | #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 512 Bytes */
91 | /**
92 | * @}
93 | */
94 |
95 |
96 | /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
97 | * @{
98 | */
99 | #define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
100 | void FLASH_PageErase(uint32_t Banks, uint32_t Page);
101 | /**
102 | * @}
103 | */
104 |
105 | /**
106 | * @}
107 | */
108 |
109 | /**
110 | * @}
111 | */
112 |
113 | #ifdef __cplusplus
114 | }
115 | #endif
116 |
117 | #endif /* STM32G0xx_HAL_FLASH_EX_H */
118 |
119 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
120 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pcd_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_pcd_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of PCD HAL Extension module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_PCD_EX_H
22 | #define STM32G0xx_HAL_PCD_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | #if defined (USB_DRD_FS)
32 | /** @addtogroup STM32G0xx_HAL_Driver
33 | * @{
34 | */
35 |
36 | /** @addtogroup PCDEx
37 | * @{
38 | */
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /* Exported macros -----------------------------------------------------------*/
42 | /* Exported functions --------------------------------------------------------*/
43 | /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
44 | * @{
45 | */
46 | /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
47 | * @{
48 | */
49 |
50 |
51 |
52 | HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
53 | uint16_t ep_kind, uint32_t pmaadress);
54 |
55 |
56 | HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
57 | HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
58 |
59 |
60 | HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
61 | HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
62 | void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
63 |
64 | void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
65 | void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /**
76 | * @}
77 | */
78 |
79 | /**
80 | * @}
81 | */
82 | #endif /* defined (USB_DRD_FS) */
83 |
84 | #ifdef __cplusplus
85 | }
86 | #endif
87 |
88 |
89 | #endif /* STM32G0xx_HAL_PCD_EX_H */
90 |
91 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
92 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smbus_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_smbus_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of SMBUS HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_SMBUS_EX_H
22 | #define STM32G0xx_HAL_SMBUS_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G0xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup SMBUSEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 |
41 | /* Exported constants --------------------------------------------------------*/
42 | /** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
43 | * @{
44 | */
45 |
46 | /** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
47 | * @{
48 | */
49 | #define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
50 | #define SMBUS_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9 */
51 | #define SMBUS_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */
52 | #define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
53 | #define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
54 | #define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
55 | #define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
56 | #define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
57 | #define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
58 | #if defined(SYSCFG_CFGR1_I2C3_FMP)
59 | #define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
60 | #else
61 | #define SMBUS_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
62 | #endif /* SYSCFG_CFGR1_I2C3_FMP */
63 | /**
64 | * @}
65 | */
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /* Exported macro ------------------------------------------------------------*/
72 | /** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
73 | * @{
74 | */
75 |
76 | /**
77 | * @}
78 | */
79 |
80 | /* Exported functions --------------------------------------------------------*/
81 | /** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
82 | * @{
83 | */
84 |
85 | /** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions
86 | * @{
87 | */
88 | void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
89 | void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
90 | /**
91 | * @}
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | /* Private constants ---------------------------------------------------------*/
99 | /** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
100 | * @{
101 | */
102 |
103 | /**
104 | * @}
105 | */
106 |
107 | /* Private macros ------------------------------------------------------------*/
108 | /** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
109 | * @{
110 | */
111 | #define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
112 | ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA9)) == SMBUS_FASTMODEPLUS_PA9) || \
113 | (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA10)) == SMBUS_FASTMODEPLUS_PA10) || \
114 | (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \
115 | (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \
116 | (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \
117 | (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \
118 | (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
119 | (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
120 | (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3)))
121 | /**
122 | * @}
123 | */
124 |
125 | /* Private Functions ---------------------------------------------------------*/
126 | /** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
127 | * @{
128 | */
129 | /* Private functions are defined in stm32g0xx_hal_smbus_ex.c file */
130 | /**
131 | * @}
132 | */
133 |
134 | /**
135 | * @}
136 | */
137 |
138 | /**
139 | * @}
140 | */
141 |
142 | #ifdef __cplusplus
143 | }
144 | #endif
145 |
146 | #endif /* STM32G0xx_HAL_SMBUS_EX_H */
147 |
148 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
149 |
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_spi_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of SPI HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G0xx_HAL_SPI_EX_H
22 | #define STM32G0xx_HAL_SPI_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g0xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G0xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup SPIEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /* Exported macros -----------------------------------------------------------*/
42 | /* Exported functions --------------------------------------------------------*/
43 | /** @addtogroup SPIEx_Exported_Functions
44 | * @{
45 | */
46 |
47 | /* Initialization and de-initialization functions ****************************/
48 | /* IO operation functions *****************************************************/
49 | /** @addtogroup SPIEx_Exported_Functions_Group1
50 | * @{
51 | */
52 | HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
53 | /**
54 | * @}
55 | */
56 |
57 | /**
58 | * @}
59 | */
60 |
61 | /**
62 | * @}
63 | */
64 |
65 | /**
66 | * @}
67 | */
68 |
69 | #ifdef __cplusplus
70 | }
71 | #endif
72 |
73 | #endif /* STM32G0xx_HAL_SPI_EX_H */
74 |
75 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
76 |
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_msp_template.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_msp_template.c
4 | * @author MCD Application Team
5 | * @brief HAL MSP module.
6 | * This file template is located in the HAL folder and should be copied
7 | * to the user folder.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © Copyright (c) 2018 STMicroelectronics.
12 | * All rights reserved.
13 | *
14 | * This software component is licensed by ST under BSD 3-Clause license,
15 | * the "License"; You may not use this file except in compliance with the
16 | * License. You may obtain a copy of the License at:
17 | * opensource.org/licenses/BSD-3-Clause
18 | *
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32g0xx_hal.h"
24 |
25 | /** @addtogroup STM32G0xx_HAL_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup HAL_MSP HAL MSP module driver
30 | * @brief HAL MSP module.
31 | * @{
32 | */
33 |
34 | /* Private typedef -----------------------------------------------------------*/
35 | /* Private define ------------------------------------------------------------*/
36 | /* Private macro -------------------------------------------------------------*/
37 | /* Private variables ---------------------------------------------------------*/
38 | /* Private function prototypes -----------------------------------------------*/
39 | /* Private functions ---------------------------------------------------------*/
40 |
41 | /** @defgroup HAL_MSP_Private_Functions
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief Initialize the Global MSP.
47 | * @retval None
48 | */
49 | void HAL_MspInit(void)
50 | {
51 | /* NOTE : This function is generated automatically by STM32CubeMX and eventually
52 | modified by the user
53 | */
54 | }
55 |
56 | /**
57 | * @brief DeInitialize the Global MSP.
58 | * @retval None
59 | */
60 | void HAL_MspDeInit(void)
61 | {
62 | /* NOTE : This function is generated automatically by STM32CubeMX and eventually
63 | modified by the user
64 | */
65 | }
66 |
67 | /**
68 | * @brief Initialize the PPP MSP.
69 | * @retval None
70 | */
71 | void HAL_PPP_MspInit(void)
72 | {
73 | /* NOTE : This function is generated automatically by STM32CubeMX and eventually
74 | modified by the user
75 | */
76 | }
77 |
78 | /**
79 | * @brief DeInitialize the PPP MSP.
80 | * @retval None
81 | */
82 | void HAL_PPP_MspDeInit(void)
83 | {
84 | /* NOTE : This function is generated automatically by STM32CubeMX and eventually
85 | modified by the user
86 | */
87 | }
88 |
89 | /**
90 | * @}
91 | */
92 |
93 | /**
94 | * @}
95 | */
96 |
97 | /**
98 | * @}
99 | */
100 |
101 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
102 |
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_smbus_ex.c
4 | * @author MCD Application Team
5 | * @brief SMBUS Extended HAL module driver.
6 | * This file provides firmware functions to manage the following
7 | * functionalities of SMBUS Extended peripheral:
8 | * + Extended features functions
9 | *
10 | @verbatim
11 | ==============================================================================
12 | ##### SMBUS peripheral Extended features #####
13 | ==============================================================================
14 |
15 | [..] Comparing to other previous devices, the SMBUS interface for STM32G0xx
16 | devices contains the following additional features
17 |
18 | (+) Disable or enable Fast Mode Plus
19 |
20 | ##### How to use this driver #####
21 | ==============================================================================
22 | (#) Configure the enable or disable of fast mode plus driving capability using the functions :
23 | (++) HAL_SMBUSEx_EnableFastModePlus()
24 | (++) HAL_SMBUSEx_DisableFastModePlus()
25 | @endverbatim
26 | ******************************************************************************
27 | * @attention
28 | *
29 | * © Copyright (c) 2018 STMicroelectronics.
30 | * All rights reserved.
31 | *
32 | * This software component is licensed by ST under BSD 3-Clause license,
33 | * the "License"; You may not use this file except in compliance with the
34 | * License. You may obtain a copy of the License at:
35 | * opensource.org/licenses/BSD-3-Clause
36 | *
37 | ******************************************************************************
38 | */
39 |
40 | /* Includes ------------------------------------------------------------------*/
41 | #include "stm32g0xx_hal.h"
42 |
43 | /** @addtogroup STM32G0xx_HAL_Driver
44 | * @{
45 | */
46 |
47 | /** @defgroup SMBUSEx SMBUSEx
48 | * @brief SMBUS Extended HAL module driver
49 | * @{
50 | */
51 |
52 | #ifdef HAL_SMBUS_MODULE_ENABLED
53 |
54 | /* Private typedef -----------------------------------------------------------*/
55 | /* Private define ------------------------------------------------------------*/
56 | /* Private macro -------------------------------------------------------------*/
57 | /* Private variables ---------------------------------------------------------*/
58 | /* Private function prototypes -----------------------------------------------*/
59 | /* Private functions ---------------------------------------------------------*/
60 |
61 | /** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
62 | * @{
63 | */
64 |
65 | /** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions
66 | * @brief Extended features functions
67 | *
68 | @verbatim
69 | ===============================================================================
70 | ##### Extended features functions #####
71 | ===============================================================================
72 | [..] This section provides functions allowing to:
73 |
74 | (+) Configure Fast Mode Plus
75 |
76 | @endverbatim
77 | * @{
78 | */
79 |
80 | /**
81 | * @brief Enable the SMBUS fast mode plus driving capability.
82 | * @param ConfigFastModePlus Selects the pin.
83 | * This parameter can be one of the @ref SMBUSEx_FastModePlus values
84 | * @note For I2C1, fast mode plus driving capability can be enabled on all selected
85 | * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
86 | * on each one of the following pins PB6, PB7, PB8 and PB9.
87 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
88 | * can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
89 | * @note For all I2C2 pins fast mode plus driving capability can be enabled
90 | * only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
91 | * @note For all I2C3 pins fast mode plus driving capability can be enabled
92 | * only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
93 | * @retval None
94 | */
95 | void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
96 | {
97 | /* Check the parameter */
98 | assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
99 |
100 | /* Enable SYSCFG clock */
101 | __HAL_RCC_SYSCFG_CLK_ENABLE();
102 |
103 | /* Enable fast mode plus driving capability for selected pin */
104 | SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
105 | }
106 |
107 | /**
108 | * @brief Disable the SMBUS fast mode plus driving capability.
109 | * @param ConfigFastModePlus Selects the pin.
110 | * This parameter can be one of the @ref SMBUSEx_FastModePlus values
111 | * @note For I2C1, fast mode plus driving capability can be disabled on all selected
112 | * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
113 | * on each one of the following pins PB6, PB7, PB8 and PB9.
114 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
115 | * can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
116 | * @note For all I2C2 pins fast mode plus driving capability can be disabled
117 | * only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
118 | * @note For all I2C3 pins fast mode plus driving capability can be disabled
119 | * only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
120 | * @retval None
121 | */
122 | void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
123 | {
124 | /* Check the parameter */
125 | assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
126 |
127 | /* Enable SYSCFG clock */
128 | __HAL_RCC_SYSCFG_CLK_ENABLE();
129 |
130 | /* Disable fast mode plus driving capability for selected pin */
131 | CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
132 | }
133 |
134 |
135 | /**
136 | * @}
137 | */
138 |
139 | /**
140 | * @}
141 | */
142 |
143 | #endif /* HAL_SMBUS_MODULE_ENABLED */
144 | /**
145 | * @}
146 | */
147 |
148 | /**
149 | * @}
150 | */
151 |
152 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
153 |
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_hal_spi_ex.c
4 | * @author MCD Application Team
5 | * @brief Extended SPI HAL module driver.
6 | * This file provides firmware functions to manage the following
7 | * SPI peripheral extended functionalities :
8 | * + IO operation functions
9 | *
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © Copyright (c) 2018 STMicroelectronics.
14 | * All rights reserved.
15 | *
16 | * This software component is licensed by ST under BSD 3-Clause license,
17 | * the "License"; You may not use this file except in compliance with the
18 | * License. You may obtain a copy of the License at:
19 | * opensource.org/licenses/BSD-3-Clause
20 | *
21 | ******************************************************************************
22 | */
23 |
24 | /* Includes ------------------------------------------------------------------*/
25 | #include "stm32g0xx_hal.h"
26 |
27 | /** @addtogroup STM32G0xx_HAL_Driver
28 | * @{
29 | */
30 |
31 | /** @defgroup SPIEx SPIEx
32 | * @brief SPI Extended HAL module driver
33 | * @{
34 | */
35 | #ifdef HAL_SPI_MODULE_ENABLED
36 |
37 | /* Private typedef -----------------------------------------------------------*/
38 | /* Private defines -----------------------------------------------------------*/
39 | /** @defgroup SPIEx_Private_Constants SPIEx Private Constants
40 | * @{
41 | */
42 | #define SPI_FIFO_SIZE 4UL
43 | /**
44 | * @}
45 | */
46 |
47 | /* Private macros ------------------------------------------------------------*/
48 | /* Private variables ---------------------------------------------------------*/
49 | /* Private function prototypes -----------------------------------------------*/
50 | /* Exported functions --------------------------------------------------------*/
51 |
52 | /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
53 | * @{
54 | */
55 |
56 | /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
57 | * @brief Data transfers functions
58 | *
59 | @verbatim
60 | ==============================================================================
61 | ##### IO operation functions #####
62 | ===============================================================================
63 | [..]
64 | This subsection provides a set of extended functions to manage the SPI
65 | data transfers.
66 |
67 | (#) Rx data flush function:
68 | (++) HAL_SPIEx_FlushRxFifo()
69 |
70 | @endverbatim
71 | * @{
72 | */
73 |
74 | /**
75 | * @brief Flush the RX fifo.
76 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains
77 | * the configuration information for the specified SPI module.
78 | * @retval HAL status
79 | */
80 | HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
81 | {
82 | __IO uint32_t tmpreg;
83 | uint8_t count = 0U;
84 | while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
85 | {
86 | count++;
87 | tmpreg = hspi->Instance->DR;
88 | UNUSED(tmpreg); /* To avoid GCC warning */
89 | if (count == SPI_FIFO_SIZE)
90 | {
91 | return HAL_TIMEOUT;
92 | }
93 | }
94 | return HAL_OK;
95 | }
96 |
97 | /**
98 | * @}
99 | */
100 |
101 | /**
102 | * @}
103 | */
104 |
105 | #endif /* HAL_SPI_MODULE_ENABLED */
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
116 |
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_alarm_template.c:
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_timebase_rtc_wakeup_template.c:
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c:
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/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crc.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_ll_crc.c
4 | * @author MCD Application Team
5 | * @brief CRC LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g0xx_ll_crc.h"
23 | #include "stm32g0xx_ll_bus.h"
24 |
25 | #ifdef USE_FULL_ASSERT
26 | #include "stm32_assert.h"
27 | #else
28 | #define assert_param(expr) ((void)0U)
29 | #endif /* USE_FULL_ASSERT */
30 |
31 | /** @addtogroup STM32G0xx_LL_Driver
32 | * @{
33 | */
34 |
35 | #if defined (CRC)
36 |
37 | /** @addtogroup CRC_LL
38 | * @{
39 | */
40 |
41 | /* Private types -------------------------------------------------------------*/
42 | /* Private variables ---------------------------------------------------------*/
43 | /* Private constants ---------------------------------------------------------*/
44 | /* Private macros ------------------------------------------------------------*/
45 | /* Private function prototypes -----------------------------------------------*/
46 |
47 | /* Exported functions --------------------------------------------------------*/
48 | /** @addtogroup CRC_LL_Exported_Functions
49 | * @{
50 | */
51 |
52 | /** @addtogroup CRC_LL_EF_Init
53 | * @{
54 | */
55 |
56 | /**
57 | * @brief De-initialize CRC registers (Registers restored to their default values).
58 | * @param CRCx CRC Instance
59 | * @retval An ErrorStatus enumeration value:
60 | * - SUCCESS: CRC registers are de-initialized
61 | * - ERROR: CRC registers are not de-initialized
62 | */
63 | ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
64 | {
65 | ErrorStatus status = SUCCESS;
66 |
67 | /* Check the parameters */
68 | assert_param(IS_CRC_ALL_INSTANCE(CRCx));
69 |
70 | if (CRCx == CRC)
71 | {
72 | /* Force CRC reset */
73 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
74 |
75 | /* Release CRC reset */
76 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
77 | }
78 | else
79 | {
80 | status = ERROR;
81 | }
82 |
83 | return (status);
84 | }
85 |
86 | /**
87 | * @}
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | #endif /* defined (CRC) */
99 |
100 | /**
101 | * @}
102 | */
103 |
104 | #endif /* USE_FULL_LL_DRIVER */
105 |
106 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
107 |
108 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crs.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_ll_crs.h
4 | * @author MCD Application Team
5 | * @brief CRS LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g0xx_ll_crs.h"
23 | #include "stm32g0xx_ll_bus.h"
24 |
25 | /** @addtogroup STM32G0xx_LL_Driver
26 | * @{
27 | */
28 |
29 | #if defined(CRS)
30 |
31 | /** @defgroup CRS_LL CRS
32 | * @{
33 | */
34 |
35 | /* Private types -------------------------------------------------------------*/
36 | /* Private variables ---------------------------------------------------------*/
37 | /* Private constants ---------------------------------------------------------*/
38 | /* Private macros ------------------------------------------------------------*/
39 | /* Private function prototypes -----------------------------------------------*/
40 |
41 | /* Exported functions --------------------------------------------------------*/
42 | /** @addtogroup CRS_LL_Exported_Functions
43 | * @{
44 | */
45 |
46 | /** @addtogroup CRS_LL_EF_Init
47 | * @{
48 | */
49 |
50 | /**
51 | * @brief De-Initializes CRS peripheral registers to their default reset values.
52 | * @retval An ErrorStatus enumeration value:
53 | * - SUCCESS: CRS registers are de-initialized
54 | * - ERROR: not applicable
55 | */
56 | ErrorStatus LL_CRS_DeInit(void)
57 | {
58 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
59 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
60 |
61 | return SUCCESS;
62 | }
63 |
64 |
65 |
66 | /**
67 | * @}
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /**
75 | * @}
76 | */
77 |
78 | #endif /* defined(CRS) */
79 |
80 | /**
81 | * @}
82 | */
83 |
84 | #endif /* USE_FULL_LL_DRIVER */
85 |
86 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
87 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_pwr.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_ll_pwr.c
4 | * @author MCD Application Team
5 | * @brief PWR LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g0xx_ll_pwr.h"
23 | #include "stm32g0xx_ll_bus.h"
24 |
25 | /** @addtogroup STM32G0xx_LL_Driver
26 | * @{
27 | */
28 |
29 | #if defined(PWR)
30 |
31 | /** @defgroup PWR_LL PWR
32 | * @{
33 | */
34 |
35 | /* Private types -------------------------------------------------------------*/
36 | /* Private variables ---------------------------------------------------------*/
37 | /* Private constants ---------------------------------------------------------*/
38 | /* Private macros ------------------------------------------------------------*/
39 | /* Private function prototypes -----------------------------------------------*/
40 |
41 | /* Exported functions --------------------------------------------------------*/
42 | /** @addtogroup PWR_LL_Exported_Functions
43 | * @{
44 | */
45 |
46 | /** @addtogroup PWR_LL_EF_Init
47 | * @{
48 | */
49 |
50 | /**
51 | * @brief De-initialize the PWR registers to their default reset values.
52 | * @retval An ErrorStatus enumeration value:
53 | * - SUCCESS: PWR registers are de-initialized
54 | * - ERROR: not applicable
55 | */
56 | ErrorStatus LL_PWR_DeInit(void)
57 | {
58 | /* Force reset of PWR clock */
59 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
60 |
61 | /* Release reset of PWR clock */
62 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
63 |
64 | return SUCCESS;
65 | }
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /**
76 | * @}
77 | */
78 | #endif /* defined(PWR) */
79 | /**
80 | * @}
81 | */
82 |
83 | #endif /* USE_FULL_LL_DRIVER */
84 |
85 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
86 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_ll_rng.c
4 | * @author MCD Application Team
5 | * @brief RNG LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g0xx_ll_rng.h"
23 | #include "stm32g0xx_ll_bus.h"
24 |
25 | #ifdef USE_FULL_ASSERT
26 | #include "stm32_assert.h"
27 | #else
28 | #define assert_param(expr) ((void)0U)
29 | #endif /* USE_FULL_ASSERT */
30 |
31 | /** @addtogroup STM32G0xx_LL_Driver
32 | * @{
33 | */
34 |
35 | #if defined (RNG)
36 |
37 | /** @addtogroup RNG_LL
38 | * @{
39 | */
40 |
41 | /* Private types -------------------------------------------------------------*/
42 | /* Private variables ---------------------------------------------------------*/
43 | /* Private constants ---------------------------------------------------------*/
44 | /* Private macros ------------------------------------------------------------*/
45 | /** @defgroup RNG_LL_Private_Macros RNG Private Macros
46 | * @{
47 | */
48 | #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
49 | ((__MODE__) == LL_RNG_CED_DISABLE))
50 |
51 | /**
52 | * @}
53 | */
54 | /* Private function prototypes -----------------------------------------------*/
55 |
56 | /* Exported functions --------------------------------------------------------*/
57 | /** @addtogroup RNG_LL_Exported_Functions
58 | * @{
59 | */
60 |
61 | /** @addtogroup RNG_LL_EF_Init
62 | * @{
63 | */
64 |
65 | /**
66 | * @brief De-initialize RNG registers (Registers restored to their default values).
67 | * @param RNGx RNG Instance
68 | * @retval An ErrorStatus enumeration value:
69 | * - SUCCESS: RNG registers are de-initialized
70 | * - ERROR: not applicable
71 | */
72 | ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
73 | {
74 | /* Check the parameters */
75 | assert_param(IS_RNG_ALL_INSTANCE(RNGx));
76 | /* Enable RNG reset state */
77 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG);
78 |
79 | /* Release RNG from reset state */
80 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG);
81 | return (SUCCESS);
82 | }
83 |
84 | /**
85 | * @brief Initialize RNG registers according to the specified parameters in RNG_InitStruct.
86 | * @param RNGx RNG Instance
87 | * @param RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure
88 | * that contains the configuration information for the specified RNG peripheral.
89 | * @retval An ErrorStatus enumeration value:
90 | * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
91 | * - ERROR: not applicable
92 | */
93 | ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
94 | {
95 | /* Check the parameters */
96 | assert_param(IS_RNG_ALL_INSTANCE(RNGx));
97 | assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
98 |
99 | /* Clock Error Detection configuration */
100 | MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection);
101 |
102 | return (SUCCESS);
103 | }
104 |
105 | /**
106 | * @brief Set each @ref LL_RNG_InitTypeDef field to default value.
107 | * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure
108 | * whose fields will be set to default values.
109 | * @retval None
110 | */
111 | void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
112 | {
113 | /* Set RNG_InitStruct fields to default values */
114 | RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
115 |
116 | }
117 | /**
118 | * @}
119 | */
120 |
121 | /**
122 | * @}
123 | */
124 |
125 | /**
126 | * @}
127 | */
128 |
129 | #endif /* RNG */
130 |
131 | /**
132 | * @}
133 | */
134 |
135 | #endif /* USE_FULL_LL_DRIVER */
136 |
137 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
138 |
139 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g0xx_ll_ucpd.c
4 | * @author MCD Application Team
5 | * @brief UCPD LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g0xx_ll_ucpd.h"
23 | #include "stm32g0xx_ll_bus.h"
24 | #include "stm32g0xx_ll_rcc.h"
25 |
26 | #ifdef USE_FULL_ASSERT
27 | #include "stm32_assert.h"
28 | #else
29 | #define assert_param(expr) ((void)0U)
30 | #endif
31 |
32 | /** @addtogroup STM32G0xx_LL_Driver
33 | * @{
34 | */
35 | #if defined (UCPD1) || defined (UCPD2)
36 | /** @addtogroup UCPD_LL
37 | * @{
38 | */
39 |
40 | /* Private types -------------------------------------------------------------*/
41 | /* Private variables ---------------------------------------------------------*/
42 |
43 | /* Private constants ---------------------------------------------------------*/
44 | /** @defgroup UCPD_LL_Private_Constants UCPD Private Constants
45 | * @{
46 | */
47 |
48 | /**
49 | * @}
50 | */
51 |
52 | /* Private macros ------------------------------------------------------------*/
53 | /** @defgroup UCPD_LL_Private_Macros UCPD Private Macros
54 | * @{
55 | */
56 |
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /* Private function prototypes -----------------------------------------------*/
63 |
64 | /* Exported functions --------------------------------------------------------*/
65 | /** @addtogroup UCPD_LL_Exported_Functions
66 | * @{
67 | */
68 |
69 | /** @addtogroup UCPD_LL_EF_Init
70 | * @{
71 | */
72 |
73 | /**
74 | * @brief De-initialize the UCPD registers to their default reset values.
75 | * @param UCPDx ucpd Instance
76 | * @retval An ErrorStatus enumeration value:
77 | * - SUCCESS: ucpd registers are de-initialized
78 | * - ERROR: ucpd registers are not de-initialized
79 | */
80 | ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx)
81 | {
82 | ErrorStatus status = ERROR;
83 |
84 | /* Check the parameters */
85 | assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
86 |
87 | LL_UCPD_Disable(UCPDx);
88 |
89 | if (UCPD1 == UCPDx)
90 | {
91 | /* Force reset of ucpd clock */
92 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UCPD1);
93 |
94 | /* Release reset of ucpd clock */
95 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UCPD1);
96 |
97 | /* Disable ucpd clock */
98 | LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UCPD1);
99 |
100 | status = SUCCESS;
101 | }
102 | if (UCPD2 == UCPDx)
103 | {
104 | /* Force reset of ucpd clock */
105 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UCPD2);
106 |
107 | /* Release reset of ucpd clock */
108 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UCPD2);
109 |
110 | /* Disable ucpd clock */
111 | LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UCPD2);
112 |
113 | status = SUCCESS;
114 | }
115 |
116 | return status;
117 | }
118 |
119 | /**
120 | * @brief Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
121 | * @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled (ucpd_CR1_SPE bit =0),
122 | * UCPD peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
123 | * @param UCPDx UCPD Instance
124 | * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains
125 | * the configuration information for the UCPD peripheral.
126 | * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
127 | */
128 | ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
129 | {
130 | /* Check the ucpd Instance UCPDx*/
131 | assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
132 |
133 | if(UCPD1 == UCPDx)
134 | {
135 | LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UCPD1);
136 | }
137 |
138 | if(UCPD2 == UCPDx)
139 | {
140 | LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UCPD2);
141 | }
142 |
143 | LL_UCPD_Disable(UCPDx);
144 |
145 | /*---------------------------- UCPDx CFG1 Configuration ------------------------*/
146 | MODIFY_REG(UCPDx->CFG1,
147 | UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV,
148 | UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin << UCPD_CFG1_TRANSWIN_Pos) |
149 | (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv);
150 |
151 | return SUCCESS;
152 | }
153 |
154 | /**
155 | * @brief Set each @ref LL_UCPD_InitTypeDef field to default value.
156 | * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure
157 | * whose fields will be set to default values.
158 | * @retval None
159 | */
160 | void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct)
161 | {
162 | /* Set UCPD_InitStruct fields to default values */
163 | UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV2;
164 | UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */
165 | UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */
166 | UCPD_InitStruct->HbitClockDiv = 0x0D; /* Divide by 14 to produce HBITCLK */
167 | }
168 |
169 | /**
170 | * @}
171 | */
172 |
173 | /**
174 | * @}
175 | */
176 |
177 | /**
178 | * @}
179 | */
180 | #endif /* defined (UCPD1) || defined (UCPD2) */
181 | /**
182 | * @}
183 | */
184 |
185 | #endif /* USE_FULL_LL_DRIVER */
186 |
187 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
188 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/MDK-ARM/DebugConfig/STM32G071_Cortex_M0_RTT_STM32G071RBTx_1.0.0.dbgconf:
--------------------------------------------------------------------------------
1 | // File: STM32G0x1.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32G0x1 reference manual (RM0444)
4 |
5 | // <<< Use Configuration Wizard in Context Menu >>>
6 |
7 | // Debug MCU configuration register (DBGMCU_CR)
8 | // Reserved bits must be kept at reset value
9 | // DBG_STANDBY Debug Standby Mode
10 | // DBG_STOP Debug Stop Mode
11 | //
12 | DbgMCU_CR = 0x00000006;
13 |
14 | // Debug MCU APB freeze register 1 (DBGMCU_APB_FZ1)
15 | // Reserved bits must be kept at reset value
16 | // DBG_LPTIM1_STOP LPTIMER1 counter stopped when core is halted
17 | // DBG_LPTIM2_STOP LPTIMER2 counter stopped when core is halted
18 | // DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout is frozen
19 | // DBG_IWDG_STOP Debug independent watchdog stopped when core is halted
20 | // DBG_WWDG_STOP Debug window watchdog stopped when core is halted
21 | // DBG_RTC_STOP Debug RTC stopped when core is halted
22 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
23 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
24 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
25 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
26 | //
27 | DbgMCU_APB_Fz1 = 0x00000000;
28 |
29 | // Debug MCU APB freeze register 2 (DBGMCU_APB_FZ2)
30 | // Reserved bits must be kept at reset value
31 | // DBG_TIM17_STOP TIM17 counter stopped when core is halted
32 | // DBG_TIM16_STOP TIM16 counter stopped when core is halted
33 | // DBG_TIM15_STOP TIM15 counter stopped when core is halted
34 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted
35 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
36 | //
37 | DbgMCU_APB_Fz2 = 0x00000000;
38 |
39 | // <<< end of configuration section >>>
40 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/MDK-ARM/EventRecorderStub.scvd:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/MDK-ARM/JLinkSettings.ini:
--------------------------------------------------------------------------------
1 | [BREAKPOINTS]
2 | ForceImpTypeAny = 0
3 | ShowInfoWin = 1
4 | EnableFlashBP = 2
5 | BPDuringExecution = 0
6 | [CFI]
7 | CFISize = 0x00
8 | CFIAddr = 0x00
9 | [CPU]
10 | MonModeVTableAddr = 0xFFFFFFFF
11 | MonModeDebug = 0
12 | MaxNumAPs = 0
13 | LowPowerHandlingMode = 0
14 | OverrideMemMap = 0
15 | AllowSimulation = 1
16 | ScriptFile=""
17 | [FLASH]
18 | CacheExcludeSize = 0x00
19 | CacheExcludeAddr = 0x00
20 | MinNumBytesFlashDL = 0
21 | SkipProgOnCRCMatch = 1
22 | VerifyDownload = 1
23 | AllowCaching = 1
24 | EnableFlashDL = 2
25 | Override = 1
26 | Device="STM32G071RB"
27 | [GENERAL]
28 | WorkRAMSize = 0x8000
29 | WorkRAMAddr = 0x20000000
30 | RAMUsageLimit = 0x00
31 | [SWO]
32 | SWOLogFile=""
33 | [MEM]
34 | RdOverrideOrMask = 0x00
35 | RdOverrideAndMask = 0xFFFFFFFF
36 | RdOverrideAddr = 0xFFFFFFFF
37 | WrOverrideOrMask = 0x00
38 | WrOverrideAndMask = 0xFFFFFFFF
39 | WrOverrideAddr = 0xFFFFFFFF
40 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/MDK-ARM/RTE/_STM32G071_Cortex_M0_RTT/RTE_Components.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * Auto generated Run-Time-Environment Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'STM32G071_Cortex_M0_RTT'
7 | * Target: 'STM32G071_Cortex_M0_RTT'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32g0xx.h"
18 |
19 |
20 |
21 | #endif /* RTE_COMPONENTS_H */
22 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/SEGGER/CRC16.c:
--------------------------------------------------------------------------------
1 | static const unsigned char aucCRCHi[] = {
2 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
3 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
4 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
5 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
6 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
7 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
8 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
9 | 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
10 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
11 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
12 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
13 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
14 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
15 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
16 | 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
17 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
18 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
19 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
20 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
21 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
22 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
23 | 0x00, 0xC1, 0x81, 0x40
24 | };
25 |
26 | static const unsigned char aucCRCLo[] = {
27 | 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
28 | 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
29 | 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
30 | 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
31 | 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
32 | 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
33 | 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
34 | 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
35 | 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
36 | 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
37 | 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
38 | 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
39 | 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
40 | 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
41 | 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
42 | 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
43 | 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
44 | 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
45 | 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
46 | 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
47 | 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
48 | 0x41, 0x81, 0x80, 0x40
49 | };
50 |
51 | unsigned short usMBCRC16(unsigned char * pucFrame, unsigned short usLen)
52 | {
53 | unsigned char ucCRCHi = 0xFF;
54 | unsigned char ucCRCLo = 0xFF;
55 | int iIndex;
56 |
57 | while (usLen--)
58 | {
59 | iIndex = ucCRCLo ^ *(pucFrame++);
60 | ucCRCLo = (unsigned char)(ucCRCHi ^ aucCRCHi[iIndex]);
61 | ucCRCHi = aucCRCLo[iIndex];
62 | }
63 | return (unsigned short)(ucCRCHi << 8 | ucCRCLo);
64 | }
65 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/SEGGER/CRC16.h:
--------------------------------------------------------------------------------
1 |
2 | extern unsigned short usMBCRC16(unsigned char * pucFrame, unsigned short usLen);
3 |
4 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/KeilMDK_NUCLEOG071RB/STM32G071RB_Cortex_M0.ioc:
--------------------------------------------------------------------------------
1 | #MicroXplorer Configuration settings - do not modify
2 | File.Version=6
3 | GPIO.groupedBy=
4 | KeepUserPlacement=false
5 | Mcu.Family=STM32G0
6 | Mcu.IP0=NVIC
7 | Mcu.IP1=RCC
8 | Mcu.IP2=SYS
9 | Mcu.IP3=TIM1
10 | Mcu.IPNb=4
11 | Mcu.Name=STM32G071R(6-8-B)Tx
12 | Mcu.Package=LQFP64
13 | Mcu.Pin0=PA13
14 | Mcu.Pin1=PA14-BOOT0
15 | Mcu.Pin2=VP_SYS_VS_Systick
16 | Mcu.Pin3=VP_SYS_VS_DBSignals
17 | Mcu.Pin4=VP_TIM1_VS_ClockSourceINT
18 | Mcu.PinsNb=5
19 | Mcu.ThirdPartyNb=0
20 | Mcu.UserConstants=
21 | Mcu.UserName=STM32G071RBTx
22 | MxCube.Version=6.3.0
23 | MxDb.Version=DB.6.0.30
24 | NVIC.ForceEnableDMAVector=true
25 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
26 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
27 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
28 | NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false
29 | NVIC.SysTick_IRQn=true\:3\:0\:false\:false\:true\:false\:true
30 | NVIC.TIM1_BRK_UP_TRG_COM_IRQn=true\:0\:0\:false\:false\:true\:true\:true
31 | PA13.Mode=Serial_Wire
32 | PA13.Signal=SYS_SWDIO
33 | PA14-BOOT0.Mode=Serial_Wire
34 | PA14-BOOT0.Signal=SYS_SWCLK
35 | PinOutPanel.RotationAngle=0
36 | ProjectManager.AskForMigrate=true
37 | ProjectManager.BackupPrevious=false
38 | ProjectManager.CompilerOptimize=6
39 | ProjectManager.ComputerToolchain=false
40 | ProjectManager.CoupleFile=false
41 | ProjectManager.CustomerFirmwarePackage=
42 | ProjectManager.DefaultFWLocation=true
43 | ProjectManager.DeletePrevious=true
44 | ProjectManager.DeviceId=STM32G071RBTx
45 | ProjectManager.FirmwarePackage=STM32Cube FW_G0 V1.5.0
46 | ProjectManager.FreePins=false
47 | ProjectManager.HalAssertFull=false
48 | ProjectManager.HeapSize=0x200
49 | ProjectManager.KeepUserCode=true
50 | ProjectManager.LastFirmware=true
51 | ProjectManager.LibraryCopy=0
52 | ProjectManager.MainLocation=Core/Src
53 | ProjectManager.NoMain=false
54 | ProjectManager.PreviousToolchain=
55 | ProjectManager.ProjectBuild=false
56 | ProjectManager.ProjectFileName=STM32G071_Cortex_M0_RTT.ioc
57 | ProjectManager.ProjectName=STM32G071_Cortex_M0_RTT
58 | ProjectManager.RegisterCallBack=
59 | ProjectManager.StackSize=0x400
60 | ProjectManager.TargetToolchain=MDK-ARM V5.32
61 | ProjectManager.ToolChainLocation=
62 | ProjectManager.UnderRoot=false
63 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_TIM1_Init-TIM1-false-HAL-true
64 | RCC.ADCFreq_Value=64000000
65 | RCC.AHBFreq_Value=64000000
66 | RCC.APBFreq_Value=64000000
67 | RCC.APBTimFreq_Value=64000000
68 | RCC.CECFreq_Value=32786.88524590164
69 | RCC.CortexFreq_Value=64000000
70 | RCC.EXTERNAL_CLOCK_VALUE=48000
71 | RCC.FCLKCortexFreq_Value=64000000
72 | RCC.FamilyName=M
73 | RCC.HCLKFreq_Value=64000000
74 | RCC.HSE_VALUE=8000000
75 | RCC.HSI_VALUE=16000000
76 | RCC.I2C1Freq_Value=64000000
77 | RCC.I2S1Freq_Value=64000000
78 | RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CECFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2S1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIM15Freq_Value,TIM1Freq_Value,USART1Freq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
79 | RCC.LPTIM1Freq_Value=64000000
80 | RCC.LPTIM2Freq_Value=64000000
81 | RCC.LPUART1Freq_Value=64000000
82 | RCC.LSCOPinFreq_Value=32000
83 | RCC.LSE_VALUE=32768
84 | RCC.LSI_VALUE=32000
85 | RCC.MCO1PinFreq_Value=64000000
86 | RCC.PLLPoutputFreq_Value=64000000
87 | RCC.PLLQoutputFreq_Value=64000000
88 | RCC.PLLRCLKFreq_Value=64000000
89 | RCC.PWRFreq_Value=64000000
90 | RCC.SYSCLKFreq_VALUE=64000000
91 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
92 | RCC.TIM15Freq_Value=64000000
93 | RCC.TIM1Freq_Value=64000000
94 | RCC.USART1Freq_Value=64000000
95 | RCC.USART2Freq_Value=64000000
96 | RCC.VCOInputFreq_Value=16000000
97 | RCC.VCOOutputFreq_Value=128000000
98 | TIM1.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
99 | TIM1.IPParameters=Period,AutoReloadPreload
100 | TIM1.Period=6400-1
101 | VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals
102 | VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals
103 | VP_SYS_VS_Systick.Mode=SysTick
104 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick
105 | VP_TIM1_VS_ClockSourceINT.Mode=Internal
106 | VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
107 | board=custom
108 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/SimulinkHostModel/SimCoJLinkExample_G071.slx:
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https://raw.githubusercontent.com/jiafan1949/SimCoJLink/62fcea8b79075927edc732b7662d8b72725e89fb/SimCoJLink_Example/NUM1_NUCLEO_G071RB_Cortex_M0/SimulinkHostModel/SimCoJLinkExample_G071.slx
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/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Core/Inc/BspUtils.h:
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1 | #include "stm32g4xx_hal.h"
2 | #include "stm32g4xx_ll_cordic.h"
3 | #include "arm_math.h"
4 |
5 | extern void UtilsCordicSinCos(float in, float *sin, float *cos);
6 |
7 | extern void UtilsCordicAtan2(float in_x, float in_y, float *out);
8 |
9 | extern void UtilsCordicModulus(float in_x, float in_y, float *out);
10 |
11 | extern void UtilsCordicExp(float in, float *out);
12 |
13 | extern void UtilsCordicNegExp(float in, float *out);
14 |
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/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Core/Inc/bsp.h:
--------------------------------------------------------------------------------
1 | #include "stm32g4xx_hal.h"
2 |
3 | #define PI_2 6.2832F
4 |
5 | #define PC10_SET HAL_GPIO_WritePin(GPIOC, GPIO_PIN_10, GPIO_PIN_SET)
6 | #define PC10_RESET HAL_GPIO_WritePin(GPIOC, GPIO_PIN_10, GPIO_PIN_RESET)
7 |
8 | #define PC11_SET HAL_GPIO_WritePin(GPIOC, GPIO_PIN_11, GPIO_PIN_SET)
9 | #define PC11_RESET HAL_GPIO_WritePin(GPIOC, GPIO_PIN_11, GPIO_PIN_RESET)
10 |
11 | #define PC12_SET HAL_GPIO_WritePin(GPIOC, GPIO_PIN_12, GPIO_PIN_SET)
12 | #define PC12_RESET HAL_GPIO_WritePin(GPIOC, GPIO_PIN_12, GPIO_PIN_RESET)
13 |
14 | #define PD2_SET HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_SET)
15 | #define PD2_RESET HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_RESET)
16 |
17 | typedef enum
18 | {
19 | NONE_ERR,
20 | LV_ERR,
21 | OV_ERR,
22 | OC_ERR
23 | } enMcErr;
24 |
25 | typedef enum
26 | {
27 | MC_RDY,
28 | MC_STAT,
29 | MC_RUN,
30 | MC_STOP,
31 | MC_ERR
32 | } enMcState;
33 |
34 | typedef enum
35 | {
36 | STAT_CMD,
37 | STOP_CMD
38 | } enMcCMD;
39 |
40 | typedef struct
41 | {
42 | enMcCMD cmd;
43 | float refFreq;
44 | float refIq;
45 | float refRPM;
46 | float refPos;
47 | } stMcCMD;
48 |
49 |
50 | extern void StartPWM(void);
51 | extern void BspCordicInit(void);
52 | extern void BspInit(void);
53 |
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/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Core/Inc/main.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file : main.h
5 | * @brief : Header for main.c file.
6 | * This file contains the common defines of the application.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2020 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __MAIN_H
24 | #define __MAIN_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32g4xx_hal.h"
32 |
33 | /* Private includes ----------------------------------------------------------*/
34 | /* USER CODE BEGIN Includes */
35 |
36 | /* USER CODE END Includes */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* USER CODE BEGIN ET */
40 |
41 | /* USER CODE END ET */
42 |
43 | /* Exported constants --------------------------------------------------------*/
44 | /* USER CODE BEGIN EC */
45 |
46 | /* USER CODE END EC */
47 |
48 | /* Exported macro ------------------------------------------------------------*/
49 | /* USER CODE BEGIN EM */
50 |
51 | /* USER CODE END EM */
52 |
53 | /* Exported functions prototypes ---------------------------------------------*/
54 | void Error_Handler(void);
55 |
56 | /* USER CODE BEGIN EFP */
57 |
58 | /* USER CODE END EFP */
59 |
60 | /* Private defines -----------------------------------------------------------*/
61 | /* USER CODE BEGIN Private defines */
62 |
63 | /* USER CODE END Private defines */
64 |
65 | #ifdef __cplusplus
66 | }
67 | #endif
68 |
69 | #endif /* __MAIN_H */
70 |
71 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
72 |
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/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Core/Inc/stm32g4xx_it.h:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32g4xx_it.h
5 | * @brief This file contains the headers of the interrupt handlers.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Define to prevent recursive inclusion -------------------------------------*/
22 | #ifndef __STM32G4xx_IT_H
23 | #define __STM32G4xx_IT_H
24 |
25 | #ifdef __cplusplus
26 | extern "C" {
27 | #endif
28 |
29 | /* Private includes ----------------------------------------------------------*/
30 | /* USER CODE BEGIN Includes */
31 |
32 | /* USER CODE END Includes */
33 |
34 | /* Exported types ------------------------------------------------------------*/
35 | /* USER CODE BEGIN ET */
36 |
37 | /* USER CODE END ET */
38 |
39 | /* Exported constants --------------------------------------------------------*/
40 | /* USER CODE BEGIN EC */
41 |
42 | /* USER CODE END EC */
43 |
44 | /* Exported macro ------------------------------------------------------------*/
45 | /* USER CODE BEGIN EM */
46 |
47 | /* USER CODE END EM */
48 |
49 | /* Exported functions prototypes ---------------------------------------------*/
50 | void NMI_Handler(void);
51 | void HardFault_Handler(void);
52 | void MemManage_Handler(void);
53 | void BusFault_Handler(void);
54 | void UsageFault_Handler(void);
55 | void SVC_Handler(void);
56 | void DebugMon_Handler(void);
57 | void PendSV_Handler(void);
58 | void SysTick_Handler(void);
59 | void TIM1_UP_TIM16_IRQHandler(void);
60 | /* USER CODE BEGIN EFP */
61 |
62 | /* USER CODE END EFP */
63 |
64 | #ifdef __cplusplus
65 | }
66 | #endif
67 |
68 | #endif /* __STM32G4xx_IT_H */
69 |
70 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
71 |
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/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Core/Src/BspUtils.c:
--------------------------------------------------------------------------------
1 | #include "BspUtils.h"
2 | #include "bsp.h"
3 | #include "stm32g4xx_ll_bus.h"
4 |
5 | float sin_test, cos_test;
6 |
7 | void UtilsCordicSinCos(float in, float *sin, float *cos)
8 | {
9 | q31_t in_q31, sin_q31, cos_q31;
10 | // LL_CORDIC_DeInit(CORDIC);
11 | RCC->AHB1RSTR |= 0x00000008;
12 | RCC->AHB1RSTR &= 0xFFFFFFF7;
13 | /* LL_CORDIC_Config(CORDIC, LL_CORDIC_FUNCTION_COSINE,
14 | LL_CORDIC_PRECISION_6CYCLES,
15 | LL_CORDIC_SCALE_0,
16 | LL_CORDIC_NBWRITE_1,
17 | LL_CORDIC_NBREAD_2,
18 | LL_CORDIC_INSIZE_32BITS,
19 | LL_CORDIC_OUTSIZE_32BITS);
20 | */
21 | CORDIC->CSR = 0x00080060;
22 | float temp = in / PI;
23 | // arm_float_to_q31( &temp, &in_q31, 1);
24 | in_q31 = temp * 2147483648.0f;
25 | LL_CORDIC_WriteData(CORDIC, in_q31);
26 | cos_q31 = (int32_t)LL_CORDIC_ReadData(CORDIC);
27 | sin_q31 = (int32_t)LL_CORDIC_ReadData(CORDIC);
28 | // arm_q31_to_float( &cos_q31, cos, 1);
29 | // arm_q31_to_float( &sin_q31, sin, 1);
30 | *cos = cos_q31 / 2147483648.0f;
31 | *sin = sin_q31 / 2147483648.0f;
32 | sin_test = *sin;
33 | cos_test = *cos;
34 | }
35 |
36 | void UtilsCordicAtan2(float in_x, float in_y, float *out)
37 | {
38 | q31_t in_x_q31, in_y_q31, out_q31;
39 | LL_CORDIC_DeInit(CORDIC);
40 | LL_CORDIC_Config(CORDIC, LL_CORDIC_FUNCTION_PHASE,
41 | LL_CORDIC_PRECISION_6CYCLES,
42 | LL_CORDIC_SCALE_0,
43 | LL_CORDIC_NBWRITE_2,
44 | LL_CORDIC_NBREAD_1,
45 | LL_CORDIC_INSIZE_32BITS,
46 | LL_CORDIC_OUTSIZE_32BITS);
47 |
48 | arm_float_to_q31( &in_x, &in_x_q31, 1);
49 | arm_float_to_q31( &in_y, &in_y_q31, 1);
50 | LL_CORDIC_WriteData(CORDIC, in_x_q31);
51 | LL_CORDIC_WriteData(CORDIC, in_y_q31);
52 | out_q31 = (int32_t)LL_CORDIC_ReadData(CORDIC);
53 | arm_q31_to_float( &out_q31, out, 1);
54 | }
55 |
56 |
57 | void UtilsCordicModulus(float in_x, float in_y, float *out)
58 | {
59 | q31_t in_x_q31, in_y_q31, out_q31;
60 | //LL_CORDIC_DeInit(CORDIC);
61 | RCC->AHB1RSTR |= 0x00000008;
62 | RCC->AHB1RSTR &= 0xFFFFFFF7;
63 | /* LL_CORDIC_Config(CORDIC, LL_CORDIC_FUNCTION_MODULUS,
64 | LL_CORDIC_PRECISION_6CYCLES,
65 | LL_CORDIC_SCALE_0,
66 | LL_CORDIC_NBWRITE_2,
67 | LL_CORDIC_NBREAD_1,
68 | LL_CORDIC_INSIZE_32BITS,
69 | LL_CORDIC_OUTSIZE_32BITS);
70 | */
71 | CORDIC->CSR = 0x00100063;
72 |
73 | in_x /= 20;
74 | in_y /= 20;
75 | in_x_q31 = in_x * 2147483648.0f;
76 | in_y_q31 = in_y * 2147483648.0f;
77 | LL_CORDIC_WriteData(CORDIC, in_x_q31);
78 | LL_CORDIC_WriteData(CORDIC, in_y_q31);
79 | out_q31 = (int32_t)LL_CORDIC_ReadData(CORDIC);
80 | *out = out_q31 / 2147483648.0f;
81 | *out *= 20;
82 | }
83 |
84 | void UtilsCordicExp(float in, float *out)
85 | {
86 | q31_t in_q31, sinh_q31, cosh_q31, exp_x_q31;
87 | LL_CORDIC_DeInit(CORDIC);
88 | LL_CORDIC_Config(CORDIC, LL_CORDIC_FUNCTION_HCOSINE,
89 | LL_CORDIC_PRECISION_6CYCLES,
90 | LL_CORDIC_SCALE_0,
91 | LL_CORDIC_NBWRITE_1,
92 | LL_CORDIC_NBREAD_2,
93 | LL_CORDIC_INSIZE_32BITS,
94 | LL_CORDIC_OUTSIZE_32BITS);
95 |
96 | arm_float_to_q31( &in, &in_q31, 1);
97 | LL_CORDIC_WriteData(CORDIC, in_q31);
98 | cosh_q31 = (int32_t)LL_CORDIC_ReadData(CORDIC);
99 | sinh_q31 = (int32_t)LL_CORDIC_ReadData(CORDIC);
100 | exp_x_q31 = cosh_q31 + sinh_q31;
101 | arm_q31_to_float( &exp_x_q31, out, 1);
102 | }
103 |
104 | void UtilsCordicNegExp(float in, float *out)
105 | {
106 | q31_t in_q31, sinh_q31, cosh_q31, exp_neg_x_q31;
107 | LL_CORDIC_DeInit(CORDIC);
108 | LL_CORDIC_Config(CORDIC, LL_CORDIC_FUNCTION_HCOSINE,
109 | LL_CORDIC_PRECISION_6CYCLES,
110 | LL_CORDIC_SCALE_0,
111 | LL_CORDIC_NBWRITE_1,
112 | LL_CORDIC_NBREAD_2,
113 | LL_CORDIC_INSIZE_32BITS,
114 | LL_CORDIC_OUTSIZE_32BITS);
115 |
116 | arm_float_to_q31( &in, &in_q31, 1);
117 | LL_CORDIC_WriteData(CORDIC, in_q31);
118 | cosh_q31 = (int32_t)LL_CORDIC_ReadData(CORDIC);
119 | sinh_q31 = (int32_t)LL_CORDIC_ReadData(CORDIC);
120 | exp_neg_x_q31 = cosh_q31 - sinh_q31;
121 | arm_q31_to_float( &exp_neg_x_q31, out, 1);
122 | }
123 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Core/Src/BspUtils_new.c:
--------------------------------------------------------------------------------
1 | #include "BspUtils.h"
2 |
3 | void UtilsCordicSinCos(float in, float *sin, float *cos)
4 | {
5 |
6 | }
7 |
8 | void UtilsCordicAtan2(float in_x, float in_y, float *out)
9 | {
10 |
11 | }
12 |
13 | void UtilsCordicModulus(float in_x, float in_y, float *out)
14 | {
15 |
16 | }
17 |
18 | void UtilsCordicExp(float in, float *out)
19 | {
20 |
21 | }
22 |
23 | void UtilsCordicNegExp(float in, float *out)
24 | {
25 |
26 | }
27 |
28 |
29 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Core/Src/bsp.c:
--------------------------------------------------------------------------------
1 | #include "bsp.h"
2 | #include "Subsystem.h"
3 | #include "SEGGER_RTT.h"
4 |
5 |
6 | static void StopPWM(void);
7 |
8 | static void UploadParameter(void);
9 |
10 | uint16_t Adc1ValueIN1, Adc1ValueIN6, Adc2ValueIN7;
11 | uint32_t Temperature, Vbus;
12 | float encoder_angle, encoder_angle_1;
13 | volatile enMcErr mc_err;
14 | enMcState mc_state;
15 | stMcCMD mc_cmd;
16 |
17 |
18 | float CmdFreq, CmdAmp;
19 |
20 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
21 | {
22 | Subsystem_step();
23 | UploadParameter();
24 | }
25 | /*
26 | * Function Describe : Deal with FOC algorithm.
27 | * exec period : 20kHz
28 | */
29 | void HAL_ADCEx_InjectedConvCpltCallback( ADC_HandleTypeDef *hadc)
30 | {
31 | extern ADC_HandleTypeDef hadc1, hadc2;
32 | extern TIM_HandleTypeDef htim1;
33 | extern TIM_HandleTypeDef htim2;
34 |
35 | if( hadc->Instance == hadc1.Instance)
36 | {
37 | // UploadParameter();
38 | }
39 | }
40 |
41 |
42 | /*
43 | * Function Describe : When over current, shutdown pwm output.
44 | *
45 | */
46 | void HAL_TIMEx_Break2Callback( TIM_HandleTypeDef * htim)
47 | {
48 | extern TIM_HandleTypeDef htim1;
49 | HAL_TIM_PWM_Stop( &htim1, TIM_CHANNEL_1);
50 | HAL_TIM_PWM_Stop( &htim1, TIM_CHANNEL_2);
51 | HAL_TIM_PWM_Stop( &htim1, TIM_CHANNEL_3);
52 | HAL_TIMEx_PWMN_Stop_IT( &htim1, TIM_CHANNEL_1);
53 | HAL_TIMEx_PWMN_Stop_IT( &htim1, TIM_CHANNEL_2);
54 | HAL_TIMEx_PWMN_Stop_IT( &htim1, TIM_CHANNEL_3);
55 |
56 | mc_err = OC_ERR;
57 | HAL_GPIO_WritePin( GPIOB, GPIO_PIN_2, GPIO_PIN_SET);
58 | }
59 |
60 | int32_t encoder_count;
61 | uint16_t encoder_dir;
62 | float z_count;
63 | // z signal angle: 2.337 rad.
64 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
65 | {
66 | extern TIM_HandleTypeDef htim2;
67 | if( GPIO_Pin == GPIO_PIN_10)
68 | {
69 | // encoder_dir = __HAL_TIM_IS_TIM_COUNTING_DOWN( &htim2);
70 | // encoder_count = __HAL_TIM_GET_COUNTER( &htim2) - 65536;
71 | // __HAL_TIM_SET_COUNTER( &htim2, 65536);
72 | encoder_angle = 0.5155366f;
73 | }
74 | }
75 |
76 | void BspCordicInit(void)
77 | {
78 |
79 | }
80 |
81 | void StopPWM(void)
82 | {
83 | extern TIM_HandleTypeDef htim1;
84 | HAL_TIM_PWM_Stop( &htim1, TIM_CHANNEL_1);
85 | HAL_TIM_PWM_Stop( &htim1, TIM_CHANNEL_2);
86 | HAL_TIM_PWM_Stop( &htim1, TIM_CHANNEL_3);
87 | HAL_TIMEx_PWMN_Stop_IT( &htim1, TIM_CHANNEL_1);
88 | HAL_TIMEx_PWMN_Stop_IT( &htim1, TIM_CHANNEL_2);
89 | HAL_TIMEx_PWMN_Stop_IT( &htim1, TIM_CHANNEL_3);
90 | }
91 |
92 | void StartPWM(void)
93 | {
94 | extern TIM_HandleTypeDef htim1;
95 | HAL_TIM_PWM_Start( &htim1, TIM_CHANNEL_1);
96 | HAL_TIM_PWM_Start( &htim1, TIM_CHANNEL_2);
97 | HAL_TIM_PWM_Start( &htim1, TIM_CHANNEL_3);
98 | HAL_TIMEx_PWMN_Start_IT( &htim1, TIM_CHANNEL_1);
99 | HAL_TIMEx_PWMN_Start_IT( &htim1, TIM_CHANNEL_2);
100 | HAL_TIMEx_PWMN_Start_IT( &htim1, TIM_CHANNEL_3);
101 | }
102 |
103 | void BspInit(void)
104 | {
105 | mc_cmd.cmd = STOP_CMD;
106 | mc_cmd.refFreq = 0.0f;
107 | mc_cmd.refIq = 0.0f;
108 | mc_cmd.refRPM = 0.0f;
109 | mc_cmd.refPos = 0.0f;
110 | mc_state = MC_RDY;
111 | mc_err = NONE_ERR;
112 | }
113 |
114 | float TransBuff[20];
115 | uint8_t CmdBuffer[100];
116 | float CmdType[20];
117 | int16_t AvailBytes, AvailReadBytes;
118 | uint32_t RecvCount;
119 | uint8_t vv_debug;
120 | float vv_debug_float;
121 | float KKK_Freq;
122 | void UploadParameter(void)
123 | {
124 | static uint16_t count;
125 | uint8_t TransHeader[] = { 'T','T',':'};
126 | uint8_t TransTerminator[] = {'E', 'T', '!'};
127 | static float kk_test = 0.0F;
128 | if(kk_test > 10.0F)
129 | kk_test = 0.0F;
130 | kk_test += 0.05F;
131 |
132 | TransBuff[0] = Observer.theta_e;
133 | TransBuff[1] = CmdType[0] * Observer.u_alpha;
134 | TransBuff[2] = CmdType[0] * Observer.u_beta;
135 | // TransBuff[3] = Observer.theta_e;
136 | // TransBuff[4] = Observer.u_alpha;
137 | // TransBuff[5] = Observer.u_beta;
138 | // TransBuff[6] = Observer.theta_e;
139 | // TransBuff[7] = Observer.u_alpha;
140 | // TransBuff[8] = Observer.u_beta;
141 | // TransBuff[9] = Observer.theta_e;
142 | // TransBuff[10] = Observer.u_alpha;
143 | // TransBuff[11] = Observer.u_beta;
144 | // TransBuff[12] = Observer.theta_e;
145 | // TransBuff[13] = Observer.u_alpha;
146 | // TransBuff[14] = Observer.u_beta;
147 | // TransBuff[15] = Observer.theta_e;
148 | // TransBuff[16] = Observer.u_alpha;
149 | // TransBuff[17] = Observer.u_beta;
150 | // TransBuff[18] = Observer.theta_e;
151 | // TransBuff[19] = Observer.u_alpha;
152 | // TransBuff[20] = Observer.u_beta;
153 |
154 | if( count == 0)
155 | {
156 | SEGGER_RTT_WriteNoLock(0, TransHeader, 3);
157 | SEGGER_RTT_WriteNoLock(0, TransBuff, 3*4);
158 | }
159 | else if( count == 999)
160 | {
161 | SEGGER_RTT_WriteNoLock(0, TransBuff, 3*4);
162 | SEGGER_RTT_WriteNoLock(0, TransTerminator, 3);
163 | }
164 | else
165 | {
166 | SEGGER_RTT_WriteNoLock(0, TransBuff, 3*4);
167 | }
168 |
169 | if( count == 999)
170 | {
171 | count = 0;
172 | }
173 | else
174 | {
175 | count++;
176 | }
177 | AvailBytes = SEGGER_RTT_GetAvailWriteSpace(0);
178 | AvailReadBytes = SEGGER_RTT_GetAvailReadSpace(0);
179 |
180 | if(AvailReadBytes > 25-1)
181 | {
182 | SEGGER_RTT_ReadNoLock(0, CmdBuffer, 25);
183 | static float * CmdTypePtr = (float*)(CmdBuffer + 3);
184 | RecvCount++;
185 | memcpy(CmdType, CmdBuffer+3, 20);
186 | KKK_Freq = CmdType[1];
187 | // vv_debug_float = CmdTypePtr[0];
188 | // a = *(float *)(CmdBuffer + 3);
189 | // b = *(float *)(CmdBuffer + 3) + 1;
190 | // c = *(CmdTypePtr+2);
191 | // d = *(CmdTypePtr+3);
192 | }
193 | }
194 |
195 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Core/Src/stm32g4xx_hal_msp.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * File Name : stm32g4xx_hal_msp.c
5 | * Description : This file provides code for the MSP Initialization
6 | * and de-Initialization codes.
7 | ******************************************************************************
8 | * @attention
9 | *
10 | * © Copyright (c) 2020 STMicroelectronics.
11 | * All rights reserved.
12 | *
13 | * This software component is licensed by ST under BSD 3-Clause license,
14 | * the "License"; You may not use this file except in compliance with the
15 | * License. You may obtain a copy of the License at:
16 | * opensource.org/licenses/BSD-3-Clause
17 | *
18 | ******************************************************************************
19 | */
20 | /* USER CODE END Header */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "main.h"
24 | /* USER CODE BEGIN Includes */
25 |
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN Define */
35 |
36 | /* USER CODE END Define */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN Macro */
40 |
41 | /* USER CODE END Macro */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* External functions --------------------------------------------------------*/
54 | /* USER CODE BEGIN ExternalFunctions */
55 |
56 | /* USER CODE END ExternalFunctions */
57 |
58 | /* USER CODE BEGIN 0 */
59 |
60 | /* USER CODE END 0 */
61 | /**
62 | * Initializes the Global MSP.
63 | */
64 | void HAL_MspInit(void)
65 | {
66 | /* USER CODE BEGIN MspInit 0 */
67 |
68 | /* USER CODE END MspInit 0 */
69 |
70 | __HAL_RCC_SYSCFG_CLK_ENABLE();
71 | __HAL_RCC_PWR_CLK_ENABLE();
72 |
73 | /* System interrupt init*/
74 |
75 | /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
76 | */
77 | HAL_PWREx_DisableUCPDDeadBattery();
78 |
79 | /* USER CODE BEGIN MspInit 1 */
80 |
81 | /* USER CODE END MspInit 1 */
82 | }
83 |
84 | /**
85 | * @brief TIM_Base MSP Initialization
86 | * This function configures the hardware resources used in this example
87 | * @param htim_base: TIM_Base handle pointer
88 | * @retval None
89 | */
90 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
91 | {
92 | if(htim_base->Instance==TIM1)
93 | {
94 | /* USER CODE BEGIN TIM1_MspInit 0 */
95 |
96 | /* USER CODE END TIM1_MspInit 0 */
97 | /* Peripheral clock enable */
98 | __HAL_RCC_TIM1_CLK_ENABLE();
99 | /* TIM1 interrupt Init */
100 | HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, 0, 0);
101 | HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
102 | /* USER CODE BEGIN TIM1_MspInit 1 */
103 |
104 | /* USER CODE END TIM1_MspInit 1 */
105 | }
106 |
107 | }
108 |
109 | /**
110 | * @brief TIM_Base MSP De-Initialization
111 | * This function freeze the hardware resources used in this example
112 | * @param htim_base: TIM_Base handle pointer
113 | * @retval None
114 | */
115 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
116 | {
117 | if(htim_base->Instance==TIM1)
118 | {
119 | /* USER CODE BEGIN TIM1_MspDeInit 0 */
120 |
121 | /* USER CODE END TIM1_MspDeInit 0 */
122 | /* Peripheral clock disable */
123 | __HAL_RCC_TIM1_CLK_DISABLE();
124 |
125 | /* TIM1 interrupt DeInit */
126 | HAL_NVIC_DisableIRQ(TIM1_UP_TIM16_IRQn);
127 | /* USER CODE BEGIN TIM1_MspDeInit 1 */
128 |
129 | /* USER CODE END TIM1_MspDeInit 1 */
130 | }
131 |
132 | }
133 |
134 | /* USER CODE BEGIN 1 */
135 |
136 | /* USER CODE END 1 */
137 |
138 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
139 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Core/Src/stm32g4xx_it.c:
--------------------------------------------------------------------------------
1 | /* USER CODE BEGIN Header */
2 | /**
3 | ******************************************************************************
4 | * @file stm32g4xx_it.c
5 | * @brief Interrupt Service Routines.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2020 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | /* USER CODE END Header */
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "main.h"
23 | #include "stm32g4xx_it.h"
24 | /* Private includes ----------------------------------------------------------*/
25 | /* USER CODE BEGIN Includes */
26 | /* USER CODE END Includes */
27 |
28 | /* Private typedef -----------------------------------------------------------*/
29 | /* USER CODE BEGIN TD */
30 |
31 | /* USER CODE END TD */
32 |
33 | /* Private define ------------------------------------------------------------*/
34 | /* USER CODE BEGIN PD */
35 |
36 | /* USER CODE END PD */
37 |
38 | /* Private macro -------------------------------------------------------------*/
39 | /* USER CODE BEGIN PM */
40 |
41 | /* USER CODE END PM */
42 |
43 | /* Private variables ---------------------------------------------------------*/
44 | /* USER CODE BEGIN PV */
45 |
46 | /* USER CODE END PV */
47 |
48 | /* Private function prototypes -----------------------------------------------*/
49 | /* USER CODE BEGIN PFP */
50 |
51 | /* USER CODE END PFP */
52 |
53 | /* Private user code ---------------------------------------------------------*/
54 | /* USER CODE BEGIN 0 */
55 |
56 | /* USER CODE END 0 */
57 |
58 | /* External variables --------------------------------------------------------*/
59 | extern TIM_HandleTypeDef htim1;
60 | /* USER CODE BEGIN EV */
61 |
62 | /* USER CODE END EV */
63 |
64 | /******************************************************************************/
65 | /* Cortex-M4 Processor Interruption and Exception Handlers */
66 | /******************************************************************************/
67 | /**
68 | * @brief This function handles Non maskable interrupt.
69 | */
70 | void NMI_Handler(void)
71 | {
72 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
73 |
74 | /* USER CODE END NonMaskableInt_IRQn 0 */
75 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
76 |
77 | /* USER CODE END NonMaskableInt_IRQn 1 */
78 | }
79 |
80 | /**
81 | * @brief This function handles Hard fault interrupt.
82 | */
83 | void HardFault_Handler(void)
84 | {
85 | /* USER CODE BEGIN HardFault_IRQn 0 */
86 |
87 | /* USER CODE END HardFault_IRQn 0 */
88 | while (1)
89 | {
90 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */
91 | /* USER CODE END W1_HardFault_IRQn 0 */
92 | }
93 | }
94 |
95 | /**
96 | * @brief This function handles Memory management fault.
97 | */
98 | void MemManage_Handler(void)
99 | {
100 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */
101 |
102 | /* USER CODE END MemoryManagement_IRQn 0 */
103 | while (1)
104 | {
105 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
106 | /* USER CODE END W1_MemoryManagement_IRQn 0 */
107 | }
108 | }
109 |
110 | /**
111 | * @brief This function handles Prefetch fault, memory access fault.
112 | */
113 | void BusFault_Handler(void)
114 | {
115 | /* USER CODE BEGIN BusFault_IRQn 0 */
116 |
117 | /* USER CODE END BusFault_IRQn 0 */
118 | while (1)
119 | {
120 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */
121 | /* USER CODE END W1_BusFault_IRQn 0 */
122 | }
123 | }
124 |
125 | /**
126 | * @brief This function handles Undefined instruction or illegal state.
127 | */
128 | void UsageFault_Handler(void)
129 | {
130 | /* USER CODE BEGIN UsageFault_IRQn 0 */
131 |
132 | /* USER CODE END UsageFault_IRQn 0 */
133 | while (1)
134 | {
135 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
136 | /* USER CODE END W1_UsageFault_IRQn 0 */
137 | }
138 | }
139 |
140 | /**
141 | * @brief This function handles System service call via SWI instruction.
142 | */
143 | void SVC_Handler(void)
144 | {
145 | /* USER CODE BEGIN SVCall_IRQn 0 */
146 |
147 | /* USER CODE END SVCall_IRQn 0 */
148 | /* USER CODE BEGIN SVCall_IRQn 1 */
149 |
150 | /* USER CODE END SVCall_IRQn 1 */
151 | }
152 |
153 | /**
154 | * @brief This function handles Debug monitor.
155 | */
156 | void DebugMon_Handler(void)
157 | {
158 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */
159 |
160 | /* USER CODE END DebugMonitor_IRQn 0 */
161 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */
162 |
163 | /* USER CODE END DebugMonitor_IRQn 1 */
164 | }
165 |
166 | /**
167 | * @brief This function handles Pendable request for system service.
168 | */
169 | void PendSV_Handler(void)
170 | {
171 | /* USER CODE BEGIN PendSV_IRQn 0 */
172 |
173 | /* USER CODE END PendSV_IRQn 0 */
174 | /* USER CODE BEGIN PendSV_IRQn 1 */
175 |
176 | /* USER CODE END PendSV_IRQn 1 */
177 | }
178 |
179 | /**
180 | * @brief This function handles System tick timer.
181 | */
182 | void SysTick_Handler(void)
183 | {
184 | /* USER CODE BEGIN SysTick_IRQn 0 */
185 |
186 | /* USER CODE END SysTick_IRQn 0 */
187 | HAL_IncTick();
188 | /* USER CODE BEGIN SysTick_IRQn 1 */
189 |
190 | /* USER CODE END SysTick_IRQn 1 */
191 | }
192 |
193 | /******************************************************************************/
194 | /* STM32G4xx Peripheral Interrupt Handlers */
195 | /* Add here the Interrupt Handlers for the used peripherals. */
196 | /* For the available peripheral interrupt handler names, */
197 | /* please refer to the startup file (startup_stm32g4xx.s). */
198 | /******************************************************************************/
199 |
200 | /**
201 | * @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
202 | */
203 | void TIM1_UP_TIM16_IRQHandler(void)
204 | {
205 | /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
206 |
207 | /* USER CODE END TIM1_UP_TIM16_IRQn 0 */
208 | HAL_TIM_IRQHandler(&htim1);
209 | /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
210 |
211 | /* USER CODE END TIM1_UP_TIM16_IRQn 1 */
212 | }
213 |
214 | /* USER CODE BEGIN 1 */
215 |
216 | /* USER CODE END 1 */
217 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
218 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32_assert_template.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32_assert.h
4 | * @author MCD Application Team
5 | * @brief STM32 assert template file.
6 | * This file should be copied to the application folder and renamed
7 | * to stm32_assert.h.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © Copyright (c) 2019 STMicroelectronics.
12 | * All rights reserved.
13 | *
14 | * This software component is licensed by ST under BSD 3-Clause license,
15 | * the "License"; You may not use this file except in compliance with the
16 | * License. You may obtain a copy of the License at:
17 | * opensource.org/licenses/BSD-3-Clause
18 | *
19 | ******************************************************************************
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef STM32_ASSERT_H
24 | #define STM32_ASSERT_H
25 |
26 | #ifdef __cplusplus
27 | extern "C" {
28 | #endif
29 |
30 | /* Exported types ------------------------------------------------------------*/
31 | /* Exported constants --------------------------------------------------------*/
32 | /* Includes ------------------------------------------------------------------*/
33 | /* Exported macro ------------------------------------------------------------*/
34 | #ifdef USE_FULL_ASSERT
35 | /**
36 | * @brief The assert_param macro is used for function's parameters check.
37 | * @param expr: If expr is false, it calls assert_failed function
38 | * which reports the name of the source file and the source
39 | * line number of the call that failed.
40 | * If expr is true, it returns no value.
41 | * @retval None
42 | */
43 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
44 | /* Exported functions ------------------------------------------------------- */
45 | void assert_failed(uint8_t *file, uint32_t line);
46 | #else
47 | #define assert_param(expr) ((void)0U)
48 | #endif /* USE_FULL_ASSERT */
49 |
50 | #ifdef __cplusplus
51 | }
52 | #endif
53 |
54 | #endif /* STM32_ASSERT_H */
55 |
56 |
57 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
58 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_crc_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of CRC HAL extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G4xx_HAL_CRC_EX_H
22 | #define STM32G4xx_HAL_CRC_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup CRCEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
42 | * @{
43 | */
44 |
45 | /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
46 | * @{
47 | */
48 | #define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
49 | #define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
50 | #define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
51 | #define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
52 | /**
53 | * @}
54 | */
55 |
56 | /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
57 | * @{
58 | */
59 | #define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
60 | #define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
61 | /**
62 | * @}
63 | */
64 |
65 | /**
66 | * @}
67 | */
68 |
69 | /* Exported macro ------------------------------------------------------------*/
70 | /** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
71 | * @{
72 | */
73 |
74 | /**
75 | * @brief Set CRC output reversal
76 | * @param __HANDLE__ CRC handle
77 | * @retval None
78 | */
79 | #define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
80 |
81 | /**
82 | * @brief Unset CRC output reversal
83 | * @param __HANDLE__ CRC handle
84 | * @retval None
85 | */
86 | #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
87 |
88 | /**
89 | * @brief Set CRC non-default polynomial
90 | * @param __HANDLE__ CRC handle
91 | * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
92 | * @retval None
93 | */
94 | #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
95 |
96 | /**
97 | * @}
98 | */
99 |
100 | /* Private macros --------------------------------------------------------*/
101 | /** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
102 | * @{
103 | */
104 |
105 | #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
106 | ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
107 | ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
108 | ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
109 |
110 | #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
111 | ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | /* Exported functions --------------------------------------------------------*/
118 |
119 | /** @addtogroup CRCEx_Exported_Functions
120 | * @{
121 | */
122 |
123 | /** @addtogroup CRCEx_Exported_Functions_Group1
124 | * @{
125 | */
126 | /* Initialization and de-initialization functions ****************************/
127 | HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
128 | HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
129 | HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
130 |
131 | /**
132 | * @}
133 | */
134 |
135 | /**
136 | * @}
137 | */
138 |
139 | /**
140 | * @}
141 | */
142 |
143 | /**
144 | * @}
145 | */
146 |
147 | #ifdef __cplusplus
148 | }
149 | #endif
150 |
151 | #endif /* STM32G4xx_HAL_CRC_EX_H */
152 |
153 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
154 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_cryp_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of CRYPEx HAL module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G4xx_HAL_CRYP_EX_H
22 | #define STM32G4xx_HAL_CRYP_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | #if defined(AES)
36 |
37 | /** @defgroup CRYPEx CRYPEx
38 | * @brief CRYP Extension HAL module driver.
39 | * @{
40 | */
41 |
42 | /* Exported types ------------------------------------------------------------*/
43 | /* Exported constants --------------------------------------------------------*/
44 | /* Private types -------------------------------------------------------------*/
45 | /** @defgroup CRYPEx_Private_Types CRYPEx Private Types
46 | * @{
47 | */
48 |
49 | /**
50 | * @}
51 | */
52 |
53 | /* Private variables ---------------------------------------------------------*/
54 | /** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
55 | * @{
56 | */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /* Private constants ---------------------------------------------------------*/
63 | /** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
64 | * @{
65 | */
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /* Private macros ------------------------------------------------------------*/
72 | /** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
73 | * @{
74 | */
75 |
76 | /**
77 | * @}
78 | */
79 |
80 | /* Private functions ---------------------------------------------------------*/
81 | /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
82 | * @{
83 | */
84 |
85 | /**
86 | * @}
87 | */
88 |
89 | /* Exported functions --------------------------------------------------------*/
90 | /** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
91 | * @{
92 | */
93 |
94 | /** @addtogroup CRYPEx_Exported_Functions_Group1
95 | * @{
96 | */
97 | HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
98 | HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
99 |
100 | /**
101 | * @}
102 | */
103 |
104 | /** @addtogroup CRYPEx_Exported_Functions_Group2
105 | * @{
106 | */
107 | void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
108 | void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
109 |
110 | /**
111 | * @}
112 | */
113 |
114 | /**
115 | * @}
116 | */
117 |
118 | /**
119 | * @}
120 | */
121 | #endif /* AES */
122 |
123 | /**
124 | * @}
125 | */
126 |
127 | #ifdef __cplusplus
128 | }
129 | #endif
130 |
131 | #endif /* STM32G4xx_HAL_CRYP_EX_H */
132 |
133 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
134 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_flash_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of FLASH HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © COPYRIGHT(c) 2019 STMicroelectronics
10 | *
11 | * This software component is licensed by ST under BSD 3-Clause license,
12 | * the "License"; You may not use this file except in compliance with the
13 | * License. You may obtain a copy of the License at:
14 | * opensource.org/licenses/BSD-3-Clause
15 | *
16 | ******************************************************************************
17 | */
18 |
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef STM32G4xx_HAL_FLASH_EX_H
21 | #define STM32G4xx_HAL_FLASH_EX_H
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "stm32g4xx_hal_def.h"
29 |
30 | /** @addtogroup STM32G4xx_HAL_Driver
31 | * @{
32 | */
33 |
34 | /** @addtogroup FLASHEx
35 | * @{
36 | */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 |
40 | /* Exported constants --------------------------------------------------------*/
41 |
42 | /* Exported macro ------------------------------------------------------------*/
43 |
44 | /* Exported functions --------------------------------------------------------*/
45 | /** @addtogroup FLASHEx_Exported_Functions
46 | * @{
47 | */
48 |
49 | /* Extended Program operation functions *************************************/
50 | /** @addtogroup FLASHEx_Exported_Functions_Group1
51 | * @{
52 | */
53 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
54 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
55 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
56 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
57 | HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
58 | void HAL_FLASHEx_EnableDebugger(void);
59 | void HAL_FLASHEx_DisableDebugger(void);
60 | /**
61 | * @}
62 | */
63 |
64 | /**
65 | * @}
66 | */
67 |
68 | /** @addtogroup FLASHEx_Private_Functions
69 | * @{
70 | */
71 | void FLASH_PageErase(uint32_t Page, uint32_t Banks);
72 | void FLASH_FlushCaches(void);
73 | /**
74 | * @}
75 | */
76 |
77 | /**
78 | * @}
79 | */
80 |
81 | /**
82 | * @}
83 | */
84 |
85 | #ifdef __cplusplus
86 | }
87 | #endif
88 |
89 | #endif /* STM32G4xx_HAL_FLASH_EX_H */
90 |
91 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
92 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_flash_ramfunc.h
4 | * @author MCD Application Team
5 | * @brief Header file of FLASH RAMFUNC driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © COPYRIGHT(c) 2019 STMicroelectronics
10 | *
11 | * This software component is licensed by ST under BSD 3-Clause license,
12 | * the "License"; You may not use this file except in compliance with the
13 | * License. You may obtain a copy of the License at:
14 | * opensource.org/licenses/BSD-3-Clause
15 | *
16 | ******************************************************************************
17 | */
18 |
19 | /* Define to prevent recursive inclusion -------------------------------------*/
20 | #ifndef STM32G4xx_FLASH_RAMFUNC_H
21 | #define STM32G4xx_FLASH_RAMFUNC_H
22 |
23 | #ifdef __cplusplus
24 | extern "C" {
25 | #endif
26 |
27 | /* Includes ------------------------------------------------------------------*/
28 | #include "stm32g4xx_hal_def.h"
29 |
30 | /** @addtogroup STM32G4xx_HAL_Driver
31 | * @{
32 | */
33 |
34 | /** @addtogroup FLASH_RAMFUNC
35 | * @{
36 | */
37 |
38 | /* Exported types ------------------------------------------------------------*/
39 | /* Exported macro ------------------------------------------------------------*/
40 | /* Exported functions --------------------------------------------------------*/
41 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions
42 | * @{
43 | */
44 |
45 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
46 | * @{
47 | */
48 | /* Peripheral Control functions ************************************************/
49 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
50 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
51 | #if defined (FLASH_OPTR_DBANK)
52 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
53 | #endif
54 | /**
55 | * @}
56 | */
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /**
67 | * @}
68 | */
69 |
70 | #ifdef __cplusplus
71 | }
72 | #endif
73 |
74 | #endif /* STM32G4xx_FLASH_RAMFUNC_H */
75 |
76 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
77 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_i2c_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of I2C HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G4xx_HAL_I2C_EX_H
22 | #define STM32G4xx_HAL_I2C_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup I2CEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
42 | * @{
43 | */
44 |
45 | /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
46 | * @{
47 | */
48 | #define I2C_ANALOGFILTER_ENABLE 0x00000000U
49 | #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
50 | /**
51 | * @}
52 | */
53 |
54 | /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
55 | * @{
56 | */
57 | #define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
58 | #define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
59 | #define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
60 | #define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
61 | #define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
62 | #define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
63 | #define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
64 | #define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
65 | #if defined(SYSCFG_CFGR1_I2C4_FMP)
66 | #define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
67 | #else
68 | #define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
69 | #endif
70 | /**
71 | * @}
72 | */
73 |
74 | /**
75 | * @}
76 | */
77 |
78 | /* Exported macro ------------------------------------------------------------*/
79 | /** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
80 | * @{
81 | */
82 |
83 | /**
84 | * @}
85 | */
86 |
87 | /* Exported functions --------------------------------------------------------*/
88 | /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
89 | * @{
90 | */
91 |
92 | /** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
93 | * @{
94 | */
95 | /* Peripheral Control functions ************************************************/
96 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
97 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
98 | /**
99 | * @}
100 | */
101 |
102 | /** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
103 | * @{
104 | */
105 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
106 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
107 | /**
108 | * @}
109 | */
110 |
111 | /** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
112 | * @{
113 | */
114 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
115 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
116 | /**
117 | * @}
118 | */
119 |
120 |
121 | /**
122 | * @}
123 | */
124 |
125 | /* Private constants ---------------------------------------------------------*/
126 | /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
127 | * @{
128 | */
129 |
130 | /**
131 | * @}
132 | */
133 |
134 | /* Private macros ------------------------------------------------------------*/
135 | /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
136 | * @{
137 | */
138 | #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
139 | ((FILTER) == I2C_ANALOGFILTER_DISABLE))
140 |
141 | #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
142 |
143 | #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
144 | ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
145 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
146 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
147 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
148 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
149 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
150 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
151 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
152 | /**
153 | * @}
154 | */
155 |
156 | /* Private Functions ---------------------------------------------------------*/
157 | /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
158 | * @{
159 | */
160 | /* Private functions are defined in stm32g4xx_hal_i2c_ex.c file */
161 | /**
162 | * @}
163 | */
164 |
165 | /**
166 | * @}
167 | */
168 |
169 | /**
170 | * @}
171 | */
172 |
173 | #ifdef __cplusplus
174 | }
175 | #endif
176 |
177 | #endif /* STM32G4xx_HAL_I2C_EX_H */
178 |
179 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
180 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_opamp_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of OPAMP HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G4xx_HAL_OPAMP_EX_H
22 | #define STM32G4xx_HAL_OPAMP_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup OPAMPEx OPAMPEx
36 | * @{
37 | */
38 | /* Exported types ------------------------------------------------------------*/
39 | /* Exported constants --------------------------------------------------------*/
40 | /* Exported macro ------------------------------------------------------------*/
41 | /* Exported functions --------------------------------------------------------*/
42 | /** @addtogroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
43 | * @{
44 | */
45 |
46 | /** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
47 | * @{
48 | */
49 |
50 | /* I/O operation functions *****************************************************/
51 |
52 | #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx)
53 | HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
54 | OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6);
55 | #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
56 | HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
57 | OPAMP_HandleTypeDef *hopamp3);
58 | #elif defined(STM32G491xx) || defined(STM32G4A1xx)
59 | HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
60 | OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6);
61 | #endif
62 |
63 | /**
64 | * @}
65 | */
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /**
76 | * @}
77 | */
78 |
79 |
80 | #ifdef __cplusplus
81 | }
82 | #endif
83 |
84 |
85 | #endif /* STM32G4xx_HAL_OPAMP_EX_H */
86 |
87 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
88 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_pcd_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of PCD HAL Extension module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G4xx_HAL_PCD_EX_H
22 | #define STM32G4xx_HAL_PCD_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g4xx_hal_def.h"
30 |
31 | #if defined (USB)
32 | /** @addtogroup STM32G4xx_HAL_Driver
33 | * @{
34 | */
35 |
36 | /** @addtogroup PCDEx
37 | * @{
38 | */
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /* Exported macros -----------------------------------------------------------*/
42 | /* Exported functions --------------------------------------------------------*/
43 | /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
44 | * @{
45 | */
46 | /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
47 | * @{
48 | */
49 |
50 |
51 |
52 | HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
53 | uint16_t ep_addr,
54 | uint16_t ep_kind,
55 | uint32_t pmaadress);
56 |
57 |
58 | HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
59 | HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
60 |
61 |
62 | HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
63 | HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
64 | void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
65 |
66 | void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
67 | void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /**
74 | * @}
75 | */
76 |
77 | /**
78 | * @}
79 | */
80 |
81 | /**
82 | * @}
83 | */
84 | #endif /* defined (USB) */
85 |
86 | #ifdef __cplusplus
87 | }
88 | #endif
89 |
90 |
91 | #endif /* STM32G4xx_HAL_PCD_EX_H */
92 |
93 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
94 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_sai_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of SAI HAL extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G4xx_HAL_SAI_EX_H
22 | #define STM32G4xx_HAL_SAI_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup SAIEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /** @defgroup SAIEx_Exported_Types SAIEx Exported Types
41 | * @{
42 | */
43 |
44 | /**
45 | * @brief PDM microphone delay structure definition
46 | */
47 | typedef struct
48 | {
49 | uint32_t MicPair; /*!< Specifies which pair of microphones is selected.
50 | This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
51 |
52 | uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone.
53 | This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
54 |
55 | uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone.
56 | This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
57 | } SAIEx_PdmMicDelayParamTypeDef;
58 |
59 | /**
60 | * @}
61 | */
62 |
63 | /* Exported constants --------------------------------------------------------*/
64 | /* Exported macros -----------------------------------------------------------*/
65 | /* Exported functions --------------------------------------------------------*/
66 | /** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
67 | * @{
68 | */
69 |
70 | /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
71 | * @{
72 | */
73 | HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
74 | /**
75 | * @}
76 | */
77 |
78 | /**
79 | * @}
80 | */
81 |
82 | /* Private macros ------------------------------------------------------------*/
83 | /** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
84 | * @{
85 | */
86 | #define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)
87 | /**
88 | * @}
89 | */
90 |
91 | /**
92 | * @}
93 | */
94 |
95 | /**
96 | * @}
97 | */
98 |
99 | #ifdef __cplusplus
100 | }
101 | #endif
102 |
103 | #endif /* STM32G4xx_HAL_SAI_EX_H */
104 |
105 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
106 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_spi_ex.h
4 | * @author MCD Application Team
5 | * @brief Header file of SPI HAL Extended module.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 |
20 | /* Define to prevent recursive inclusion -------------------------------------*/
21 | #ifndef STM32G4xx_HAL_SPI_EX_H
22 | #define STM32G4xx_HAL_SPI_EX_H
23 |
24 | #ifdef __cplusplus
25 | extern "C" {
26 | #endif
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32g4xx_hal_def.h"
30 |
31 | /** @addtogroup STM32G4xx_HAL_Driver
32 | * @{
33 | */
34 |
35 | /** @addtogroup SPIEx
36 | * @{
37 | */
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /* Exported macros -----------------------------------------------------------*/
42 | /* Exported functions --------------------------------------------------------*/
43 | /** @addtogroup SPIEx_Exported_Functions
44 | * @{
45 | */
46 |
47 | /* Initialization and de-initialization functions ****************************/
48 | /* IO operation functions *****************************************************/
49 | /** @addtogroup SPIEx_Exported_Functions_Group1
50 | * @{
51 | */
52 | HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
53 | /**
54 | * @}
55 | */
56 |
57 | /**
58 | * @}
59 | */
60 |
61 | /**
62 | * @}
63 | */
64 |
65 | /**
66 | * @}
67 | */
68 |
69 | #ifdef __cplusplus
70 | }
71 | #endif
72 |
73 | #endif /* STM32G4xx_HAL_SPI_EX_H */
74 |
75 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
76 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_msp_template.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_msp_template.c
4 | * @author MCD Application Team
5 | * @brief HAL MSP module.
6 | * This file template is located in the HAL folder and should be copied
7 | * to the user folder.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © Copyright (c) 2019 STMicroelectronics.
12 | * All rights reserved.
13 | *
14 | * This software component is licensed by ST under BSD 3-Clause license,
15 | * the "License"; You may not use this file except in compliance with the
16 | * License. You may obtain a copy of the License at:
17 | * opensource.org/licenses/BSD-3-Clause
18 | *
19 | ******************************************************************************
20 | */
21 |
22 | /* Includes ------------------------------------------------------------------*/
23 | #include "stm32g4xx_hal.h"
24 |
25 | /** @addtogroup STM32G4xx_HAL_Driver
26 | * @{
27 | */
28 |
29 | /** @defgroup HAL_MSP HAL MSP module driver
30 | * @brief HAL MSP module.
31 | * @{
32 | */
33 |
34 | /* Private typedef -----------------------------------------------------------*/
35 | /* Private define ------------------------------------------------------------*/
36 | /* Private macro -------------------------------------------------------------*/
37 | /* Private variables ---------------------------------------------------------*/
38 | /* Private function prototypes -----------------------------------------------*/
39 | /* Private functions ---------------------------------------------------------*/
40 |
41 | /** @defgroup HAL_MSP_Private_Functions
42 | * @{
43 | */
44 |
45 | /**
46 | * @brief Initialize the Global MSP.
47 | * @param None
48 | * @retval None
49 | */
50 | void HAL_MspInit(void)
51 | {
52 | /* NOTE : This function is generated automatically by STM32CubeMX and eventually
53 | modified by the user
54 | */
55 | }
56 |
57 | /**
58 | * @brief DeInitialize the Global MSP.
59 | * @param None
60 | * @retval None
61 | */
62 | void HAL_MspDeInit(void)
63 | {
64 | /* NOTE : This function is generated automatically by STM32CubeMX and eventually
65 | modified by the user
66 | */
67 | }
68 |
69 | /**
70 | * @brief Initialize the PPP MSP.
71 | * @param None
72 | * @retval None
73 | */
74 | void HAL_PPP_MspInit(void)
75 | {
76 | /* NOTE : This function is generated automatically by STM32CubeMX and eventually
77 | modified by the user
78 | */
79 | }
80 |
81 | /**
82 | * @brief DeInitialize the PPP MSP.
83 | * @param None
84 | * @retval None
85 | */
86 | void HAL_PPP_MspDeInit(void)
87 | {
88 | /* NOTE : This function is generated automatically by STM32CubeMX and eventually
89 | modified by the user
90 | */
91 | }
92 |
93 | /**
94 | * @}
95 | */
96 |
97 | /**
98 | * @}
99 | */
100 |
101 | /**
102 | * @}
103 | */
104 |
105 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
106 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_sai_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_sai_ex.c
4 | * @author MCD Application Team
5 | * @brief SAI Extended HAL module driver.
6 | * This file provides firmware functions to manage the following
7 | * functionality of the SAI Peripheral Controller:
8 | * + Modify PDM microphone delays.
9 | *
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © Copyright (c) 2019 STMicroelectronics.
14 | * All rights reserved.
15 | *
16 | * This software component is licensed by ST under BSD 3-Clause license,
17 | * the "License"; You may not use this file except in compliance with the
18 | * License. You may obtain a copy of the License at:
19 | * opensource.org/licenses/BSD-3-Clause
20 | *
21 | ******************************************************************************
22 | */
23 |
24 | /* Includes ------------------------------------------------------------------*/
25 | #include "stm32g4xx_hal.h"
26 |
27 | /** @addtogroup STM32G4xx_HAL_Driver
28 | * @{
29 | */
30 | #ifdef HAL_SAI_MODULE_ENABLED
31 |
32 | /** @defgroup SAIEx SAIEx
33 | * @brief SAI Extended HAL module driver
34 | * @{
35 | */
36 |
37 | /* Private types -------------------------------------------------------------*/
38 | /* Private variables ---------------------------------------------------------*/
39 | /* Private constants ---------------------------------------------------------*/
40 | /** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines
41 | * @{
42 | */
43 | #define SAI_PDM_DELAY_MASK 0x77U
44 | #define SAI_PDM_DELAY_OFFSET 8U
45 | #define SAI_PDM_RIGHT_DELAY_OFFSET 4U
46 | /**
47 | * @}
48 | */
49 |
50 | /* Private macros ------------------------------------------------------------*/
51 | /* Private functions ---------------------------------------------------------*/
52 | /* Exported functions --------------------------------------------------------*/
53 | /** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
54 | * @{
55 | */
56 |
57 | /** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
58 | * @brief SAIEx control functions
59 | *
60 | @verbatim
61 | ===============================================================================
62 | ##### Extended features functions #####
63 | ===============================================================================
64 | [..] This section provides functions allowing to:
65 | (+) Modify PDM microphone delays
66 |
67 | @endverbatim
68 | * @{
69 | */
70 |
71 | /**
72 | * @brief Configure PDM microphone delays.
73 | * @param hsai SAI handle.
74 | * @param pdmMicDelay Microphone delays configuration.
75 | * @retval HAL status
76 | */
77 | HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
78 | {
79 | HAL_StatusTypeDef status = HAL_OK;
80 | uint32_t offset;
81 |
82 | /* Check that SAI sub-block is SAI1 sub-block A */
83 | if (hsai->Instance != SAI1_Block_A)
84 | {
85 | status = HAL_ERROR;
86 | }
87 | else
88 | {
89 | /* Check microphone delay parameters */
90 | assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair));
91 | assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
92 | assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
93 |
94 | /* Compute offset on PDMDLY register according mic pair number */
95 | offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U);
96 |
97 | /* Check SAI state and offset */
98 | if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U))
99 | {
100 | /* Reset current delays for specified microphone */
101 | SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset);
102 |
103 | /* Apply new microphone delays */
104 | SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset);
105 | }
106 | else
107 | {
108 | status = HAL_ERROR;
109 | }
110 | }
111 | return status;
112 | }
113 |
114 | /**
115 | * @}
116 | */
117 |
118 | /**
119 | * @}
120 | */
121 |
122 | /**
123 | * @}
124 | */
125 |
126 | #endif /* HAL_SAI_MODULE_ENABLED */
127 | /**
128 | * @}
129 | */
130 |
131 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
132 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_spi_ex.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_hal_spi_ex.c
4 | * @author MCD Application Team
5 | * @brief Extended SPI HAL module driver.
6 | * This file provides firmware functions to manage the following
7 | * SPI peripheral extended functionalities :
8 | * + IO operation functions
9 | *
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © Copyright (c) 2019 STMicroelectronics.
14 | * All rights reserved.
15 | *
16 | * This software component is licensed by ST under BSD 3-Clause license,
17 | * the "License"; You may not use this file except in compliance with the
18 | * License. You may obtain a copy of the License at:
19 | * opensource.org/licenses/BSD-3-Clause
20 | *
21 | ******************************************************************************
22 | */
23 |
24 | /* Includes ------------------------------------------------------------------*/
25 | #include "stm32g4xx_hal.h"
26 |
27 | /** @addtogroup STM32G4xx_HAL_Driver
28 | * @{
29 | */
30 |
31 | /** @defgroup SPIEx SPIEx
32 | * @brief SPI Extended HAL module driver
33 | * @{
34 | */
35 | #ifdef HAL_SPI_MODULE_ENABLED
36 |
37 | /* Private typedef -----------------------------------------------------------*/
38 | /* Private defines -----------------------------------------------------------*/
39 | /** @defgroup SPIEx_Private_Constants SPIEx Private Constants
40 | * @{
41 | */
42 | #define SPI_FIFO_SIZE 4UL
43 | /**
44 | * @}
45 | */
46 |
47 | /* Private macros ------------------------------------------------------------*/
48 | /* Private variables ---------------------------------------------------------*/
49 | /* Private function prototypes -----------------------------------------------*/
50 | /* Exported functions --------------------------------------------------------*/
51 |
52 | /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
53 | * @{
54 | */
55 |
56 | /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
57 | * @brief Data transfers functions
58 | *
59 | @verbatim
60 | ==============================================================================
61 | ##### IO operation functions #####
62 | ===============================================================================
63 | [..]
64 | This subsection provides a set of extended functions to manage the SPI
65 | data transfers.
66 |
67 | (#) Rx data flush function:
68 | (++) HAL_SPIEx_FlushRxFifo()
69 |
70 | @endverbatim
71 | * @{
72 | */
73 |
74 | /**
75 | * @brief Flush the RX fifo.
76 | * @param hspi pointer to a SPI_HandleTypeDef structure that contains
77 | * the configuration information for the specified SPI module.
78 | * @retval HAL status
79 | */
80 | HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
81 | {
82 | __IO uint32_t tmpreg;
83 | uint8_t count = 0U;
84 | while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
85 | {
86 | count++;
87 | tmpreg = hspi->Instance->DR;
88 | UNUSED(tmpreg); /* To avoid GCC warning */
89 | if (count == SPI_FIFO_SIZE)
90 | {
91 | return HAL_TIMEOUT;
92 | }
93 | }
94 | return HAL_OK;
95 | }
96 |
97 | /**
98 | * @}
99 | */
100 |
101 | /**
102 | * @}
103 | */
104 |
105 | #endif /* HAL_SPI_MODULE_ENABLED */
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /**
112 | * @}
113 | */
114 |
115 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
116 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_wwdg.c:
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https://raw.githubusercontent.com/jiafan1949/SimCoJLink/62fcea8b79075927edc732b7662d8b72725e89fb/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_wwdg.c
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/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_cordic.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_ll_cordic.c
4 | * @author MCD Application Team
5 | * @brief CORDIC LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g4xx_ll_cordic.h"
23 | #include "stm32g4xx_ll_bus.h"
24 | #ifdef USE_FULL_ASSERT
25 | #include "stm32_assert.h"
26 | #else
27 | #define assert_param(expr) ((void)0U)
28 | #endif
29 |
30 | /** @addtogroup STM32G4xx_LL_Driver
31 | * @{
32 | */
33 |
34 | #if defined(CORDIC)
35 |
36 | /** @addtogroup CORDIC_LL
37 | * @{
38 | */
39 |
40 | /* Private types -------------------------------------------------------------*/
41 | /* Private variables ---------------------------------------------------------*/
42 | /* Private constants ---------------------------------------------------------*/
43 | /* Private macros ------------------------------------------------------------*/
44 | /* Private function prototypes -----------------------------------------------*/
45 |
46 | /* Exported functions --------------------------------------------------------*/
47 | /** @addtogroup CORDIC_LL_Exported_Functions
48 | * @{
49 | */
50 |
51 | /** @addtogroup CORDIC_LL_EF_Init
52 | * @{
53 | */
54 |
55 | /**
56 | * @brief De-Initialize CORDIC peripheral registers to their default reset values.
57 | * @param CORDICx CORDIC Instance
58 | * @retval An ErrorStatus enumeration value:
59 | * - SUCCESS: CORDIC registers are de-initialized
60 | * - ERROR: CORDIC registers are not de-initialized
61 | */
62 | ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx)
63 | {
64 | ErrorStatus status = SUCCESS;
65 |
66 | /* Check the parameters */
67 | assert_param(IS_CORDIC_ALL_INSTANCE(CORDICx));
68 |
69 | if (CORDICx == CORDIC)
70 | {
71 | /* Force CORDIC reset */
72 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CORDIC);
73 |
74 | /* Release CORDIC reset */
75 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CORDIC);
76 | }
77 | else
78 | {
79 | status = ERROR;
80 | }
81 |
82 | return (status);
83 | }
84 |
85 | /**
86 | * @}
87 | */
88 |
89 | /**
90 | * @}
91 | */
92 |
93 | /**
94 | * @}
95 | */
96 |
97 | #endif /* defined(CORDIC) */
98 |
99 | /**
100 | * @}
101 | */
102 |
103 | #endif /* USE_FULL_LL_DRIVER */
104 |
105 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
106 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_crc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_ll_crc.c
4 | * @author MCD Application Team
5 | * @brief CRC LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g4xx_ll_crc.h"
23 | #include "stm32g4xx_ll_bus.h"
24 |
25 | #ifdef USE_FULL_ASSERT
26 | #include "stm32_assert.h"
27 | #else
28 | #define assert_param(expr) ((void)0U)
29 | #endif
30 |
31 | /** @addtogroup STM32G4xx_LL_Driver
32 | * @{
33 | */
34 |
35 | #if defined (CRC)
36 |
37 | /** @addtogroup CRC_LL
38 | * @{
39 | */
40 |
41 | /* Private types -------------------------------------------------------------*/
42 | /* Private variables ---------------------------------------------------------*/
43 | /* Private constants ---------------------------------------------------------*/
44 | /* Private macros ------------------------------------------------------------*/
45 | /* Private function prototypes -----------------------------------------------*/
46 |
47 | /* Exported functions --------------------------------------------------------*/
48 | /** @addtogroup CRC_LL_Exported_Functions
49 | * @{
50 | */
51 |
52 | /** @addtogroup CRC_LL_EF_Init
53 | * @{
54 | */
55 |
56 | /**
57 | * @brief De-initialize CRC registers (Registers restored to their default values).
58 | * @param CRCx CRC Instance
59 | * @retval An ErrorStatus enumeration value:
60 | * - SUCCESS: CRC registers are de-initialized
61 | * - ERROR: CRC registers are not de-initialized
62 | */
63 | ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
64 | {
65 | ErrorStatus status = SUCCESS;
66 |
67 | /* Check the parameters */
68 | assert_param(IS_CRC_ALL_INSTANCE(CRCx));
69 |
70 | if (CRCx == CRC)
71 | {
72 | /* Force CRC reset */
73 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
74 |
75 | /* Release CRC reset */
76 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
77 | }
78 | else
79 | {
80 | status = ERROR;
81 | }
82 |
83 | return (status);
84 | }
85 |
86 | /**
87 | * @}
88 | */
89 |
90 | /**
91 | * @}
92 | */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | #endif /* defined (CRC) */
99 |
100 | /**
101 | * @}
102 | */
103 |
104 | #endif /* USE_FULL_LL_DRIVER */
105 |
106 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
107 |
108 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_crs.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_ll_crs.h
4 | * @author MCD Application Team
5 | * @brief CRS LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g4xx_ll_crs.h"
23 | #include "stm32g4xx_ll_bus.h"
24 |
25 | /** @addtogroup STM32G4xx_LL_Driver
26 | * @{
27 | */
28 |
29 | #if defined(CRS)
30 |
31 | /** @defgroup CRS_LL CRS
32 | * @{
33 | */
34 |
35 | /* Private types -------------------------------------------------------------*/
36 | /* Private variables ---------------------------------------------------------*/
37 | /* Private constants ---------------------------------------------------------*/
38 | /* Private macros ------------------------------------------------------------*/
39 | /* Private function prototypes -----------------------------------------------*/
40 |
41 | /* Exported functions --------------------------------------------------------*/
42 | /** @addtogroup CRS_LL_Exported_Functions
43 | * @{
44 | */
45 |
46 | /** @addtogroup CRS_LL_EF_Init
47 | * @{
48 | */
49 |
50 | /**
51 | * @brief De-Initializes CRS peripheral registers to their default reset values.
52 | * @retval An ErrorStatus enumeration value:
53 | * - SUCCESS: CRS registers are de-initialized
54 | * - ERROR: not applicable
55 | */
56 | ErrorStatus LL_CRS_DeInit(void)
57 | {
58 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
59 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
60 |
61 | return SUCCESS;
62 | }
63 |
64 |
65 |
66 | /**
67 | * @}
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /**
75 | * @}
76 | */
77 |
78 | #endif /* defined(CRS) */
79 |
80 | /**
81 | * @}
82 | */
83 |
84 | #endif /* USE_FULL_LL_DRIVER */
85 |
86 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
87 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_fmac.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_ll_fmac.c
4 | * @author MCD Application Team
5 | * @brief Header for stm32g4xx_ll_fmac.c module
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g4xx_ll_fmac.h"
23 | #include "stm32g4xx_ll_bus.h"
24 | #ifdef USE_FULL_ASSERT
25 | #include "stm32_assert.h"
26 | #else
27 | #define assert_param(expr) ((void)0)
28 | #endif /* USE_FULL_ASSERT */
29 |
30 | /** @addtogroup STM32G4xx_LL_Driver
31 | * @{
32 | */
33 |
34 | #if defined(FMAC)
35 |
36 | /** @addtogroup FMAC_LL
37 | * @{
38 | */
39 |
40 | /* Private typedef -----------------------------------------------------------*/
41 | /* Private defines -----------------------------------------------------------*/
42 | /* Private macros ------------------------------------------------------------*/
43 | /* Private variables ---------------------------------------------------------*/
44 | /* Global variables ----------------------------------------------------------*/
45 | /* Private function prototypes -----------------------------------------------*/
46 | /* Functions Definition ------------------------------------------------------*/
47 | /** @addtogroup FMAC_LL_Exported_Functions
48 | * @{
49 | */
50 |
51 | /** @addtogroup FMAC_LL_EF_Init
52 | * @{
53 | */
54 |
55 | /**
56 | * @brief Initialize FMAC peripheral registers to their default reset values.
57 | * @param FMACx FMAC Instance
58 | * @retval ErrorStatus enumeration value:
59 | * - SUCCESS: FMAC registers are initialized
60 | * - ERROR: FMAC registers are not initialized
61 | */
62 | ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx)
63 | {
64 | ErrorStatus status = SUCCESS;
65 |
66 | /* Check the parameters */
67 | assert_param(IS_FMAC_ALL_INSTANCE(FMACx));
68 |
69 | if (FMACx == FMAC)
70 | {
71 | /* Perform the reset */
72 | LL_FMAC_EnableReset(FMACx);
73 |
74 | /* Wait until flag is reset */
75 | while (LL_FMAC_IsEnabledReset(FMACx) != 0UL)
76 | {
77 | }
78 | }
79 | else
80 | {
81 | status = ERROR;
82 | }
83 |
84 | return (status);
85 | }
86 |
87 | /**
88 | * @brief De-Initialize FMAC peripheral registers to their default reset values.
89 | * @param FMACx FMAC Instance
90 | * @retval An ErrorStatus enumeration value:
91 | * - SUCCESS: FMAC registers are de-initialized
92 | * - ERROR: FMAC registers are not de-initialized
93 | */
94 | ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx)
95 | {
96 | ErrorStatus status = SUCCESS;
97 |
98 | /* Check the parameters */
99 | assert_param(IS_FMAC_ALL_INSTANCE(FMACx));
100 |
101 | if (FMACx == FMAC)
102 | {
103 | /* Force FMAC reset */
104 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_FMAC);
105 |
106 | /* Release FMAC reset */
107 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_FMAC);
108 | }
109 | else
110 | {
111 | status = ERROR;
112 | }
113 |
114 | return (status);
115 | }
116 |
117 |
118 |
119 | /**
120 | * @}
121 | */
122 |
123 | /**
124 | * @}
125 | */
126 |
127 | /**
128 | * @}
129 | */
130 |
131 | #endif /* defined(FMAC) */
132 |
133 | /**
134 | * @}
135 | */
136 |
137 | #endif /* USE_FULL_LL_DRIVER */
138 |
139 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
140 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_hrtim.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_ll_hrtim.c
4 | * @author MCD Application Team
5 | * @brief HRTIM LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g4xx_ll_hrtim.h"
23 | #include "stm32g4xx_ll_bus.h"
24 |
25 | #ifdef USE_FULL_ASSERT
26 | #include "stm32_assert.h"
27 | #else
28 | #define assert_param(expr) ((void)0U)
29 | #endif
30 |
31 | /** @addtogroup STM32G4xx_LL_Driver
32 | * @{
33 | */
34 |
35 | #if defined (HRTIM1)
36 |
37 | /** @addtogroup HRTIM_LL
38 | * @{
39 | */
40 |
41 | /* Private types -------------------------------------------------------------*/
42 | /* Private variables ---------------------------------------------------------*/
43 | /* Private constants ---------------------------------------------------------*/
44 | /* Private macros ------------------------------------------------------------*/
45 | /* Private function prototypes -----------------------------------------------*/
46 | /* Exported functions --------------------------------------------------------*/
47 | /** @addtogroup HRTIM_LL_Exported_Functions
48 | * @{
49 | */
50 | /**
51 | * @brief Set HRTIM instance registers to their reset values.
52 | * @param HRTIMx High Resolution Timer instance
53 | * @retval ErrorStatus enumeration value:
54 | * - SUCCESS: HRTIMx registers are de-initialized
55 | * - ERROR: invalid HRTIMx instance
56 | */
57 | ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx)
58 | {
59 | ErrorStatus result = SUCCESS;
60 |
61 | /* Check the parameters */
62 | assert_param(IS_HRTIM_ALL_INSTANCE(HRTIMx));
63 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM1);
64 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM1);
65 | return result;
66 | }
67 | /**
68 | * @}
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | #endif /* HRTIM1 */
76 |
77 | /**
78 | * @}
79 | */
80 |
81 | #endif /* USE_FULL_LL_DRIVER */
82 |
83 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
84 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_pwr.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_ll_pwr.c
4 | * @author MCD Application Team
5 | * @brief PWR LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g4xx_ll_pwr.h"
23 | #include "stm32g4xx_ll_bus.h"
24 |
25 | /** @addtogroup STM32G4xx_LL_Driver
26 | * @{
27 | */
28 |
29 | #if defined(PWR)
30 |
31 | /** @defgroup PWR_LL PWR
32 | * @{
33 | */
34 |
35 | /* Private types -------------------------------------------------------------*/
36 | /* Private variables ---------------------------------------------------------*/
37 | /* Private constants ---------------------------------------------------------*/
38 | /* Private macros ------------------------------------------------------------*/
39 | /* Private function prototypes -----------------------------------------------*/
40 |
41 | /* Exported functions --------------------------------------------------------*/
42 | /** @addtogroup PWR_LL_Exported_Functions
43 | * @{
44 | */
45 |
46 | /** @addtogroup PWR_LL_EF_Init
47 | * @{
48 | */
49 |
50 | /**
51 | * @brief De-initialize the PWR registers to their default reset values.
52 | * @retval An ErrorStatus enumeration value:
53 | * - SUCCESS: PWR registers are de-initialized
54 | * - ERROR: not applicable
55 | */
56 | ErrorStatus LL_PWR_DeInit(void)
57 | {
58 | /* Force reset of PWR clock */
59 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
60 |
61 | /* Release reset of PWR clock */
62 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
63 |
64 | return SUCCESS;
65 | }
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /**
76 | * @}
77 | */
78 | #endif /* defined(PWR) */
79 | /**
80 | * @}
81 | */
82 |
83 | #endif /* USE_FULL_LL_DRIVER */
84 |
85 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
86 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_rng.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_ll_rng.c
4 | * @author MCD Application Team
5 | * @brief RNG LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2019 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g4xx_ll_rng.h"
23 | #include "stm32g4xx_ll_bus.h"
24 |
25 | #ifdef USE_FULL_ASSERT
26 | #include "stm32_assert.h"
27 | #else
28 | #define assert_param(expr) ((void)0U)
29 | #endif
30 |
31 | /** @addtogroup STM32G4xx_LL_Driver
32 | * @{
33 | */
34 |
35 | #if defined (RNG)
36 |
37 | /** @addtogroup RNG_LL
38 | * @{
39 | */
40 |
41 | /* Private types -------------------------------------------------------------*/
42 | /* Private variables ---------------------------------------------------------*/
43 | /* Private constants ---------------------------------------------------------*/
44 | /* Private macros ------------------------------------------------------------*/
45 | /** @addtogroup RNG_LL_Private_Macros
46 | * @{
47 | */
48 | #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
49 | ((__MODE__) == LL_RNG_CED_DISABLE))
50 |
51 | /**
52 | * @}
53 | */
54 | /* Private function prototypes -----------------------------------------------*/
55 |
56 | /* Exported functions --------------------------------------------------------*/
57 | /** @addtogroup RNG_LL_Exported_Functions
58 | * @{
59 | */
60 |
61 | /** @addtogroup RNG_LL_EF_Init
62 | * @{
63 | */
64 |
65 | /**
66 | * @brief De-initialize RNG registers (Registers restored to their default values).
67 | * @param RNGx RNG Instance
68 | * @retval An ErrorStatus enumeration value:
69 | * - SUCCESS: RNG registers are de-initialized
70 | * - ERROR: not applicable
71 | */
72 | ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
73 | {
74 | /* Check the parameters */
75 | assert_param(IS_RNG_ALL_INSTANCE(RNGx));
76 | /* Enable RNG reset state */
77 | LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
78 |
79 | /* Release RNG from reset state */
80 | LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
81 | return (SUCCESS);
82 | }
83 |
84 | /**
85 | * @brief Initialize RNG registers according to the specified parameters in RNG_InitStruct.
86 | * @param RNGx RNG Instance
87 | * @param RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure
88 | * that contains the configuration information for the specified RNG peripheral.
89 | * @retval An ErrorStatus enumeration value:
90 | * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
91 | * - ERROR: not applicable
92 | */
93 | ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
94 | {
95 | /* Check the parameters */
96 | assert_param(IS_RNG_ALL_INSTANCE(RNGx));
97 | assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
98 |
99 | /* Clock Error Detection configuration */
100 | MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection);
101 |
102 | return (SUCCESS);
103 | }
104 |
105 | /**
106 | * @brief Set each @ref LL_RNG_InitTypeDef field to default value.
107 | * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure
108 | * whose fields will be set to default values.
109 | * @retval None
110 | */
111 | void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
112 | {
113 | /* Set RNG_InitStruct fields to default values */
114 | RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
115 |
116 | }
117 | /**
118 | * @}
119 | */
120 |
121 | /**
122 | * @}
123 | */
124 |
125 | /**
126 | * @}
127 | */
128 |
129 | #endif /* RNG */
130 |
131 | /**
132 | * @}
133 | */
134 |
135 | #endif /* USE_FULL_LL_DRIVER */
136 |
137 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
138 |
139 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32g4xx_ll_ucpd.c
4 | * @author MCD Application Team
5 | * @brief UCPD LL module driver.
6 | ******************************************************************************
7 | * @attention
8 | *
9 | * © Copyright (c) 2018 STMicroelectronics.
10 | * All rights reserved.
11 | *
12 | * This software component is licensed by ST under BSD 3-Clause license,
13 | * the "License"; You may not use this file except in compliance with the
14 | * License. You may obtain a copy of the License at:
15 | * opensource.org/licenses/BSD-3-Clause
16 | *
17 | ******************************************************************************
18 | */
19 | #if defined(USE_FULL_LL_DRIVER)
20 |
21 | /* Includes ------------------------------------------------------------------*/
22 | #include "stm32g4xx_ll_ucpd.h"
23 | #include "stm32g4xx_ll_bus.h"
24 | #include "stm32g4xx_ll_rcc.h"
25 |
26 | #ifdef USE_FULL_ASSERT
27 | #include "stm32_assert.h"
28 | #else
29 | #define assert_param(expr) ((void)0U)
30 | #endif
31 |
32 | /** @addtogroup STM32G4xx_LL_Driver
33 | * @{
34 | */
35 | #if defined (UCPD1)
36 | /** @addtogroup UCPD_LL
37 | * @{
38 | */
39 |
40 | /* Private types -------------------------------------------------------------*/
41 | /* Private variables ---------------------------------------------------------*/
42 |
43 | /* Private constants ---------------------------------------------------------*/
44 | /** @defgroup UCPD_LL_Private_Constants UCPD Private Constants
45 | * @{
46 | */
47 |
48 | /**
49 | * @}
50 | */
51 |
52 | /* Private macros ------------------------------------------------------------*/
53 | /** @defgroup UCPD_LL_Private_Macros UCPD Private Macros
54 | * @{
55 | */
56 |
57 |
58 | /**
59 | * @}
60 | */
61 |
62 | /* Private function prototypes -----------------------------------------------*/
63 |
64 | /* Exported functions --------------------------------------------------------*/
65 | /** @addtogroup UCPD_LL_Exported_Functions
66 | * @{
67 | */
68 |
69 | /** @addtogroup UCPD_LL_EF_Init
70 | * @{
71 | */
72 |
73 | /**
74 | * @brief De-initialize the UCPD registers to their default reset values.
75 | * @param UCPDx ucpd Instance
76 | * @retval An ErrorStatus enumeration value:
77 | * - SUCCESS: ucpd registers are de-initialized
78 | * - ERROR: ucpd registers are not de-initialized
79 | */
80 | ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx)
81 | {
82 | ErrorStatus status = ERROR;
83 |
84 | /* Check the parameters */
85 | assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
86 |
87 | LL_UCPD_Disable(UCPDx);
88 |
89 | if (UCPD1 == UCPDx)
90 | {
91 | /* Force reset of ucpd clock */
92 | LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1);
93 |
94 | /* Release reset of ucpd clock */
95 | LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1);
96 |
97 | /* Disable ucpd clock */
98 | LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1);
99 |
100 | status = SUCCESS;
101 | }
102 |
103 | return status;
104 | }
105 |
106 | /**
107 | * @brief Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
108 | * @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled (ucpd_CR1_SPE bit =0),
109 | * UCPD peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
110 | * @param UCPDx UCPD Instance
111 | * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains
112 | * the configuration information for the UCPD peripheral.
113 | * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
114 | */
115 | ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
116 | {
117 | /* Check the ucpd Instance UCPDx*/
118 | assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
119 |
120 | if(UCPD1 == UCPDx)
121 | {
122 | LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1);
123 | }
124 |
125 |
126 | LL_UCPD_Disable(UCPDx);
127 |
128 | /*---------------------------- UCPDx CFG1 Configuration ------------------------*/
129 | MODIFY_REG(UCPDx->CFG1,
130 | UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV,
131 | UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin << UCPD_CFG1_TRANSWIN_Pos) |
132 | (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv);
133 |
134 | return SUCCESS;
135 | }
136 |
137 | /**
138 | * @brief Set each @ref LL_UCPD_InitTypeDef field to default value.
139 | * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure
140 | * whose fields will be set to default values.
141 | * @retval None
142 | */
143 | void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct)
144 | {
145 | /* Set UCPD_InitStruct fields to default values */
146 | UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV2;
147 | UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */
148 | UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */
149 | UCPD_InitStruct->HbitClockDiv = 0x0D; /* Divide by 14 to produce HBITCLK */
150 | }
151 |
152 | /**
153 | * @}
154 | */
155 |
156 | /**
157 | * @}
158 | */
159 |
160 | /**
161 | * @}
162 | */
163 | #endif /* defined (UCPD1) */
164 | /**
165 | * @}
166 | */
167 |
168 | #endif /* USE_FULL_LL_DRIVER */
169 |
170 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
171 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/MDK-ARM/DebugConfig/STM32G474RET_ESC_STM32G474RETx.dbgconf:
--------------------------------------------------------------------------------
1 | // File: STM32G4xx.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32G4xx Reference manual (RM0440)
4 | // refer to STM32G4xx datasheets
5 |
6 | // <<< Use Configuration Wizard in Context Menu >>>
7 |
8 | // Debug MCU configuration register (DBGMCU_CR)
9 | // DBG_STANDBY Debug Standby mode
10 | // DBG_STOP Debug Stop mode
11 | // DBG_SLEEP Debug Sleep mode
12 | //
13 | DbgMCU_CR = 0x00000007;
14 |
15 | // Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
16 | // Reserved bits must be kept at reset value
17 | // DBG_LPTIM1_STOP LPTIM1 counter stopped when core is halted
18 | // DBG_I2C3_STOP I2C3 SMBUS timeout counter stopped when core is halted
19 | // DBG_I2C2_STOP I2C2 SMBUS timeout counter stopped when core is halted
20 | // DBG_I2C1_STOP I2C1 SMBUS timeout counter stopped when core is halted
21 | // DBG_IWDG_STOP Independent watchdog counter stopped when core is halted
22 | // DBG_WWDG_STOP Window watchdog counter stopped when core is halted
23 | // DBG_RTC_STOP RTC counter stopped when core is halted
24 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
25 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
26 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted
27 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted
28 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
29 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
30 | //
31 | DbgMCU_APB1_Fz1 = 0x00000000;
32 |
33 | // Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
34 | // Reserved bits must be kept at reset value
35 | // DBG_I2C4_STOP I2C4 SMBUS timeout counter stopped when core is halted
36 | //
37 | DbgMCU_APB1_Fz2 = 0x00000000;
38 |
39 | // Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
40 | // Reserved bits must be kept at reset value
41 | // DBG_HRTIM_STOP HRTIM counter stopped when core is halted
42 | // DBG_TIM20_STOP TIM20 counter stopped when core is halted
43 | // DBG_TIM17_STOP TIM17 counter stopped when core is halted
44 | // DBG_TIM16_STOP TIM16 counter stopped when core is halted
45 | // DBG_TIM15_STOP TIM15 counter stopped when core is halted
46 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted
47 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
48 | //
49 | DbgMCU_APB2_Fz = 0x00000000;
50 | //
51 |
52 | // <<< end of configuration section >>>
53 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/MDK-ARM/DebugConfig/STM32G474RE_Cortex_M4_STM32G474RETx.dbgconf:
--------------------------------------------------------------------------------
1 | // File: STM32G4xx.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32G4xx Reference manual (RM0440)
4 | // refer to STM32G4xx datasheets
5 |
6 | // <<< Use Configuration Wizard in Context Menu >>>
7 |
8 | // Debug MCU configuration register (DBGMCU_CR)
9 | // DBG_STANDBY Debug Standby mode
10 | // DBG_STOP Debug Stop mode
11 | // DBG_SLEEP Debug Sleep mode
12 | //
13 | DbgMCU_CR = 0x00000007;
14 |
15 | // Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
16 | // Reserved bits must be kept at reset value
17 | // DBG_LPTIM1_STOP LPTIM1 counter stopped when core is halted
18 | // DBG_I2C3_STOP I2C3 SMBUS timeout counter stopped when core is halted
19 | // DBG_I2C2_STOP I2C2 SMBUS timeout counter stopped when core is halted
20 | // DBG_I2C1_STOP I2C1 SMBUS timeout counter stopped when core is halted
21 | // DBG_IWDG_STOP Independent watchdog counter stopped when core is halted
22 | // DBG_WWDG_STOP Window watchdog counter stopped when core is halted
23 | // DBG_RTC_STOP RTC counter stopped when core is halted
24 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
25 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
26 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted
27 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted
28 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
29 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
30 | //
31 | DbgMCU_APB1_Fz1 = 0x00000000;
32 |
33 | // Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
34 | // Reserved bits must be kept at reset value
35 | // DBG_I2C4_STOP I2C4 SMBUS timeout counter stopped when core is halted
36 | //
37 | DbgMCU_APB1_Fz2 = 0x00000000;
38 |
39 | // Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
40 | // Reserved bits must be kept at reset value
41 | // DBG_HRTIM_STOP HRTIM counter stopped when core is halted
42 | // DBG_TIM20_STOP TIM20 counter stopped when core is halted
43 | // DBG_TIM17_STOP TIM17 counter stopped when core is halted
44 | // DBG_TIM16_STOP TIM16 counter stopped when core is halted
45 | // DBG_TIM15_STOP TIM15 counter stopped when core is halted
46 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted
47 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
48 | //
49 | DbgMCU_APB2_Fz = 0x00000000;
50 | //
51 |
52 | // <<< end of configuration section >>>
53 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/MDK-ARM/EventRecorderStub.scvd:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/MDK-ARM/JLinkSettings.ini:
--------------------------------------------------------------------------------
1 | [BREAKPOINTS]
2 | ForceImpTypeAny = 0
3 | ShowInfoWin = 1
4 | EnableFlashBP = 2
5 | BPDuringExecution = 0
6 | [CFI]
7 | CFISize = 0x00
8 | CFIAddr = 0x00
9 | [CPU]
10 | MonModeVTableAddr = 0xFFFFFFFF
11 | MonModeDebug = 0
12 | MaxNumAPs = 0
13 | LowPowerHandlingMode = 0
14 | OverrideMemMap = 0
15 | AllowSimulation = 1
16 | ScriptFile=""
17 | [FLASH]
18 | CacheExcludeSize = 0x00
19 | CacheExcludeAddr = 0x00
20 | MinNumBytesFlashDL = 0
21 | SkipProgOnCRCMatch = 1
22 | VerifyDownload = 1
23 | AllowCaching = 1
24 | EnableFlashDL = 2
25 | Override = 1
26 | Device="STM32G474RE"
27 | [GENERAL]
28 | WorkRAMSize = 0x20000
29 | WorkRAMAddr = 0x20000000
30 | RAMUsageLimit = 0x00
31 | [SWO]
32 | SWOLogFile=""
33 | [MEM]
34 | RdOverrideOrMask = 0x00
35 | RdOverrideAndMask = 0xFFFFFFFF
36 | RdOverrideAddr = 0xFFFFFFFF
37 | WrOverrideOrMask = 0x00
38 | WrOverrideAndMask = 0xFFFFFFFF
39 | WrOverrideAddr = 0xFFFFFFFF
40 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/MDK-ARM/RTE/_STM32G474RE_Cortex_M4/RTE_Components.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * Auto generated Run-Time-Environment Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'STM32G474RE_Cortex_M4'
7 | * Target: 'STM32G474RE_Cortex_M4'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32g4xx.h"
18 |
19 |
20 |
21 | #endif /* RTE_COMPONENTS_H */
22 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/SEGGER/CRC16.c:
--------------------------------------------------------------------------------
1 | static const unsigned char aucCRCHi[] = {
2 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
3 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
4 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
5 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
6 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
7 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
8 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
9 | 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
10 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
11 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
12 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
13 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
14 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
15 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
16 | 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
17 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
18 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
19 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
20 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
21 | 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
22 | 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
23 | 0x00, 0xC1, 0x81, 0x40
24 | };
25 |
26 | static const unsigned char aucCRCLo[] = {
27 | 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
28 | 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
29 | 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
30 | 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
31 | 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
32 | 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
33 | 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
34 | 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
35 | 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
36 | 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
37 | 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
38 | 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
39 | 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
40 | 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
41 | 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
42 | 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
43 | 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
44 | 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
45 | 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
46 | 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
47 | 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
48 | 0x41, 0x81, 0x80, 0x40
49 | };
50 |
51 | unsigned short usMBCRC16(unsigned char * pucFrame, unsigned short usLen)
52 | {
53 | unsigned char ucCRCHi = 0xFF;
54 | unsigned char ucCRCLo = 0xFF;
55 | int iIndex;
56 |
57 | while (usLen--)
58 | {
59 | iIndex = ucCRCLo ^ *(pucFrame++);
60 | ucCRCLo = (unsigned char)(ucCRCHi ^ aucCRCHi[iIndex]);
61 | ucCRCHi = aucCRCLo[iIndex];
62 | }
63 | return (unsigned short)(ucCRCHi << 8 | ucCRCLo);
64 | }
65 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/SEGGER/CRC16.h:
--------------------------------------------------------------------------------
1 |
2 | extern unsigned short usMBCRC16(unsigned char * pucFrame, unsigned short usLen);
3 |
4 |
--------------------------------------------------------------------------------
/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/KeilMDK_NUCLEOG474RE/STM32G474RE_Cortex_M4.ioc:
--------------------------------------------------------------------------------
1 | #MicroXplorer Configuration settings - do not modify
2 | File.Version=6
3 | GPIO.groupedBy=Group By Peripherals
4 | KeepUserPlacement=false
5 | Mcu.Family=STM32G4
6 | Mcu.IP0=NVIC
7 | Mcu.IP1=RCC
8 | Mcu.IP2=SYS
9 | Mcu.IP3=TIM1
10 | Mcu.IPNb=4
11 | Mcu.Name=STM32G474R(B-C-E)Tx
12 | Mcu.Package=LQFP64
13 | Mcu.Pin0=PF0-OSC_IN
14 | Mcu.Pin1=PF1-OSC_OUT
15 | Mcu.Pin2=PA13
16 | Mcu.Pin3=PA14
17 | Mcu.Pin4=VP_SYS_VS_Systick
18 | Mcu.Pin5=VP_SYS_VS_DBSignals
19 | Mcu.Pin6=VP_TIM1_VS_ClockSourceINT
20 | Mcu.PinsNb=7
21 | Mcu.ThirdPartyNb=0
22 | Mcu.UserConstants=
23 | Mcu.UserName=STM32G474RETx
24 | MxCube.Version=6.0.1
25 | MxDb.Version=DB.6.0.0
26 | NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
27 | NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
28 | NVIC.ForceEnableDMAVector=true
29 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
30 | NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
31 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
32 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
33 | NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
34 | NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
35 | NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
36 | NVIC.TIM1_UP_TIM16_IRQn=true\:0\:0\:false\:false\:true\:true\:true
37 | NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
38 | PA13.Mode=Serial_Wire
39 | PA13.Signal=SYS_JTMS-SWDIO
40 | PA14.Mode=Serial_Wire
41 | PA14.Signal=SYS_JTCK-SWCLK
42 | PF0-OSC_IN.Mode=HSE-External-Oscillator
43 | PF0-OSC_IN.Signal=RCC_OSC_IN
44 | PF1-OSC_OUT.Mode=HSE-External-Oscillator
45 | PF1-OSC_OUT.Signal=RCC_OSC_OUT
46 | PinOutPanel.RotationAngle=0
47 | ProjectManager.AskForMigrate=true
48 | ProjectManager.BackupPrevious=false
49 | ProjectManager.CompilerOptimize=6
50 | ProjectManager.ComputerToolchain=false
51 | ProjectManager.CoupleFile=false
52 | ProjectManager.CustomerFirmwarePackage=
53 | ProjectManager.DefaultFWLocation=true
54 | ProjectManager.DeletePrevious=true
55 | ProjectManager.DeviceId=STM32G474RETx
56 | ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.3.0
57 | ProjectManager.FreePins=false
58 | ProjectManager.HalAssertFull=false
59 | ProjectManager.HeapSize=0x200
60 | ProjectManager.KeepUserCode=true
61 | ProjectManager.LastFirmware=true
62 | ProjectManager.LibraryCopy=0
63 | ProjectManager.MainLocation=Core/Src
64 | ProjectManager.NoMain=false
65 | ProjectManager.PreviousToolchain=
66 | ProjectManager.ProjectBuild=false
67 | ProjectManager.ProjectFileName=STM32G474RE_Cortex_M4.ioc
68 | ProjectManager.ProjectName=STM32G474RE_Cortex_M4
69 | ProjectManager.RegisterCallBack=
70 | ProjectManager.StackSize=0x400
71 | ProjectManager.TargetToolchain=MDK-ARM V5.27
72 | ProjectManager.ToolChainLocation=
73 | ProjectManager.UnderRoot=false
74 | ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_TIM1_Init-TIM1-false-HAL-true
75 | RCC.ADC12Freq_Value=170000000
76 | RCC.ADC345Freq_Value=170000000
77 | RCC.AHBFreq_Value=170000000
78 | RCC.APB1Freq_Value=170000000
79 | RCC.APB1TimFreq_Value=170000000
80 | RCC.APB2Freq_Value=170000000
81 | RCC.APB2TimFreq_Value=170000000
82 | RCC.CRSFreq_Value=48000000
83 | RCC.CortexFreq_Value=170000000
84 | RCC.EXTERNAL_CLOCK_VALUE=12288000
85 | RCC.FCLKCortexFreq_Value=170000000
86 | RCC.FDCANFreq_Value=170000000
87 | RCC.FamilyName=M
88 | RCC.HCLKFreq_Value=170000000
89 | RCC.HRTIM1Freq_Value=170000000
90 | RCC.HSE_VALUE=24000000
91 | RCC.HSI48_VALUE=48000000
92 | RCC.HSI_VALUE=16000000
93 | RCC.I2C1Freq_Value=170000000
94 | RCC.I2C2Freq_Value=170000000
95 | RCC.I2C3Freq_Value=170000000
96 | RCC.I2C4Freq_Value=170000000
97 | RCC.I2SFreq_Value=170000000
98 | RCC.IPParameters=ADC12Freq_Value,ADC345Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
99 | RCC.LPTIM1Freq_Value=170000000
100 | RCC.LPUART1Freq_Value=170000000
101 | RCC.LSCOPinFreq_Value=32000
102 | RCC.LSE_VALUE=32768
103 | RCC.LSI_VALUE=32000
104 | RCC.MCO1PinFreq_Value=16000000
105 | RCC.PLLM=RCC_PLLM_DIV4
106 | RCC.PLLN=85
107 | RCC.PLLPoutputFreq_Value=170000000
108 | RCC.PLLQoutputFreq_Value=170000000
109 | RCC.PLLRCLKFreq_Value=170000000
110 | RCC.PWRFreq_Value=170000000
111 | RCC.QSPIFreq_Value=170000000
112 | RCC.RNGFreq_Value=170000000
113 | RCC.SAI1Freq_Value=170000000
114 | RCC.SYSCLKFreq_VALUE=170000000
115 | RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
116 | RCC.UART4Freq_Value=170000000
117 | RCC.UART5Freq_Value=170000000
118 | RCC.USART1Freq_Value=170000000
119 | RCC.USART2Freq_Value=170000000
120 | RCC.USART3Freq_Value=170000000
121 | RCC.USBFreq_Value=170000000
122 | RCC.VCOInputFreq_Value=4000000
123 | RCC.VCOOutputFreq_Value=340000000
124 | TIM1.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
125 | TIM1.IPParameters=Prescaler,PeriodNoDither,AutoReloadPreload
126 | TIM1.PeriodNoDither=17000-1
127 | TIM1.Prescaler=0
128 | VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals
129 | VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals
130 | VP_SYS_VS_Systick.Mode=SysTick
131 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick
132 | VP_TIM1_VS_ClockSourceINT.Mode=Internal
133 | VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
134 | board=custom
135 |
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/SimCoJLink_Example/NUM2_NUCLEO_G474RE_Cortex_M4/SimulinkHostModel/SimCoJLinkExample_G474.slx:
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/SimCoJLink_SimulinkLib/SimCoJLink.slx:
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/SimCoJLink_SimulinkLib/SimCoJLink_Receive.mexw64:
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/SimCoJLink_SimulinkLib/SimCoJLink_Set.mexw64:
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/SimCoJLink_SimulinkLib/SimCoJLink_Transmit.mexw64:
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/SimCoJLink_SimulinkLib/slblocks.m:
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1 | function blkStruct = slblocks
2 | % This function specifies that the library should appear
3 | % in the Library Browser
4 | % and be cached in the browser repository
5 |
6 | Browser.Library = 'SimCoJLink';
7 | % 'mylib' is the name of the library
8 |
9 | Browser.Name = 'SimCoJLink';
10 | % 'My Library' is the library name that appears
11 | % in the Library Browser
12 |
13 | blkStruct.Browser = Browser;
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/SimCoJLink使用说明.pdf:
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https://raw.githubusercontent.com/jiafan1949/SimCoJLink/62fcea8b79075927edc732b7662d8b72725e89fb/SimCoJLink使用说明.pdf
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