├── README.md ├── ZYBO_RM_B_V6.pdf ├── devicetree ├── devicetree.dtb ├── pl.dtsi ├── skeleton.dtsi ├── system.dts └── zynq-7000.dtsi ├── hardware_pro └── workshop_v1_0 │ ├── hw.xdc │ ├── ip_repo │ ├── MatrixMult_v1.0 │ │ ├── autoimpl.log │ │ ├── auxiliary.xml │ │ ├── bd │ │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── constraints │ │ │ └── mmult_accel_core_ooc.xdc │ │ ├── doc │ │ │ └── ReleaseNotes.txt │ │ ├── drivers │ │ │ └── mmult_accel_core_top_v1_0 │ │ │ │ ├── data │ │ │ │ ├── mmult_accel_core_top.mdd │ │ │ │ └── mmult_accel_core_top.tcl │ │ │ │ └── src │ │ │ │ ├── Makefile │ │ │ │ ├── xmmult_accel_core.c │ │ │ │ ├── xmmult_accel_core.h │ │ │ │ ├── xmmult_accel_core_hw.h │ │ │ │ ├── xmmult_accel_core_linux.c │ │ │ │ └── xmmult_accel_core_sinit.c │ │ ├── example │ │ │ ├── ipi_example.bat │ │ │ └── ipi_example.tcl │ │ ├── hdl │ │ │ ├── ip │ │ │ │ ├── mmult_accel_core_ap_fadd_3_full_dsp.vhd │ │ │ │ └── mmult_accel_core_ap_fmul_2_max_dsp.vhd │ │ │ └── verilog │ │ │ │ ├── mmult_accel_core.v │ │ │ │ ├── mmult_accel_core_CONTROL_BUS_if.v │ │ │ │ ├── mmult_accel_core_INPUT_STREAM_if.v │ │ │ │ ├── mmult_accel_core_OUTPUT_STREAM_if.v │ │ │ │ ├── mmult_accel_core_ap_rst_if.v │ │ │ │ ├── mmult_accel_core_dut_mmult_accel_core_float_16_256_4_5_5_s.v │ │ │ │ ├── mmult_accel_core_dut_mmult_accel_core_float_16_256_4_5_5_s_a_0_1.v │ │ │ │ ├── mmult_accel_core_dut_mmult_accel_core_float_16_256_4_5_5_s_out.v │ │ │ │ ├── mmult_accel_core_fadd_32ns_32ns_32_5_full_dsp.v │ │ │ │ ├── mmult_accel_core_fmul_32ns_32ns_32_4_max_dsp.v │ │ │ │ ├── mmult_accel_core_matrix_multiply_hw_float_16_s.v │ │ │ │ ├── mmult_accel_core_pop_stream_float_4_5_5_s.v │ │ │ │ ├── mmult_accel_core_push_stream_float_4_5_5_s.v │ │ │ │ └── mmult_accel_core_top.v │ │ ├── misc │ │ │ └── logo.png │ │ ├── pack.bat │ │ ├── run_ippack.tcl │ │ ├── subcore │ │ │ ├── mmult_accel_core_ap_fadd_3_full_dsp_ip.tcl │ │ │ └── mmult_accel_core_ap_fmul_2_max_dsp_ip.tcl │ │ ├── tmp.srcs │ │ │ └── sources_1 │ │ │ │ └── ip │ │ │ │ ├── mmult_accel_core_ap_fadd_3_full_dsp │ │ │ │ ├── axi_utils_v2_0 │ │ │ │ │ └── hdl │ │ │ │ │ │ ├── axi_slave_2to1.vhd │ │ │ │ │ │ ├── axi_slave_3to1.vhd │ │ │ │ │ │ ├── axi_slave_4to1.vhd │ │ │ │ │ │ ├── axi_utils_comps.vhd │ │ │ │ │ │ ├── axi_utils_v2_0_pkg.vhd │ │ │ │ │ │ ├── glb_ifx_master.vhd │ │ │ │ │ │ ├── glb_ifx_slave.vhd │ │ │ │ │ │ ├── glb_srl_fifo.vhd │ │ │ │ │ │ └── global_util_pkg.vhd │ │ │ │ ├── floating_point_v7_0 │ │ │ │ │ └── hdl │ │ │ │ │ │ ├── fix_to_flt_conv │ │ │ │ │ │ ├── fix_to_flt_conv.vhd │ │ │ │ │ │ └── fix_to_flt_conv_exp.vhd │ │ │ │ │ │ ├── floating_point_v7_0.vhd │ │ │ │ │ │ ├── floating_point_v7_0_comp.vhd │ │ │ │ │ │ ├── floating_point_v7_0_consts.vhd │ │ │ │ │ │ ├── floating_point_v7_0_pkg.vhd │ │ │ │ │ │ ├── floating_point_v7_0_table_pkg.vhd │ │ │ │ │ │ ├── floating_point_v7_0_viv.vhd │ │ │ │ │ │ ├── floating_point_v7_0_viv_comp.vhd │ │ │ │ │ │ ├── flt_accum │ │ │ │ │ │ ├── flt_accum.vhd │ │ │ │ │ │ ├── flt_accum_bit_encode.vhd │ │ │ │ │ │ └── flt_accum_flt_to_fix.vhd │ │ │ │ │ │ ├── flt_add │ │ │ │ │ │ ├── flt_add.vhd │ │ │ │ │ │ ├── flt_add_dsp.vhd │ │ │ │ │ │ ├── flt_add_exp.vhd │ │ │ │ │ │ ├── flt_add_lat.vhd │ │ │ │ │ │ ├── flt_add_lat_align_add.vhd │ │ │ │ │ │ ├── flt_add_lat_exp.vhd │ │ │ │ │ │ ├── flt_add_lat_norm.vhd │ │ │ │ │ │ └── flt_add_logic.vhd │ │ │ │ │ │ ├── flt_cmp │ │ │ │ │ │ └── flt_cmp.vhd │ │ │ │ │ │ ├── flt_div │ │ │ │ │ │ ├── flt_div.vhd │ │ │ │ │ │ ├── flt_div_exp.vhd │ │ │ │ │ │ ├── flt_div_mant.vhd │ │ │ │ │ │ └── flt_div_mant_addsub.vhd │ │ │ │ │ │ ├── flt_exp │ │ │ │ │ │ ├── floating_point_v7_0_exp_table_pkg.vhd │ │ │ │ │ │ ├── flt_exp.vhd │ │ │ │ │ │ ├── flt_exp_ccm.vhd │ │ │ │ │ │ ├── flt_exp_dp_poly.vhd │ │ │ │ │ │ ├── flt_exp_e2A.vhd │ │ │ │ │ │ ├── flt_exp_e2zmzm1.vhd │ │ │ │ │ │ ├── flt_exp_recomb.vhd │ │ │ │ │ │ └── flt_exp_specialcase.vhd │ │ │ │ │ │ ├── flt_fma │ │ │ │ │ │ ├── flt_fma.vhd │ │ │ │ │ │ ├── flt_fma_add.vhd │ │ │ │ │ │ ├── flt_fma_add_exp.vhd │ │ │ │ │ │ ├── flt_fma_add_logic.vhd │ │ │ │ │ │ ├── flt_fma_addsub.vhd │ │ │ │ │ │ ├── flt_fma_addsub_dsp1.vhd │ │ │ │ │ │ ├── flt_fma_addsub_dsp2.vhd │ │ │ │ │ │ ├── flt_fma_align_add.vhd │ │ │ │ │ │ ├── flt_fma_alignment.vhd │ │ │ │ │ │ ├── flt_fma_mul.vhd │ │ │ │ │ │ ├── flt_fma_norm_logic.vhd │ │ │ │ │ │ ├── flt_fma_renorm_and_round_logic.vhd │ │ │ │ │ │ ├── flt_fma_round_bit.vhd │ │ │ │ │ │ ├── flt_fma_special_detect.vhd │ │ │ │ │ │ └── flt_fma_specialcase.vhd │ │ │ │ │ │ ├── flt_log │ │ │ │ │ │ ├── flt_log.vhd │ │ │ │ │ │ ├── flt_log_L_block.vhd │ │ │ │ │ │ ├── flt_log_L_block_pkg.vhd │ │ │ │ │ │ ├── flt_log_L_memory.vhd │ │ │ │ │ │ ├── flt_log_addsub.vhd │ │ │ │ │ │ ├── flt_log_addsub_taylor_combiner_fabric.vhd │ │ │ │ │ │ ├── flt_log_addsub_taylor_fabric.vhd │ │ │ │ │ │ ├── flt_log_exp.vhd │ │ │ │ │ │ ├── flt_log_inproc.vhd │ │ │ │ │ │ ├── flt_log_lead_zero_encode.vhd │ │ │ │ │ │ ├── flt_log_norm.vhd │ │ │ │ │ │ ├── flt_log_normalize.vhd │ │ │ │ │ │ ├── flt_log_recomb.vhd │ │ │ │ │ │ ├── flt_log_rnd.vhd │ │ │ │ │ │ ├── flt_log_rr.vhd │ │ │ │ │ │ ├── flt_log_rr_mul.vhd │ │ │ │ │ │ ├── flt_log_rr_mul_iter.vhd │ │ │ │ │ │ ├── flt_log_shift_msb_first.vhd │ │ │ │ │ │ ├── flt_log_single_one_detect.vhd │ │ │ │ │ │ ├── flt_log_specialcase.vhd │ │ │ │ │ │ └── flt_log_taylor.vhd │ │ │ │ │ │ ├── flt_mult │ │ │ │ │ │ ├── fix_mult │ │ │ │ │ │ │ ├── fix_mult.vhd │ │ │ │ │ │ │ ├── fix_mult_dsp48e1_dbl.vhd │ │ │ │ │ │ │ ├── fix_mult_dsp48e1_lat_dbl.vhd │ │ │ │ │ │ │ ├── fix_mult_dsp48e1_sgl.vhd │ │ │ │ │ │ │ ├── fix_mult_dsp48e2_dbl.vhd │ │ │ │ │ │ │ ├── fix_mult_qq.vhd │ │ │ │ │ │ │ └── fix_mult_xx.vhd │ │ │ │ │ │ ├── flt_mult.vhd │ │ │ │ │ │ ├── flt_mult_exp.vhd │ │ │ │ │ │ └── flt_mult_round │ │ │ │ │ │ │ ├── flt_mult_round.vhd │ │ │ │ │ │ │ ├── flt_round_dsp_opt_full.vhd │ │ │ │ │ │ │ └── flt_round_dsp_opt_part.vhd │ │ │ │ │ │ ├── flt_recip │ │ │ │ │ │ ├── flt_recip.vhd │ │ │ │ │ │ ├── flt_recip_approx.vhd │ │ │ │ │ │ ├── flt_recip_eval.vhd │ │ │ │ │ │ ├── flt_recip_nr.vhd │ │ │ │ │ │ ├── flt_recip_postprocess.vhd │ │ │ │ │ │ ├── flt_recip_recomb.vhd │ │ │ │ │ │ ├── flt_recip_reduction_calc.vhd │ │ │ │ │ │ ├── flt_recip_specialcase.vhd │ │ │ │ │ │ ├── flt_recipsqrt_dp_m_calc.vhd │ │ │ │ │ │ ├── flt_recipsqrt_dp_recsqrt_r_rom.vhd │ │ │ │ │ │ └── flt_recipsqrt_sp_sqrt_r_rom.vhd │ │ │ │ │ │ ├── flt_sqrt │ │ │ │ │ │ ├── flt_sqrt.vhd │ │ │ │ │ │ ├── flt_sqrt_exp.vhd │ │ │ │ │ │ ├── flt_sqrt_mant.vhd │ │ │ │ │ │ └── flt_sqrt_mant_addsub.vhd │ │ │ │ │ │ ├── flt_to_fix_conv │ │ │ │ │ │ └── flt_to_fix_conv.vhd │ │ │ │ │ │ ├── flt_to_flt_conv │ │ │ │ │ │ ├── flt_to_flt_conv.vhd │ │ │ │ │ │ └── flt_to_flt_conv_exp.vhd │ │ │ │ │ │ ├── shared │ │ │ │ │ │ ├── addsub.vhd │ │ │ │ │ │ ├── addsub_dsp.vhd │ │ │ │ │ │ ├── addsub_logic.vhd │ │ │ │ │ │ ├── align_add.vhd │ │ │ │ │ │ ├── align_add_dsp48e1_sgl.vhd │ │ │ │ │ │ ├── alignment.vhd │ │ │ │ │ │ ├── carry_chain.vhd │ │ │ │ │ │ ├── compare.vhd │ │ │ │ │ │ ├── compare_eq.vhd │ │ │ │ │ │ ├── compare_eq_im.vhd │ │ │ │ │ │ ├── compare_ge.vhd │ │ │ │ │ │ ├── compare_gt.vhd │ │ │ │ │ │ ├── compare_ne_im.vhd │ │ │ │ │ │ ├── delay.vhd │ │ │ │ │ │ ├── dsp48e1_wrapper.vhd │ │ │ │ │ │ ├── dsp48e2_wrapper.vhd │ │ │ │ │ │ ├── flt_dec_op.vhd │ │ │ │ │ │ ├── flt_dec_op_lat.vhd │ │ │ │ │ │ ├── flt_round_bit.vhd │ │ │ │ │ │ ├── flt_utils.vhd │ │ │ │ │ │ ├── lead_zero_encode.vhd │ │ │ │ │ │ ├── lead_zero_encode_shift.vhd │ │ │ │ │ │ ├── multadd.vhd │ │ │ │ │ │ ├── mux4.vhd │ │ │ │ │ │ ├── mux_bus2.vhd │ │ │ │ │ │ ├── norm_and_round_dsp48e1_sgl.vhd │ │ │ │ │ │ ├── norm_and_round_logic.vhd │ │ │ │ │ │ ├── norm_zero_det.vhd │ │ │ │ │ │ ├── normalize.vhd │ │ │ │ │ │ ├── renorm_and_round_logic.vhd │ │ │ │ │ │ ├── shift_msb_first.vhd │ │ │ │ │ │ ├── special_detect.vhd │ │ │ │ │ │ ├── twos_comp.vhd │ │ │ │ │ │ └── zero_det_sel.vhd │ │ │ │ │ │ ├── vm2 │ │ │ │ │ │ ├── dsp48Mult.vhd │ │ │ │ │ │ ├── dsp48MultALine.vhd │ │ │ │ │ │ ├── vm2Arch.vhd │ │ │ │ │ │ ├── vm2Comps.vhd │ │ │ │ │ │ ├── vm2Utils.vhd │ │ │ │ │ │ ├── vmsMultCore.vhd │ │ │ │ │ │ └── xMult.vhd │ │ │ │ │ │ └── vt2m │ │ │ │ │ │ ├── vt2mArch.vhd │ │ │ │ │ │ ├── vt2mComps.vhd │ │ │ │ │ │ └── vt2mUtils.vhd │ │ │ │ ├── mmult_accel_core_ap_fadd_3_full_dsp.xci │ │ │ │ ├── mmult_accel_core_ap_fadd_3_full_dsp.xml │ │ │ │ ├── mmult_accel_core_ap_fadd_3_full_dsp_ooc.xdc │ │ │ │ ├── mult_gen_v12_0 │ │ │ │ │ └── hdl │ │ │ │ │ │ ├── cc_compare.vhd │ │ │ │ │ │ ├── ccm.vhd │ │ │ │ │ │ ├── ccm_dist_mem.vhd │ │ │ │ │ │ ├── ccm_dp_block_mem.vhd │ │ │ │ │ │ ├── ccm_operation.vhd │ │ │ │ │ │ ├── ccm_scaled_adder.vhd │ │ │ │ │ │ ├── ccm_sp_block_mem.vhd │ │ │ │ │ │ ├── ccm_syncmem.vhd │ │ │ │ │ │ ├── delay_line.vhd │ │ │ │ │ │ ├── dsp.vhd │ │ │ │ │ │ ├── dsp_pkg.vhd │ │ │ │ │ │ ├── hybrid.vhd │ │ │ │ │ │ ├── luts.vhd │ │ │ │ │ │ ├── mult18.vhd │ │ │ │ │ │ ├── multMxN_lut6.vhd │ │ │ │ │ │ ├── mult_gen_v12_0.vhd │ │ │ │ │ │ ├── mult_gen_v12_0_comp.vhd │ │ │ │ │ │ ├── mult_gen_v12_0_pkg.vhd │ │ │ │ │ │ ├── mult_gen_v12_0_viv.vhd │ │ │ │ │ │ ├── mult_gen_v12_0_viv_comp.vhd │ │ │ │ │ │ ├── op_resize.vhd │ │ │ │ │ │ └── three_input_adder.vhd │ │ │ │ ├── sim │ │ │ │ │ └── mmult_accel_core_ap_fadd_3_full_dsp.vhd │ │ │ │ ├── synth │ │ │ │ │ └── mmult_accel_core_ap_fadd_3_full_dsp.vhd │ │ │ │ ├── xbip_bram18k_v3_0 │ │ │ │ │ └── hdl │ │ │ │ │ │ ├── xbip_bram18k_hdl_pkg.vhd │ │ │ │ │ │ ├── xbip_bram18k_rtl.vhd │ │ │ │ │ │ ├── xbip_bram18k_synth.vhd │ │ │ │ │ │ ├── xbip_bram18k_v3_0.vhd │ │ │ │ │ │ ├── xbip_bram18k_v3_0_pkg.vhd │ │ │ │ │ │ ├── xbip_bram18k_v3_0_viv.vhd │ │ │ │ │ │ └── xbip_bram18k_v3_0_viv_comp.vhd │ │ │ │ ├── xbip_dsp48_addsub_v3_0 │ │ │ │ │ └── hdl │ │ │ │ │ │ ├── xbip_dsp48_addsub_rtl.vhd │ │ │ │ │ │ ├── xbip_dsp48_addsub_synth.vhd │ │ │ │ │ │ ├── xbip_dsp48_addsub_v3_0.vhd │ │ │ │ │ │ ├── xbip_dsp48_addsub_v3_0_comp.vhd │ │ │ │ │ │ ├── xbip_dsp48_addsub_v3_0_pkg.vhd │ │ │ │ │ │ ├── xbip_dsp48_addsub_v3_0_viv.vhd │ │ │ │ │ │ └── xbip_dsp48_addsub_v3_0_viv_comp.vhd │ │ │ │ ├── xbip_dsp48_wrapper_v3_0 │ │ │ │ │ └── hdl │ │ │ │ │ │ ├── xbip_dsp48_wrapper_v3_0.vhd │ │ │ │ │ │ ├── xbip_dsp48_wrapper_v3_0_pkg.vhd │ │ │ │ │ │ ├── xbip_dsp48a1_wrapper_v3_0.vhd │ │ │ │ │ │ ├── xbip_dsp48a_wrapper_v3_0.vhd │ │ │ │ │ │ ├── xbip_dsp48e1_wrapper_v3_0.vhd │ │ │ │ │ │ ├── xbip_dsp48e2_wrapper_v3_0.vhd │ │ │ │ │ │ └── xbip_dsp48e_wrapper_v3_0.vhd │ │ │ │ ├── xbip_pipe_v3_0 │ │ │ │ │ └── hdl │ │ │ │ │ │ ├── xbip_pipe_v3_0.vhd │ │ │ │ │ │ ├── xbip_pipe_v3_0_comp.vhd │ │ │ │ │ │ ├── xbip_pipe_v3_0_viv.vhd │ │ │ │ │ │ └── xbip_pipe_v3_0_viv_comp.vhd │ │ │ │ └── xbip_utils_v3_0 │ │ │ │ │ └── hdl │ │ │ │ │ ├── xbip_utils_v3_0_pkg.vhd │ │ │ │ │ └── xcc_utils_v3_0.vhd │ │ │ │ └── mmult_accel_core_ap_fmul_2_max_dsp │ │ │ │ ├── axi_utils_v2_0 │ │ │ │ └── hdl │ │ │ │ │ ├── axi_slave_2to1.vhd │ │ │ │ │ ├── axi_slave_3to1.vhd │ │ │ │ │ ├── axi_slave_4to1.vhd │ │ │ │ │ ├── axi_utils_comps.vhd │ │ │ │ │ ├── axi_utils_v2_0_pkg.vhd │ │ │ │ │ ├── glb_ifx_master.vhd │ │ │ │ │ ├── glb_ifx_slave.vhd │ │ │ │ │ ├── glb_srl_fifo.vhd │ │ │ │ │ └── global_util_pkg.vhd │ │ │ │ ├── floating_point_v7_0 │ │ │ │ └── hdl │ │ │ │ │ ├── fix_to_flt_conv │ │ │ │ │ ├── fix_to_flt_conv.vhd │ │ │ │ │ └── fix_to_flt_conv_exp.vhd │ │ │ │ │ ├── floating_point_v7_0.vhd │ │ │ │ │ ├── floating_point_v7_0_comp.vhd │ │ │ │ │ ├── floating_point_v7_0_consts.vhd │ │ │ │ │ ├── floating_point_v7_0_pkg.vhd │ │ │ │ │ ├── floating_point_v7_0_table_pkg.vhd │ │ │ │ │ ├── floating_point_v7_0_viv.vhd │ │ │ │ │ ├── floating_point_v7_0_viv_comp.vhd │ │ │ │ │ ├── flt_accum │ │ │ │ │ ├── flt_accum.vhd │ │ │ │ │ ├── flt_accum_bit_encode.vhd │ │ │ │ │ └── flt_accum_flt_to_fix.vhd │ │ │ │ │ ├── flt_add │ │ │ │ │ ├── flt_add.vhd │ │ │ │ │ ├── flt_add_dsp.vhd │ │ │ │ │ ├── flt_add_exp.vhd │ │ │ │ │ ├── flt_add_lat.vhd │ │ │ │ │ ├── flt_add_lat_align_add.vhd │ │ │ │ │ ├── flt_add_lat_exp.vhd │ │ │ │ │ ├── flt_add_lat_norm.vhd │ │ │ │ │ └── flt_add_logic.vhd │ │ │ │ │ ├── flt_cmp │ │ │ │ │ └── flt_cmp.vhd │ │ │ │ │ ├── flt_div │ │ │ │ │ ├── flt_div.vhd │ │ │ │ │ ├── flt_div_exp.vhd │ │ │ │ │ ├── flt_div_mant.vhd │ │ │ │ │ └── flt_div_mant_addsub.vhd │ │ │ │ │ ├── flt_exp │ │ │ │ │ ├── floating_point_v7_0_exp_table_pkg.vhd │ │ │ │ │ ├── flt_exp.vhd │ │ │ │ │ ├── flt_exp_ccm.vhd │ │ │ │ │ ├── flt_exp_dp_poly.vhd │ │ │ │ │ ├── flt_exp_e2A.vhd │ │ │ │ │ ├── flt_exp_e2zmzm1.vhd │ │ │ │ │ ├── flt_exp_recomb.vhd │ │ │ │ │ └── flt_exp_specialcase.vhd │ │ │ │ │ ├── flt_fma │ │ │ │ │ ├── flt_fma.vhd │ │ │ │ │ ├── flt_fma_add.vhd │ │ │ │ │ ├── flt_fma_add_exp.vhd │ │ │ │ │ ├── flt_fma_add_logic.vhd │ │ │ │ │ ├── flt_fma_addsub.vhd │ │ │ │ │ ├── flt_fma_addsub_dsp1.vhd │ │ │ │ │ ├── flt_fma_addsub_dsp2.vhd │ │ │ │ │ ├── flt_fma_align_add.vhd │ │ │ │ │ ├── flt_fma_alignment.vhd │ │ │ │ │ ├── flt_fma_mul.vhd │ │ │ │ │ ├── flt_fma_norm_logic.vhd │ │ │ │ │ ├── flt_fma_renorm_and_round_logic.vhd │ │ │ │ │ ├── flt_fma_round_bit.vhd │ │ │ │ │ ├── flt_fma_special_detect.vhd │ │ │ │ │ └── flt_fma_specialcase.vhd │ │ │ │ │ ├── flt_log │ │ │ │ │ ├── flt_log.vhd │ │ │ │ │ ├── flt_log_L_block.vhd │ │ │ │ │ ├── flt_log_L_block_pkg.vhd │ │ │ │ │ ├── flt_log_L_memory.vhd │ │ │ │ │ ├── flt_log_addsub.vhd │ │ │ │ │ ├── flt_log_addsub_taylor_combiner_fabric.vhd │ │ │ │ │ ├── flt_log_addsub_taylor_fabric.vhd │ │ │ │ │ ├── flt_log_exp.vhd │ │ │ │ │ ├── flt_log_inproc.vhd │ │ │ │ │ ├── flt_log_lead_zero_encode.vhd │ │ │ │ │ ├── flt_log_norm.vhd │ │ │ │ │ ├── flt_log_normalize.vhd │ │ │ │ │ ├── flt_log_recomb.vhd │ │ │ │ │ ├── flt_log_rnd.vhd │ │ │ │ │ ├── flt_log_rr.vhd │ │ │ │ │ ├── flt_log_rr_mul.vhd │ │ │ │ │ ├── flt_log_rr_mul_iter.vhd │ │ │ │ │ ├── flt_log_shift_msb_first.vhd │ │ │ │ │ ├── flt_log_single_one_detect.vhd │ │ │ │ │ ├── flt_log_specialcase.vhd │ │ │ │ │ └── flt_log_taylor.vhd │ │ │ │ │ ├── flt_mult │ │ │ │ │ ├── fix_mult │ │ │ │ │ │ ├── fix_mult.vhd │ │ │ │ │ │ ├── fix_mult_dsp48e1_dbl.vhd │ │ │ │ │ │ ├── fix_mult_dsp48e1_lat_dbl.vhd │ │ │ │ │ │ ├── fix_mult_dsp48e1_sgl.vhd │ │ │ │ │ │ ├── fix_mult_dsp48e2_dbl.vhd │ │ │ │ │ │ ├── fix_mult_qq.vhd │ │ │ │ │ │ └── fix_mult_xx.vhd │ │ │ │ │ ├── flt_mult.vhd │ │ │ │ │ ├── flt_mult_exp.vhd │ │ │ │ │ └── flt_mult_round │ │ │ │ │ │ ├── flt_mult_round.vhd │ │ │ │ │ │ ├── flt_round_dsp_opt_full.vhd │ │ │ │ │ │ └── flt_round_dsp_opt_part.vhd │ │ │ │ │ ├── flt_recip │ │ │ │ │ ├── flt_recip.vhd │ │ │ │ │ ├── flt_recip_approx.vhd │ │ │ │ │ ├── flt_recip_eval.vhd │ │ │ │ │ ├── flt_recip_nr.vhd │ │ │ │ │ ├── flt_recip_postprocess.vhd │ │ │ │ │ ├── flt_recip_recomb.vhd │ │ │ │ │ ├── flt_recip_reduction_calc.vhd │ │ │ │ │ ├── flt_recip_specialcase.vhd │ │ │ │ │ ├── flt_recipsqrt_dp_m_calc.vhd │ │ │ │ │ ├── flt_recipsqrt_dp_recsqrt_r_rom.vhd │ │ │ │ │ └── flt_recipsqrt_sp_sqrt_r_rom.vhd │ │ │ │ │ ├── flt_sqrt │ │ │ │ │ ├── flt_sqrt.vhd │ │ │ │ │ ├── flt_sqrt_exp.vhd │ │ │ │ │ ├── flt_sqrt_mant.vhd │ │ │ │ │ └── flt_sqrt_mant_addsub.vhd │ │ │ │ │ ├── flt_to_fix_conv │ │ │ │ │ └── flt_to_fix_conv.vhd │ │ │ │ │ ├── flt_to_flt_conv │ │ │ │ │ ├── flt_to_flt_conv.vhd │ │ │ │ │ └── flt_to_flt_conv_exp.vhd │ │ │ │ │ ├── shared │ │ │ │ │ ├── addsub.vhd │ │ │ │ │ ├── addsub_dsp.vhd │ │ │ │ │ ├── addsub_logic.vhd │ │ │ │ │ ├── align_add.vhd │ │ │ │ │ ├── align_add_dsp48e1_sgl.vhd │ │ │ │ │ ├── alignment.vhd │ │ │ │ │ ├── carry_chain.vhd │ │ │ │ │ ├── compare.vhd │ │ │ │ │ ├── compare_eq.vhd │ │ │ │ │ ├── compare_eq_im.vhd │ │ │ │ │ ├── compare_ge.vhd │ │ │ │ │ ├── compare_gt.vhd │ │ │ │ │ ├── compare_ne_im.vhd │ │ │ │ │ ├── delay.vhd │ │ │ │ │ ├── dsp48e1_wrapper.vhd │ │ │ │ │ ├── dsp48e2_wrapper.vhd │ │ │ │ │ ├── flt_dec_op.vhd │ │ │ │ │ ├── flt_dec_op_lat.vhd │ │ │ │ │ ├── flt_round_bit.vhd │ │ │ │ │ ├── flt_utils.vhd │ │ │ │ │ ├── lead_zero_encode.vhd │ │ │ │ │ ├── lead_zero_encode_shift.vhd │ │ │ │ │ ├── multadd.vhd │ │ │ │ │ ├── mux4.vhd │ │ │ │ │ ├── mux_bus2.vhd │ │ │ │ │ ├── norm_and_round_dsp48e1_sgl.vhd │ │ │ │ │ ├── norm_and_round_logic.vhd │ │ │ │ │ ├── norm_zero_det.vhd │ │ │ │ │ ├── normalize.vhd │ │ │ │ │ ├── renorm_and_round_logic.vhd │ │ │ │ │ ├── shift_msb_first.vhd │ │ │ │ │ ├── special_detect.vhd │ │ │ │ │ ├── twos_comp.vhd │ │ │ │ │ └── zero_det_sel.vhd │ │ │ │ │ ├── vm2 │ │ │ │ │ ├── dsp48Mult.vhd │ │ │ │ │ ├── dsp48MultALine.vhd │ │ │ │ │ ├── vm2Arch.vhd │ │ │ │ │ ├── vm2Comps.vhd │ │ │ │ │ ├── vm2Utils.vhd │ │ │ │ │ ├── vmsMultCore.vhd │ │ │ │ │ └── xMult.vhd │ │ │ │ │ └── vt2m │ │ │ │ │ ├── vt2mArch.vhd │ │ │ │ │ ├── vt2mComps.vhd │ │ │ │ │ └── vt2mUtils.vhd │ │ │ │ ├── mmult_accel_core_ap_fmul_2_max_dsp.xci │ │ │ │ ├── mmult_accel_core_ap_fmul_2_max_dsp.xml │ │ │ │ ├── mmult_accel_core_ap_fmul_2_max_dsp_ooc.xdc │ │ │ │ ├── mult_gen_v12_0 │ │ │ │ └── hdl │ │ │ │ │ ├── cc_compare.vhd │ │ │ │ │ ├── ccm.vhd │ │ │ │ │ ├── ccm_dist_mem.vhd │ │ │ │ │ ├── ccm_dp_block_mem.vhd │ │ │ │ │ ├── ccm_operation.vhd │ │ │ │ │ ├── ccm_scaled_adder.vhd │ │ │ │ │ ├── ccm_sp_block_mem.vhd │ │ │ │ │ ├── ccm_syncmem.vhd │ │ │ │ │ ├── delay_line.vhd │ │ │ │ │ ├── dsp.vhd │ │ │ │ │ ├── dsp_pkg.vhd │ │ │ │ │ ├── hybrid.vhd │ │ │ │ │ ├── luts.vhd │ │ │ │ │ ├── mult18.vhd │ │ │ │ │ ├── multMxN_lut6.vhd │ │ │ │ │ ├── mult_gen_v12_0.vhd │ │ │ │ │ ├── mult_gen_v12_0_comp.vhd │ │ │ │ │ ├── mult_gen_v12_0_pkg.vhd │ │ │ │ │ ├── mult_gen_v12_0_viv.vhd │ │ │ │ │ ├── mult_gen_v12_0_viv_comp.vhd │ │ │ │ │ ├── op_resize.vhd │ │ │ │ │ └── three_input_adder.vhd │ │ │ │ ├── sim │ │ │ │ └── mmult_accel_core_ap_fmul_2_max_dsp.vhd │ │ │ │ ├── synth │ │ │ │ └── mmult_accel_core_ap_fmul_2_max_dsp.vhd │ │ │ │ ├── xbip_bram18k_v3_0 │ │ │ │ └── hdl │ │ │ │ │ ├── xbip_bram18k_hdl_pkg.vhd │ │ │ │ │ ├── xbip_bram18k_rtl.vhd │ │ │ │ │ ├── xbip_bram18k_synth.vhd │ │ │ │ │ ├── xbip_bram18k_v3_0.vhd │ │ │ │ │ ├── xbip_bram18k_v3_0_pkg.vhd │ │ │ │ │ ├── xbip_bram18k_v3_0_viv.vhd │ │ │ │ │ └── xbip_bram18k_v3_0_viv_comp.vhd │ │ │ │ ├── xbip_dsp48_addsub_v3_0 │ │ │ │ └── hdl │ │ │ │ │ ├── xbip_dsp48_addsub_rtl.vhd │ │ │ │ │ ├── xbip_dsp48_addsub_synth.vhd │ │ │ │ │ ├── xbip_dsp48_addsub_v3_0.vhd │ │ │ │ │ ├── xbip_dsp48_addsub_v3_0_comp.vhd │ │ │ │ │ ├── xbip_dsp48_addsub_v3_0_pkg.vhd │ │ │ │ │ ├── xbip_dsp48_addsub_v3_0_viv.vhd │ │ │ │ │ └── xbip_dsp48_addsub_v3_0_viv_comp.vhd │ │ │ │ ├── xbip_dsp48_wrapper_v3_0 │ │ │ │ └── hdl │ │ │ │ │ ├── xbip_dsp48_wrapper_v3_0.vhd │ │ │ │ │ ├── xbip_dsp48_wrapper_v3_0_pkg.vhd │ │ │ │ │ ├── xbip_dsp48a1_wrapper_v3_0.vhd │ │ │ │ │ ├── xbip_dsp48a_wrapper_v3_0.vhd │ │ │ │ │ ├── xbip_dsp48e1_wrapper_v3_0.vhd │ │ │ │ │ ├── xbip_dsp48e2_wrapper_v3_0.vhd │ │ │ │ │ └── xbip_dsp48e_wrapper_v3_0.vhd │ │ │ │ ├── xbip_pipe_v3_0 │ │ │ │ └── hdl │ │ │ │ │ ├── xbip_pipe_v3_0.vhd │ │ │ │ │ ├── xbip_pipe_v3_0_comp.vhd │ │ │ │ │ ├── xbip_pipe_v3_0_viv.vhd │ │ │ │ │ └── xbip_pipe_v3_0_viv_comp.vhd │ │ │ │ └── xbip_utils_v3_0 │ │ │ │ └── hdl │ │ │ │ ├── xbip_utils_v3_0_pkg.vhd │ │ │ │ └── xcc_utils_v3_0.vhd │ │ ├── tmp.xpr │ │ ├── vivado.jou │ │ ├── vivado.log │ │ ├── xgui │ │ │ └── mmult_accel_core_v1_0.tcl │ │ └── xilinx_com_hls_mmult_accel_core_1_0.zip │ ├── axi_pwm_4ch_1.0 │ │ ├── axi_pwm_4ch_v1_0_project │ │ │ ├── axi_pwm_4ch_v1_0_project.cache │ │ │ │ └── wt │ │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ │ └── webtalk_pa.xml │ │ │ └── axi_pwm_4ch_v1_0_project.xpr │ │ ├── axi_pwm_4ch_v1_0_v1_0_project │ │ │ ├── axi_pwm_4ch_v1_0_v1_0_project.cache │ │ │ │ └── wt │ │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ │ └── webtalk_pa.xml │ │ │ └── axi_pwm_4ch_v1_0_v1_0_project.xpr │ │ └── example_designs │ │ │ ├── bfm_design │ │ │ ├── axi_pwm_4ch_v1_0_tb.v │ │ │ └── design.tcl │ │ │ └── debug_hw_design │ │ │ ├── axi_pwm_4ch_v1_0_hw_test.tcl │ │ │ └── design.tcl │ ├── axi_pwm_6ch_1.0 │ │ ├── axi_pwm_6ch_v1_0_project │ │ │ ├── axi_pwm_6ch_v1_0_project.cache │ │ │ │ └── wt │ │ │ │ │ ├── java_command_handlers.wdf │ │ │ │ │ └── webtalk_pa.xml │ │ │ └── axi_pwm_6ch_v1_0_project.xpr │ │ ├── bd │ │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── drivers │ │ │ └── axi_pwm_6ch_v1_0 │ │ │ │ ├── data │ │ │ │ ├── axi_pwm_6ch.mdd │ │ │ │ └── axi_pwm_6ch.tcl │ │ │ │ └── src │ │ │ │ ├── Makefile │ │ │ │ ├── axi_pwm_6ch.c │ │ │ │ ├── axi_pwm_6ch.h │ │ │ │ └── axi_pwm_6ch_selftest.c │ │ ├── example_designs │ │ │ ├── bfm_design │ │ │ │ ├── axi_pwm_6ch_v1_0_tb.v │ │ │ │ └── design.tcl │ │ │ └── debug_hw_design │ │ │ │ ├── axi_pwm_6ch_v1_0_hw_test.tcl │ │ │ │ └── design.tcl │ │ ├── hdl │ │ │ ├── axi_pwm_6ch_v1_0.v │ │ │ └── axi_pwm_6ch_v1_0_S00_AXI.v │ │ └── xgui │ │ │ └── axi_pwm_6ch_v1_0.tcl │ ├── xilinx.com_xup_Quadrature_Encoder_IP_v1_0_1.0 │ │ ├── component.xml │ │ ├── imports │ │ │ └── hdl │ │ │ │ ├── Quadrature_Encoder_IP_v1_0.v │ │ │ │ └── Quadrature_Encoder_IP_v1_0_S00_AXI.v │ │ ├── new │ │ │ ├── motor_control.v │ │ │ └── speed_dir_measure.v │ │ └── xgui │ │ │ └── Quadrature_Encoder_IP_v1_0_v1_0.tcl │ ├── xilinx.com_xup_Ultrasonic_ip_v1_0_1.0.zip │ └── xilinx.com_xup_Ultrasonic_ip_v1_0_1.0 │ │ ├── component.xml │ │ ├── imports │ │ └── hdl │ │ │ ├── Ultrasonic_ip_v1_0.v │ │ │ └── Ultrasonic_ip_v1_0_S00_AXI.v │ │ ├── new │ │ └── ultrasonic.v │ │ └── xgui │ │ └── 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