├── .gitattributes ├── src ├── main.c ├── DAP │ ├── DAP.c │ └── debug_cm.h ├── SWD_flash.c ├── SWD_host.c ├── DAP_config.h ├── algo │ ├── STM32F10x_128.c │ ├── flash_blob.h │ └── STM32F4xx_1024.c ├── CSL │ ├── CMSIS │ │ ├── DeviceSupport │ │ │ ├── stm32f10x.h │ │ │ ├── system_stm32f10x.h │ │ │ └── startup │ │ │ │ └── gcc │ │ │ │ ├── startup_stm32f10x_ld.s │ │ │ │ └── startup_stm32f10x_md.s │ │ └── CoreSupport │ │ │ ├── arm_const_structs.h │ │ │ └── arm_common_tables.h │ ├── STM32F10x_StdPeriph_Driver │ │ ├── stm32f10x_i2c.c │ │ ├── stm32f10x_flash.c │ │ ├── stm32f10x_usart.c │ │ ├── stm32f10x_crc.h │ │ ├── stm32f10x_wwdg.h │ │ ├── stm32f10x_crc.c │ │ ├── stm32f10x_dbgmcu.h │ │ ├── stm32f10x_iwdg.h │ │ ├── stm32f10x_rtc.h │ │ ├── stm32f10x_pwr.h │ │ ├── stm32f10x_iwdg.c │ │ ├── stm32f10x_dbgmcu.c │ │ ├── stm32f10x_wwdg.c │ │ ├── stm32f10x_cec.h │ │ ├── stm32f10x_exti.h │ │ ├── misc.c │ │ ├── stm32f10x_exti.c │ │ ├── stm32f10x_bkp.h │ │ ├── stm32f10x_bkp.c │ │ ├── misc.h │ │ ├── stm32f10x_pwr.c │ │ └── stm32f10x_rtc.c │ └── stm32f10x_conf.h ├── SWD_flash.h ├── error.h ├── SWD_host.h └── error.c ├── keilkill.bat ├── out ├── OFDD.asm ├── OFDD.bin ├── DAPProg.asm └── DAPProg.bin ├── README.md ├── doc └── FlashAlgo │ ├── STM32F10x_128.FLM │ ├── STM32F4xx_1024.FLM │ ├── c_blob.tmpl │ ├── STM32F10x_128.c │ ├── STM32F4xx_1024.c │ └── flash_algo.py ├── .gitignore ├── JLinkSettings.ini └── DebugConfig ├── STM32F103C8_STM32F103C8.dbgconf ├── OFFLINE_DOWNLOAD_STM32F103C8.dbgconf └── Offline_downloader_STM32F103C8.dbgconf /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/main.c -------------------------------------------------------------------------------- /keilkill.bat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/keilkill.bat -------------------------------------------------------------------------------- /out/OFDD.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/out/OFDD.asm -------------------------------------------------------------------------------- /out/OFDD.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/out/OFDD.bin -------------------------------------------------------------------------------- /out/DAPProg.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/out/DAPProg.asm -------------------------------------------------------------------------------- /out/DAPProg.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/out/DAPProg.bin -------------------------------------------------------------------------------- /src/DAP/DAP.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/DAP/DAP.c -------------------------------------------------------------------------------- /src/SWD_flash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/SWD_flash.c -------------------------------------------------------------------------------- /src/SWD_host.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/SWD_host.c -------------------------------------------------------------------------------- /src/DAP_config.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/DAP_config.h -------------------------------------------------------------------------------- /src/algo/STM32F10x_128.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/algo/STM32F10x_128.c -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 基于STM32C8T6 2 | 工程源来自https://github.com/XIVN1987/DAPProg 3 | 在此基础之参照了X893作者修改的stlink，对SWD接口的IO定义进行了重新移植，方便定义任意端口 4 | -------------------------------------------------------------------------------- /doc/FlashAlgo/STM32F10x_128.FLM: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/doc/FlashAlgo/STM32F10x_128.FLM -------------------------------------------------------------------------------- /doc/FlashAlgo/STM32F4xx_1024.FLM: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/doc/FlashAlgo/STM32F4xx_1024.FLM -------------------------------------------------------------------------------- /src/CSL/CMSIS/DeviceSupport/stm32f10x.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/CSL/CMSIS/DeviceSupport/stm32f10x.h -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_i2c.c -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_flash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_flash.c -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_usart.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiaosanjue/swd_offlie_downloader/HEAD/src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_usart.c -------------------------------------------------------------------------------- /src/SWD_flash.h: -------------------------------------------------------------------------------- 1 | #ifndef __SWD_FLASH_H__ 2 | #define __SWD_FLASH_H__ 3 | 4 | #include 5 | 6 | #include "error.h" 7 | 8 | error_t target_flash_init(uint32_t flash_start); 9 | error_t target_flash_uninit(void); 10 | error_t target_flash_program_page(uint32_t addr, const uint8_t *buf, uint32_t size); 11 | error_t target_flash_erase_sector(uint32_t addr); 12 | error_t target_flash_erase_chip(void); 13 | 14 | 15 | #endif // __SWD_FLASH_H__ 16 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Object files 5 | *.o 6 | *.ko 7 | *.obj 8 | *.elf 9 | 10 | # Linker output 11 | *.ilk 12 | *.map 13 | *.exp 14 | 15 | # Precompiled Headers 16 | *.gch 17 | *.pch 18 | 19 | # Libraries 20 | *.lib 21 | *.a 22 | *.la 23 | *.lo 24 | 25 | # Shared objects (inc. Windows DLLs) 26 | *.dll 27 | *.so 28 | *.so.* 29 | *.dylib 30 | 31 | # Executables 32 | *.exe 33 | *.out 34 | *.app 35 | *.i*86 36 | *.x86_64 37 | *.hex 38 | 39 | # Debug files 40 | *.dSYM/ 41 | *.su 42 | *.idb 43 | *.pdb 44 | 45 | # Kernel Module Compile Results 46 | *.mod* 47 | *.cmd 48 | .tmp_versions/ 49 | modules.order 50 | Module.symvers 51 | Mkfile.old 52 | dkms.conf 53 | -------------------------------------------------------------------------------- /src/algo/flash_blob.h: -------------------------------------------------------------------------------- 1 | #ifndef FLASH_BLOB_H 2 | #define FLASH_BLOB_H 3 | 4 | #include 5 | 6 | 7 | typedef struct { 8 | uint32_t breakpoint; 9 | uint32_t static_base; 10 | uint32_t stack_pointer; 11 | } program_syscall_t; 12 | 13 | typedef struct { 14 | const uint32_t init; 15 | const uint32_t uninit; 16 | const uint32_t erase_chip; 17 | const uint32_t erase_sector; 18 | const uint32_t program_page; 19 | const program_syscall_t sys_call_s; 20 | const uint32_t program_buffer; 21 | const uint32_t algo_start; 22 | const uint32_t algo_size; 23 | const uint32_t *algo_blob; 24 | const uint32_t program_buffer_size; 25 | } program_target_t; 26 | 27 | typedef struct { 28 | const uint32_t start; 29 | const uint32_t size; 30 | } sector_info_t; 31 | 32 | 33 | #endif 34 | -------------------------------------------------------------------------------- /JLinkSettings.ini: -------------------------------------------------------------------------------- 1 | [BREAKPOINTS] 2 | ForceImpTypeAny = 0 3 | ShowInfoWin = 1 4 | EnableFlashBP = 2 5 | BPDuringExecution = 0 6 | [CFI] 7 | CFISize = 0x00 8 | CFIAddr = 0x00 9 | [CPU] 10 | MonModeVTableAddr = 0xFFFFFFFF 11 | MonModeDebug = 0 12 | MaxNumAPs = 0 13 | LowPowerHandlingMode = 0 14 | OverrideMemMap = 0 15 | AllowSimulation = 1 16 | ScriptFile="" 17 | [FLASH] 18 | CacheExcludeSize = 0x00 19 | CacheExcludeAddr = 0x00 20 | MinNumBytesFlashDL = 0 21 | SkipProgOnCRCMatch = 1 22 | VerifyDownload = 1 23 | AllowCaching = 1 24 | EnableFlashDL = 2 25 | Override = 0 26 | Device="ARM7" 27 | [GENERAL] 28 | WorkRAMSize = 0x00 29 | WorkRAMAddr = 0x00 30 | RAMUsageLimit = 0x00 31 | [SWO] 32 | SWOLogFile="" 33 | [MEM] 34 | RdOverrideOrMask = 0x00 35 | RdOverrideAndMask = 0xFFFFFFFF 36 | RdOverrideAddr = 0xFFFFFFFF 37 | WrOverrideOrMask = 0x00 38 | WrOverrideAndMask = 0xFFFFFFFF 39 | WrOverrideAddr = 0xFFFFFFFF 40 | -------------------------------------------------------------------------------- /src/error.h: -------------------------------------------------------------------------------- 1 | #ifndef ERROR_H 2 | #define ERROR_H 3 | 4 | 5 | // Keep in sync with the lists error_message and error_type 6 | typedef enum 7 | { 8 | /* Shared errors */ 9 | ERROR_SUCCESS = 0, 10 | ERROR_FAILURE, 11 | ERROR_INTERNAL, 12 | 13 | /* Target flash errors */ 14 | ERROR_RESET, 15 | ERROR_ALGO_DL, 16 | ERROR_ALGO_DATA_SEQ, 17 | ERROR_INIT, 18 | ERROR_SECURITY_BITS, 19 | ERROR_UNLOCK, 20 | ERROR_ERASE_SECTOR, 21 | ERROR_ERASE_ALL, 22 | ERROR_WRITE, 23 | 24 | // Add new values here 25 | 26 | ERROR_COUNT 27 | } error_t; 28 | 29 | 30 | typedef unsigned char error_type_t; 31 | 32 | #define ERROR_TYPE_INTERNAL 0x1 33 | #define ERROR_TYPE_TRANSIENT 0x2 34 | #define ERROR_TYPE_USER 0x4 35 | #define ERROR_TYPE_TARGET 0x8 36 | 37 | #define ERROR_TYPE_MASK 0xF 38 | 39 | 40 | const char *error_get_string(error_t error); 41 | 42 | error_type_t error_get_type(error_t error); 43 | 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /doc/FlashAlgo/c_blob.tmpl: -------------------------------------------------------------------------------- 1 | /* Flash OS Routines (Automagically Generated) 2 | * Copyright (c) 2009-2015 ARM Limited 3 | */ 4 | #include "flash_blob.h" 5 | 6 | static const uint32_t flash_code[] = { 7 | {{prog_header}} 8 | {{algo.format_algo_data(4, 8, "c")}} 9 | }; 10 | 11 | const program_target_t flash_algo = { 12 | {{'0x%08X' % (algo.symbols['Init'] + header_size + entry)}}, // Init 13 | {{'0x%08X' % (algo.symbols['UnInit'] + header_size + entry)}}, // UnInit 14 | {{'0x%08X' % (algo.symbols['EraseChip'] + header_size + entry)}}, // EraseChip 15 | {{'0x%08X' % (algo.symbols['EraseSector'] + header_size + entry)}}, // EraseSector 16 | {{'0x%08X' % (algo.symbols['ProgramPage'] + header_size + entry)}}, // ProgramPage 17 | 18 | // BKPT : start of blob + 1 19 | // RSB : address to access global/static data 20 | // RSP : stack pointer 21 | { 22 | {{'0x%08X' % (entry + 1)}}, 23 | {{'0x%08X' % (entry + 1024*3)}}, 24 | {{'0x%08X' % stack_pointer}} 25 | }, 26 | 27 | {{'0x%08X' % (entry + 1024)}}, // mem buffer location 28 | {{'0x%08X' % entry}}, // location to write prog_blob in target RAM 29 | sizeof(flash_code), // prog_blob size 30 | flash_code, // address of prog_blob 31 | {{'0x%08X' % algo.flash_page_size}}, // ram_to_flash_bytes_to_be_written 32 | }; 33 | 34 | -------------------------------------------------------------------------------- /src/SWD_host.h: -------------------------------------------------------------------------------- 1 | #ifndef SWDHOST_CM_H 2 | #define SWDHOST_CM_H 3 | 4 | #include 5 | 6 | #include "algo/flash_blob.h" 7 | 8 | 9 | typedef enum 10 | { 11 | RESET_HOLD, // Hold target in reset 12 | RESET_PROGRAM, // Reset target and setup for flash programming. 13 | RESET_RUN, // Reset target and run normally 14 | NO_DEBUG, // Disable debug on running target 15 | DEBUG, // Enable debug on running target 16 | HALT, // Halt the target without resetting it 17 | RUN // Resume the target without resetting it 18 | } TARGET_RESET_STATE; 19 | 20 | 21 | uint8_t swd_init(void); 22 | uint8_t swd_off(void); 23 | uint8_t swd_init_debug(void); 24 | uint8_t swd_read_dp(uint8_t adr, uint32_t *val); 25 | uint8_t swd_write_dp(uint8_t adr, uint32_t val); 26 | uint8_t swd_read_ap(uint32_t adr, uint32_t *val); 27 | uint8_t swd_write_ap(uint32_t adr, uint32_t val); 28 | uint8_t swd_read_memory(uint32_t address, uint8_t *data, uint32_t size); 29 | uint8_t swd_write_memory(uint32_t address, uint8_t *data, uint32_t size); 30 | uint8_t swd_flash_syscall_exec(const program_syscall_t *sysCallParam, uint32_t entry, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4); 31 | void swd_set_target_reset(uint8_t asserted); 32 | uint8_t swd_set_target_state_hw(TARGET_RESET_STATE state); 33 | uint8_t swd_set_target_state_sw(TARGET_RESET_STATE state); 34 | 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /doc/FlashAlgo/STM32F10x_128.c: -------------------------------------------------------------------------------- 1 | /* Flash OS Routines (Automagically Generated) 2 | * Copyright (c) 2009-2015 ARM Limited 3 | */ 4 | #include "flash_blob.h" 5 | 6 | static const uint32_t flash_code[] = { 7 | 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, 8 | 0x4603B510, 0x4C442000, 0x48446020, 0x48446060, 0x46206060, 0xF01069C0, 0xD1080F04, 0x5055F245, 9 | 0x60204C40, 0x60602006, 0x70FFF640, 0x200060A0, 0x4601BD10, 0x69004838, 0x0080F040, 0x61104A36, 10 | 0x47702000, 0x69004834, 0x0004F040, 0x61084932, 0x69004608, 0x0040F040, 0xE0036108, 0x20AAF64A, 11 | 0x60084930, 0x68C0482C, 0x0F01F010, 0x482AD1F6, 0xF0206900, 0x49280004, 0x20006108, 0x46014770, 12 | 0x69004825, 0x0002F040, 0x61104A23, 0x61414610, 0xF0406900, 0x61100040, 0xF64AE003, 0x4A2120AA, 13 | 0x481D6010, 0xF01068C0, 0xD1F60F01, 0x6900481A, 0x0002F020, 0x61104A18, 0x47702000, 0x4603B510, 14 | 0xF0201C48, 0xE0220101, 0x69004813, 0x0001F040, 0x61204C11, 0x80188810, 0x480FBF00, 0xF01068C0, 15 | 0xD1FA0F01, 0x6900480C, 0x0001F020, 0x61204C0A, 0x68C04620, 0x0F14F010, 0x4620D006, 0xF04068C0, 16 | 0x60E00014, 0xBD102001, 0x1C921C9B, 0x29001E89, 0x2000D1DA, 0x0000E7F7, 0x40022000, 0x45670123, 17 | 0xCDEF89AB, 0x40003000, 0x00000000 18 | }; 19 | 20 | const program_target_t flash_algo = { 21 | 0x20000021, // Init 22 | 0x20000053, // UnInit 23 | 0x20000065, // EraseChip 24 | 0x2000009F, // EraseSector 25 | 0x200000DD, // ProgramPage 26 | 27 | // BKPT : start of blob + 1 28 | // RSB : address to access global/static data 29 | // RSP : stack pointer 30 | { 31 | 0x20000001, 32 | 0x20000C00, 33 | 0x20001000 34 | }, 35 | 36 | 0x20000400, // mem buffer location 37 | 0x20000000, // location to write prog_blob in target RAM 38 | sizeof(flash_code), // prog_blob size 39 | flash_code, // address of prog_blob 40 | 0x00000400, // ram_to_flash_bytes_to_be_written 41 | }; 42 | -------------------------------------------------------------------------------- /src/algo/STM32F4xx_1024.c: -------------------------------------------------------------------------------- 1 | /* Flash OS Routines (Automagically Generated) 2 | * Copyright (c) 2009-2015 ARM Limited 3 | */ 4 | #include "flash_blob.h" 5 | 6 | static const uint32_t flash_code[] = { 7 | 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, 8 | 0x0E000300, 0xD3022820, 0x1D000940, 0x28104770, 0x0900D302, 0x47701CC0, 0x47700880, 0x49414842, 9 | 0x49426041, 0x21006041, 0x68C16001, 0x431122F0, 0x694060C1, 0xD4060680, 0x493D483E, 0x21066001, 10 | 0x493D6041, 0x20006081, 0x48374770, 0x05426901, 0x61014311, 0x47702000, 0x4833B510, 0x24046901, 11 | 0x61014321, 0x03A26901, 0x61014311, 0x4A314933, 0x6011E000, 0x03DB68C3, 0x6901D4FB, 0x610143A1, 12 | 0xBD102000, 0xF7FFB530, 0x4927FFBB, 0x23F068CA, 0x60CA431A, 0x610C2402, 0x0700690A, 0x43020E40, 13 | 0x6908610A, 0x431003E2, 0x48246108, 0xE0004A21, 0x68CD6010, 0xD4FB03ED, 0x43A06908, 0x68C86108, 14 | 0x0F000600, 0x68C8D003, 0x60C84318, 0xBD302001, 0x4D15B570, 0x08891CC9, 0x008968EB, 0x433326F0, 15 | 0x230060EB, 0x4B16612B, 0x692CE017, 0x612C431C, 0x60046814, 0x03E468EC, 0x692CD4FC, 0x00640864, 16 | 0x68EC612C, 0x0F240624, 0x68E8D004, 0x60E84330, 0xBD702001, 0x1D121D00, 0x29001F09, 0x2000D1E5, 17 | 0x0000BD70, 0x45670123, 0x40023C00, 0xCDEF89AB, 0x00005555, 0x40003000, 0x00000FFF, 0x0000AAAA, 18 | 0x00000201, 0x00000000 19 | }; 20 | 21 | const program_target_t flash_algo = { 22 | 0x2000003D, // Init 23 | 0x2000006B, // UnInit 24 | 0x20000079, // EraseChip 25 | 0x200000A5, // EraseSector 26 | 0x200000F1, // ProgramPage 27 | 28 | // BKPT : start of blob + 1 29 | // RSB : address to access global/static data 30 | // RSP : stack pointer 31 | { 32 | 0x20000001, 33 | 0x20000C00, 34 | 0x20001000 35 | }, 36 | 37 | 0x20000400, // mem buffer location 38 | 0x20000000, // location to write prog_blob in target RAM 39 | sizeof(flash_code), // prog_blob size 40 | flash_code, // address of prog_blob 41 | 0x00000400, // ram_to_flash_bytes_to_be_written 42 | }; 43 | -------------------------------------------------------------------------------- /doc/FlashAlgo/STM32F4xx_1024.c: -------------------------------------------------------------------------------- 1 | /* Flash OS Routines (Automagically Generated) 2 | * Copyright (c) 2009-2015 ARM Limited 3 | */ 4 | #include "flash_blob.h" 5 | 6 | static const uint32_t flash_code[] = { 7 | 0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2, 8 | 0x0E000300, 0xD3022820, 0x1D000940, 0x28104770, 0x0900D302, 0x47701CC0, 0x47700880, 0x49414842, 9 | 0x49426041, 0x21006041, 0x68C16001, 0x431122F0, 0x694060C1, 0xD4060680, 0x493D483E, 0x21066001, 10 | 0x493D6041, 0x20006081, 0x48374770, 0x05426901, 0x61014311, 0x47702000, 0x4833B510, 0x24046901, 11 | 0x61014321, 0x03A26901, 0x61014311, 0x4A314933, 0x6011E000, 0x03DB68C3, 0x6901D4FB, 0x610143A1, 12 | 0xBD102000, 0xF7FFB530, 0x4927FFBB, 0x23F068CA, 0x60CA431A, 0x610C2402, 0x0700690A, 0x43020E40, 13 | 0x6908610A, 0x431003E2, 0x48246108, 0xE0004A21, 0x68CD6010, 0xD4FB03ED, 0x43A06908, 0x68C86108, 14 | 0x0F000600, 0x68C8D003, 0x60C84318, 0xBD302001, 0x4D15B570, 0x08891CC9, 0x008968EB, 0x433326F0, 15 | 0x230060EB, 0x4B16612B, 0x692CE017, 0x612C431C, 0x60046814, 0x03E468EC, 0x692CD4FC, 0x00640864, 16 | 0x68EC612C, 0x0F240624, 0x68E8D004, 0x60E84330, 0xBD702001, 0x1D121D00, 0x29001F09, 0x2000D1E5, 17 | 0x0000BD70, 0x45670123, 0x40023C00, 0xCDEF89AB, 0x00005555, 0x40003000, 0x00000FFF, 0x0000AAAA, 18 | 0x00000201, 0x00000000 19 | }; 20 | 21 | const program_target_t flash_algo = { 22 | 0x2000003D, // Init 23 | 0x2000006B, // UnInit 24 | 0x20000079, // EraseChip 25 | 0x200000A5, // EraseSector 26 | 0x200000F1, // ProgramPage 27 | 28 | // BKPT : start of blob + 1 29 | // RSB : address to access global/static data 30 | // RSP : stack pointer 31 | { 32 | 0x20000001, 33 | 0x20000C00, 34 | 0x20001000 35 | }, 36 | 37 | 0x20000400, // mem buffer location 38 | 0x20000000, // location to write prog_blob in target RAM 39 | sizeof(flash_code), // prog_blob size 40 | flash_code, // address of prog_blob 41 | 0x00000400, // ram_to_flash_bytes_to_be_written 42 | }; 43 | -------------------------------------------------------------------------------- /src/CSL/CMSIS/DeviceSupport/system_stm32f10x.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /** @addtogroup CMSIS 23 | * @{ 24 | */ 25 | 26 | /** @addtogroup stm32f10x_system 27 | * @{ 28 | */ 29 | 30 | /** 31 | * @brief Define to prevent recursive inclusion 32 | */ 33 | #ifndef __SYSTEM_STM32F10X_H 34 | #define __SYSTEM_STM32F10X_H 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | /** @addtogroup STM32F10x_System_Includes 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @} 46 | */ 47 | 48 | 49 | /** @addtogroup STM32F10x_System_Exported_types 50 | * @{ 51 | */ 52 | 53 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @addtogroup STM32F10x_System_Exported_Constants 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F10x_System_Exported_Macros 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F10x_System_Exported_Functions 76 | * @{ 77 | */ 78 | 79 | extern void SystemInit(void); 80 | extern void SystemCoreClockUpdate(void); 81 | /** 82 | * @} 83 | */ 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif /*__SYSTEM_STM32F10X_H */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 99 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_crc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the CRC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_CRC_H 25 | #define __STM32F10x_CRC_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup CRC 39 | * @{ 40 | */ 41 | 42 | /** @defgroup CRC_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup CRC_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @defgroup CRC_Exported_Macros 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup CRC_Exported_Functions 67 | * @{ 68 | */ 69 | 70 | void CRC_ResetDR(void); 71 | uint32_t CRC_CalcCRC(uint32_t Data); 72 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 73 | uint32_t CRC_GetCRC(void); 74 | void CRC_SetIDRegister(uint8_t IDValue); 75 | uint8_t CRC_GetIDRegister(void); 76 | 77 | #ifdef __cplusplus 78 | } 79 | #endif 80 | 81 | #endif /* __STM32F10x_CRC_H */ 82 | /** 83 | * @} 84 | */ 85 | 86 | /** 87 | * @} 88 | */ 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 95 | -------------------------------------------------------------------------------- /src/error.c: -------------------------------------------------------------------------------- 1 | /** 2 | * @file error.c 3 | * @brief collection of known errors and accessor for the friendly string 4 | */ 5 | 6 | #include "error.h" 7 | 8 | static const char *const error_message[] = 9 | { 10 | 11 | /* Shared errors */ 12 | 13 | // ERROR_SUCCESS 14 | "Operation was successful", 15 | // ERROR_FAILURE 16 | "An error has occurred", 17 | // ERROR_INTERNAL 18 | "An internal error has occurred", 19 | 20 | 21 | /* Target flash errors */ 22 | 23 | // ERROR_RESET 24 | "The interface firmware FAILED to reset/halt the target MCU", 25 | // ERROR_ALGO_DL 26 | "The interface firmware FAILED to download the flash programming algorithms to the target MCU", 27 | // ERROR_ALGO_DATA_SEQ 28 | "The interface firmware FAILED to download the flash data contents to be programmed", 29 | // ERROR_INIT 30 | "The interface firmware FAILED to initialize the target MCU", 31 | // ERROR_SECURITY_BITS 32 | "The interface firmware ABORTED programming. Image is trying to set security bits", 33 | // ERROR_UNLOCK 34 | "The interface firmware FAILED to unlock the target for programming", 35 | // ERROR_ERASE_SECTOR 36 | "Flash algorithm erase sector command FAILURE", 37 | // ERROR_ERASE_ALL 38 | "Flash algorithm erase all command FAILURE", 39 | // ERROR_WRITE 40 | "Flash algorithm write command FAILURE", 41 | }; 42 | 43 | static error_type_t error_type[] = 44 | { 45 | 46 | /* These should always stay the same for each error type. */ 47 | 48 | // ERROR_SUCCESS 49 | 0, 50 | // ERROR_FAILURE 51 | ERROR_TYPE_INTERNAL, 52 | // ERROR_INTERNAL 53 | ERROR_TYPE_INTERNAL, 54 | 55 | 56 | /* Target flash errors */ 57 | 58 | // ERROR_RESET 59 | ERROR_TYPE_TARGET, 60 | // ERROR_ALGO_DL 61 | ERROR_TYPE_TARGET, 62 | // ERROR_ALGO_DATA_SEQ 63 | ERROR_TYPE_TARGET, 64 | // ERROR_INIT 65 | ERROR_TYPE_TARGET, 66 | // ERROR_SECURITY_BITS 67 | ERROR_TYPE_USER, 68 | // ERROR_UNLOCK 69 | ERROR_TYPE_TARGET, 70 | // ERROR_ERASE_SECTOR 71 | ERROR_TYPE_TARGET, 72 | // ERROR_ERASE_ALL 73 | ERROR_TYPE_TARGET, 74 | // ERROR_WRITE 75 | ERROR_TYPE_TARGET, 76 | }; 77 | 78 | const char *error_get_string(error_t error) 79 | { 80 | const char *msg = 0; 81 | 82 | if(error < ERROR_COUNT) 83 | { 84 | msg = error_message[error]; 85 | } 86 | 87 | return msg; 88 | } 89 | 90 | error_type_t error_get_type(error_t error) 91 | { 92 | error_type_t type = ERROR_TYPE_INTERNAL; 93 | 94 | if(error < ERROR_COUNT) 95 | { 96 | type = error_type[error]; 97 | } 98 | 99 | return type; 100 | } 101 | -------------------------------------------------------------------------------- /src/CSL/stm32f10x_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 08-April-2011 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_CONF_H 24 | #define __STM32F10x_CONF_H 25 | 26 | /* Includes ------------------------------------------------------------------*/ 27 | /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ 28 | #include "stm32f10x_adc.h" 29 | #include "stm32f10x_bkp.h" 30 | #include "stm32f10x_can.h" 31 | #include "stm32f10x_cec.h" 32 | #include "stm32f10x_crc.h" 33 | #include "stm32f10x_dac.h" 34 | #include "stm32f10x_dbgmcu.h" 35 | #include "stm32f10x_dma.h" 36 | #include "stm32f10x_exti.h" 37 | #include "stm32f10x_flash.h" 38 | #include "stm32f10x_fsmc.h" 39 | #include "stm32f10x_gpio.h" 40 | #include "stm32f10x_i2c.h" 41 | #include "stm32f10x_iwdg.h" 42 | #include "stm32f10x_pwr.h" 43 | #include "stm32f10x_rcc.h" 44 | #include "stm32f10x_rtc.h" 45 | #include "stm32f10x_sdio.h" 46 | #include "stm32f10x_spi.h" 47 | #include "stm32f10x_tim.h" 48 | #include "stm32f10x_usart.h" 49 | #include "stm32f10x_wwdg.h" 50 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 51 | 52 | /* Exported types ------------------------------------------------------------*/ 53 | /* Exported constants --------------------------------------------------------*/ 54 | /* Uncomment the line below to expanse the "assert_param" macro in the 55 | Standard Peripheral Library drivers code */ 56 | /* #define USE_FULL_ASSERT 1 */ 57 | 58 | /* Exported macro ------------------------------------------------------------*/ 59 | #ifdef USE_FULL_ASSERT 60 | 61 | /** 62 | * @brief The assert_param macro is used for function's parameters check. 63 | * @param expr: If expr is false, it calls assert_failed function which reports 64 | * the name of the source file and the source line number of the call 65 | * that failed. If expr is true, it returns no value. 66 | * @retval None 67 | */ 68 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 69 | /* Exported functions ------------------------------------------------------- */ 70 | void assert_failed(uint8_t* file, uint32_t line); 71 | #else 72 | #define assert_param(expr) ((void)0) 73 | #endif /* USE_FULL_ASSERT */ 74 | 75 | #endif /* __STM32F10x_CONF_H */ 76 | 77 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 78 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_wwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the WWDG firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_WWDG_H 25 | #define __STM32F10x_WWDG_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup WWDG 39 | * @{ 40 | */ 41 | 42 | /** @defgroup WWDG_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup WWDG_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup WWDG_Prescaler 55 | * @{ 56 | */ 57 | 58 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 59 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 60 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 61 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ 63 | ((PRESCALER) == WWDG_Prescaler_2) || \ 64 | ((PRESCALER) == WWDG_Prescaler_4) || \ 65 | ((PRESCALER) == WWDG_Prescaler_8)) 66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) 67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** 74 | * @} 75 | */ 76 | 77 | /** @defgroup WWDG_Exported_Macros 78 | * @{ 79 | */ 80 | /** 81 | * @} 82 | */ 83 | 84 | /** @defgroup WWDG_Exported_Functions 85 | * @{ 86 | */ 87 | 88 | void WWDG_DeInit(void); 89 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 90 | void WWDG_SetWindowValue(uint8_t WindowValue); 91 | void WWDG_EnableIT(void); 92 | void WWDG_SetCounter(uint8_t Counter); 93 | void WWDG_Enable(uint8_t Counter); 94 | FlagStatus WWDG_GetFlagStatus(void); 95 | void WWDG_ClearFlag(void); 96 | 97 | #ifdef __cplusplus 98 | } 99 | #endif 100 | 101 | #endif /* __STM32F10x_WWDG_H */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | /** 112 | * @} 113 | */ 114 | 115 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 116 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_crc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the CRC firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_crc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup CRC 30 | * @brief CRC driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup CRC_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup CRC_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup CRC_Private_Macros 51 | * @{ 52 | */ 53 | 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @defgroup CRC_Private_Variables 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup CRC_Private_FunctionPrototypes 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup CRC_Private_Functions 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @brief Resets the CRC Data register (DR). 80 | * @param None 81 | * @retval None 82 | */ 83 | void CRC_ResetDR(void) 84 | { 85 | /* Reset CRC generator */ 86 | CRC->CR = CRC_CR_RESET; 87 | } 88 | 89 | /** 90 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 91 | * @param Data: data word(32-bit) to compute its CRC 92 | * @retval 32-bit CRC 93 | */ 94 | uint32_t CRC_CalcCRC(uint32_t Data) 95 | { 96 | CRC->DR = Data; 97 | 98 | return (CRC->DR); 99 | } 100 | 101 | /** 102 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 103 | * @param pBuffer: pointer to the buffer containing the data to be computed 104 | * @param BufferLength: length of the buffer to be computed 105 | * @retval 32-bit CRC 106 | */ 107 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 108 | { 109 | uint32_t index = 0; 110 | 111 | for(index = 0; index < BufferLength; index++) 112 | { 113 | CRC->DR = pBuffer[index]; 114 | } 115 | return (CRC->DR); 116 | } 117 | 118 | /** 119 | * @brief Returns the current CRC value. 120 | * @param None 121 | * @retval 32-bit CRC 122 | */ 123 | uint32_t CRC_GetCRC(void) 124 | { 125 | return (CRC->DR); 126 | } 127 | 128 | /** 129 | * @brief Stores a 8-bit data in the Independent Data(ID) register. 130 | * @param IDValue: 8-bit value to be stored in the ID register 131 | * @retval None 132 | */ 133 | void CRC_SetIDRegister(uint8_t IDValue) 134 | { 135 | CRC->IDR = IDValue; 136 | } 137 | 138 | /** 139 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register 140 | * @param None 141 | * @retval 8-bit value of the ID register 142 | */ 143 | uint8_t CRC_GetIDRegister(void) 144 | { 145 | return (CRC->IDR); 146 | } 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /** 153 | * @} 154 | */ 155 | 156 | /** 157 | * @} 158 | */ 159 | 160 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 161 | -------------------------------------------------------------------------------- /src/CSL/CMSIS/CoreSupport/arm_const_structs.h: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. 3 | * 4 | * $Date: 31. July 2014 5 | * $Revision: V1.4.4 6 | * 7 | * Project: CMSIS DSP Library 8 | * Title: arm_const_structs.h 9 | * 10 | * Description: This file has constant structs that are initialized for 11 | * user convenience. For example, some can be given as 12 | * arguments to the arm_cfft_f32() function. 13 | * 14 | * Target Processor: Cortex-M4/Cortex-M3 15 | * 16 | * Redistribution and use in source and binary forms, with or without 17 | * modification, are permitted provided that the following conditions 18 | * are met: 19 | * - Redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer. 21 | * - Redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in 23 | * the documentation and/or other materials provided with the 24 | * distribution. 25 | * - Neither the name of ARM LIMITED nor the names of its contributors 26 | * may be used to endorse or promote products derived from this 27 | * software without specific prior written permission. 28 | * 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 32 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 33 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 35 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 39 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 | * POSSIBILITY OF SUCH DAMAGE. 41 | * -------------------------------------------------------------------- */ 42 | 43 | #ifndef _ARM_CONST_STRUCTS_H 44 | #define _ARM_CONST_STRUCTS_H 45 | 46 | #include "arm_math.h" 47 | #include "arm_common_tables.h" 48 | 49 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; 50 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; 51 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; 52 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; 53 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; 54 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; 55 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; 56 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; 57 | extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; 58 | 59 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; 60 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; 61 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; 62 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; 63 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; 64 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; 65 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; 66 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; 67 | extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; 68 | 69 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; 70 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; 71 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; 72 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; 73 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; 74 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; 75 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; 76 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; 77 | extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; 78 | 79 | #endif 80 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the DBGMCU 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_DBGMCU_H 25 | #define __STM32F10x_DBGMCU_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup DBGMCU 39 | * @{ 40 | */ 41 | 42 | /** @defgroup DBGMCU_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup DBGMCU_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | #define DBGMCU_SLEEP ((uint32_t)0x00000001) 55 | #define DBGMCU_STOP ((uint32_t)0x00000002) 56 | #define DBGMCU_STANDBY ((uint32_t)0x00000004) 57 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) 58 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) 59 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) 60 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) 61 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) 62 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) 63 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) 64 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) 65 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) 66 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) 67 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) 68 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) 69 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) 70 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) 71 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) 72 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) 73 | #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) 74 | #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) 75 | #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) 76 | #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) 77 | #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) 78 | #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) 79 | #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) 80 | 81 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) 82 | /** 83 | * @} 84 | */ 85 | 86 | /** @defgroup DBGMCU_Exported_Macros 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @defgroup DBGMCU_Exported_Functions 95 | * @{ 96 | */ 97 | 98 | uint32_t DBGMCU_GetREVID(void); 99 | uint32_t DBGMCU_GetDEVID(void); 100 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 101 | 102 | #ifdef __cplusplus 103 | } 104 | #endif 105 | 106 | #endif /* __STM32F10x_DBGMCU_H */ 107 | /** 108 | * @} 109 | */ 110 | 111 | /** 112 | * @} 113 | */ 114 | 115 | /** 116 | * @} 117 | */ 118 | 119 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 120 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_iwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the IWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_IWDG_H 25 | #define __STM32F10x_IWDG_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup IWDG 39 | * @{ 40 | */ 41 | 42 | /** @defgroup IWDG_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup IWDG_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup IWDG_WriteAccess 55 | * @{ 56 | */ 57 | 58 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 59 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 60 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ 61 | ((ACCESS) == IWDG_WriteAccess_Disable)) 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup IWDG_prescaler 67 | * @{ 68 | */ 69 | 70 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 71 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 72 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 73 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 74 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 75 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 76 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 77 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ 78 | ((PRESCALER) == IWDG_Prescaler_8) || \ 79 | ((PRESCALER) == IWDG_Prescaler_16) || \ 80 | ((PRESCALER) == IWDG_Prescaler_32) || \ 81 | ((PRESCALER) == IWDG_Prescaler_64) || \ 82 | ((PRESCALER) == IWDG_Prescaler_128)|| \ 83 | ((PRESCALER) == IWDG_Prescaler_256)) 84 | /** 85 | * @} 86 | */ 87 | 88 | /** @defgroup IWDG_Flag 89 | * @{ 90 | */ 91 | 92 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 93 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 94 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) 95 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) 96 | /** 97 | * @} 98 | */ 99 | 100 | /** 101 | * @} 102 | */ 103 | 104 | /** @defgroup IWDG_Exported_Macros 105 | * @{ 106 | */ 107 | 108 | /** 109 | * @} 110 | */ 111 | 112 | /** @defgroup IWDG_Exported_Functions 113 | * @{ 114 | */ 115 | 116 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 117 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 118 | void IWDG_SetReload(uint16_t Reload); 119 | void IWDG_ReloadCounter(void); 120 | void IWDG_Enable(void); 121 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 122 | 123 | #ifdef __cplusplus 124 | } 125 | #endif 126 | 127 | #endif /* __STM32F10x_IWDG_H */ 128 | /** 129 | * @} 130 | */ 131 | 132 | /** 133 | * @} 134 | */ 135 | 136 | /** 137 | * @} 138 | */ 139 | 140 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 141 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_rtc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_rtc.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the RTC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_RTC_H 25 | #define __STM32F10x_RTC_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup RTC 39 | * @{ 40 | */ 41 | 42 | /** @defgroup RTC_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup RTC_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup RTC_interrupts_define 55 | * @{ 56 | */ 57 | 58 | #define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ 59 | #define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ 60 | #define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ 61 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) 62 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ 63 | ((IT) == RTC_IT_SEC)) 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup RTC_interrupts_flags 69 | * @{ 70 | */ 71 | 72 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ 73 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ 74 | #define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ 75 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ 76 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ 77 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) 78 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ 79 | ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ 80 | ((FLAG) == RTC_FLAG_SEC)) 81 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /** 88 | * @} 89 | */ 90 | 91 | /** @defgroup RTC_Exported_Macros 92 | * @{ 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | 99 | /** @defgroup RTC_Exported_Functions 100 | * @{ 101 | */ 102 | 103 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); 104 | void RTC_EnterConfigMode(void); 105 | void RTC_ExitConfigMode(void); 106 | uint32_t RTC_GetCounter(void); 107 | void RTC_SetCounter(uint32_t CounterValue); 108 | void RTC_SetPrescaler(uint32_t PrescalerValue); 109 | void RTC_SetAlarm(uint32_t AlarmValue); 110 | uint32_t RTC_GetDivider(void); 111 | void RTC_WaitForLastTask(void); 112 | void RTC_WaitForSynchro(void); 113 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); 114 | void RTC_ClearFlag(uint16_t RTC_FLAG); 115 | ITStatus RTC_GetITStatus(uint16_t RTC_IT); 116 | void RTC_ClearITPendingBit(uint16_t RTC_IT); 117 | 118 | #ifdef __cplusplus 119 | } 120 | #endif 121 | 122 | #endif /* __STM32F10x_RTC_H */ 123 | /** 124 | * @} 125 | */ 126 | 127 | /** 128 | * @} 129 | */ 130 | 131 | /** 132 | * @} 133 | */ 134 | 135 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 136 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the PWR firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_PWR_H 25 | #define __STM32F10x_PWR_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup PWR 39 | * @{ 40 | */ 41 | 42 | /** @defgroup PWR_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup PWR_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup PVD_detection_level 55 | * @{ 56 | */ 57 | 58 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) 59 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) 60 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) 61 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) 62 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) 63 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) 64 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) 65 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) 66 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ 67 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ 68 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ 69 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup Regulator_state_is_STOP_mode 75 | * @{ 76 | */ 77 | 78 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 79 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001) 80 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ 81 | ((REGULATOR) == PWR_Regulator_LowPower)) 82 | /** 83 | * @} 84 | */ 85 | 86 | /** @defgroup STOP_mode_entry 87 | * @{ 88 | */ 89 | 90 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 91 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 92 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /** @defgroup PWR_Flag 99 | * @{ 100 | */ 101 | 102 | #define PWR_FLAG_WU ((uint32_t)0x00000001) 103 | #define PWR_FLAG_SB ((uint32_t)0x00000002) 104 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 105 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 106 | ((FLAG) == PWR_FLAG_PVDO)) 107 | 108 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) 109 | /** 110 | * @} 111 | */ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | /** @defgroup PWR_Exported_Macros 118 | * @{ 119 | */ 120 | 121 | /** 122 | * @} 123 | */ 124 | 125 | /** @defgroup PWR_Exported_Functions 126 | * @{ 127 | */ 128 | 129 | void PWR_DeInit(void); 130 | void PWR_BackupAccessCmd(FunctionalState NewState); 131 | void PWR_PVDCmd(FunctionalState NewState); 132 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 133 | void PWR_WakeUpPinCmd(FunctionalState NewState); 134 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 135 | void PWR_EnterSTANDBYMode(void); 136 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 137 | void PWR_ClearFlag(uint32_t PWR_FLAG); 138 | 139 | #ifdef __cplusplus 140 | } 141 | #endif 142 | 143 | #endif /* __STM32F10x_PWR_H */ 144 | /** 145 | * @} 146 | */ 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /** 153 | * @} 154 | */ 155 | 156 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 157 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_iwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the IWDG firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_iwdg.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup IWDG 30 | * @brief IWDG driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup IWDG_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup IWDG_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /* ---------------------- IWDG registers bit mask ----------------------------*/ 47 | 48 | /* KR register bit mask */ 49 | #define KR_KEY_Reload ((uint16_t)0xAAAA) 50 | #define KR_KEY_Enable ((uint16_t)0xCCCC) 51 | 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup IWDG_Private_Macros 57 | * @{ 58 | */ 59 | 60 | /** 61 | * @} 62 | */ 63 | 64 | /** @defgroup IWDG_Private_Variables 65 | * @{ 66 | */ 67 | 68 | /** 69 | * @} 70 | */ 71 | 72 | /** @defgroup IWDG_Private_FunctionPrototypes 73 | * @{ 74 | */ 75 | 76 | /** 77 | * @} 78 | */ 79 | 80 | /** @defgroup IWDG_Private_Functions 81 | * @{ 82 | */ 83 | 84 | /** 85 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. 86 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. 87 | * This parameter can be one of the following values: 88 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers 89 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers 90 | * @retval None 91 | */ 92 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 93 | { 94 | /* Check the parameters */ 95 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); 96 | IWDG->KR = IWDG_WriteAccess; 97 | } 98 | 99 | /** 100 | * @brief Sets IWDG Prescaler value. 101 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value. 102 | * This parameter can be one of the following values: 103 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 104 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 105 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 106 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 107 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 108 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 109 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 110 | * @retval None 111 | */ 112 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 113 | { 114 | /* Check the parameters */ 115 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); 116 | IWDG->PR = IWDG_Prescaler; 117 | } 118 | 119 | /** 120 | * @brief Sets IWDG Reload value. 121 | * @param Reload: specifies the IWDG Reload value. 122 | * This parameter must be a number between 0 and 0x0FFF. 123 | * @retval None 124 | */ 125 | void IWDG_SetReload(uint16_t Reload) 126 | { 127 | /* Check the parameters */ 128 | assert_param(IS_IWDG_RELOAD(Reload)); 129 | IWDG->RLR = Reload; 130 | } 131 | 132 | /** 133 | * @brief Reloads IWDG counter with value defined in the reload register 134 | * (write access to IWDG_PR and IWDG_RLR registers disabled). 135 | * @param None 136 | * @retval None 137 | */ 138 | void IWDG_ReloadCounter(void) 139 | { 140 | IWDG->KR = KR_KEY_Reload; 141 | } 142 | 143 | /** 144 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). 145 | * @param None 146 | * @retval None 147 | */ 148 | void IWDG_Enable(void) 149 | { 150 | IWDG->KR = KR_KEY_Enable; 151 | } 152 | 153 | /** 154 | * @brief Checks whether the specified IWDG flag is set or not. 155 | * @param IWDG_FLAG: specifies the flag to check. 156 | * This parameter can be one of the following values: 157 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going 158 | * @arg IWDG_FLAG_RVU: Reload Value Update on going 159 | * @retval The new state of IWDG_FLAG (SET or RESET). 160 | */ 161 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 162 | { 163 | FlagStatus bitstatus = RESET; 164 | /* Check the parameters */ 165 | assert_param(IS_IWDG_FLAG(IWDG_FLAG)); 166 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) 167 | { 168 | bitstatus = SET; 169 | } 170 | else 171 | { 172 | bitstatus = RESET; 173 | } 174 | /* Return the flag status */ 175 | return bitstatus; 176 | } 177 | 178 | /** 179 | * @} 180 | */ 181 | 182 | /** 183 | * @} 184 | */ 185 | 186 | /** 187 | * @} 188 | */ 189 | 190 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 191 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the DBGMCU firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_dbgmcu.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup DBGMCU 30 | * @brief DBGMCU driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup DBGMCU_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup DBGMCU_Private_Defines 43 | * @{ 44 | */ 45 | 46 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) 47 | /** 48 | * @} 49 | */ 50 | 51 | /** @defgroup DBGMCU_Private_Macros 52 | * @{ 53 | */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @defgroup DBGMCU_Private_Variables 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup DBGMCU_Private_FunctionPrototypes 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @defgroup DBGMCU_Private_Functions 76 | * @{ 77 | */ 78 | 79 | /** 80 | * @brief Returns the device revision identifier. 81 | * @param None 82 | * @retval Device revision identifier 83 | */ 84 | uint32_t DBGMCU_GetREVID(void) 85 | { 86 | return(DBGMCU->IDCODE >> 16); 87 | } 88 | 89 | /** 90 | * @brief Returns the device identifier. 91 | * @param None 92 | * @retval Device identifier 93 | */ 94 | uint32_t DBGMCU_GetDEVID(void) 95 | { 96 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); 97 | } 98 | 99 | /** 100 | * @brief Configures the specified peripheral and low power mode behavior 101 | * when the MCU under Debug mode. 102 | * @param DBGMCU_Periph: specifies the peripheral and low power mode. 103 | * This parameter can be any combination of the following values: 104 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode 105 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode 106 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode 107 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted 108 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted 109 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted 110 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted 111 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted 112 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted 113 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted 114 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted 115 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted 116 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted 117 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted 118 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted 119 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted 120 | * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 121 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted 122 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted 123 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted 124 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted 125 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted 126 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted 127 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted 128 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted 129 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 130 | * @param NewState: new state of the specified peripheral in Debug mode. 131 | * This parameter can be: ENABLE or DISABLE. 132 | * @retval None 133 | */ 134 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 135 | { 136 | /* Check the parameters */ 137 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); 138 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 139 | 140 | if (NewState != DISABLE) 141 | { 142 | DBGMCU->CR |= DBGMCU_Periph; 143 | } 144 | else 145 | { 146 | DBGMCU->CR &= ~DBGMCU_Periph; 147 | } 148 | } 149 | 150 | /** 151 | * @} 152 | */ 153 | 154 | /** 155 | * @} 156 | */ 157 | 158 | /** 159 | * @} 160 | */ 161 | 162 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 163 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_wwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the WWDG firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_wwdg.h" 24 | #include "stm32f10x_rcc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup WWDG 31 | * @brief WWDG driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup WWDG_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup WWDG_Private_Defines 44 | * @{ 45 | */ 46 | 47 | /* ----------- WWDG registers bit address in the alias region ----------- */ 48 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) 49 | 50 | /* Alias word address of EWI bit */ 51 | #define CFR_OFFSET (WWDG_OFFSET + 0x04) 52 | #define EWI_BitNumber 0x09 53 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) 54 | 55 | /* --------------------- WWDG registers bit mask ------------------------ */ 56 | 57 | /* CR register bit mask */ 58 | #define CR_WDGA_Set ((uint32_t)0x00000080) 59 | 60 | /* CFR register bit mask */ 61 | #define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) 62 | #define CFR_W_Mask ((uint32_t)0xFFFFFF80) 63 | #define BIT_Mask ((uint8_t)0x7F) 64 | 65 | /** 66 | * @} 67 | */ 68 | 69 | /** @defgroup WWDG_Private_Macros 70 | * @{ 71 | */ 72 | 73 | /** 74 | * @} 75 | */ 76 | 77 | /** @defgroup WWDG_Private_Variables 78 | * @{ 79 | */ 80 | 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @defgroup WWDG_Private_FunctionPrototypes 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /** @defgroup WWDG_Private_Functions 94 | * @{ 95 | */ 96 | 97 | /** 98 | * @brief Deinitializes the WWDG peripheral registers to their default reset values. 99 | * @param None 100 | * @retval None 101 | */ 102 | void WWDG_DeInit(void) 103 | { 104 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 105 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 106 | } 107 | 108 | /** 109 | * @brief Sets the WWDG Prescaler. 110 | * @param WWDG_Prescaler: specifies the WWDG Prescaler. 111 | * This parameter can be one of the following values: 112 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 113 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 114 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 115 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 116 | * @retval None 117 | */ 118 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 119 | { 120 | uint32_t tmpreg = 0; 121 | /* Check the parameters */ 122 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); 123 | /* Clear WDGTB[1:0] bits */ 124 | tmpreg = WWDG->CFR & CFR_WDGTB_Mask; 125 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ 126 | tmpreg |= WWDG_Prescaler; 127 | /* Store the new value */ 128 | WWDG->CFR = tmpreg; 129 | } 130 | 131 | /** 132 | * @brief Sets the WWDG window value. 133 | * @param WindowValue: specifies the window value to be compared to the downcounter. 134 | * This parameter value must be lower than 0x80. 135 | * @retval None 136 | */ 137 | void WWDG_SetWindowValue(uint8_t WindowValue) 138 | { 139 | __IO uint32_t tmpreg = 0; 140 | 141 | /* Check the parameters */ 142 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); 143 | /* Clear W[6:0] bits */ 144 | 145 | tmpreg = WWDG->CFR & CFR_W_Mask; 146 | 147 | /* Set W[6:0] bits according to WindowValue value */ 148 | tmpreg |= WindowValue & (uint32_t) BIT_Mask; 149 | 150 | /* Store the new value */ 151 | WWDG->CFR = tmpreg; 152 | } 153 | 154 | /** 155 | * @brief Enables the WWDG Early Wakeup interrupt(EWI). 156 | * @param None 157 | * @retval None 158 | */ 159 | void WWDG_EnableIT(void) 160 | { 161 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; 162 | } 163 | 164 | /** 165 | * @brief Sets the WWDG counter value. 166 | * @param Counter: specifies the watchdog counter value. 167 | * This parameter must be a number between 0x40 and 0x7F. 168 | * @retval None 169 | */ 170 | void WWDG_SetCounter(uint8_t Counter) 171 | { 172 | /* Check the parameters */ 173 | assert_param(IS_WWDG_COUNTER(Counter)); 174 | /* Write to T[6:0] bits to configure the counter value, no need to do 175 | a read-modify-write; writing a 0 to WDGA bit does nothing */ 176 | WWDG->CR = Counter & BIT_Mask; 177 | } 178 | 179 | /** 180 | * @brief Enables WWDG and load the counter value. 181 | * @param Counter: specifies the watchdog counter value. 182 | * This parameter must be a number between 0x40 and 0x7F. 183 | * @retval None 184 | */ 185 | void WWDG_Enable(uint8_t Counter) 186 | { 187 | /* Check the parameters */ 188 | assert_param(IS_WWDG_COUNTER(Counter)); 189 | WWDG->CR = CR_WDGA_Set | Counter; 190 | } 191 | 192 | /** 193 | * @brief Checks whether the Early Wakeup interrupt flag is set or not. 194 | * @param None 195 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) 196 | */ 197 | FlagStatus WWDG_GetFlagStatus(void) 198 | { 199 | return (FlagStatus)(WWDG->SR); 200 | } 201 | 202 | /** 203 | * @brief Clears Early Wakeup interrupt flag. 204 | * @param None 205 | * @retval None 206 | */ 207 | void WWDG_ClearFlag(void) 208 | { 209 | WWDG->SR = (uint32_t)RESET; 210 | } 211 | 212 | /** 213 | * @} 214 | */ 215 | 216 | /** 217 | * @} 218 | */ 219 | 220 | /** 221 | * @} 222 | */ 223 | 224 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 225 | -------------------------------------------------------------------------------- /DebugConfig/STM32F103C8_STM32F103C8.dbgconf: -------------------------------------------------------------------------------- 1 | // <<< Use Configuration Wizard in Context Menu >>> 2 | // Debug MCU Configuration 3 | // DBG_SLEEP 4 | // Debug Sleep Mode 5 | // 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled 6 | // 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK 7 | // DBG_STOP 8 | // Debug Stop Mode 9 | // 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks 10 | // 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active 11 | // DBG_STANDBY 12 | // Debug Standby Mode 13 | // 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. 14 | // 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active 15 | // DBG_IWDG_STOP 16 | // Debug independent watchdog stopped when core is halted 17 | // 0: The watchdog counter clock continues even if the core is halted 18 | // 1: The watchdog counter clock is stopped when the core is halted 19 | // DBG_WWDG_STOP 20 | // Debug window watchdog stopped when core is halted 21 | // 0: The window watchdog counter clock continues even if the core is halted 22 | // 1: The window watchdog counter clock is stopped when the core is halted 23 | // DBG_TIM1_STOP 24 | // Timer 1 counter stopped when core is halted 25 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 26 | // 1: The clock of the involved Timer counter is stopped when the core is halted 27 | // DBG_TIM2_STOP 28 | // Timer 2 counter stopped when core is halted 29 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 30 | // 1: The clock of the involved Timer counter is stopped when the core is halted 31 | // DBG_TIM3_STOP 32 | // Timer 3 counter stopped when core is halted 33 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 34 | // 1: The clock of the involved Timer counter is stopped when the core is halted 35 | // DBG_TIM4_STOP 36 | // Timer 4 counter stopped when core is halted 37 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 38 | // 1: The clock of the involved Timer counter is stopped when the core is halted 39 | // DBG_CAN1_STOP 40 | // Debug CAN1 stopped when Core is halted 41 | // 0: Same behavior as in normal mode 42 | // 1: CAN1 receive registers are frozen 43 | // DBG_I2C1_SMBUS_TIMEOUT 44 | // I2C1 SMBUS timeout mode stopped when Core is halted 45 | // 0: Same behavior as in normal mode 46 | // 1: The SMBUS timeout is frozen 47 | // DBG_I2C2_SMBUS_TIMEOUT 48 | // I2C2 SMBUS timeout mode stopped when Core is halted 49 | // 0: Same behavior as in normal mode 50 | // 1: The SMBUS timeout is frozen 51 | // DBG_TIM8_STOP 52 | // Timer 8 counter stopped when core is halted 53 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 54 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 55 | // DBG_TIM5_STOP 56 | // Timer 5 counter stopped when core is halted 57 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 58 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 59 | // DBG_TIM6_STOP 60 | // Timer 6 counter stopped when core is halted 61 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 62 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 63 | // DBG_TIM7_STOP 64 | // Timer 7 counter stopped when core is halted 65 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 66 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 67 | // DBG_CAN2_STOP 68 | // Debug CAN2 stopped when Core is halted 69 | // 0: Same behavior as in normal mode 70 | // 1: CAN2 receive registers are frozen 71 | // DBG_TIM12_STOP 72 | // Timer 12 counter stopped when core is halted 73 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 74 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 75 | // DBG_TIM13_STOP 76 | // Timer 13 counter stopped when core is halted 77 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 78 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 79 | // DBG_TIM14_STOP 80 | // Timer 14 counter stopped when core is halted 81 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 82 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 83 | // DBG_TIM9_STOP 84 | // Timer 9 counter stopped when core is halted 85 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 86 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 87 | // DBG_TIM10_STOP 88 | // Timer 10 counter stopped when core is halted 89 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 90 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 91 | // DBG_TIM11_STOP 92 | // Timer 11 counter stopped when core is halted 93 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 94 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 95 | // 96 | DbgMCU_CR = 0x00000007; 97 | // <<< end of configuration section >>> -------------------------------------------------------------------------------- /DebugConfig/OFFLINE_DOWNLOAD_STM32F103C8.dbgconf: -------------------------------------------------------------------------------- 1 | // <<< Use Configuration Wizard in Context Menu >>> 2 | // Debug MCU Configuration 3 | // DBG_SLEEP 4 | // Debug Sleep Mode 5 | // 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled 6 | // 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK 7 | // DBG_STOP 8 | // Debug Stop Mode 9 | // 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks 10 | // 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active 11 | // DBG_STANDBY 12 | // Debug Standby Mode 13 | // 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. 14 | // 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active 15 | // DBG_IWDG_STOP 16 | // Debug independent watchdog stopped when core is halted 17 | // 0: The watchdog counter clock continues even if the core is halted 18 | // 1: The watchdog counter clock is stopped when the core is halted 19 | // DBG_WWDG_STOP 20 | // Debug window watchdog stopped when core is halted 21 | // 0: The window watchdog counter clock continues even if the core is halted 22 | // 1: The window watchdog counter clock is stopped when the core is halted 23 | // DBG_TIM1_STOP 24 | // Timer 1 counter stopped when core is halted 25 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 26 | // 1: The clock of the involved Timer counter is stopped when the core is halted 27 | // DBG_TIM2_STOP 28 | // Timer 2 counter stopped when core is halted 29 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 30 | // 1: The clock of the involved Timer counter is stopped when the core is halted 31 | // DBG_TIM3_STOP 32 | // Timer 3 counter stopped when core is halted 33 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 34 | // 1: The clock of the involved Timer counter is stopped when the core is halted 35 | // DBG_TIM4_STOP 36 | // Timer 4 counter stopped when core is halted 37 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 38 | // 1: The clock of the involved Timer counter is stopped when the core is halted 39 | // DBG_CAN1_STOP 40 | // Debug CAN1 stopped when Core is halted 41 | // 0: Same behavior as in normal mode 42 | // 1: CAN1 receive registers are frozen 43 | // DBG_I2C1_SMBUS_TIMEOUT 44 | // I2C1 SMBUS timeout mode stopped when Core is halted 45 | // 0: Same behavior as in normal mode 46 | // 1: The SMBUS timeout is frozen 47 | // DBG_I2C2_SMBUS_TIMEOUT 48 | // I2C2 SMBUS timeout mode stopped when Core is halted 49 | // 0: Same behavior as in normal mode 50 | // 1: The SMBUS timeout is frozen 51 | // DBG_TIM8_STOP 52 | // Timer 8 counter stopped when core is halted 53 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 54 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 55 | // DBG_TIM5_STOP 56 | // Timer 5 counter stopped when core is halted 57 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 58 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 59 | // DBG_TIM6_STOP 60 | // Timer 6 counter stopped when core is halted 61 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 62 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 63 | // DBG_TIM7_STOP 64 | // Timer 7 counter stopped when core is halted 65 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 66 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 67 | // DBG_CAN2_STOP 68 | // Debug CAN2 stopped when Core is halted 69 | // 0: Same behavior as in normal mode 70 | // 1: CAN2 receive registers are frozen 71 | // DBG_TIM12_STOP 72 | // Timer 12 counter stopped when core is halted 73 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 74 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 75 | // DBG_TIM13_STOP 76 | // Timer 13 counter stopped when core is halted 77 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 78 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 79 | // DBG_TIM14_STOP 80 | // Timer 14 counter stopped when core is halted 81 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 82 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 83 | // DBG_TIM9_STOP 84 | // Timer 9 counter stopped when core is halted 85 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 86 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 87 | // DBG_TIM10_STOP 88 | // Timer 10 counter stopped when core is halted 89 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 90 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 91 | // DBG_TIM11_STOP 92 | // Timer 11 counter stopped when core is halted 93 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 94 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 95 | // 96 | DbgMCU_CR = 0x00000007; 97 | // <<< end of configuration section >>> -------------------------------------------------------------------------------- /DebugConfig/Offline_downloader_STM32F103C8.dbgconf: -------------------------------------------------------------------------------- 1 | // <<< Use Configuration Wizard in Context Menu >>> 2 | // Debug MCU Configuration 3 | // DBG_SLEEP 4 | // Debug Sleep Mode 5 | // 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled 6 | // 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK 7 | // DBG_STOP 8 | // Debug Stop Mode 9 | // 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks 10 | // 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active 11 | // DBG_STANDBY 12 | // Debug Standby Mode 13 | // 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. 14 | // 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active 15 | // DBG_IWDG_STOP 16 | // Debug independent watchdog stopped when core is halted 17 | // 0: The watchdog counter clock continues even if the core is halted 18 | // 1: The watchdog counter clock is stopped when the core is halted 19 | // DBG_WWDG_STOP 20 | // Debug window watchdog stopped when core is halted 21 | // 0: The window watchdog counter clock continues even if the core is halted 22 | // 1: The window watchdog counter clock is stopped when the core is halted 23 | // DBG_TIM1_STOP 24 | // Timer 1 counter stopped when core is halted 25 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 26 | // 1: The clock of the involved Timer counter is stopped when the core is halted 27 | // DBG_TIM2_STOP 28 | // Timer 2 counter stopped when core is halted 29 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 30 | // 1: The clock of the involved Timer counter is stopped when the core is halted 31 | // DBG_TIM3_STOP 32 | // Timer 3 counter stopped when core is halted 33 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 34 | // 1: The clock of the involved Timer counter is stopped when the core is halted 35 | // DBG_TIM4_STOP 36 | // Timer 4 counter stopped when core is halted 37 | // 0: The clock of the involved Timer Counter is fed even if the core is halted 38 | // 1: The clock of the involved Timer counter is stopped when the core is halted 39 | // DBG_CAN1_STOP 40 | // Debug CAN1 stopped when Core is halted 41 | // 0: Same behavior as in normal mode 42 | // 1: CAN1 receive registers are frozen 43 | // DBG_I2C1_SMBUS_TIMEOUT 44 | // I2C1 SMBUS timeout mode stopped when Core is halted 45 | // 0: Same behavior as in normal mode 46 | // 1: The SMBUS timeout is frozen 47 | // DBG_I2C2_SMBUS_TIMEOUT 48 | // I2C2 SMBUS timeout mode stopped when Core is halted 49 | // 0: Same behavior as in normal mode 50 | // 1: The SMBUS timeout is frozen 51 | // DBG_TIM8_STOP 52 | // Timer 8 counter stopped when core is halted 53 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 54 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 55 | // DBG_TIM5_STOP 56 | // Timer 5 counter stopped when core is halted 57 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 58 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 59 | // DBG_TIM6_STOP 60 | // Timer 6 counter stopped when core is halted 61 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 62 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 63 | // DBG_TIM7_STOP 64 | // Timer 7 counter stopped when core is halted 65 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 66 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 67 | // DBG_CAN2_STOP 68 | // Debug CAN2 stopped when Core is halted 69 | // 0: Same behavior as in normal mode 70 | // 1: CAN2 receive registers are frozen 71 | // DBG_TIM12_STOP 72 | // Timer 12 counter stopped when core is halted 73 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 74 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 75 | // DBG_TIM13_STOP 76 | // Timer 13 counter stopped when core is halted 77 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 78 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 79 | // DBG_TIM14_STOP 80 | // Timer 14 counter stopped when core is halted 81 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 82 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 83 | // DBG_TIM9_STOP 84 | // Timer 9 counter stopped when core is halted 85 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 86 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 87 | // DBG_TIM10_STOP 88 | // Timer 10 counter stopped when core is halted 89 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 90 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 91 | // DBG_TIM11_STOP 92 | // Timer 11 counter stopped when core is halted 93 | // 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. 94 | // 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). 95 | // 96 | DbgMCU_CR = 0x00000007; 97 | // <<< end of configuration section >>> -------------------------------------------------------------------------------- /src/DAP/debug_cm.h: -------------------------------------------------------------------------------- 1 | /** 2 | * @file debug_cm.h 3 | * @brief Access to ARM DAP (Cortex-M) using CMSIS-DAP protocol 4 | */ 5 | #ifndef DEBUG_CM_H 6 | #define DEBUG_CM_H 7 | 8 | #include "DAP.h" 9 | 10 | 11 | // Abort Register definitions 12 | #define DAPABORT 0x00000001 // DAP Abort 13 | #define STKCMPCLR 0x00000002 // Clear STICKYCMP Flag (SW Only) 14 | #define STKERRCLR 0x00000004 // Clear STICKYERR Flag (SW Only) 15 | #define WDERRCLR 0x00000008 // Clear WDATAERR Flag (SW Only) 16 | #define ORUNERRCLR 0x00000010 // Clear STICKYORUN Flag (SW Only) 17 | 18 | // Debug Control and Status definitions 19 | #define ORUNDETECT 0x00000001 // Overrun Detect 20 | #define STICKYORUN 0x00000002 // Sticky Overrun 21 | #define TRNMODE 0x0000000C // Transfer Mode Mask 22 | #define TRNNORMAL 0x00000000 // Transfer Mode: Normal 23 | #define TRNVERIFY 0x00000004 // Transfer Mode: Pushed Verify 24 | #define TRNCOMPARE 0x00000008 // Transfer Mode: Pushed Compare 25 | #define STICKYCMP 0x00000010 // Sticky Compare 26 | #define STICKYERR 0x00000020 // Sticky Error 27 | #define READOK 0x00000040 // Read OK (SW Only) 28 | #define WDATAERR 0x00000080 // Write Data Error (SW Only) 29 | #define MASKLANE 0x00000F00 // Mask Lane Mask 30 | #define MASKLANE0 0x00000100 // Mask Lane 0 31 | #define MASKLANE1 0x00000200 // Mask Lane 1 32 | #define MASKLANE2 0x00000400 // Mask Lane 2 33 | #define MASKLANE3 0x00000800 // Mask Lane 3 34 | #define TRNCNT 0x001FF000 // Transaction Counter Mask 35 | #define CDBGRSTREQ 0x04000000 // Debug Reset Request 36 | #define CDBGRSTACK 0x08000000 // Debug Reset Acknowledge 37 | #define CDBGPWRUPREQ 0x10000000 // Debug Power-up Request 38 | #define CDBGPWRUPACK 0x20000000 // Debug Power-up Acknowledge 39 | #define CSYSPWRUPREQ 0x40000000 // System Power-up Request 40 | #define CSYSPWRUPACK 0x80000000 // System Power-up Acknowledge 41 | 42 | // Debug Select Register definitions 43 | #define CTRLSEL 0x00000001 // CTRLSEL (SW Only) 44 | #define APBANKSEL 0x000000F0 // APBANKSEL Mask 45 | #define APSEL 0xFF000000 // APSEL Mask 46 | 47 | // Access Port Register Addresses 48 | #define AP_CSW 0x00 // Control and Status Word 49 | #define AP_TAR 0x04 // Transfer Address 50 | #define AP_DRW 0x0C // Data Read/Write 51 | #define AP_BD0 0x10 // Banked Data 0 52 | #define AP_BD1 0x14 // Banked Data 1 53 | #define AP_BD2 0x18 // Banked Data 2 54 | #define AP_BD3 0x1C // Banked Data 3 55 | #define AP_ROM 0xF8 // Debug ROM Address 56 | #define AP_IDR 0xFC // Identification Register 57 | 58 | // AP Control and Status Word definitions 59 | #define CSW_SIZE 0x00000007 // Access Size: Selection Mask 60 | #define CSW_SIZE8 0x00000000 // Access Size: 8-bit 61 | #define CSW_SIZE16 0x00000001 // Access Size: 16-bit 62 | #define CSW_SIZE32 0x00000002 // Access Size: 32-bit 63 | #define CSW_ADDRINC 0x00000030 // Auto Address Increment Mask 64 | #define CSW_NADDRINC 0x00000000 // No Address Increment 65 | #define CSW_SADDRINC 0x00000010 // Single Address Increment 66 | #define CSW_PADDRINC 0x00000020 // Packed Address Increment 67 | #define CSW_DBGSTAT 0x00000040 // Debug Status 68 | #define CSW_TINPROG 0x00000080 // Transfer in progress 69 | #define CSW_HPROT 0x02000000 // User/Privilege Control 70 | #define CSW_MSTRTYPE 0x20000000 // Master Type Mask 71 | #define CSW_MSTRCORE 0x00000000 // Master Type: Core 72 | #define CSW_MSTRDBG 0x20000000 // Master Type: Debug 73 | #define CSW_RESERVED 0x01000000 // Reserved Value 74 | 75 | // Core Debug Register Address Offsets 76 | #define DBG_OFS 0x0DF0 // Debug Register Offset inside NVIC 77 | #define DBG_HCSR_OFS 0x00 // Debug Halting Control & Status Register 78 | #define DBG_CRSR_OFS 0x04 // Debug Core Register Selector Register 79 | #define DBG_CRDR_OFS 0x08 // Debug Core Register Data Register 80 | #define DBG_EMCR_OFS 0x0C // Debug Exception & Monitor Control Register 81 | 82 | // Core Debug Register Addresses 83 | #define DBG_HCSR (DBG_Addr + DBG_HCSR_OFS) 84 | #define DBG_CRSR (DBG_Addr + DBG_CRSR_OFS) 85 | #define DBG_CRDR (DBG_Addr + DBG_CRDR_OFS) 86 | #define DBG_EMCR (DBG_Addr + DBG_EMCR_OFS) 87 | 88 | // Debug Halting Control and Status Register definitions 89 | #define C_DEBUGEN 0x00000001 // Debug Enable 90 | #define C_HALT 0x00000002 // Halt 91 | #define C_STEP 0x00000004 // Step 92 | #define C_MASKINTS 0x00000008 // Mask Interrupts 93 | #define C_SNAPSTALL 0x00000020 // Snap Stall 94 | #define S_REGRDY 0x00010000 // Register R/W Ready Flag 95 | #define S_HALT 0x00020000 // Halt Flag 96 | #define S_SLEEP 0x00040000 // Sleep Flag 97 | #define S_LOCKUP 0x00080000 // Lockup Flag 98 | #define S_RETIRE_ST 0x01000000 // Sticky Retire Flag 99 | #define S_RESET_ST 0x02000000 // Sticky Reset Flag 100 | #define DBGKEY 0xA05F0000 // Debug Key 101 | 102 | // Debug Exception and Monitor Control Register definitions 103 | #define VC_CORERESET 0x00000001 // Reset Vector Catch 104 | #define VC_MMERR 0x00000010 // Debug Trap on MMU Fault 105 | #define VC_NOCPERR 0x00000020 // Debug Trap on No Coprocessor Fault 106 | #define VC_CHKERR 0x00000040 // Debug Trap on Checking Error Fault 107 | #define VC_STATERR 0x00000080 // Debug Trap on State Error Fault 108 | #define VC_BUSERR 0x00000100 // Debug Trap on Bus Error Fault 109 | #define VC_INTERR 0x00000200 // Debug Trap on Interrupt Error Fault 110 | #define VC_HARDERR 0x00000400 // Debug Trap on Hard Fault 111 | #define MON_EN 0x00010000 // Monitor Enable 112 | #define MON_PEND 0x00020000 // Monitor Pend 113 | #define MON_STEP 0x00040000 // Monitor Step 114 | #define MON_REQ 0x00080000 // Monitor Request 115 | #define TRCENA 0x01000000 // Trace Enable (DWT, ITM, ETM, TPIU) 116 | 117 | // NVIC: Interrupt Controller Type Register 118 | #define NVIC_ICT (NVIC_Addr + 0x0004) 119 | #define INTLINESNUM 0x0000001F // Interrupt Line Numbers 120 | 121 | // NVIC: CPUID Base Register 122 | #define NVIC_CPUID (NVIC_Addr + 0x0D00) 123 | #define CPUID_PARTNO 0x0000FFF0 // Part Number Mask 124 | #define CPUID_REVISION 0x0000000F // Revision Mask 125 | #define CPUID_VARIANT 0x00F00000 // Variant Mask 126 | 127 | // NVIC: Application Interrupt/Reset Control Register 128 | #define NVIC_AIRCR (NVIC_Addr + 0x0D0C) 129 | #define VECTRESET 0x00000001 // Reset Cortex-M (except Debug) 130 | #define VECTCLRACTIVE 0x00000002 // Clear Active Vector Bit 131 | #define SYSRESETREQ 0x00000004 // Reset System (except Debug) 132 | #define VECTKEY 0x05FA0000 // Write Key 133 | 134 | // NVIC: Debug Fault Status Register 135 | #define NVIC_DFSR (NVIC_Addr + 0x0D30) 136 | #define HALTED 0x00000001 // Halt Flag 137 | #define BKPT 0x00000002 // BKPT Flag 138 | #define DWTTRAP 0x00000004 // DWT Match 139 | #define VCATCH 0x00000008 // Vector Catch Flag 140 | #define EXTERNAL 0x00000010 // External Debug Request 141 | 142 | 143 | #endif 144 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_cec.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_cec.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the CEC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_CEC_H 25 | #define __STM32F10x_CEC_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup CEC 39 | * @{ 40 | */ 41 | 42 | 43 | /** @defgroup CEC_Exported_Types 44 | * @{ 45 | */ 46 | 47 | /** 48 | * @brief CEC Init structure definition 49 | */ 50 | typedef struct 51 | { 52 | uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 53 | This parameter can be a value of @ref CEC_BitTiming_Mode */ 54 | uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 55 | This parameter can be a value of @ref CEC_BitPeriod_Mode */ 56 | }CEC_InitTypeDef; 57 | 58 | /** 59 | * @} 60 | */ 61 | 62 | /** @defgroup CEC_Exported_Constants 63 | * @{ 64 | */ 65 | 66 | /** @defgroup CEC_BitTiming_Mode 67 | * @{ 68 | */ 69 | #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ 70 | #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ 71 | 72 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ 73 | ((MODE) == CEC_BitTimingErrFreeMode)) 74 | /** 75 | * @} 76 | */ 77 | 78 | /** @defgroup CEC_BitPeriod_Mode 79 | * @{ 80 | */ 81 | #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ 82 | #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ 83 | 84 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ 85 | ((MODE) == CEC_BitPeriodFlexibleMode)) 86 | /** 87 | * @} 88 | */ 89 | 90 | 91 | /** @defgroup CEC_interrupts_definition 92 | * @{ 93 | */ 94 | #define CEC_IT_TERR CEC_CSR_TERR 95 | #define CEC_IT_TBTRF CEC_CSR_TBTRF 96 | #define CEC_IT_RERR CEC_CSR_RERR 97 | #define CEC_IT_RBTF CEC_CSR_RBTF 98 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ 99 | ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) 100 | /** 101 | * @} 102 | */ 103 | 104 | 105 | /** @defgroup CEC_Own_Address 106 | * @{ 107 | */ 108 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) 109 | /** 110 | * @} 111 | */ 112 | 113 | /** @defgroup CEC_Prescaler 114 | * @{ 115 | */ 116 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) 117 | 118 | /** 119 | * @} 120 | */ 121 | 122 | /** @defgroup CEC_flags_definition 123 | * @{ 124 | */ 125 | 126 | /** 127 | * @brief ESR register flags 128 | */ 129 | #define CEC_FLAG_BTE ((uint32_t)0x10010000) 130 | #define CEC_FLAG_BPE ((uint32_t)0x10020000) 131 | #define CEC_FLAG_RBTFE ((uint32_t)0x10040000) 132 | #define CEC_FLAG_SBE ((uint32_t)0x10080000) 133 | #define CEC_FLAG_ACKE ((uint32_t)0x10100000) 134 | #define CEC_FLAG_LINE ((uint32_t)0x10200000) 135 | #define CEC_FLAG_TBTFE ((uint32_t)0x10400000) 136 | 137 | /** 138 | * @brief CSR register flags 139 | */ 140 | #define CEC_FLAG_TEOM ((uint32_t)0x00000002) 141 | #define CEC_FLAG_TERR ((uint32_t)0x00000004) 142 | #define CEC_FLAG_TBTRF ((uint32_t)0x00000008) 143 | #define CEC_FLAG_RSOM ((uint32_t)0x00000010) 144 | #define CEC_FLAG_REOM ((uint32_t)0x00000020) 145 | #define CEC_FLAG_RERR ((uint32_t)0x00000040) 146 | #define CEC_FLAG_RBTF ((uint32_t)0x00000080) 147 | 148 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) 149 | 150 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ 151 | ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ 152 | ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ 153 | ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ 154 | ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ 155 | ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ 156 | ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) 157 | 158 | /** 159 | * @} 160 | */ 161 | 162 | /** 163 | * @} 164 | */ 165 | 166 | /** @defgroup CEC_Exported_Macros 167 | * @{ 168 | */ 169 | 170 | /** 171 | * @} 172 | */ 173 | 174 | /** @defgroup CEC_Exported_Functions 175 | * @{ 176 | */ 177 | void CEC_DeInit(void); 178 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); 179 | void CEC_Cmd(FunctionalState NewState); 180 | void CEC_ITConfig(FunctionalState NewState); 181 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); 182 | void CEC_SetPrescaler(uint16_t CEC_Prescaler); 183 | void CEC_SendDataByte(uint8_t Data); 184 | uint8_t CEC_ReceiveDataByte(void); 185 | void CEC_StartOfMessage(void); 186 | void CEC_EndOfMessageCmd(FunctionalState NewState); 187 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); 188 | void CEC_ClearFlag(uint32_t CEC_FLAG); 189 | ITStatus CEC_GetITStatus(uint8_t CEC_IT); 190 | void CEC_ClearITPendingBit(uint16_t CEC_IT); 191 | 192 | #ifdef __cplusplus 193 | } 194 | #endif 195 | 196 | #endif /* __STM32F10x_CEC_H */ 197 | 198 | /** 199 | * @} 200 | */ 201 | 202 | /** 203 | * @} 204 | */ 205 | 206 | /** 207 | * @} 208 | */ 209 | 210 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 211 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_exti.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the EXTI firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_EXTI_H 25 | #define __STM32F10x_EXTI_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup EXTI 39 | * @{ 40 | */ 41 | 42 | /** @defgroup EXTI_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief EXTI mode enumeration 48 | */ 49 | 50 | typedef enum 51 | { 52 | EXTI_Mode_Interrupt = 0x00, 53 | EXTI_Mode_Event = 0x04 54 | }EXTIMode_TypeDef; 55 | 56 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) 57 | 58 | /** 59 | * @brief EXTI Trigger enumeration 60 | */ 61 | 62 | typedef enum 63 | { 64 | EXTI_Trigger_Rising = 0x08, 65 | EXTI_Trigger_Falling = 0x0C, 66 | EXTI_Trigger_Rising_Falling = 0x10 67 | }EXTITrigger_TypeDef; 68 | 69 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ 70 | ((TRIGGER) == EXTI_Trigger_Falling) || \ 71 | ((TRIGGER) == EXTI_Trigger_Rising_Falling)) 72 | /** 73 | * @brief EXTI Init Structure definition 74 | */ 75 | 76 | typedef struct 77 | { 78 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. 79 | This parameter can be any combination of @ref EXTI_Lines */ 80 | 81 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. 82 | This parameter can be a value of @ref EXTIMode_TypeDef */ 83 | 84 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. 85 | This parameter can be a value of @ref EXTIMode_TypeDef */ 86 | 87 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. 88 | This parameter can be set either to ENABLE or DISABLE */ 89 | }EXTI_InitTypeDef; 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @defgroup EXTI_Exported_Constants 96 | * @{ 97 | */ 98 | 99 | /** @defgroup EXTI_Lines 100 | * @{ 101 | */ 102 | 103 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ 104 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ 105 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ 106 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ 107 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ 108 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ 109 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ 110 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ 111 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ 112 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ 113 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ 114 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ 115 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ 116 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ 117 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ 118 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ 119 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ 120 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ 121 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS 122 | Wakeup from suspend event */ 123 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ 124 | 125 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) 126 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ 127 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ 128 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ 129 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ 130 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ 131 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ 132 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ 133 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ 134 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ 135 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) 136 | 137 | 138 | /** 139 | * @} 140 | */ 141 | 142 | /** 143 | * @} 144 | */ 145 | 146 | /** @defgroup EXTI_Exported_Macros 147 | * @{ 148 | */ 149 | 150 | /** 151 | * @} 152 | */ 153 | 154 | /** @defgroup EXTI_Exported_Functions 155 | * @{ 156 | */ 157 | 158 | void EXTI_DeInit(void); 159 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); 160 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); 161 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 162 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 163 | void EXTI_ClearFlag(uint32_t EXTI_Line); 164 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 165 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 166 | 167 | #ifdef __cplusplus 168 | } 169 | #endif 170 | 171 | #endif /* __STM32F10x_EXTI_H */ 172 | /** 173 | * @} 174 | */ 175 | 176 | /** 177 | * @} 178 | */ 179 | 180 | /** 181 | * @} 182 | */ 183 | 184 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 185 | -------------------------------------------------------------------------------- /src/CSL/CMSIS/CoreSupport/arm_common_tables.h: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved. 3 | * 4 | * $Date: 31. July 2014 5 | * $Revision: V1.4.4 6 | * 7 | * Project: CMSIS DSP Library 8 | * Title: arm_common_tables.h 9 | * 10 | * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 11 | * 12 | * Target Processor: Cortex-M4/Cortex-M3 13 | * 14 | * Redistribution and use in source and binary forms, with or without 15 | * modification, are permitted provided that the following conditions 16 | * are met: 17 | * - Redistributions of source code must retain the above copyright 18 | * notice, this list of conditions and the following disclaimer. 19 | * - Redistributions in binary form must reproduce the above copyright 20 | * notice, this list of conditions and the following disclaimer in 21 | * the documentation and/or other materials provided with the 22 | * distribution. 23 | * - Neither the name of ARM LIMITED nor the names of its contributors 24 | * may be used to endorse or promote products derived from this 25 | * software without specific prior written permission. 26 | * 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 | * POSSIBILITY OF SUCH DAMAGE. 39 | * -------------------------------------------------------------------- */ 40 | 41 | #ifndef _ARM_COMMON_TABLES_H 42 | #define _ARM_COMMON_TABLES_H 43 | 44 | #include "arm_math.h" 45 | 46 | extern const uint16_t armBitRevTable[1024]; 47 | extern const q15_t armRecipTableQ15[64]; 48 | extern const q31_t armRecipTableQ31[64]; 49 | //extern const q31_t realCoefAQ31[1024]; 50 | //extern const q31_t realCoefBQ31[1024]; 51 | extern const float32_t twiddleCoef_16[32]; 52 | extern const float32_t twiddleCoef_32[64]; 53 | extern const float32_t twiddleCoef_64[128]; 54 | extern const float32_t twiddleCoef_128[256]; 55 | extern const float32_t twiddleCoef_256[512]; 56 | extern const float32_t twiddleCoef_512[1024]; 57 | extern const float32_t twiddleCoef_1024[2048]; 58 | extern const float32_t twiddleCoef_2048[4096]; 59 | extern const float32_t twiddleCoef_4096[8192]; 60 | #define twiddleCoef twiddleCoef_4096 61 | extern const q31_t twiddleCoef_16_q31[24]; 62 | extern const q31_t twiddleCoef_32_q31[48]; 63 | extern const q31_t twiddleCoef_64_q31[96]; 64 | extern const q31_t twiddleCoef_128_q31[192]; 65 | extern const q31_t twiddleCoef_256_q31[384]; 66 | extern const q31_t twiddleCoef_512_q31[768]; 67 | extern const q31_t twiddleCoef_1024_q31[1536]; 68 | extern const q31_t twiddleCoef_2048_q31[3072]; 69 | extern const q31_t twiddleCoef_4096_q31[6144]; 70 | extern const q15_t twiddleCoef_16_q15[24]; 71 | extern const q15_t twiddleCoef_32_q15[48]; 72 | extern const q15_t twiddleCoef_64_q15[96]; 73 | extern const q15_t twiddleCoef_128_q15[192]; 74 | extern const q15_t twiddleCoef_256_q15[384]; 75 | extern const q15_t twiddleCoef_512_q15[768]; 76 | extern const q15_t twiddleCoef_1024_q15[1536]; 77 | extern const q15_t twiddleCoef_2048_q15[3072]; 78 | extern const q15_t twiddleCoef_4096_q15[6144]; 79 | extern const float32_t twiddleCoef_rfft_32[32]; 80 | extern const float32_t twiddleCoef_rfft_64[64]; 81 | extern const float32_t twiddleCoef_rfft_128[128]; 82 | extern const float32_t twiddleCoef_rfft_256[256]; 83 | extern const float32_t twiddleCoef_rfft_512[512]; 84 | extern const float32_t twiddleCoef_rfft_1024[1024]; 85 | extern const float32_t twiddleCoef_rfft_2048[2048]; 86 | extern const float32_t twiddleCoef_rfft_4096[4096]; 87 | 88 | 89 | /* floating-point bit reversal tables */ 90 | #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) 91 | #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) 92 | #define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) 93 | #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) 94 | #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) 95 | #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) 96 | #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) 97 | #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) 98 | #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) 99 | 100 | extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; 101 | extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; 102 | extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; 103 | extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; 104 | extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; 105 | extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; 106 | extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; 107 | extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; 108 | extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; 109 | 110 | /* fixed-point bit reversal tables */ 111 | #define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) 112 | #define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) 113 | #define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) 114 | #define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) 115 | #define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) 116 | #define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) 117 | #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) 118 | #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) 119 | #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) 120 | 121 | extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; 122 | extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; 123 | extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; 124 | extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; 125 | extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; 126 | extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; 127 | extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; 128 | extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; 129 | extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; 130 | 131 | /* Tables for Fast Math Sine and Cosine */ 132 | extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; 133 | extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; 134 | extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; 135 | 136 | #endif /* ARM_COMMON_TABLES_H */ 137 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/misc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the miscellaneous firmware functions (add-on 8 | * to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes ------------------------------------------------------------------*/ 24 | #include "misc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup MISC 31 | * @brief MISC driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup MISC_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup MISC_Private_Defines 44 | * @{ 45 | */ 46 | 47 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) 48 | /** 49 | * @} 50 | */ 51 | 52 | /** @defgroup MISC_Private_Macros 53 | * @{ 54 | */ 55 | 56 | /** 57 | * @} 58 | */ 59 | 60 | /** @defgroup MISC_Private_Variables 61 | * @{ 62 | */ 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup MISC_Private_FunctionPrototypes 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup MISC_Private_Functions 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @brief Configures the priority grouping: pre-emption priority and subpriority. 82 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length. 83 | * This parameter can be one of the following values: 84 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority 85 | * 4 bits for subpriority 86 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority 87 | * 3 bits for subpriority 88 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority 89 | * 2 bits for subpriority 90 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority 91 | * 1 bits for subpriority 92 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority 93 | * 0 bits for subpriority 94 | * @retval None 95 | */ 96 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 97 | { 98 | /* Check the parameters */ 99 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); 100 | 101 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ 102 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; 103 | } 104 | 105 | /** 106 | * @brief Initializes the NVIC peripheral according to the specified 107 | * parameters in the NVIC_InitStruct. 108 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains 109 | * the configuration information for the specified NVIC peripheral. 110 | * @retval None 111 | */ 112 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) 113 | { 114 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; 115 | 116 | /* Check the parameters */ 117 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); 118 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); 119 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); 120 | 121 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 122 | { 123 | /* Compute the Corresponding IRQ Priority --------------------------------*/ 124 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 125 | tmppre = (0x4 - tmppriority); 126 | tmpsub = tmpsub >> tmppriority; 127 | 128 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 129 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; 130 | tmppriority = tmppriority << 0x04; 131 | 132 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 133 | 134 | /* Enable the Selected IRQ Channels --------------------------------------*/ 135 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 136 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 137 | } 138 | else 139 | { 140 | /* Disable the Selected IRQ Channels -------------------------------------*/ 141 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 142 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 143 | } 144 | } 145 | 146 | /** 147 | * @brief Sets the vector table location and Offset. 148 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. 149 | * This parameter can be one of the following values: 150 | * @arg NVIC_VectTab_RAM 151 | * @arg NVIC_VectTab_FLASH 152 | * @param Offset: Vector Table base offset field. This value must be a multiple 153 | * of 0x200. 154 | * @retval None 155 | */ 156 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) 157 | { 158 | /* Check the parameters */ 159 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); 160 | assert_param(IS_NVIC_OFFSET(Offset)); 161 | 162 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); 163 | } 164 | 165 | /** 166 | * @brief Selects the condition for the system to enter low power mode. 167 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. 168 | * This parameter can be one of the following values: 169 | * @arg NVIC_LP_SEVONPEND 170 | * @arg NVIC_LP_SLEEPDEEP 171 | * @arg NVIC_LP_SLEEPONEXIT 172 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. 173 | * @retval None 174 | */ 175 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) 176 | { 177 | /* Check the parameters */ 178 | assert_param(IS_NVIC_LP(LowPowerMode)); 179 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 180 | 181 | if (NewState != DISABLE) 182 | { 183 | SCB->SCR |= LowPowerMode; 184 | } 185 | else 186 | { 187 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 188 | } 189 | } 190 | 191 | /** 192 | * @brief Configures the SysTick clock source. 193 | * @param SysTick_CLKSource: specifies the SysTick clock source. 194 | * This parameter can be one of the following values: 195 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. 196 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. 197 | * @retval None 198 | */ 199 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) 200 | { 201 | /* Check the parameters */ 202 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); 203 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 204 | { 205 | SysTick->CTRL |= SysTick_CLKSource_HCLK; 206 | } 207 | else 208 | { 209 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 210 | } 211 | } 212 | 213 | /** 214 | * @} 215 | */ 216 | 217 | /** 218 | * @} 219 | */ 220 | 221 | /** 222 | * @} 223 | */ 224 | 225 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 226 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_exti.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_exti.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the EXTI firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_exti.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup EXTI 30 | * @brief EXTI driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup EXTI_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup EXTI_Private_Defines 43 | * @{ 44 | */ 45 | 46 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ 47 | 48 | /** 49 | * @} 50 | */ 51 | 52 | /** @defgroup EXTI_Private_Macros 53 | * @{ 54 | */ 55 | 56 | /** 57 | * @} 58 | */ 59 | 60 | /** @defgroup EXTI_Private_Variables 61 | * @{ 62 | */ 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup EXTI_Private_FunctionPrototypes 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup EXTI_Private_Functions 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @brief Deinitializes the EXTI peripheral registers to their default reset values. 82 | * @param None 83 | * @retval None 84 | */ 85 | void EXTI_DeInit(void) 86 | { 87 | EXTI->IMR = 0x00000000; 88 | EXTI->EMR = 0x00000000; 89 | EXTI->RTSR = 0x00000000; 90 | EXTI->FTSR = 0x00000000; 91 | EXTI->PR = 0x000FFFFF; 92 | } 93 | 94 | /** 95 | * @brief Initializes the EXTI peripheral according to the specified 96 | * parameters in the EXTI_InitStruct. 97 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure 98 | * that contains the configuration information for the EXTI peripheral. 99 | * @retval None 100 | */ 101 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) 102 | { 103 | uint32_t tmp = 0; 104 | 105 | /* Check the parameters */ 106 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); 107 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); 108 | assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); 109 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); 110 | 111 | tmp = (uint32_t)EXTI_BASE; 112 | 113 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) 114 | { 115 | /* Clear EXTI line configuration */ 116 | EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; 117 | EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; 118 | 119 | tmp += EXTI_InitStruct->EXTI_Mode; 120 | 121 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 122 | 123 | /* Clear Rising Falling edge configuration */ 124 | EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; 125 | EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; 126 | 127 | /* Select the trigger for the selected external interrupts */ 128 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 129 | { 130 | /* Rising Falling edge */ 131 | EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; 132 | EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; 133 | } 134 | else 135 | { 136 | tmp = (uint32_t)EXTI_BASE; 137 | tmp += EXTI_InitStruct->EXTI_Trigger; 138 | 139 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 140 | } 141 | } 142 | else 143 | { 144 | tmp += EXTI_InitStruct->EXTI_Mode; 145 | 146 | /* Disable the selected external lines */ 147 | *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; 148 | } 149 | } 150 | 151 | /** 152 | * @brief Fills each EXTI_InitStruct member with its reset value. 153 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will 154 | * be initialized. 155 | * @retval None 156 | */ 157 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) 158 | { 159 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 160 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 161 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 162 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 163 | } 164 | 165 | /** 166 | * @brief Generates a Software interrupt. 167 | * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. 168 | * This parameter can be any combination of EXTI_Linex where x can be (0..19). 169 | * @retval None 170 | */ 171 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 172 | { 173 | /* Check the parameters */ 174 | assert_param(IS_EXTI_LINE(EXTI_Line)); 175 | 176 | EXTI->SWIER |= EXTI_Line; 177 | } 178 | 179 | /** 180 | * @brief Checks whether the specified EXTI line flag is set or not. 181 | * @param EXTI_Line: specifies the EXTI line flag to check. 182 | * This parameter can be: 183 | * @arg EXTI_Linex: External interrupt line x where x(0..19) 184 | * @retval The new state of EXTI_Line (SET or RESET). 185 | */ 186 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 187 | { 188 | FlagStatus bitstatus = RESET; 189 | /* Check the parameters */ 190 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 191 | 192 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 193 | { 194 | bitstatus = SET; 195 | } 196 | else 197 | { 198 | bitstatus = RESET; 199 | } 200 | return bitstatus; 201 | } 202 | 203 | /** 204 | * @brief Clears the EXTI's line pending flags. 205 | * @param EXTI_Line: specifies the EXTI lines flags to clear. 206 | * This parameter can be any combination of EXTI_Linex where x can be (0..19). 207 | * @retval None 208 | */ 209 | void EXTI_ClearFlag(uint32_t EXTI_Line) 210 | { 211 | /* Check the parameters */ 212 | assert_param(IS_EXTI_LINE(EXTI_Line)); 213 | 214 | EXTI->PR = EXTI_Line; 215 | } 216 | 217 | /** 218 | * @brief Checks whether the specified EXTI line is asserted or not. 219 | * @param EXTI_Line: specifies the EXTI line to check. 220 | * This parameter can be: 221 | * @arg EXTI_Linex: External interrupt line x where x(0..19) 222 | * @retval The new state of EXTI_Line (SET or RESET). 223 | */ 224 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 225 | { 226 | ITStatus bitstatus = RESET; 227 | uint32_t enablestatus = 0; 228 | /* Check the parameters */ 229 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 230 | 231 | enablestatus = EXTI->IMR & EXTI_Line; 232 | if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) 233 | { 234 | bitstatus = SET; 235 | } 236 | else 237 | { 238 | bitstatus = RESET; 239 | } 240 | return bitstatus; 241 | } 242 | 243 | /** 244 | * @brief Clears the EXTI's line pending bits. 245 | * @param EXTI_Line: specifies the EXTI lines to clear. 246 | * This parameter can be any combination of EXTI_Linex where x can be (0..19). 247 | * @retval None 248 | */ 249 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 250 | { 251 | /* Check the parameters */ 252 | assert_param(IS_EXTI_LINE(EXTI_Line)); 253 | 254 | EXTI->PR = EXTI_Line; 255 | } 256 | 257 | /** 258 | * @} 259 | */ 260 | 261 | /** 262 | * @} 263 | */ 264 | 265 | /** 266 | * @} 267 | */ 268 | 269 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 270 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_bkp.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the BKP firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __STM32F10x_BKP_H 25 | #define __STM32F10x_BKP_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup BKP 39 | * @{ 40 | */ 41 | 42 | /** @defgroup BKP_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup BKP_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup Tamper_Pin_active_level 55 | * @{ 56 | */ 57 | 58 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000) 59 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) 60 | #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ 61 | ((LEVEL) == BKP_TamperPinLevel_Low)) 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 67 | * @{ 68 | */ 69 | 70 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000) 71 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) 72 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) 73 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) 74 | #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ 75 | ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ 76 | ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ 77 | ((SOURCE) == BKP_RTCOutputSource_Second)) 78 | /** 79 | * @} 80 | */ 81 | 82 | /** @defgroup Data_Backup_Register 83 | * @{ 84 | */ 85 | 86 | #define BKP_DR1 ((uint16_t)0x0004) 87 | #define BKP_DR2 ((uint16_t)0x0008) 88 | #define BKP_DR3 ((uint16_t)0x000C) 89 | #define BKP_DR4 ((uint16_t)0x0010) 90 | #define BKP_DR5 ((uint16_t)0x0014) 91 | #define BKP_DR6 ((uint16_t)0x0018) 92 | #define BKP_DR7 ((uint16_t)0x001C) 93 | #define BKP_DR8 ((uint16_t)0x0020) 94 | #define BKP_DR9 ((uint16_t)0x0024) 95 | #define BKP_DR10 ((uint16_t)0x0028) 96 | #define BKP_DR11 ((uint16_t)0x0040) 97 | #define BKP_DR12 ((uint16_t)0x0044) 98 | #define BKP_DR13 ((uint16_t)0x0048) 99 | #define BKP_DR14 ((uint16_t)0x004C) 100 | #define BKP_DR15 ((uint16_t)0x0050) 101 | #define BKP_DR16 ((uint16_t)0x0054) 102 | #define BKP_DR17 ((uint16_t)0x0058) 103 | #define BKP_DR18 ((uint16_t)0x005C) 104 | #define BKP_DR19 ((uint16_t)0x0060) 105 | #define BKP_DR20 ((uint16_t)0x0064) 106 | #define BKP_DR21 ((uint16_t)0x0068) 107 | #define BKP_DR22 ((uint16_t)0x006C) 108 | #define BKP_DR23 ((uint16_t)0x0070) 109 | #define BKP_DR24 ((uint16_t)0x0074) 110 | #define BKP_DR25 ((uint16_t)0x0078) 111 | #define BKP_DR26 ((uint16_t)0x007C) 112 | #define BKP_DR27 ((uint16_t)0x0080) 113 | #define BKP_DR28 ((uint16_t)0x0084) 114 | #define BKP_DR29 ((uint16_t)0x0088) 115 | #define BKP_DR30 ((uint16_t)0x008C) 116 | #define BKP_DR31 ((uint16_t)0x0090) 117 | #define BKP_DR32 ((uint16_t)0x0094) 118 | #define BKP_DR33 ((uint16_t)0x0098) 119 | #define BKP_DR34 ((uint16_t)0x009C) 120 | #define BKP_DR35 ((uint16_t)0x00A0) 121 | #define BKP_DR36 ((uint16_t)0x00A4) 122 | #define BKP_DR37 ((uint16_t)0x00A8) 123 | #define BKP_DR38 ((uint16_t)0x00AC) 124 | #define BKP_DR39 ((uint16_t)0x00B0) 125 | #define BKP_DR40 ((uint16_t)0x00B4) 126 | #define BKP_DR41 ((uint16_t)0x00B8) 127 | #define BKP_DR42 ((uint16_t)0x00BC) 128 | 129 | #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ 130 | ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ 131 | ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ 132 | ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ 133 | ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ 134 | ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ 135 | ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ 136 | ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ 137 | ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ 138 | ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ 139 | ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ 140 | ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ 141 | ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ 142 | ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) 143 | 144 | #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) 145 | /** 146 | * @} 147 | */ 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /** @defgroup BKP_Exported_Macros 154 | * @{ 155 | */ 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /** @defgroup BKP_Exported_Functions 162 | * @{ 163 | */ 164 | 165 | void BKP_DeInit(void); 166 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); 167 | void BKP_TamperPinCmd(FunctionalState NewState); 168 | void BKP_ITConfig(FunctionalState NewState); 169 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); 170 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); 171 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); 172 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); 173 | FlagStatus BKP_GetFlagStatus(void); 174 | void BKP_ClearFlag(void); 175 | ITStatus BKP_GetITStatus(void); 176 | void BKP_ClearITPendingBit(void); 177 | 178 | #ifdef __cplusplus 179 | } 180 | #endif 181 | 182 | #endif /* __STM32F10x_BKP_H */ 183 | /** 184 | * @} 185 | */ 186 | 187 | /** 188 | * @} 189 | */ 190 | 191 | /** 192 | * @} 193 | */ 194 | 195 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 196 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_bkp.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the BKP firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_bkp.h" 24 | #include "stm32f10x_rcc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup BKP 31 | * @brief BKP driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup BKP_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup BKP_Private_Defines 44 | * @{ 45 | */ 46 | 47 | /* ------------ BKP registers bit address in the alias region --------------- */ 48 | #define BKP_OFFSET (BKP_BASE - PERIPH_BASE) 49 | 50 | /* --- CR Register ----*/ 51 | 52 | /* Alias word address of TPAL bit */ 53 | #define CR_OFFSET (BKP_OFFSET + 0x30) 54 | #define TPAL_BitNumber 0x01 55 | #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) 56 | 57 | /* Alias word address of TPE bit */ 58 | #define TPE_BitNumber 0x00 59 | #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) 60 | 61 | /* --- CSR Register ---*/ 62 | 63 | /* Alias word address of TPIE bit */ 64 | #define CSR_OFFSET (BKP_OFFSET + 0x34) 65 | #define TPIE_BitNumber 0x02 66 | #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) 67 | 68 | /* Alias word address of TIF bit */ 69 | #define TIF_BitNumber 0x09 70 | #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) 71 | 72 | /* Alias word address of TEF bit */ 73 | #define TEF_BitNumber 0x08 74 | #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) 75 | 76 | /* ---------------------- BKP registers bit mask ------------------------ */ 77 | 78 | /* RTCCR register bit mask */ 79 | #define RTCCR_CAL_MASK ((uint16_t)0xFF80) 80 | #define RTCCR_MASK ((uint16_t)0xFC7F) 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | 87 | /** @defgroup BKP_Private_Macros 88 | * @{ 89 | */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @defgroup BKP_Private_Variables 96 | * @{ 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** @defgroup BKP_Private_FunctionPrototypes 104 | * @{ 105 | */ 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @defgroup BKP_Private_Functions 112 | * @{ 113 | */ 114 | 115 | /** 116 | * @brief Deinitializes the BKP peripheral registers to their default reset values. 117 | * @param None 118 | * @retval None 119 | */ 120 | void BKP_DeInit(void) 121 | { 122 | RCC_BackupResetCmd(ENABLE); 123 | RCC_BackupResetCmd(DISABLE); 124 | } 125 | 126 | /** 127 | * @brief Configures the Tamper Pin active level. 128 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. 129 | * This parameter can be one of the following values: 130 | * @arg BKP_TamperPinLevel_High: Tamper pin active on high level 131 | * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level 132 | * @retval None 133 | */ 134 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) 135 | { 136 | /* Check the parameters */ 137 | assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); 138 | *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; 139 | } 140 | 141 | /** 142 | * @brief Enables or disables the Tamper Pin activation. 143 | * @param NewState: new state of the Tamper Pin activation. 144 | * This parameter can be: ENABLE or DISABLE. 145 | * @retval None 146 | */ 147 | void BKP_TamperPinCmd(FunctionalState NewState) 148 | { 149 | /* Check the parameters */ 150 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 151 | *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; 152 | } 153 | 154 | /** 155 | * @brief Enables or disables the Tamper Pin Interrupt. 156 | * @param NewState: new state of the Tamper Pin Interrupt. 157 | * This parameter can be: ENABLE or DISABLE. 158 | * @retval None 159 | */ 160 | void BKP_ITConfig(FunctionalState NewState) 161 | { 162 | /* Check the parameters */ 163 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 164 | *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; 165 | } 166 | 167 | /** 168 | * @brief Select the RTC output source to output on the Tamper pin. 169 | * @param BKP_RTCOutputSource: specifies the RTC output source. 170 | * This parameter can be one of the following values: 171 | * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. 172 | * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency 173 | * divided by 64 on the Tamper pin. 174 | * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on 175 | * the Tamper pin. 176 | * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on 177 | * the Tamper pin. 178 | * @retval None 179 | */ 180 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) 181 | { 182 | uint16_t tmpreg = 0; 183 | /* Check the parameters */ 184 | assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); 185 | tmpreg = BKP->RTCCR; 186 | /* Clear CCO, ASOE and ASOS bits */ 187 | tmpreg &= RTCCR_MASK; 188 | 189 | /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ 190 | tmpreg |= BKP_RTCOutputSource; 191 | /* Store the new value */ 192 | BKP->RTCCR = tmpreg; 193 | } 194 | 195 | /** 196 | * @brief Sets RTC Clock Calibration value. 197 | * @param CalibrationValue: specifies the RTC Clock Calibration value. 198 | * This parameter must be a number between 0 and 0x7F. 199 | * @retval None 200 | */ 201 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) 202 | { 203 | uint16_t tmpreg = 0; 204 | /* Check the parameters */ 205 | assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); 206 | tmpreg = BKP->RTCCR; 207 | /* Clear CAL[6:0] bits */ 208 | tmpreg &= RTCCR_CAL_MASK; 209 | /* Set CAL[6:0] bits according to CalibrationValue value */ 210 | tmpreg |= CalibrationValue; 211 | /* Store the new value */ 212 | BKP->RTCCR = tmpreg; 213 | } 214 | 215 | /** 216 | * @brief Writes user data to the specified Data Backup Register. 217 | * @param BKP_DR: specifies the Data Backup Register. 218 | * This parameter can be BKP_DRx where x:[1, 42] 219 | * @param Data: data to write 220 | * @retval None 221 | */ 222 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) 223 | { 224 | __IO uint32_t tmp = 0; 225 | 226 | /* Check the parameters */ 227 | assert_param(IS_BKP_DR(BKP_DR)); 228 | 229 | tmp = (uint32_t)BKP_BASE; 230 | tmp += BKP_DR; 231 | 232 | *(__IO uint32_t *) tmp = Data; 233 | } 234 | 235 | /** 236 | * @brief Reads data from the specified Data Backup Register. 237 | * @param BKP_DR: specifies the Data Backup Register. 238 | * This parameter can be BKP_DRx where x:[1, 42] 239 | * @retval The content of the specified Data Backup Register 240 | */ 241 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) 242 | { 243 | __IO uint32_t tmp = 0; 244 | 245 | /* Check the parameters */ 246 | assert_param(IS_BKP_DR(BKP_DR)); 247 | 248 | tmp = (uint32_t)BKP_BASE; 249 | tmp += BKP_DR; 250 | 251 | return (*(__IO uint16_t *) tmp); 252 | } 253 | 254 | /** 255 | * @brief Checks whether the Tamper Pin Event flag is set or not. 256 | * @param None 257 | * @retval The new state of the Tamper Pin Event flag (SET or RESET). 258 | */ 259 | FlagStatus BKP_GetFlagStatus(void) 260 | { 261 | return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); 262 | } 263 | 264 | /** 265 | * @brief Clears Tamper Pin Event pending flag. 266 | * @param None 267 | * @retval None 268 | */ 269 | void BKP_ClearFlag(void) 270 | { 271 | /* Set CTE bit to clear Tamper Pin Event flag */ 272 | BKP->CSR |= BKP_CSR_CTE; 273 | } 274 | 275 | /** 276 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not. 277 | * @param None 278 | * @retval The new state of the Tamper Pin Interrupt (SET or RESET). 279 | */ 280 | ITStatus BKP_GetITStatus(void) 281 | { 282 | return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); 283 | } 284 | 285 | /** 286 | * @brief Clears Tamper Pin Interrupt pending bit. 287 | * @param None 288 | * @retval None 289 | */ 290 | void BKP_ClearITPendingBit(void) 291 | { 292 | /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ 293 | BKP->CSR |= BKP_CSR_CTI; 294 | } 295 | 296 | /** 297 | * @} 298 | */ 299 | 300 | /** 301 | * @} 302 | */ 303 | 304 | /** 305 | * @} 306 | */ 307 | 308 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 309 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/misc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file contains all the functions prototypes for the miscellaneous 8 | * firmware library functions (add-on to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2011 STMicroelectronics

20 | ****************************************************************************** 21 | */ 22 | 23 | /* Define to prevent recursive inclusion -------------------------------------*/ 24 | #ifndef __MISC_H 25 | #define __MISC_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | /* Includes ------------------------------------------------------------------*/ 32 | #include "stm32f10x.h" 33 | 34 | /** @addtogroup STM32F10x_StdPeriph_Driver 35 | * @{ 36 | */ 37 | 38 | /** @addtogroup MISC 39 | * @{ 40 | */ 41 | 42 | /** @defgroup MISC_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief NVIC Init Structure definition 48 | */ 49 | 50 | typedef struct 51 | { 52 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. 53 | This parameter can be a value of @ref IRQn_Type 54 | (For the complete STM32 Devices IRQ Channels list, please 55 | refer to stm32f10x.h file) */ 56 | 57 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel 58 | specified in NVIC_IRQChannel. This parameter can be a value 59 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 60 | 61 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified 62 | in NVIC_IRQChannel. This parameter can be a value 63 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 64 | 65 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel 66 | will be enabled or disabled. 67 | This parameter can be set either to ENABLE or DISABLE */ 68 | } NVIC_InitTypeDef; 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup NVIC_Priority_Table 75 | * @{ 76 | */ 77 | 78 | /** 79 | @code 80 | The table below gives the allowed values of the pre-emption priority and subpriority according 81 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function 82 | ============================================================================================================================ 83 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description 84 | ============================================================================================================================ 85 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority 86 | | | | 4 bits for subpriority 87 | ---------------------------------------------------------------------------------------------------------------------------- 88 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority 89 | | | | 3 bits for subpriority 90 | ---------------------------------------------------------------------------------------------------------------------------- 91 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority 92 | | | | 2 bits for subpriority 93 | ---------------------------------------------------------------------------------------------------------------------------- 94 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority 95 | | | | 1 bits for subpriority 96 | ---------------------------------------------------------------------------------------------------------------------------- 97 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority 98 | | | | 0 bits for subpriority 99 | ============================================================================================================================ 100 | @endcode 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /** @defgroup MISC_Exported_Constants 108 | * @{ 109 | */ 110 | 111 | /** @defgroup Vector_Table_Base 112 | * @{ 113 | */ 114 | 115 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000) 116 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) 117 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ 118 | ((VECTTAB) == NVIC_VectTab_FLASH)) 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @defgroup System_Low_Power 124 | * @{ 125 | */ 126 | 127 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10) 128 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) 129 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) 130 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ 131 | ((LP) == NVIC_LP_SLEEPDEEP) || \ 132 | ((LP) == NVIC_LP_SLEEPONEXIT)) 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup Preemption_Priority_Group 138 | * @{ 139 | */ 140 | 141 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 142 | 4 bits for subpriority */ 143 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 144 | 3 bits for subpriority */ 145 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 146 | 2 bits for subpriority */ 147 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 148 | 1 bits for subpriority */ 149 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 150 | 0 bits for subpriority */ 151 | 152 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ 153 | ((GROUP) == NVIC_PriorityGroup_1) || \ 154 | ((GROUP) == NVIC_PriorityGroup_2) || \ 155 | ((GROUP) == NVIC_PriorityGroup_3) || \ 156 | ((GROUP) == NVIC_PriorityGroup_4)) 157 | 158 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 159 | 160 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 161 | 162 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) 163 | 164 | /** 165 | * @} 166 | */ 167 | 168 | /** @defgroup SysTick_clock_source 169 | * @{ 170 | */ 171 | 172 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 173 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 174 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ 175 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) 176 | /** 177 | * @} 178 | */ 179 | 180 | /** 181 | * @} 182 | */ 183 | 184 | /** @defgroup MISC_Exported_Macros 185 | * @{ 186 | */ 187 | 188 | /** 189 | * @} 190 | */ 191 | 192 | /** @defgroup MISC_Exported_Functions 193 | * @{ 194 | */ 195 | 196 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 197 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 198 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); 199 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 200 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); 201 | 202 | #ifdef __cplusplus 203 | } 204 | #endif 205 | 206 | #endif /* __MISC_H */ 207 | 208 | /** 209 | * @} 210 | */ 211 | 212 | /** 213 | * @} 214 | */ 215 | 216 | /** 217 | * @} 218 | */ 219 | 220 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 221 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_pwr.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the PWR firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_pwr.h" 24 | #include "stm32f10x_rcc.h" 25 | 26 | /** @addtogroup STM32F10x_StdPeriph_Driver 27 | * @{ 28 | */ 29 | 30 | /** @defgroup PWR 31 | * @brief PWR driver modules 32 | * @{ 33 | */ 34 | 35 | /** @defgroup PWR_Private_TypesDefinitions 36 | * @{ 37 | */ 38 | 39 | /** 40 | * @} 41 | */ 42 | 43 | /** @defgroup PWR_Private_Defines 44 | * @{ 45 | */ 46 | 47 | /* --------- PWR registers bit address in the alias region ---------- */ 48 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 49 | 50 | /* --- CR Register ---*/ 51 | 52 | /* Alias word address of DBP bit */ 53 | #define CR_OFFSET (PWR_OFFSET + 0x00) 54 | #define DBP_BitNumber 0x08 55 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 56 | 57 | /* Alias word address of PVDE bit */ 58 | #define PVDE_BitNumber 0x04 59 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 60 | 61 | /* --- CSR Register ---*/ 62 | 63 | /* Alias word address of EWUP bit */ 64 | #define CSR_OFFSET (PWR_OFFSET + 0x04) 65 | #define EWUP_BitNumber 0x08 66 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 67 | 68 | /* ------------------ PWR registers bit mask ------------------------ */ 69 | 70 | /* CR register bit mask */ 71 | #define CR_DS_MASK ((uint32_t)0xFFFFFFFC) 72 | #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) 73 | 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @defgroup PWR_Private_Macros 80 | * @{ 81 | */ 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /** @defgroup PWR_Private_Variables 88 | * @{ 89 | */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @defgroup PWR_Private_FunctionPrototypes 96 | * @{ 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** @defgroup PWR_Private_Functions 104 | * @{ 105 | */ 106 | 107 | /** 108 | * @brief Deinitializes the PWR peripheral registers to their default reset values. 109 | * @param None 110 | * @retval None 111 | */ 112 | void PWR_DeInit(void) 113 | { 114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 115 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 116 | } 117 | 118 | /** 119 | * @brief Enables or disables access to the RTC and backup registers. 120 | * @param NewState: new state of the access to the RTC and backup registers. 121 | * This parameter can be: ENABLE or DISABLE. 122 | * @retval None 123 | */ 124 | void PWR_BackupAccessCmd(FunctionalState NewState) 125 | { 126 | /* Check the parameters */ 127 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 128 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 129 | } 130 | 131 | /** 132 | * @brief Enables or disables the Power Voltage Detector(PVD). 133 | * @param NewState: new state of the PVD. 134 | * This parameter can be: ENABLE or DISABLE. 135 | * @retval None 136 | */ 137 | void PWR_PVDCmd(FunctionalState NewState) 138 | { 139 | /* Check the parameters */ 140 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 141 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; 142 | } 143 | 144 | /** 145 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 146 | * @param PWR_PVDLevel: specifies the PVD detection level 147 | * This parameter can be one of the following values: 148 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V 149 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V 150 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V 151 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V 152 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V 153 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V 154 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V 155 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V 156 | * @retval None 157 | */ 158 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 159 | { 160 | uint32_t tmpreg = 0; 161 | /* Check the parameters */ 162 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 163 | tmpreg = PWR->CR; 164 | /* Clear PLS[7:5] bits */ 165 | tmpreg &= CR_PLS_MASK; 166 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */ 167 | tmpreg |= PWR_PVDLevel; 168 | /* Store the new value */ 169 | PWR->CR = tmpreg; 170 | } 171 | 172 | /** 173 | * @brief Enables or disables the WakeUp Pin functionality. 174 | * @param NewState: new state of the WakeUp Pin functionality. 175 | * This parameter can be: ENABLE or DISABLE. 176 | * @retval None 177 | */ 178 | void PWR_WakeUpPinCmd(FunctionalState NewState) 179 | { 180 | /* Check the parameters */ 181 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 182 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; 183 | } 184 | 185 | /** 186 | * @brief Enters STOP mode. 187 | * @param PWR_Regulator: specifies the regulator state in STOP mode. 188 | * This parameter can be one of the following values: 189 | * @arg PWR_Regulator_ON: STOP mode with regulator ON 190 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode 191 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. 192 | * This parameter can be one of the following values: 193 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 194 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 195 | * @retval None 196 | */ 197 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 198 | { 199 | uint32_t tmpreg = 0; 200 | /* Check the parameters */ 201 | assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 202 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 203 | 204 | /* Select the regulator state in STOP mode ---------------------------------*/ 205 | tmpreg = PWR->CR; 206 | /* Clear PDDS and LPDS bits */ 207 | tmpreg &= CR_DS_MASK; 208 | /* Set LPDS bit according to PWR_Regulator value */ 209 | tmpreg |= PWR_Regulator; 210 | /* Store the new value */ 211 | PWR->CR = tmpreg; 212 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 213 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 214 | 215 | /* Select STOP mode entry --------------------------------------------------*/ 216 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 217 | { 218 | /* Request Wait For Interrupt */ 219 | __WFI(); 220 | } 221 | else 222 | { 223 | /* Request Wait For Event */ 224 | __WFE(); 225 | } 226 | 227 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ 228 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 229 | } 230 | 231 | /** 232 | * @brief Enters STANDBY mode. 233 | * @param None 234 | * @retval None 235 | */ 236 | void PWR_EnterSTANDBYMode(void) 237 | { 238 | /* Clear Wake-up flag */ 239 | PWR->CR |= PWR_CR_CWUF; 240 | /* Select STANDBY mode */ 241 | PWR->CR |= PWR_CR_PDDS; 242 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 243 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 244 | /* This option is used to ensure that store operations are completed */ 245 | #if defined ( __CC_ARM ) 246 | __force_stores(); 247 | #endif 248 | /* Request Wait For Interrupt */ 249 | __WFI(); 250 | } 251 | 252 | /** 253 | * @brief Checks whether the specified PWR flag is set or not. 254 | * @param PWR_FLAG: specifies the flag to check. 255 | * This parameter can be one of the following values: 256 | * @arg PWR_FLAG_WU: Wake Up flag 257 | * @arg PWR_FLAG_SB: StandBy flag 258 | * @arg PWR_FLAG_PVDO: PVD Output 259 | * @retval The new state of PWR_FLAG (SET or RESET). 260 | */ 261 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 262 | { 263 | FlagStatus bitstatus = RESET; 264 | /* Check the parameters */ 265 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 266 | 267 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 268 | { 269 | bitstatus = SET; 270 | } 271 | else 272 | { 273 | bitstatus = RESET; 274 | } 275 | /* Return the flag status */ 276 | return bitstatus; 277 | } 278 | 279 | /** 280 | * @brief Clears the PWR's pending flags. 281 | * @param PWR_FLAG: specifies the flag to clear. 282 | * This parameter can be one of the following values: 283 | * @arg PWR_FLAG_WU: Wake Up flag 284 | * @arg PWR_FLAG_SB: StandBy flag 285 | * @retval None 286 | */ 287 | void PWR_ClearFlag(uint32_t PWR_FLAG) 288 | { 289 | /* Check the parameters */ 290 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 291 | 292 | PWR->CR |= PWR_FLAG << 2; 293 | } 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /** 304 | * @} 305 | */ 306 | 307 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 308 | -------------------------------------------------------------------------------- /src/CSL/STM32F10x_StdPeriph_Driver/stm32f10x_rtc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_rtc.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief This file provides all the RTC firmware functions. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "stm32f10x_rtc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup RTC 30 | * @brief RTC driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup RTC_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | /** 38 | * @} 39 | */ 40 | 41 | /** @defgroup RTC_Private_Defines 42 | * @{ 43 | */ 44 | #define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ 45 | #define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ 46 | 47 | /** 48 | * @} 49 | */ 50 | 51 | /** @defgroup RTC_Private_Macros 52 | * @{ 53 | */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @defgroup RTC_Private_Variables 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup RTC_Private_FunctionPrototypes 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @defgroup RTC_Private_Functions 76 | * @{ 77 | */ 78 | 79 | /** 80 | * @brief Enables or disables the specified RTC interrupts. 81 | * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. 82 | * This parameter can be any combination of the following values: 83 | * @arg RTC_IT_OW: Overflow interrupt 84 | * @arg RTC_IT_ALR: Alarm interrupt 85 | * @arg RTC_IT_SEC: Second interrupt 86 | * @param NewState: new state of the specified RTC interrupts. 87 | * This parameter can be: ENABLE or DISABLE. 88 | * @retval None 89 | */ 90 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) 91 | { 92 | /* Check the parameters */ 93 | assert_param(IS_RTC_IT(RTC_IT)); 94 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 95 | 96 | if (NewState != DISABLE) 97 | { 98 | RTC->CRH |= RTC_IT; 99 | } 100 | else 101 | { 102 | RTC->CRH &= (uint16_t)~RTC_IT; 103 | } 104 | } 105 | 106 | /** 107 | * @brief Enters the RTC configuration mode. 108 | * @param None 109 | * @retval None 110 | */ 111 | void RTC_EnterConfigMode(void) 112 | { 113 | /* Set the CNF flag to enter in the Configuration Mode */ 114 | RTC->CRL |= RTC_CRL_CNF; 115 | } 116 | 117 | /** 118 | * @brief Exits from the RTC configuration mode. 119 | * @param None 120 | * @retval None 121 | */ 122 | void RTC_ExitConfigMode(void) 123 | { 124 | /* Reset the CNF flag to exit from the Configuration Mode */ 125 | RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); 126 | } 127 | 128 | /** 129 | * @brief Gets the RTC counter value. 130 | * @param None 131 | * @retval RTC counter value. 132 | */ 133 | uint32_t RTC_GetCounter(void) 134 | { 135 | uint16_t tmp = 0; 136 | tmp = RTC->CNTL; 137 | return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; 138 | } 139 | 140 | /** 141 | * @brief Sets the RTC counter value. 142 | * @param CounterValue: RTC counter new value. 143 | * @retval None 144 | */ 145 | void RTC_SetCounter(uint32_t CounterValue) 146 | { 147 | RTC_EnterConfigMode(); 148 | /* Set RTC COUNTER MSB word */ 149 | RTC->CNTH = CounterValue >> 16; 150 | /* Set RTC COUNTER LSB word */ 151 | RTC->CNTL = (CounterValue & RTC_LSB_MASK); 152 | RTC_ExitConfigMode(); 153 | } 154 | 155 | /** 156 | * @brief Sets the RTC prescaler value. 157 | * @param PrescalerValue: RTC prescaler new value. 158 | * @retval None 159 | */ 160 | void RTC_SetPrescaler(uint32_t PrescalerValue) 161 | { 162 | /* Check the parameters */ 163 | assert_param(IS_RTC_PRESCALER(PrescalerValue)); 164 | 165 | RTC_EnterConfigMode(); 166 | /* Set RTC PRESCALER MSB word */ 167 | RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; 168 | /* Set RTC PRESCALER LSB word */ 169 | RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); 170 | RTC_ExitConfigMode(); 171 | } 172 | 173 | /** 174 | * @brief Sets the RTC alarm value. 175 | * @param AlarmValue: RTC alarm new value. 176 | * @retval None 177 | */ 178 | void RTC_SetAlarm(uint32_t AlarmValue) 179 | { 180 | RTC_EnterConfigMode(); 181 | /* Set the ALARM MSB word */ 182 | RTC->ALRH = AlarmValue >> 16; 183 | /* Set the ALARM LSB word */ 184 | RTC->ALRL = (AlarmValue & RTC_LSB_MASK); 185 | RTC_ExitConfigMode(); 186 | } 187 | 188 | /** 189 | * @brief Gets the RTC divider value. 190 | * @param None 191 | * @retval RTC Divider value. 192 | */ 193 | uint32_t RTC_GetDivider(void) 194 | { 195 | uint32_t tmp = 0x00; 196 | tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; 197 | tmp |= RTC->DIVL; 198 | return tmp; 199 | } 200 | 201 | /** 202 | * @brief Waits until last write operation on RTC registers has finished. 203 | * @note This function must be called before any write to RTC registers. 204 | * @param None 205 | * @retval None 206 | */ 207 | void RTC_WaitForLastTask(void) 208 | { 209 | /* Loop until RTOFF flag is set */ 210 | while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) 211 | { 212 | } 213 | } 214 | 215 | /** 216 | * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) 217 | * are synchronized with RTC APB clock. 218 | * @note This function must be called before any read operation after an APB reset 219 | * or an APB clock stop. 220 | * @param None 221 | * @retval None 222 | */ 223 | void RTC_WaitForSynchro(void) 224 | { 225 | /* Clear RSF flag */ 226 | RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; 227 | /* Loop until RSF flag is set */ 228 | while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) 229 | { 230 | } 231 | } 232 | 233 | /** 234 | * @brief Checks whether the specified RTC flag is set or not. 235 | * @param RTC_FLAG: specifies the flag to check. 236 | * This parameter can be one the following values: 237 | * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag 238 | * @arg RTC_FLAG_RSF: Registers Synchronized flag 239 | * @arg RTC_FLAG_OW: Overflow flag 240 | * @arg RTC_FLAG_ALR: Alarm flag 241 | * @arg RTC_FLAG_SEC: Second flag 242 | * @retval The new state of RTC_FLAG (SET or RESET). 243 | */ 244 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) 245 | { 246 | FlagStatus bitstatus = RESET; 247 | 248 | /* Check the parameters */ 249 | assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); 250 | 251 | if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) 252 | { 253 | bitstatus = SET; 254 | } 255 | else 256 | { 257 | bitstatus = RESET; 258 | } 259 | return bitstatus; 260 | } 261 | 262 | /** 263 | * @brief Clears the RTC's pending flags. 264 | * @param RTC_FLAG: specifies the flag to clear. 265 | * This parameter can be any combination of the following values: 266 | * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after 267 | * an APB reset or an APB Clock stop. 268 | * @arg RTC_FLAG_OW: Overflow flag 269 | * @arg RTC_FLAG_ALR: Alarm flag 270 | * @arg RTC_FLAG_SEC: Second flag 271 | * @retval None 272 | */ 273 | void RTC_ClearFlag(uint16_t RTC_FLAG) 274 | { 275 | /* Check the parameters */ 276 | assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); 277 | 278 | /* Clear the corresponding RTC flag */ 279 | RTC->CRL &= (uint16_t)~RTC_FLAG; 280 | } 281 | 282 | /** 283 | * @brief Checks whether the specified RTC interrupt has occurred or not. 284 | * @param RTC_IT: specifies the RTC interrupts sources to check. 285 | * This parameter can be one of the following values: 286 | * @arg RTC_IT_OW: Overflow interrupt 287 | * @arg RTC_IT_ALR: Alarm interrupt 288 | * @arg RTC_IT_SEC: Second interrupt 289 | * @retval The new state of the RTC_IT (SET or RESET). 290 | */ 291 | ITStatus RTC_GetITStatus(uint16_t RTC_IT) 292 | { 293 | ITStatus bitstatus = RESET; 294 | /* Check the parameters */ 295 | assert_param(IS_RTC_GET_IT(RTC_IT)); 296 | 297 | bitstatus = (ITStatus)(RTC->CRL & RTC_IT); 298 | if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) 299 | { 300 | bitstatus = SET; 301 | } 302 | else 303 | { 304 | bitstatus = RESET; 305 | } 306 | return bitstatus; 307 | } 308 | 309 | /** 310 | * @brief Clears the RTC's interrupt pending bits. 311 | * @param RTC_IT: specifies the interrupt pending bit to clear. 312 | * This parameter can be any combination of the following values: 313 | * @arg RTC_IT_OW: Overflow interrupt 314 | * @arg RTC_IT_ALR: Alarm interrupt 315 | * @arg RTC_IT_SEC: Second interrupt 316 | * @retval None 317 | */ 318 | void RTC_ClearITPendingBit(uint16_t RTC_IT) 319 | { 320 | /* Check the parameters */ 321 | assert_param(IS_RTC_IT(RTC_IT)); 322 | 323 | /* Clear the corresponding RTC pending bit */ 324 | RTC->CRL &= (uint16_t)~RTC_IT; 325 | } 326 | 327 | /** 328 | * @} 329 | */ 330 | 331 | /** 332 | * @} 333 | */ 334 | 335 | /** 336 | * @} 337 | */ 338 | 339 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 340 | -------------------------------------------------------------------------------- /doc/FlashAlgo/flash_algo.py: -------------------------------------------------------------------------------- 1 | #! C:\Python27\python.exe 2 | #coding: utf-8 3 | """ 4 | mbed 5 | Copyright (c) 2017-2017 ARM Limited 6 | """ 7 | import os 8 | import struct 9 | import binascii 10 | import StringIO 11 | from collections import namedtuple 12 | 13 | import jinja2 14 | from elftools.elf.elffile import ELFFile 15 | 16 | 17 | class PackFlashAlgo(object): 18 | REQUIRED_SYMBOLS = ( 19 | "Init", 20 | "UnInit", 21 | "EraseSector", 22 | "ProgramPage", 23 | ) 24 | 25 | EXTRA_SYMBOLS = ( 26 | "BlankCheck", 27 | "EraseChip", 28 | "Verify", 29 | "Read", 30 | ) 31 | 32 | def __init__(self, data): 33 | ''' 从ELF文件中依次解析出Flash信息和所需的symbols、sections， 34 | 然后根据section的信息创建可在RAM中执行的算法程序的二进制blob ''' 35 | self.elf = ElfFileSimple(data) 36 | 37 | self.flash_info = PackFlashInfo(self.elf) 38 | self.flash_start = self.flash_info.start 39 | self.flash_size = self.flash_info.size 40 | self.flash_page_size = self.flash_info.page_size 41 | 42 | 43 | self.symbols = {} 44 | for symbol in self.REQUIRED_SYMBOLS: 45 | if symbol not in self.elf.symbols: raise Exception("Missing symbol %s" % symbol) 46 | self.symbols[symbol] = self.elf.symbols[symbol].value 47 | for symbol in self.EXTRA_SYMBOLS: 48 | if symbol not in self.elf.symbols: self.symbols[symbol] = 0xFFFFFFFF 49 | else: self.symbols[symbol] = self.elf.symbols[symbol].value 50 | 51 | 52 | ''' 算法程序工程的link脚本： 53 | PRG 0 PI 54 | { 55 | PrgCode +0 ; Code 56 | { 57 | * (+RO) 58 | } 59 | 60 | PrgData +0 ; Data 61 | { 62 | * (+RW,+ZI) 63 | } 64 | } 65 | ''' 66 | ro_rw_zi = [None, None, None] 67 | for section in self.elf.iter_sections(): 68 | for i, name_and_type in enumerate((("PrgCode", "SHT_PROGBITS"), 69 | ("PrgData", "SHT_PROGBITS"), 70 | ("PrgData", "SHT_NOBITS"),)): 71 | if name_and_type != (section.name, section["sh_type"]): continue 72 | if ro_rw_zi[i] is not None: raise Exception("Duplicated section") 73 | 74 | ro_rw_zi[i] = section 75 | 76 | ''' 若zi段丢失，创建一个空的 ''' 77 | s_ro, s_rw, s_zi = ro_rw_zi 78 | if s_rw is not None and s_zi is None: 79 | s_zi = { 80 | "sh_addr": s_rw["sh_addr"] + s_rw["sh_size"], 81 | "sh_size": 0 82 | } 83 | 84 | if s_ro is None: raise Exception("RO section is missing") 85 | if s_rw is None: raise Exception("RW section is missing") 86 | if s_zi is None: raise Exception("ZI section is missing") 87 | if s_ro["sh_addr"] != 0: 88 | raise Exception("RO section does not start at address 0") 89 | if s_ro["sh_addr"] + s_ro["sh_size"] != s_rw["sh_addr"]: 90 | raise Exception("RW section does not follow RO section") 91 | if s_rw["sh_addr"] + s_rw["sh_size"] != s_zi["sh_addr"]: 92 | raise Exception("ZI section does not follow RW section") 93 | 94 | self.ro_start = s_ro["sh_addr"] 95 | self.ro_size = s_ro["sh_size"] 96 | self.rw_start = s_rw["sh_addr"] 97 | self.rw_size = s_rw["sh_size"] 98 | self.zi_start = s_zi["sh_addr"] 99 | self.zi_size = s_zi["sh_size"] 100 | 101 | 102 | algo_size = s_ro["sh_size"] + s_rw["sh_size"] + s_zi["sh_size"] 103 | self.algo_data = bytearray(algo_size) 104 | for section in (s_ro, s_rw): 105 | start = section["sh_addr"] 106 | size = section["sh_size"] 107 | assert len(section.data()) == size 108 | self.algo_data[start : start+size] = section.data() 109 | 110 | def format_algo_data(self, spaces, group_size, fmt): 111 | ''' 返回一个能表示algo_data的字符串 suitable for use in a template 112 | spaces: 每行的前导空格个数 group_size: 每行的元素个数 fmt: hex、c 113 | ''' 114 | padding = " " * spaces 115 | if fmt == "hex": 116 | blob = binascii.b2a_hex(self.algo_data) 117 | line_list = [] 118 | for i in xrange(0, len(blob), group_size): 119 | line_list.append('"' + blob[i:i + group_size] + '"') 120 | return ("\n" + padding).join(line_list) 121 | elif fmt == "c": 122 | blob = self.algo_data[:] 123 | pad_size = 0 if len(blob) % 4 == 0 else 4 - len(blob) % 4 124 | blob = blob + "\x00" * pad_size 125 | integer_list = struct.unpack("<" + "L" * (len(blob) / 4), blob) 126 | line_list = [] 127 | for pos in range(0, len(integer_list), group_size): 128 | group = ["0x%08X" % value for value in 129 | integer_list[pos:pos + group_size]] 130 | line_list.append(", ".join(group)) 131 | return (",\n" + padding).join(line_list) 132 | else: 133 | raise Exception("Unsupported format %s" % fmt) 134 | 135 | def process_template(self, template_path, output_path, data_dict=None): 136 | ''' 用模板文件生成输出文件， 此类的所有数据都可以在模板中通过 'algo' 访问 137 | data_dict: 生成输出时模板需要的其他数据 ''' 138 | if data_dict is None: data_dict = {} 139 | 140 | assert "algo" not in data_dict, "algo already set by user data" 141 | data_dict["algo"] = self 142 | 143 | with open(template_path) as f: 144 | template = jinja2.Template(f.read()) 145 | 146 | with open(output_path, "wb") as f: 147 | f.write(template.render(data_dict)) 148 | 149 | 150 | class PackFlashInfo(object): 151 | """从ELF文件中解析出FlashDev.c文件中定义的FlashDevice结构体变量的值""" 152 | 153 | FLASH_DEVICE_STRUCT = "= seg_addr and addr + size <= seg_addr + seg_size: 223 | start = addr - seg_addr 224 | return segment.data()[start : start+size] 225 | else: 226 | continue 227 | 228 | 229 | if __name__ == '__main__': 230 | # 中断halt程序，让函数执行完后返回到这里来执行从而让CPU自动halt住 231 | BLOB_HEADER = '0xE00ABE00, 0x062D780D, 0x24084068, 0xD3000040, 0x1E644058, 0x1C49D1FA, 0x2A001E52, 0x4770D1F2,' 232 | HEADER_SIZE = 0x20 233 | 234 | data_dict = { 235 | 'prog_header': BLOB_HEADER, 236 | 'header_size': HEADER_SIZE, 237 | 'entry': 0x20000000, 238 | 'stack_pointer': 0x20000000 + 4096, 239 | } 240 | 241 | for name in os.listdir(os.getcwd()): 242 | if os.path.isfile(name) and name.endswith('.FLM'): 243 | with open(name, 'rb') as f: 244 | algo = PackFlashAlgo(f.read()) 245 | print algo.flash_info 246 | if 'algo' in data_dict: del data_dict['algo'] 247 | algo.process_template('c_blob.tmpl', name.replace('.FLM', '.c'), data_dict) 248 | -------------------------------------------------------------------------------- /src/CSL/CMSIS/DeviceSupport/startup/gcc/startup_stm32f10x_ld.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_ld.s 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 21 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 22 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 23 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 24 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 25 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 26 | * 27 | *

© COPYRIGHT 2011 STMicroelectronics

28 | ****************************************************************************** 29 | */ 30 | 31 | .syntax unified 32 | .cpu cortex-m3 33 | .fpu softvfp 34 | .thumb 35 | 36 | .global g_pfnVectors 37 | .global Default_Handler 38 | 39 | /* start address for the initialization values of the .data section. 40 | defined in linker script */ 41 | .word _sidata 42 | /* start address for the .data section. defined in linker script */ 43 | .word _sdata 44 | /* end address for the .data section. defined in linker script */ 45 | .word _edata 46 | /* start address for the .bss section. defined in linker script */ 47 | .word _sbss 48 | /* end address for the .bss section. defined in linker script */ 49 | .word _ebss 50 | 51 | .equ BootRAM, 0xF108F85F 52 | /** 53 | * @brief This is the code that gets called when the processor first 54 | * starts execution following a reset event. Only the absolutely 55 | * necessary set is performed, after which the application 56 | * supplied main() routine is called. 57 | * @param None 58 | * @retval : None 59 | */ 60 | 61 | .section .text.Reset_Handler 62 | .weak Reset_Handler 63 | .type Reset_Handler, %function 64 | Reset_Handler: 65 | 66 | /* Copy the data segment initializers from flash to SRAM */ 67 | movs r1, #0 68 | b LoopCopyDataInit 69 | 70 | CopyDataInit: 71 | ldr r3, =_sidata 72 | ldr r3, [r3, r1] 73 | str r3, [r0, r1] 74 | adds r1, r1, #4 75 | 76 | LoopCopyDataInit: 77 | ldr r0, =_sdata 78 | ldr r3, =_edata 79 | adds r2, r0, r1 80 | cmp r2, r3 81 | bcc CopyDataInit 82 | ldr r2, =_sbss 83 | b LoopFillZerobss 84 | /* Zero fill the bss segment. */ 85 | FillZerobss: 86 | movs r3, #0 87 | str r3, [r2], #4 88 | 89 | LoopFillZerobss: 90 | ldr r3, = _ebss 91 | cmp r2, r3 92 | bcc FillZerobss 93 | /* Call the clock system intitialization function.*/ 94 | bl SystemInit 95 | /* Call the application's entry point.*/ 96 | bl main 97 | bx lr 98 | .size Reset_Handler, .-Reset_Handler 99 | 100 | /** 101 | * @brief This is the code that gets called when the processor receives an 102 | * unexpected interrupt. This simply enters an infinite loop, preserving 103 | * the system state for examination by a debugger. 104 | * @param None 105 | * @retval None 106 | */ 107 | .section .text.Default_Handler,"ax",%progbits 108 | Default_Handler: 109 | Infinite_Loop: 110 | b Infinite_Loop 111 | .size Default_Handler, .-Default_Handler 112 | /****************************************************************************** 113 | * 114 | * The minimal vector table for a Cortex M3. Note that the proper constructs 115 | * must be placed on this to ensure that it ends up at physical address 116 | * 0x0000.0000. 117 | * 118 | ******************************************************************************/ 119 | .section .isr_vector,"a",%progbits 120 | .type g_pfnVectors, %object 121 | .size g_pfnVectors, .-g_pfnVectors 122 | 123 | 124 | g_pfnVectors: 125 | .word _estack 126 | .word Reset_Handler 127 | .word NMI_Handler 128 | .word HardFault_Handler 129 | .word MemManage_Handler 130 | .word BusFault_Handler 131 | .word UsageFault_Handler 132 | .word 0 133 | .word 0 134 | .word 0 135 | .word 0 136 | .word SVC_Handler 137 | .word DebugMon_Handler 138 | .word 0 139 | .word PendSV_Handler 140 | .word SysTick_Handler 141 | .word WWDG_IRQHandler 142 | .word PVD_IRQHandler 143 | .word TAMPER_IRQHandler 144 | .word RTC_IRQHandler 145 | .word FLASH_IRQHandler 146 | .word RCC_IRQHandler 147 | .word EXTI0_IRQHandler 148 | .word EXTI1_IRQHandler 149 | .word EXTI2_IRQHandler 150 | .word EXTI3_IRQHandler 151 | .word EXTI4_IRQHandler 152 | .word DMA1_Channel1_IRQHandler 153 | .word DMA1_Channel2_IRQHandler 154 | .word DMA1_Channel3_IRQHandler 155 | .word DMA1_Channel4_IRQHandler 156 | .word DMA1_Channel5_IRQHandler 157 | .word DMA1_Channel6_IRQHandler 158 | .word DMA1_Channel7_IRQHandler 159 | .word ADC1_2_IRQHandler 160 | .word USB_HP_CAN1_TX_IRQHandler 161 | .word USB_LP_CAN1_RX0_IRQHandler 162 | .word CAN1_RX1_IRQHandler 163 | .word CAN1_SCE_IRQHandler 164 | .word EXTI9_5_IRQHandler 165 | .word TIM1_BRK_IRQHandler 166 | .word TIM1_UP_IRQHandler 167 | .word TIM1_TRG_COM_IRQHandler 168 | .word TIM1_CC_IRQHandler 169 | .word TIM2_IRQHandler 170 | .word TIM3_IRQHandler 171 | .word 0 172 | .word I2C1_EV_IRQHandler 173 | .word I2C1_ER_IRQHandler 174 | .word 0 175 | .word 0 176 | .word SPI1_IRQHandler 177 | .word 0 178 | .word USART1_IRQHandler 179 | .word USART2_IRQHandler 180 | .word 0 181 | .word EXTI15_10_IRQHandler 182 | .word RTCAlarm_IRQHandler 183 | .word USBWakeUp_IRQHandler 184 | .word 0 185 | .word 0 186 | .word 0 187 | .word 0 188 | .word 0 189 | .word 0 190 | .word 0 191 | .word BootRAM /* @0x108. This is for boot in RAM mode for 192 | STM32F10x Low Density devices.*/ 193 | 194 | /******************************************************************************* 195 | * 196 | * Provide weak aliases for each Exception handler to the Default_Handler. 197 | * As they are weak aliases, any function with the same name will override 198 | * this definition. 199 | * 200 | *******************************************************************************/ 201 | 202 | .weak NMI_Handler 203 | .thumb_set NMI_Handler,Default_Handler 204 | 205 | .weak HardFault_Handler 206 | .thumb_set HardFault_Handler,Default_Handler 207 | 208 | .weak MemManage_Handler 209 | .thumb_set MemManage_Handler,Default_Handler 210 | 211 | .weak BusFault_Handler 212 | .thumb_set BusFault_Handler,Default_Handler 213 | 214 | .weak UsageFault_Handler 215 | .thumb_set UsageFault_Handler,Default_Handler 216 | 217 | .weak SVC_Handler 218 | .thumb_set SVC_Handler,Default_Handler 219 | 220 | .weak DebugMon_Handler 221 | .thumb_set DebugMon_Handler,Default_Handler 222 | 223 | .weak PendSV_Handler 224 | .thumb_set PendSV_Handler,Default_Handler 225 | 226 | .weak SysTick_Handler 227 | .thumb_set SysTick_Handler,Default_Handler 228 | 229 | .weak WWDG_IRQHandler 230 | .thumb_set WWDG_IRQHandler,Default_Handler 231 | 232 | .weak PVD_IRQHandler 233 | .thumb_set PVD_IRQHandler,Default_Handler 234 | 235 | .weak TAMPER_IRQHandler 236 | .thumb_set TAMPER_IRQHandler,Default_Handler 237 | 238 | .weak RTC_IRQHandler 239 | .thumb_set RTC_IRQHandler,Default_Handler 240 | 241 | .weak FLASH_IRQHandler 242 | .thumb_set FLASH_IRQHandler,Default_Handler 243 | 244 | .weak RCC_IRQHandler 245 | .thumb_set RCC_IRQHandler,Default_Handler 246 | 247 | .weak EXTI0_IRQHandler 248 | .thumb_set EXTI0_IRQHandler,Default_Handler 249 | 250 | .weak EXTI1_IRQHandler 251 | .thumb_set EXTI1_IRQHandler,Default_Handler 252 | 253 | .weak EXTI2_IRQHandler 254 | .thumb_set EXTI2_IRQHandler,Default_Handler 255 | 256 | .weak EXTI3_IRQHandler 257 | .thumb_set EXTI3_IRQHandler,Default_Handler 258 | 259 | .weak EXTI4_IRQHandler 260 | .thumb_set EXTI4_IRQHandler,Default_Handler 261 | 262 | .weak DMA1_Channel1_IRQHandler 263 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 264 | 265 | .weak DMA1_Channel2_IRQHandler 266 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 267 | 268 | .weak DMA1_Channel3_IRQHandler 269 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 270 | 271 | .weak DMA1_Channel4_IRQHandler 272 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 273 | 274 | .weak DMA1_Channel5_IRQHandler 275 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 276 | 277 | .weak DMA1_Channel6_IRQHandler 278 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 279 | 280 | .weak DMA1_Channel7_IRQHandler 281 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 282 | 283 | .weak ADC1_2_IRQHandler 284 | .thumb_set ADC1_2_IRQHandler,Default_Handler 285 | 286 | .weak USB_HP_CAN1_TX_IRQHandler 287 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 288 | 289 | .weak USB_LP_CAN1_RX0_IRQHandler 290 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 291 | 292 | .weak CAN1_RX1_IRQHandler 293 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 294 | 295 | .weak CAN1_SCE_IRQHandler 296 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 297 | 298 | .weak EXTI9_5_IRQHandler 299 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 300 | 301 | .weak TIM1_BRK_IRQHandler 302 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 303 | 304 | .weak TIM1_UP_IRQHandler 305 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 306 | 307 | .weak TIM1_TRG_COM_IRQHandler 308 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 309 | 310 | .weak TIM1_CC_IRQHandler 311 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 312 | 313 | .weak TIM2_IRQHandler 314 | .thumb_set TIM2_IRQHandler,Default_Handler 315 | 316 | .weak TIM3_IRQHandler 317 | .thumb_set TIM3_IRQHandler,Default_Handler 318 | 319 | .weak I2C1_EV_IRQHandler 320 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 321 | 322 | .weak I2C1_ER_IRQHandler 323 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 324 | 325 | .weak SPI1_IRQHandler 326 | .thumb_set SPI1_IRQHandler,Default_Handler 327 | 328 | .weak USART1_IRQHandler 329 | .thumb_set USART1_IRQHandler,Default_Handler 330 | 331 | .weak USART2_IRQHandler 332 | .thumb_set USART2_IRQHandler,Default_Handler 333 | 334 | .weak EXTI15_10_IRQHandler 335 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 336 | 337 | .weak RTCAlarm_IRQHandler 338 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 339 | 340 | .weak USBWakeUp_IRQHandler 341 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 342 | 343 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 344 | -------------------------------------------------------------------------------- /src/CSL/CMSIS/DeviceSupport/startup/gcc/startup_stm32f10x_md.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f10x_md.s 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the clock system 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M3 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 21 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 22 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 23 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 24 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 25 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 26 | * 27 | *

© COPYRIGHT 2011 STMicroelectronics

28 | ****************************************************************************** 29 | */ 30 | 31 | .syntax unified 32 | .cpu cortex-m3 33 | .fpu softvfp 34 | .thumb 35 | 36 | .global g_pfnVectors 37 | .global Default_Handler 38 | 39 | /* start address for the initialization values of the .data section. 40 | defined in linker script */ 41 | .word _sidata 42 | /* start address for the .data section. defined in linker script */ 43 | .word _sdata 44 | /* end address for the .data section. defined in linker script */ 45 | .word _edata 46 | /* start address for the .bss section. defined in linker script */ 47 | .word _sbss 48 | /* end address for the .bss section. defined in linker script */ 49 | .word _ebss 50 | 51 | .equ BootRAM, 0xF108F85F 52 | /** 53 | * @brief This is the code that gets called when the processor first 54 | * starts execution following a reset event. Only the absolutely 55 | * necessary set is performed, after which the application 56 | * supplied main() routine is called. 57 | * @param None 58 | * @retval : None 59 | */ 60 | 61 | .section .text.Reset_Handler 62 | .weak Reset_Handler 63 | .type Reset_Handler, %function 64 | Reset_Handler: 65 | 66 | /* Copy the data segment initializers from flash to SRAM */ 67 | movs r1, #0 68 | b LoopCopyDataInit 69 | 70 | CopyDataInit: 71 | ldr r3, =_sidata 72 | ldr r3, [r3, r1] 73 | str r3, [r0, r1] 74 | adds r1, r1, #4 75 | 76 | LoopCopyDataInit: 77 | ldr r0, =_sdata 78 | ldr r3, =_edata 79 | adds r2, r0, r1 80 | cmp r2, r3 81 | bcc CopyDataInit 82 | ldr r2, =_sbss 83 | b LoopFillZerobss 84 | /* Zero fill the bss segment. */ 85 | FillZerobss: 86 | movs r3, #0 87 | str r3, [r2], #4 88 | 89 | LoopFillZerobss: 90 | ldr r3, = _ebss 91 | cmp r2, r3 92 | bcc FillZerobss 93 | /* Call the clock system intitialization function.*/ 94 | bl SystemInit 95 | /* Call the application's entry point.*/ 96 | bl main 97 | bx lr 98 | .size Reset_Handler, .-Reset_Handler 99 | 100 | /** 101 | * @brief This is the code that gets called when the processor receives an 102 | * unexpected interrupt. This simply enters an infinite loop, preserving 103 | * the system state for examination by a debugger. 104 | * @param None 105 | * @retval None 106 | */ 107 | .section .text.Default_Handler,"ax",%progbits 108 | Default_Handler: 109 | Infinite_Loop: 110 | b Infinite_Loop 111 | .size Default_Handler, .-Default_Handler 112 | /****************************************************************************** 113 | * 114 | * The minimal vector table for a Cortex M3. Note that the proper constructs 115 | * must be placed on this to ensure that it ends up at physical address 116 | * 0x0000.0000. 117 | * 118 | ******************************************************************************/ 119 | .section .isr_vector,"a",%progbits 120 | .type g_pfnVectors, %object 121 | .size g_pfnVectors, .-g_pfnVectors 122 | 123 | 124 | g_pfnVectors: 125 | .word _estack 126 | .word Reset_Handler 127 | .word NMI_Handler 128 | .word HardFault_Handler 129 | .word MemManage_Handler 130 | .word BusFault_Handler 131 | .word UsageFault_Handler 132 | .word 0 133 | .word 0 134 | .word 0 135 | .word 0 136 | .word SVC_Handler 137 | .word DebugMon_Handler 138 | .word 0 139 | .word PendSV_Handler 140 | .word SysTick_Handler 141 | .word WWDG_IRQHandler 142 | .word PVD_IRQHandler 143 | .word TAMPER_IRQHandler 144 | .word RTC_IRQHandler 145 | .word FLASH_IRQHandler 146 | .word RCC_IRQHandler 147 | .word EXTI0_IRQHandler 148 | .word EXTI1_IRQHandler 149 | .word EXTI2_IRQHandler 150 | .word EXTI3_IRQHandler 151 | .word EXTI4_IRQHandler 152 | .word DMA1_Channel1_IRQHandler 153 | .word DMA1_Channel2_IRQHandler 154 | .word DMA1_Channel3_IRQHandler 155 | .word DMA1_Channel4_IRQHandler 156 | .word DMA1_Channel5_IRQHandler 157 | .word DMA1_Channel6_IRQHandler 158 | .word DMA1_Channel7_IRQHandler 159 | .word ADC1_2_IRQHandler 160 | .word USB_HP_CAN1_TX_IRQHandler 161 | .word USB_LP_CAN1_RX0_IRQHandler 162 | .word CAN1_RX1_IRQHandler 163 | .word CAN1_SCE_IRQHandler 164 | .word EXTI9_5_IRQHandler 165 | .word TIM1_BRK_IRQHandler 166 | .word TIM1_UP_IRQHandler 167 | .word TIM1_TRG_COM_IRQHandler 168 | .word TIM1_CC_IRQHandler 169 | .word TIM2_IRQHandler 170 | .word TIM3_IRQHandler 171 | .word TIM4_IRQHandler 172 | .word I2C1_EV_IRQHandler 173 | .word I2C1_ER_IRQHandler 174 | .word I2C2_EV_IRQHandler 175 | .word I2C2_ER_IRQHandler 176 | .word SPI1_IRQHandler 177 | .word SPI2_IRQHandler 178 | .word USART1_IRQHandler 179 | .word USART2_IRQHandler 180 | .word USART3_IRQHandler 181 | .word EXTI15_10_IRQHandler 182 | .word RTCAlarm_IRQHandler 183 | .word USBWakeUp_IRQHandler 184 | .word 0 185 | .word 0 186 | .word 0 187 | .word 0 188 | .word 0 189 | .word 0 190 | .word 0 191 | .word BootRAM /* @0x108. This is for boot in RAM mode for 192 | STM32F10x Medium Density devices. */ 193 | 194 | /******************************************************************************* 195 | * 196 | * Provide weak aliases for each Exception handler to the Default_Handler. 197 | * As they are weak aliases, any function with the same name will override 198 | * this definition. 199 | * 200 | *******************************************************************************/ 201 | 202 | .weak NMI_Handler 203 | .thumb_set NMI_Handler,Default_Handler 204 | 205 | .weak HardFault_Handler 206 | .thumb_set HardFault_Handler,Default_Handler 207 | 208 | .weak MemManage_Handler 209 | .thumb_set MemManage_Handler,Default_Handler 210 | 211 | .weak BusFault_Handler 212 | .thumb_set BusFault_Handler,Default_Handler 213 | 214 | .weak UsageFault_Handler 215 | .thumb_set UsageFault_Handler,Default_Handler 216 | 217 | .weak SVC_Handler 218 | .thumb_set SVC_Handler,Default_Handler 219 | 220 | .weak DebugMon_Handler 221 | .thumb_set DebugMon_Handler,Default_Handler 222 | 223 | .weak PendSV_Handler 224 | .thumb_set PendSV_Handler,Default_Handler 225 | 226 | .weak SysTick_Handler 227 | .thumb_set SysTick_Handler,Default_Handler 228 | 229 | .weak WWDG_IRQHandler 230 | .thumb_set WWDG_IRQHandler,Default_Handler 231 | 232 | .weak PVD_IRQHandler 233 | .thumb_set PVD_IRQHandler,Default_Handler 234 | 235 | .weak TAMPER_IRQHandler 236 | .thumb_set TAMPER_IRQHandler,Default_Handler 237 | 238 | .weak RTC_IRQHandler 239 | .thumb_set RTC_IRQHandler,Default_Handler 240 | 241 | .weak FLASH_IRQHandler 242 | .thumb_set FLASH_IRQHandler,Default_Handler 243 | 244 | .weak RCC_IRQHandler 245 | .thumb_set RCC_IRQHandler,Default_Handler 246 | 247 | .weak EXTI0_IRQHandler 248 | .thumb_set EXTI0_IRQHandler,Default_Handler 249 | 250 | .weak EXTI1_IRQHandler 251 | .thumb_set EXTI1_IRQHandler,Default_Handler 252 | 253 | .weak EXTI2_IRQHandler 254 | .thumb_set EXTI2_IRQHandler,Default_Handler 255 | 256 | .weak EXTI3_IRQHandler 257 | .thumb_set EXTI3_IRQHandler,Default_Handler 258 | 259 | .weak EXTI4_IRQHandler 260 | .thumb_set EXTI4_IRQHandler,Default_Handler 261 | 262 | .weak DMA1_Channel1_IRQHandler 263 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 264 | 265 | .weak DMA1_Channel2_IRQHandler 266 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 267 | 268 | .weak DMA1_Channel3_IRQHandler 269 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 270 | 271 | .weak DMA1_Channel4_IRQHandler 272 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 273 | 274 | .weak DMA1_Channel5_IRQHandler 275 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 276 | 277 | .weak DMA1_Channel6_IRQHandler 278 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 279 | 280 | .weak DMA1_Channel7_IRQHandler 281 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 282 | 283 | .weak ADC1_2_IRQHandler 284 | .thumb_set ADC1_2_IRQHandler,Default_Handler 285 | 286 | .weak USB_HP_CAN1_TX_IRQHandler 287 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler 288 | 289 | .weak USB_LP_CAN1_RX0_IRQHandler 290 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler 291 | 292 | .weak CAN1_RX1_IRQHandler 293 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 294 | 295 | .weak CAN1_SCE_IRQHandler 296 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 297 | 298 | .weak EXTI9_5_IRQHandler 299 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 300 | 301 | .weak TIM1_BRK_IRQHandler 302 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler 303 | 304 | .weak TIM1_UP_IRQHandler 305 | .thumb_set TIM1_UP_IRQHandler,Default_Handler 306 | 307 | .weak TIM1_TRG_COM_IRQHandler 308 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler 309 | 310 | .weak TIM1_CC_IRQHandler 311 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 312 | 313 | .weak TIM2_IRQHandler 314 | .thumb_set TIM2_IRQHandler,Default_Handler 315 | 316 | .weak TIM3_IRQHandler 317 | .thumb_set TIM3_IRQHandler,Default_Handler 318 | 319 | .weak TIM4_IRQHandler 320 | .thumb_set TIM4_IRQHandler,Default_Handler 321 | 322 | .weak I2C1_EV_IRQHandler 323 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 324 | 325 | .weak I2C1_ER_IRQHandler 326 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 327 | 328 | .weak I2C2_EV_IRQHandler 329 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 330 | 331 | .weak I2C2_ER_IRQHandler 332 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 333 | 334 | .weak SPI1_IRQHandler 335 | .thumb_set SPI1_IRQHandler,Default_Handler 336 | 337 | .weak SPI2_IRQHandler 338 | .thumb_set SPI2_IRQHandler,Default_Handler 339 | 340 | .weak USART1_IRQHandler 341 | .thumb_set USART1_IRQHandler,Default_Handler 342 | 343 | .weak USART2_IRQHandler 344 | .thumb_set USART2_IRQHandler,Default_Handler 345 | 346 | .weak USART3_IRQHandler 347 | .thumb_set USART3_IRQHandler,Default_Handler 348 | 349 | .weak EXTI15_10_IRQHandler 350 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 351 | 352 | .weak RTCAlarm_IRQHandler 353 | .thumb_set RTCAlarm_IRQHandler,Default_Handler 354 | 355 | .weak USBWakeUp_IRQHandler 356 | .thumb_set USBWakeUp_IRQHandler,Default_Handler 357 | 358 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 359 | --------------------------------------------------------------------------------