├── .gitignore ├── LICENSE ├── README.md ├── arm.yaml ├── chisel_memory_lower ├── __init__.py ├── arm.py ├── generate.py ├── parser.py ├── utils.py └── xilinx.py ├── example.conf ├── mem_1r1w_arm.v ├── mem_1r1w_masked_32x136_arm.v ├── mem_1r1w_masked_32x136_xilinx.v ├── mem_1r1w_masked_32x64_arm.v ├── mem_1r1w_masked_32x64_xilinx.v ├── mem_1r1w_masked_48x64_arm.v ├── mem_1r1w_masked_48x64_xilinx.v ├── mem_1r1w_xilinx.v ├── mem_1rw_arm.v ├── mem_1rw_xilinx.v ├── requirements.in ├── requirements.txt └── sim.tcl /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/chisel-memory-lower/HEAD/.gitignore -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/chisel-memory-lower/HEAD/LICENSE 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