├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile ├── README.md ├── bitstream.cfg ├── bootrom ├── .gitignore ├── Makefile ├── boot.py ├── bootloader.c ├── bootrom.S ├── bootrom.img └── linker.ld ├── build.sc ├── gdbinit ├── hw_handoff └── .keep ├── openocd.cfg ├── proj └── .keep ├── project_info.tcl ├── rbb.cfg ├── repo └── local │ └── .keep ├── reset.tcl ├── shell.nix ├── software ├── .gitignore ├── Makefile ├── common.h ├── init.S ├── linker.ld └── uart.c ├── src ├── bd │ ├── .keep │ └── system.tcl ├── constraints │ ├── .keep │ ├── debug.xdc │ ├── spi.xdc │ └── system.xdc ├── hdl │ ├── .keep │ ├── EICG_wrapper.v │ ├── plusarg_reader.v │ ├── rocketchip_wrapper.v │ └── vcu128.RocketConfig.sv ├── ip │ └── .keep ├── main │ └── scala │ │ ├── BscanJTAG.scala │ │ ├── Configs.scala │ │ └── Top.scala └── other │ └── .keep ├── verilator ├── .gitignore ├── BSCANE2.v ├── BUFGCE.v ├── EICG_wrapper.v ├── Makefile ├── README.md ├── RocketChip.sv ├── axi_ram.v ├── plusarg_reader.v ├── rocketchip_wrapper.v ├── testbench_rocketchip.v └── top.cpp └── vpi.cfg /.gitignore: -------------------------------------------------------------------------------- 1 | # This is a gitignore file automatically generated by digilent_vivado_checkin.tcl 2 | # The file will not be overwritten unless deleted 3 | 4 | # root 5 | /* 6 | !.gitignore 7 | !README.md 8 | !LICENSE 9 | !project_info.tcl 10 | !proj/ 11 | !repo/ 12 | !src/ 13 | !scripts/ 14 | !hw_handoff/ 15 | 16 | # vivado workspace 17 | proj/* 18 | 19 | # ip repository 20 | repo/** 21 | !repo/vivado-library 22 | repo/vivado-library/** 23 | !repo/local 24 | !repo/local/** 25 | !repo/cache 26 | repo/cache/** 27 | 28 | # version controlled sources 29 | src/** 30 | !src/bd 31 | src/bd/** 32 | !src/bd/*.tcl 33 | !src/constraints 34 | src/constraints/** 35 | !src/constraints/*.xdc 36 | !src/hdl 37 | src/hdl/** 38 | !src/hdl/*.v 39 | !src/hdl/*.sv 40 | !src/hdl/*.vhd 41 | !src/ip 42 | !src/ip/* 43 | src/ip/*/** 44 | !src/ip/**/*.xci 45 | !src/other 46 | !src/other/** 47 | !src/main 48 | !src/main/scala 49 | !src/main/scala/** 50 | 51 | # hardware handoff 52 | hw_handoff/* 53 | !hw_handoff/*.xsa 54 | 55 | # maintain required directories 56 | !**/.keep 57 | 58 | # rocket chip 59 | !project/build.properties 60 | !build.sbt 61 | !Makefile 62 | !prologue.v 63 | !bootrom 64 | !verilator 65 | !software 66 | !submodules 67 | !*.cfg 68 | !build.sc 69 | !gdbinit 70 | !reset.tcl 71 | !*.nix 72 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "digilent-vivado-scripts"] 2 | path = digilent-vivado-scripts 3 | url = git@github.com:Digilent/digilent-vivado-scripts.git 4 | [submodule "submodules/rocket-chip"] 5 | path = submodules/rocket-chip 6 | url = git@github.com:chipsalliance/rocket-chip.git 7 | [submodule "submodules/api-config-chipsalliance"] 8 | path = submodules/api-config-chipsalliance 9 | url = git@github.com:chipsalliance/api-config-chipsalliance.git 10 | [submodule "submodules/berkeley-hardfloat"] 11 | path = submodules/berkeley-hardfloat 12 | url = git@github.com:ucb-bar/berkeley-hardfloat.git 13 | [submodule "submodules/verilog-axi"] 14 | path = submodules/verilog-axi 15 | url = git@github.com:alexforencich/verilog-axi.git 16 | [submodule "submodules/riscv-boom"] 17 | path = submodules/riscv-boom 18 | url = git@github.com:riscv-boom/riscv-boom.git 19 | [submodule "submodules/rocket-chip-inclusive-cache"] 20 | path = submodules/rocket-chip-inclusive-cache 21 | url = git@github.com:chipsalliance/rocket-chip-inclusive-cache.git 22 | [submodule "submodules/diplomacy"] 23 | path = submodules/diplomacy 24 | url = git@github.com:chipsalliance/diplomacy.git 25 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Jiajie Chen 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | JOBS = 16 2 | TOP_MODULE_PROJECT ?= vcu128 3 | TOP_MODULE ?= RocketChip 4 | CONFIG ?= RocketConfig 5 | 6 | BASE_DIR = $(abspath .) 7 | BUILD = $(BASE_DIR)/build 8 | SRC = $(BASE_DIR)/src 9 | 10 | SHELL := /bin/bash 11 | 12 | MILL ?= mill 13 | 14 | all: $(BUILD)/$(TOP_MODULE_PROJECT).$(CONFIG).sv 15 | 16 | LOOKUP_SCALA_SRCS = $(shell find $(1)/. -iname "*.scala" 2> /dev/null) 17 | BOOTROM := $(shell find bootrom -iname "*.img" 2> /dev/null) 18 | 19 | $(BUILD)/$(TOP_MODULE_PROJECT).$(CONFIG).fir: $(call LOOKUP_SCALA_SRCS,$(SRC)) $(BOOTROM) 20 | mkdir -p $(@D) 21 | rm -f $(BUILD)/RocketChip.anno.json $(BUILD)/RocketChip.fir 22 | $(MILL) vcu128.runMain freechips.rocketchip.diplomacy.Main --dir $(BUILD) --top $(TOP_MODULE_PROJECT).$(TOP_MODULE) --config $(TOP_MODULE_PROJECT).$(CONFIG) 23 | mv $(BUILD)/RocketChip.fir $@ 24 | 25 | $(BUILD)/$(TOP_MODULE_PROJECT).$(CONFIG).sv: $(BUILD)/$(TOP_MODULE_PROJECT).$(CONFIG).fir 26 | # scala firrtl compiler 27 | # $(MILL) vcu128.runMain firrtl.stage.FirrtlMain --emission-options disableMemRandomization,disableRegisterRandomization -i $< -o $@ -X verilog 28 | # vivado cannot infer sram in dcache 29 | # firtool --disable-all-randomization $< -o $@ 30 | firtool --lower-memories --disable-all-randomization $< -o $@ 31 | 32 | clean: 33 | rm -rf build/* 34 | 35 | .PHONY: all clean 36 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # rocket-chip-vcu128 2 | 3 | Port Rocket Chip to VCU128 platform. Based on [rocket2thinpad](https://github.com/jiegec/rocket2thinpad). Tested with Vivado 2020.2. 4 | 5 | CAVEAT: You can use either BOOM Core or Rocket Core. Change configuration at `src/main/scala/Configs.scala` before building. 6 | 7 | AXI Interconnect memory mapping: 8 | 9 | 1. AXI Quad SPI: 0x6010_0000 10 | 2. AXI UART16550: 0x6020_0000 11 | 3. AXI Ethernet DMA: 0x6030_0000 12 | 4. AXI Ethernet: 0x6040_0000 13 | 5. AXI I2C: 0x6050_0000 14 | 6. HBM: 0x8000_0000 ~ 0x9FFF_FFFF 15 | 16 | Rocket Chip memory mapping: 17 | 18 | 1. Boot ROM: 0x0001_0000 19 | 2. CLINT: 0x0200_0000 20 | 3. MMIO: 0x6000_0000 ~ 0x7FFF_FFFF 21 | 4. Memory: 0x8000_0000 ~ 0xFFFF_FFFF 22 | 23 | External interrupt: 24 | 25 | 1. AXI UART16550 26 | 2. AXI Quad SPI 27 | 3. AXI Ethernet 28 | 4. AXI Ethernet DMA RX 29 | 5. AXI Ethernet DMA TX 30 | 6. AXI I2C 31 | 32 | Access uart from USB at /dev/ttyUSB2, baudrate 115200. A virtual reset is available at VIO. 33 | 34 | Software modifications: 35 | 36 | - [Custom OpenSBI](https://github.com/jiegec/opensbi/tree/rocket-chip-vcu128) [Changes](https://github.com/jiegec/opensbi/compare/master...jiegec:opensbi:rocket-chip-vcu128?expand=1) 37 | - [Custom U-Boot](https://github.com/jiegec/u-boot/tree/rocket-chip-vcu128) [Changes](https://github.com/jiegec/u-boot/compare/master...jiegec:u-boot:rocket-chip-vcu128?expand=1) 38 | - [Custom Linux](https://github.com/jiegec/linux/tree/rocket-chip-vcu128) [Changes](https://github.com/jiegec/linux/compare/master...jiegec:linux:rocket-chip-vcu128?expand=1) 39 | - [Custom Buildroot](https://github.com/jiegec/buildroot/tree/rocket-chip-vcu128) 40 | - [Custom Buildroot External](https://github.com/jiegec/buildroot-external/tree/master/rocket-chip-vcu128) 41 | 42 | Boot custom OpenSBI in M-mode with custom U-Boot in S-mode: 43 | 44 | ```shell 45 | # place custom opensbi at ~/opensbi, custom uboot at ~/u-boot 46 | # in u-boot 47 | $ ./build.sh 48 | # in this repo 49 | $ python3 boot.py ~/opensbi/build/platform/rocket-chip-vcu128-dual-core/firmware/fw_payload.bin /dev/ttyUSB2 50 | Boot HART ID : 1 51 | Boot HART Domain : root 52 | Boot HART Priv Version : v1.11 53 | Boot HART Base ISA : rv64imafdcx 54 | Boot HART ISA Extensions : sdtrig 55 | Boot HART PMP Count : 8 56 | Boot HART PMP Granularity : 2 bits 57 | Boot HART PMP Address Bits: 30 58 | Boot HART MHPM Info : 0 (0x00000000) 59 | Boot HART Debug Triggers : 1 triggers 60 | Boot HART MIDELEG : 0x0000000000000222 61 | Boot HART MEDELEG : 0x000000000000b109 62 | 63 | 64 | U-Boot 2024.10-g33523922a4ac (Nov 16 2024 - 11:29:29 +0800) 65 | 66 | CPU: sifive,rocket0 67 | Model: freechips,rocketchip-unknown 68 | DRAM: 512 MiB 69 | Core: 16 devices, 12 uclasses, devicetree: board 70 | Loading Environment from nowhere... OK 71 | In: serial@60200000 72 | Out: serial@60200000 73 | Err: serial@60200000 74 | Net: AXI EMAC: 60400000, phyaddr 3, interface sgmii 75 | eth0: eth0@60400000 76 | => 77 | ``` 78 | 79 | Run bare-metal executable from TFTP: 80 | 81 | ```shell 82 | # build and launch tftp server 83 | $ sudo pip3 install -U py3tftp 84 | $ cd software 85 | $ make 86 | $ sudo python3 -m py3tftp -p 69 87 | # in u-boot 88 | => tftpboot 0x80200000 10.0.0.1:uart.img 89 | Using eth0@60400000 device 90 | TFTP from server 10.0.0.1; our IP address is 10.0.0.2 91 | Filename 'uart.img'. 92 | Load address: 0x80200000 93 | Loading: # 94 | 929.7 KiB/s 95 | done 96 | Bytes transferred = 952 (3b8 hex) 97 | => go 0x80200000 98 | ## Starting application at 0x80200000 ... 99 | test 100 | ``` 101 | 102 | Boot custom Linux with custom [Buildroot external repo](https://github.com/jiegec/buildroot-external/tree/master/rocket-chip-vcu128): 103 | 104 | ```shell 105 | # in buildroot-external 106 | $ cd rocket-chip-vcu128 107 | $ ./build.sh 108 | # in linux 109 | $ ./build.sh 110 | # in this repo 111 | $ python3 boot.py ~/opensbi/build/platform/rocket-chip-vcu128-dual-core/firmware/fw_payload.bin /dev/ttyUSB2 112 | => run boot_dual 113 | Using eth0@60400000 device 114 | TFTP from server 10.0.0.1; our IP address is 10.0.0.2 115 | Filename 'image.itb'. 116 | Load address: 0x80100000 117 | [ 1.757872] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled 118 | [ 1.778840] printk: console [ttyS0] disabled 119 | [ 1.782014] 60200000.serial: ttyS0 at MMIO 0x60201000 (irq = 1, base_baud = 6250000) is a 16550A 120 | [ 1.787402] printk: console [ttyS0] enabled 121 | [ 1.787402] printk: console [ttyS0] enabled 122 | [ 1.792138] printk: bootconsole [sbi0] disabled 123 | [ 1.792138] printk: bootconsole [sbi0] disabled 124 | 125 | [ 1.847546] Freeing unused kernel image (initmem) memory: 2116K 126 | [ 1.851446] Run /init as init process 127 | Starting syslogd: OK 128 | Starting klogd: OK 129 | Running sysctl: OK 130 | 131 | Welcome to Buildroot 132 | buildroot login: root 133 | Jan 1 00:00:28 login[82]: root login on 'ttyS0' 134 | ``` 135 | 136 | Launch OpenOCD & GDB for debugging: 137 | 138 | ```shell 139 | $ openocd -f openocd.cfg 140 | Open On-Chip Debugger 0.12.0 141 | Licensed under GNU GPL v2 142 | For bug reports, read 143 | http://openocd.org/doc/doxygen/bugs.html 144 | 1 145 | Info : Listening on port 6666 for tcl connections 146 | Info : Listening on port 4444 for telnet connections 147 | Info : clock speed 10000 kHz 148 | Info : JTAG tap: riscv.cpu tap/device found: 0x10000913 (mfg: 0x489 (SiFive Inc), part: 0x0000, ver: 0x1) 149 | Info : datacount=2 progbufsize=16 150 | Info : Disabling abstract command reads from CSRs. 151 | Info : Examined RISC-V core; found 2 harts 152 | Info : hart 0: XLEN=64, misa=0x800000000094112d 153 | Info : starting gdb server for riscv.cpu.0 on 3333 154 | Info : Listening on port 3333 for gdb connections 155 | $ riscv64-unknown-elf-gdb 156 | GNU gdb (GDB) 12.0.50.20220308-git 157 | Copyright (C) 2022 Free Software Foundation, Inc. 158 | License GPLv3+: GNU GPL version 3 or later 159 | This is free software: you are free to change and redistribute it. 160 | There is NO WARRANTY, to the extent permitted by law. 161 | Type "show copying" and "show warranty" for details. 162 | This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv64-unknown-elf". 163 | Type "show configuration" for configuration details. 164 | For bug reporting instructions, please see: 165 | . 166 | Find the GDB manual and other documentation resources online at: 167 | . 168 | 169 | For help, type "help". 170 | Type "apropos word" to search for commands related to "word". 171 | (gdb) target extended-remote localhost:3333 172 | Remote debugging using localhost:3333 173 | warning: No executable has been specified and target does not support 174 | determining executable automatically. Try using the "file" command. 175 | 0x0000000000010106 in ?? () 176 | (gdb) 177 | ``` 178 | 179 | Boot process: 180 | 181 | 1. Run BootROM in 0x10000, load opensbi+uboot from serial 182 | 2. Run OpenSBI @ 0x80000000, jump to U-Boot at 0x80040000 183 | 3. U-Boot relocates to high address, load Linux kernel + dts from network at 0x80100000 184 | 4. Copy Linux kernel to 0x82000000 and jump to Linux kernel 185 | 186 | Performance of one big Rocket Chip running Linux @ 50MHz: 187 | 188 | - Dhrystone(-O2): 122850.1 per second, `122850.1 / 1757 / 50 = 1.40 DMIPS/MHz` 189 | - Coremark(-O2): 104.2 per second, `104.2 / 50 = 2.08 Coremark/MHz` 190 | - Whetstone: 33.3 MIPS 191 | 192 | Performance of one medium BOOM core running Linux @ 50MHz: 193 | 194 | - Dhrystone(-O2): 197238.7 per second, `197238.7 / 1757 / 50 = 2.25 DMIPS/MHz` 195 | - Coremark(-O2): 171.0 per second, `171.0 / 50 = 3.42 Coremark/MHz` 196 | - Whetstone: 50.0/100.0 MIPS 197 | -------------------------------------------------------------------------------- /bitstream.cfg: -------------------------------------------------------------------------------- 1 | # openocd config 2 | # use ftdi channel 0 3 | adapter speed 100000 4 | adapter driver ftdi 5 | transport select jtag 6 | ftdi_vid_pid 0x0403 0x6011 7 | ftdi_layout_init 0x0008 0x000b 8 | ftdi_tdo_sample_edge falling 9 | ftdi_channel 0 10 | reset_config none 11 | 12 | jtag newtap xcvu37p tap -irlen 18 -expected-id 0x14b79093 13 | 14 | init 15 | 16 | svf -tap xcvu37p.tap ../program.svf progress 17 | 18 | exit -------------------------------------------------------------------------------- /bootrom/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | -------------------------------------------------------------------------------- /bootrom/Makefile: -------------------------------------------------------------------------------- 1 | bootrom_img = bootrom.img 2 | 3 | GCC=riscv64-unknown-elf-gcc 4 | OBJCOPY=riscv64-unknown-elf-objcopy 5 | 6 | all: $(bootrom_img) 7 | 8 | %.img: %.elf 9 | $(OBJCOPY) -O binary $< $@ 10 | 11 | %.elf: %.S bootloader.c linker.ld 12 | $(GCC) -Tlinker.ld $< bootloader.c -ffreestanding -nostdlib -static -Wl,--no-gc-sections -o $@ 13 | -------------------------------------------------------------------------------- /bootrom/boot.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import sys 4 | import os 5 | import struct 6 | import serial 7 | import select 8 | import time 9 | import getopt 10 | import tqdm 11 | 12 | try: 13 | optlist, args = getopt.getopt(sys.argv[1:], 's') 14 | 15 | timeout = 0.01 16 | n = 1024 17 | slow = False 18 | 19 | for o, a in optlist: 20 | if o == "-s": 21 | slow = True 22 | n = 16 23 | print('Running in slow mode') 24 | 25 | out = serial.Serial(args[1], 115200, timeout=timeout) 26 | 27 | size = os.path.getsize(args[0]) 28 | out.write(struct.pack('>I', size)) 29 | with open(args[0], 'rb') as f: 30 | data = f.read() 31 | for i in tqdm.tqdm(range(0, len(data), n)): 32 | out.write(data[i:i+n]) 33 | if slow: 34 | time.sleep(timeout) 35 | 36 | out.close() 37 | os.execlp('screen', 'screen', '-L', args[1], '115200') 38 | except getopt.GetoptError as err: 39 | print(str(err)) 40 | print('Usage: send.py [-s] file tty') 41 | -------------------------------------------------------------------------------- /bootrom/bootloader.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | const uintptr_t UART_BASE = 0x60200000; 4 | volatile uint8_t *UART_RBR = (uint8_t *)(UART_BASE + 0x1000); 5 | volatile uint8_t *UART_THR = (uint8_t *)(UART_BASE + 0x1000); 6 | volatile uint8_t *UART_DLL = (uint8_t *)(UART_BASE + 0x1000); // LCR(7)=1 7 | volatile uint8_t *UART_IER = (uint8_t *)(UART_BASE + 0x1004); 8 | volatile uint8_t *UART_DLM = (uint8_t *)(UART_BASE + 0x1004); // LCR(7)=1 9 | volatile uint8_t *UART_FCR = (uint8_t *)(UART_BASE + 0x1008); 10 | volatile uint8_t *UART_LCR = (uint8_t *)(UART_BASE + 0x100C); 11 | volatile uint8_t *UART_MCR = (uint8_t *)(UART_BASE + 0x1010); 12 | volatile uint8_t *UART_LSR = (uint8_t *)(UART_BASE + 0x1014); 13 | volatile int *CLINT = (int *)0x2000000; 14 | 15 | void init_serial() { 16 | // Enable 8 bytes FIFO 17 | *UART_FCR = 0x81; 18 | // LCR(7) = 1 19 | *UART_LCR = 0x80; 20 | // 115200: 100M / 16 / 115200 = 54 21 | *UART_DLL = 54; 22 | *UART_DLM = 0; 23 | // LCR(7) = 0, 8N1 24 | *UART_LCR = ~0x80 & 0x03; 25 | *UART_MCR = 0; 26 | *UART_IER = 0; 27 | } 28 | 29 | void putc(char ch) { 30 | while (!(*UART_LSR & 0x40)) 31 | ; 32 | *UART_THR = ch; 33 | } 34 | 35 | uint8_t getc() { 36 | while (!(*UART_LSR & 0x1)) 37 | ; 38 | return *UART_RBR; 39 | } 40 | 41 | uint32_t getlen() { 42 | uint32_t len = 0; 43 | len |= getc(); 44 | len = len << 8; 45 | len |= getc(); 46 | len = len << 8; 47 | len |= getc(); 48 | len = len << 8; 49 | len |= getc(); 50 | return len; 51 | } 52 | 53 | void puts(char *s) { 54 | while (*s) { 55 | putc(*s++); 56 | } 57 | } 58 | 59 | void puthex(uint32_t num) { 60 | int i, temp; 61 | for (i = 7; i >= 0; i--) { 62 | temp = (num >> (i * 4)) & 0xF; 63 | if (temp <= 10) { 64 | putc('0' + temp); 65 | } else if (temp < 16) { 66 | putc('A' + temp - 10); 67 | } else { 68 | putc('.'); 69 | } 70 | } 71 | } 72 | 73 | void bootloader(int mhartid) { 74 | void (*boot)() = (void (*)())0x80000000; 75 | // Boot Hart 76 | init_serial(); 77 | puts("NO BOOT FAIL\r\n"); 78 | uint32_t len = getlen(); 79 | puts("LEN "); 80 | puthex(len); 81 | puts("\r\n"); 82 | volatile uint8_t *MEM = (uint8_t *)0x80000000; 83 | for (uint32_t i = 0; i < len; i++) { 84 | *MEM = getc(); 85 | MEM++; 86 | } 87 | puts("BOOT\r\n"); 88 | // ask hart 1 to jump 89 | CLINT[1] = 1; 90 | boot(); 91 | } 92 | 93 | void halt(uint32_t epc) { 94 | puts("HALT "); 95 | puthex(epc); 96 | } 97 | -------------------------------------------------------------------------------- /bootrom/bootrom.S: -------------------------------------------------------------------------------- 1 | #define DRAM_TOP 0x80800000 2 | #define DRAM_BASE 0x80000000 3 | 4 | .section .text.start, "ax", @progbits 5 | .globl _start 6 | _start: 7 | csrwi 0x7c1, 0 // disable chicken bits 8 | li sp, DRAM_TOP 9 | la s0, bootloader 10 | csrr a0, mhartid 11 | bnez a0, boot_other_hart 12 | 13 | la a1, _dtb 14 | jr s0 15 | 16 | .section .text.hang, "ax", @progbits 17 | .globl _hang 18 | _hang: 19 | csrwi 0x7c1, 0 // disable chicken bits 20 | csrr a0, mhartid 21 | la a1, _dtb 22 | csrwi mie, 0 23 | 1: 24 | wfi 25 | j 1b 26 | 27 | boot_other_hart: 28 | la s0, trap 29 | csrw mtvec, s0 30 | // enable m-mode software interrupt 31 | csrsi mie, 0x8 32 | // enable m-mode interrupt 33 | csrsi mstatus, 0x8 34 | j 1b 35 | 36 | .p2align 2 37 | trap: 38 | csrr a0, mhartid 39 | li s0, DRAM_BASE 40 | jr s0 41 | 42 | 43 | .section .rodata.dtb, "a", @progbits 44 | .globl _dtb 45 | .align 5, 0 46 | _dtb: 47 | .ascii "DTB goes here" 48 | -------------------------------------------------------------------------------- /bootrom/bootrom.img: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/rocket-chip-vcu128/7aa67a4046fdebdc74d05a61fe0a4eec4dd2cf8f/bootrom/bootrom.img -------------------------------------------------------------------------------- /bootrom/linker.ld: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | ROM_BASE = 0x10000; /* ... but actually position independent */ 4 | 5 | . = ROM_BASE; 6 | .text.start : { *(.text.start) } 7 | . = ROM_BASE + 0x40; 8 | .text.hang : { *(.text.hang) } 9 | } 10 | -------------------------------------------------------------------------------- /build.sc: -------------------------------------------------------------------------------- 1 | import mill._ 2 | import mill.scalalib.publish._ 3 | import scalalib._ 4 | import scalafmt._ 5 | import coursier.maven.MavenRepository 6 | import $ivy.`com.goyeau::mill-scalafix_mill0.11:0.3.1` 7 | import com.goyeau.mill.scalafix.ScalafixModule 8 | 9 | // learned from https://github.com/OpenXiangShan/fudian/blob/main/build.sc 10 | val defaultVersions = Map( 11 | "chisel" -> ("org.chipsalliance", "6.6.0", false), 12 | "chisel-plugin" -> ("org.chipsalliance", "6.6.0", true), 13 | "json4s-jackson" -> ("org.json4s", "4.0.6", false), 14 | "chiseltest" -> ("edu.berkeley.cs", "0.6.0-RC3", false), 15 | "scalatest" -> ("org.scalatest", "3.2.15", false), 16 | "sourcecode" -> ("com.lihaoyi", "0.3.1", false), 17 | "mainargs" -> ("com.lihaoyi", "0.5.0", false), 18 | ) 19 | 20 | val commonScalaVersion = "2.13.15" 21 | 22 | def getVersion(dep: String) = { 23 | val (org, ver, cross) = defaultVersions(dep) 24 | val version = sys.env.getOrElse(dep + "Version", ver) 25 | if (cross) 26 | ivy"$org:::$dep:$version" 27 | else 28 | ivy"$org::$dep:$version" 29 | } 30 | 31 | trait CommonModule extends ScalaModule { 32 | def scalaVersion = commonScalaVersion 33 | 34 | // for snapshot dependencies 35 | override def repositoriesTask = T.task { 36 | super.repositoriesTask() ++ Seq( 37 | MavenRepository("https://oss.sonatype.org/content/repositories/snapshots") 38 | ) 39 | } 40 | 41 | // for scalafix rules 42 | override def scalacOptions = 43 | Seq("-Ywarn-unused", "-deprecation") 44 | } 45 | 46 | object hardfloat extends CommonModule with SbtModule { 47 | override def millSourcePath = 48 | os.pwd / "submodules" / "berkeley-hardfloat" / "hardfloat" 49 | 50 | override def ivyDeps = super.ivyDeps() ++ Agg( 51 | getVersion("chisel") 52 | ) 53 | 54 | override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg( 55 | getVersion("chisel-plugin") 56 | ) 57 | } 58 | 59 | object apiConfigChipsalliance extends CommonModule { 60 | override def millSourcePath = 61 | os.pwd / "submodules" / "api-config-chipsalliance" / "cde" 62 | } 63 | 64 | object diplomacy extends CommonModule with ScalaModule { 65 | override def millSourcePath = 66 | os.pwd / "submodules" / "diplomacy" / "diplomacy" 67 | 68 | override def ivyDeps = super.ivyDeps() ++ Agg( 69 | getVersion("chisel"), 70 | getVersion("sourcecode"), 71 | ) 72 | 73 | override def moduleDeps = 74 | super.moduleDeps ++ Seq( 75 | apiConfigChipsalliance 76 | ) 77 | 78 | override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg( 79 | getVersion("chisel-plugin") 80 | ) 81 | } 82 | 83 | object rocketChipMacros extends CommonModule { 84 | override def millSourcePath = os.pwd / "submodules" / "rocket-chip" / "macros" 85 | 86 | override def ivyDeps = super.ivyDeps() ++ Agg( 87 | ivy"org.scala-lang:scala-reflect:$commonScalaVersion" 88 | ) 89 | } 90 | 91 | object rocketChip extends CommonModule with SbtModule { 92 | override def millSourcePath = os.pwd / "submodules" / "rocket-chip" 93 | 94 | override def ivyDeps = super.ivyDeps() ++ Agg( 95 | getVersion("chisel"), 96 | getVersion("mainargs"), 97 | getVersion("json4s-jackson"), 98 | ivy"org.scala-lang:scala-reflect:$commonScalaVersion" 99 | ) 100 | 101 | override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg( 102 | getVersion("chisel-plugin") 103 | ) 104 | 105 | override def moduleDeps = 106 | super.moduleDeps ++ Seq( 107 | hardfloat, 108 | rocketChipMacros, 109 | apiConfigChipsalliance, 110 | diplomacy 111 | ) 112 | 113 | override def scalacOptions = super.scalacOptions() ++ 114 | Seq("-deprecation", "-unchecked") 115 | } 116 | 117 | object boom extends CommonModule with SbtModule { 118 | override def millSourcePath = os.pwd / "submodules" / "riscv-boom" 119 | override def moduleDeps = super.moduleDeps ++ Seq(rocketChip) 120 | override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg( 121 | getVersion("chisel-plugin") 122 | ) 123 | } 124 | 125 | object inclusiveCache extends CommonModule with ScalaModule { 126 | override def millSourcePath = 127 | os.pwd / "submodules" / "rocket-chip-inclusive-cache" / "design" / "craft" / "inclusivecache" 128 | override def moduleDeps = super.moduleDeps ++ Seq(rocketChip) 129 | override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg( 130 | getVersion("chisel-plugin") 131 | ) 132 | } 133 | 134 | object vcu128 extends CommonModule with ScalafmtModule { 135 | override def millSourcePath = os.pwd 136 | 137 | override def ivyDeps = super.ivyDeps() ++ Agg( 138 | getVersion("chisel"), 139 | getVersion("chiseltest") 140 | ) 141 | 142 | override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg( 143 | getVersion("chisel-plugin") 144 | ) 145 | 146 | override def moduleDeps = 147 | super.moduleDeps ++ Seq( 148 | apiConfigChipsalliance, 149 | rocketChip, 150 | boom, 151 | inclusiveCache 152 | ) 153 | 154 | object test extends ScalaTests with TestModule.ScalaTest { 155 | override def ivyDeps = super.ivyDeps() ++ Agg( 156 | getVersion("scalatest") 157 | ) 158 | } 159 | } 160 | -------------------------------------------------------------------------------- /gdbinit: -------------------------------------------------------------------------------- 1 | target extended-remote localhost:3333 2 | -------------------------------------------------------------------------------- /hw_handoff/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/rocket-chip-vcu128/7aa67a4046fdebdc74d05a61fe0a4eec4dd2cf8f/hw_handoff/.keep -------------------------------------------------------------------------------- /openocd.cfg: -------------------------------------------------------------------------------- 1 | # openocd config 2 | # use ftdi channel 1 3 | # vcu128 uart0 as jtag 4 | adapter speed 10000 5 | adapter driver ftdi 6 | ftdi_vid_pid 0x0403 0x6011 7 | ftdi_layout_init 0x0008 0x000b 8 | ftdi_tdo_sample_edge falling 9 | ftdi_channel 1 10 | reset_config none 11 | 12 | set _CHIPNAME riscv 13 | jtag newtap $_CHIPNAME cpu -irlen 5 14 | 15 | set _TARGETNAME $_CHIPNAME.cpu 16 | 17 | target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME 18 | $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 -------------------------------------------------------------------------------- /proj/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/rocket-chip-vcu128/7aa67a4046fdebdc74d05a61fe0a4eec4dd2cf8f/proj/.keep -------------------------------------------------------------------------------- /project_info.tcl: -------------------------------------------------------------------------------- 1 | # This is an automatically generated file used by digilent_vivado_checkout.tcl to set project options 2 | proc set_project_properties_post_create_project {proj_name} { 3 | set project_obj [get_projects $proj_name] 4 | set_property "part" "xcvu37p-fsvh2892-2L-e" $project_obj 5 | set_property "board_part" "xilinx.com:vcu128:part0:1.0" $project_obj 6 | set_property "default_lib" "xil_defaultlib" $project_obj 7 | set_property "simulator_language" "Mixed" $project_obj 8 | set_property "target_language" "Verilog" $project_obj 9 | } 10 | 11 | proc set_project_properties_pre_add_repo {proj_name} { 12 | set project_obj [get_projects $proj_name] 13 | # default nothing 14 | } 15 | 16 | proc set_project_properties_post_create_runs {proj_name} { 17 | set project_obj [get_projects $proj_name] 18 | #Custom directives for synthesis and implementation 19 | set_property STEPS.WRITE_BITSTREAM.ARGS.READBACK_FILE 0 [get_runs impl_1] 20 | set_property STEPS.WRITE_BITSTREAM.ARGS.VERBOSE 0 [get_runs impl_1] 21 | } 22 | -------------------------------------------------------------------------------- /rbb.cfg: -------------------------------------------------------------------------------- 1 | # openocd config 2 | # remote bitbang 3 | # for simulation 4 | adapter speed 10000 5 | adapter driver remote_bitbang 6 | remote_bitbang_host localhost 7 | remote_bitbang_port 12345 8 | 9 | set _CHIPNAME riscv 10 | jtag newtap $_CHIPNAME cpu -irlen 5 11 | 12 | set _TARGETNAME $_CHIPNAME.cpu 13 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 14 | 15 | riscv set_reset_timeout_sec 120 16 | riscv set_command_timeout_sec 120 17 | 18 | init 19 | halt 20 | echo "Ready for Remote Connections" 21 | -------------------------------------------------------------------------------- /repo/local/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/rocket-chip-vcu128/7aa67a4046fdebdc74d05a61fe0a4eec4dd2cf8f/repo/local/.keep -------------------------------------------------------------------------------- /reset.tcl: -------------------------------------------------------------------------------- 1 | open_hw_manager 2 | #connect_hw_server 3 | open_hw_target 4 | set_property PROGRAM.FILE {./proj/rocket-chip-vcu128.runs/impl_1/system_wrapper.bit} [lindex [get_hw_devices] 0] 5 | set_property PROBES.FILE {./proj/rocket-chip-vcu128.runs/impl_1/system_wrapper.ltx} [lindex [get_hw_devices] 0] 6 | refresh_hw_device 7 | 8 | set_property OUTPUT_VALUE 1 [get_hw_probes system_i/vio_0_probe_out0] 9 | commit_hw_vio [get_hw_probes {system_i/vio_0_probe_out0}] 10 | set_property OUTPUT_VALUE 0 [get_hw_probes system_i/vio_0_probe_out0] 11 | commit_hw_vio [get_hw_probes {system_i/vio_0_probe_out0}] 12 | set_property OUTPUT_VALUE 1 [get_hw_probes system_i/vio_0_probe_out0] 13 | commit_hw_vio [get_hw_probes {system_i/vio_0_probe_out0}] 14 | -------------------------------------------------------------------------------- /shell.nix: -------------------------------------------------------------------------------- 1 | { pkgs ? import (fetchTarball "https://github.com/NixOS/nixpkgs/archive/7995cae3ad60e3d6931283d650d7f43d31aaa5c7.tar.gz") {} 2 | }: 3 | 4 | pkgs.mkShell { 5 | buildInputs = with pkgs; [ 6 | circt # 1.62.0 7 | gmp 8 | ncurses 9 | ]; 10 | } 11 | 12 | -------------------------------------------------------------------------------- /software/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.img -------------------------------------------------------------------------------- /software/Makefile: -------------------------------------------------------------------------------- 1 | GCC=riscv64-unknown-elf-gcc 2 | OBJCOPY=riscv64-unknown-elf-objcopy 3 | 4 | all: img 5 | 6 | img: uart.img 7 | 8 | %.img: %.elf 9 | $(OBJCOPY) -O binary --change-addresses=-0x80200000 $< $@ 10 | 11 | %.elf: %.c linker.ld 12 | $(GCC) -mcmodel=medany -mabi=lp64 -march=rv64ima -Tlinker.ld init.S $< -nostdlib -ffreestanding -static -o $@ 13 | -------------------------------------------------------------------------------- /software/common.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | const uintptr_t UART_BASE = 0x60200000; 4 | volatile uint8_t *UART_RBR = (uint8_t *)(UART_BASE + 0x1000); 5 | volatile uint8_t *UART_THR = (uint8_t *)(UART_BASE + 0x1000); 6 | volatile uint8_t *UART_DLL = (uint8_t *)(UART_BASE + 0x1000); // LCR(7)=1 7 | volatile uint8_t *UART_IER = (uint8_t *)(UART_BASE + 0x1004); 8 | volatile uint8_t *UART_DLM = (uint8_t *)(UART_BASE + 0x1004); // LCR(7)=1 9 | volatile uint8_t *UART_FCR = (uint8_t *)(UART_BASE + 0x1008); 10 | volatile uint8_t *UART_LCR = (uint8_t *)(UART_BASE + 0x100C); 11 | volatile uint8_t *UART_MCR = (uint8_t *)(UART_BASE + 0x1010); 12 | volatile uint8_t *UART_LSR = (uint8_t *)(UART_BASE + 0x1014); 13 | 14 | void init_serial() { 15 | // Enable 8 bytes FIFO 16 | *UART_FCR = 0x81; 17 | // LCR(7) = 1 18 | *UART_LCR = 0x80; 19 | // 115200: 100M / 16 / 115200 = 54 20 | *UART_DLL = 54; 21 | *UART_DLM = 0; 22 | // LCR(7) = 0, 8N1 23 | *UART_LCR = ~0x80 & 0x03; 24 | *UART_MCR = 0; 25 | *UART_IER = 0; 26 | } 27 | 28 | void putc(char ch) { 29 | while (!(*UART_LSR & 0x40)) 30 | ; 31 | *UART_THR = ch; 32 | } 33 | 34 | uint8_t getc() { 35 | while (!(*UART_LSR & 0x1)) 36 | ; 37 | return *UART_RBR; 38 | } 39 | 40 | uint32_t getlen() { 41 | uint32_t len = 0; 42 | len |= getc(); 43 | len = len << 8; 44 | len |= getc(); 45 | len = len << 8; 46 | len |= getc(); 47 | len = len << 8; 48 | len |= getc(); 49 | return len; 50 | } 51 | 52 | void puts(char *s) { 53 | while (*s) { 54 | putc(*s++); 55 | } 56 | } 57 | 58 | void puthex(uint32_t num) { 59 | int i, temp; 60 | for (i = 7; i >= 0; i--) { 61 | temp = (num >> (i * 4)) & 0xF; 62 | if (temp <= 10) { 63 | putc('0' + temp); 64 | } else if (temp < 16) { 65 | putc('A' + temp - 10); 66 | } else { 67 | putc('.'); 68 | } 69 | } 70 | } 71 | -------------------------------------------------------------------------------- /software/init.S: -------------------------------------------------------------------------------- 1 | #define DRAM_TOP 0x88000000 2 | 3 | .section .text.start, "ax", @progbits 4 | .globl _start 5 | _start: 6 | li sp, DRAM_TOP // setup stack 7 | jal main 8 | 9 | _hang: 10 | j _hang -------------------------------------------------------------------------------- /software/linker.ld: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | RAM_BASE = 0x80200000; 4 | 5 | . = RAM_BASE; 6 | .text.init : { 7 | *(.text.init .text.init.*) 8 | } 9 | .text : { 10 | *(.text .text.*) 11 | } 12 | .data : { 13 | *(.data .data.*) 14 | } 15 | .sdata : { 16 | *(.sdata .sdata.*) 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /software/uart.c: -------------------------------------------------------------------------------- 1 | #include "common.h" 2 | 3 | void main() { 4 | puts("test\r\n"); 5 | for (;;){ 6 | 7 | } 8 | } -------------------------------------------------------------------------------- /src/bd/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/rocket-chip-vcu128/7aa67a4046fdebdc74d05a61fe0a4eec4dd2cf8f/src/bd/.keep -------------------------------------------------------------------------------- /src/bd/system.tcl: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # This is a generated script based on design: system 4 | # 5 | # Though there are limitations about the generated script, 6 | # the main purpose of this utility is to make learning 7 | # IP Integrator Tcl commands easier. 8 | ################################################################ 9 | 10 | namespace eval _tcl { 11 | proc get_script_folder {} { 12 | set script_path [file normalize [info script]] 13 | set script_folder [file dirname $script_path] 14 | return $script_folder 15 | } 16 | } 17 | variable script_folder 18 | set script_folder [_tcl::get_script_folder] 19 | 20 | ################################################################ 21 | # Check if script is running in correct Vivado version. 22 | ################################################################ 23 | set scripts_vivado_version 2020.2 24 | set current_vivado_version [version -short] 25 | 26 | if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { 27 | puts "" 28 | catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} 29 | 30 | return 1 31 | } 32 | 33 | ################################################################ 34 | # START 35 | ################################################################ 36 | 37 | # To test this script, run the following commands from Vivado Tcl console: 38 | # source system_script.tcl 39 | 40 | 41 | # The design that will be created by this Tcl script contains the following 42 | # module references: 43 | # rocketchip_wrapper 44 | 45 | # Please add the sources of those modules before sourcing this Tcl script. 46 | 47 | # If there is no project opened, this script will create a 48 | # project, but make sure you do not have an existing project 49 | # <./myproj/project_1.xpr> in the current working folder. 50 | 51 | set list_projs [get_projects -quiet] 52 | if { $list_projs eq "" } { 53 | create_project project_1 myproj -part xcvu37p-fsvh2892-2L-e 54 | set_property BOARD_PART xilinx.com:vcu128:part0:1.0 [current_project] 55 | } 56 | 57 | 58 | # CHANGE DESIGN NAME HERE 59 | variable design_name 60 | set design_name system 61 | 62 | # If you do not already have an existing IP Integrator design open, 63 | # you can create a design using the following command: 64 | # create_bd_design $design_name 65 | 66 | # Creating design if needed 67 | set errMsg "" 68 | set nRet 0 69 | 70 | set cur_design [current_bd_design -quiet] 71 | set list_cells [get_bd_cells -quiet] 72 | 73 | if { ${design_name} eq "" } { 74 | # USE CASES: 75 | # 1) Design_name not set 76 | 77 | set errMsg "Please set the variable to a non-empty value." 78 | set nRet 1 79 | 80 | } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { 81 | # USE CASES: 82 | # 2): Current design opened AND is empty AND names same. 83 | # 3): Current design opened AND is empty AND names diff; design_name NOT in project. 84 | # 4): Current design opened AND is empty AND names diff; design_name exists in project. 85 | 86 | if { $cur_design ne $design_name } { 87 | common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." 88 | set design_name [get_property NAME $cur_design] 89 | } 90 | common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." 91 | 92 | } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { 93 | # USE CASES: 94 | # 5) Current design opened AND has components AND same names. 95 | 96 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 97 | set nRet 1 98 | } elseif { [get_files -quiet ${design_name}.bd] ne "" } { 99 | # USE CASES: 100 | # 6) Current opened design, has components, but diff names, design_name exists in project. 101 | # 7) No opened design, design_name exists in project. 102 | 103 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 104 | set nRet 2 105 | 106 | } else { 107 | # USE CASES: 108 | # 8) No opened design, design_name not in project. 109 | # 9) Current opened design, has components, but diff names, design_name not in project. 110 | 111 | common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." 112 | 113 | create_bd_design $design_name 114 | 115 | common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." 116 | current_bd_design $design_name 117 | 118 | } 119 | 120 | common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." 121 | 122 | if { $nRet != 0 } { 123 | catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} 124 | return $nRet 125 | } 126 | 127 | set bCheckIPsPassed 1 128 | ################################################################## 129 | # CHECK IPs 130 | ################################################################## 131 | set bCheckIPs 1 132 | if { $bCheckIPs == 1 } { 133 | set list_check_ips "\ 134 | xilinx.com:ip:axi_ethernet:7.2\ 135 | xilinx.com:ip:axi_dma:7.1\ 136 | xilinx.com:ip:axi_iic:2.0\ 137 | xilinx.com:ip:axi_quad_spi:3.2\ 138 | xilinx.com:ip:axi_uart16550:2.0\ 139 | xilinx.com:ip:clk_wiz:6.0\ 140 | xilinx.com:ip:hbm:1.0\ 141 | xilinx.com:ip:jtag_axi:1.2\ 142 | xilinx.com:ip:proc_sys_reset:5.0\ 143 | xilinx.com:ip:vio:3.0\ 144 | xilinx.com:ip:xlconcat:2.1\ 145 | xilinx.com:ip:xlconstant:1.1\ 146 | " 147 | 148 | set list_ips_missing "" 149 | common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." 150 | 151 | foreach ip_vlnv $list_check_ips { 152 | set ip_obj [get_ipdefs -all $ip_vlnv] 153 | if { $ip_obj eq "" } { 154 | lappend list_ips_missing $ip_vlnv 155 | } 156 | } 157 | 158 | if { $list_ips_missing ne "" } { 159 | catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } 160 | set bCheckIPsPassed 0 161 | } 162 | 163 | } 164 | 165 | ################################################################## 166 | # CHECK Modules 167 | ################################################################## 168 | set bCheckModules 1 169 | if { $bCheckModules == 1 } { 170 | set list_check_mods "\ 171 | rocketchip_wrapper\ 172 | " 173 | 174 | set list_mods_missing "" 175 | common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." 176 | 177 | foreach mod_vlnv $list_check_mods { 178 | if { [can_resolve_reference $mod_vlnv] == 0 } { 179 | lappend list_mods_missing $mod_vlnv 180 | } 181 | } 182 | 183 | if { $list_mods_missing ne "" } { 184 | catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } 185 | common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." 186 | set bCheckIPsPassed 0 187 | } 188 | } 189 | 190 | if { $bCheckIPsPassed != 1 } { 191 | common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." 192 | return 3 193 | } 194 | 195 | ################################################################## 196 | # DESIGN PROCs 197 | ################################################################## 198 | 199 | 200 | 201 | # Procedure to create entire design; Provide argument to make 202 | # procedure reusable. If parentCell is "", will use root. 203 | proc create_root_design { parentCell } { 204 | 205 | variable script_folder 206 | variable design_name 207 | 208 | if { $parentCell eq "" } { 209 | set parentCell [get_bd_cells /] 210 | } 211 | 212 | # Get object for parentCell 213 | set parentObj [get_bd_cells $parentCell] 214 | if { $parentObj == "" } { 215 | catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} 216 | return 217 | } 218 | 219 | # Make sure parentObj is hier blk 220 | set parentType [get_property TYPE $parentObj] 221 | if { $parentType ne "hier" } { 222 | catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 223 | return 224 | } 225 | 226 | # Save current instance; Restore later 227 | set oldCurInst [current_bd_instance .] 228 | 229 | # Set parent object as current 230 | current_bd_instance $parentObj 231 | 232 | 233 | # Create interface ports 234 | set default_100mhz_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_100mhz_clk ] 235 | set_property -dict [ list \ 236 | CONFIG.FREQ_HZ {100000000} \ 237 | ] $default_100mhz_clk 238 | 239 | set iic_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_0 ] 240 | 241 | set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ] 242 | 243 | set rs232_uart_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart_0 ] 244 | 245 | set sgmii_lvds [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii_lvds ] 246 | 247 | set sgmii_phyclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sgmii_phyclk ] 248 | set_property -dict [ list \ 249 | CONFIG.FREQ_HZ {625000000} \ 250 | ] $sgmii_phyclk 251 | 252 | 253 | # Create ports 254 | set dummy_port_in [ create_bd_port -dir I -type rst dummy_port_in ] 255 | set_property -dict [ list \ 256 | CONFIG.POLARITY {ACTIVE_HIGH} \ 257 | ] $dummy_port_in 258 | set jtag_TCK [ create_bd_port -dir I jtag_TCK ] 259 | set jtag_TDI [ create_bd_port -dir I jtag_TDI ] 260 | set jtag_TDO [ create_bd_port -dir O jtag_TDO ] 261 | set jtag_TMS [ create_bd_port -dir I jtag_TMS ] 262 | set reset [ create_bd_port -dir I -type rst reset ] 263 | set_property -dict [ list \ 264 | CONFIG.POLARITY {ACTIVE_HIGH} \ 265 | ] $reset 266 | 267 | # Create instance: axi_ethernet_0, and set properties 268 | set axi_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.2 axi_ethernet_0 ] 269 | set_property -dict [ list \ 270 | CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk} \ 271 | CONFIG.ENABLE_LVDS {true} \ 272 | CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds} \ 273 | CONFIG.InstantiateBitslice0 {true} \ 274 | CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} \ 275 | CONFIG.PHYADDR {0} \ 276 | CONFIG.PHYRST_BOARD_INTERFACE {Custom} \ 277 | CONFIG.PHYRST_BOARD_INTERFACE_DUMMY_PORT {dummy_port_in} \ 278 | CONFIG.PHY_TYPE {SGMII} \ 279 | CONFIG.RXCSUM {Full} \ 280 | CONFIG.TXCSUM {Full} \ 281 | CONFIG.lvdsclkrate {625} \ 282 | CONFIG.rxlane0_placement {DIFF_PAIR_2} \ 283 | CONFIG.rxnibblebitslice0used {false} \ 284 | CONFIG.txlane0_placement {DIFF_PAIR_1} \ 285 | ] $axi_ethernet_0 286 | 287 | # Create instance: axi_ethernet_0_dma, and set properties 288 | set axi_ethernet_0_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_0_dma ] 289 | set_property -dict [ list \ 290 | CONFIG.c_addr_width {64} \ 291 | CONFIG.c_include_mm2s_dre {1} \ 292 | CONFIG.c_include_s2mm_dre {1} \ 293 | CONFIG.c_m_axi_mm2s_data_width {32} \ 294 | CONFIG.c_m_axis_mm2s_tdata_width {32} \ 295 | CONFIG.c_mm2s_burst_size {16} \ 296 | CONFIG.c_sg_length_width {16} \ 297 | CONFIG.c_sg_use_stsapp_length {1} \ 298 | ] $axi_ethernet_0_dma 299 | 300 | # Create instance: axi_iic_0, and set properties 301 | set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ] 302 | set_property -dict [ list \ 303 | CONFIG.IIC_BOARD_INTERFACE {iic_0} \ 304 | CONFIG.USE_BOARD_FLOW {true} \ 305 | ] $axi_iic_0 306 | 307 | # Create instance: axi_interconnect_0, and set properties 308 | set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] 309 | set_property -dict [ list \ 310 | CONFIG.NUM_MI {1} \ 311 | CONFIG.NUM_SI {4} \ 312 | ] $axi_interconnect_0 313 | 314 | # Create instance: axi_interconnect_1, and set properties 315 | set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ] 316 | set_property -dict [ list \ 317 | CONFIG.NUM_MI {1} \ 318 | ] $axi_interconnect_1 319 | 320 | # Create instance: axi_mem_intercon, and set properties 321 | set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] 322 | set_property -dict [ list \ 323 | CONFIG.NUM_MI {6} \ 324 | CONFIG.NUM_SI {1} \ 325 | ] $axi_mem_intercon 326 | 327 | # Create instance: axi_quad_spi_0, and set properties 328 | set axi_quad_spi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0 ] 329 | set_property -dict [ list \ 330 | CONFIG.C_FIFO_DEPTH {256} \ 331 | CONFIG.C_SCK_RATIO {2} \ 332 | CONFIG.C_SPI_MEMORY {2} \ 333 | CONFIG.C_SPI_MEM_ADDR_BITS {24} \ 334 | CONFIG.C_SPI_MODE {0} \ 335 | CONFIG.C_TYPE_OF_AXI4_INTERFACE {1} \ 336 | CONFIG.C_USE_STARTUP {1} \ 337 | CONFIG.C_USE_STARTUP_INT {1} \ 338 | CONFIG.C_XIP_MODE {0} \ 339 | CONFIG.C_XIP_PERF_MODE {0} \ 340 | ] $axi_quad_spi_0 341 | 342 | # Create instance: axi_uart16550_0, and set properties 343 | set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ] 344 | set_property -dict [ list \ 345 | CONFIG.UART_BOARD_INTERFACE {rs232_uart_1} \ 346 | CONFIG.USE_BOARD_FLOW {true} \ 347 | ] $axi_uart16550_0 348 | 349 | # Create instance: clk_wiz_0, and set properties 350 | set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] 351 | set_property -dict [ list \ 352 | CONFIG.CLKOUT2_JITTER {132.683} \ 353 | CONFIG.CLKOUT2_PHASE_ERROR {87.180} \ 354 | CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50} \ 355 | CONFIG.CLKOUT2_USED {true} \ 356 | CONFIG.CLK_IN1_BOARD_INTERFACE {default_100mhz_clk} \ 357 | CONFIG.CLK_OUT1_PORT {clk_100M} \ 358 | CONFIG.CLK_OUT2_PORT {clk_50M} \ 359 | CONFIG.MMCM_CLKOUT1_DIVIDE {24} \ 360 | CONFIG.NUM_OUT_CLKS {2} \ 361 | CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \ 362 | CONFIG.RESET_BOARD_INTERFACE {Custom} \ 363 | CONFIG.USE_BOARD_FLOW {true} \ 364 | ] $clk_wiz_0 365 | 366 | # Create instance: hbm_0, and set properties 367 | set hbm_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:hbm:1.0 hbm_0 ] 368 | set_property -dict [ list \ 369 | CONFIG.USER_APB_EN {false} \ 370 | CONFIG.USER_CLK_SEL_LIST0 {AXI_00_ACLK} \ 371 | CONFIG.USER_SAXI_01 {false} \ 372 | CONFIG.USER_SAXI_02 {false} \ 373 | CONFIG.USER_SAXI_03 {false} \ 374 | CONFIG.USER_SAXI_04 {false} \ 375 | CONFIG.USER_SAXI_05 {false} \ 376 | CONFIG.USER_SAXI_06 {false} \ 377 | CONFIG.USER_SAXI_07 {false} \ 378 | CONFIG.USER_SAXI_08 {false} \ 379 | CONFIG.USER_SAXI_09 {false} \ 380 | CONFIG.USER_SAXI_10 {false} \ 381 | CONFIG.USER_SAXI_11 {false} \ 382 | CONFIG.USER_SAXI_12 {false} \ 383 | CONFIG.USER_SAXI_13 {false} \ 384 | CONFIG.USER_SAXI_14 {false} \ 385 | CONFIG.USER_SAXI_15 {false} \ 386 | ] $hbm_0 387 | 388 | # Create instance: jtag_axi_0, and set properties 389 | set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] 390 | set_property -dict [ list \ 391 | CONFIG.M_AXI_ADDR_WIDTH {64} \ 392 | CONFIG.M_AXI_DATA_WIDTH {64} \ 393 | ] $jtag_axi_0 394 | 395 | # Create instance: rocketchip_wrapper_0, and set properties 396 | set block_name rocketchip_wrapper 397 | set block_cell_name rocketchip_wrapper_0 398 | if { [catch {set rocketchip_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { 399 | catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} 400 | return 1 401 | } elseif { $rocketchip_wrapper_0 eq "" } { 402 | catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} 403 | return 1 404 | } 405 | 406 | # Create instance: rst_clk_wiz_0_100M, and set properties 407 | set rst_clk_wiz_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_0_100M ] 408 | 409 | # Create instance: vio_0, and set properties 410 | set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ] 411 | set_property -dict [ list \ 412 | CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ 413 | CONFIG.C_NUM_PROBE_IN {0} \ 414 | CONFIG.C_PROBE_OUT0_INIT_VAL {0x1} \ 415 | ] $vio_0 416 | 417 | # Create instance: xlconcat_0, and set properties 418 | set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] 419 | set_property -dict [ list \ 420 | CONFIG.NUM_PORTS {6} \ 421 | ] $xlconcat_0 422 | 423 | # Create instance: xlconstant_0, and set properties 424 | set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] 425 | set_property -dict [ list \ 426 | CONFIG.CONST_VAL {0} \ 427 | ] $xlconstant_0 428 | 429 | # Create interface connections 430 | connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins rocketchip_wrapper_0/M_AXI_MMIO] 431 | connect_bd_intf_net -intf_net S00_AXI_2 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins rocketchip_wrapper_0/M_AXI] 432 | connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXIS_CNTRL [get_bd_intf_pins axi_ethernet_0/s_axis_txc] [get_bd_intf_pins axi_ethernet_0_dma/M_AXIS_CNTRL] 433 | connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXIS_MM2S [get_bd_intf_pins axi_ethernet_0/s_axis_txd] [get_bd_intf_pins axi_ethernet_0_dma/M_AXIS_MM2S] 434 | connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXI_MM2S [get_bd_intf_pins axi_ethernet_0_dma/M_AXI_MM2S] [get_bd_intf_pins axi_interconnect_0/S01_AXI] 435 | connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXI_S2MM [get_bd_intf_pins axi_ethernet_0_dma/M_AXI_S2MM] [get_bd_intf_pins axi_interconnect_0/S02_AXI] 436 | connect_bd_intf_net -intf_net axi_ethernet_0_dma_M_AXI_SG [get_bd_intf_pins axi_ethernet_0_dma/M_AXI_SG] [get_bd_intf_pins axi_interconnect_0/S00_AXI] 437 | connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxd [get_bd_intf_pins axi_ethernet_0/m_axis_rxd] [get_bd_intf_pins axi_ethernet_0_dma/S_AXIS_S2MM] 438 | connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxs [get_bd_intf_pins axi_ethernet_0/m_axis_rxs] [get_bd_intf_pins axi_ethernet_0_dma/S_AXIS_STS] 439 | connect_bd_intf_net -intf_net axi_ethernet_0_mdio [get_bd_intf_ports mdio_mdc] [get_bd_intf_pins axi_ethernet_0/mdio] 440 | connect_bd_intf_net -intf_net axi_ethernet_0_sgmii [get_bd_intf_ports sgmii_lvds] [get_bd_intf_pins axi_ethernet_0/sgmii] 441 | connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_ports iic_0] [get_bd_intf_pins axi_iic_0/IIC] 442 | connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins rocketchip_wrapper_0/S_AXI] 443 | connect_bd_intf_net -intf_net axi_interconnect_1_M00_AXI [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins hbm_0/SAXI_00] 444 | connect_bd_intf_net -intf_net axi_mem_intercon_M01_AXI [get_bd_intf_pins axi_mem_intercon/M01_AXI] [get_bd_intf_pins axi_quad_spi_0/AXI_FULL] 445 | connect_bd_intf_net -intf_net axi_mem_intercon_M02_AXI [get_bd_intf_pins axi_mem_intercon/M02_AXI] [get_bd_intf_pins axi_uart16550_0/S_AXI] 446 | connect_bd_intf_net -intf_net axi_mem_intercon_M03_AXI [get_bd_intf_pins axi_ethernet_0/s_axi] [get_bd_intf_pins axi_mem_intercon/M03_AXI] 447 | connect_bd_intf_net -intf_net axi_mem_intercon_M04_AXI [get_bd_intf_pins axi_ethernet_0_dma/S_AXI_LITE] [get_bd_intf_pins axi_mem_intercon/M04_AXI] 448 | connect_bd_intf_net -intf_net axi_mem_intercon_M05_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins axi_mem_intercon/M05_AXI] 449 | connect_bd_intf_net -intf_net axi_uart16550_0_UART [get_bd_intf_ports rs232_uart_0] [get_bd_intf_pins axi_uart16550_0/UART] 450 | connect_bd_intf_net -intf_net default_100mhz_clk_1 [get_bd_intf_ports default_100mhz_clk] [get_bd_intf_pins clk_wiz_0/CLK_IN1_D] 451 | connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins axi_interconnect_0/S03_AXI] [get_bd_intf_pins jtag_axi_0/M_AXI] 452 | connect_bd_intf_net -intf_net sgmii_phyclk_1 [get_bd_intf_ports sgmii_phyclk] [get_bd_intf_pins axi_ethernet_0/lvds_clk] 453 | 454 | # Create port connections 455 | connect_bd_net -net ARESETN_1 [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins rst_clk_wiz_0_100M/interconnect_aresetn] 456 | connect_bd_net -net axi_ethernet_0_dma_mm2s_cntrl_reset_out_n [get_bd_pins axi_ethernet_0/axi_txc_arstn] [get_bd_pins axi_ethernet_0_dma/mm2s_cntrl_reset_out_n] 457 | connect_bd_net -net axi_ethernet_0_dma_mm2s_introut [get_bd_pins axi_ethernet_0_dma/mm2s_introut] [get_bd_pins xlconcat_0/In4] 458 | connect_bd_net -net axi_ethernet_0_dma_mm2s_prmry_reset_out_n [get_bd_pins axi_ethernet_0/axi_txd_arstn] [get_bd_pins axi_ethernet_0_dma/mm2s_prmry_reset_out_n] 459 | connect_bd_net -net axi_ethernet_0_dma_s2mm_introut [get_bd_pins axi_ethernet_0_dma/s2mm_introut] [get_bd_pins xlconcat_0/In3] 460 | connect_bd_net -net axi_ethernet_0_dma_s2mm_prmry_reset_out_n [get_bd_pins axi_ethernet_0/axi_rxd_arstn] [get_bd_pins axi_ethernet_0_dma/s2mm_prmry_reset_out_n] 461 | connect_bd_net -net axi_ethernet_0_dma_s2mm_sts_reset_out_n [get_bd_pins axi_ethernet_0/axi_rxs_arstn] [get_bd_pins axi_ethernet_0_dma/s2mm_sts_reset_out_n] 462 | connect_bd_net -net axi_ethernet_0_interrupt [get_bd_pins axi_ethernet_0/interrupt] [get_bd_pins xlconcat_0/In2] 463 | connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins xlconcat_0/In5] 464 | connect_bd_net -net axi_quad_spi_0_ip2intc_irpt [get_bd_pins axi_quad_spi_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In1] 465 | connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_pins axi_uart16550_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In0] 466 | connect_bd_net -net clk_wiz_0_clk_50M [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins clk_wiz_0/clk_50M] [get_bd_pins rocketchip_wrapper_0/clk] [get_bd_pins rst_clk_wiz_0_100M/slowest_sync_clk] 467 | connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins axi_ethernet_0/axis_clk] [get_bd_pins axi_ethernet_0/s_axi_lite_clk] [get_bd_pins axi_ethernet_0_dma/m_axi_mm2s_aclk] [get_bd_pins axi_ethernet_0_dma/m_axi_s2mm_aclk] [get_bd_pins axi_ethernet_0_dma/m_axi_sg_aclk] [get_bd_pins axi_ethernet_0_dma/s_axi_lite_aclk] [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/S02_ACLK] [get_bd_pins axi_interconnect_0/S03_ACLK] [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/M01_ACLK] [get_bd_pins axi_mem_intercon/M02_ACLK] [get_bd_pins axi_mem_intercon/M03_ACLK] [get_bd_pins axi_mem_intercon/M04_ACLK] [get_bd_pins axi_mem_intercon/M05_ACLK] [get_bd_pins axi_quad_spi_0/s_axi4_aclk] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_100M] [get_bd_pins hbm_0/APB_0_PCLK] [get_bd_pins hbm_0/AXI_00_ACLK] [get_bd_pins hbm_0/HBM_REF_CLK_0] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins vio_0/clk] 468 | connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_clk_wiz_0_100M/dcm_locked] 469 | connect_bd_net -net dummy_port_in_1 [get_bd_ports dummy_port_in] [get_bd_pins axi_ethernet_0/dummy_port_in] 470 | connect_bd_net -net jtag_TCK_0_1 [get_bd_ports jtag_TCK] [get_bd_pins rocketchip_wrapper_0/jtag_TCK] 471 | connect_bd_net -net jtag_TDI_0_1 [get_bd_ports jtag_TDI] [get_bd_pins rocketchip_wrapper_0/jtag_TDI] 472 | connect_bd_net -net jtag_TMS_0_1 [get_bd_ports jtag_TMS] [get_bd_pins rocketchip_wrapper_0/jtag_TMS] 473 | connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins rst_clk_wiz_0_100M/ext_reset_in] 474 | connect_bd_net -net rocketchip_wrapper_0_jtag_TDO [get_bd_ports jtag_TDO] [get_bd_pins rocketchip_wrapper_0/jtag_TDO] 475 | connect_bd_net -net rst_clk_wiz_0_100M_mb_reset [get_bd_pins rocketchip_wrapper_0/reset] [get_bd_pins rst_clk_wiz_0_100M/mb_reset] 476 | connect_bd_net -net rst_clk_wiz_0_100M_peripheral_aresetn [get_bd_pins axi_ethernet_0/s_axi_lite_resetn] [get_bd_pins axi_ethernet_0_dma/axi_resetn] [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/S02_ARESETN] [get_bd_pins axi_interconnect_0/S03_ARESETN] [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/M01_ARESETN] [get_bd_pins axi_mem_intercon/M02_ARESETN] [get_bd_pins axi_mem_intercon/M03_ARESETN] [get_bd_pins axi_mem_intercon/M04_ARESETN] [get_bd_pins axi_mem_intercon/M05_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_quad_spi_0/s_axi4_aresetn] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins hbm_0/APB_0_PRESET_N] [get_bd_pins hbm_0/AXI_00_ARESET_N] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins rst_clk_wiz_0_100M/peripheral_aresetn] 477 | connect_bd_net -net vio_0_probe_out0 [get_bd_pins rst_clk_wiz_0_100M/aux_reset_in] [get_bd_pins vio_0/probe_out0] 478 | connect_bd_net -net xlconcat_0_dout [get_bd_pins rocketchip_wrapper_0/interrupts] [get_bd_pins xlconcat_0/dout] 479 | connect_bd_net -net xlconstant_0_dout [get_bd_pins clk_wiz_0/reset] [get_bd_pins xlconstant_0/dout] 480 | 481 | # Create address segments 482 | assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces axi_ethernet_0_dma/Data_SG] [get_bd_addr_segs rocketchip_wrapper_0/S_AXI/reg0] -force 483 | assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces axi_ethernet_0_dma/Data_MM2S] [get_bd_addr_segs rocketchip_wrapper_0/S_AXI/reg0] -force 484 | assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces axi_ethernet_0_dma/Data_S2MM] [get_bd_addr_segs rocketchip_wrapper_0/S_AXI/reg0] -force 485 | assign_bd_address -offset 0x00000000 -range 0x00010000000000000000 -target_address_space [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs rocketchip_wrapper_0/S_AXI/reg0] -force 486 | assign_bd_address -offset 0x60400000 -range 0x00040000 -target_address_space [get_bd_addr_spaces rocketchip_wrapper_0/M_AXI_MMIO] [get_bd_addr_segs axi_ethernet_0/s_axi/Reg0] -force 487 | assign_bd_address -offset 0x60300000 -range 0x00010000 -target_address_space [get_bd_addr_spaces rocketchip_wrapper_0/M_AXI_MMIO] [get_bd_addr_segs axi_ethernet_0_dma/S_AXI_LITE/Reg] -force 488 | assign_bd_address -offset 0x60500000 -range 0x00010000 -target_address_space [get_bd_addr_spaces rocketchip_wrapper_0/M_AXI_MMIO] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] -force 489 | assign_bd_address -offset 0x60100000 -range 0x00010000 -target_address_space [get_bd_addr_spaces rocketchip_wrapper_0/M_AXI_MMIO] [get_bd_addr_segs axi_quad_spi_0/aximm/MEM0] -force 490 | assign_bd_address -offset 0x60200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces rocketchip_wrapper_0/M_AXI_MMIO] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force 491 | assign_bd_address -offset 0x80000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces rocketchip_wrapper_0/M_AXI] [get_bd_addr_segs hbm_0/SAXI_00/HBM_MEM08] -force 492 | assign_bd_address -offset 0x90000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces rocketchip_wrapper_0/M_AXI] [get_bd_addr_segs hbm_0/SAXI_00/HBM_MEM09] -force 493 | 494 | 495 | # Restore current instance 496 | current_bd_instance $oldCurInst 497 | 498 | validate_bd_design 499 | save_bd_design 500 | } 501 | # End of create_root_design() 502 | 503 | 504 | ################################################################## 505 | # MAIN FLOW 506 | ################################################################## 507 | 508 | create_root_design "" 509 | 510 | 511 | -------------------------------------------------------------------------------- /src/constraints/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/rocket-chip-vcu128/7aa67a4046fdebdc74d05a61fe0a4eec4dd2cf8f/src/constraints/.keep -------------------------------------------------------------------------------- /src/constraints/debug.xdc: -------------------------------------------------------------------------------- 1 | # debug 2 | 3 | # create_debug_core u_ila_0 ila 4 | # set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 5 | # set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 6 | # set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 7 | # set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] 8 | # set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 9 | # set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 10 | # set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 11 | # set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 12 | # set_property port_width 1 [get_debug_ports u_ila_0/clk] 13 | # connect_debug_port u_ila_0/clk [get_nets [list system_i/clk_wiz_0/inst/clk_50M]] 14 | # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 15 | # set_property port_width 64 [get_debug_ports u_ila_0/probe0] 16 | # connect_debug_port u_ila_0/probe0 [get_nets [list {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[0]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[1]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[2]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[3]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[4]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[5]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[6]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[7]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[8]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[9]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[10]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[11]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[12]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[13]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[14]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[15]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[16]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[17]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[18]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[19]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[20]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[21]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[22]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[23]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[24]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[25]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[26]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[27]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[28]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[29]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[30]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[31]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[32]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[33]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[34]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[35]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[36]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[37]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[38]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[39]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[40]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[41]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[42]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[43]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[44]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[45]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[46]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[47]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[48]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[49]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[50]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[51]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[52]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[53]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[54]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[55]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[56]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[57]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[58]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[59]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[60]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[61]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[62]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_pc[63]}]] 17 | # create_debug_port u_ila_0 probe 18 | # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 19 | # set_property port_width 32 [get_debug_ports u_ila_0/probe1] 20 | # connect_debug_port u_ila_0/probe1 [get_nets [list {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[0]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[1]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[2]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[3]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[4]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[5]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[6]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[7]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[8]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[9]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[10]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[11]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[12]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[13]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[14]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[15]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[16]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[17]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[18]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[19]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[20]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[21]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[22]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[23]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[24]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[25]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[26]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[27]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[28]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[29]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[30]} {system_i/rocketchip_wrapper_0/inst/top/target/tile_prci_domain/tile_reset_domain/tile/core/coreMonitorBundle_inst[31]}]] 21 | # create_debug_port u_ila_0 probe 22 | # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 23 | # set_property port_width 1 [get_debug_ports u_ila_0/probe2] 24 | # connect_debug_port u_ila_0/probe2 [get_nets [list jtag_TCK_IBUF]] 25 | # create_debug_port u_ila_0 probe 26 | # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 27 | # set_property port_width 1 [get_debug_ports u_ila_0/probe3] 28 | # connect_debug_port u_ila_0/probe3 [get_nets [list jtag_TDI_IBUF]] 29 | # create_debug_port u_ila_0 probe 30 | # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 31 | # set_property port_width 1 [get_debug_ports u_ila_0/probe4] 32 | # connect_debug_port u_ila_0/probe4 [get_nets [list jtag_TDO_OBUF]] 33 | # create_debug_port u_ila_0 probe 34 | # set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 35 | # set_property port_width 1 [get_debug_ports u_ila_0/probe5] 36 | # connect_debug_port u_ila_0/probe5 [get_nets [list jtag_TMS_IBUF]] 37 | # set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] 38 | # set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] 39 | # set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] 40 | # connect_debug_port dbg_hub/clk [get_nets clk] -------------------------------------------------------------------------------- /src/constraints/spi.xdc: -------------------------------------------------------------------------------- 1 | # below is taken from axi_quad_spi xdc 2 | 3 | ## IOB constraints ###### 4 | 5 | ##################################################################################################### 6 | # The following section list the board specific constraints (with/without STARTUPE2/E3 primitive) # 7 | # as per guidance given in product guide. # 8 | # User should uncomment, update constraints based on board delays and use # 9 | ##################################################################################################### 10 | 11 | #### All the delay numbers have to be provided by the user 12 | 13 | #### Following are the SPI device parameters 14 | #### Max Tco 15 | set tco_max 7 16 | #### Min Tco 17 | set tco_min 1 18 | #### Setup time requirement 19 | set tsu 2 20 | #### Hold time requirement 21 | set th 3 22 | ##################################################################################################### 23 | # STARTUPE3 primitive included inside IP for US+ # 24 | ##################################################################################################### 25 | set tdata_trace_delay_max 0.25 26 | set tdata_trace_delay_min 0.25 27 | set tclk_trace_delay_max 0.2 28 | set tclk_trace_delay_min 0.2 29 | create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] [get_pins -hierarchical */CCLK] -edges {3 5 7} 30 | set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_pins -hierarchical *STARTUP*/DATA_IN[*]] -clock_fall; 31 | set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_pins -hierarchical *STARTUP*/DATA_IN[*]] -clock_fall; 32 | set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 33 | set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 34 | set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_pins -hierarchical *STARTUP*/DATA_OUT[*]]; 35 | set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min -$th - $tclk_trace_delay_max] [get_pins -hierarchical *STARTUP*/DATA_OUT[*]]; 36 | set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 37 | set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck -------------------------------------------------------------------------------- /src/constraints/system.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict {PACKAGE_PIN BM29 IOSTANDARD LVCMOS12} [get_ports reset] 2 | 3 | # easy to confuse rxd/txd here 4 | # uart0_txd 5 | set_property -dict {PACKAGE_PIN BP26 IOSTANDARD LVCMOS18} [get_ports jtag_TCK] 6 | # uart0_rxd 7 | set_property -dict {PACKAGE_PIN BN26 IOSTANDARD LVCMOS18} [get_ports jtag_TDI] 8 | # uart0_rts 9 | set_property -dict {PACKAGE_PIN BP22 IOSTANDARD LVCMOS18} [get_ports jtag_TDO] 10 | # uart0_cts 11 | set_property -dict {PACKAGE_PIN BP23 IOSTANDARD LVCMOS18} [get_ports jtag_TMS] 12 | 13 | # assume 10MHz jtag 14 | # ref https://github.com/pulp-platform/pulp/blob/master/fpga/pulp-vcu118/constraints/vcu118.xdc 15 | # intel jtag timing: https://www.intel.com/content/www/us/en/docs/programmable/683301/current/jtag-configuration-timing.html 16 | # ft4232 timing: https://ftdichip.com/wp-content/uploads/2020/08/DS_FT4232H.pdf 17 | create_clock -period 100.000 -name jtag_TCK [get_ports jtag_TCK] 18 | set_input_jitter jtag_TCK 1.000 19 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF_inst/O] 20 | set_input_delay -clock jtag_TCK -clock_fall 5.000 [get_ports jtag_TDI] 21 | set_input_delay -clock jtag_TCK -clock_fall 5.000 [get_ports jtag_TMS] 22 | set_output_delay -clock jtag_TCK 5.000 [get_ports jtag_TDO] 23 | set_max_delay -to [get_ports jtag_TDO] 20.000 24 | set_max_delay -from [get_ports jtag_TMS] 20.000 25 | set_max_delay -from [get_ports jtag_TDI] 20.000 26 | set_clock_groups -asynchronous -group [get_clocks jtag_TCK] -group [get_clocks -of_objects [get_pins system_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1]] 27 | set_property ASYNC_REG TRUE [get_cells -hier -regexp "system_i/rocketchip_wrapper_0/.*/cdc_reg_reg.*"] 28 | 29 | set_property MARK_DEBUG true [get_nets jtag_TDI] 30 | set_property MARK_DEBUG true [get_nets jtag_TDO] 31 | set_property MARK_DEBUG true [get_nets jtag_TCK] 32 | set_property MARK_DEBUG true [get_nets jtag_TMS] -------------------------------------------------------------------------------- /src/hdl/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/rocket-chip-vcu128/7aa67a4046fdebdc74d05a61fe0a4eec4dd2cf8f/src/hdl/.keep -------------------------------------------------------------------------------- /src/hdl/EICG_wrapper.v: -------------------------------------------------------------------------------- 1 | /* verilator lint_off UNOPTFLAT */ 2 | 3 | module EICG_wrapper( 4 | output out, 5 | input en, 6 | input test_en, 7 | input in 8 | ); 9 | 10 | reg en_latched /*verilator clock_enable*/; 11 | 12 | always @(*) begin 13 | if (!in) begin 14 | en_latched = en || test_en; 15 | end 16 | end 17 | 18 | assign out = en_latched && in; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /src/hdl/plusarg_reader.v: -------------------------------------------------------------------------------- 1 | // See LICENSE.SiFive for license details. 2 | 3 | //VCS coverage exclude_file 4 | 5 | // No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment), 6 | // but Incisive demands them. These default values should never be used. 7 | module plusarg_reader #(parameter FORMAT="borked=%d", DEFAULT=0, WIDTH=1) ( 8 | output [WIDTH-1:0] out 9 | ); 10 | 11 | `ifdef SYNTHESIS 12 | assign out = DEFAULT; 13 | `else 14 | reg [WIDTH-1:0] myplus; 15 | assign out = myplus; 16 | 17 | initial begin 18 | if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT; 19 | end 20 | `endif 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /src/hdl/rocketchip_wrapper.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////// 2 | // Company: 3 | // Engineer: 4 | // 5 | // Create Date: 11/04/2019 05:46:57 PM 6 | // Design Name: 7 | // Module Name: rocketchip_wrapper 8 | // Project Name: 9 | // Target Devices: 10 | // Tool Versions: 11 | // Description: 12 | // 13 | // Dependencies: 14 | // 15 | // Revision: 16 | // Revision 0.01 - File Created 17 | // Additional Comments: 18 | // 19 | ////////////////////////////////////////////////////////////////////////////////// 20 | 21 | 22 | module rocketchip_wrapper( 23 | clk, 24 | reset, 25 | interrupts, 26 | 27 | // MEM 28 | M_AXI_awready, 29 | M_AXI_awvalid, 30 | M_AXI_awid, 31 | M_AXI_awaddr, 32 | M_AXI_awlen, 33 | M_AXI_awsize, 34 | M_AXI_awburst, 35 | M_AXI_awlock, 36 | M_AXI_awcache, 37 | M_AXI_awprot, 38 | M_AXI_awqos, 39 | 40 | M_AXI_wready, 41 | M_AXI_wvalid, 42 | M_AXI_wdata, 43 | M_AXI_wstrb, 44 | M_AXI_wlast, 45 | 46 | M_AXI_bready, 47 | M_AXI_bvalid, 48 | M_AXI_bid, 49 | M_AXI_bresp, 50 | 51 | M_AXI_arready, 52 | M_AXI_arvalid, 53 | M_AXI_arid, 54 | M_AXI_araddr, 55 | M_AXI_arlen, 56 | M_AXI_arsize, 57 | M_AXI_arburst, 58 | M_AXI_arlock, 59 | M_AXI_arcache, 60 | M_AXI_arprot, 61 | M_AXI_arqos, 62 | 63 | M_AXI_rready, 64 | M_AXI_rvalid, 65 | M_AXI_rid, 66 | M_AXI_rdata, 67 | M_AXI_rresp, 68 | M_AXI_rlast, 69 | 70 | // MMIO 71 | M_AXI_MMIO_awready, 72 | M_AXI_MMIO_awvalid, 73 | M_AXI_MMIO_awid, 74 | M_AXI_MMIO_awaddr, 75 | M_AXI_MMIO_awlen, 76 | M_AXI_MMIO_awsize, 77 | M_AXI_MMIO_awburst, 78 | M_AXI_MMIO_awlock, 79 | M_AXI_MMIO_awcache, 80 | M_AXI_MMIO_awprot, 81 | M_AXI_MMIO_awqos, 82 | 83 | M_AXI_MMIO_wready, 84 | M_AXI_MMIO_wvalid, 85 | M_AXI_MMIO_wdata, 86 | M_AXI_MMIO_wstrb, 87 | M_AXI_MMIO_wlast, 88 | 89 | M_AXI_MMIO_bready, 90 | M_AXI_MMIO_bvalid, 91 | M_AXI_MMIO_bid, 92 | M_AXI_MMIO_bresp, 93 | 94 | M_AXI_MMIO_arready, 95 | M_AXI_MMIO_arvalid, 96 | M_AXI_MMIO_arid, 97 | M_AXI_MMIO_araddr, 98 | M_AXI_MMIO_arlen, 99 | M_AXI_MMIO_arsize, 100 | M_AXI_MMIO_arburst, 101 | M_AXI_MMIO_arlock, 102 | M_AXI_MMIO_arcache, 103 | M_AXI_MMIO_arprot, 104 | M_AXI_MMIO_arqos, 105 | 106 | M_AXI_MMIO_rready, 107 | M_AXI_MMIO_rvalid, 108 | M_AXI_MMIO_rid, 109 | M_AXI_MMIO_rdata, 110 | M_AXI_MMIO_rresp, 111 | M_AXI_MMIO_rlast, 112 | 113 | // slave port for dma 114 | S_AXI_awready, 115 | S_AXI_awvalid, 116 | S_AXI_awid, 117 | S_AXI_awaddr, 118 | S_AXI_awlen, 119 | S_AXI_awsize, 120 | S_AXI_awburst, 121 | S_AXI_awlock, 122 | S_AXI_awcache, 123 | S_AXI_awprot, 124 | S_AXI_awqos, 125 | 126 | S_AXI_wready, 127 | S_AXI_wvalid, 128 | S_AXI_wdata, 129 | S_AXI_wstrb, 130 | S_AXI_wlast, 131 | 132 | S_AXI_bready, 133 | S_AXI_bvalid, 134 | S_AXI_bid, 135 | S_AXI_bresp, 136 | 137 | S_AXI_arready, 138 | S_AXI_arvalid, 139 | S_AXI_arid, 140 | S_AXI_araddr, 141 | S_AXI_arlen, 142 | S_AXI_arsize, 143 | S_AXI_arburst, 144 | S_AXI_arlock, 145 | S_AXI_arcache, 146 | S_AXI_arprot, 147 | S_AXI_arqos, 148 | 149 | S_AXI_rready, 150 | S_AXI_rvalid, 151 | S_AXI_rid, 152 | S_AXI_rdata, 153 | S_AXI_rresp, 154 | S_AXI_rlast, 155 | 156 | // JTAG 157 | jtag_TCK, 158 | jtag_TMS, 159 | jtag_TDI, 160 | jtag_TDO 161 | ); 162 | 163 | input clk; 164 | input reset; 165 | input [5:0] interrupts; 166 | 167 | // MEM 168 | input M_AXI_awready; 169 | output M_AXI_awvalid; 170 | output [4:0] M_AXI_awid; 171 | output [63:0] M_AXI_awaddr; 172 | output [7:0] M_AXI_awlen; 173 | output [2:0] M_AXI_awsize; 174 | output [1:0] M_AXI_awburst; 175 | output M_AXI_awlock; 176 | output [3:0] M_AXI_awcache; 177 | output [2:0] M_AXI_awprot; 178 | output [3:0] M_AXI_awqos; 179 | 180 | input M_AXI_wready; 181 | output M_AXI_wvalid; 182 | output [63:0] M_AXI_wdata; 183 | output [7:0] M_AXI_wstrb; 184 | output M_AXI_wlast; 185 | 186 | output M_AXI_bready; 187 | input M_AXI_bvalid; 188 | input [4:0] M_AXI_bid; 189 | input [1:0] M_AXI_bresp; 190 | 191 | input M_AXI_arready; 192 | output M_AXI_arvalid; 193 | output [4:0] M_AXI_arid; 194 | output [63:0] M_AXI_araddr; 195 | output [7:0] M_AXI_arlen; 196 | output [2:0] M_AXI_arsize; 197 | output [1:0] M_AXI_arburst; 198 | output M_AXI_arlock; 199 | output [3:0] M_AXI_arcache; 200 | output [2:0] M_AXI_arprot; 201 | output [3:0] M_AXI_arqos; 202 | 203 | output M_AXI_rready; 204 | input M_AXI_rvalid; 205 | input [4:0] M_AXI_rid; 206 | input [63:0] M_AXI_rdata; 207 | input [1:0] M_AXI_rresp; 208 | input M_AXI_rlast; 209 | 210 | // MMIO 211 | input M_AXI_MMIO_awready; 212 | output M_AXI_MMIO_awvalid; 213 | output [4:0] M_AXI_MMIO_awid; 214 | output [63:0] M_AXI_MMIO_awaddr; 215 | output [7:0] M_AXI_MMIO_awlen; 216 | output [2:0] M_AXI_MMIO_awsize; 217 | output [1:0] M_AXI_MMIO_awburst; 218 | output M_AXI_MMIO_awlock; 219 | output [3:0] M_AXI_MMIO_awcache; 220 | output [2:0] M_AXI_MMIO_awprot; 221 | output [3:0] M_AXI_MMIO_awqos; 222 | 223 | input M_AXI_MMIO_wready; 224 | output M_AXI_MMIO_wvalid; 225 | output [63:0] M_AXI_MMIO_wdata; 226 | output [7:0] M_AXI_MMIO_wstrb; 227 | output M_AXI_MMIO_wlast; 228 | 229 | output M_AXI_MMIO_bready; 230 | input M_AXI_MMIO_bvalid; 231 | input [4:0] M_AXI_MMIO_bid; 232 | input [1:0] M_AXI_MMIO_bresp; 233 | 234 | input M_AXI_MMIO_arready; 235 | output M_AXI_MMIO_arvalid; 236 | output [4:0] M_AXI_MMIO_arid; 237 | output [63:0] M_AXI_MMIO_araddr; 238 | output [7:0] M_AXI_MMIO_arlen; 239 | output [2:0] M_AXI_MMIO_arsize; 240 | output [1:0] M_AXI_MMIO_arburst; 241 | output M_AXI_MMIO_arlock; 242 | output [3:0] M_AXI_MMIO_arcache; 243 | output [2:0] M_AXI_MMIO_arprot; 244 | output [3:0] M_AXI_MMIO_arqos; 245 | 246 | output M_AXI_MMIO_rready; 247 | input M_AXI_MMIO_rvalid; 248 | input [4:0] M_AXI_MMIO_rid; 249 | input [63:0] M_AXI_MMIO_rdata; 250 | input [1:0] M_AXI_MMIO_rresp; 251 | input M_AXI_MMIO_rlast; 252 | 253 | // MMIO 254 | output S_AXI_awready; 255 | input S_AXI_awvalid; 256 | input [7:0] S_AXI_awid; 257 | input [63:0] S_AXI_awaddr; 258 | input [7:0] S_AXI_awlen; 259 | input [2:0] S_AXI_awsize; 260 | input [1:0] S_AXI_awburst; 261 | input S_AXI_awlock; 262 | input [3:0] S_AXI_awcache; 263 | input [2:0] S_AXI_awprot; 264 | input [3:0] S_AXI_awqos; 265 | 266 | output S_AXI_wready; 267 | input S_AXI_wvalid; 268 | input [63:0] S_AXI_wdata; 269 | input [7:0] S_AXI_wstrb; 270 | input S_AXI_wlast; 271 | 272 | input S_AXI_bready; 273 | output S_AXI_bvalid; 274 | output [7:0] S_AXI_bid; 275 | output [1:0] S_AXI_bresp; 276 | 277 | output S_AXI_arready; 278 | input S_AXI_arvalid; 279 | input [7:0] S_AXI_arid; 280 | input [63:0] S_AXI_araddr; 281 | input [7:0] S_AXI_arlen; 282 | input [2:0] S_AXI_arsize; 283 | input [1:0] S_AXI_arburst; 284 | input S_AXI_arlock; 285 | input [3:0] S_AXI_arcache; 286 | input [2:0] S_AXI_arprot; 287 | input [3:0] S_AXI_arqos; 288 | 289 | input S_AXI_rready; 290 | output S_AXI_rvalid; 291 | output [7:0] S_AXI_rid; 292 | output [63:0] S_AXI_rdata; 293 | output [1:0] S_AXI_rresp; 294 | output S_AXI_rlast; 295 | 296 | assign M_AXI_araddr[63:32] = 0; 297 | assign M_AXI_awaddr[63:32] = 0; 298 | assign M_AXI_MMIO_araddr[63:31] = 0; 299 | assign M_AXI_MMIO_awaddr[63:31] = 0; 300 | 301 | // jtag 302 | input jtag_TCK; 303 | input jtag_TMS; 304 | input jtag_TDI; 305 | output jtag_TDO; 306 | 307 | RocketChip top ( 308 | .clock(clk), 309 | .reset(reset), 310 | 311 | .io_mem_axi4_ar_valid (M_AXI_arvalid), 312 | .io_mem_axi4_ar_ready (M_AXI_arready), 313 | .io_mem_axi4_ar_bits_addr (M_AXI_araddr[31:0]), 314 | .io_mem_axi4_ar_bits_id (M_AXI_arid), 315 | .io_mem_axi4_ar_bits_size (M_AXI_arsize), 316 | .io_mem_axi4_ar_bits_len (M_AXI_arlen), 317 | .io_mem_axi4_ar_bits_burst (M_AXI_arburst), 318 | .io_mem_axi4_ar_bits_cache (M_AXI_arcache), 319 | .io_mem_axi4_ar_bits_lock (M_AXI_arlock), 320 | .io_mem_axi4_ar_bits_prot (M_AXI_arprot), 321 | .io_mem_axi4_ar_bits_qos (M_AXI_arqos), 322 | .io_mem_axi4_aw_valid (M_AXI_awvalid), 323 | .io_mem_axi4_aw_ready (M_AXI_awready), 324 | .io_mem_axi4_aw_bits_addr (M_AXI_awaddr[31:0]), 325 | .io_mem_axi4_aw_bits_id (M_AXI_awid), 326 | .io_mem_axi4_aw_bits_size (M_AXI_awsize), 327 | .io_mem_axi4_aw_bits_len (M_AXI_awlen), 328 | .io_mem_axi4_aw_bits_burst (M_AXI_awburst), 329 | .io_mem_axi4_aw_bits_cache (M_AXI_awcache), 330 | .io_mem_axi4_aw_bits_lock (M_AXI_awlock), 331 | .io_mem_axi4_aw_bits_prot (M_AXI_awprot), 332 | .io_mem_axi4_aw_bits_qos (M_AXI_awqos), 333 | .io_mem_axi4_w_valid (M_AXI_wvalid), 334 | .io_mem_axi4_w_ready (M_AXI_wready), 335 | .io_mem_axi4_w_bits_strb (M_AXI_wstrb), 336 | .io_mem_axi4_w_bits_data (M_AXI_wdata), 337 | .io_mem_axi4_w_bits_last (M_AXI_wlast), 338 | .io_mem_axi4_b_valid (M_AXI_bvalid), 339 | .io_mem_axi4_b_ready (M_AXI_bready), 340 | .io_mem_axi4_b_bits_resp (M_AXI_bresp), 341 | .io_mem_axi4_b_bits_id (M_AXI_bid), 342 | .io_mem_axi4_r_valid (M_AXI_rvalid), 343 | .io_mem_axi4_r_ready (M_AXI_rready), 344 | .io_mem_axi4_r_bits_resp (M_AXI_rresp), 345 | .io_mem_axi4_r_bits_id (M_AXI_rid), 346 | .io_mem_axi4_r_bits_data (M_AXI_rdata), 347 | .io_mem_axi4_r_bits_last (M_AXI_rlast), 348 | 349 | .io_mmio_axi4_ar_valid (M_AXI_MMIO_arvalid), 350 | .io_mmio_axi4_ar_ready (M_AXI_MMIO_arready), 351 | .io_mmio_axi4_ar_bits_addr (M_AXI_MMIO_araddr[30:0]), 352 | .io_mmio_axi4_ar_bits_id (M_AXI_MMIO_arid), 353 | .io_mmio_axi4_ar_bits_size (M_AXI_MMIO_arsize), 354 | .io_mmio_axi4_ar_bits_len (M_AXI_MMIO_arlen), 355 | .io_mmio_axi4_ar_bits_burst (M_AXI_MMIO_arburst), 356 | .io_mmio_axi4_ar_bits_cache (M_AXI_MMIO_arcache), 357 | .io_mmio_axi4_ar_bits_lock (M_AXI_MMIO_arlock), 358 | .io_mmio_axi4_ar_bits_prot (M_AXI_MMIO_arprot), 359 | .io_mmio_axi4_ar_bits_qos (M_AXI_MMIO_arqos), 360 | .io_mmio_axi4_aw_valid (M_AXI_MMIO_awvalid), 361 | .io_mmio_axi4_aw_ready (M_AXI_MMIO_awready), 362 | .io_mmio_axi4_aw_bits_addr (M_AXI_MMIO_awaddr[30:0]), 363 | .io_mmio_axi4_aw_bits_id (M_AXI_MMIO_awid), 364 | .io_mmio_axi4_aw_bits_size (M_AXI_MMIO_awsize), 365 | .io_mmio_axi4_aw_bits_len (M_AXI_MMIO_awlen), 366 | .io_mmio_axi4_aw_bits_burst (M_AXI_MMIO_awburst), 367 | .io_mmio_axi4_aw_bits_cache (M_AXI_MMIO_awcache), 368 | .io_mmio_axi4_aw_bits_lock (M_AXI_MMIO_awlock), 369 | .io_mmio_axi4_aw_bits_prot (M_AXI_MMIO_awprot), 370 | .io_mmio_axi4_aw_bits_qos (M_AXI_MMIO_awqos), 371 | .io_mmio_axi4_w_valid (M_AXI_MMIO_wvalid), 372 | .io_mmio_axi4_w_ready (M_AXI_MMIO_wready), 373 | .io_mmio_axi4_w_bits_strb (M_AXI_MMIO_wstrb), 374 | .io_mmio_axi4_w_bits_data (M_AXI_MMIO_wdata), 375 | .io_mmio_axi4_w_bits_last (M_AXI_MMIO_wlast), 376 | .io_mmio_axi4_b_valid (M_AXI_MMIO_bvalid), 377 | .io_mmio_axi4_b_ready (M_AXI_MMIO_bready), 378 | .io_mmio_axi4_b_bits_resp (M_AXI_MMIO_bresp), 379 | .io_mmio_axi4_b_bits_id (M_AXI_MMIO_bid), 380 | .io_mmio_axi4_r_valid (M_AXI_MMIO_rvalid), 381 | .io_mmio_axi4_r_ready (M_AXI_MMIO_rready), 382 | .io_mmio_axi4_r_bits_resp (M_AXI_MMIO_rresp), 383 | .io_mmio_axi4_r_bits_id (M_AXI_MMIO_rid), 384 | .io_mmio_axi4_r_bits_data (M_AXI_MMIO_rdata), 385 | .io_mmio_axi4_r_bits_last (M_AXI_MMIO_rlast), 386 | 387 | .io_slave_axi4_ar_valid (S_AXI_arvalid), 388 | .io_slave_axi4_ar_ready (S_AXI_arready), 389 | .io_slave_axi4_ar_bits_addr (S_AXI_araddr), 390 | .io_slave_axi4_ar_bits_id (S_AXI_arid), 391 | .io_slave_axi4_ar_bits_size (S_AXI_arsize), 392 | .io_slave_axi4_ar_bits_len (S_AXI_arlen), 393 | .io_slave_axi4_ar_bits_burst (S_AXI_arburst), 394 | .io_slave_axi4_ar_bits_cache (S_AXI_arcache), 395 | .io_slave_axi4_ar_bits_lock (S_AXI_arlock), 396 | .io_slave_axi4_ar_bits_prot (S_AXI_arprot), 397 | .io_slave_axi4_ar_bits_qos (S_AXI_arqos), 398 | .io_slave_axi4_aw_valid (S_AXI_awvalid), 399 | .io_slave_axi4_aw_ready (S_AXI_awready), 400 | .io_slave_axi4_aw_bits_addr (S_AXI_awaddr), 401 | .io_slave_axi4_aw_bits_id (S_AXI_awid), 402 | .io_slave_axi4_aw_bits_size (S_AXI_awsize), 403 | .io_slave_axi4_aw_bits_len (S_AXI_awlen), 404 | .io_slave_axi4_aw_bits_burst (S_AXI_awburst), 405 | .io_slave_axi4_aw_bits_cache (S_AXI_awcache), 406 | .io_slave_axi4_aw_bits_lock (S_AXI_awlock), 407 | .io_slave_axi4_aw_bits_prot (S_AXI_awprot), 408 | .io_slave_axi4_aw_bits_qos (S_AXI_awqos), 409 | .io_slave_axi4_w_valid (S_AXI_wvalid), 410 | .io_slave_axi4_w_ready (S_AXI_wready), 411 | .io_slave_axi4_w_bits_strb (S_AXI_wstrb), 412 | .io_slave_axi4_w_bits_data (S_AXI_wdata), 413 | .io_slave_axi4_w_bits_last (S_AXI_wlast), 414 | .io_slave_axi4_b_valid (S_AXI_bvalid), 415 | .io_slave_axi4_b_ready (S_AXI_bready), 416 | .io_slave_axi4_b_bits_resp (S_AXI_bresp), 417 | .io_slave_axi4_b_bits_id (S_AXI_bid), 418 | .io_slave_axi4_r_valid (S_AXI_rvalid), 419 | .io_slave_axi4_r_ready (S_AXI_rready), 420 | .io_slave_axi4_r_bits_resp (S_AXI_rresp), 421 | .io_slave_axi4_r_bits_id (S_AXI_rid), 422 | .io_slave_axi4_r_bits_data (S_AXI_rdata), 423 | .io_slave_axi4_r_bits_last (S_AXI_rlast), 424 | 425 | .io_interrupts(interrupts), 426 | 427 | .io_jtag_TCK(jtag_TCK), 428 | .io_jtag_TMS(jtag_TMS), 429 | .io_jtag_TDI(jtag_TDI), 430 | .io_jtag_TDO_data(jtag_TDO) 431 | ); 432 | endmodule 433 | -------------------------------------------------------------------------------- /src/hdl/vcu128.RocketConfig.sv: -------------------------------------------------------------------------------- 1 | ../../build/vcu128.RocketConfig.sv -------------------------------------------------------------------------------- /src/ip/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/rocket-chip-vcu128/7aa67a4046fdebdc74d05a61fe0a4eec4dd2cf8f/src/ip/.keep -------------------------------------------------------------------------------- /src/main/scala/BscanJTAG.scala: -------------------------------------------------------------------------------- 1 | package vcu128 2 | 3 | // Taken from https://github.com/KireinaHoro/rocket-zcu102/blob/master/src/main/scala/BscanJTAG.scala 4 | 5 | import chisel3._ 6 | import chisel3.util._ 7 | import chisel3.experimental.ExtModule 8 | 9 | class BUFGCE extends ExtModule { 10 | val O = IO(Output(Bool())) 11 | val CE = IO(Input(Bool())) 12 | val I = IO(Input(Bool())) 13 | } 14 | 15 | class BSCANE2 extends ExtModule(Map("JTAG_CHAIN" -> 4)) { 16 | val TDO = IO(Input(Bool())) 17 | val CAPTURE = IO(Output(Bool())) 18 | val DRCK = IO(Output(Bool())) 19 | val RESET = IO(Output(Bool())) 20 | val RUNTEST = IO(Output(Bool())) 21 | val SEL = IO(Output(Bool())) 22 | val SHIFT = IO(Output(Bool())) 23 | val TCK = IO(Output(Bool())) 24 | val TDI = IO(Output(Bool())) 25 | val TMS = IO(Output(Bool())) 26 | val UPDATE = IO(Output(Bool())) 27 | } 28 | 29 | class BscanJTAG extends Module { 30 | val tck: Clock = IO(Output(Clock())) 31 | val tms: Bool = IO(Output(Bool())) 32 | val tdi: Bool = IO(Output(Bool())) 33 | val tdo: Bool = IO(Input(Bool())) 34 | val tdoEnable: Bool = IO(Input(Bool())) 35 | 36 | val bscane2 = Module(new BSCANE2) 37 | tdi := bscane2.TDI 38 | bscane2.TDO := Mux(tdoEnable, tdo, true.B) 39 | val bufgce = Module(new BUFGCE) 40 | bufgce.I := bscane2.TCK 41 | bufgce.CE := bscane2.SEL 42 | tck := bufgce.O.asClock 43 | 44 | val posClock: Clock = bscane2.TCK.asClock 45 | val negClock: Clock = (!bscane2.TCK).asClock 46 | 47 | /** This two wire will cross two clock domain, generated at [[posClock]], used 48 | * in [[negClock]] 49 | */ 50 | val tdiRegisterWire = Wire(Bool()) 51 | val shiftCounterWire = Wire(UInt(7.W)) 52 | withReset(!bscane2.SHIFT) { 53 | withClock(posClock) { 54 | val shiftCounter = RegInit(0.U(7.W)) 55 | val posCounter = RegInit(0.U(8.W)) 56 | val tdiRegister = RegInit(false.B) 57 | posCounter := posCounter + 1.U 58 | when(posCounter >= 1.U && posCounter <= 7.U) { 59 | shiftCounter := Cat(bscane2.TDI, shiftCounter.head(6)) 60 | } 61 | when(posCounter === 0.U) { 62 | tdiRegister := !bscane2.TDI 63 | } 64 | tdiRegisterWire := tdiRegister 65 | shiftCounterWire := shiftCounter 66 | } 67 | withClock(negClock) { 68 | val negCounter = RegInit(0.U(8.W)) 69 | negCounter := negCounter + 1.U 70 | tms := MuxLookup(negCounter, false.B)( 71 | Array( 72 | 4.U -> tdiRegisterWire, 73 | 5.U -> true.B, 74 | shiftCounterWire + 7.U -> true.B, 75 | shiftCounterWire + 8.U -> true.B 76 | ) 77 | ) 78 | } 79 | } 80 | } 81 | -------------------------------------------------------------------------------- /src/main/scala/Configs.scala: -------------------------------------------------------------------------------- 1 | package vcu128 2 | 3 | import freechips.rocketchip.rocket._ 4 | import freechips.rocketchip.devices.debug._ 5 | import freechips.rocketchip.devices.tilelink.BootROMLocated 6 | import freechips.rocketchip.subsystem._ 7 | import freechips.rocketchip.subsystem.MemoryPortParams 8 | import freechips.rocketchip.subsystem.WithInclusiveCache 9 | import org.chipsalliance.cde.config.Config 10 | import boom.v4.common.BoomTileAttachParams 11 | import boom.v4.common.WithNMediumBooms 12 | 13 | class WithBootROMResetAddress(resetAddress: BigInt) 14 | extends Config((_, _, up) => { case BootROMLocated(x) => 15 | up(BootROMLocated(x)).map(_.copy(hang = resetAddress)) 16 | }) 17 | 18 | class WithIDBits(n: Int) 19 | extends Config((_, _, up) => { 20 | case ExtMem => 21 | up(ExtMem).map(x => x.copy(master = x.master.copy(idBits = n))) 22 | case ExtBus => up(ExtBus).map(x => x.copy(idBits = n)) 23 | }) 24 | 25 | class WithCustomMMIOPort 26 | extends Config((site, _, _) => { case ExtBus => 27 | Some( 28 | MasterPortParams( 29 | base = BigInt("60000000", 16), 30 | size = BigInt("20000000", 16), 31 | beatBytes = site(MemoryBusKey).beatBytes, 32 | idBits = 4 33 | ) 34 | ) 35 | }) 36 | 37 | class WithCustomMemPort 38 | extends Config((site, _, _) => { case ExtMem => 39 | Some( 40 | MemoryPortParams( 41 | MasterPortParams( 42 | base = BigInt("80000000", 16), 43 | size = BigInt("80000000", 16), 44 | beatBytes = site(MemoryBusKey).beatBytes, 45 | idBits = 4 46 | ), 47 | 1 48 | ) 49 | ) 50 | }) 51 | 52 | class WithCFlush 53 | extends Config((_, _, up) => { case TilesLocated(InSubsystem) => 54 | up(TilesLocated(InSubsystem)) map { 55 | case tp: RocketTileAttachParams => 56 | tp.copy(tileParams = 57 | tp.tileParams.copy( 58 | core = tp.tileParams.core.copy( 59 | haveCFlush = true 60 | ) 61 | ) 62 | ) 63 | case tp: BoomTileAttachParams => 64 | tp.copy(tileParams = 65 | tp.tileParams.copy( 66 | core = tp.tileParams.core.copy( 67 | haveCFlush = true 68 | ) 69 | ) 70 | ) 71 | case t => t 72 | } 73 | }) 74 | 75 | class WithCustomJtag 76 | extends Config((_, _, _) => { case JtagDTMKey => 77 | new JtagDTMConfig( 78 | idcodeVersion = 1, 79 | idcodePartNum = 0, 80 | idcodeManufId = 0x489, // SiFive 81 | debugIdleCycles = 5 82 | ) 83 | }) 84 | 85 | class BaseConfig 86 | extends Config( 87 | new WithInclusiveCache ++ 88 | new WithBootROMResetAddress(0x10000) ++ 89 | new WithNExtTopInterrupts(6) ++ // UART(1) + ETH(1+2) + I2C(1) + SPI(1) 90 | new WithCustomMemPort ++ 91 | new WithCustomMMIOPort ++ 92 | new WithDefaultSlavePort ++ 93 | new freechips.rocketchip.system.BaseConfig 94 | ) 95 | 96 | class RocketConfig 97 | extends Config( 98 | new WithCoherentBusTopology ++ 99 | new WithoutTLMonitors ++ 100 | new WithIDBits(5) ++ 101 | new WithCFlush ++ 102 | new WithCustomJtag ++ 103 | new WithJtagDTM ++ 104 | // Rocket Core 105 | new WithNHugeCores(2) ++ 106 | new BaseConfig 107 | ) 108 | 109 | class BOOMConfig 110 | extends Config( 111 | new WithCoherentBusTopology ++ 112 | new WithoutTLMonitors ++ 113 | new WithIDBits(5) ++ 114 | new WithCFlush ++ 115 | new WithCustomJtag ++ 116 | new WithJtagDTM ++ 117 | // BOOM Core 118 | new WithNMediumBooms(2) ++ 119 | new BaseConfig 120 | ) 121 | 122 | // set reset address to 0x80000000 for simulation 123 | class SimConfig 124 | extends Config( 125 | new WithBootROMResetAddress(0x80000000L) ++ 126 | new RocketConfig 127 | ) 128 | -------------------------------------------------------------------------------- /src/main/scala/Top.scala: -------------------------------------------------------------------------------- 1 | package vcu128 2 | 3 | import chisel3._ 4 | import freechips.rocketchip.devices.tilelink._ 5 | import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 6 | import freechips.rocketchip.subsystem._ 7 | import freechips.rocketchip.util._ 8 | import freechips.rocketchip.tile._ 9 | import freechips.rocketchip.devices.debug.HasPeripheryDebug 10 | import freechips.rocketchip.jtag.JTAGIO 11 | import freechips.rocketchip.devices.debug.Debug 12 | import freechips.rocketchip.devices.debug.JtagDTMKey 13 | import org.chipsalliance.cde.config.Parameters 14 | 15 | class RocketChip(implicit val p: Parameters) extends Module { 16 | val config = p(ExtIn) 17 | val top = LazyModule(new RocketTop) 18 | val target = Module(top.module) 19 | 20 | top.io_clocks.get.elements.values.foreach(_.clock := clock) 21 | // Allow the debug ndreset to reset the dut, but not until the initial reset has completed 22 | val childReset = (reset.asBool | top.debug 23 | .map { debug => AsyncResetReg(debug.ndreset) } 24 | .getOrElse(false.B)).asBool 25 | top.io_clocks.get.elements.values.foreach(_.reset := childReset) 26 | 27 | require(target.mem_axi4.size == 1) 28 | require(target.mmio_axi4.size == 1) 29 | require(target.slave_axi4.size == 1) 30 | 31 | val io = IO(new Bundle { 32 | val interrupts = Input(UInt(p(NExtTopInterrupts).W)) 33 | val mem_axi4 = target.mem_axi4.head.cloneType 34 | val mmio_axi4 = target.mmio_axi4.head.cloneType 35 | val slave_axi4 = Flipped(target.slave_axi4.head.cloneType) 36 | val jtag = Flipped(new JTAGIO()) 37 | }) 38 | 39 | val systemJtag = top.debug.get.systemjtag.get 40 | systemJtag.jtag.TCK := io.jtag.TCK 41 | systemJtag.jtag.TMS := io.jtag.TMS 42 | systemJtag.jtag.TDI := io.jtag.TDI 43 | io.jtag.TDO := systemJtag.jtag.TDO 44 | systemJtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) 45 | systemJtag.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) 46 | systemJtag.version := p(JtagDTMKey).idcodeVersion.U(4.W) 47 | // MUST use async reset here 48 | // otherwise the internal logic(e.g. TLXbar) might not function 49 | // if reset deasserted before TCK rises 50 | systemJtag.reset := reset.asAsyncReset 51 | top.resetctrl.foreach { rc => 52 | rc.hartIsInReset.foreach { _ := childReset } 53 | } 54 | 55 | Debug.connectDebugClockAndReset(top.debug, clock) 56 | 57 | io.mem_axi4 <> target.mem_axi4.head 58 | io.mmio_axi4 <> target.mmio_axi4.head 59 | io.slave_axi4 <> target.slave_axi4.head 60 | 61 | target.interrupts := io.interrupts 62 | 63 | target.dontTouchPorts() 64 | } 65 | 66 | class RocketTop(implicit p: Parameters) 67 | extends RocketSubsystem 68 | with HasAsyncExtInterrupts 69 | with HasPeripheryDebug 70 | with CanHaveMasterAXI4MemPort 71 | with CanHaveMasterAXI4MMIOPort 72 | with CanHaveSlaveAXI4Port { 73 | override lazy val module = new RocketTopModule(this) 74 | 75 | // from freechips.rocketchip.system.ExampleRocketSystem 76 | val bootROM = p(BootROMLocated(location)).map { 77 | BootROM.attach(_, this, CBUS) 78 | } 79 | } 80 | 81 | class RocketTopModule(outer: RocketTop) 82 | extends RocketSubsystemModuleImp(outer) 83 | with HasRTCModuleImp 84 | with HasExtInterruptsModuleImp 85 | with DontTouch { 86 | lazy val mem_axi4 = outer.mem_axi4 87 | lazy val mmio_axi4 = outer.mmio_axi4 88 | lazy val slave_axi4 = outer.l2_frontend_bus_axi4 89 | } 90 | -------------------------------------------------------------------------------- /src/other/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jiegec/rocket-chip-vcu128/7aa67a4046fdebdc74d05a61fe0a4eec4dd2cf8f/src/other/.keep -------------------------------------------------------------------------------- /verilator/.gitignore: -------------------------------------------------------------------------------- 1 | obj_dir 2 | *.vcd 3 | *.log 4 | Vtestbench_rocketchip 5 | -------------------------------------------------------------------------------- /verilator/BSCANE2.v: -------------------------------------------------------------------------------- 1 | module BSCANE2 ( 2 | output CAPTURE, 3 | output DRCK, 4 | output RESET, 5 | output RUNTEST, 6 | output SEL, 7 | output SHIFT, 8 | output TCK, 9 | output TDI, 10 | output TMS, 11 | output UPDATE, 12 | 13 | input TDO 14 | ); 15 | 16 | parameter integer JTAG_CHAIN = 1; 17 | 18 | assign CAPTURE = 0; 19 | assign DRCK = 0; 20 | assign RESET = 0; 21 | assign RUNTEST = 1; 22 | assign SEL = 0; 23 | assign SHIFT = 0; 24 | assign TCK = 0; 25 | assign TDI = 0; 26 | assign TMS = 0; 27 | assign UPDATE = 0; 28 | endmodule 29 | -------------------------------------------------------------------------------- /verilator/BUFGCE.v: -------------------------------------------------------------------------------- 1 | module BUFGCE ( 2 | output O, 3 | input CE, 4 | input I 5 | ); 6 | assign O = CE ? I : 1'b0; 7 | endmodule -------------------------------------------------------------------------------- /verilator/EICG_wrapper.v: -------------------------------------------------------------------------------- 1 | ../src/hdl/EICG_wrapper.v -------------------------------------------------------------------------------- /verilator/Makefile: -------------------------------------------------------------------------------- 1 | CFLAGS ?= --std=c++14 -O3 2 | GMP_CFLAGS = $(shell pkg-config --cflags gmp) 3 | GMP_LDFLAGS = $(shell pkg-config --libs gmp) 4 | GMPXX_CFLAGS = $(shell pkg-config --cflags gmpxx) 5 | GMPXX_LDFLAGS = $(shell pkg-config --libs gmpxx) 6 | NCURSES_CFLAGS = $(shell pkg-config --cflags ncurses) 7 | NCURSES_LDFLAGS = $(shell pkg-config --libs ncurses) 8 | VERILATOR ?= verilator 9 | VERILATOR_FLAGS ?= -threads 4 -O3 -Wall -Wno-fatal -trace -CFLAGS "$(CFLAGS) $(GMP_CFLAGS) $(GMPXX_CFLAGS) $(NCURSES_CFLAGS)" -LDFLAGS "$(GMP_LDFLAGS) $(GMP_LDFLAGS) $(NCURSES_LDFLAGS)" --timescale-override 1ns/1ns 10 | 11 | all: Vtestbench_rocketchip 12 | 13 | Vtestbench_rocketchip: *.v top.cpp 14 | $(VERILATOR) $(VERILATOR_FLAGS) --cc testbench_rocketchip.v --exe top.cpp 15 | make -j -C obj_dir -f Vtestbench_rocketchip.mk Vtestbench_rocketchip 16 | cp obj_dir/Vtestbench_rocketchip . 17 | 18 | .PHONY: clean disasm all 19 | clean: 20 | rm -f Vtestbench_rocketchip 21 | rm -rf obj_dir 22 | -------------------------------------------------------------------------------- /verilator/README.md: -------------------------------------------------------------------------------- 1 | # Simulation 2 | 3 | You can simulate the dual core system in verilator: 4 | 5 | ```shell 6 | # generate verilog for simulation 7 | make -C .. CONFIG=SimConfig 8 | # compile simulator 9 | make 10 | # boot to uboot 11 | ./Vtestbench_rocketchip ~/opensbi/build/platform/rocket-chip-vcu128-dual-core/firmware/fw_payload.bin 2>/dev/null 12 | # boot to uboot & linux 13 | # you need to run `bootm 0x80100000` in u-boot shell 14 | ./Vtestbench_rocketchip ~/opensbi/build/platform/rocket-chip-vcu128-dual-core/firmware/fw_payload.bin ~/linux/arch/riscv/boot/image-dual-core.itb 2>/dev/null 15 | ``` 16 | -------------------------------------------------------------------------------- /verilator/RocketChip.sv: -------------------------------------------------------------------------------- 1 | ../build/vcu128.SimConfig.sv -------------------------------------------------------------------------------- /verilator/axi_ram.v: -------------------------------------------------------------------------------- 1 | ../submodules/verilog-axi/rtl/axi_ram.v -------------------------------------------------------------------------------- /verilator/plusarg_reader.v: -------------------------------------------------------------------------------- 1 | ../src/hdl/plusarg_reader.v -------------------------------------------------------------------------------- /verilator/rocketchip_wrapper.v: -------------------------------------------------------------------------------- 1 | ../src/hdl/rocketchip_wrapper.v -------------------------------------------------------------------------------- /verilator/testbench_rocketchip.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////// 2 | // Company: 3 | // Engineer: 4 | // 5 | // Create Date: 11/05/2019 12:21:36 PM 6 | // Design Name: 7 | // Module Name: testbench_rocketchip 8 | // Project Name: 9 | // Target Devices: 10 | // Tool Versions: 11 | // Description: 12 | // 13 | // Dependencies: 14 | // 15 | // Revision: 16 | // Revision 0.01 - File Created 17 | // Additional Comments: 18 | // 19 | ////////////////////////////////////////////////////////////////////////////////// 20 | 21 | 22 | module testbench_rocketchip( 23 | clock, 24 | reset, 25 | interrupts, 26 | 27 | // MEM 28 | M_AXI_awready, 29 | M_AXI_awvalid, 30 | M_AXI_awid, 31 | M_AXI_awaddr, 32 | M_AXI_awlen, 33 | M_AXI_awsize, 34 | M_AXI_awburst, 35 | M_AXI_awlock, 36 | M_AXI_awcache, 37 | M_AXI_awprot, 38 | M_AXI_awqos, 39 | 40 | M_AXI_wready, 41 | M_AXI_wvalid, 42 | M_AXI_wdata, 43 | M_AXI_wstrb, 44 | M_AXI_wlast, 45 | 46 | M_AXI_bready, 47 | M_AXI_bvalid, 48 | M_AXI_bid, 49 | M_AXI_bresp, 50 | 51 | M_AXI_arready, 52 | M_AXI_arvalid, 53 | M_AXI_arid, 54 | M_AXI_araddr, 55 | M_AXI_arlen, 56 | M_AXI_arsize, 57 | M_AXI_arburst, 58 | M_AXI_arlock, 59 | M_AXI_arcache, 60 | M_AXI_arprot, 61 | M_AXI_arqos, 62 | 63 | M_AXI_rready, 64 | M_AXI_rvalid, 65 | M_AXI_rid, 66 | M_AXI_rdata, 67 | M_AXI_rresp, 68 | M_AXI_rlast, 69 | 70 | // MMIO 71 | M_AXI_MMIO_awready, 72 | M_AXI_MMIO_awvalid, 73 | M_AXI_MMIO_awid, 74 | M_AXI_MMIO_awaddr, 75 | M_AXI_MMIO_awlen, 76 | M_AXI_MMIO_awsize, 77 | M_AXI_MMIO_awburst, 78 | M_AXI_MMIO_awlock, 79 | M_AXI_MMIO_awcache, 80 | M_AXI_MMIO_awprot, 81 | M_AXI_MMIO_awqos, 82 | 83 | M_AXI_MMIO_wready, 84 | M_AXI_MMIO_wvalid, 85 | M_AXI_MMIO_wdata, 86 | M_AXI_MMIO_wstrb, 87 | M_AXI_MMIO_wlast, 88 | 89 | M_AXI_MMIO_bready, 90 | M_AXI_MMIO_bvalid, 91 | M_AXI_MMIO_bid, 92 | M_AXI_MMIO_bresp, 93 | 94 | M_AXI_MMIO_arready, 95 | M_AXI_MMIO_arvalid, 96 | M_AXI_MMIO_arid, 97 | M_AXI_MMIO_araddr, 98 | M_AXI_MMIO_arlen, 99 | M_AXI_MMIO_arsize, 100 | M_AXI_MMIO_arburst, 101 | M_AXI_MMIO_arlock, 102 | M_AXI_MMIO_arcache, 103 | M_AXI_MMIO_arprot, 104 | M_AXI_MMIO_arqos, 105 | 106 | M_AXI_MMIO_rready, 107 | M_AXI_MMIO_rvalid, 108 | M_AXI_MMIO_rid, 109 | M_AXI_MMIO_rdata, 110 | M_AXI_MMIO_rresp, 111 | M_AXI_MMIO_rlast, 112 | 113 | // JTAG 114 | jtag_TCK, 115 | jtag_TMS, 116 | jtag_TDI, 117 | jtag_TDO 118 | ); 119 | 120 | input clock; 121 | input reset; 122 | input [5:0] interrupts; 123 | 124 | // MEM 125 | input M_AXI_awready; 126 | output M_AXI_awvalid; 127 | output [4:0] M_AXI_awid; 128 | output [63:0] M_AXI_awaddr; 129 | output [7:0] M_AXI_awlen; 130 | output [2:0] M_AXI_awsize; 131 | output [1:0] M_AXI_awburst; 132 | output M_AXI_awlock; 133 | output [3:0] M_AXI_awcache; 134 | output [2:0] M_AXI_awprot; 135 | output [3:0] M_AXI_awqos; 136 | 137 | input M_AXI_wready; 138 | output M_AXI_wvalid; 139 | output [63:0] M_AXI_wdata; 140 | output [7:0] M_AXI_wstrb; 141 | output M_AXI_wlast; 142 | 143 | output M_AXI_bready; 144 | input M_AXI_bvalid; 145 | input [4:0] M_AXI_bid; 146 | input [1:0] M_AXI_bresp; 147 | 148 | input M_AXI_arready; 149 | output M_AXI_arvalid; 150 | output [4:0] M_AXI_arid; 151 | output [63:0] M_AXI_araddr; 152 | output [7:0] M_AXI_arlen; 153 | output [2:0] M_AXI_arsize; 154 | output [1:0] M_AXI_arburst; 155 | output M_AXI_arlock; 156 | output [3:0] M_AXI_arcache; 157 | output [2:0] M_AXI_arprot; 158 | output [3:0] M_AXI_arqos; 159 | 160 | output M_AXI_rready; 161 | input M_AXI_rvalid; 162 | input [4:0] M_AXI_rid; 163 | input [63:0] M_AXI_rdata; 164 | input [1:0] M_AXI_rresp; 165 | input M_AXI_rlast; 166 | 167 | // MMIO 168 | input M_AXI_MMIO_awready; 169 | output M_AXI_MMIO_awvalid; 170 | output [4:0] M_AXI_MMIO_awid; 171 | output [63:0] M_AXI_MMIO_awaddr; 172 | output [7:0] M_AXI_MMIO_awlen; 173 | output [2:0] M_AXI_MMIO_awsize; 174 | output [1:0] M_AXI_MMIO_awburst; 175 | output M_AXI_MMIO_awlock; 176 | output [3:0] M_AXI_MMIO_awcache; 177 | output [2:0] M_AXI_MMIO_awprot; 178 | output [3:0] M_AXI_MMIO_awqos; 179 | 180 | input M_AXI_MMIO_wready; 181 | output M_AXI_MMIO_wvalid; 182 | output [63:0] M_AXI_MMIO_wdata; 183 | output [7:0] M_AXI_MMIO_wstrb; 184 | output M_AXI_MMIO_wlast; 185 | 186 | output M_AXI_MMIO_bready; 187 | input M_AXI_MMIO_bvalid; 188 | input [4:0] M_AXI_MMIO_bid; 189 | input [1:0] M_AXI_MMIO_bresp; 190 | 191 | input M_AXI_MMIO_arready; 192 | output M_AXI_MMIO_arvalid; 193 | output [4:0] M_AXI_MMIO_arid; 194 | output [63:0] M_AXI_MMIO_araddr; 195 | output [7:0] M_AXI_MMIO_arlen; 196 | output [2:0] M_AXI_MMIO_arsize; 197 | output [1:0] M_AXI_MMIO_arburst; 198 | output M_AXI_MMIO_arlock; 199 | output [3:0] M_AXI_MMIO_arcache; 200 | output [2:0] M_AXI_MMIO_arprot; 201 | output [3:0] M_AXI_MMIO_arqos; 202 | 203 | output M_AXI_MMIO_rready; 204 | input M_AXI_MMIO_rvalid; 205 | input [4:0] M_AXI_MMIO_rid; 206 | input [63:0] M_AXI_MMIO_rdata; 207 | input [1:0] M_AXI_MMIO_rresp; 208 | input M_AXI_MMIO_rlast; 209 | 210 | // jtag 211 | input jtag_TCK; 212 | input jtag_TMS; 213 | input jtag_TDI; 214 | output jtag_TDO; 215 | 216 | rocketchip_wrapper dut ( 217 | .clk(clock), 218 | .reset(reset), 219 | .interrupts(interrupts), 220 | 221 | .M_AXI_awready(M_AXI_awready), 222 | .M_AXI_awvalid(M_AXI_awvalid), 223 | .M_AXI_awid(M_AXI_awid), 224 | .M_AXI_awaddr(M_AXI_awaddr), 225 | .M_AXI_awlen(M_AXI_awlen), 226 | .M_AXI_awsize(M_AXI_awsize), 227 | .M_AXI_awburst(M_AXI_awburst), 228 | .M_AXI_awlock(M_AXI_awlock), 229 | .M_AXI_awcache(M_AXI_awcache), 230 | .M_AXI_awprot(M_AXI_awprot), 231 | .M_AXI_awqos(M_AXI_awqos), 232 | 233 | .M_AXI_wready(M_AXI_wready), 234 | .M_AXI_wvalid(M_AXI_wvalid), 235 | .M_AXI_wdata(M_AXI_wdata), 236 | .M_AXI_wstrb(M_AXI_wstrb), 237 | .M_AXI_wlast(M_AXI_wlast), 238 | 239 | .M_AXI_bready(M_AXI_bready), 240 | .M_AXI_bvalid(M_AXI_bvalid), 241 | .M_AXI_bid(M_AXI_bid), 242 | .M_AXI_bresp(M_AXI_bresp), 243 | 244 | .M_AXI_arready(M_AXI_arready), 245 | .M_AXI_arvalid(M_AXI_arvalid), 246 | .M_AXI_arid(M_AXI_arid), 247 | .M_AXI_araddr(M_AXI_araddr), 248 | .M_AXI_arlen(M_AXI_arlen), 249 | .M_AXI_arsize(M_AXI_arsize), 250 | .M_AXI_arburst(M_AXI_arburst), 251 | .M_AXI_arlock(M_AXI_arlock), 252 | .M_AXI_arcache(M_AXI_arcache), 253 | .M_AXI_arprot(M_AXI_arprot), 254 | .M_AXI_arqos(M_AXI_arqos), 255 | 256 | .M_AXI_rready(M_AXI_rready), 257 | .M_AXI_rvalid(M_AXI_rvalid), 258 | .M_AXI_rid(M_AXI_rid), 259 | .M_AXI_rdata(M_AXI_rdata), 260 | .M_AXI_rresp(M_AXI_rresp), 261 | .M_AXI_rlast(M_AXI_rlast), 262 | 263 | .M_AXI_MMIO_awready(M_AXI_MMIO_awready), 264 | .M_AXI_MMIO_awvalid(M_AXI_MMIO_awvalid), 265 | .M_AXI_MMIO_awid(M_AXI_MMIO_awid), 266 | .M_AXI_MMIO_awaddr(M_AXI_MMIO_awaddr), 267 | .M_AXI_MMIO_awlen(M_AXI_MMIO_awlen), 268 | .M_AXI_MMIO_awsize(M_AXI_MMIO_awsize), 269 | .M_AXI_MMIO_awburst(M_AXI_MMIO_awburst), 270 | .M_AXI_MMIO_awlock(M_AXI_MMIO_awlock), 271 | .M_AXI_MMIO_awcache(M_AXI_MMIO_awcache), 272 | .M_AXI_MMIO_awprot(M_AXI_MMIO_awprot), 273 | .M_AXI_MMIO_awqos(M_AXI_MMIO_awqos), 274 | 275 | .M_AXI_MMIO_wready(M_AXI_MMIO_wready), 276 | .M_AXI_MMIO_wvalid(M_AXI_MMIO_wvalid), 277 | .M_AXI_MMIO_wdata(M_AXI_MMIO_wdata), 278 | .M_AXI_MMIO_wstrb(M_AXI_MMIO_wstrb), 279 | .M_AXI_MMIO_wlast(M_AXI_MMIO_wlast), 280 | 281 | .M_AXI_MMIO_bready(M_AXI_MMIO_bready), 282 | .M_AXI_MMIO_bvalid(M_AXI_MMIO_bvalid), 283 | .M_AXI_MMIO_bid(M_AXI_MMIO_bid), 284 | .M_AXI_MMIO_bresp(M_AXI_MMIO_bresp), 285 | 286 | .M_AXI_MMIO_arready(M_AXI_MMIO_arready), 287 | .M_AXI_MMIO_arvalid(M_AXI_MMIO_arvalid), 288 | .M_AXI_MMIO_arid(M_AXI_MMIO_arid), 289 | .M_AXI_MMIO_araddr(M_AXI_MMIO_araddr), 290 | .M_AXI_MMIO_arlen(M_AXI_MMIO_arlen), 291 | .M_AXI_MMIO_arsize(M_AXI_MMIO_arsize), 292 | .M_AXI_MMIO_arburst(M_AXI_MMIO_arburst), 293 | .M_AXI_MMIO_arlock(M_AXI_MMIO_arlock), 294 | .M_AXI_MMIO_arcache(M_AXI_MMIO_arcache), 295 | .M_AXI_MMIO_arprot(M_AXI_MMIO_arprot), 296 | .M_AXI_MMIO_arqos(M_AXI_MMIO_arqos), 297 | 298 | .M_AXI_MMIO_rready(M_AXI_MMIO_rready), 299 | .M_AXI_MMIO_rvalid(M_AXI_MMIO_rvalid), 300 | .M_AXI_MMIO_rid(M_AXI_MMIO_rid), 301 | .M_AXI_MMIO_rdata(M_AXI_MMIO_rdata), 302 | .M_AXI_MMIO_rresp(M_AXI_MMIO_rresp), 303 | .M_AXI_MMIO_rlast(M_AXI_MMIO_rlast), 304 | 305 | .S_AXI_awvalid(1'b0), 306 | .S_AXI_wvalid(1'b0), 307 | .S_AXI_bready(1'b0), 308 | .S_AXI_arvalid(1'b0), 309 | .S_AXI_rready(1'b0), 310 | 311 | .jtag_TCK(jtag_TCK), 312 | .jtag_TMS(jtag_TMS), 313 | .jtag_TDI(jtag_TDI), 314 | .jtag_TDO(jtag_TDO) 315 | ); 316 | endmodule 317 | -------------------------------------------------------------------------------- /verilator/top.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | 14 | #if VM_TRACE 15 | #include // Trace file format header 16 | #endif 17 | 18 | using namespace std; 19 | 20 | // VGCDTester *top; 21 | Vtestbench_rocketchip *top; 22 | 23 | uint64_t sim_time = 24 | 0; // Current simulation time 25 | // This is a 64-bit integer to reduce wrap over issues and 26 | // allow modulus. You can also use a double, if you wish. 27 | 28 | double sc_time_stamp() { // Called by $time in Verilog 29 | return sim_time; // converts to double, to match 30 | // what SystemC does 31 | } 32 | 33 | // memory mapping 34 | typedef uint32_t mem_t; 35 | std::map memory; 36 | 37 | // align to mem_t boundary 38 | uint64_t align(uint64_t addr) { return (addr / sizeof(mem_t)) * sizeof(mem_t); } 39 | 40 | const uint64_t MEM_AXI_DATA_WIDTH = 64; 41 | const uint64_t MEM_AXI_DATA_BYTES = MEM_AXI_DATA_WIDTH / 8; 42 | const uint64_t MMIO_AXI_DATA_WIDTH = 64; 43 | const uint64_t MMIO_AXI_DATA_BYTES = MMIO_AXI_DATA_WIDTH / 8; 44 | 45 | // serial 46 | // default at 0x60201000 47 | uint64_t serial_addr = 0x60201000; 48 | 49 | // axi ethernet 50 | uint64_t emac_addr = 0x60400000; 51 | 52 | // initialize signals 53 | void init() { 54 | top->M_AXI_awready = 0; 55 | top->M_AXI_wready = 0; 56 | top->M_AXI_bvalid = 0; 57 | 58 | top->M_AXI_arready = 0; 59 | top->M_AXI_rvalid = 0; 60 | 61 | top->M_AXI_MMIO_awready = 0; 62 | top->M_AXI_MMIO_wready = 0; 63 | top->M_AXI_MMIO_bvalid = 0; 64 | 65 | top->M_AXI_MMIO_arready = 0; 66 | top->M_AXI_MMIO_rvalid = 0; 67 | } 68 | 69 | // step per clock fall 70 | void step_mem() { 71 | // handle read 72 | static bool pending_read = false; 73 | static uint64_t pending_read_id = 0; 74 | static uint64_t pending_read_addr = 0; 75 | static uint64_t pending_read_len = 0; 76 | static uint64_t pending_read_size = 0; 77 | 78 | if (!pending_read) { 79 | if (top->M_AXI_arvalid) { 80 | top->M_AXI_arready = 1; 81 | pending_read = true; 82 | pending_read_id = top->M_AXI_arid; 83 | pending_read_addr = top->M_AXI_araddr; 84 | pending_read_len = top->M_AXI_arlen; 85 | pending_read_size = top->M_AXI_arsize; 86 | } 87 | 88 | top->M_AXI_rvalid = 0; 89 | } else { 90 | top->M_AXI_arready = 0; 91 | 92 | top->M_AXI_rvalid = 1; 93 | top->M_AXI_rid = pending_read_id; 94 | mpz_class r_data; 95 | 96 | uint64_t aligned = 97 | (pending_read_addr / MEM_AXI_DATA_BYTES) * MEM_AXI_DATA_BYTES; 98 | for (int i = 0; i < MEM_AXI_DATA_BYTES / sizeof(mem_t); i++) { 99 | uint64_t addr = aligned + i * sizeof(mem_t); 100 | mem_t r = memory[addr]; 101 | mpz_class res = r; 102 | res <<= (i * (sizeof(mem_t) * 8)); 103 | r_data += res; 104 | } 105 | 106 | mpz_class mask = 1; 107 | mask <<= (1L << pending_read_size) * 8; 108 | mask -= 1; 109 | 110 | mpz_class shifted_mask = 111 | mask << ((pending_read_addr & (MEM_AXI_DATA_BYTES - 1)) * 8); 112 | r_data &= shifted_mask; 113 | 114 | // top->M_AXI_rdata = r_data & shifted_mask; 115 | memset(&top->M_AXI_rdata, 0, sizeof(top->M_AXI_rdata)); 116 | mpz_export(&top->M_AXI_rdata, NULL, -1, 4, -1, 0, r_data.get_mpz_t()); 117 | top->M_AXI_rlast = pending_read_len == 0; 118 | 119 | // RREADY might be stale without eval() 120 | top->eval(); 121 | if (top->M_AXI_rready) { 122 | if (pending_read_len == 0) { 123 | pending_read = false; 124 | } else { 125 | pending_read_addr += 1 << pending_read_size; 126 | pending_read_len--; 127 | } 128 | } 129 | } 130 | 131 | // handle write 132 | static bool pending_write = false; 133 | static bool pending_write_finished = false; 134 | static uint64_t pending_write_addr = 0; 135 | static uint64_t pending_write_len = 0; 136 | static uint64_t pending_write_size = 0; 137 | static uint64_t pending_write_id = 0; 138 | if (!pending_write) { 139 | // idle 140 | if (top->M_AXI_awvalid) { 141 | top->M_AXI_awready = 1; 142 | pending_write = true; 143 | pending_write_addr = top->M_AXI_awaddr; 144 | pending_write_len = top->M_AXI_awlen; 145 | pending_write_size = top->M_AXI_awsize; 146 | pending_write_id = top->M_AXI_awid; 147 | pending_write_finished = false; 148 | } 149 | top->M_AXI_wready = 0; 150 | top->M_AXI_bvalid = 0; 151 | } else if (!pending_write_finished) { 152 | // writing 153 | top->M_AXI_awready = 0; 154 | top->M_AXI_wready = 1; 155 | 156 | // WVALID might be stale without eval() 157 | top->eval(); 158 | if (top->M_AXI_wvalid) { 159 | mpz_class mask = 1; 160 | mask <<= 1L << pending_write_size; 161 | mask -= 1; 162 | 163 | mpz_class shifted_mask = 164 | mask << (pending_write_addr & (MEM_AXI_DATA_BYTES - 1)); 165 | mpz_class wdata; 166 | mpz_import(wdata.get_mpz_t(), MEM_AXI_DATA_BYTES / 4, -1, 4, -1, 0, 167 | &top->M_AXI_wdata); 168 | 169 | uint64_t aligned = 170 | pending_write_addr / MEM_AXI_DATA_BYTES * MEM_AXI_DATA_BYTES; 171 | for (int i = 0; i < MEM_AXI_DATA_BYTES / sizeof(mem_t); i++) { 172 | uint64_t addr = aligned + i * sizeof(mem_t); 173 | 174 | mpz_class local_wdata_mpz = wdata >> (i * (sizeof(mem_t) * 8)); 175 | mem_t local_wdata = local_wdata_mpz.get_ui(); 176 | 177 | uint64_t local_wstrb = (top->M_AXI_wstrb >> (i * sizeof(mem_t))) & 0xfL; 178 | 179 | mpz_class local_mask_mpz = shifted_mask >> (i * sizeof(mem_t)); 180 | uint64_t local_mask = local_mask_mpz.get_ui() & 0xfL; 181 | if (local_mask & local_wstrb) { 182 | mem_t base = memory[addr]; 183 | mem_t input = local_wdata; 184 | uint64_t be = local_mask & local_wstrb; 185 | 186 | mem_t muxed = 0; 187 | for (int i = 0; i < sizeof(mem_t); i++) { 188 | mem_t sel; 189 | if (((be >> i) & 1) == 1) { 190 | sel = (input >> (i * 8)) & 0xff; 191 | } else { 192 | sel = (base >> (i * 8)) & 0xff; 193 | } 194 | muxed |= (sel << (i * 8)); 195 | } 196 | 197 | memory[addr] = muxed; 198 | } 199 | } 200 | 201 | uint64_t input = wdata.get_ui(); 202 | pending_write_addr += 1L << pending_write_size; 203 | pending_write_len--; 204 | if (top->M_AXI_wlast) { 205 | assert(pending_write_len == -1); 206 | pending_write_finished = true; 207 | } 208 | } 209 | 210 | top->M_AXI_bvalid = 0; 211 | } else { 212 | // finishing 213 | top->M_AXI_awready = 0; 214 | top->M_AXI_wready = 0; 215 | top->M_AXI_bvalid = 1; 216 | top->M_AXI_bresp = 0; 217 | top->M_AXI_bid = pending_write_id; 218 | 219 | // BREADY might be stale without eval() 220 | top->eval(); 221 | if (top->M_AXI_bready) { 222 | pending_write = false; 223 | pending_write_finished = false; 224 | } 225 | } 226 | } 227 | 228 | // step per clock fall 229 | void step_mmio() { 230 | // handle read 231 | static bool pending_read = false; 232 | static uint64_t pending_read_id = 0; 233 | static uint64_t pending_read_addr = 0; 234 | static uint64_t pending_read_len = 0; 235 | static uint64_t pending_read_size = 0; 236 | 237 | if (!pending_read) { 238 | if (top->M_AXI_MMIO_arvalid) { 239 | top->M_AXI_MMIO_arready = 1; 240 | pending_read = true; 241 | pending_read_id = top->M_AXI_MMIO_arid; 242 | pending_read_addr = top->M_AXI_MMIO_araddr; 243 | pending_read_len = top->M_AXI_MMIO_arlen; 244 | pending_read_size = top->M_AXI_MMIO_arsize; 245 | } 246 | 247 | top->M_AXI_MMIO_rvalid = 0; 248 | } else { 249 | top->M_AXI_MMIO_arready = 0; 250 | 251 | top->M_AXI_MMIO_rvalid = 1; 252 | top->M_AXI_MMIO_rid = pending_read_id; 253 | mpz_class r_data; 254 | static std::vector serial_recv_fifo; 255 | int ch = getch(); 256 | if (ch != ERR) { 257 | serial_recv_fifo.push_back(ch); 258 | top->interrupts |= 1; 259 | } 260 | if (pending_read_addr == serial_addr) { 261 | // Receiver Holding Register 262 | if (serial_recv_fifo.size() > 0) { 263 | r_data = serial_recv_fifo[0]; 264 | serial_recv_fifo.erase(serial_recv_fifo.begin()); 265 | 266 | if (serial_recv_fifo.size() == 0) { 267 | top->interrupts &= ~1; 268 | } 269 | } else { 270 | // ignored 271 | r_data = 0; 272 | } 273 | } else if (pending_read_addr == serial_addr + 0x4) { 274 | // Interrupt Enable Register 275 | r_data = 0; 276 | } else if (pending_read_addr == serial_addr + 0x8) { 277 | // Interrupt Status Register 278 | uint64_t isr = 0; 279 | if (serial_recv_fifo.size() > 0) { 280 | // interrupt status 281 | isr |= (1L << 0); 282 | } 283 | r_data = isr; 284 | } else if (pending_read_addr == serial_addr + 0xc) { 285 | // Line Control Register 286 | r_data = 0; 287 | } else if (pending_read_addr == serial_addr + 0x14) { 288 | // Line Status Register 289 | // THRE | TEMT 290 | uint64_t lsr = (1L << 5) | (1L << 6); 291 | if (serial_recv_fifo.size() > 0) { 292 | // data ready 293 | lsr |= (1L << 0); 294 | } 295 | r_data = lsr << 32; 296 | } else if (pending_read_addr == serial_addr + 0x18) { 297 | // Modem Status Register 298 | r_data = 0; 299 | } else if (pending_read_addr == emac_addr + 0x504) { 300 | // MDIO Control Word (0x504) 301 | // bit 7: MDIO ready 302 | r_data = (uint64_t)(1 << 7) << 32; 303 | } else if (pending_read_addr == emac_addr + 0x50c) { 304 | // MDIO Read Data (0x50C) 305 | // bit 16: MDIO ready 306 | r_data = (uint64_t)(1 << 16) << 32; 307 | } else if (pending_read_addr == emac_addr + 0x704) { 308 | // Unicast Address Word 1 309 | r_data = 0; 310 | } else { 311 | printw("Unhandled mmio read from %lx\n", pending_read_addr); 312 | r_data = 0; 313 | } 314 | 315 | mpz_class mask = 1; 316 | mask <<= (1L << pending_read_size) * 8; 317 | mask -= 1; 318 | 319 | mpz_class shifted_mask = 320 | mask << ((pending_read_addr & (MMIO_AXI_DATA_BYTES - 1)) * 8); 321 | r_data &= shifted_mask; 322 | 323 | // top->M_AXI_MMIO_RDATA = r_data & shifted_mask; 324 | memset(&top->M_AXI_MMIO_rdata, 0, sizeof(top->M_AXI_MMIO_rdata)); 325 | mpz_export(&top->M_AXI_MMIO_rdata, NULL, -1, 4, -1, 0, r_data.get_mpz_t()); 326 | top->M_AXI_MMIO_rlast = pending_read_len == 0; 327 | 328 | // RREADY might be stale without eval() 329 | top->eval(); 330 | if (top->M_AXI_MMIO_rready) { 331 | if (pending_read_len == 0) { 332 | pending_read = false; 333 | } else { 334 | pending_read_addr += 1 << pending_read_size; 335 | pending_read_len--; 336 | } 337 | } 338 | } 339 | 340 | // handle write 341 | static bool pending_write = false; 342 | static bool pending_write_finished = false; 343 | static uint64_t pending_write_addr = 0; 344 | static uint64_t pending_write_len = 0; 345 | static uint64_t pending_write_size = 0; 346 | static uint64_t pending_write_id = 0; 347 | if (!pending_write) { 348 | if (top->M_AXI_MMIO_awvalid) { 349 | top->M_AXI_MMIO_awready = 1; 350 | pending_write = 1; 351 | pending_write_addr = top->M_AXI_MMIO_awaddr; 352 | pending_write_len = top->M_AXI_MMIO_awlen; 353 | pending_write_size = top->M_AXI_MMIO_awsize; 354 | pending_write_id = top->M_AXI_MMIO_awid; 355 | pending_write_finished = 0; 356 | } 357 | top->M_AXI_MMIO_wready = 0; 358 | top->M_AXI_MMIO_bvalid = 0; 359 | } else if (!pending_write_finished) { 360 | top->M_AXI_MMIO_awready = 0; 361 | top->M_AXI_MMIO_wready = 1; 362 | 363 | // WVALID might be stale without eval() 364 | top->eval(); 365 | if (top->M_AXI_MMIO_wvalid) { 366 | mpz_class mask = 1; 367 | mask <<= 1L << pending_write_size; 368 | mask -= 1; 369 | 370 | mpz_class shifted_mask = 371 | mask << (pending_write_addr & (MMIO_AXI_DATA_BYTES - 1)); 372 | mpz_class wdata; 373 | mpz_import(wdata.get_mpz_t(), MMIO_AXI_DATA_BYTES / 4, -1, 4, -1, 0, 374 | &top->M_AXI_MMIO_wdata); 375 | 376 | uint64_t input = wdata.get_ui(); 377 | static bool dlab = 0; 378 | // serial 379 | if (pending_write_addr == serial_addr) { 380 | if (!dlab) { 381 | static FILE *fp = NULL; 382 | if (!fp) { 383 | fp = fopen("console.log", "w"); 384 | assert(fp); 385 | } 386 | char ch = (char)(input & 0xFF); 387 | fputc(ch, fp); 388 | fflush(fp); 389 | if (ch != '\r') 390 | addch(ch); 391 | } 392 | } else if (pending_write_addr == serial_addr + 0x4 || 393 | pending_write_addr == serial_addr + 0x8 || 394 | pending_write_addr == serial_addr + 0x10 || 395 | pending_write_addr == serial_addr + 0x1c) { 396 | // ignored 397 | } else if (pending_write_addr == serial_addr + 0xc) { 398 | dlab = ((input >> 32) >> 7) & 1; 399 | } else if (pending_write_addr == emac_addr + 0x500) { 400 | // MDIO Setup Word (0x500) 401 | } else if (pending_write_addr == emac_addr + 0x504) { 402 | // MDIO Control Word (0x504) 403 | } else if (pending_write_addr == emac_addr + 0x700) { 404 | // Unicast Address Word 0 405 | } else if (pending_write_addr == emac_addr + 0x704) { 406 | // Unicast Address Word 1 407 | } else { 408 | printw("Unhandled mmio write to %lx\n", pending_write_addr); 409 | } 410 | 411 | pending_write_addr += 1L << pending_write_size; 412 | pending_write_len--; 413 | if (top->M_AXI_MMIO_wlast) { 414 | assert(pending_write_len == -1); 415 | pending_write_finished = true; 416 | } 417 | } 418 | 419 | top->M_AXI_MMIO_bvalid = 0; 420 | } else { 421 | // finishing 422 | top->M_AXI_MMIO_awready = 0; 423 | top->M_AXI_MMIO_wready = 0; 424 | top->M_AXI_MMIO_bvalid = 1; 425 | top->M_AXI_MMIO_bresp = 0; 426 | top->M_AXI_MMIO_bid = pending_write_id; 427 | 428 | // BREADY might be stale without eval() 429 | top->eval(); 430 | if (top->M_AXI_MMIO_bready) { 431 | pending_write = false; 432 | pending_write_finished = false; 433 | } 434 | } 435 | } 436 | 437 | // load file 438 | void load_file(const std::string &path, uint64_t addr = 0x80000000) { 439 | // load as bin 440 | FILE *fp = fopen(path.c_str(), "rb"); 441 | assert(fp); 442 | 443 | // read whole file and pad to multiples of mem_t 444 | fseek(fp, 0, SEEK_END); 445 | size_t size = ftell(fp); 446 | fseek(fp, 0, SEEK_SET); 447 | size_t padded_size = align(size + sizeof(mem_t) - 1); 448 | uint8_t *buffer = new uint8_t[padded_size]; 449 | memset(buffer, 0, padded_size); 450 | 451 | size_t offset = 0; 452 | while (!feof(fp)) { 453 | ssize_t read = fread(&buffer[offset], 1, size - offset, fp); 454 | if (read <= 0) { 455 | break; 456 | } 457 | offset += read; 458 | } 459 | 460 | for (int i = 0; i < padded_size; i += sizeof(mem_t)) { 461 | memory[addr + i] = *((mem_t *)&buffer[i]); 462 | } 463 | printw("> Loaded %ld bytes from BIN %s\n", size, path.c_str()); 464 | fclose(fp); 465 | delete[] buffer; 466 | } 467 | 468 | uint64_t get_time_us() { 469 | struct timeval tv = {}; 470 | gettimeofday(&tv, NULL); 471 | return tv.tv_sec * 1000000 + tv.tv_usec; 472 | } 473 | 474 | bool finished = false; 475 | 476 | void ctrlc_handler(int arg) { 477 | printw("Received Ctrl-C\n"); 478 | finished = true; 479 | } 480 | 481 | int main(int argc, char **argv) { 482 | // init ncurses 483 | initscr(); 484 | // enter no delay mode 485 | nodelay(stdscr, TRUE); 486 | // disable echo 487 | noecho(); 488 | // enable scrolling 489 | scrollok(stdscr, TRUE); 490 | 491 | Verilated::commandArgs(argc, argv); // Remember args 492 | bool trace = false; 493 | char opt; 494 | while ((opt = getopt(argc, argv, "t")) != -1) { 495 | switch (opt) { 496 | case 't': 497 | trace = true; 498 | break; 499 | default: /* '?' */ 500 | fprintf(stderr, "Usage: %s [-t] memory_content [memory_content2]\n", 501 | argv[0]); 502 | return 1; 503 | } 504 | } 505 | 506 | if (optind >= argc) { 507 | fprintf(stderr, "Usage: %s [-t] memory_content [memory_content2]\n", 508 | argv[0]); 509 | return 1; 510 | } 511 | 512 | load_file(argv[optind]); 513 | // load linux FIT image 514 | if (optind + 1 < argc) { 515 | load_file(argv[optind + 1], 0x80100000); 516 | } 517 | top = new Vtestbench_rocketchip; 518 | 519 | signal(SIGINT, ctrlc_handler); 520 | 521 | #if VM_TRACE // If verilator was invoked with --trace 522 | VerilatedVcdC *tfp = NULL; 523 | if (trace) { 524 | Verilated::traceEverOn(true); // Verilator must compute traced signals 525 | printw("> Enabling waves...\n"); 526 | tfp = new VerilatedVcdC; 527 | top->trace(tfp, 99); // Trace 99 levels of hierarchy 528 | tfp->open("dump.vcd"); // Open the dump file 529 | } 530 | #endif 531 | 532 | top->reset = 1; 533 | top->interrupts = 0; 534 | 535 | // init 536 | top->jtag_TCK = 1; 537 | top->jtag_TMS = 1; 538 | top->jtag_TDI = 1; 539 | 540 | printw("> Starting simulation!\n"); 541 | 542 | uint64_t begin = get_time_us(); 543 | uint64_t clocks = 0; 544 | while (!Verilated::gotFinish() && !finished) { 545 | if (sim_time > 1000) { 546 | top->reset = 0; // Deassert reset 547 | } 548 | if ((sim_time % 10) == 1) { 549 | clocks++; 550 | top->clock = 1; // Toggle clock 551 | } 552 | if ((sim_time % 10) == 6) { 553 | top->clock = 0; 554 | step_mem(); 555 | step_mmio(); 556 | } 557 | top->eval(); // Evaluate model 558 | #if VM_TRACE 559 | if (tfp) 560 | tfp->dump(sim_time); // Create waveform trace for this timestamp 561 | #endif 562 | sim_time++; // Time passes... 563 | } 564 | 565 | uint64_t elapsed_us = get_time_us() - begin; 566 | printw("> Simulation completed at time %ld\n", sim_time); 567 | printw("> Simulation speed %lf mcycle/s\n", 568 | (double)clocks * 1000000 / elapsed_us); 569 | 570 | // Run for 10 more clocks 571 | vluint64_t end_time = sim_time + 100; 572 | while (sim_time < end_time) { 573 | if ((sim_time % 10) == 1) { 574 | top->clock = 1; // Toggle clock 575 | } 576 | if ((sim_time % 10) == 6) { 577 | top->clock = 0; 578 | } 579 | top->eval(); // Evaluate model 580 | #if VM_TRACE 581 | if (tfp) 582 | tfp->dump(sim_time); // Create waveform trace for this timestamp 583 | #endif 584 | sim_time++; // Time passes... 585 | } 586 | 587 | #if VM_TRACE 588 | if (tfp) 589 | tfp->close(); 590 | #endif 591 | endwin(); 592 | } 593 | -------------------------------------------------------------------------------- /vpi.cfg: -------------------------------------------------------------------------------- 1 | # openocd config 2 | # jtag_vpi 3 | # for simulation 4 | adapter speed 10000 5 | adapter driver jtag_vpi 6 | set VPI_PORT 12345 7 | source [find interface/jtag_vpi.cfg] 8 | 9 | set _CHIPNAME riscv 10 | jtag newtap $_CHIPNAME cpu -irlen 5 11 | 12 | set _TARGETNAME $_CHIPNAME.cpu 13 | target create $_TARGETNAME riscv -chain-position $_TARGETNAME 14 | 15 | riscv set_reset_timeout_sec 120 16 | riscv set_command_timeout_sec 120 17 | 18 | init 19 | halt 20 | echo "Ready for Remote Connections" 21 | --------------------------------------------------------------------------------