├── .gitmodules ├── LICENSE ├── README.md ├── SIGCSE_2021_RISCV_Paper.pdf ├── SIGCSE_2021_RISCV_Slides.pptx ├── labs ├── lab1 │ ├── assignment │ │ ├── source │ │ │ ├── Makefile │ │ │ ├── tut_mod.v │ │ │ ├── tut_mod2.v │ │ │ ├── tut_synth.tcl │ │ │ └── tut_test.v │ │ └── tex │ │ │ ├── Makefile.lab1 │ │ │ ├── data-pane.png │ │ │ ├── eecs470lab1assignment.tex │ │ │ ├── mod-hier-pane.png │ │ │ ├── schematic-viewer.png │ │ │ ├── source-pane.png │ │ │ └── waveform-viewer.png │ └── slides │ │ ├── beamercolorthemewolverine.sty │ │ ├── beamerthemeLab.sty │ │ ├── eecs470lab1slides.tex │ │ └── verilog │ │ ├── and.v │ │ ├── and2.v │ │ ├── and4.v │ │ └── macro.v ├── lab2 │ ├── assignment │ │ ├── source │ │ │ ├── fa1.v │ │ │ ├── fa1_test.v │ │ │ ├── fa64.v │ │ │ └── fa64_test.v │ │ └── tex │ │ │ └── eecs470lab2assignment.tex │ └── slides │ │ ├── beamercolorthemewolverine.sty │ │ ├── beamerthemeLab.sty │ │ ├── eecs470lab2slides.tex │ │ ├── scripts │ │ ├── Makefile.example │ │ ├── Makefile.lab1 │ │ ├── Makefile.lab1.old │ │ ├── synth.tcl │ │ └── synth.tcl.old │ │ └── verilog │ │ ├── and.v │ │ ├── and2.v │ │ ├── and4.v │ │ └── macro.v ├── lab3 │ ├── assignment │ │ ├── source │ │ │ ├── part_a │ │ │ │ ├── Makefile │ │ │ │ ├── fsm_ab.tcl │ │ │ │ ├── fsm_ab.v │ │ │ │ └── test_ab.v │ │ │ └── part_b │ │ │ │ ├── Makefile │ │ │ │ ├── fsm_cd.tcl │ │ │ │ ├── fsm_cd.v │ │ │ │ ├── sys_defs.vh │ │ │ │ └── test_cd.v │ │ └── tex │ │ │ └── eecs470lab3assignment.tex │ └── slides │ │ ├── beamercolorthemewolverine.sty │ │ ├── beamerthemeLab.sty │ │ ├── eecs470lab3slides.tex │ │ ├── enum_dve.jpg │ │ ├── hierarchy.txt │ │ └── verilog │ │ └── fsm.v ├── lab4 │ ├── assignment │ │ ├── source │ │ │ ├── buggy1 │ │ │ │ ├── ISR.vg │ │ │ │ └── Makefile │ │ │ ├── buggy2 │ │ │ │ ├── ISR.vg │ │ │ │ └── Makefile │ │ │ ├── buggy3 │ │ │ │ ├── ISR.vg │ │ │ │ └── Makefile │ │ │ └── isr_test.v │ │ └── tex │ │ │ └── eecs470lab4assignment.tex │ ├── lab4_part2.pptx │ └── slides │ │ ├── beamercolorthemewolverine.sty │ │ ├── beamerthemeLab.sty │ │ ├── eecs470lab4slides.tex │ │ ├── example.txt │ │ ├── script.txt │ │ └── ssh-keygen.txt ├── lab5 │ ├── assignment │ │ └── tex │ │ │ ├── eecs470lab5assignment.tex │ │ │ └── scripts │ │ │ └── ground-truth-skeleton.sh │ └── slides │ │ ├── beamercolorthemewolverine.sty │ │ ├── beamerthemeLab.sty │ │ └── eecs470lab5slides.tex ├── lab6 │ ├── assignment │ │ ├── lab6 │ │ │ ├── Makefile │ │ │ ├── cam.tcl │ │ │ ├── cam.v │ │ │ ├── check.sh │ │ │ ├── sys_defs.vh │ │ │ ├── test.v │ │ │ └── top.tcl │ │ ├── solution │ │ │ └── cam.v │ │ ├── source │ │ │ ├── .restartSimSession.tcl.old │ │ │ ├── Makefile │ │ │ ├── cam.tcl │ │ │ ├── cam.v │ │ │ ├── check.sh │ │ │ ├── sys_defs.vh │ │ │ └── test.v │ │ └── tex │ │ │ └── eecs470lab6assignment.tex │ └── slides │ │ ├── .DS_Store │ │ ├── beamercolorthemewolverine.sty │ │ ├── beamerthemeLab.sty │ │ ├── eecs470lab6slides.tex │ │ ├── latch.png │ │ └── multiple_bits.png └── lab7 │ ├── beamercolorthemewolverine.sty │ ├── beamerthemeLab.sty │ └── eecs470lab7slides.tex └── projects ├── project1 ├── project1.pdf ├── source │ ├── And.v │ ├── Makefile │ ├── test.v │ ├── testAND.v │ └── testD.v └── tex │ ├── and.v │ ├── eecs470project1.tex │ └── submission.txt ├── project2 ├── project2.pdf ├── source │ ├── Makefile │ ├── mult.tcl │ ├── mult_stage.tcl │ ├── mult_stage.v │ ├── mult_test.v │ └── pipe_mult.v └── tex │ ├── eecs470project2.tex │ └── submission.txt ├── project3 ├── project3.pdf └── tex │ └── eecs470project3.tex └── project4 ├── project4.pdf └── tex └── exception_spec.tex /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "projects/project-v-open"] 2 | path = projects/project-v-open 3 | url = git@github.com:jieltan/project-v-open.git 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Jielun Tan 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## Overview 2 | 3 | This is the repository associated with our SIGCSE '21 paper "RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA". 4 | 5 | * What's in the repo: 6 | * the paper and slides (Creative Commons, woohoo!) 7 | * current (as of 2021) project and lab assignments in PDF and LaTeX 8 | * a pointer to the repo containing the in-order RISC-V CPU developed for the course 9 | * link to the current course web page 10 | 11 | * What's not in the repo: 12 | * An out-of-order RISC-V CPU (more on this below) 13 | * Project/lab solutions 14 | 15 | ### Abstract 16 | 17 | *"We describe our experience teaching an undergraduate capstone (and elective graduate course) in computer architecture with a semester-long project in which teams of five students design and implement an out-of-order (OoO) pipelined processor core using the open-source RISC-V instruction set. The course content includes OoO scheduling algorithms for instructions to exploit instruction-level parallelism (ILP), example microarchitectures, caching, prefetching, and virtual memory. The labs and projects help students gain proficiency with the SystemVerilog language.* 18 | 19 | *Students use the concepts learned in class to design processors with the goals of achieving correctness and high performance for a suite of test programs representative of different data structures and algorithms. Using RISC-V enables students to validate and benchmark their designs by compiling test programs using GCC with a custom linker. By collaborating as a team, students learn how to write and debug a large code base over the two-month project.* 20 | 21 | *We explain the project content and process in detail, identify the challenges involved for students and the necessary instructor support, and share statistics and student feedback about the project. We have open-sourced our lab and project materials to enable others to teach similar courses."* 22 | 23 | ## Some words about access and distribution 24 | Our paper and CPU design are released under the Creative Commons license because we want other people to be able to reuse our work! Please feel free to copy, in whole or in part, anything from the CPU design or paper for use in your own non-commercial course or project. All we ask is that you attribute the original credit to us (this can be as simple as a comment in the HDL). 25 | 26 | As of this writing most course documents are available on the course web site. However we do not have the ability to release these documents under the Creative Commons license because we do not have the permission of all the authors. 27 | 28 | ## Course Web Site 29 | 30 | As of 2021, most (all?) assignments/slides/starter code for the course is available at: 31 | http://www.eecs.umich.edu/eecs/courses/eecs470/?page=home.php 32 | 33 | If you can't find what you're looking for, email us and we'll try to help. 34 | 35 | ## FAQ 36 | Q: **Wait, I don't see an out-of-order CPU here. Isn't that the whole point of this class?** 37 | 38 | A: The students build their OoO design from the in-order CPU design we provide. We have not publicly released a fully-functional OoO design because we want students to create their own design. If you'd like to see an example of a completed project, please get in touch with us by email and we would be happy to send you the code. 39 | 40 | Q: **How do I build the project?** 41 | 42 | Currently you will need to replace the build commands in the Makefile in all the projects with your technology library and simulator to properly compile and simulate 43 | 44 | 45 | -------------------------------------------------------------------------------- /SIGCSE_2021_RISCV_Paper.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/SIGCSE_2021_RISCV_Paper.pdf -------------------------------------------------------------------------------- /SIGCSE_2021_RISCV_Slides.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/SIGCSE_2021_RISCV_Slides.pptx -------------------------------------------------------------------------------- /labs/lab1/assignment/source/Makefile: -------------------------------------------------------------------------------- 1 | # make <- runs simv (after compiling simv if needed) 2 | # make simv <- compiles simv without running 3 | # make dve <- runs GUI debugger (after compiling it if needed) 4 | # make syn <- runs syn_simv (after synthesizing if needed then 5 | # compiling syn_simv if needed) 6 | # make clean <- remove files created during compilations (but not synthesis) 7 | # make nuke <- remove all files created during compilation and synthesis 8 | # 9 | # To compile additional files, add them to the TESTBENCH or SIMFILES as needed 10 | # Every .vg file will need its own rule and one or more synthesis scripts 11 | # The information contained here (in the rules for those vg files) will be 12 | # similar to the information in those scripts but that seems hard to avoid. 13 | # 14 | 15 | VCS = SW_VCS=2017.12-SP2-1 vcs -sverilog +vc -Mupdate -line -full64 +define+ 16 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 17 | 18 | all: simv 19 | ./simv | tee program.out 20 | 21 | ##### 22 | # Modify starting here 23 | ##### 24 | 25 | TESTBENCH = tut_test.v 26 | SIMFILES = tut_mod.v 27 | SYNFILES = two_bit_pred.vg 28 | 29 | 30 | ##### 31 | # Should be no need to modify after here 32 | ##### 33 | simv: $(SIMFILES) $(TESTBENCH) 34 | $(VCS) $(TESTBENCH) $(SIMFILES) -o simv 35 | 36 | dve: $(SIMFILES) $(TESTBENCH) 37 | $(VCS) +memcbk $(TESTBENCH) $(SIMFILES) -o dve -R -gui 38 | 39 | .PHONY: dve 40 | 41 | syn_simv: $(SYNFILES) $(TESTBENCH) 42 | $(VCS) $(TESTBENCH) $(SYNFILES) $(LIB) -o syn_simv 43 | 44 | syn: syn_simv 45 | ./syn_simv | tee syn_program.out 46 | 47 | clean: 48 | rm -rvf simv *.daidir csrc vcs.key program.out \ 49 | syn_simv syn_simv.daidir syn_program.out \ 50 | dve *.vpd *.vcd *.dump ucli.key 51 | 52 | nuke: clean 53 | rm -rvf *.vg *.rep *.db *.chk *.log *.out DVEfiles/ 54 | -------------------------------------------------------------------------------- /labs/lab1/assignment/source/tut_mod.v: -------------------------------------------------------------------------------- 1 | module two_bit_pred( 2 | input clock, reset, taken, transition, 3 | output prediction); 4 | 5 | 6 | logic [1:0] state; 7 | loggic [1:0] next_state; 8 | 9 | assign prediction = state[1]; 10 | 11 | always_comb begin 12 | case(state) 13 | 2'b01, 2'b10 : next_state = taken ? 2'b11 : 2'b00; 14 | 2'b00 : next_state = taken ? 2'b01 : 2'b00; 15 | 2'b11 : next_state = taken ? 2'b11 : 2'b10; 16 | endcase 17 | end 18 | 19 | always_ff @(posedge clock) begin 20 | if(reset) 21 | state <= #1 2'b01; 22 | else if(transition) 23 | state <= #1 next_state; 24 | end 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /labs/lab1/assignment/source/tut_mod2.v: -------------------------------------------------------------------------------- 1 | module two_bit_pred( 2 | input clock, reset, taken, transition, 3 | output prediction); 4 | 5 | logic loop1, loop2; 6 | 7 | logic [1:0] state; 8 | logic [1:0] next_state; 9 | 10 | assign prediction = state[1]; 11 | assign loop1 = (taken & loop2) ? 0 : 1; 12 | assign loop2 = (taken & loop1) ? 1 : 0; 13 | 14 | always_comb begin 15 | case(state) 16 | 2'b01, 2'b10 : next_state = taken ? 2'b11 : 2'b00; 17 | 2'b00 : next_state = taken ? 2'b01 : 2'b00; 18 | 2'b11 : next_state = taken ? 2'b11 : 2'b10; 19 | endcase 20 | end 21 | 22 | always_ff @(posedge clock) begin 23 | if(reset) 24 | state <= #1 2'b01; 25 | else if(transition) 26 | state <= #1 next_state; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /labs/lab1/assignment/source/tut_synth.tcl: -------------------------------------------------------------------------------- 1 | #/***********************************************************/ 2 | #/* FILE : tut_synth.tcl */ 3 | #/* Description : Default Synopsys Design Compiler Script */ 4 | #/* Usage : dc_shell -tcl_mode -f default.tcl */ 5 | #/* You'll need to minimally set design_name & read files */ 6 | #/***********************************************************/ 7 | 8 | #/***********************************************************/ 9 | #/* The following five lines must be updated for every */ 10 | #/* new design */ 11 | #/***********************************************************/ 12 | 13 | read_file -f sverilog [list "tut_mod.v"] 14 | set design_name two_bit_pred 15 | set clock_name clock 16 | set reset_name reset 17 | set CLK_PERIOD 10 18 | 19 | 20 | 21 | 22 | 23 | #/***********************************************************/ 24 | #/* The rest of this file may be left alone for most small */ 25 | #/* to moderate sized designs. You may need to alter it */ 26 | #/* when synthesizing your final project. */ 27 | #/***********************************************************/ 28 | set SYN_DIR ./ 29 | set search_path "/afs/umich.edu/class/eecs470/lib/synopsys/" 30 | set target_library "lec25dscc25_TT.db" 31 | set link_library [concat "*" $target_library] 32 | 33 | #/***********************************************************/ 34 | #/* Set some flags for optimisation */ 35 | 36 | set compile_top_all_paths "true" 37 | set auto_wire_load_selection "false" 38 | 39 | 40 | #/***********************************************************/ 41 | #/* Clk Periods/uncertainty/transition */ 42 | 43 | set CLK_TRANSITION 0.1 44 | set CLK_UNCERTAINTY 0.1 45 | set CLK_LATENCY 0.1 46 | 47 | #/* Input/output Delay values */ 48 | set AVG_INPUT_DELAY 0.1 49 | set AVG_OUTPUT_DELAY 0.1 50 | 51 | #/* Critical Range (ns) */ 52 | set CRIT_RANGE 1.0 53 | 54 | #/***********************************************************/ 55 | #/* Design Constrains: Not all used */ 56 | set MAX_TRANSITION 1.0 57 | set FAST_TRANSITION 0.1 58 | set MAX_FANOUT 32 59 | set MID_FANOUT 8 60 | set LOW_FANOUT 1 61 | set HIGH_DRIVE 0 62 | set HIGH_LOAD 1.0 63 | set AVG_LOAD 0.1 64 | set AVG_FANOUT_LOAD 10 65 | 66 | #/***********************************************************/ 67 | #/*BASIC_INPUT = cb18os120_tsmc_max/nd02d1/A1 68 | #BASIC_OUTPUT = cb18os120_tsmc_max/nd02d1/ZN*/ 69 | 70 | set DRIVING_CELL dffacs1 71 | 72 | #/* DONT_USE_LIST = { } */ 73 | 74 | #/*************operation cons**************/ 75 | #/*OP_WCASE = WCCOM; 76 | #OP_BCASE = BCCOM;*/ 77 | set WIRE_LOAD "tsmcwire" 78 | set LOGICLIB lec25dscc25_TT 79 | #/*****************************/ 80 | 81 | #/* Sourcing the file that sets the Search path and the libraries(target,link) */ 82 | 83 | set sys_clk $clock_name 84 | 85 | set netlist_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".vg"] 86 | set ddc_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".ddc"] 87 | set rep_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".rep"] 88 | set dc_shell_status [ set chk_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".chk"] ] 89 | 90 | #/* if we didnt find errors at this point, run */ 91 | if { $dc_shell_status != [list] } { 92 | current_design $design_name 93 | link 94 | set_wire_load_model -name $WIRE_LOAD -lib $LOGICLIB $design_name 95 | set_wire_load_mode top 96 | set_fix_multiple_port_nets -outputs -buffer_constants 97 | create_clock -period $CLK_PERIOD -name $sys_clk [find port $sys_clk] 98 | set_clock_uncertainty $CLK_UNCERTAINTY $sys_clk 99 | set_fix_hold $sys_clk 100 | group_path -from [all_inputs] -name input_grp 101 | group_path -to [all_outputs] -name output_grp 102 | set_driving_cell -lib_cell $DRIVING_CELL [all_inputs] 103 | remove_driving_cell [find port $sys_clk] 104 | set_fanout_load $AVG_FANOUT_LOAD [all_outputs] 105 | set_load $AVG_LOAD [all_outputs] 106 | set_input_delay $AVG_INPUT_DELAY -clock $sys_clk [all_inputs] 107 | remove_input_delay -clock $sys_clk [find port $sys_clk] 108 | set_output_delay $AVG_OUTPUT_DELAY -clock $sys_clk [all_outputs] 109 | set_dont_touch $reset_name 110 | set_resistance 0 $reset_name 111 | set_drive 0 $reset_name 112 | set_critical_range $CRIT_RANGE [current_design] 113 | set_max_delay $CLK_PERIOD [all_outputs] 114 | set MAX_FANOUT $MAX_FANOUT 115 | set MAX_TRANSITION $MAX_TRANSITION 116 | uniquify 117 | ungroup -all -flatten 118 | redirect $chk_file { check_design } 119 | compile -map_effort high 120 | write -hier -format verilog -output $netlist_file $design_name 121 | write -hier -format ddc -output $ddc_file $design_name 122 | redirect $rep_file { report_design -nosplit } 123 | redirect -append $rep_file { report_area } 124 | redirect -append $rep_file { report_timing -max_paths 2 -input_pins -nets -transition_time -nosplit } 125 | redirect -append $rep_file { report_constraint -max_delay -verbose -nosplit } 126 | remove_design -all 127 | read_file -format verilog $netlist_file 128 | current_design $design_name 129 | redirect -append $rep_file { report_reference -nosplit } 130 | quit 131 | } else { 132 | quit 133 | } 134 | 135 | 136 | -------------------------------------------------------------------------------- /labs/lab1/assignment/source/tut_test.v: -------------------------------------------------------------------------------- 1 | module testbench; 2 | 3 | logic clock, reset, taken, transition; 4 | logic [15:0] bigsignal; 5 | logic prediction; 6 | 7 | two_bit_pred tbp(.clock(clock), .reset(reset), .taken(taekn), 8 | .transition(transition), .prediction(prediction)); 9 | 10 | always begin 11 | #5; 12 | clock=~clock; 13 | end 14 | 15 | initial begin 16 | 17 | $monitor("Time:%4.0f clock:%b reset:%b taken:%b transition:%b prediction:%b", 18 | $time, clock, reset, taken, transition, prediction); 19 | 20 | bigsignal = 16'hdead; 21 | clock = 1'b0; 22 | reset = 1'b1; 23 | taken = 1'b0; 24 | transition = 1'b1; 25 | 26 | @(negedge clock); 27 | @(negedge clock); 28 | reset = 1'b0; 29 | @(negedge clock); 30 | taken = 1'b1; 31 | @(negedge clock); 32 | transition = 1'b0; 33 | bigsignal = 16'hbeef; 34 | @(negedge clock); 35 | @(negedge clock); 36 | transition = 1'b1; 37 | #3 transition = 1'b0; 38 | @(negedge clock); 39 | transition = 1'b1; 40 | @(negedge clock); 41 | taken = 1'b0; 42 | @(negedge clock); 43 | @(negedge clock); 44 | $finish; 45 | 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /labs/lab1/assignment/tex/Makefile.lab1: -------------------------------------------------------------------------------- 1 | ../../source/Makefile -------------------------------------------------------------------------------- /labs/lab1/assignment/tex/data-pane.png: -------------------------------------------------------------------------------- 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See the file doc/licenses/LICENSE for more details. 9 | 10 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/color/beamercolorthemewolverine.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 11 | 12 | \mode 13 | 14 | \definecolor{darkblue}{rgb}{0,0,0.8} 15 | 16 | \setbeamercolor{alerted text}{fg=darkblue!80!yellow} 17 | \setbeamercolor*{palette primary}{fg=darkblue!60!black,bg=yellow!85!orange} 18 | \setbeamercolor*{palette secondary}{fg=darkblue!60!black,bg=yellow!85!orange} 19 | %\setbeamercolor*{palette secondary}{fg=darkblue!70!black,bg=yellow!60!orange} 20 | \setbeamercolor*{palette tertiary}{bg=darkblue!80!black,fg=yellow!50!orange} 21 | \setbeamercolor*{palette quaternary}{fg=darkblue,bg=yellow!20!orange} 22 | 23 | \setbeamercolor*{sidebar}{fg=darkblue,bg=orange!75!white} 24 | 25 | \setbeamercolor*{palette sidebar primary}{fg=darkblue!10!black} 26 | \setbeamercolor*{palette sidebar secondary}{fg=white} 27 | \setbeamercolor*{palette sidebar tertiary}{fg=darkblue!50!black} 28 | \setbeamercolor*{palette sidebar quaternary}{fg=yellow!10!orange} 29 | 30 | \setbeamercolor*{titlelike}{parent=palette primary} 31 | \setbeamercolor{frametitle}{bg=yellow!90!orange} 32 | \setbeamercolor{frametitle right}{bg=yellow!60!orange} 33 | 34 | \setbeamercolor*{separation line}{} 35 | \setbeamercolor*{fine separation line}{} 36 | 37 | \mode 38 | 39 | -------------------------------------------------------------------------------- /labs/lab1/slides/beamerthemeLab.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2014 William Cunningham 2 | % For use in U of M EECS 470 - Computer Architecture Labs 3 | % 4 | % This file may be distributed and/or modified 5 | % 6 | % 1. under the LaTeX Project Public License and/or 7 | % 2. under the GNU Public License. 8 | % 9 | % See the file doc/licenses/LICENSE for more details. 10 | 11 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/theme/beamerthemedLabs.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 12 | 13 | 14 | \mode 15 | 16 | \usefonttheme{default} 17 | \usecolortheme{wolverine} 18 | \useinnertheme{default} 19 | \useoutertheme{infolines} 20 | 21 | \mode 22 | 23 | -------------------------------------------------------------------------------- /labs/lab1/slides/verilog/and.v: -------------------------------------------------------------------------------- 1 | module and2( 2 | input [1:0] a, 3 | output logic x 4 | ); 5 | assign x=a[0] & a[1]; 6 | endmodule 7 | 8 | module and4( 9 | input [3:0] in, 10 | output logic out 11 | ); 12 | logic [1:0] tmp; 13 | and2 left(.a(in[1:0]),.x(tmp[0])); 14 | and2 right(.a(in[3:2]),.x(tmp[1])); 15 | and2 top(.a(tmp),.x(out)); 16 | endmodule 17 | -------------------------------------------------------------------------------- /labs/lab1/slides/verilog/and2.v: -------------------------------------------------------------------------------- 1 | `ifndef __AND_2_V__ 2 | `define __AND_2_V__ 3 | 4 | module and2( 5 | input [1:0] a, 6 | output logic x 7 | ); 8 | assign x=a[0] & a[1]; 9 | endmodule 10 | 11 | `endif 12 | -------------------------------------------------------------------------------- /labs/lab1/slides/verilog/and4.v: -------------------------------------------------------------------------------- 1 | `include "and2.v" 2 | module and4( 3 | input [3:0] in, 4 | output logic out 5 | ); 6 | logic [1:0] tmp; 7 | and2 left(.a(in[1:0]),.x(tmp[0])); 8 | and2 right(.a(in[3:2]),.x(tmp[1])); 9 | and2 top(.a(tmp),.x(out)); 10 | endmodule 11 | -------------------------------------------------------------------------------- /labs/lab1/slides/verilog/macro.v: -------------------------------------------------------------------------------- 1 | `define DEBUG 2 | `define LOCKED 1'b0 3 | `define UNLOCKED 1'b1 4 | module turnstile( 5 | input coin, push, 6 | input clock, reset 7 | `ifdef DEBUG 8 | ,output logic state 9 | `endif 10 | ); 11 | `ifndef DEBUG 12 | logic state; 13 | `endif 14 | always_comb begin 15 | next_state=state; 16 | if (state==`LOCKED&&coin) next_state = `UNLOCKED; 17 | if (state==`UNLOCKED&&push) next_state = `LOCKED; 18 | end 19 | always_ff @(posedge clock) begin 20 | if (reset) state <= #1 `LOCKED; 21 | else state <= #1 next_state; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /labs/lab2/assignment/source/fa1.v: -------------------------------------------------------------------------------- 1 | module full_adder_1bit( A, B, carry_in, S, carry_out ); 2 | input A, B, carry_in; 3 | output S, carry_out; 4 | logic w1, w2, w3, w4; 5 | 6 | assign w2 = B & carry_in; 7 | assign w1 = B ^ carry_in; 8 | assign S = A ^ w1; 9 | assign w3 = B & A; 10 | assign w4 = carry_in & B; 11 | assign carry_out = (w2 | w3 | w4); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /labs/lab2/assignment/source/fa1_test.v: -------------------------------------------------------------------------------- 1 | //TESTBENCH FOR 1-BIT FULL ADDER 2 | //Class: EECS470 3 | //Specific: Lab 2 4 | //Description: This file contains the testbench for a 1-bit full adder. 5 | 6 | module testbench; 7 | 8 | // I/O of the full_adder_1bit module 9 | logic A, B, Cin; 10 | logic Sum, Cout; 11 | 12 | logic clock; 13 | logic [1:0] GOLDEN_SUM; 14 | logic correct; 15 | 16 | // Don't forget to wire in your signals to the module instantiation here! 17 | full_adder_1bit DUT( 18 | .A(), 19 | .B(), 20 | .carry_in(), 21 | .S(), 22 | .carry_out() 23 | ); 24 | 25 | // Golden output 26 | assign GOLDEN_SUM = A + B + Cin; 27 | 28 | // Comparison between the output of the module and golden output 29 | assign correct = ( Sum === GOLDEN_SUM[0] ) && ( Cout === GOLDEN_SUM[1] ); 30 | 31 | always@(correct) 32 | begin 33 | #2 34 | if(!correct) 35 | begin 36 | //Note that nothing will be displayed unless your adder produces 37 | // incorrect output 38 | $display("@@@ Incorrect at time %4.0f", $time); 39 | $display("@@@ Time:%4.0f clock:%b A:%h B:%h CIN:%b SUM:%h COUT:%b", 40 | $time, clock, A, B, Cin, Sum, Cout); 41 | $display("@@@ expected sum=%b cout=%b", GOLDEN_SUM[0],GOLDEN_SUM[1] ); 42 | $finish; 43 | end 44 | end 45 | 46 | //--- Clock Generation Block ---// 47 | always 48 | begin 49 | #5 clock=~clock; 50 | end 51 | 52 | //--- Value Setting Block ---// 53 | initial 54 | begin 55 | clock = 0; 56 | A = 0; 57 | B = 0; 58 | Cin = 0; 59 | 60 | // Remember that monitor statements change whenever *any argument* changes 61 | //$monitor("Time:%4.0f clock:%b A:%h B:%h CIN:%b SUM:%h COUT:%b", $time, clock, A, B, Cin, Sum, Cout); 62 | 63 | // How many unique inputs are possible for a 1-bit full adder? 64 | // Would it be better to change them all by hand or to use some kind of test 65 | // bench flow control? 66 | 67 | @(negedge clock) 68 | @(negedge clock) 69 | @(negedge clock) 70 | $finish; 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /labs/lab2/assignment/source/fa64.v: -------------------------------------------------------------------------------- 1 | module full_adder_64bit( A, B, carry_in, S, carry_out ); 2 | input [63:0] A, B; 3 | input carry_in; 4 | output [63:0] S; 5 | output carry_out; 6 | 7 | logic [63:0] S; 8 | logic carry_out; 9 | 10 | // Implement a 64-bit adder using array instantiated 1-bit adders 11 | // ASSUME: bit 63 of 63:0 is the MSB 12 | 13 | // ----FILL IN HERE---- 14 | 15 | // ---------------------- 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /labs/lab2/assignment/source/fa64_test.v: -------------------------------------------------------------------------------- 1 | //TESTBENCH FOR 64 BIT ADDER 2 | //Class: EECS470 3 | //Specific: Lab 2 4 | //Description: This file contains the testbench for the 64-bit adder. 5 | 6 | 7 | // Note: This testbench is heavily commented for your benefit, please 8 | // read through and understand _what_ it is doing 9 | 10 | // The testbench itself is a module, so declare it as such 11 | module testbench; 12 | 13 | //MODULE PARAMETERS: 14 | parameter MAX_64BIT_NUM = 64'hFFFF_FFFF_FFFF_FFFF; 15 | 16 | // We need to define inputs and output for the module we wish to test. 17 | // In general, inputs should be registers (since a register is a physical 18 | // device that can hold state and can be wired from) and outputs should 19 | // be wires (since we only need to read the value of the output, we have 20 | // no desire or need to latch it) 21 | logic [63:0] A,B; 22 | logic [63:0] SUM; 23 | logic C_IN; 24 | logic C_OUT; 25 | 26 | // Strictly speaking, this is an asynchronous circuit, and thus we do not 27 | // need a clock. We'll use one to delimit test cases, as it makes looking 28 | // at the output much easier. 29 | logic clock; 30 | 31 | // Need a number? It's a testbench, we can do that! Conceptually these are 32 | // much more like variables from C, and do not necessarily correlate to any 33 | // physical hardware (thus they can only be used in testbenches) 34 | integer /*[63:0]*/ i,j; 35 | 36 | 37 | 38 | // Now we declare an instance of the module we'd like to test, in this case 39 | // the 64-bit full adder. We also wire in the signals declared above. 40 | full_adder_64bit fa_test_64( 41 | .A(A), 42 | .B(B), 43 | .carry_in(C_IN), 44 | .S(SUM), 45 | .carry_out(C_OUT) 46 | ); 47 | 48 | 49 | 50 | // "tasks" are verilog-speak for functions. These are really useful and help 51 | // to save on a lot of repeated / duplicated work. 52 | task exit_on_error; 53 | input [63:0] A, B, SUM; 54 | input C_IN, C_OUT; 55 | begin 56 | $display("@@@ Incorrect at time %4.0f", $time); 57 | $display("@@@ Time:%4.0f clock:%b A:%h B:%h CIN:%b SUM:%h COUT:%b", $time, clock, A, B, C_IN, SUM, C_OUT); 58 | $display("@@@ expected sum=%b", (A+B+C_IN) ); 59 | $finish; 60 | end 61 | endtask 62 | 63 | task compare_correct_sum; 64 | input [63:0] A, B, SUM; 65 | input C_IN, C_OUT; 66 | begin 67 | // Check the answer... 68 | if( SUM == (A+B+C_IN) ) 69 | begin 70 | // "empty" cases are legal, since the begin/end 71 | // block is consuming the true if-branch 72 | end else begin 73 | exit_on_error( A, B, SUM, C_IN, C_OUT ); 74 | end 75 | 76 | // What doesn't this function test that it probably should? 77 | end 78 | endtask 79 | 80 | 81 | 82 | 83 | 84 | // Set up the clock to tick, notice that this block inverts clock every 5 ticks, 85 | // so the actual period of the clock is 10, not 5. 86 | always begin 87 | #5; 88 | clock=~clock; 89 | end 90 | 91 | 92 | 93 | // Start the "real" testbench here. Initial is the beginning of simulated time. 94 | initial begin 95 | 96 | // Monitors can be really useful, but for larger testbenches, they can 97 | // dump a huge amount of text to the screen. 98 | 99 | // Conceptually a monitor is a "magic" printf that will print itself 100 | // any time one of the signals changes. 101 | 102 | // Try uncommenting this monitor once and running the testbench... 103 | //$monitor("Time:%4.0f clock:%b A:%h B:%h CIN:%b SUM:%h COUT:%b", $time, clock, A, B, C_IN, SUM, C_OUT); 104 | 105 | 106 | 107 | // Recall that verilog has an "unknown" state (x) which every signal 108 | // starts at. In practice, most internal registers will get set by a 109 | // reset signal and you will only need to specify testbench signals here 110 | A = 64'd0; 111 | B = 64'd0; 112 | C_IN = 0; 113 | 114 | // Don't forget to initialize the clock! Otherwise that always block 115 | // above will just keep inverting "x" to "x". 116 | clock = 0; 117 | 118 | $display("STARTING TESTBENCH!"); 119 | 120 | // Finally, we can get to actually testing things! 121 | // (Remember you can use non-synthesizable Verilog in testbenches) 122 | 123 | // ------------------------------------------------------------------------------------------------------------ 124 | // Here, we present a method to test every possible input 125 | @(negedge clock); 126 | // For every input A, 0..2^64-1 127 | for (i=0; i <= 64'hFFFF_FFFF_FFFF_FFFF; i=i+1) begin 128 | // For every input B, 0..2^64-1 129 | for (j=0; j <= 64'hFFFF_FFFF_FFFF_FFFF ; j=j+1) begin 130 | // Set the inputs 131 | A = i; 132 | B = j; 133 | C_IN = 0; 134 | 135 | // Since there's no clock, we have to add a delay 136 | // to allow signals to propagate 137 | #1 138 | 139 | // And check the result (aren't tasks great?) 140 | compare_correct_sum(A, B, SUM, C_IN, C_OUT); 141 | @(negedge clock); 142 | 143 | // And for the other carry 144 | C_IN = 1; 145 | #1 146 | compare_correct_sum(A, B, SUM, C_IN, C_OUT); 147 | @(negedge clock); 148 | end 149 | 150 | // How long will it take for this line to print? 151 | // How many times does it have to print? 152 | $display("Finished one inner loop"); 153 | end 154 | 155 | // ------------------------------------------------------------------------------------------------------------ 156 | // If we wish to test some specific cases instead... 157 | // Usually used for corner cases testing 158 | 159 | // Test 1 160 | @(negedge clock); 161 | A = 0; 162 | B = 0; 163 | C_IN = 0; 164 | #1 165 | compare_correct_sum(A, B, SUM, C_IN, C_OUT); 166 | 167 | 168 | // Test 2 169 | @(negedge clock); 170 | A = 0; 171 | B = 0; 172 | C_IN = 1; 173 | #1 174 | compare_correct_sum(A, B, SUM, C_IN, C_OUT); 175 | 176 | 177 | 178 | // ------------------------------------------------------------------------------------------------------------ 179 | // Or, we could throw probability at the problem... 180 | 181 | // Random Tests 182 | @(negedge clock); 183 | for (i=0; i <= 99; i=i+1) begin 184 | for (j=0; j <= 99 ; j=j+1) begin 185 | A = {$random,$random}; // What's up with this syntax? 186 | B = {$random,$random}; 187 | #1 188 | compare_correct_sum(A, B, SUM, C_IN, C_OUT); 189 | @(negedge clock); 190 | end 191 | end 192 | 193 | 194 | // DON'T FORGET TO FINISH THE SIMULATION 195 | $display("\nENDING TESTBENCH: SUCCESS!\n"); 196 | $finish; 197 | 198 | end 199 | 200 | endmodule 201 | 202 | -------------------------------------------------------------------------------- /labs/lab2/assignment/tex/eecs470lab2assignment.tex: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/labs/lab2/assignment/tex/eecs470lab2assignment.tex -------------------------------------------------------------------------------- /labs/lab2/slides/beamercolorthemewolverine.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2004 by Madhusudan Singh 2 | % 3 | % This file may be distributed and/or modified 4 | % 5 | % 1. under the LaTeX Project Public License and/or 6 | % 2. under the GNU Public License. 7 | % 8 | % See the file doc/licenses/LICENSE for more details. 9 | 10 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/color/beamercolorthemewolverine.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 11 | 12 | \mode 13 | 14 | \definecolor{darkblue}{rgb}{0,0,0.8} 15 | 16 | \setbeamercolor{alerted text}{fg=darkblue!80!yellow} 17 | \setbeamercolor*{palette primary}{fg=darkblue!60!black,bg=yellow!85!orange} 18 | \setbeamercolor*{palette secondary}{fg=darkblue!60!black,bg=yellow!85!orange} 19 | %\setbeamercolor*{palette secondary}{fg=darkblue!70!black,bg=yellow!60!orange} 20 | \setbeamercolor*{palette tertiary}{bg=darkblue!80!black,fg=yellow!50!orange} 21 | \setbeamercolor*{palette quaternary}{fg=darkblue,bg=yellow!20!orange} 22 | 23 | \setbeamercolor*{sidebar}{fg=darkblue,bg=orange!75!white} 24 | 25 | \setbeamercolor*{palette sidebar primary}{fg=darkblue!10!black} 26 | \setbeamercolor*{palette sidebar secondary}{fg=white} 27 | \setbeamercolor*{palette sidebar tertiary}{fg=darkblue!50!black} 28 | \setbeamercolor*{palette sidebar quaternary}{fg=yellow!10!orange} 29 | 30 | \setbeamercolor*{titlelike}{parent=palette primary} 31 | \setbeamercolor{frametitle}{bg=yellow!90!orange} 32 | \setbeamercolor{frametitle right}{bg=yellow!60!orange} 33 | 34 | \setbeamercolor*{separation line}{} 35 | \setbeamercolor*{fine separation line}{} 36 | 37 | \mode 38 | 39 | -------------------------------------------------------------------------------- /labs/lab2/slides/beamerthemeLab.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2014 William Cunningham 2 | % For use in U of M EECS 470 - Computer Architecture Labs 3 | % 4 | % This file may be distributed and/or modified 5 | % 6 | % 1. under the LaTeX Project Public License and/or 7 | % 2. under the GNU Public License. 8 | % 9 | % See the file doc/licenses/LICENSE for more details. 10 | 11 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/theme/beamerthemedLabs.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 12 | 13 | 14 | \mode 15 | 16 | \usefonttheme{default} 17 | \usecolortheme{wolverine} 18 | \useinnertheme{default} 19 | \useoutertheme{infolines} 20 | 21 | \mode 22 | 23 | -------------------------------------------------------------------------------- /labs/lab2/slides/scripts/Makefile.example: -------------------------------------------------------------------------------- 1 | target: dep1 dep2 ... 2 | command1 3 | command2 4 | -------------------------------------------------------------------------------- /labs/lab2/slides/scripts/Makefile.lab1: -------------------------------------------------------------------------------- 1 | ../../../lab1/assignment/source/Makefile -------------------------------------------------------------------------------- /labs/lab2/slides/scripts/Makefile.lab1.old: -------------------------------------------------------------------------------- 1 | # make <- runs simv (after compiling simv if needed) 2 | # make simv <- runs simv (after compiling simv if needed) 3 | # make dve <- runs GUI debugger (after compiling it if needed) 4 | # make syn <- runs syn_simv (after synthesizing if needed then 5 | # compiling synsimv if needed) 6 | # make clean <- remove files created during compilations (but not synthesis) 7 | # make nuke <- remove all files created during compilation and synthesis 8 | # 9 | # To compile additional files, add them to the TESTBENCH or SIMFILES as needed 10 | # Every .vg file will need its own rule and one or more synthesis scripts 11 | # The information contained here (in the rules for those vg files) will be 12 | # similar to the information in those scripts but that seems hard to avoid. 13 | # 14 | 15 | # added "SW_VCS=2011.03 and "-full64" option -- awdeorio fall 2011 16 | # replaced "+v2k" with "-sverilog" option 17 | # and removed deprecated Virsim references -- jbbeau fall 2013 18 | # updated library path name -- jbbeau fall 2013 19 | VCS = SW_VCS=2011.03 vcs -sverilog +vc -Mupdate -line -full64 20 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 21 | 22 | all: simv 23 | 24 | ##### 25 | # Modify starting here 26 | ##### 27 | 28 | TESTBENCH = tut_test.v 29 | SIMFILES = tut_mod.v 30 | SYNFILES = two_bit_pred.vg 31 | 32 | 33 | ##### 34 | # Should be no need to modify after here 35 | ##### 36 | simv: $(SIMFILES) $(TESTBENCH) 37 | $(VCS) $(TESTBENCH) $(SIMFILES) -o simv -R | tee program.out 38 | 39 | # updated interactive debugger "DVE", using the latest version of VCS 40 | # awdeorio fall 2011 41 | dve: $(SIMFILES) $(TESTBENCH) 42 | $(VCS) +memcbk $(TESTBENCH) $(SIMFILES) -o dve -R -gui 43 | 44 | .PHONY: dve 45 | 46 | syn_simv: $(SYNFILES) $(TESTBENCH) 47 | $(VCS) $(TESTBENCH) $(SYNFILES) $(LIB) -o syn_simv | tee synth.out 48 | 49 | syn: syn_simv 50 | ./syn_simv | tee syn_program.out 51 | 52 | clean: 53 | rm -rvf simv *.daidir csrc vcs.key program.out \ 54 | syn_simv syn_simv.daidir syn_program.out \ 55 | dve *.vpd *.vcd *.dump ucli.key 56 | 57 | nuke: clean 58 | rm -rvf *.vg *.rep *.db *.chk *.log *.out DVEfiles/ 59 | 60 | -------------------------------------------------------------------------------- /labs/lab2/slides/scripts/synth.tcl: -------------------------------------------------------------------------------- 1 | ../../../lab1/assignment/source/tut_synth.tcl -------------------------------------------------------------------------------- /labs/lab2/slides/scripts/synth.tcl.old: -------------------------------------------------------------------------------- 1 | # 2 | # Written by : DC-Transcript, Version X-2005.09-SP2 -- Jan 03, 2006 3 | # Date : Tue Aug 29 17:09:34 2006 4 | # 5 | 6 | # 7 | # Translation of script: tut_synth.scr 8 | # 9 | 10 | #/***********************************************************/ 11 | #/* FILE : tut_synth.scr */ 12 | #/* Description : Default Synopsys Design Compiler Script */ 13 | #/* Usage : dc_shell -f tut_synth.scr */ 14 | #/* You'll need to minimally set design_name & read files */ 15 | #/***********************************************************/ 16 | 17 | #/***********************************************************/ 18 | #/* The following five lines must be updated for every */ 19 | #/* new design */ 20 | #/***********************************************************/ 21 | read_file -f sverilog [list "tut_mod.v"] 22 | set design_name two_bit_pred 23 | set clock_name clock 24 | set reset_name reset 25 | set CLK_PERIOD 6 26 | 27 | 28 | #/***********************************************************/ 29 | #/* The rest of this file may be left alone for most small */ 30 | #/* to moderate sized designs. You may need to alter it */ 31 | #/* when synthesizing your final project. */ 32 | #/***********************************************************/ 33 | set SYN_DIR ./ 34 | set search_path "/afs/umich.edu/class/eecs470/lib/synopsys/" 35 | set target_library "lec25dscc25_TT.db" 36 | 37 | set link_library [concat "*" $target_library] 38 | 39 | #/***********************************************************/ 40 | #/* Set some flags for optimisation */ 41 | 42 | set compile_top_all_paths "true" 43 | set auto_wire_load_selection "false" 44 | 45 | 46 | #/***********************************************************/ 47 | #/* Clk Periods/uncertainty/transition */ 48 | 49 | set CLK_TRANSITION 0.1 50 | set CLK_UNCERTAINTY 0.1 51 | set CLK_LATENCY 0.1 52 | 53 | #/* Input/output Delay values */ 54 | set AVG_INPUT_DELAY 0.1 55 | set AVG_OUTPUT_DELAY 0.1 56 | 57 | #/* Critical Range (ns) */ 58 | set CRIT_RANGE 1.0 59 | 60 | #/***********************************************************/ 61 | #/* Design Constrains: Not all used */ 62 | set MAX_TRANSITION 1.0 63 | set FAST_TRANSITION 0.1 64 | set MAX_FANOUT 32 65 | set MID_FANOUT 8 66 | set LOW_FANOUT 1 67 | set HIGH_DRIVE 0 68 | set HIGH_LOAD 1.0 69 | set AVG_LOAD 0.1 70 | set AVG_FANOUT_LOAD 10 71 | 72 | #/***********************************************************/ 73 | #/*BASIC_INPUT = cb18os120_tsmc_max/nd02d1/A1 74 | #BASIC_OUTPUT = cb18os120_tsmc_max/nd02d1/ZN*/ 75 | 76 | set DRIVING_CELL dffacs1 77 | 78 | #/* DONT_USE_LIST = { } */ 79 | 80 | #/*************operation cons**************/ 81 | #/*OP_WCASE = WCCOM; 82 | #OP_BCASE = BCCOM;*/ 83 | set WIRE_LOAD "tsmcwire" 84 | set LOGICLIB lec25dscc25_TT 85 | #/*****************************/ 86 | 87 | #/* Sourcing the file that sets the Search path and the libraries(target,link) */ 88 | 89 | set sys_clk $clock_name 90 | 91 | set netlist_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".vg"] 92 | set ddc_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".ddc"] 93 | set rep_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".rep"] 94 | set dc_shell_status [ set chk_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".chk"] ] 95 | 96 | #/* if we didnt find errors at this point, run */ 97 | if { $dc_shell_status != [list] } { 98 | current_design $design_name 99 | link 100 | set_wire_load_model -name $WIRE_LOAD -lib $LOGICLIB $design_name 101 | set_wire_load_mode top 102 | set_fix_multiple_port_nets -outputs -buffer_constants 103 | create_clock -period $CLK_PERIOD -name $sys_clk [find port $sys_clk] 104 | set_clock_uncertainty $CLK_UNCERTAINTY $sys_clk 105 | set_fix_hold $sys_clk 106 | group_path -from [all_inputs] -name input_grp 107 | group_path -to [all_outputs] -name output_grp 108 | set_driving_cell -lib_cell $DRIVING_CELL [all_inputs] 109 | remove_driving_cell [find port $sys_clk] 110 | set_fanout_load $AVG_FANOUT_LOAD [all_outputs] 111 | set_load $AVG_LOAD [all_outputs] 112 | set_input_delay $AVG_INPUT_DELAY -clock $sys_clk [all_inputs] 113 | remove_input_delay -clock $sys_clk [find port $sys_clk] 114 | set_output_delay $AVG_OUTPUT_DELAY -clock $sys_clk [all_outputs] 115 | set_dont_touch $reset_name 116 | set_resistance 0 $reset_name 117 | set_drive 0 $reset_name 118 | set_critical_range $CRIT_RANGE [current_design] 119 | set_max_delay $CLK_PERIOD [all_outputs] 120 | set MAX_FANOUT $MAX_FANOUT 121 | set MAX_TRANSITION $MAX_TRANSITION 122 | uniquify 123 | redirect $chk_file { check_design } 124 | compile -map_effort medium 125 | write -hier -format verilog -output $netlist_file $design_name 126 | write -hier -format ddc -output $ddc_file $design_name 127 | redirect $rep_file { report_design -nosplit } 128 | redirect -append $rep_file { report_area } 129 | redirect -append $rep_file { report_timing -max_paths 2 -input_pins\ 130 | -nets -transition_time -nosplit } 131 | redirect -append $rep_file { report_constraint -all_violators\ 132 | -verbose -nosplit } 133 | remove_design -all 134 | read_file -format verilog $netlist_file 135 | current_design $design_name 136 | redirect -append $rep_file { report_reference -nosplit } 137 | quit 138 | } else { 139 | quit 140 | } 141 | 142 | -------------------------------------------------------------------------------- /labs/lab2/slides/verilog/and.v: -------------------------------------------------------------------------------- 1 | module and2( 2 | input [1:0] a, 3 | output logic x 4 | ); 5 | assign x=a[0] & a[1]; 6 | endmodule 7 | 8 | module and4( 9 | input [3:0] in, 10 | output logic out 11 | ); 12 | logic [1:0] tmp; 13 | and2 left(.a(in[1:0]),.x(tmp[0])); 14 | and2 right(.a(in[3:2]),.x(tmp[1])); 15 | and2 top(.a(tmp),.x(out)); 16 | endmodule 17 | -------------------------------------------------------------------------------- /labs/lab2/slides/verilog/and2.v: -------------------------------------------------------------------------------- 1 | `ifndef __AND_2_V__ 2 | `define __AND_2_V__ 3 | 4 | module and2( 5 | input [1:0] a, 6 | output logic x 7 | ); 8 | assign x=a[0] & a[1]; 9 | endmodule 10 | 11 | `endif 12 | -------------------------------------------------------------------------------- /labs/lab2/slides/verilog/and4.v: -------------------------------------------------------------------------------- 1 | `include "and2.v" 2 | module and4( 3 | input [3:0] in, 4 | output logic out 5 | ); 6 | logic [1:0] tmp; 7 | and2 left(.a(in[1:0]),.x(tmp[0])); 8 | and2 right(.a(in[3:2]),.x(tmp[1])); 9 | and2 top(.a(tmp),.x(out)); 10 | endmodule 11 | -------------------------------------------------------------------------------- /labs/lab2/slides/verilog/macro.v: -------------------------------------------------------------------------------- 1 | `define DEBUG 2 | `define LOCKED 1'b0 3 | `define UNLOCKED 1'b1 4 | module turnstile( 5 | input coin, push, 6 | input clock, reset 7 | `ifdef DEBUG 8 | ,output logic state 9 | `endif 10 | ); 11 | `ifndef DEBUG 12 | logic state; 13 | `endif 14 | always_comb begin 15 | next_state=state; 16 | if (state==`LOCKED&&coin) next_state = `UNLOCKED; 17 | if (state==`UNLOCKED&&push) next_state = `LOCKED; 18 | end 19 | always_ff @(posedge clock) begin 20 | if (reset) state <= #1 `LOCKED; 21 | else state <= #1 next_state; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /labs/lab3/assignment/source/part_a/Makefile: -------------------------------------------------------------------------------- 1 | # make <- runs simv (after compiling simv if needed) 2 | # make simv <- compile simv if needed (but do not run) 3 | # make int <- runs int_simv interactively (after compiling it if needed) 4 | # make syn <- runs syn_simv (after synthesizing if needed then 5 | # compiling synsimv if needed) 6 | # make syn_int <- runs syn_int_simv interactively (much like make syn) 7 | # make clean <- remove files created during compilations (but not synthesis) 8 | # make nuke <- remove all files created during compilation and synthesis 9 | # 10 | # To compile additional files, add them to the TESTBENCH or SIMFILES as needed 11 | # Every .vg file will need its own rule and one or more synthesis scripts 12 | # The information contained here (in the rules for those vg files) will be 13 | # similar to the information in those scripts but that seems hard to avoid. 14 | # 15 | 16 | VCS = SW_VCS=2015.09 vcs -sverilog +vc -Mupdate -line -full64 17 | 18 | all: simv 19 | # ./simv | tee program.out 20 | 21 | ##### 22 | # Modify starting here 23 | ##### 24 | 25 | TESTBENCH = test_ab.v 26 | SIMFILES = fsm_ab.v 27 | SYNFILES = fsm_ab.vg 28 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 29 | 30 | fsm_ab.vg: test_ab.v fsm_ab.tcl 31 | dc_shell-t -f fsm_ab.tcl | tee synth.out 32 | 33 | 34 | ##### 35 | # Should be no need to modify after here 36 | ##### 37 | 38 | # updated interactive debugger "DVE", using the latest version of VCS 39 | # awdeorio fall 2011 40 | dve: $(SIMFILES) $(TESTBENCH) 41 | $(VCS) +memcbk $(TESTBENCH) $(SIMFILES) -o dve -R -gui 42 | 43 | simv: $(SIMFILES) $(TESTBENCH) 44 | $(VCS) $(TESTBENCH) $(SIMFILES) -o simv -R | tee program.out 45 | 46 | syn_simv: $(SYNFILES) $(TESTBENCH) 47 | $(VCS) $(TESTBENCH) $(SYNFILES) $(LIB) -o syn_simv -R | tee syn_program.out 48 | 49 | syn: syn_simv 50 | # ./syn_simv | tee syn_program.out 51 | 52 | clean: 53 | rm -rvf simv *.daidir csrc vcs.key program.out \ 54 | syn_simv syn_simv.daidir syn_program.out \ 55 | dve *.vpd *.vcd *.dump ucli.key 56 | 57 | nuke: clean 58 | rm -rvf *.vg *.rep *.db *.chk *.log *.out DVEfiles/ 59 | -------------------------------------------------------------------------------- /labs/lab3/assignment/source/part_a/fsm_ab.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Written by : DC-Transcript, Version X-2005.09-SP2 -- Jan 03, 2006 3 | # Date : Tue Aug 29 17:09:34 2006 4 | # 5 | 6 | # 7 | # Translation of script: tut_synth.scr 8 | # 9 | 10 | #/***********************************************************/ 11 | #/* FILE : tut_synth.scr */ 12 | #/* Description : Default Synopsys Design Compiler Script */ 13 | #/* Usage : dc_shell -f tut_synth.scr */ 14 | #/* You'll need to minimally set design_name & read files */ 15 | #/***********************************************************/ 16 | set SYN_DIR ./ 17 | set search_path [ list "./" "/afs/umich.edu/class/eecs470/lib/synopsys" ] 18 | set target_library "lec25dscc25_TT.db" 19 | set link_library [concat "*" $target_library] 20 | 21 | #/***********************************************************/ 22 | #/* Set some flags to suppress warnings we don't care about */ 23 | set suppress_errors [concat $suppress_errors "UID-401"] 24 | suppress_message {"VER-130"} 25 | 26 | #/***********************************************************/ 27 | #/* The following four lines must be updated for every */ 28 | #/* new design */ 29 | #/***********************************************************/ 30 | read_file -f sverilog [list "fsm_ab.v"] 31 | set design_name fsm_ab 32 | #set reset_name reset 33 | set clock_name clock 34 | set CLK_PERIOD 10 35 | 36 | 37 | #/***********************************************************/ 38 | #/* The rest of this file may be left alone for most small */ 39 | #/* to moderate sized designs. You may need to alter it */ 40 | #/* when synthesizing your final project. */ 41 | #/***********************************************************/ 42 | 43 | #/***********************************************************/ 44 | #/* Set some flags for optimisation */ 45 | 46 | set compile_top_all_paths "true" 47 | set auto_wire_load_selection "false" 48 | 49 | 50 | #/***********************************************************/ 51 | #/* Clk Periods/uncertainty/transition */ 52 | 53 | set CLK_TRANSITION 0.1 54 | set CLK_UNCERTAINTY 0.1 55 | set CLK_LATENCY 0.1 56 | 57 | #/* Input/output Delay values */ 58 | set AVG_INPUT_DELAY 0.1 59 | set AVG_OUTPUT_DELAY 0.1 60 | 61 | #/* Critical Range (ns) */ 62 | set CRIT_RANGE 1.0 63 | 64 | #/***********************************************************/ 65 | #/* Design Constrains: Not all used */ 66 | set MAX_TRANSITION 1.0 67 | set FAST_TRANSITION 0.1 68 | set MAX_FANOUT 32 69 | set MID_FANOUT 8 70 | set LOW_FANOUT 1 71 | set HIGH_DRIVE 0 72 | set HIGH_LOAD 1.0 73 | set AVG_LOAD 0.1 74 | set AVG_FANOUT_LOAD 10 75 | 76 | #/***********************************************************/ 77 | #/*BASIC_INPUT = cb18os120_tsmc_max/nd02d1/A1 78 | #BASIC_OUTPUT = cb18os120_tsmc_max/nd02d1/ZN*/ 79 | 80 | set DRIVING_CELL dffacs1 81 | 82 | #/* DONT_USE_LIST = { } */ 83 | 84 | #/*************operation cons**************/ 85 | #/*OP_WCASE = WCCOM; 86 | #OP_BCASE = BCCOM;*/ 87 | set WIRE_LOAD "tsmcwire" 88 | set LOGICLIB lec25dscc25_TT 89 | #/*****************************/ 90 | 91 | #/* Sourcing the file that sets the Search path and the libraries(target,link) */ 92 | 93 | set sys_clk $clock_name 94 | 95 | set netlist_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".vg"] 96 | set db_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".db"] 97 | set rep_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".rep"] 98 | set dc_shell_status [ set chk_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".chk"] ] 99 | 100 | #/* if we didnt find errors at this point, run */ 101 | if { $dc_shell_status != [list] } { 102 | current_design $design_name 103 | link 104 | set_wire_load_model -name $WIRE_LOAD -lib $LOGICLIB $design_name 105 | set_wire_load_mode top 106 | set_fix_multiple_port_nets -outputs -buffer_constants 107 | create_clock -period $CLK_PERIOD -name $sys_clk [find port $sys_clk] 108 | set_clock_uncertainty $CLK_UNCERTAINTY $sys_clk 109 | set_fix_hold $sys_clk 110 | group_path -from [all_inputs] -name input_grp 111 | group_path -to [all_outputs] -name output_grp 112 | set_driving_cell -lib_cell $DRIVING_CELL [all_inputs] 113 | remove_driving_cell [find port $sys_clk] 114 | set_fanout_load $AVG_FANOUT_LOAD [all_outputs] 115 | set_load $AVG_LOAD [all_outputs] 116 | set_input_delay $AVG_INPUT_DELAY -clock $sys_clk [all_inputs] 117 | remove_input_delay -clock $sys_clk [find port $sys_clk] 118 | set_output_delay $AVG_OUTPUT_DELAY -clock $sys_clk [all_outputs] 119 | set_dont_touch reset_name 120 | set_resistance 0 reset_name 121 | set_drive 0 reset_name 122 | set_critical_range $CRIT_RANGE [current_design] 123 | set_max_delay $CLK_PERIOD [all_outputs] 124 | set MAX_FANOUT $MAX_FANOUT 125 | set MAX_TRANSITION $MAX_TRANSITION 126 | uniquify 127 | redirect $chk_file { check_design } 128 | compile -map_effort medium 129 | write -hier -format verilog -output $netlist_file $design_name 130 | write -hier -format db -output $db_file $design_name 131 | redirect $rep_file { report_design -nosplit } 132 | redirect -append $rep_file { report_area } 133 | redirect -append $rep_file { report_timing -max_paths 2 -input_pins -nets -transition_time -nosplit } 134 | redirect -append $rep_file { report_constraint -all_violators -verbose -nosplit } 135 | remove_design -all 136 | read_file -format verilog $netlist_file 137 | current_design $design_name 138 | redirect -append $rep_file { report_reference -nosplit } 139 | quit 140 | } else { 141 | quit 142 | } 143 | 144 | -------------------------------------------------------------------------------- /labs/lab3/assignment/source/part_a/fsm_ab.v: -------------------------------------------------------------------------------- 1 | module fsm_ab( 2 | input clock, reset, in, 3 | output logic out 4 | `ifdef DEBUG_OUT 5 | , output state_out 6 | `endif 7 | ); 8 | 9 | logic [1:0] next_state; 10 | logic [1:0] state; 11 | 12 | `ifdef DEBUG_OUT 13 | assign state_out = state; 14 | `endif 15 | 16 | always_comb begin 17 | case(state) 18 | 2'b00: begin 19 | out = 0; 20 | if(in) next_state = 2'b01; 21 | else next_state = 2'b00; 22 | end 23 | 2'b01: begin 24 | out = 0; 25 | if(in) next_state = 2'b01; 26 | else next_state = 2'b10; 27 | end 28 | 2'b10: begin 29 | out = 0; 30 | if(in) next_state = 2'b11; 31 | else next_state = 2'b00; 32 | end 33 | 2'b11: begin 34 | out = 1; 35 | if(in) next_state = 2'b01; 36 | else next_state = 2'b10; 37 | end 38 | endcase 39 | end 40 | 41 | always_ff @(posedge clock) begin 42 | if(reset) begin 43 | state = 2'b00; 44 | end 45 | else begin 46 | state = next_state; 47 | end 48 | end 49 | 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /labs/lab3/assignment/source/part_a/test_ab.v: -------------------------------------------------------------------------------- 1 | parameter CLOCK_PERIOD = 10; 2 | module testbench; 3 | //Internal Wires 4 | logic correct; 5 | logic [1:0] f1_state; 6 | 7 | //Module Wires 8 | logic clock; 9 | logic reset; 10 | logic in; 11 | logic out; 12 | 13 | fsm_ab f1(.clock(clock), .reset(reset), .in(in), .out(out) , .state_out(f1_state) ); 14 | 15 | always begin 16 | #(CLOCK_PERIOD/2); //clock "interval" ... AKA 1/2 the period 17 | clock=~clock; 18 | end 19 | 20 | //--------------Test bench functions--------------- 21 | task exit_on_error; 22 | begin 23 | $display("@@@ Incorrect at time %4.0f", $time); 24 | $display("@@@ Time:%4.0f clock:%b reset:%h state=%b in:%b out:%b correct:%b", $time, clock, reset, f1_state, in, out, correct); 25 | $display("ENDING TESTBENCH : ERROR !"); 26 | $finish; 27 | end 28 | endtask 29 | 30 | always_ff @(negedge clock) begin 31 | if( !correct ) begin //CORRECT CASE 32 | exit_on_error( ); 33 | end 34 | end 35 | 36 | //check 37 | function EXPECTED_OUT; 38 | input in; 39 | begin 40 | EXPECTED_OUT = (f1_state[1] && f1_state[0]); 41 | end 42 | endfunction 43 | 44 | task CHECK_STATE; 45 | input [1:0] tb_state; 46 | begin 47 | if( tb_state === f1_state ) correct = 1; 48 | else correct = 0; 49 | end 50 | endtask 51 | 52 | //-------------------------------------------------- 53 | 54 | initial begin 55 | 56 | $display("STARTING TESTBENCH!\n"); 57 | 58 | //INIT STATE 59 | correct = 1; 60 | clock = 0; 61 | reset = 1; 62 | in = 0; 63 | 64 | 65 | //TRANSITION TESTS 66 | reset = 1; 67 | $display("reset=%b state=%b in=%b out=%b correct=%b", reset, f1_state, in,out, correct); 68 | @(negedge clock); 69 | reset = 0; 70 | in = 0; 71 | $display("reset=%b state=%b in=%b out=%b correct=%b", reset, f1_state, in,out, correct); 72 | @(negedge clock); 73 | in = 1; 74 | CHECK_STATE( 2'b00 ); 75 | $display("reset=%b state=%b in=%b out=%b correct=%b", reset, f1_state, in,out, correct); 76 | @(negedge clock); 77 | CHECK_STATE( 2'b01 ); 78 | in = 1; 79 | $display("reset=%b state=%b in=%b out=%b correct=%b", reset, f1_state, in,out, correct); 80 | @(negedge clock); 81 | CHECK_STATE( 2'b01 ); 82 | in = 0; 83 | $display("reset=%b state=%b in=%b out=%b correct=%b", reset, f1_state, in,out, correct); 84 | @(negedge clock); 85 | CHECK_STATE( 2'b10 ); 86 | in = 1; 87 | $display("reset=%b state=%b in=%b out=%b correct=%b", reset, f1_state, in,out, correct); 88 | @(negedge clock); 89 | CHECK_STATE( 2'b11 ); 90 | in = 0; 91 | $display("reset=%b state=%b in=%b out=%b correct=%b", reset, f1_state, in,out, correct); 92 | @(negedge clock); 93 | CHECK_STATE( 2'b10 ); 94 | in = 0; 95 | $display("reset=%b state=%b in=%b out=%b correct=%b", reset, f1_state, in,out, correct); 96 | @(negedge clock); 97 | CHECK_STATE( 2'b00 ); 98 | 99 | //RANDOM TEST 100 | $display("reset=%b state=%b in=%b out=%b correct=%b", reset, f1_state, in,out, correct); 101 | @(negedge clock); 102 | reset = 0; 103 | for (int i=0; i < 400; i=i+1) begin 104 | in = $random; 105 | if(i%10) reset=0; 106 | else reset=1; 107 | #1 //Short delay to evaulate 108 | $display(" i=%d reset=%b state=%b in=%b out=%b correct=%b", i, reset, f1_state, in,out, correct); 109 | correct = (reset) ? ( out == 2'b00 ) : ( out == EXPECTED_OUT(in) ) ; 110 | @(negedge clock); 111 | end 112 | 113 | 114 | 115 | //SUCCESSFULLY END TESTBENCH 116 | $display("ENDING TESTBENCH : SUCCESS !\n"); 117 | $finish; 118 | 119 | end 120 | 121 | 122 | endmodule 123 | -------------------------------------------------------------------------------- /labs/lab3/assignment/source/part_b/Makefile: -------------------------------------------------------------------------------- 1 | # make <- runs simv (after compiling simv if needed) 2 | # make simv <- compile simv if needed (but do not run) 3 | # make int <- runs int_simv interactively (after compiling it if needed) 4 | # make syn <- runs syn_simv (after synthesizing if needed then 5 | # compiling synsimv if needed) 6 | # make syn_int <- runs syn_int_simv interactively (much like make syn) 7 | # make clean <- remove files created during compilations (but not synthesis) 8 | # make nuke <- remove all files created during compilation and synthesis 9 | # 10 | # To compile additional files, add them to the TESTBENCH or SIMFILES as needed 11 | # Every .vg file will need its own rule and one or more synthesis scripts 12 | # The information contained here (in the rules for those vg files) will be 13 | # similar to the information in those scripts but that seems hard to avoid. 14 | # 15 | 16 | VCS = SW_VCS=2015.09 vcs -sverilog +vc -Mupdate -line -full64 17 | 18 | all: simv 19 | # ./simv | tee program.out 20 | 21 | ##### 22 | # Modify starting here 23 | ##### 24 | 25 | TESTBENCH = sys_defs.vh test_cd.v 26 | SIMFILES = fsm_cd.v 27 | SYNFILES = pa2_fsm.vg 28 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 29 | 30 | 31 | pa2_fsm.vg: fsm_cd.v fsm_cd.tcl 32 | dc_shell-t -f fsm_cd.tcl | tee synth.out 33 | 34 | 35 | ##### 36 | # Should be no need to modify after here 37 | ##### 38 | 39 | # updated interactive debugger "DVE", using the latest version of VCS 40 | # awdeorio fall 2011 41 | dve: $(SIMFILES) $(TESTBENCH) 42 | $(VCS) +memcbk $(TESTBENCH) $(SIMFILES) -o dve -R -gui 43 | 44 | simv: $(SIMFILES) $(TESTBENCH) 45 | $(VCS) $(TESTBENCH) $(SIMFILES) -o simv -R | tee program.out 46 | 47 | syn_simv: $(SYNFILES) $(TESTBENCH) 48 | $(VCS) $(TESTBENCH) $(SYNFILES) $(LIB) -o syn_simv -R | tee syn_program.out 49 | 50 | syn: syn_simv 51 | # ./syn_simv | tee syn_program.out 52 | 53 | clean: 54 | rm -rvf simv *.daidir csrc vcs.key program.out \ 55 | syn_simv syn_simv.daidir syn_program.out \ 56 | dve *.vpd *.vcd *.dump ucli.key 57 | 58 | nuke: clean 59 | rm -rvf *.vg *.rep *.db *.chk *.log *.out DVEfiles/ 60 | -------------------------------------------------------------------------------- /labs/lab3/assignment/source/part_b/fsm_cd.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Written by : DC-Transcript, Version X-2005.09-SP2 -- Jan 03, 2006 3 | # Date : Tue Aug 29 17:09:34 2006 4 | # 5 | 6 | # 7 | # Translation of script: tut_synth.scr 8 | # 9 | 10 | #/***********************************************************/ 11 | #/* FILE : tut_synth.scr */ 12 | #/* Description : Default Synopsys Design Compiler Script */ 13 | #/* Usage : dc_shell -f tut_synth.scr */ 14 | #/* You'll need to minimally set design_name & read files */ 15 | #/***********************************************************/ 16 | set SYN_DIR ./ 17 | set search_path [ list "./" "/afs/umich.edu/class/eecs470/lib/synopsys/" ] 18 | set target_library "lec25dscc25_TT.db" 19 | set link_library [concat "*" $target_library] 20 | 21 | #/***********************************************************/ 22 | #/* Set some flags to suppress warnings we don't care about */ 23 | set suppress_errors [concat $suppress_errors "UID-401"] 24 | suppress_message {"VER-130"} 25 | 26 | #/***********************************************************/ 27 | #/* The following four lines must be updated for every */ 28 | #/* new design */ 29 | #/***********************************************************/ 30 | read_file -f sverilog [list "sys_defs.vh" "fsm_cd.v"] 31 | set design_name pa2_fsm 32 | set clock_name clock 33 | set CLK_PERIOD 10 34 | 35 | 36 | #/***********************************************************/ 37 | #/* The rest of this file may be left alone for most small */ 38 | #/* to moderate sized designs. You may need to alter it */ 39 | #/* when synthesizing your final project. */ 40 | #/***********************************************************/ 41 | 42 | #/***********************************************************/ 43 | #/* Set some flags for optimisation */ 44 | 45 | set compile_top_all_paths "true" 46 | set auto_wire_load_selection "false" 47 | 48 | 49 | #/***********************************************************/ 50 | #/* Clk Periods/uncertainty/transition */ 51 | 52 | set CLK_TRANSITION 0.1 53 | set CLK_UNCERTAINTY 0.1 54 | set CLK_LATENCY 0.1 55 | 56 | #/* Input/output Delay values */ 57 | set AVG_INPUT_DELAY 0.1 58 | set AVG_OUTPUT_DELAY 0.1 59 | 60 | #/* Critical Range (ns) */ 61 | set CRIT_RANGE 1.0 62 | 63 | #/***********************************************************/ 64 | #/* Design Constrains: Not all used */ 65 | set MAX_TRANSITION 1.0 66 | set FAST_TRANSITION 0.1 67 | set MAX_FANOUT 32 68 | set MID_FANOUT 8 69 | set LOW_FANOUT 1 70 | set HIGH_DRIVE 0 71 | set HIGH_LOAD 1.0 72 | set AVG_LOAD 0.1 73 | set AVG_FANOUT_LOAD 10 74 | 75 | #/***********************************************************/ 76 | #/*BASIC_INPUT = cb18os120_tsmc_max/nd02d1/A1 77 | #BASIC_OUTPUT = cb18os120_tsmc_max/nd02d1/ZN*/ 78 | 79 | set DRIVING_CELL dffacs1 80 | 81 | #/* DONT_USE_LIST = { } */ 82 | 83 | #/*************operation cons**************/ 84 | #/*OP_WCASE = WCCOM; 85 | #OP_BCASE = BCCOM;*/ 86 | set WIRE_LOAD "tsmcwire" 87 | set LOGICLIB lec25dscc25_TT 88 | #/*****************************/ 89 | 90 | #/* Sourcing the file that sets the Search path and the libraries(target,link) */ 91 | 92 | set sys_clk $clock_name 93 | 94 | set netlist_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".vg"] 95 | set db_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".db"] 96 | set rep_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".rep"] 97 | set dc_shell_status [ set chk_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".chk"] ] 98 | 99 | #/* if we didnt find errors at this point, run */ 100 | if { $dc_shell_status != [list] } { 101 | current_design $design_name 102 | link 103 | set_wire_load_model -name $WIRE_LOAD -lib $LOGICLIB $design_name 104 | set_wire_load_mode top 105 | set_fix_multiple_port_nets -outputs -buffer_constants 106 | create_clock -period $CLK_PERIOD -name $sys_clk [find port $sys_clk] 107 | set_clock_uncertainty $CLK_UNCERTAINTY $sys_clk 108 | set_fix_hold $sys_clk 109 | group_path -from [all_inputs] -name input_grp 110 | group_path -to [all_outputs] -name output_grp 111 | set_driving_cell -lib_cell $DRIVING_CELL [all_inputs] 112 | remove_driving_cell [find port $sys_clk] 113 | set_fanout_load $AVG_FANOUT_LOAD [all_outputs] 114 | set_load $AVG_LOAD [all_outputs] 115 | set_input_delay $AVG_INPUT_DELAY -clock $sys_clk [all_inputs] 116 | remove_input_delay -clock $sys_clk [find port $sys_clk] 117 | set_output_delay $AVG_OUTPUT_DELAY -clock $sys_clk [all_outputs] 118 | set_dont_touch reset_name 119 | set_resistance 0 reset_name 120 | set_drive 0 reset_name 121 | set_critical_range $CRIT_RANGE [current_design] 122 | set_max_delay $CLK_PERIOD [all_outputs] 123 | set MAX_FANOUT $MAX_FANOUT 124 | set MAX_TRANSITION $MAX_TRANSITION 125 | uniquify 126 | redirect $chk_file { check_design } 127 | compile -map_effort medium 128 | write -hier -format verilog -output $netlist_file $design_name 129 | write -hier -format db -output $db_file $design_name 130 | redirect $rep_file { report_design -nosplit } 131 | redirect -append $rep_file { report_area } 132 | redirect -append $rep_file { report_timing -max_paths 2 -input_pins -nets -transition_time -nosplit } 133 | redirect -append $rep_file { report_constraint -all_violators -verbose -nosplit } 134 | remove_design -all 135 | read_file -format verilog $netlist_file 136 | current_design $design_name 137 | redirect -append $rep_file { report_reference -nosplit } 138 | quit 139 | } else { 140 | quit 141 | } 142 | 143 | -------------------------------------------------------------------------------- /labs/lab3/assignment/source/part_b/fsm_cd.v: -------------------------------------------------------------------------------- 1 | //Module Written By: Josh Smith 2 | 3 | module pa2_fsm( 4 | input clock, 5 | input reset, 6 | input valid, 7 | input [3:0] num, 8 | input [3:0] seq, 9 | output STATE state, 10 | output STATE n_state, 11 | output logic [3:0] cnt, 12 | output logic [3:0] n_cnt, 13 | output logic hit 14 | 15 | ); 16 | 17 | logic cnt_inc, cnt_dec; 18 | 19 | // Control/output logic 20 | assign cnt_inc = (n_state == WATCH) && (seq==num); 21 | assign cnt_dec = (n_state == ASSERT); 22 | assign n_cnt = cnt_inc ? cnt + 4'h1 : 23 | cnt_dec ? cnt - 4'h1 : cnt; 24 | 25 | assign hit = (state == ASSERT); 26 | 27 | // Next-state logic 28 | always_comb begin 29 | case(state) 30 | WAIT: 31 | if (valid) n_state = WATCH; 32 | else n_state = WAIT; 33 | 34 | WATCH: 35 | if (!valid) n_state = (n_cnt==0) ? WAIT : ASSERT; 36 | else n_state = WATCH; 37 | 38 | ASSERT: 39 | // check >1, because if we decrement to 0 we'll assert 40 | // hit one time too many 41 | if (cnt>4'h1) n_state = ASSERT; 42 | else n_state = WAIT; 43 | 44 | default: n_state = WAIT; 45 | endcase 46 | end 47 | 48 | always_ff @(posedge clock) begin 49 | if (reset) begin 50 | state <= #1 WAIT; 51 | cnt <= #1 4'h0; 52 | end else begin 53 | state <= #1 n_state; 54 | cnt <= #1 n_cnt; 55 | end 56 | end 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /labs/lab3/assignment/source/part_b/sys_defs.vh: -------------------------------------------------------------------------------- 1 | ///////////////////////////////////////////////////////////////////////// 2 | // // 3 | // Modulename : sys_defs.vh // 4 | // // 5 | // Description : This file has the parameter and typedefs used in // 6 | // in-lab 3 part b // 7 | // // 8 | ///////////////////////////////////////////////////////////////////////// 9 | 10 | typedef enum {WAIT, WATCH, ASSERT} STATE; 11 | typedef enum {RAND, MATCH, NO_MATCH} OVERRIDE; 12 | 13 | parameter CLOCK_PERIOD = 10; 14 | -------------------------------------------------------------------------------- /labs/lab3/assignment/source/part_b/test_cd.v: -------------------------------------------------------------------------------- 1 | //Written by: Josh Smith 2 | 3 | module test_pa2_fsm; 4 | 5 | // DUT I/O 6 | logic clock; 7 | logic reset; 8 | logic valid; 9 | logic [3:0] num; 10 | logic [3:0] seq; 11 | logic hit; 12 | logic [3:0] cnt, n_cnt; 13 | STATE state, n_state; 14 | // Testbench variables 15 | logic [3:0] int_cnt; // Keeps track of # hits on input 16 | logic [3:0] hit_cnt; // Used to monitor hit output signal 17 | logic [3:0] seq_len; 18 | 19 | pa2_fsm dut( .clock, 20 | .reset, 21 | .valid, 22 | .num, 23 | .seq, 24 | .state, 25 | .cnt, 26 | .n_cnt, 27 | .hit 28 | ); 29 | 30 | always 31 | #5 clock = ~clock; 32 | 33 | initial begin 34 | // setup monitor and reset signals 35 | $monitor("time: %3.0d vld: %b num: %2.0d seq: %2.0d cnt: %2.0d n_cnt: %2.0d state: %b n_state: %b hit: %b", 36 | $time, valid, num, seq, cnt, n_cnt, state, n_state, hit); 37 | 38 | clock = 1'b0; 39 | reset = 1'b0; 40 | valid = 1'b0; 41 | num = 4'h5; 42 | seq = 4'h0; 43 | seq_len = 4'h0; 44 | int_cnt = 4'h0; 45 | hit_cnt = 4'h0; 46 | 47 | // Apply reset to DUT 48 | reset = 1'b1; 49 | @(negedge clock); 50 | reset = 1'b0; 51 | 52 | // Apply sequence with zero matches 53 | // then wait 11-15 cycles to start over (to allow for hit cycles) 54 | apply_sequence(4'd10, NO_MATCH); 55 | repeat (11) @(negedge clock); 56 | 57 | // Apply sequence with all matches 58 | apply_sequence(4'd10, MATCH); 59 | repeat (11) @(negedge clock); 60 | 61 | // Apply sequence with length 1 (no match) 62 | apply_sequence(4'd1, NO_MATCH); 63 | repeat (2) @(negedge clock); 64 | 65 | // Apply sequence with length 1 (match) 66 | apply_sequence(4'd1, MATCH); 67 | repeat (3) @(negedge clock); 68 | 69 | // Go through 5 rounds of random sequences 70 | repeat(5) begin 71 | seq_len = ($random % 4'd10) + 1; // num between 1-10 72 | apply_sequence(seq_len, RAND); 73 | repeat (11) @(negedge clock); 74 | end 75 | 76 | @(negedge clock); 77 | $display(" FINISHED : SUCCESS ! \n "); 78 | $finish; 79 | end 80 | 81 | // Block to monitor "hit" output 82 | always @(negedge clock) begin 83 | #1; 84 | // Check to see if hit is asserted when it shouldn't be 85 | if (hit && hit_cnt==0) begin 86 | $display("@@@ FAIL: Hit asserted erroneously!"); 87 | $finish; 88 | 89 | // Check to see if hit not asserted when it should be 90 | end else if (!hit && hit_cnt>0) begin 91 | $display("@@@ FAIL: Hit not asserted but should be!"); 92 | $finish; 93 | 94 | // Decrement counter 95 | end else if (hit && hit_cnt>0) begin 96 | hit_cnt = hit_cnt-4'h1; 97 | end 98 | end 99 | 100 | // Task to apply a sequence of numbers to the DUT 101 | task apply_sequence; 102 | input [3:0] length; 103 | input OVERRIDE override; // RAND: use random inputs 104 | // MATCH: force seq to match num 105 | // NO_MATCH: force seq to not match num 106 | begin 107 | int_cnt = 4'h0; 108 | valid = 1'b1; 109 | repeat(length) begin 110 | @(negedge clock); 111 | case(override) 112 | RAND: seq = ($random % 'd16); // num between 0-15 113 | MATCH: seq = num; 114 | NO_MATCH: seq = ~num; 115 | endcase 116 | if (seq == num) 117 | int_cnt = int_cnt + 4'h1; 118 | end 119 | valid = 1'b0; 120 | 121 | // Initialize hit_cnt for hit output monitoring 122 | #2; 123 | hit_cnt = int_cnt; 124 | end 125 | endtask 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /labs/lab3/assignment/tex/eecs470lab3assignment.tex: -------------------------------------------------------------------------------- 1 | %***********************************************% 2 | % % 3 | % EECS 470 - Lab 03 % 4 | %<------------------> % 5 | % Last Modified by: % 6 | % William Cunningham on 2013-9-15 % 7 | % % 8 | %***********************************************% 9 | 10 | %***********************************************% 11 | % Preamble % 12 | %***********************************************% 13 | 14 | \documentclass{article} 15 | 16 | \usepackage{ 17 | tikz, 18 | xcolor, 19 | colortbl, 20 | graphicx, 21 | amsmath, 22 | amssymb, 23 | hyperref, 24 | mathrsfs, 25 | float, 26 | siunitx, 27 | fancyhdr, 28 | url, 29 | minted 30 | } 31 | 32 | \usepackage 33 | [left=1in,top=1in,right=1in,bottom=1in] 34 | {geometry} 35 | 36 | \pagestyle{fancy} 37 | \raggedright 38 | 39 | %--- Header ---% 40 | 41 | \newcommand{\courseNumber}{EECS 470} 42 | \newcommand{\courseTitle}{Computer Architecture} 43 | \newcommand{\university}{University of Michigan, Ann Arbor} 44 | \newcommand{\labdate}{January 24$^{\text{th}}$, 2019} 45 | 46 | 47 | \lhead{ 48 | \small{ 49 | \university 50 | } 51 | } 52 | \rhead{ 53 | \small{ 54 | \emph{Date: \labdate} \hspace*{-1em} 55 | % Why is the above \hspace necessary? 56 | } 57 | } 58 | 59 | \newcommand{\shortbar}{ 60 | \vspace*{-12pt} 61 | \begin{center} 62 | \rule{5ex}{0.1pt} 63 | \end{center} 64 | } 65 | \newcommand{\lab}[1]{ 66 | \begin{center} 67 | \LARGE{ 68 | \vspace*{-12pt} 69 | EECS 470 Lab #1 Assignment 70 | \shortbar 71 | } 72 | \end{center} 73 | } 74 | 75 | 76 | %***********************************************% 77 | % % 78 | % TikZ Definitions % 79 | % % 80 | %***********************************************% 81 | 82 | \usetikzlibrary{shapes,arrows} 83 | 84 | % Block Diagram Styles 85 | \tikzstyle{block} = [draw, fill=blue!20, rectangle, 86 | minimum height=3em, minimum width=6em] 87 | \tikzstyle{sum} = [draw, fill=blue!20, circle, node distance=2cm] 88 | \tikzstyle{input} = [coordinate] 89 | \tikzstyle{output} = [coordinate] 90 | \tikzstyle{branch} = [coordinate] 91 | \tikzstyle{pinstyle} = [pin edge={to-, thin, black}] 92 | 93 | % Signal Flow Graph Styles 94 | \tikzstyle{signal} = [draw, fill=blue!20, circle, 95 | minimum height=3em] 96 | \tikzstyle{state} = [draw, fill=blue!20, circle, 97 | minimum height=3em] 98 | 99 | %***********************************************% 100 | % % 101 | % Document % 102 | % % 103 | %***********************************************% 104 | 105 | \begin{document} 106 | \vspace*{-20pt} 107 | \lab{3} 108 | \vspace*{-20pt} 109 | 110 | \section*{Note:} 111 | \begin{itemize} 112 | \item The lab should be completed individually. 113 | \item The lab must be checked off by a GSI by 114 | Thursday, 31$^\text{st}$ January 2018. 115 | \end{itemize} 116 | 117 | \section{Introduction} 118 | This lab is on debugging. We will cover several ways of debugging internal and 119 | external errors in the lab. Here, external errors refer to errors in the 120 | directory, file setup, or with the \texttt{Makefile} and \texttt{*.tcl} file. 121 | Internal error means an error inside the SystemVerilog files, either syntax or 122 | logical error. You will need to find the errors in the finite state machine for 123 | Part A and for Part B. 124 | 125 | Initially you are given a .tar file with all the files needed to run and test 126 | Finite State Machines (FSMs) A and B. You should extract this tar file to a 127 | folder. This folder should automatically contain a sub-folder for Part A and 128 | Part B (\texttt{part\_a} and \texttt{part\_b}, are the respective folder 129 | names). Note that Part A and Part B are different FSMs that have nothing to do 130 | with each other. 131 | 132 | \section{Assignment} 133 | In both Part A and Part B there is at least 1 error. 134 | Your task is to debug both FSMs and get them working according to the testbench. 135 | The errors may exist in either the design file or the testbench, but you should not 136 | modify the testbench functionality (meaning don't change the what the testbench is 137 | checking for). 138 | 139 | \subsection{Part A} 140 | \begin{figure}[H] 141 | \centering 142 | \begin{tikzpicture}[auto, node distance=4cm,>=latex',every text node 143 | part/.style={align=center}] 144 | \node[state] (zero) {state=00 \\ out=0}; 145 | \node[state,right of=zero] (one) {state=01 \\ out=0}; 146 | \node[state,below of=one] (two) {state=10 \\ out=0}; 147 | \node[state,below of=zero] (three) {state=11 \\ out=1}; 148 | 149 | \draw[->] (zero) to[out=150, in=120, looseness=8] node{0} (zero); 150 | \draw[->] (one) to[out=29, in=60, looseness=8] node[above]{1} (one); 151 | \draw[->] (one.south) -- node{0} (two.north); 152 | \draw[->] (zero.east) -- node{1} (one.west); 153 | \draw[->] (two.west) -- node{1} (three.east); 154 | \draw[->] (three) to[out=300,in=240] node{0} (two); 155 | \draw[->] (three.north east) -- node[pos=0.8]{1}(one.south west); 156 | \draw[->] (two.north west) -- node[pos=0.8,above]{0}(zero.south east); 157 | \end{tikzpicture} 158 | \caption{FSM A: The \texttt{reset} signal should send the state machine back to 159 | state=00. The transition signal for this state machine is labeled 160 | \texttt{in}.} 161 | \end{figure} 162 | 163 | Fix the errors in this FSM (\texttt{fsm\_ab.v}) to operate as shown in Fig. 1. 164 | 165 | \subsection{Part B} 166 | \begin{figure}[H] 167 | \centering 168 | \begin{tikzpicture}[auto, node distance=4cm,>=latex',every text node 169 | part/.style={align=center}] 170 | \node[state] (wait) {state=WAIT \\ cnt+=0 \\ hit=0}; 171 | \node[state,right of=zero,node distance=8cm] (watch) {state=WATCH \\ hit=0 \\ 172 | if(seq==num) cnt++}; 173 | \node[state,below of=watch] (assert) {state=ASSERT \\ cnt--\\ hit=1}; 174 | 175 | \draw[->] (wait) to[out=150, in=120, looseness=6] node{!valid} (wait); 176 | \draw[->] (watch) to[out=30, in=60, looseness=4] node[pos=0.6,node 177 | distance=3cm,above]{valid} (watch); 178 | \draw[->] (assert) to[out=240, in=300, looseness=3] node[below]{cnt$>$1} (assert); 179 | \draw[->] (assert).. controls+(180:5cm) and +(270:3cm) .. node{!(cnt$>$1)} (wait); 180 | \draw[->] (watch.south) -- node{n\_cnt!=0 \&\& !valid}(assert.north); 181 | \draw[->] (wait.30) -- node[above]{valid} (watch.160); 182 | \draw[->] (watch.west) -- node[below]{n\_cnt==0 \&\& !valid} 183 | (wait.east); 184 | \end{tikzpicture} 185 | \caption{FSM B: The \texttt{reset} signal should send the state machine back 186 | to state=WAIT and set \texttt{cnt} to zero.} 187 | \end{figure} 188 | 189 | Fix the errors in this FSM (\texttt{fsm\_cd.v}) to operate as shown in Fig. 2. 190 | 191 | \section{Submission} 192 | Once you are confident in your module and testbench, put yourself on the \href{https://oh.eecs.umich.edu/courses/eecs470}{\underline{help queue}} and we will come check you off. 193 | 194 | \end{document} 195 | -------------------------------------------------------------------------------- /labs/lab3/slides/beamercolorthemewolverine.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2004 by Madhusudan Singh 2 | % 3 | % This file may be distributed and/or modified 4 | % 5 | % 1. under the LaTeX Project Public License and/or 6 | % 2. under the GNU Public License. 7 | % 8 | % See the file doc/licenses/LICENSE for more details. 9 | 10 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/color/beamercolorthemewolverine.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 11 | 12 | \mode 13 | 14 | \definecolor{darkblue}{rgb}{0,0,0.8} 15 | 16 | \setbeamercolor{alerted text}{fg=red!85!black} 17 | \setbeamercolor*{palette primary}{fg=darkblue!60!black,bg=yellow!85!orange} 18 | \setbeamercolor*{palette secondary}{fg=darkblue!60!black,bg=yellow!85!orange} 19 | %\setbeamercolor*{palette secondary}{fg=darkblue!70!black,bg=yellow!60!orange} 20 | \setbeamercolor*{palette tertiary}{bg=darkblue!80!black,fg=yellow!50!orange} 21 | \setbeamercolor*{palette quaternary}{fg=darkblue,bg=yellow!20!orange} 22 | 23 | \setbeamercolor*{sidebar}{fg=darkblue,bg=orange!75!white} 24 | 25 | 26 | \setbeamercolor*{palette sidebar primary}{fg=darkblue!10!black} 27 | \setbeamercolor*{palette sidebar secondary}{fg=white} 28 | \setbeamercolor*{palette sidebar tertiary}{fg=darkblue!50!black} 29 | \setbeamercolor*{palette sidebar quaternary}{fg=yellow!10!orange} 30 | 31 | \setbeamercolor*{titlelike}{parent=palette primary} 32 | \setbeamercolor{frametitle}{bg=yellow!90!orange} 33 | \setbeamercolor{frametitle right}{bg=yellow!60!orange} 34 | 35 | \setbeamercolor*{separation line}{} 36 | \setbeamercolor*{fine separation line}{} 37 | 38 | \mode 39 | 40 | -------------------------------------------------------------------------------- /labs/lab3/slides/beamerthemeLab.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2014 William Cunningham 2 | % For use in U of M EECS 470 - Computer Architecture Labs 3 | % 4 | % This file may be distributed and/or modified 5 | % 6 | % 1. under the LaTeX Project Public License and/or 7 | % 2. under the GNU Public License. 8 | % 9 | % See the file doc/licenses/LICENSE for more details. 10 | 11 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/theme/beamerthemedLabs.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 12 | 13 | 14 | \mode 15 | 16 | \usefonttheme{default} 17 | \usecolortheme{wolverine} 18 | \useinnertheme{default} 19 | \useoutertheme{infolines} 20 | 21 | \mode 22 | 23 | -------------------------------------------------------------------------------- /labs/lab3/slides/enum_dve.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/labs/lab3/slides/enum_dve.jpg -------------------------------------------------------------------------------- /labs/lab3/slides/hierarchy.txt: -------------------------------------------------------------------------------- 1 | Design Hierarchy 2 | 3 | 4 | ---------------- 5 | SCORE LINE TOGGLE 6 | 80.50 97.27 63.72 testbench 7 | 8 | ---------------- 9 | SCORE LINE TOGGLE 10 | 81.22 100.00 62.44 m0 11 | 12 | ---------------- 13 | SCORE LINE TOGGLE 14 | 88.67 100.00 77.33 mstage[0] 15 | 93.19 100.00 86.37 mstage[1] 16 | 88.67 100.00 77.33 mstage[2] 17 | 84.15 100.00 68.29 mstage[3] 18 | 79.63 100.00 59.25 mstage[4] 19 | 75.11 100.00 50.21 mstage[5] 20 | 70.59 100.00 41.17 mstage[6] 21 | 66.07 100.00 32.13 mstage[7] 22 | -------------------------------------------------------------------------------- /labs/lab3/slides/verilog/fsm.v: -------------------------------------------------------------------------------- 1 | typedef enum logic { LOCKED, UNLOCKED } ts_state; 2 | 3 | module turnstile( 4 | input wire coin, push, 5 | input wire clock, reset, 6 | output ts_state state 7 | ); 8 | 9 | ts_state next_state; 10 | 11 | always_comb begin 12 | next_state=state; 13 | if (state==LOCKED && coin) next_state = UNLOCKED; 14 | if (state==UNLOCKED && push) next_state = LOCKED; 15 | end 16 | always_ff @(posedge clock) begin 17 | if (reset) state <= #1 LOCKED; 18 | else state <= #1 next_state; 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /labs/lab4/assignment/source/buggy1/Makefile: -------------------------------------------------------------------------------- 1 | # Stripped down Makefile 2 | 3 | VCS = SW_VCS=2011.03 vcs -sverilog +vc -Mupdate -line -full64 4 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 5 | TEST = isr_test.v 6 | VG = ISR.vg 7 | 8 | test: simv 9 | ./simv 10 | 11 | simv: $(TEST) $(VG) $(LIB) 12 | $(VCS) $^ -o $@ 13 | 14 | dve: $(TEST) $(VG) $(LIB) 15 | $(VCS) +memcbk $^ -o dve -R -gui 16 | 17 | clean: 18 | rm -rvf simv *.daidir csrc vcs.key program.out \ 19 | syn_simv syn_simv.daidir syn_program.out \ 20 | int_simv int_simv.daidir syn_int_simv syn_int_simv.daidir \ 21 | dve *.vpd *.vcd *.dump ucli.key 22 | 23 | .PHONY: test clean 24 | -------------------------------------------------------------------------------- /labs/lab4/assignment/source/buggy2/Makefile: -------------------------------------------------------------------------------- 1 | # Stripped down Makefile 2 | 3 | VCS = SW_VCS=2011.03 vcs -sverilog +vc -Mupdate -line -full64 4 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 5 | TEST = isr_test.v 6 | VG = ISR.vg 7 | 8 | test: simv 9 | ./simv 10 | 11 | simv: $(TEST) $(VG) $(LIB) 12 | $(VCS) $^ -o $@ 13 | 14 | dve: $(TEST) $(VG) $(LIB) 15 | $(VCS) +memcbk $^ -o dve -R -gui 16 | 17 | clean: 18 | rm -rvf simv *.daidir csrc vcs.key program.out \ 19 | syn_simv syn_simv.daidir syn_program.out \ 20 | int_simv int_simv.daidir syn_int_simv syn_int_simv.daidir \ 21 | dve *.vpd *.vcd *.dump ucli.key 22 | 23 | .PHONY: test clean 24 | -------------------------------------------------------------------------------- /labs/lab4/assignment/source/buggy3/Makefile: -------------------------------------------------------------------------------- 1 | # Stripped down Makefile 2 | 3 | VCS = SW_VCS=2011.03 vcs -sverilog +vc -Mupdate -line -full64 4 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 5 | TEST = isr_test.v 6 | VG = ISR.vg 7 | 8 | test: simv 9 | ./simv 10 | 11 | simv: $(TEST) $(VG) $(LIB) 12 | $(VCS) $^ -o $@ 13 | 14 | dve: $(TEST) $(VG) $(LIB) 15 | $(VCS) +memcbk $^ -o dve -R -gui 16 | 17 | clean: 18 | rm -rvf simv *.daidir csrc vcs.key program.out \ 19 | syn_simv syn_simv.daidir syn_program.out \ 20 | int_simv int_simv.daidir syn_int_simv syn_int_simv.daidir \ 21 | dve *.vpd *.vcd *.dump ucli.key 22 | 23 | .PHONY: test clean 24 | -------------------------------------------------------------------------------- /labs/lab4/assignment/source/isr_test.v: -------------------------------------------------------------------------------- 1 | // Add your testbench here 2 | -------------------------------------------------------------------------------- /labs/lab4/assignment/tex/eecs470lab4assignment.tex: -------------------------------------------------------------------------------- 1 | %***********************************************% 2 | % % 3 | % EECS 470 - Lab 04 % 4 | %<------------------> % 5 | % Last Modified by: % 6 | % William Cunningham on 2014-9-22 % 7 | % % 8 | %***********************************************% 9 | 10 | %***********************************************% 11 | % Preamble % 12 | %***********************************************% 13 | 14 | \documentclass{article} 15 | 16 | \usepackage{ 17 | tikz, 18 | xcolor, 19 | colortbl, 20 | graphicx, 21 | amsmath, 22 | amssymb, 23 | mathrsfs, 24 | float, 25 | siunitx, 26 | fancyhdr, 27 | url, 28 | listings, 29 | cleveref 30 | } 31 | 32 | \usepackage 33 | [left=1in,top=1in,right=1in,bottom=1in] 34 | {geometry} 35 | 36 | \pagestyle{fancy} 37 | \raggedright 38 | 39 | %--- Header ---% 40 | 41 | \newcommand{\courseNumber}{EECS 470} 42 | \newcommand{\courseTitle}{Computer Architecture} 43 | \newcommand{\university}{University of Michigan, Ann Arbor} 44 | \newcommand{\labdate}{31$^{\text{st}}$ January, 2019} 45 | 46 | 47 | \lhead{ 48 | \small{ 49 | \university 50 | } 51 | } 52 | \rhead{ 53 | \small{ 54 | \emph{Date: \labdate} \hspace*{-1em} 55 | % Why is the above \hspace necessary? 56 | } 57 | } 58 | 59 | \newcommand{\shortbar}{ 60 | \vspace*{-12pt} 61 | \begin{center} 62 | \rule{5ex}{0.1pt} 63 | \end{center} 64 | } 65 | \newcommand{\lab}[1]{ 66 | \begin{center} 67 | \LARGE{ 68 | \vspace*{-32pt} 69 | EECS 470 Lab #1 Assignment 70 | \shortbar 71 | \vspace*{-20pt} 72 | } 73 | \end{center} 74 | } 75 | 76 | 77 | %***********************************************% 78 | % % 79 | % TikZ Definitions % 80 | % % 81 | %***********************************************% 82 | 83 | \usetikzlibrary{shapes,arrows} 84 | 85 | % Block Diagram Styles 86 | \tikzstyle{block} = [draw, fill=blue!20, rectangle, 87 | minimum height=3em, minimum width=6em] 88 | \tikzstyle{sum} = [draw, fill=blue!20, circle, node distance=2cm] 89 | \tikzstyle{input} = [coordinate] 90 | \tikzstyle{output} = [coordinate] 91 | \tikzstyle{branch} = [coordinate] 92 | \tikzstyle{pinstyle} = [pin edge={to-, thin, black}] 93 | 94 | % Signal Flow Graph Styles 95 | \tikzstyle{signal} = [draw, fill=blue!20, circle, 96 | minimum height=3em] 97 | \tikzstyle{state} = [draw, fill=blue!20, circle, 98 | minimum height=3em] 99 | 100 | %***********************************************% 101 | % % 102 | % Document % 103 | % % 104 | %***********************************************% 105 | 106 | \begin{document} 107 | \lab{4} 108 | 109 | \section*{Note:} 110 | \begin{itemize} 111 | \item The lab should be completed individually. 112 | \item The lab must be submitted by the end of Thursday office hours the 113 | following week and checked off by a GSI. 114 | \end{itemize} 115 | 116 | \section{Introduction} 117 | You have been supplied with three, obfuscated, buggy ISR modules. These modules 118 | should implement the ISR functionality from Project 2 correctly, however they 119 | are not quite right. The supplied ISRs are using a 4-cycle version of the 120 | pipelined multiplier. The module has the regular definition: 121 | 122 | \texttt{module ISR(reset, value, clock, result, done);} 123 | 124 | \section{Assignment} 125 | For this lab, you will need to write a testbench that will catch all the three 126 | buggy modules. Your testbench must use a task to check the solution of the ISR 127 | module (this is not that easy to do). See the testbenches from the previous labs 128 | if you do not remember how to write a task. 129 | 130 | In addition to catching the bugs, you must figure out what the source of each 131 | bug is. This will require you to think critically. Since you do not have access 132 | to the source of the module, you will have to look at its outputs and try to 133 | theorize what could be causing the errors you are seeing. This is not easy, you 134 | will have to think hard about how the ISR should work and how that compares to 135 | what you are seeing. 136 | 137 | \emph{Hint:} The bugs in \texttt{buggy1} and \texttt{buggy3} are in the ISR 138 | module. The bug in \texttt{buggy2} is in one of the submodules. 139 | 140 | 141 | \section{Submission} 142 | Unlike previous labs, we cannot autograde your lab. You will need to show it to 143 | one of the GSIs. In order to get your work checked off, you will need to type up 144 | explanations of the bugs and show the file to a GSI. Once you think you have 145 | identified and described the bugs, please add yourself to the help queue and 146 | mark that you wish to be checked off. 147 | 148 | \end{document} 149 | -------------------------------------------------------------------------------- /labs/lab4/lab4_part2.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/labs/lab4/lab4_part2.pptx -------------------------------------------------------------------------------- /labs/lab4/slides/beamercolorthemewolverine.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2004 by Madhusudan Singh 2 | % 3 | % This file may be distributed and/or modified 4 | % 5 | % 1. under the LaTeX Project Public License and/or 6 | % 2. under the GNU Public License. 7 | % 8 | % See the file doc/licenses/LICENSE for more details. 9 | 10 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/color/beamercolorthemewolverine.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 11 | 12 | \mode 13 | 14 | \definecolor{darkblue}{rgb}{0,0,0.8} 15 | 16 | \setbeamercolor{alerted text}{fg=red!85!black} 17 | \setbeamercolor*{palette primary}{fg=darkblue!60!black,bg=yellow!85!orange} 18 | \setbeamercolor*{palette secondary}{fg=darkblue!60!black,bg=yellow!85!orange} 19 | %\setbeamercolor*{palette secondary}{fg=darkblue!70!black,bg=yellow!60!orange} 20 | \setbeamercolor*{palette tertiary}{bg=darkblue!80!black,fg=yellow!50!orange} 21 | \setbeamercolor*{palette quaternary}{fg=darkblue,bg=yellow!20!orange} 22 | 23 | \setbeamercolor*{sidebar}{fg=darkblue,bg=orange!75!white} 24 | 25 | 26 | \setbeamercolor*{palette sidebar primary}{fg=darkblue!10!black} 27 | \setbeamercolor*{palette sidebar secondary}{fg=white} 28 | \setbeamercolor*{palette sidebar tertiary}{fg=darkblue!50!black} 29 | \setbeamercolor*{palette sidebar quaternary}{fg=yellow!10!orange} 30 | 31 | \setbeamercolor*{titlelike}{parent=palette primary} 32 | \setbeamercolor{frametitle}{bg=yellow!90!orange} 33 | \setbeamercolor{frametitle right}{bg=yellow!60!orange} 34 | 35 | \setbeamercolor*{separation line}{} 36 | \setbeamercolor*{fine separation line}{} 37 | 38 | \mode 39 | 40 | -------------------------------------------------------------------------------- /labs/lab4/slides/beamerthemeLab.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2014 William Cunningham 2 | % For use in U of M EECS 470 - Computer Architecture Labs 3 | % 4 | % This file may be distributed and/or modified 5 | % 6 | % 1. under the LaTeX Project Public License and/or 7 | % 2. under the GNU Public License. 8 | % 9 | % See the file doc/licenses/LICENSE for more details. 10 | 11 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/theme/beamerthemedLabs.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 12 | 13 | 14 | \mode 15 | 16 | \usefonttheme{default} 17 | \usecolortheme{wolverine} 18 | \useinnertheme{default} 19 | \useoutertheme{infolines} 20 | 21 | \mode 22 | 23 | -------------------------------------------------------------------------------- /labs/lab4/slides/example.txt: -------------------------------------------------------------------------------- 1 | [wcunning@dahak ~] $ git clone git@bitbucket.org:eecs470staff/course_material.git 2 | Cloning into 'course_material'... 3 | Warning: Permanently added the RSA host key for IP address '131.103.20.168' to the list of known hosts. 4 | remote: Counting objects: 183, done. 5 | remote: Compressing objects: 100% (166/166), done. 6 | remote: Total 183 (delta 39), reused 0 (delta 0) 7 | Receiving objects: 100% (183/183), 141.58 KiB | 0 bytes/s, done. 8 | Resolving deltas: 100% (39/39), done. 9 | Checking connectivity... done 10 | [wcunning@dahak Documents] $ cd course_material/ 11 | [wcunning@dahak project1] [master] $ vim projects/project1/testD.v 12 | [wcunning@dahak project1] [master *] $ git add projects/project1/testD.v 13 | [wcunning@dahak project1] [master +] $ git commit 14 | [master 4caae96] Updated Project 1 to use @(posedge clock); 15 | 1 file changed, 11 insertions(+), 11 deletions(-) 16 | [wcunning@dahak project1] [master] $ git push 17 | Counting objects: 10, done. 18 | Delta compression using up to 4 threads. 19 | Compressing objects: 100% (5/5), done. 20 | Writing objects: 100% (5/5), 544 bytes | 0 bytes/s, done. 21 | Total 5 (delta 3), reused 0 (delta 0) 22 | To git@bitbucket.org:eecs470staff/course_material.git 23 | da0cf7a..4caae96 master -> master 24 | -------------------------------------------------------------------------------- /labs/lab4/slides/script.txt: -------------------------------------------------------------------------------- 1 | [jbbeau@dahak ~] $ git clone git@bitbucket.org:eecs470staff/course_material.git 2 | Cloning into '.'... 3 | remote: Counting objects: 79, done. 4 | remote: Compressing objects: 100% (68/68), done. 5 | remote: Total 79 (delta 13), reused 0 (delta 0) 6 | Receiving objects: 100% (79/79), 79.99 KiB, done. 7 | Resolving deltas: 100% (13/13), done. 8 | [jbbeau@dahak slides] [master *] $ git status 9 | # On branch master 10 | # Changes not staged for commit: 11 | # (use "git add ..." to update what will be committed) 12 | # (use "git checkout -- ..." to discard changes in working directory) 13 | # 14 | # \color{Red}{modified: eecs470lab4slides.tex} 15 | # 16 | [jbbeau@dahak slides] [master *] $ git add eecs470lab4slides.tex 17 | [jbbeau@dahak slides] [master +] $ git status 18 | # On branch master 19 | # Changes to be committed: 20 | # (use git reset HEAD ..." to unstage 21 | # 22 | # \color{Green}{modified: eecs470lab4slides.tex} 23 | # 24 | [jbbeau@dahak slides] [master +] $ git commit 25 | [master f2ea0f5] Lab 4 diagram change 26 | 1 file changed, 1 insertion(+), 1 deletion(-) 27 | [jbbeau@dahak slides] [master] $ git push 28 | Counting objects: 11, done. 29 | Delta compression using up to 8 threads. 30 | Compressing objects: 100% (5/5), done. 31 | Writing objects: 100% (6/6), 475 bytes | 0 bytes/s, done. 32 | Total 6 (delta 3), reused 0 (delta 0) 33 | To git@bitbucket.org:eecs470staff/course_material.git 34 | 9a12490..f2ea0f5 master -> master 35 | [wcunning@mycroft-holmes course_material] [master] $ git pull 36 | remote: Counting objects: 13, done. 37 | remote: Compressing objects: 100% (7/7), done. 38 | remote: Total 8 (delta 2), reused 0 (delta 0) 39 | Unpacking objects: 100% (8/8), done. 40 | From bitbucket.org:eecs470staff/course_material 41 | 9a12490..f2ea0f5 master -> origin/master 42 | Already up-to-date. 43 | [wcunning@mycroft-holmes slides] [master *] $ git status 44 | # On branch master 45 | # Changes not staged for commit: 46 | # (use "git add/rm ..." to update what will be committed) 47 | # (use "git checkout -- ..." to discard changes in working directory) 48 | # 49 | # \color{Red}{deleted: beamerthemeLab.sty} 50 | # 51 | no changes added to commit (use "git add" and/or "git commit -a") 52 | [wcunning@mycroft-holmes slides] [master *] $ git reset --hard 53 | HEAD is now at f2ea0f5 Lab 4 diagram change 54 | [wcunning@mycroft-holmes slides] [master] $ git branch lab4 55 | [wcunning@mycroft-holmes slides] [master] $ git status 56 | On branch master 57 | Your branch is up-to-date with 'origin/master'. 58 | [wcunning@mycroft-holmes slides] [master] $ git checkout lab4 59 | Switched to branch 'lab4' 60 | [wcunning@mycroft-holmes slides] [lab4 *] $ git status 61 | # On branch lab4 62 | # Changes not staged for commit: 63 | # (use "git add ..." to update what will be committed) 64 | # (use "git checkout -- ..." to discard changes in working directory) 65 | # 66 | # \color{Red}{modified: eecs470lab4slides.tex} 67 | # 68 | [wcunning@mycroft-holmes slides] [lab4 *] $ git add eecs470lab4slides.tex 69 | [wcunning@mycroft-holmes slides] [lab4 +] $ git commit 70 | [lab4 b73416d] Better lab4slides skeleton/outline 71 | 1 file changed, 137 insertions(+) 72 | [wcunning@dahak slides] [lab4] $ git push origin lab4 73 | Counting objects: 11, done. 74 | Delta compression using up to 8 threads. 75 | Compressing objects: 100% (5/5), done. 76 | Writing objects: 100% (6/6), 758 bytes | 0 bytes/s, done. 77 | Total 6 (delta 3), reused 0 (delta 0) 78 | To git@bitbucket.org:eecs470staff/course_material.git 79 | * [new branch] lab4 -> lab4 80 | [wcunning@mycroft-holmes slides] [lab4 *] $ git stash 81 | Saved working directory and index state WIP on lab4: 25cbbce Added .gitignore for LaTeX files, along 82 | with changes to the git slides and date updates to the assignment 83 | HEAD is now at 25cbbce Added .gitignore for LaTeX files, along with changes to the git slides 84 | [wcunning@mycroft-holmes slides] [lab4 $] $ git checkout master 85 | Switched to branch 'master' 86 | Your branch is up-to-date with 'origin/master'. 87 | [wcunning@mycroft-holmes slides] [master $] $ git merge lab4 88 | Updating f2ea0f5..25cbbce 89 | Fast-forward 90 | .gitignore | 68 \color{Green}{+++++++} 91 | labs/lab4/assignment/tex/eecs470lab4assignment.tex | 2 \color{Green}{+}\color{Red}{-} 92 | labs/lab4/slides/eecs470lab4slides.tex | 613 \color{Green}{++++++++++++++++++++} 93 | labs/lab4/slides/script.txt | 148 \color{Green}{++++++++++++++} 94 | labs/lab4/slides/ssh-keygen.txt | 21 \color{Green}{++} 95 | 5 files changed, 841 insertions(+), 11 deletions(-) 96 | create mode 100644 .gitignore 97 | create mode 100644 labs/lab4/slides/script.txt 98 | create mode 100644 labs/lab4/slides/ssh-keygen.txt 99 | [wcunning@mycroft-holmes slides] [master $] $ git stash pop 100 | On branch master 101 | Your branch is ahead of 'origin/master' by 3 commits. 102 | (use "git push" to publish your local commits) 103 | 104 | Changes not staged for commit: 105 | (use "git add ..." to update what will be committed) 106 | (use "git checkout -- ..." to discard changes in working directory) 107 | 108 | modified: eecs470lab4slides.tex 109 | 110 | Untracked files: 111 | (use "git add ..." to include in what will be committed) 112 | 113 | ../../lab2/slides/.eecs470lab2slides.tex.swx 114 | ../assignment/source/ 115 | eecs470project3slides.tex 116 | figs/ 117 | project3/ 118 | ../../../projects/ 119 | 120 | no changes added to commit (use "git add" and/or "git commit -a") 121 | Dropped refs/stash@{0} (fe1617fa8d1fa972b942a76555a9c20340719712) 122 | 123 | [wcunning@mycroft-holmes w14] [master] $ git tag -a lab4-release HEAD 124 | [wcunning@mycroft-holmes w14] [master] $ git push origin lab4-release 125 | Counting objects: 1, done. 126 | Writing objects: 100% (1/1), 187 bytes | 0 bytes/s, done. 127 | Total 1 (delta 0), reused 0 (delta 0) 128 | To git@bitbucket.org:eecs470staff/course_material.git 129 | * [new tag] lab4-release -> lab4-release 130 | [wcunning@mycroft-holmes w14] [master] $ git tag -l 131 | lab4-release 132 | -------------------------------------------------------------------------------- /labs/lab4/slides/ssh-keygen.txt: -------------------------------------------------------------------------------- 1 | [wcunning@dahak ~] $ ssh-keygen -t rsa -b 4096 2 | Generating public/private rsa key pair. 3 | Enter file in which to save the key (/home/wcunning/.ssh/id_rsa): 4 | Enter passphrase (empty for no passphrase): 5 | Enter same passphrase again: 6 | Your identification has been saved in /home/wcunning/.ssh/id_rsa. 7 | Your public key has been saved in /home/wcunning/.ssh/id_rsa.pub. 8 | The key fingerprint is: 9 | 3f:91:f9:7f:d7:be:4e:62:56:27:88:1d:3a:5d:b4:56 wcunning@dahak 10 | The key's randomart image is: 11 | +--[ RSA 4096]----+ 12 | | . E| 13 | | . o | 14 | | . + | 15 | | B = | 16 | | S B + ...| 17 | | . + ...| 18 | | o .+ ..| 19 | | .o.o +| 20 | | o=+| 21 | +-----------------+ 22 | -------------------------------------------------------------------------------- /labs/lab5/assignment/tex/eecs470lab5assignment.tex: -------------------------------------------------------------------------------- 1 | %***********************************************% 2 | % % 3 | % EECS 470 - Lab 04 % 4 | %<------------------> % 5 | % Last Modified by: % 6 | % William Cunningham on 2013-12-25 % 7 | % % 8 | %***********************************************% 9 | 10 | %***********************************************% 11 | % Preamble % 12 | %***********************************************% 13 | 14 | \documentclass[dvipsnames]{article} 15 | 16 | \usepackage{ 17 | tikz, 18 | xcolor, 19 | colortbl, 20 | graphicx, 21 | amsmath, 22 | amssymb, 23 | float, 24 | siunitx, 25 | fancyhdr, 26 | hyperref, 27 | cleveref, 28 | minted 29 | } 30 | 31 | \usepackage 32 | [left=1in,top=1in,right=1in,bottom=1in] 33 | {geometry} 34 | 35 | \pagestyle{fancy} 36 | \raggedright 37 | 38 | %--- Header ---% 39 | 40 | \newcommand{\courseNumber}{EECS 470} 41 | \newcommand{\courseTitle}{Computer Architecture} 42 | \newcommand{\university}{University of Michigan, Ann Arbor} 43 | \newcommand{\labdate}{3$^{\text{rd}}$ October, 2019} 44 | 45 | 46 | \lhead{ 47 | \small{ 48 | \university 49 | } 50 | } 51 | \rhead{ 52 | \small{ 53 | \emph{Date: \labdate} \hspace*{-1em} 54 | % Why is the above \hspace necessary? 55 | } 56 | } 57 | 58 | \newcommand{\shortbar}{ 59 | \vspace*{-12pt} 60 | \begin{center} 61 | \rule{5ex}{0.1pt} 62 | \end{center} 63 | } 64 | \newcommand{\lab}[1]{ 65 | \begin{center} 66 | \LARGE{ 67 | \vspace*{-32pt} 68 | EECS 470 Lab #1 Assignment 69 | \shortbar 70 | \vspace*{-20pt} 71 | } 72 | \end{center} 73 | } 74 | 75 | 76 | %***********************************************% 77 | % % 78 | % TikZ Definitions % 79 | % % 80 | %***********************************************% 81 | 82 | \usetikzlibrary{shapes,arrows} 83 | 84 | % Block Diagram Styles 85 | \tikzstyle{block} = [draw, fill=blue!20, rectangle, 86 | minimum height=3em, minimum width=6em] 87 | \tikzstyle{sum} = [draw, fill=blue!20, circle, node distance=2cm] 88 | \tikzstyle{input} = [coordinate] 89 | \tikzstyle{output} = [coordinate] 90 | \tikzstyle{branch} = [coordinate] 91 | \tikzstyle{pinstyle} = [pin edge={to-, thin, black}] 92 | 93 | % Signal Flow Graph Styles 94 | \tikzstyle{signal} = [draw, fill=blue!20, circle, 95 | minimum height=3em] 96 | \tikzstyle{state} = [draw, fill=blue!20, circle, 97 | minimum height=3em] 98 | 99 | %***********************************************% 100 | % % 101 | % Document % 102 | % % 103 | %***********************************************% 104 | 105 | \begin{document} 106 | \lab{5} 107 | 108 | \section*{Note:} 109 | \begin{itemize} 110 | \item The lab should be completed individually. 111 | \item The lab must be submitted by the end of Friday the 112 | following week and checked off by a GSI. 113 | \end{itemize} 114 | 115 | \section{Introduction} 116 | You have just learned about the BASH shell and some of the useful utilities 117 | provided by the standard GNU/Linux environment. Today you will be using this 118 | knowledge to automate the testing of Project 3. The general form of this script 119 | will closely resemble the actual Project 3 Autograder, though there are a number 120 | of additional testcases which are not released to you. 121 | 122 | \section{Assignment} 123 | You are required to automatically check that a modified version of the 124 | Verisimple pipeline produces correct output. The following parts lay out how we 125 | recommend you do this, but you are free to do this however you would like. 126 | 127 | \subsection{Ground Truth} 128 | \label{sec:truth} 129 | First, we need a \emph{ground truth}, a set of known-correct outputs. To build 130 | this, you should write a simple script to loop through files in a directory (the 131 | assembly testcases) and call a command or commands on each of them. This should 132 | look something like: 133 | 134 | \inputminted[frame=lines]{bash}{scripts/ground-truth-skeleton.sh} 135 | 136 | \subsection{Testing} 137 | Now that you have a script that generates some ground truth data, it is time to 138 | modify it to compare that data with the output of some unknown version of the 139 | Verisimple pipeline. This will be done in several steps. 140 | 141 | First, you will need to run the script you wrote in \cref{sec:truth} to generate 142 | your ground truth. Then, you will need to make sure the executable you are 143 | running is up-to-date. After that, for each of your testcases you will need to 144 | \begin{itemize} 145 | \item Simulate the testcase. Do you need to rebuild the executable 146 | for this? 147 | \item Check that the \texttt{writeback.out} files match exactly with 148 | the ground truth version. What utility does this? 149 | \item Check that the lines beginning with \texttt{@@@} in the 150 | \texttt{program.out} files match exactly. What utility lets us 151 | find only these lines, before using the one from above to 152 | compare? 153 | \item Print whether the testcase passed or failed. 154 | \end{itemize} 155 | 156 | \section{Check Off} 157 | In order to get your work checked off, you will need to show your \textbf{well-commented} 158 | scripts to a GSI. Once you think you have your scripts working, please add 159 | yourself to the help queue and mark that you wish to be checked off. While you 160 | wait, you might consider implementing one of the optional features listed below 161 | or working on the project itself. 162 | 163 | \textbf{In addition, you also need to show your git repository of project 3 and grant Admin access to the account \texttt{eecs470staff@umich.edu}.} 164 | 165 | \appendix 166 | 167 | \section{Optional Features} 168 | This was a very basic version of this script, and we can improve it 169 | significantly from here forward. Here are a few things you could do to make this 170 | script better/prettier/more useful for the final project\dots 171 | 172 | \begin{itemize} 173 | \item Use BASH functions to modularize this script. I would recommend adding 174 | this to your \texttt{.bash\_profile} so that you can call (e.g. 175 | \texttt{source .test.bash}). 176 | \item Colorize your output. I find it more satisfying to read something like 177 | \textcolor{Green}{\texttt{PASSED}} than to read \texttt{PASSED} without the 178 | color. The Linux Documentation Project has a good description of 179 | \href{http://www.tldp.org/HOWTO/Bash-Prompt-HOWTO/x329.html}{BASH colors}. 180 | \item You may want to move some significant portion of the handling of the 181 | testcases/assembly files into the Makefile/test bench. For instance, the 182 | \texttt{\$readmemh} command in the test bench can be pointed at a file 183 | provided by a \texttt{\`{}define}, which in turn can be provided by an 184 | environment variable/Makefile macro. The dependency resolution 185 | capabilities of make is also very useful for making sure that you are 186 | running the right test case. 187 | \item Detecting and killing infinite loops or hung simulations is extremely 188 | useful, but also very hard. 189 | \end{itemize} 190 | 191 | \end{document} 192 | -------------------------------------------------------------------------------- /labs/lab5/assignment/tex/scripts/ground-truth-skeleton.sh: -------------------------------------------------------------------------------- 1 | for file in test_progs/*.s; do 2 | file=$(echo $file | cut -d'.' -f1) 3 | echo "Assembling $file" 4 | # How do you assemble a testcase? 5 | echo "Running $file" 6 | # How do you run a testcase? 7 | echo "Saving $file output" 8 | # How do you want to save the output? 9 | # What files do you want to save? 10 | done 11 | -------------------------------------------------------------------------------- /labs/lab5/slides/beamercolorthemewolverine.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2004 by Madhusudan Singh 2 | % 3 | % This file may be distributed and/or modified 4 | % 5 | % 1. under the LaTeX Project Public License and/or 6 | % 2. under the GNU Public License. 7 | % 8 | % See the file doc/licenses/LICENSE for more details. 9 | 10 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/color/beamercolorthemewolverine.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 11 | 12 | \mode 13 | 14 | \definecolor{darkblue}{rgb}{0,0,0.8} 15 | 16 | \setbeamercolor{alerted text}{fg=red!85!black} 17 | \setbeamercolor*{palette primary}{fg=darkblue!60!black,bg=yellow!85!orange} 18 | \setbeamercolor*{palette secondary}{fg=darkblue!60!black,bg=yellow!85!orange} 19 | %\setbeamercolor*{palette secondary}{fg=darkblue!70!black,bg=yellow!60!orange} 20 | \setbeamercolor*{palette tertiary}{bg=darkblue!80!black,fg=yellow!50!orange} 21 | \setbeamercolor*{palette quaternary}{fg=darkblue,bg=yellow!20!orange} 22 | 23 | \setbeamercolor*{sidebar}{fg=darkblue,bg=orange!75!white} 24 | 25 | 26 | \setbeamercolor*{palette sidebar primary}{fg=darkblue!10!black} 27 | \setbeamercolor*{palette sidebar secondary}{fg=white} 28 | \setbeamercolor*{palette sidebar tertiary}{fg=darkblue!50!black} 29 | \setbeamercolor*{palette sidebar quaternary}{fg=yellow!10!orange} 30 | 31 | \setbeamercolor*{titlelike}{parent=palette primary} 32 | \setbeamercolor{frametitle}{bg=yellow!90!orange} 33 | \setbeamercolor{frametitle right}{bg=yellow!60!orange} 34 | 35 | \setbeamercolor*{separation line}{} 36 | \setbeamercolor*{fine separation line}{} 37 | 38 | \mode 39 | 40 | -------------------------------------------------------------------------------- /labs/lab5/slides/beamerthemeLab.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2014 William Cunningham 2 | % For use in U of M EECS 470 - Computer Architecture Labs 3 | % 4 | % This file may be distributed and/or modified 5 | % 6 | % 1. under the LaTeX Project Public License and/or 7 | % 2. under the GNU Public License. 8 | % 9 | % See the file doc/licenses/LICENSE for more details. 10 | 11 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/theme/beamerthemedLabs.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 12 | 13 | 14 | \mode 15 | 16 | \usefonttheme{default} 17 | \usecolortheme{wolverine} 18 | \useinnertheme{default} 19 | \useoutertheme{infolines} 20 | 21 | \mode 22 | 23 | -------------------------------------------------------------------------------- /labs/lab6/assignment/lab6/Makefile: -------------------------------------------------------------------------------- 1 | # make <- runs simv (after compiling simv if needed) 2 | # make simv <- compile simv if needed (but do not run) 3 | # make syn <- runs syn_simv (after synthesizing if needed then 4 | # compiling synsimv if needed) 5 | # make clean <- remove files created during compilations (but not synthesis) 6 | # make nuke <- remove all files created during compilation and synthesis 7 | # 8 | # To compile additional files, add them to the TESTBENCH or SIMFILES as needed 9 | # Every .vg file will need its own rule and one or more synthesis scripts 10 | # The information contained here (in the rules for those vg files) will be 11 | # similar to the information in those scripts but that seems hard to avoid. 12 | # 13 | 14 | VCS = SW_VCS=2012.09 vcs -sverilog +vc -Mupdate -line -full64 +define+TEST_SIZE=$(CAM_SIZE) 15 | 16 | all: simv 17 | ./simv | tee program.out 18 | 19 | ##### 20 | # Modify starting here 21 | ##### 22 | 23 | TESTBENCH = sys_defs.vh test.v 24 | SIMFILES = cam.v 25 | SYNFILES = CAM.vg CAM_svsim.sv 26 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 27 | 28 | CAM.vg: cam.v cam.tcl 29 | dc_shell-t -f cam.tcl | tee synth.out 30 | 31 | ##### 32 | # Should be no need to modify after here 33 | ##### 34 | 35 | dve: $(SIMFILES) $(TESTBENCH) 36 | $(VCS) +memcbk $(TESTBENCH) $(SIMFILES) -o dve -R -gui 37 | 38 | dve_syn: $(SYNFILES) $(TESTBENCH) 39 | $(VCS) $(TESTBENCH) $(SYNFILES) $(LIB) +define+SYNTH_TEST -o syn_simv -R -gui 40 | 41 | simv: $(SIMFILES) $(TESTBENCH) 42 | $(VCS) $(TESTBENCH) $(SIMFILES) -o simv 43 | 44 | syn_simv: $(SYNFILES) $(TESTBENCH) 45 | $(VCS) $(TESTBENCH) $(SYNFILES) $(LIB) +define+SYNTH_TEST -o syn_simv 46 | 47 | syn: syn_simv 48 | ./syn_simv | tee syn_program.out 49 | 50 | clean: 51 | rm -rvf simv *.daidir csrc vcs.key program.out \ 52 | syn_simv syn_simv.daidir syn_program.out \ 53 | dve *.vpd *.vcd *.dump ucli.key 54 | 55 | nuke: clean 56 | rm -rvf *.vg *.rep *.db *.chk *.log *.out DVEfiles/ *.ddc *.res *_svsim.sv default.svf *.vdb 57 | -------------------------------------------------------------------------------- /labs/lab6/assignment/lab6/cam.tcl: -------------------------------------------------------------------------------- 1 | set search_path [ list "./" "/afs/umich.edu/class/eecs470/lib/synopsys/" ] 2 | set target_library "lec25dscc25_TT.db" 3 | set link_library [concat "*" $target_library] 4 | 5 | #/***********************************************************/ 6 | #/* Set some flags to suppress warnings we don't care about */ 7 | set suppress_errors [concat $suppress_errors "UID-401"] 8 | suppress_message {"VER-130"} 9 | 10 | #/***********************************************************/ 11 | #/* The following lines are set from environment variables 12 | #/* automatically by the Makefile 13 | #/***********************************************************/ 14 | lappend search_path ../ 15 | 16 | read_file -f sverilog [list sys_defs.vh cam.v] 17 | set design_name CAM 18 | set clock_name clock 19 | set reset_name reset 20 | set CLK_PERIOD 10 21 | 22 | 23 | #/***********************************************************/ 24 | #/* The rest of this file may be left alone for most small */ 25 | #/* to moderate sized designs. You may need to alter it */ 26 | #/* when synthesizing your final project. */ 27 | #/***********************************************************/ 28 | set SYN_DIR ./ 29 | 30 | #/***********************************************************/ 31 | #/* Set some flags for optimisation */ 32 | 33 | set compile_top_all_paths "true" 34 | set auto_wire_load_selection "false" 35 | set compile_seqmap_synchronous_extraction "true" 36 | 37 | # uncomment this and change number appropriately if on multi-core machine 38 | #set_host_options -max_cores 2 39 | 40 | #/***********************************************************/ 41 | #/* Clk Periods/uncertainty/transition */ 42 | 43 | set CLK_TRANSITION 0.1 44 | set CLK_UNCERTAINTY 0.1 45 | set CLK_LATENCY 0.1 46 | 47 | #/* Input/output Delay values */ 48 | set AVG_INPUT_DELAY 0.1 49 | set AVG_OUTPUT_DELAY 0.1 50 | 51 | #/* Critical Range (ns) */ 52 | set CRIT_RANGE 1.0 53 | 54 | #/***********************************************************/ 55 | #/* Design Constrains: Not all used */ 56 | set MAX_TRANSITION 1.0 57 | set FAST_TRANSITION 0.1 58 | set MAX_FANOUT 32 59 | set MID_FANOUT 8 60 | set LOW_FANOUT 1 61 | set HIGH_DRIVE 0 62 | set HIGH_LOAD 1.0 63 | set AVG_LOAD 0.1 64 | set AVG_FANOUT_LOAD 10 65 | 66 | #/***********************************************************/ 67 | #/*BASIC_INPUT = cb18os120_tsmc_max/nd02d1/A1 68 | #BASIC_OUTPUT = cb18os120_tsmc_max/nd02d1/ZN*/ 69 | 70 | set DRIVING_CELL dffacs1 71 | 72 | #/* DONT_USE_LIST = { } */ 73 | 74 | #/*************operation cons**************/ 75 | #/*OP_WCASE = WCCOM; 76 | #OP_BCASE = BCCOM;*/ 77 | set WIRE_LOAD "tsmcwire" 78 | set LOGICLIB lec25dscc25_TT 79 | #/*****************************/ 80 | 81 | #/* Sourcing the file that sets the Search path and the libraries(target,link) */ 82 | 83 | set sys_clk $clock_name 84 | 85 | set netlist_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".vg"] 86 | set svsim_file [format "%s%s%s" $SYN_DIR $design_name "_svsim.sv"] 87 | set ddc_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".ddc"] 88 | set rep_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".rep"] 89 | set res_file [format "%s%s%s" $SYN_DIR $design_name ".res"] 90 | set dc_shell_status [ set chk_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".chk"] ] 91 | 92 | #/* if we didnt find errors at this point, run */ 93 | if { $dc_shell_status != [list] } { 94 | current_design $design_name 95 | link 96 | set_wire_load_model -name $WIRE_LOAD -lib $LOGICLIB $design_name 97 | set_wire_load_mode top 98 | set_fix_multiple_port_nets -outputs -buffer_constants 99 | create_clock -period $CLK_PERIOD -name $sys_clk [find port $sys_clk] 100 | set_clock_uncertainty $CLK_UNCERTAINTY $sys_clk 101 | set_fix_hold $sys_clk 102 | group_path -from [all_inputs] -name input_grp 103 | group_path -to [all_outputs] -name output_grp 104 | set_driving_cell -lib_cell $DRIVING_CELL [all_inputs] 105 | remove_driving_cell [find port $sys_clk] 106 | set_fanout_load $AVG_FANOUT_LOAD [all_outputs] 107 | set_load $AVG_LOAD [all_outputs] 108 | set_input_delay $AVG_INPUT_DELAY -clock $sys_clk [all_inputs] 109 | remove_input_delay -clock $sys_clk [find port $sys_clk] 110 | set_output_delay $AVG_OUTPUT_DELAY -clock $sys_clk [all_outputs] 111 | set_dont_touch $reset_name 112 | set_resistance 0 $reset_name 113 | set_drive 0 $reset_name 114 | set_critical_range $CRIT_RANGE [current_design] 115 | set_max_delay $CLK_PERIOD [all_outputs] 116 | set MAX_FANOUT $MAX_FANOUT 117 | set MAX_TRANSITION $MAX_TRANSITION 118 | uniquify 119 | ungroup -all -flatten 120 | redirect $chk_file { check_design } 121 | compile -map_effort medium 122 | write -hier -format verilog -output $netlist_file $design_name 123 | write -hier -format ddc -output $ddc_file $design_name 124 | write -format svsim -output $svsim_file $design_name 125 | redirect $rep_file { report_design -nosplit } 126 | redirect -append $rep_file { report_area } 127 | redirect -append $rep_file { report_timing -max_paths 2 -input_pins -nets -transition_time -nosplit } 128 | redirect -append $rep_file { report_constraint -max_delay -verbose -nosplit } 129 | redirect $res_file { report_resources -hier } 130 | remove_design -all 131 | read_file -format verilog $netlist_file 132 | current_design $design_name 133 | redirect -append $rep_file { report_reference -nosplit } 134 | quit 135 | } else { 136 | quit 137 | } 138 | 139 | 140 | -------------------------------------------------------------------------------- /labs/lab6/assignment/lab6/cam.v: -------------------------------------------------------------------------------- 1 | module CAM #(parameter SIZE=8) ( 2 | 3 | input clock, reset, 4 | input enable, 5 | 6 | input COMMAND command, 7 | 8 | input [31:0] data, 9 | 10 | input [$clog2(SIZE)-1:0] write_idx, 11 | 12 | output logic [$clog2(SIZE)-1:0] read_idx, 13 | output logic hit 14 | ); 15 | 16 | // Fill in design here 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /labs/lab6/assignment/lab6/check.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | for i in 4 8 15 16 23 42 4 | do 5 | echo "Running simulation of CAM with size $i" 6 | export CAM_SIZE=$i 7 | make clean simv &> /dev/null 8 | ./simv | grep "@@@" 9 | done 10 | 11 | echo "Running synthesis" 12 | export CAM_SIZE=8 13 | make nuke syn_simv &> /dev/null 14 | ./syn_simv | grep "@@@" 15 | 16 | -------------------------------------------------------------------------------- /labs/lab6/assignment/lab6/sys_defs.vh: -------------------------------------------------------------------------------- 1 | `ifndef __SYS_DEFS_VH__ 2 | `define __SYS_DEFS_VH__ 3 | 4 | `ifdef SYNTH_TEST 5 | `define DUT(mod) mod``_svsim 6 | `else 7 | `define DUT(mod) mod 8 | `endif 9 | 10 | typedef enum logic {READ, WRITE} COMMAND; 11 | 12 | `define TEST_SIZE 8 13 | 14 | `endif -------------------------------------------------------------------------------- /labs/lab6/assignment/lab6/test.v: -------------------------------------------------------------------------------- 1 | module testbench; 2 | logic clock, reset, enable; 3 | 4 | logic [31:0] data; 5 | COMMAND command; 6 | 7 | logic [$clog2(`TEST_SIZE)-1:0] write_idx, read_idx; 8 | logic hit; 9 | `DUT(CAM) #(.SIZE(`TEST_SIZE)) dut (.clock, .reset, .enable, .command, .write_idx, .read_idx, .data, .hit); 10 | 11 | always #5 clock = ~clock; 12 | 13 | task exit_on_error; 14 | begin 15 | #1; 16 | $display("@@@Failed at time %f", $time); 17 | $finish; 18 | end 19 | endtask 20 | 21 | initial begin 22 | 23 | $monitor("Command: %s, enable: %b, data: %h, write_idx: %h, read_idx: %h, hit: %b", command.name, enable, data, write_idx, read_idx, hit); 24 | 25 | clock = 0; 26 | write_idx = 0; 27 | enable = 0; 28 | command = READ; 29 | data = 0; 30 | 31 | /***RESET***/ 32 | reset = 1; 33 | @(negedge clock) 34 | reset = 0; 35 | 36 | /***CHECK THAT ALL ELEMENTS ARE INVALID***/ 37 | @(negedge clock); 38 | assert(!hit) else #1 exit_on_error; 39 | 40 | /***INITIALIZE MEMORY****/ 41 | command = WRITE; 42 | enable = 1; 43 | for(int i=0; i<`TEST_SIZE; i++) begin 44 | write_idx = i; 45 | data = $random; 46 | @(negedge clock); 47 | end 48 | 49 | /***OVERWRITE***/ 50 | for(int i=0; i<(2**$clog2(`TEST_SIZE)); i++) begin 51 | write_idx = i; 52 | data = i; 53 | @(negedge clock); 54 | end 55 | 56 | /***READ VALUES***/ 57 | command = READ; 58 | for(int i=0; i<`TEST_SIZE; i++) begin 59 | data = i; 60 | @(negedge clock); 61 | assert(hit && read_idx == i) else exit_on_error; 62 | end 63 | 64 | /***CHECK SIZE***/ 65 | data = `TEST_SIZE; 66 | @(negedge clock); 67 | assert(!hit) else #1 exit_on_error; 68 | 69 | /***TEST WITH MULTIPLE COPIES OF VALUE***/ 70 | command = WRITE; 71 | data = $random; 72 | write_idx = 0; 73 | @(negedge clock); 74 | repeat(5) begin 75 | write_idx = $random; 76 | @(negedge clock); 77 | end 78 | 79 | command = READ; 80 | @(negedge clock); 81 | assert(read_idx == 0) else exit_on_error; 82 | 83 | 84 | $display("@@@Passed"); 85 | $finish; 86 | 87 | end 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /labs/lab6/assignment/lab6/top.tcl: -------------------------------------------------------------------------------- 1 | set search_path [ list "./" "/afs/umich.edu/class/eecs470/lib/synopsys/" ] 2 | set target_library "lec25dscc25_TT.db" 3 | set link_library [concat "*" $target_library] 4 | 5 | #/***********************************************************/ 6 | #/* Set some flags to suppress warnings we don't care about */ 7 | set suppress_errors [concat $suppress_errors "UID-401"] 8 | suppress_message {"VER-130"} 9 | 10 | #/***********************************************************/ 11 | #/* The following lines are set from environment variables 12 | #/* automatically by the Makefile 13 | #/***********************************************************/ 14 | lappend search_path ../ 15 | 16 | read_file -f sverilog [list sys_defs.vh top.v CAM.vg CAM_svsim.sv] 17 | set_dont_touch CAM 18 | set design_name top 19 | set clock_name clock 20 | set reset_name reset 21 | set CLK_PERIOD 10 22 | 23 | 24 | #/***********************************************************/ 25 | #/* The rest of this file may be left alone for most small */ 26 | #/* to moderate sized designs. You may need to alter it */ 27 | #/* when synthesizing your final project. */ 28 | #/***********************************************************/ 29 | set SYN_DIR ./ 30 | 31 | #/***********************************************************/ 32 | #/* Set some flags for optimisation */ 33 | 34 | set compile_top_all_paths "true" 35 | set auto_wire_load_selection "false" 36 | set compile_seqmap_synchronous_extraction "true" 37 | 38 | # uncomment this and change number appropriately if on multi-core machine 39 | #set_host_options -max_cores 2 40 | 41 | #/***********************************************************/ 42 | #/* Clk Periods/uncertainty/transition */ 43 | 44 | set CLK_TRANSITION 0.1 45 | set CLK_UNCERTAINTY 0.1 46 | set CLK_LATENCY 0.1 47 | 48 | #/* Input/output Delay values */ 49 | set AVG_INPUT_DELAY 0.1 50 | set AVG_OUTPUT_DELAY 0.1 51 | 52 | #/* Critical Range (ns) */ 53 | set CRIT_RANGE 1.0 54 | 55 | #/***********************************************************/ 56 | #/* Design Constrains: Not all used */ 57 | set MAX_TRANSITION 1.0 58 | set FAST_TRANSITION 0.1 59 | set MAX_FANOUT 32 60 | set MID_FANOUT 8 61 | set LOW_FANOUT 1 62 | set HIGH_DRIVE 0 63 | set HIGH_LOAD 1.0 64 | set AVG_LOAD 0.1 65 | set AVG_FANOUT_LOAD 10 66 | 67 | #/***********************************************************/ 68 | #/*BASIC_INPUT = cb18os120_tsmc_max/nd02d1/A1 69 | #BASIC_OUTPUT = cb18os120_tsmc_max/nd02d1/ZN*/ 70 | 71 | set DRIVING_CELL dffacs1 72 | 73 | #/* DONT_USE_LIST = { } */ 74 | 75 | #/*************operation cons**************/ 76 | #/*OP_WCASE = WCCOM; 77 | #OP_BCASE = BCCOM;*/ 78 | set WIRE_LOAD "tsmcwire" 79 | set LOGICLIB lec25dscc25_TT 80 | #/*****************************/ 81 | 82 | #/* Sourcing the file that sets the Search path and the libraries(target,link) */ 83 | 84 | set sys_clk $clock_name 85 | 86 | set netlist_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".vg"] 87 | set svsim_file [format "%s%s%s" $SYN_DIR $design_name "_svsim.sv"] 88 | set ddc_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".ddc"] 89 | set rep_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".rep"] 90 | set res_file [format "%s%s%s" $SYN_DIR $design_name ".res"] 91 | set dc_shell_status [ set chk_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".chk"] ] 92 | 93 | #/* if we didnt find errors at this point, run */ 94 | if { $dc_shell_status != [list] } { 95 | current_design $design_name 96 | link 97 | set_wire_load_model -name $WIRE_LOAD -lib $LOGICLIB $design_name 98 | set_wire_load_mode top 99 | set_fix_multiple_port_nets -outputs -buffer_constants 100 | create_clock -period $CLK_PERIOD -name $sys_clk [find port $sys_clk] 101 | set_clock_uncertainty $CLK_UNCERTAINTY $sys_clk 102 | set_fix_hold $sys_clk 103 | group_path -from [all_inputs] -name input_grp 104 | group_path -to [all_outputs] -name output_grp 105 | set_driving_cell -lib_cell $DRIVING_CELL [all_inputs] 106 | remove_driving_cell [find port $sys_clk] 107 | set_fanout_load $AVG_FANOUT_LOAD [all_outputs] 108 | set_load $AVG_LOAD [all_outputs] 109 | set_input_delay $AVG_INPUT_DELAY -clock $sys_clk [all_inputs] 110 | remove_input_delay -clock $sys_clk [find port $sys_clk] 111 | set_output_delay $AVG_OUTPUT_DELAY -clock $sys_clk [all_outputs] 112 | set_dont_touch $reset_name 113 | set_resistance 0 $reset_name 114 | set_drive 0 $reset_name 115 | set_critical_range $CRIT_RANGE [current_design] 116 | set_max_delay $CLK_PERIOD [all_outputs] 117 | set MAX_FANOUT $MAX_FANOUT 118 | set MAX_TRANSITION $MAX_TRANSITION 119 | uniquify 120 | ungroup -all -flatten 121 | redirect $chk_file { check_design } 122 | compile -map_effort medium 123 | write -hier -format verilog -output $netlist_file $design_name 124 | write -hier -format ddc -output $ddc_file $design_name 125 | write -format svsim -output $svsim_file $design_name 126 | redirect $rep_file { report_design -nosplit } 127 | redirect -append $rep_file { report_area } 128 | redirect -append $rep_file { report_timing -max_paths 2 -input_pins -nets -transition_time -nosplit } 129 | redirect -append $rep_file { report_constraint -max_delay -verbose -nosplit } 130 | redirect $res_file { report_resources -hier } 131 | remove_design -all 132 | read_file -format verilog $netlist_file 133 | current_design $design_name 134 | redirect -append $rep_file { report_reference -nosplit } 135 | quit 136 | } else { 137 | quit 138 | } 139 | 140 | 141 | -------------------------------------------------------------------------------- /labs/lab6/assignment/solution/cam.v: -------------------------------------------------------------------------------- 1 | module CAM #(parameter SIZE=8) ( 2 | 3 | input clock, reset, 4 | input enable, 5 | 6 | input COMMAND command, 7 | 8 | input [31:0] data, 9 | 10 | input [$clog2(SIZE)-1:0] write_idx, 11 | 12 | output logic [$clog2(SIZE)-1:0] read_idx, 13 | output logic hit 14 | ); 15 | 16 | logic [SIZE-1:0] [31:0] content; 17 | logic [SIZE-1:0] valid; 18 | 19 | always_ff @(posedge clock) begin 20 | if(reset) begin 21 | for(int i=0; i /dev/null 8 | ./simv | grep "@@@" 9 | done 10 | 11 | echo "Running synthesis" 12 | export CAM_SIZE=8 13 | make nuke syn_simv &> /dev/null 14 | ./syn_simv | grep "@@@" 15 | 16 | -------------------------------------------------------------------------------- /labs/lab6/assignment/source/sys_defs.vh: -------------------------------------------------------------------------------- 1 | `ifndef __SYS_DEFS_VH__ 2 | `define __SYS_DEFS_VH__ 3 | 4 | `ifdef SYNTH_TEST 5 | `define DUT(mod) mod``_svsim 6 | `else 7 | `define DUT(mod) mod 8 | `endif 9 | 10 | typedef enum logic {READ, WRITE} COMMAND; 11 | 12 | `define TEST_SIZE 8 13 | 14 | `endif -------------------------------------------------------------------------------- /labs/lab6/assignment/source/test.v: -------------------------------------------------------------------------------- 1 | module testbench; 2 | logic clock, reset, enable; 3 | 4 | logic [31:0] data; 5 | COMMAND command; 6 | 7 | logic [$clog2(`TEST_SIZE)-1:0] write_idx, read_idx; 8 | logic hit; 9 | `DUT(CAM) #(.SIZE(`TEST_SIZE)) dut (.clock, .reset, .enable, .command, .write_idx, .read_idx, .data, .hit); 10 | 11 | always #5 clock = ~clock; 12 | 13 | task exit_on_error; 14 | begin 15 | #1; 16 | $display("@@@Failed at time %f", $time); 17 | $finish; 18 | end 19 | endtask 20 | 21 | initial begin 22 | 23 | $monitor("Command: %s, enable: %b, data: %h, write_idx: %h, read_idx: %h, hit: %b", command.name, enable, data, write_idx, read_idx, hit); 24 | 25 | clock = 0; 26 | write_idx = 0; 27 | enable = 0; 28 | command = READ; 29 | data = 0; 30 | 31 | /***RESET***/ 32 | reset = 1; 33 | @(negedge clock) 34 | reset = 0; 35 | 36 | /***CHECK THAT ALL ELEMENTS ARE INVALID***/ 37 | @(negedge clock); 38 | assert(!hit) else #1 exit_on_error; 39 | 40 | /***INITIALIZE MEMORY****/ 41 | command = WRITE; 42 | enable = 1; 43 | for(int i=0; i<`TEST_SIZE; i++) begin 44 | write_idx = i; 45 | data = $random; 46 | @(negedge clock); 47 | end 48 | 49 | /***OVERWRITE***/ 50 | for(int i=0; i<(2**$clog2(`TEST_SIZE)); i++) begin 51 | write_idx = i; 52 | data = i; 53 | @(negedge clock); 54 | end 55 | 56 | /***READ VALUES***/ 57 | command = READ; 58 | for(int i=0; i<`TEST_SIZE; i++) begin 59 | data = i; 60 | @(negedge clock); 61 | assert(hit && read_idx == i) else exit_on_error; 62 | end 63 | 64 | /***CHECK SIZE***/ 65 | data = `TEST_SIZE; 66 | @(negedge clock); 67 | assert(!hit) else #1 exit_on_error; 68 | 69 | /***TEST WITH MULTIPLE COPIES OF VALUE***/ 70 | command = WRITE; 71 | data = $random; 72 | write_idx = 0; 73 | @(negedge clock); 74 | repeat(5) begin 75 | write_idx = $random; 76 | @(negedge clock); 77 | end 78 | 79 | command = READ; 80 | @(negedge clock); 81 | assert(read_idx == 0) else exit_on_error; 82 | 83 | 84 | $display("@@@Passed"); 85 | $finish; 86 | 87 | end 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /labs/lab6/assignment/tex/eecs470lab6assignment.tex: -------------------------------------------------------------------------------- 1 | %***********************************************% 2 | % % 3 | % EECS 470 - Lab 06 % 4 | %<------------------> % 5 | % Last Modified by: % 6 | % Jonathan Beaumont on 2014-2-21 % 7 | % % 8 | %***********************************************% 9 | 10 | %***********************************************% 11 | % Preamble % 12 | %***********************************************% 13 | 14 | \documentclass{article} 15 | 16 | \usepackage{ 17 | tikz, 18 | xcolor, 19 | colortbl, 20 | graphicx, 21 | amsmath, 22 | amssymb, 23 | mathrsfs, 24 | float, 25 | siunitx, 26 | fancyhdr, 27 | minted, 28 | url, 29 | listings 30 | } 31 | 32 | \usepackage 33 | [left=1in,top=1in,right=1in,bottom=1in] 34 | {geometry} 35 | 36 | \pagestyle{fancy} 37 | \raggedright 38 | 39 | %--- Header ---% 40 | 41 | \newcommand{\courseNumber}{EECS 470} 42 | \newcommand{\courseTitle}{Computer Architecture} 43 | \newcommand{\university}{University of Michigan, Ann Arbor} 44 | \newcommand{\labdate}{February 19$^{\text{rd}}$, 2015} 45 | 46 | 47 | \lhead{ 48 | \small{ 49 | \university 50 | } 51 | } 52 | \rhead{ 53 | \small{ 54 | \emph{Date: \labdate} \hspace*{-1em} 55 | % Why is the above \hspace necessary? 56 | } 57 | } 58 | 59 | \newcommand{\shortbar}{ 60 | \vspace*{-12pt} 61 | \begin{center} 62 | \rule{5ex}{0.1pt} 63 | \end{center} 64 | } 65 | \newcommand{\lab}[1]{ 66 | \begin{center} 67 | \LARGE{ 68 | \vspace*{-12pt} 69 | EECS 470 Lab #1 Assignment 70 | \shortbar 71 | } 72 | \end{center} 73 | } 74 | 75 | 76 | %***********************************************% 77 | % % 78 | % TikZ Definitions % 79 | % % 80 | %***********************************************% 81 | 82 | \usetikzlibrary{shapes,arrows} 83 | 84 | % Block Diagram Styles 85 | \tikzstyle{block} = [draw, fill=blue!20, rectangle, 86 | minimum height=3em, minimum width=6em] 87 | \tikzstyle{sum} = [draw, fill=blue!20, circle, node distance=2cm] 88 | \tikzstyle{input} = [coordinate] 89 | \tikzstyle{output} = [coordinate] 90 | \tikzstyle{branch} = [coordinate] 91 | \tikzstyle{pinstyle} = [pin edge={to-, thin, black}] 92 | 93 | % Signal Flow Graph Styles 94 | \tikzstyle{signal} = [draw, fill=blue!20, circle, 95 | minimum height=3em] 96 | \tikzstyle{state} = [draw, fill=blue!20, circle, 97 | minimum height=3em] 98 | 99 | %***********************************************% 100 | % % 101 | % Document % 102 | % % 103 | %***********************************************% 104 | 105 | \begin{document} 106 | \vspace*{-20pt} 107 | \lab{6} 108 | \vspace*{-20pt} 109 | 110 | \section*{Note:} 111 | \begin{itemize} 112 | \item The lab should be completed individually. 113 | \item The lab must be submitted by 11:59PM on February 26th. 114 | \end{itemize} 115 | 116 | \section{Introduction} 117 | In this lab you will be designing a simplified, generically-sized Content Addressable Memory (CAM). A CAM has the property that, when queried with a value, it will search through all of its contents in parallel, returning the index at which that data exists (if it does). Our simplified CAM has the following module header: 118 | 119 | \begin{lstlisting} 120 | 121 | module CAM #(parameter SIZE=8) ( 122 | input clock, reset, 123 | input enable, 124 | 125 | input COMMAND command, 126 | 127 | input [31:0] data, 128 | 129 | input [$clog2(SIZE)-1:0] write_idx, 130 | 131 | output [$clog2(SIZE)-1:0] read_idx, 132 | output hit 133 | ); 134 | 135 | \end{lstlisting} 136 | 137 | CAM should have the following functionality: 138 | 139 | \begin{itemize} 140 | \item The design will maintain a set of "SIZE" (default of 8) 32-bit memory elements, which should only be updated on the positive edge of "clock". 141 | \item When "reset" is high on the rising clock edge, all entries in memory should be invalidated. 142 | \item If "enable" is high and "command" is set to "WRITE" (see sys\_defs.vh), CAM should store the value of "data" to memory address "write\_idx" and validate it. If the index is out of bounds (larger than "SIZE-1"), CAM should not modify its memory. 143 | \item If "enable" is high and "command" is "READ", CAM should write the lowest location of valid memory whose value equals "data" to "read\_idx". If the memory does not contain "data", "hit" should be set low. Otherwise, it should be high. 144 | \end{itemize} 145 | 146 | Before running 'make', set the "SIZE" by typing 'export CAM\_SIZE=[i]' in your terminal, replacing '[i]' with the appropriate integer. Your design should function correctly for any value of "SIZE". It is up to you how to implement this functionality. We recommend using a "for" loop inside of an "always" block. Remember than in a procedural block, all assignments happen simultaneously. If multiple assignments are made to the same variable, only the "later" one (the one listed furthest down in the block, or the furthest iteration of a "for" loop) takes effect. 147 | 148 | 149 | Your design should pass the testbench after synthesis as well, however you needn't worry for this lab about clock period. Just make a design that works. 150 | 151 | \section{Check Off} 152 | A script has been provided (check.sh) that checks the correctness for a few different test SIZES. Once you are passing all those cases, submit the lab using the standard submission script (/afs/umich.edu/user/m/o/moorthya/Public/470labsubmit -l6 lab6): 153 | 154 | \end{document} 155 | -------------------------------------------------------------------------------- /labs/lab6/slides/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/labs/lab6/slides/.DS_Store -------------------------------------------------------------------------------- /labs/lab6/slides/beamercolorthemewolverine.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2004 by Madhusudan Singh 2 | % 3 | % This file may be distributed and/or modified 4 | % 5 | % 1. under the LaTeX Project Public License and/or 6 | % 2. under the GNU Public License. 7 | % 8 | % See the file doc/licenses/LICENSE for more details. 9 | 10 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/color/beamercolorthemewolverine.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 11 | 12 | \mode 13 | 14 | \definecolor{darkblue}{rgb}{0,0,0.8} 15 | 16 | \setbeamercolor{alerted text}{fg=red!85!black} 17 | \setbeamercolor*{palette primary}{fg=darkblue!60!black,bg=yellow!85!orange} 18 | \setbeamercolor*{palette secondary}{fg=darkblue!60!black,bg=yellow!85!orange} 19 | %\setbeamercolor*{palette secondary}{fg=darkblue!70!black,bg=yellow!60!orange} 20 | \setbeamercolor*{palette tertiary}{bg=darkblue!80!black,fg=yellow!50!orange} 21 | \setbeamercolor*{palette quaternary}{fg=darkblue,bg=yellow!20!orange} 22 | 23 | \setbeamercolor*{sidebar}{fg=darkblue,bg=orange!75!white} 24 | 25 | 26 | \setbeamercolor*{palette sidebar primary}{fg=darkblue!10!black} 27 | \setbeamercolor*{palette sidebar secondary}{fg=white} 28 | \setbeamercolor*{palette sidebar tertiary}{fg=darkblue!50!black} 29 | \setbeamercolor*{palette sidebar quaternary}{fg=yellow!10!orange} 30 | 31 | \setbeamercolor*{titlelike}{parent=palette primary} 32 | \setbeamercolor{frametitle}{bg=yellow!90!orange} 33 | \setbeamercolor{frametitle right}{bg=yellow!60!orange} 34 | 35 | \setbeamercolor*{separation line}{} 36 | \setbeamercolor*{fine separation line}{} 37 | 38 | \mode 39 | 40 | -------------------------------------------------------------------------------- /labs/lab6/slides/beamerthemeLab.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2014 William Cunningham 2 | % For use in U of M EECS 470 - Computer Architecture Labs 3 | % 4 | % This file may be distributed and/or modified 5 | % 6 | % 1. under the LaTeX Project Public License and/or 7 | % 2. under the GNU Public License. 8 | % 9 | % See the file doc/licenses/LICENSE for more details. 10 | 11 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/theme/beamerthemedLabs.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 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-------------------------------------------------------------------------------- 1 | % Copyright 2004 by Madhusudan Singh 2 | % 3 | % This file may be distributed and/or modified 4 | % 5 | % 1. under the LaTeX Project Public License and/or 6 | % 2. under the GNU Public License. 7 | % 8 | % See the file doc/licenses/LICENSE for more details. 9 | 10 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/color/beamercolorthemewolverine.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 11 | 12 | \mode 13 | 14 | \definecolor{darkblue}{rgb}{0,0,0.8} 15 | 16 | \setbeamercolor{alerted text}{fg=red!85!black} 17 | \setbeamercolor*{palette primary}{fg=darkblue!60!black,bg=yellow!85!orange} 18 | \setbeamercolor*{palette secondary}{fg=darkblue!60!black,bg=yellow!85!orange} 19 | %\setbeamercolor*{palette secondary}{fg=darkblue!70!black,bg=yellow!60!orange} 20 | \setbeamercolor*{palette tertiary}{bg=darkblue!80!black,fg=yellow!50!orange} 21 | \setbeamercolor*{palette quaternary}{fg=darkblue,bg=yellow!20!orange} 22 | 23 | \setbeamercolor*{sidebar}{fg=darkblue,bg=orange!75!white} 24 | 25 | 26 | \setbeamercolor*{palette sidebar primary}{fg=darkblue!10!black} 27 | \setbeamercolor*{palette sidebar secondary}{fg=white} 28 | \setbeamercolor*{palette sidebar tertiary}{fg=darkblue!50!black} 29 | \setbeamercolor*{palette sidebar quaternary}{fg=yellow!10!orange} 30 | 31 | \setbeamercolor*{titlelike}{parent=palette primary} 32 | \setbeamercolor{frametitle}{bg=yellow!90!orange} 33 | \setbeamercolor{frametitle right}{bg=yellow!60!orange} 34 | 35 | \setbeamercolor*{separation line}{} 36 | \setbeamercolor*{fine separation line}{} 37 | 38 | \mode 39 | 40 | -------------------------------------------------------------------------------- /labs/lab7/beamerthemeLab.sty: -------------------------------------------------------------------------------- 1 | % Copyright 2014 William Cunningham 2 | % For use in U of M EECS 470 - Computer Architecture Labs 3 | % 4 | % This file may be distributed and/or modified 5 | % 6 | % 1. under the LaTeX Project Public License and/or 7 | % 2. under the GNU Public License. 8 | % 9 | % See the file doc/licenses/LICENSE for more details. 10 | 11 | \ProvidesPackageRCS $Header: /Users/joseph/Documents/LaTeX/beamer/base/themes/theme/beamerthemedLabs.sty,v d02a7cf4d8ae 2010/06/17 09:11:41 rivanvx $ 12 | 13 | 14 | \mode 15 | 16 | \usefonttheme{default} 17 | \usecolortheme{wolverine} 18 | \useinnertheme{default} 19 | \useoutertheme{infolines} 20 | 21 | \mode 22 | 23 | -------------------------------------------------------------------------------- /projects/project1/project1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/projects/project1/project1.pdf -------------------------------------------------------------------------------- /projects/project1/source/And.v: -------------------------------------------------------------------------------- 1 | module and2( 2 | input [1:0] a, 3 | output logic x 4 | ); 5 | assign x=a[0] & a[1]; 6 | endmodule 7 | 8 | module and4( 9 | input [3:0] in, 10 | output logic out 11 | ); 12 | logic [1:0] tmp; 13 | and2 left(.a(in[1:0]),.x(tmp[0])); 14 | and2 right(.a(in[3:2]),.x(tmp[1])); 15 | and2 top(.a(tmp),.x(out)); 16 | endmodule 17 | -------------------------------------------------------------------------------- /projects/project1/source/Makefile: -------------------------------------------------------------------------------- 1 | # Given no targets, 'make' will default to building 'simv', the simulated version 2 | # of the pipeline 3 | 4 | # make <- compile (and run) simv if needed 5 | 6 | # As shortcuts, any of the following will build if necessary and then run the 7 | # specified target 8 | 9 | # make sim <- runs simv (after compiling simv if needed) 10 | # make dve <- runs DVE interactively (after compiling it if needed) 11 | # 12 | 13 | # make clean <- remove files created during compilations (but not synthesis) 14 | # make nuke <- remove all files created during compilation and synthesis 15 | # 16 | # synthesis command not included in this Makefile 17 | # 18 | 19 | ################################################################################ 20 | ## CONFIGURATION 21 | ################################################################################ 22 | 23 | VCS = SW_VCS=2017.12-SP2-1 vcs -sverilog +vc -Mupdate -line -full64 24 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 25 | 26 | # SIMULATION CONFIG 27 | 28 | SIMFILES = P1a.v 29 | TESTBENCH = test.v 30 | 31 | # SYNTHESIS CONFIG 32 | 33 | # Passed through to .tcl scripts: 34 | export CLOCK_NET_NAME = clock 35 | export RESET_NET_NAME = reset 36 | export CLOCK_PERIOD = 50 # TODO: You will want to make this more aggresive 37 | 38 | ################################################################################ 39 | ## RULES 40 | ################################################################################ 41 | 42 | # Default target: 43 | all: simv 44 | ./simv | tee program.out 45 | 46 | .PHONY: all 47 | 48 | # Simulation: 49 | 50 | sim: simv $(ASSEMBLED) 51 | ./simv | tee sim_program.out 52 | 53 | simv: $(HEADERS) $(SIMFILES) $(TESTBENCH) 54 | $(VCS) $^ -o simv 55 | 56 | .PHONY: sim 57 | 58 | # Debugging 59 | 60 | dve_simv: $(HEADERS) $(SIMFILES) $(TESTBENCH) 61 | $(VCS) +memcbk $^ -o $@ -gui 62 | 63 | dve: dve_simv $(ASSEMBLED) 64 | ./$< 65 | 66 | clean: 67 | rm -rvf simv *.daidir csrc vcs.key program.out \ 68 | syn_simv syn_simv.daidir syn_program.out \ 69 | dve *.vpd *.vcd *.dump ucli.key 70 | 71 | nuke: clean 72 | rm -rvf *.vg *.rep *.db *.chk *.log *.out DVEfiles/ 73 | 74 | .PHONY: clean nuke dve 75 | -------------------------------------------------------------------------------- /projects/project1/source/test.v: -------------------------------------------------------------------------------- 1 | module testbench; 2 | logic [3:0] req; 3 | logic en; 4 | logic [3:0] gnt; 5 | logic [3:0] tb_gnt; 6 | logic correct; 7 | 8 | ps4 pe4(req, en, gnt); 9 | 10 | assign tb_gnt[3]=en&req[3]; 11 | assign tb_gnt[2]=en&req[2]&~req[3]; 12 | assign tb_gnt[1]=en&req[1]&~req[2]&~req[3]; 13 | assign tb_gnt[0]=en&req[0]&~req[1]&~req[2]&~req[3]; 14 | assign correct=(tb_gnt==gnt); 15 | 16 | always @(correct) 17 | begin 18 | #2 19 | if(!correct) 20 | begin 21 | $display("@@@ Incorrect at time %4.0f", $time); 22 | $display("@@@ gnt=%b, en=%b, req=%b",gnt,en,req); 23 | $display("@@@ expected result=%b", tb_gnt); 24 | $finish; 25 | end 26 | end 27 | 28 | initial 29 | begin 30 | $dumpvars; 31 | $monitor("Time:%4.0f req:%b en:%b gnt:%b", $time, req, en, gnt); 32 | req=4'b0000; 33 | en=1'b1; 34 | #5 35 | req=4'b1000; 36 | #5 37 | req=4'b0100; 38 | #5 39 | req=4'b0010; 40 | #5 41 | req=4'b0001; 42 | #5 43 | req=4'b0101; 44 | #5 45 | req=4'b0110; 46 | #5 47 | req=4'b1110; 48 | #5 49 | req=4'b1111; 50 | #5 51 | en=0; 52 | #5 53 | req=4'b0110; 54 | #5 55 | $finish; 56 | end // initial 57 | endmodule 58 | -------------------------------------------------------------------------------- /projects/project1/source/testAND.v: -------------------------------------------------------------------------------- 1 | module testbench; 2 | logic [3:0] in; 3 | logic out; 4 | logic tb_out; 5 | 6 | and4 test(in,out); 7 | 8 | assign tb_out = in[3]&in[2]&in[1]&in[0]; 9 | assign correct= (out == tb_out); 10 | 11 | always @(correct) 12 | begin 13 | #2 14 | if(!correct) 15 | begin 16 | $display("@@@ Incorrect at time %4.0f", $time); 17 | $display("@@@ in:%b out:%b", in, out); 18 | $display("@@@ expected result=%b", tb_out); 19 | $finish; 20 | end 21 | end 22 | 23 | initial 24 | begin 25 | $dumpvars; 26 | $monitor("Time:%4.0f in:%b out:%b", $time, in, out); 27 | in=4'b0000; 28 | #5 29 | in=4'b1100; 30 | #5 31 | in=4'b0110; 32 | #5 33 | in=4'b1111; 34 | #5 35 | in=4'b0111; 36 | #5 37 | $finish; 38 | end // initial 39 | endmodule 40 | -------------------------------------------------------------------------------- /projects/project1/source/testD.v: -------------------------------------------------------------------------------- 1 | module testbench; 2 | logic [3:0] req; 3 | logic en; 4 | logic [3:0] gnt; 5 | logic [3:0] tb_gnt; 6 | logic correct; 7 | logic [1:0] count; 8 | logic reset; 9 | logic clock; 10 | 11 | rps4 rps4_i(.clock(clock),.reset(reset),.req(req),.en(en),.gnt(gnt),.count(count)); 12 | 13 | assign correct=(gnt==tb_gnt); 14 | 15 | always @(correct) 16 | begin 17 | #2 18 | if(!correct) 19 | begin 20 | $display("@@@ Incorrect at time %4.0f", $time); 21 | $display("@@@ gnt=%b, en=%b, req=%b",gnt,en,req); 22 | $display("@@@ expected result=%b", tb_gnt); 23 | $finish; 24 | end 25 | end 26 | always 27 | #5 clock=~clock; 28 | 29 | 30 | initial 31 | begin 32 | $dumpvars; 33 | $monitor("Time:%4.0f req:%b en:%b gnt:%b, cnt:%b", $time, req, en, gnt,count); 34 | 35 | // CNT=????, need to reset. 36 | clock=0; 37 | reset=1; 38 | #6 39 | // CNT=0 40 | reset=0; 41 | req=4'b0001; 42 | en=1; 43 | tb_gnt=4'b0001; 44 | #10 45 | // CNT=1 46 | req=4'b0010; 47 | en=1; 48 | tb_gnt=4'b0010; 49 | #10 50 | // CNT=2 51 | req=4'b0101; 52 | tb_gnt=4'b0100; 53 | #10 54 | // CNT=3 55 | req=4'b0011; 56 | tb_gnt=4'b0010; 57 | #10 58 | // CNT=0 59 | req=4'b1111; 60 | tb_gnt=4'b0001; 61 | #10 62 | // CNT=1 63 | req=4'b1111; 64 | tb_gnt=4'b0010; 65 | #10 66 | // CNT=2 67 | req=4'b1111; 68 | tb_gnt=4'b0100; 69 | #10 70 | // CNT=3 71 | req=4'b1111; 72 | tb_gnt=4'b1000; 73 | #10 74 | // CNT=0 75 | req=4'b1111; 76 | en=0; 77 | tb_gnt=4'b0000; 78 | #10 79 | // CNT=1 80 | req=4'b1111; 81 | tb_gnt=4'b0000; 82 | #10 83 | $finish; 84 | end // initial 85 | endmodule 86 | -------------------------------------------------------------------------------- /projects/project1/tex/and.v: -------------------------------------------------------------------------------- 1 | module and2( 2 | input [1:0] a, 3 | output logic x 4 | ); 5 | assign x=a[0] & a[1]; 6 | endmodule 7 | 8 | module and4( 9 | input [3:0] in, 10 | output logic out 11 | ); 12 | logic [1:0] tmp; 13 | and2 left(.a(in[1:0]),.x(tmp[0])); 14 | and2 right(.a(in[3:2]),.x(tmp[1])); 15 | and2 top(.a(tmp),.x(out)); 16 | endmodule 17 | -------------------------------------------------------------------------------- /projects/project1/tex/submission.txt: -------------------------------------------------------------------------------- 1 | Submitting files in project1/ 2 | --- submitting project1/ 3 | --- submitting project1/Makefile 4 | --- submitting project1/P1a.v 5 | --- submitting project1/P1b.v 6 | --- submitting project1/And.v 7 | --- submitting project1/testAND.v 8 | --- submitting project1/testD.v 9 | --- submitting project1/test.v 10 | --- submitting project1/P1c.v 11 | --- submitting project1/P1d.v 12 | --- submitting project1/testC.v 13 | Submitted. 14 | -------------------------------------------------------------------------------- /projects/project2/project2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/projects/project2/project2.pdf -------------------------------------------------------------------------------- /projects/project2/source/Makefile: -------------------------------------------------------------------------------- 1 | # To compile additional files, add them to the TESTBENCH or SIMFILES as needed 2 | # Every .vg file will need its own rule and one or more synthesis scripts 3 | # The information contained here (in the rules for those vg files) will be 4 | # similar to the information in those scripts but that seems hard to avoid. 5 | # 6 | 7 | # added "SW_VCS=2011.03 and "-full64" option -- awdeorio fall 2011 8 | # added "-sverilog" and "SW_VCS=2012.09" option, 9 | # and removed deprecated Virsim references -- jbbeau fall 2013 10 | # updated library path name -- jbbeau fall 2013 11 | 12 | VCS = SW_VCS=2017.12-SP2-1 vcs +v2k -sverilog +vc -Mupdate -line -full64 13 | LIB = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v 14 | 15 | all: simv 16 | ./simv | tee program.out 17 | ##### 18 | # Modify starting here 19 | ##### 20 | 21 | TESTBENCH = mult_test.v 22 | SIMFILES = pipe_mult.v mult_stage.v 23 | SYNFILES = mult.vg 24 | 25 | mult.vg: pipe_mult.v mult_stage.vg mult.tcl 26 | dc_shell-t -f ./mult.tcl | tee mult_synth.out 27 | 28 | mult_stage.vg: mult_stage.v mult_stage.tcl 29 | dc_shell-t -f ./mult_stage.tcl | tee mult_stage_synth.out 30 | 31 | ##### 32 | # Should be no need to modify after here 33 | ##### 34 | sim: simv $(ASSEMBLED) 35 | ./simv | tee sim_program.out 36 | 37 | simv: $(HEADERS) $(SIMFILES) $(TESTBENCH) 38 | $(VCS) $^ -o simv 39 | 40 | .PHONY: sim 41 | 42 | 43 | # updated interactive debugger "DVE", using the latest version of VCS 44 | # awdeorio fall 2011 45 | dve: $(SIMFILES) $(TESTBENCH) 46 | $(VCS) +memcbk $(TESTBENCH) $(SIMFILES) -o dve -R -gui 47 | 48 | syn_simv: $(SYNFILES) $(TESTBENCH) 49 | $(VCS) $(TESTBENCH) $(SYNFILES) $(LIB) -o syn_simv 50 | 51 | syn: syn_simv 52 | ./syn_simv | tee syn_program.out 53 | 54 | clean: 55 | rm -rvf simv *.daidir csrc vcs.key program.out \ 56 | syn_simv syn_simv.daidir syn_program.out \ 57 | dve *.vpd *.vcd *.dump ucli.key 58 | 59 | nuke: clean 60 | rm -rvf *.vg *.rep *.db *.chk *.log *.out *.ddc *.svf DVEfiles/ 61 | 62 | .PHONY: dve clean nuke 63 | -------------------------------------------------------------------------------- /projects/project2/source/mult.tcl: -------------------------------------------------------------------------------- 1 | #/***********************************************************/ 2 | #/* FILE : mult.tcl */ 3 | #/* Description : Default Synopsys Design Compiler Script */ 4 | #/* Usage : dc_shell -tcl_mode -f mult.scr */ 5 | #/* You'll need to minimally set design_name & read files */ 6 | #/***********************************************************/ 7 | 8 | #/***********************************************************/ 9 | #/* The following lines must be updated for every */ 10 | #/* new design */ 11 | #/***********************************************************/ 12 | set search_path [ list "./" "/afs/umich.edu/class/eecs470/lib/synopsys/"] 13 | read_file -f ddc [list "mult_stage.ddc"] 14 | set_dont_touch mult_stage 15 | read_file -f sverilog [list "pipe_mult.v"] 16 | set design_name mult 17 | set clock_name clock 18 | set reset_name reset 19 | set CLK_PERIOD 11 20 | 21 | 22 | #/***********************************************************/ 23 | #/* The rest of this file may be left alone for most small */ 24 | #/* to moderate sized designs. You may need to alter it */ 25 | #/* when synthesizing your final project. */ 26 | #/***********************************************************/ 27 | set SYN_DIR ./ 28 | set target_library "lec25dscc25_TT.db" 29 | 30 | set link_library [concat "*" $target_library] 31 | 32 | #/***********************************************************/ 33 | #/* Set some flags for optimisation */ 34 | 35 | set compile_top_all_paths "true" 36 | set auto_wire_load_selection "false" 37 | 38 | 39 | #/***********************************************************/ 40 | #/* Clk Periods/uncertainty/transition */ 41 | 42 | set CLK_TRANSITION 0.1 43 | set CLK_UNCERTAINTY 0.1 44 | set CLK_LATENCY 0.1 45 | 46 | #/* Input/output Delay values */ 47 | set AVG_INPUT_DELAY 0.1 48 | set AVG_OUTPUT_DELAY 0.1 49 | 50 | #/* Critical Range (ns) */ 51 | set CRIT_RANGE 1.0 52 | 53 | #/***********************************************************/ 54 | #/* Design Constrains: Not all used */ 55 | set MAX_TRANSITION 1.0 56 | set FAST_TRANSITION 0.1 57 | set MAX_FANOUT 32 58 | set MID_FANOUT 8 59 | set LOW_FANOUT 1 60 | set HIGH_DRIVE 0 61 | set HIGH_LOAD 1.0 62 | set AVG_LOAD 0.1 63 | set AVG_FANOUT_LOAD 10 64 | 65 | #/***********************************************************/ 66 | #/*BASIC_INPUT = cb18os120_tsmc_max/nd02d1/A1 67 | #BASIC_OUTPUT = cb18os120_tsmc_max/nd02d1/ZN*/ 68 | 69 | set DRIVING_CELL dffacs1 70 | 71 | #/* DONT_USE_LIST = { } */ 72 | 73 | #/*************operation cons**************/ 74 | #/*OP_WCASE = WCCOM; 75 | #OP_BCASE = BCCOM;*/ 76 | set WIRE_LOAD "tsmcwire" 77 | set LOGICLIB lec25dscc25_TT 78 | #/*****************************/ 79 | 80 | #/* Sourcing the file that sets the Search path and the libraries(target,link) */ 81 | 82 | set sys_clk $clock_name 83 | 84 | set netlist_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".vg"] 85 | set ddc_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".ddc"] 86 | set rep_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".rep"] 87 | set dc_shell_status [ set chk_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".chk"] ] 88 | 89 | #/* if we didnt find errors at this point, run */ 90 | if { $dc_shell_status != [list] } { 91 | current_design $design_name 92 | link 93 | set_wire_load_model -name $WIRE_LOAD -lib $LOGICLIB $design_name 94 | set_wire_load_mode top 95 | set_fix_multiple_port_nets -outputs -buffer_constants 96 | create_clock -period $CLK_PERIOD -name $sys_clk [find port $sys_clk] 97 | set_clock_uncertainty $CLK_UNCERTAINTY $sys_clk 98 | set_fix_hold $sys_clk 99 | group_path -from [all_inputs] -name input_grp 100 | group_path -to [all_outputs] -name output_grp 101 | set_driving_cell -lib_cell $DRIVING_CELL [all_inputs] 102 | remove_driving_cell [find port $sys_clk] 103 | set_fanout_load $AVG_FANOUT_LOAD [all_outputs] 104 | set_load $AVG_LOAD [all_outputs] 105 | set_input_delay $AVG_INPUT_DELAY -clock $sys_clk [all_inputs] 106 | remove_input_delay -clock $sys_clk [find port $sys_clk] 107 | set_output_delay $AVG_OUTPUT_DELAY -clock $sys_clk [all_outputs] 108 | set_dont_touch $reset_name 109 | set_resistance 0 $reset_name 110 | set_drive 0 $reset_name 111 | set_critical_range $CRIT_RANGE [current_design] 112 | set_max_delay $CLK_PERIOD [all_outputs] 113 | set MAX_FANOUT $MAX_FANOUT 114 | set MAX_TRANSITION $MAX_TRANSITION 115 | uniquify 116 | ungroup -all -flatten 117 | redirect $chk_file { check_design } 118 | compile -map_effort high 119 | write -hier -format verilog -output $netlist_file $design_name 120 | write -hier -format ddc -output $ddc_file $design_name 121 | redirect $rep_file { report_design -nosplit } 122 | redirect -append $rep_file { report_area } 123 | redirect -append $rep_file { report_timing -max_paths 2 -input_pins -nets -transition_time -nosplit } 124 | redirect -append $rep_file { report_constraint -max_delay -verbose -nosplit } 125 | remove_design -all 126 | read_file -format verilog $netlist_file 127 | current_design $design_name 128 | redirect -append $rep_file { report_reference -nosplit } 129 | quit 130 | } else { 131 | quit 132 | } 133 | 134 | 135 | -------------------------------------------------------------------------------- /projects/project2/source/mult_stage.tcl: -------------------------------------------------------------------------------- 1 | #/***********************************************************/ 2 | #/* FILE : mult_stage.tcl */ 3 | #/* Description : Default Synopsys Design Compiler Script */ 4 | #/* Usage : dc_shell -tcl_mode -f default.tcl */ 5 | #/* You'll need to minimally set design_name & read files */ 6 | #/***********************************************************/ 7 | 8 | #/***********************************************************/ 9 | #/* The following five lines must be updated for every */ 10 | #/* new design */ 11 | #/***********************************************************/ 12 | 13 | read_file -f sverilog [list "mult_stage.v"] 14 | set design_name mult_stage 15 | set clock_name clock 16 | set reset_name reset 17 | set CLK_PERIOD 10 18 | 19 | 20 | 21 | 22 | 23 | #/***********************************************************/ 24 | #/* The rest of this file may be left alone for most small */ 25 | #/* to moderate sized designs. You may need to alter it */ 26 | #/* when synthesizing your final project. */ 27 | #/***********************************************************/ 28 | set SYN_DIR ./ 29 | set search_path "/afs/umich.edu/class/eecs470/lib/synopsys/" 30 | set target_library "lec25dscc25_TT.db" 31 | set link_library [concat "*" $target_library] 32 | 33 | #/***********************************************************/ 34 | #/* Set some flags for optimisation */ 35 | 36 | set compile_top_all_paths "true" 37 | set auto_wire_load_selection "false" 38 | 39 | 40 | #/***********************************************************/ 41 | #/* Clk Periods/uncertainty/transition */ 42 | 43 | set CLK_TRANSITION 0.1 44 | set CLK_UNCERTAINTY 0.1 45 | set CLK_LATENCY 0.1 46 | 47 | #/* Input/output Delay values */ 48 | set AVG_INPUT_DELAY 0.1 49 | set AVG_OUTPUT_DELAY 0.1 50 | 51 | #/* Critical Range (ns) */ 52 | set CRIT_RANGE 1.0 53 | 54 | #/***********************************************************/ 55 | #/* Design Constrains: Not all used */ 56 | set MAX_TRANSITION 1.0 57 | set FAST_TRANSITION 0.1 58 | set MAX_FANOUT 32 59 | set MID_FANOUT 8 60 | set LOW_FANOUT 1 61 | set HIGH_DRIVE 0 62 | set HIGH_LOAD 1.0 63 | set AVG_LOAD 0.1 64 | set AVG_FANOUT_LOAD 10 65 | 66 | #/***********************************************************/ 67 | #/*BASIC_INPUT = cb18os120_tsmc_max/nd02d1/A1 68 | #BASIC_OUTPUT = cb18os120_tsmc_max/nd02d1/ZN*/ 69 | 70 | set DRIVING_CELL dffacs1 71 | 72 | #/* DONT_USE_LIST = { } */ 73 | 74 | #/*************operation cons**************/ 75 | #/*OP_WCASE = WCCOM; 76 | #OP_BCASE = BCCOM;*/ 77 | set WIRE_LOAD "tsmcwire" 78 | set LOGICLIB lec25dscc25_TT 79 | #/*****************************/ 80 | 81 | #/* Sourcing the file that sets the Search path and the libraries(target,link) */ 82 | 83 | set sys_clk $clock_name 84 | 85 | set netlist_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".vg"] 86 | set ddc_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".ddc"] 87 | set rep_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".rep"] 88 | set dc_shell_status [ set chk_file [format "%s%s" [format "%s%s" $SYN_DIR $design_name] ".chk"] ] 89 | 90 | #/* if we didnt find errors at this point, run */ 91 | if { $dc_shell_status != [list] } { 92 | current_design $design_name 93 | link 94 | set_wire_load_model -name $WIRE_LOAD -lib $LOGICLIB $design_name 95 | set_wire_load_mode top 96 | set_fix_multiple_port_nets -outputs -buffer_constants 97 | create_clock -period $CLK_PERIOD -name $sys_clk [find port $sys_clk] 98 | set_clock_uncertainty $CLK_UNCERTAINTY $sys_clk 99 | set_fix_hold $sys_clk 100 | group_path -from [all_inputs] -name input_grp 101 | group_path -to [all_outputs] -name output_grp 102 | set_driving_cell -lib_cell $DRIVING_CELL [all_inputs] 103 | remove_driving_cell [find port $sys_clk] 104 | set_fanout_load $AVG_FANOUT_LOAD [all_outputs] 105 | set_load $AVG_LOAD [all_outputs] 106 | set_input_delay $AVG_INPUT_DELAY -clock $sys_clk [all_inputs] 107 | remove_input_delay -clock $sys_clk [find port $sys_clk] 108 | set_output_delay $AVG_OUTPUT_DELAY -clock $sys_clk [all_outputs] 109 | set_dont_touch $reset_name 110 | set_resistance 0 $reset_name 111 | set_drive 0 $reset_name 112 | set_critical_range $CRIT_RANGE [current_design] 113 | set_max_delay $CLK_PERIOD [all_outputs] 114 | set MAX_FANOUT $MAX_FANOUT 115 | set MAX_TRANSITION $MAX_TRANSITION 116 | uniquify 117 | ungroup -all -flatten 118 | redirect $chk_file { check_design } 119 | compile -map_effort high 120 | write -hier -format verilog -output $netlist_file $design_name 121 | write -hier -format ddc -output $ddc_file $design_name 122 | redirect $rep_file { report_design -nosplit } 123 | redirect -append $rep_file { report_area } 124 | redirect -append $rep_file { report_timing -max_paths 2 -input_pins -nets -transition_time -nosplit } 125 | redirect -append $rep_file { report_constraint -max_delay -verbose -nosplit } 126 | remove_design -all 127 | read_file -format verilog $netlist_file 128 | current_design $design_name 129 | redirect -append $rep_file { report_reference -nosplit } 130 | quit 131 | } else { 132 | quit 133 | } 134 | 135 | 136 | -------------------------------------------------------------------------------- /projects/project2/source/mult_stage.v: -------------------------------------------------------------------------------- 1 | // This is one stage of an 8 stage (9 depending on how you look at it) 2 | // pipelined multiplier that multiplies 2 64-bit integers and returns 3 | // the low 64 bits of the result. This is not an ideal multiplier but 4 | // is sufficient to allow a faster clock period than straight * 5 | module mult_stage( 6 | input clock, reset, start, 7 | input [63:0] product_in, mplier_in, mcand_in, 8 | 9 | output logic done, 10 | output logic [63:0] product_out, mplier_out, mcand_out 11 | ); 12 | 13 | 14 | 15 | logic [63:0] prod_in_reg, partial_prod_reg; 16 | logic [63:0] partial_product, next_mplier, next_mcand; 17 | 18 | assign product_out = prod_in_reg + partial_prod_reg; 19 | 20 | assign partial_product = mplier_in[7:0] * mcand_in; 21 | 22 | assign next_mplier = {8'b0,mplier_in[63:8]}; 23 | assign next_mcand = {mcand_in[55:0],8'b0}; 24 | 25 | //synopsys sync_set_reset "reset" 26 | always_ff @(posedge clock) begin 27 | prod_in_reg <= #1 product_in; 28 | partial_prod_reg <= #1 partial_product; 29 | mplier_out <= #1 next_mplier; 30 | mcand_out <= #1 next_mcand; 31 | end 32 | 33 | // synopsys sync_set_reset "reset" 34 | always_ff @(posedge clock) begin 35 | if(reset) 36 | done <= #1 1'b0; 37 | else 38 | done <= #1 start; 39 | end 40 | 41 | endmodule 42 | 43 | -------------------------------------------------------------------------------- /projects/project2/source/mult_test.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | 3 | logic [63:0] a,b; 4 | logic quit, clock, start, reset; 5 | 6 | logic [63:0] result; 7 | logic done; 8 | 9 | wire [63:0] cres = a*b; 10 | 11 | wire correct = (cres===result)|~done; 12 | 13 | 14 | mult m0( .clock(clock), 15 | .reset(reset), 16 | .mcand(a), 17 | .mplier(b), 18 | .start(start), 19 | .product(result), 20 | .done(done)); 21 | 22 | always @(posedge clock) 23 | #2 if(!correct) begin 24 | $display("Incorrect at time %4.0f",$time); 25 | $display("cres = %h result = %h",cres,result); 26 | $finish; 27 | end 28 | 29 | always begin 30 | #5; 31 | clock=~clock; 32 | end 33 | 34 | // Some students have had problems just using "@(posedge done)" because their 35 | // "done" signals glitch (even though they are the output of a register). This 36 | // prevents that by making sure "done" is high at the clock edge. 37 | task wait_until_done; 38 | forever begin : wait_loop 39 | @(posedge done); 40 | @(negedge clock); 41 | if(done) disable wait_until_done; 42 | end 43 | endtask 44 | 45 | 46 | 47 | initial begin 48 | $dumpvars; 49 | $monitor("Time:%4.0f done:%b a:%h b:%h product:%h result:%h",$time,done,a,b,cres,result); 50 | a=2; 51 | b=3; 52 | reset=1; 53 | clock=0; 54 | start=1; 55 | 56 | @(negedge clock); 57 | reset=0; 58 | @(negedge clock); 59 | start=0; 60 | wait_until_done(); 61 | start=1; 62 | a=-1; 63 | @(negedge clock); 64 | start=0; 65 | wait_until_done(); 66 | @(negedge clock); 67 | start=1; 68 | a=-20; 69 | b=5; 70 | @(negedge clock); 71 | start=0; 72 | wait_until_done(); 73 | quit = 0; 74 | quit <= #10000 1; 75 | while(~quit) begin 76 | start=1; 77 | a={$random,$random}; 78 | b={$random,$random}; 79 | @(negedge clock); 80 | start=0; 81 | wait_until_done(); 82 | end 83 | $finish; 84 | end 85 | 86 | endmodule 87 | 88 | 89 | 90 | 91 | 92 | -------------------------------------------------------------------------------- /projects/project2/source/pipe_mult.v: -------------------------------------------------------------------------------- 1 | // This is an 8 stage (9 depending on how you look at it) pipelined 2 | // multiplier that multiplies 2 64-bit integers and returns the low 64 bits 3 | // of the result. This is not an ideal multiplier but is sufficient to 4 | // allow a faster clock period than straight * 5 | // This module instantiates 8 pipeline stages as an array of submodules. 6 | module mult( 7 | input clock, reset, 8 | input [63:0] mcand, mplier, 9 | input start, 10 | 11 | output [63:0] product, 12 | output done 13 | ); 14 | 15 | logic [63:0] mcand_out, mplier_out; 16 | logic [(7*64)-1:0] internal_products, internal_mcands, internal_mpliers; 17 | logic [6:0] internal_dones; 18 | 19 | mult_stage mstage [7:0] ( 20 | .clock(clock), 21 | .reset(reset), 22 | .product_in({internal_products,64'h0}), 23 | .mplier_in({internal_mpliers,mplier}), 24 | .mcand_in({internal_mcands,mcand}), 25 | .start({internal_dones,start}), 26 | .product_out({product,internal_products}), 27 | .mplier_out({mplier_out,internal_mpliers}), 28 | .mcand_out({mcand_out,internal_mcands}), 29 | .done({done,internal_dones}) 30 | ); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /projects/project2/tex/eecs470project2.tex: -------------------------------------------------------------------------------- 1 | %***********************************************% 2 | % % 3 | % EECS 470 - Project 2 % 4 | %<------------------> % 5 | % Last Modified by: % 6 | % William Cunningham on 2014-9-14 % 7 | % % 8 | %***********************************************% 9 | 10 | %***********************************************% 11 | % Preamble % 12 | %***********************************************% 13 | 14 | \documentclass{article} 15 | 16 | \usepackage[dvipsnames]{xcolor} 17 | 18 | \usepackage{ 19 | tikz, 20 | colortbl, 21 | graphicx, 22 | amsmath, 23 | amssymb, 24 | mathrsfs, 25 | float, 26 | siunitx, 27 | fancyhdr, 28 | url, 29 | minted, 30 | cleveref, 31 | algorithm, 32 | algpseudocode 33 | } 34 | 35 | 36 | \usepackage 37 | [left=1in,top=1in,right=1in,bottom=1in] 38 | {geometry} 39 | 40 | \pagestyle{fancy} 41 | 42 | %--- Header ---% 43 | 44 | \newcommand{\courseNumber}{EECS 470} 45 | \newcommand{\courseTitle}{Computer Architecture} 46 | \newcommand{\university}{University of Michigan, Ann Arbor} 47 | \newcommand{\labdate}{January 30$^{\text{th}}$, 2021} 48 | 49 | 50 | \lhead{ 51 | \small{ 52 | \university 53 | } 54 | } 55 | \rhead{ 56 | \small{ 57 | \emph{Date: \labdate} \hspace*{-1em} 58 | % Why is the above \hspace necessary? 59 | } 60 | } 61 | 62 | \newcommand{\shortbar}{ 63 | \vspace*{-12pt} 64 | \begin{center} 65 | \rule{5ex}{0.1pt} 66 | \end{center} 67 | } 68 | \newcommand{\project}[1]{ 69 | \begin{center} 70 | \LARGE{ 71 | \vspace*{-12pt} 72 | EECS 470 Project \##1 73 | \shortbar 74 | } 75 | \end{center} 76 | } 77 | 78 | 79 | %***********************************************% 80 | % % 81 | % TikZ Definitions % 82 | % % 83 | %***********************************************% 84 | 85 | \usetikzlibrary{shapes,arrows,automata,shadows} 86 | \pgfdeclarelayer{background} 87 | \pgfdeclarelayer{foreground} 88 | \pgfsetlayers{background,main,foreground} 89 | 90 | % Block Diagram Styles 91 | \tikzstyle{block} = [draw, fill=RoyalBlue!50, rectangle, 92 | minimum height=2cm, minimum width=2cm, rounded corners] 93 | \tikzstyle{sum} = [draw, fill=blue!20, circle, node distance=2cm] 94 | \tikzstyle{input} = [coordinate] 95 | \tikzstyle{output} = [coordinate] 96 | \tikzstyle{branch} = [coordinate] 97 | \tikzstyle{pinstyle} = [pin edge={to-, thin, black}] 98 | 99 | % Signal Flow Graph Styles 100 | \tikzstyle{signal} = [draw, fill=RoyalBlue!50, circle, 101 | minimum height=3em] 102 | \tikzstyle{state} = [draw, fill=RoyalBlue!50, circle, 103 | minimum height=3em] 104 | 105 | %***********************************************% 106 | % % 107 | % Document % 108 | % % 109 | %***********************************************% 110 | 111 | \begin{document} 112 | \vspace*{-20pt} 113 | \project{2} 114 | 115 | \begin{itemize} 116 | \item This is an individual assignment. You may discuss the specification 117 | and help one another with the (System)Verilog language. Your solution, 118 | particularly the designs you submit, must be your own. 119 | \item Due at 11:59pm ET on 10$^{\text{th}}$ February, 2021. 120 | \emph{Late submissions are not accepted.} 121 | \end{itemize} 122 | \hrulefill 123 | 124 | \section{Introduction} 125 | We've mentioned synthesis several times already in the lab and lecture. 126 | Synthesis is an exponentially complex process, and so it can take a very long 127 | time on larger projects, like the one you'll be doing at the end of the 128 | semester. To mitigate this, we can synthesize submodules and then include them 129 | as black boxes in the final project, which simplifies the synthesis problem. 130 | This is particularly useful for synthesizing the caches in your final project, 131 | which can reduce the synthesis time by half or more. 132 | 133 | We will use a pipelined multiplier as an example of this process. This 134 | multiplier is actually the one you'll be using in your final project, so you 135 | should use this as a chance to get very familiar with it. 136 | 137 | Finally, we will be using this multiplier as part of a finite state machine 138 | design problem, which is intended to give you additional practice writing 139 | Verilog in reasonable style. The style we recommend for finite state machine 140 | design will be presented in the lab. 141 | 142 | \section{Hierarchical Synthesis} 143 | \subsection{Concept} 144 | Synthesis takes a behavioral level design and turns it into a structural level 145 | design. Specifically, the synthesis tool replaces larger operations, i.e. 146 | multiplication or addition with standard designs for modules, and attempts to 147 | build larger logic components out of a set of standard cells (our standard cells 148 | are in the \texttt{lec25dscc25.v} file included by your \texttt{Makefile}). 149 | Doing this optimally is an NP-hard problem, so it is often impossible in 150 | practice. In this class, it is generally merely very time consuming, meaning 151 | that your final project will take anywhere between six hours and one day to 152 | synthesize. 153 | 154 | To mitigate this problem, we can synthesize large submodules in a design 155 | individually and then include these syntheses as black boxes in the final design 156 | synthesis. Given that the original problem was NP-hard, we know that it would 157 | have been exponentially complex, where the quantity of interest is the size of a 158 | design, measured in something like the number of logic elements (standard cells, 159 | LUTs, transistors, etc.) That means that simplifying to only somewhat fewer 160 | elements still shortens the time to find a solution significantly. 161 | 162 | \subsection{Pipelined Multiplier} 163 | We have provided you with a pipelined multiplier, found in 164 | \texttt{pipe\_mult.v}, to which we will apply this concept. The multiplier does 165 | multiplication in stages, somewhat like you would have learned to carry out 166 | multiplication in elementary school. It multiplies the first 8 bits of the 167 | multiplier with the whole multiplicand in one clock cycle, then the next 8 bits 168 | of the multiplier against a shifted multiplicand, and so on to get 8 partial 169 | products. Summing those gives us the desired multiplication. This means that 170 | each multiplication will take 8 clock cycles. Each partial product is created by 171 | a separate multiplier stage, which can be found in the \texttt{mult\_stage.v} 172 | file. 173 | 174 | Your first assignment will be to find a reasonable clock period (within 175 | 2\si{\nano\second} of the lowest possible) at which the 8 stage multiplier we've 176 | provided you can be synthesized with slack met. For example, if you find that 177 | the design does not synthesize at a clock period of 4 \si{\nano\second}, but it 178 | does synthesize with a clock period of 5.5 \si{\nano\second}, then 5.5 179 | \si{\nano\second} must be within 1.5 \si{\nano\second} of the shortest possible 180 | clock period. We've already setup the \texttt{.tcl} scripts to synthesize the 181 | two modules in this design for you. Note the \texttt{set\_dont\_touch} command 182 | in the \texttt{mult.tcl} script. This command tells the synthesis tool to treat 183 | the module as a black box and to not optimize it further. 184 | 185 | To find the clock period, you will need to change the clock period in the 186 | \texttt{mult\_stage.tcl} file until you reach the best clock period that meets 187 | all slack. Once you've found that, the total clock period of the multiplier will 188 | be that stage clock period plus the additional combinational delay from the 189 | interconnects in the higher level \texttt{mult} module. This means that the 190 | clock period in the \texttt{mult\_stage.tcl} file will be different from the one 191 | found in the \texttt{mult.tcl} file. 192 | 193 | Your second assignment is to modify the pipelined multiplier we've provided to 194 | work as both a 4 stage multiplier and as a 2 stage multiplier. You can either 195 | do this by copying the files and having separate 2, 4 and 8 stage multipliers or 196 | by figuring out a combination of preprocessor macros or parameters that set 197 | pipeline depth. Whichever method you choose is fine for this project, but having 198 | the parameterized pipeline depth will be extremely helpful for the final 199 | project. Once you have the other two multipliers, you will need to find the best 200 | clock periods that they can each achieve. How do all three clock periods 201 | compare? Does this conform to your expectations? 202 | 203 | \section{Integer Square Root} 204 | \label{sec:isr} 205 | Now, you will need to create a module that uses the multiplier that we supplied, 206 | the 8 stage multiplier. You will be writing a module to compute the integer 207 | square root of a 64-bit number. It will generate a 32-bit number that is the 208 | largest integer that is not larger than the square root of the number provided. 209 | For example, the integer square root of 24 is 4. 210 | 211 | The module declaration is as follows: 212 | \begin{figure}[H] 213 | \begin{minted}[frame=lines,tabsize=4]{verilog} 214 | module ISR( 215 | input reset, 216 | input [63:0] value, 217 | input clock, 218 | output logic [31:0] result, 219 | output logic done 220 | ); 221 | \end{minted} 222 | \end{figure} 223 | It should operate as follows: 224 | \begin{itemize} 225 | \item If \texttt{reset} is asserted during a rising clock edge (synchronous 226 | reset), the \texttt{value} signal is to be stored. 227 | \item If \texttt{reset} is asserted part way through a computation, the 228 | result of that computation is discarded and a new \texttt{value} is 229 | latched into the module. 230 | \item When the module has finished computing the answer, the output is 231 | placed on the \texttt{result} line and \texttt{done} line is raised on the same cycle. 232 | \item It must not take more than 600 clock cycles to compute a result (from 233 | the last clock that \texttt{reset} is asserted to the first clock that 234 | \texttt{done} is asserted.) 235 | \end{itemize} 236 | 237 | We do not suggest that you pipeline this module. You will likely need to 238 | perform something like a binary search to find the result a simple algorithm is 239 | as follows: 240 | \begin{algorithm}[H] 241 | \caption{Integer Square Root} 242 | \begin{algorithmic}[1] 243 | \Procedure{ISR}{\texttt{value}} 244 | \For{$i \gets 31 \text{ to } 0$} 245 | \State \texttt{proposed\_solution[$i$]}$\leftarrow$1 246 | \If{\texttt{proposed\_solution}$^{2} >$ \texttt{value}} 247 | \State \texttt{proposed\_solution[$i$]}$\leftarrow$0 248 | \EndIf 249 | \EndFor 250 | \EndProcedure 251 | \end{algorithmic} 252 | \end{algorithm} 253 | 254 | Note that loops do not have a direct hardware equivalent. What hardware design 255 | technique lets us implement a procedure like this? 256 | 257 | In addition to writing this module, you will need to write a testbench for it. 258 | This testbench should probably test specific corner cases, random testing and 259 | the short loops. Your testbench should print either \texttt{@@@Passed} or 260 | \texttt{@@@Failed}. 261 | 262 | Once you have the module written and tested, synthesize it. This will probably 263 | take several minutes at least. 264 | 265 | \section{Comprehension Questions} 266 | 267 | Answer the following questions, and submit the answers in a plaintext file called 268 | \texttt{answers.txt} along with the rest of your project. 269 | 270 | \begin{enumerate} 271 | \item Consider the multiplier supplied with this project. 272 | \begin{enumerate} 273 | \item What is the cycle time achieved when you synthesized our 274 | multiplier? 275 | \item What does this mean the total latency is for a multiplication? 276 | \end{enumerate} 277 | \item Answer question 1 (parts a and b) for the two multipliers you created. 278 | \item Consider the relative values of the answers you found to questions 1 279 | and 2. Do these seem reasonable? Why or why not? 280 | \item What is the clock period achievable with the module you wrote in 281 | \cref{sec:isr}? 282 | \item How long would it take for your module to compute the square root of 283 | 1001 given the cycle time of question 4? Would you expect a performance 284 | gain or penalty if you used your 2 stage multiplier? 285 | \end{enumerate} 286 | 287 | \section{Submission} 288 | After you are confident in your solution, make sure you have the following files 289 | in your directory 290 | \begin{enumerate} 291 | \item \texttt{ISR.v} 292 | \item \texttt{test\_ISR.v} 293 | \item \texttt{answers.txt} 294 | \end{enumerate} 295 | Now, go up one directory (\texttt{cd ..}) and run: 296 | 297 | \texttt{/afs/umich.edu/user/j/b/jbbeau/Public/470submit -p2 } 298 | 299 | \noindent 300 | Note that the script takes a directory name as an argument, not an absolute 301 | path, so you must run it from one level above your project 1 directory. 302 | 303 | At this point, you should see something similar to: 304 | \inputminted[frame=lines,obeytabs,tabsize=4]{bash}{submission.txt} 305 | \noindent 306 | If there is a problem, it will be printed to the screen. Shortly after 307 | submission you should receive an email telling you if your submission passed the 308 | basic tests. This is not an autograder, so it's simply telling you that your 309 | design built successfully on the grading machine and that the module 310 | declarations looked approximately correct. If your submission didn't pass, copy 311 | the error message into an email to the course staff, and we will attempt to 312 | help. 313 | 314 | \end{document} 315 | -------------------------------------------------------------------------------- /projects/project2/tex/submission.txt: -------------------------------------------------------------------------------- 1 | Submitting files in project2/ 2 | --- submitting project2/ 3 | --- submitting project2/Makefile 4 | --- submitting project2/ISR.v 5 | --- submitting project2/test_ISR.v 6 | --- submitting project2/answers.txt 7 | Submitted. 8 | -------------------------------------------------------------------------------- /projects/project3/project3.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/projects/project3/project3.pdf -------------------------------------------------------------------------------- /projects/project3/tex/eecs470project3.tex: -------------------------------------------------------------------------------- 1 | %***********************************************% 2 | % % 3 | % EECS 470 - Project 3 % 4 | %<------------------> % 5 | % Last Modified by: % 6 | % William Cunningham on 2014-9-22 % 7 | % % 8 | %***********************************************% 9 | 10 | %***********************************************% 11 | % Preamble % 12 | %***********************************************% 13 | 14 | \documentclass{article} 15 | 16 | \usepackage[dvipsnames]{xcolor} 17 | 18 | \usepackage{ 19 | tikz, 20 | colortbl, 21 | graphicx, 22 | amsmath, 23 | amssymb, 24 | mathrsfs, 25 | float, 26 | siunitx, 27 | fancyhdr, 28 | hyperref, 29 | minted, 30 | cleveref, 31 | algorithm, 32 | algpseudocode 33 | } 34 | 35 | 36 | \usepackage 37 | [left=1in,top=1in,right=1in,bottom=1in] 38 | {geometry} 39 | 40 | \pagestyle{fancy} 41 | 42 | %--- Header ---% 43 | 44 | \newcommand{\courseNumber}{EECS 470} 45 | \newcommand{\courseTitle}{Computer Architecture} 46 | \newcommand{\university}{University of Michigan, Ann Arbor} 47 | \newcommand{\labdate}{January 28$^{\text{th}}$, 2019} 48 | 49 | 50 | \lhead{ 51 | \small{ 52 | \university 53 | } 54 | } 55 | \rhead{ 56 | \small{ 57 | \emph{Date: \labdate} \hspace*{-1em} 58 | % Why is the above \hspace necessary? 59 | } 60 | } 61 | 62 | \newcommand{\shortbar}{ 63 | \vspace*{-12pt} 64 | \begin{center} 65 | \rule{5ex}{0.1pt} 66 | \end{center} 67 | } 68 | \newcommand{\project}[1]{ 69 | \begin{center} 70 | \LARGE{ 71 | \vspace*{-12pt} 72 | EECS 470 Project \#3 73 | \shortbar 74 | } 75 | \end{center} 76 | } 77 | 78 | 79 | %***********************************************% 80 | % % 81 | % TikZ Definitions % 82 | % % 83 | %***********************************************% 84 | 85 | \usetikzlibrary{shapes,arrows,automata,shadows} 86 | \pgfdeclarelayer{background} 87 | \pgfdeclarelayer{foreground} 88 | \pgfsetlayers{background,main,foreground} 89 | 90 | % Block Diagram Styles 91 | \tikzstyle{block} = [draw, fill=RoyalBlue!50, rectangle, 92 | minimum height=2cm, minimum width=2cm, rounded corners] 93 | \tikzstyle{sum} = [draw, fill=blue!20, circle, node distance=2cm] 94 | \tikzstyle{input} = [coordinate] 95 | \tikzstyle{output} = [coordinate] 96 | \tikzstyle{branch} = [coordinate] 97 | \tikzstyle{pinstyle} = [pin edge={to-, thin, black}] 98 | 99 | % Signal Flow Graph Styles 100 | \tikzstyle{signal} = [draw, fill=RoyalBlue!50, circle, 101 | minimum height=3em] 102 | \tikzstyle{state} = [draw, fill=RoyalBlue!50, circle, 103 | minimum height=3em] 104 | 105 | %***********************************************% 106 | % % 107 | % Document % 108 | % % 109 | %***********************************************% 110 | 111 | \begin{document} 112 | \vspace*{-20pt} 113 | \project{3} 114 | 115 | \begin{itemize} 116 | \item This is an individual assignment. You may discuss the specification 117 | and help one another with the (System)Verilog language. The 118 | modifications you submit must be your own. 119 | \item This assignment is worth 4\% of your course grade. 120 | \item Due at 11:59pm EDT on Sunday, 10$^{\text{th}}$ February, 2019. 121 | \emph{Late submissions are not accepted.} 122 | \item \textbf{This assignment is considerably more work than programming assignments 1 and 2. \\Do not leave it until the last minute!} 123 | 124 | \end{itemize} 125 | \hrulefill 126 | 127 | \section{Introduction} 128 | \textsc{VeriSimpleV} is a simple pipelined implementation of a subset of the 129 | RISC-V instruction set architecture, written in synthesizable, behavioral 130 | SystemVerilog. The structure of this implementation is very similar to the MIPS 131 | pipeline covered in the text. We have provided you with a base version, which 132 | has absolutely no hazard detection logic. This version of \textsc{VeriSimpleV} 133 | inserts 4 invalid instructions (stalls) after every instruction to remove any 134 | possibility of a hazard. 135 | 136 | \section{Assignment} 137 | Your assignment will be to modify the provided implementation of 138 | \textsc{VeriSimpleV} to handle hazards and forwarding. You will need to begin by 139 | modifying the \texttt{if\_stage.sv} file to issue valid instructions so that more 140 | than one is in the pipeline at a time. 141 | 142 | Your solution is subject to the following restrictions: 143 | \begin{itemize} 144 | \item Branches should resolve in the stage in which they are currently 145 | resolved. 146 | \item All forwarding must be to the \texttt{EX} stage, even if the data 147 | isn't needed until a later stage. 148 | \item Any stalling due to data hazards must occur in the \texttt{ID} stage, 149 | meaning the dependent instruction should wait in the \texttt{ID} stage. 150 | Obviously the instruction following the stalling instruction in the 151 | \texttt{ID} stage will need wait in the \texttt{IF} stage. Thus, if you 152 | need to insert an invalid instruction (a stall), it must appear in the 153 | \texttt{EX} stage. 154 | \item If you wish to insert a \texttt{noop} you must also invalidate the 155 | instruction. Otherwise your CPI numbers will be wrong. 156 | \item If there is a structural hazard in the memory, you should let the 157 | \texttt{load}/\texttt{store} go and have the \texttt{IF} stage wait for 158 | the bus to be free. 159 | \end{itemize} 160 | 161 | You will need to add logic to handle all types of hazards: structural, control 162 | and data. You will also need to add logic to forward data to avoid data hazards, 163 | where possible within the limitations above, and add stalls if and only if there 164 | is a data hazard that cannot be resolved by forwarding. You should predict 165 | branches as not taken and squash if incorrect. Verify that your improved 166 | pipeline produces the same results as our provided version. 167 | 168 | Your improved pipeline will be tested in synthesis as well as simulation, so you 169 | should test it that way as well. Your submission will be graded automatically by 170 | comparing the files output by the provided testbench, which include the 171 | contents of the pipeline, the contents of memory and the CPI. 172 | 173 | \subsection{Hints} 174 | \begin{itemize} 175 | \item Be careful with forwarding and register 0. 176 | \item Synthesized runs of the pipeline can take a few minutes, depending on 177 | the testcase and computer. 178 | \item There is a \emph{lot} of SystemVerilog here; take your time looking it 179 | over. Try to understand how it works before you modify it. The slides 180 | from Lab 4 will also help walk you through it. 181 | \item Start this process early! 182 | \end{itemize} 183 | 184 | \section{Project Files} 185 | For this project, you are provided with most of the code and the entire build and test system. \textbf{The source files are available at \href{https://bitbucket.org/jieltan/project-v-open-beta/src/master/}{\underline{this repository}}}. Here is a quick introduction to what you've been provided and how it's structured. 186 | 187 | The VeriSimpleV pipeline is broken up into 7 files in the \texttt{project3/verilog/ }folder. There are 5 files which correspond to the pipeline stages (\texttt{project3/verilog/if\_stage.sv}, etc.); the register file module is separated into the \texttt{project3/verilog/regfile.sv} file and instantiated by the ID stage; and the stages are tied together by the pipeline module, which can be found in the project3/verilog/pipeline.v file. 188 | 189 | The \texttt{project3/sys\_defs.svh} file contains all of the \texttt{typedef's} and \texttt{`define's} that are used in the pipeline and testbench. The testbench and associated nonsynthesizable verilog can be found in the \texttt{project3/testbench/} folder. Note that the memory module defined in the \texttt{project3/testench/mem.sv} file is nonsyn- thesizable. 190 | 191 | Testing this project is less about the testbench and more about the testcases. Now that you've moved up to a complete processor design, testing requires running programs. You have been provided with a set of testcases in the \texttt{project3/test\_progs/} folder, written in RISC-V assembly or C language. To run one of them, you first have to assemble it into machine code, which is done using \texttt{riscv64-unknown-elf-gcc}. The rules for compiling testcases in the Makefile are as follows: 192 | 193 | \hrulefill 194 | 195 | \texttt{SOURCE = test\_progs/sampler.s} 196 | 197 | \texttt{...} 198 | 199 | \texttt{GCC = riscv64-unknown-elf-gcc} 200 | 201 | \texttt{...} 202 | 203 | \texttt{program: compile disassemble hex} 204 | 205 | \texttt{~~~@:} 206 | 207 | \texttt{...} 208 | 209 | \texttt{assembly: assemble dissemble hex} 210 | 211 | \texttt{~~~@:} 212 | 213 | \hrulefill 214 | 215 | \texttt{make assembly} reads the code in from the \texttt{project3/test\_progs/sampler.s} file and writes the assembled machine code out to the \texttt{project3/program.mem} file, which is then read into memory by the testbench. To compile another test case, you need to override the \texttt{SOURCE} variable in the Makefile. To comile \texttt{project3/test\_progs/*.c} testcases, \texttt{make program} should be used. Finally, once you have an assembled program ready to test, you can run the VeriSimpleV the same way you've run every other project so far, with the make command. If you need to run a little more interactively, to see where a particular instruction is in the pipeline for instance, you have been provided with a visual debugger, which can be run using the \texttt{make vis\_simv} command. Play around with this. It will make the project much easier. 216 | 217 | \section{Submission} 218 | \textbf{You will submit this project the same way you've submitted the last two, using 219 | the submission script.} In addition, you will need to create a private repository on \href{http://bitbucket.org}{Bitbucket} with the name \texttt{eecs470\_f19\_project3\_\{uniquename\}}, and grant Admin access to the account \texttt{eecs470staff@umich.edu}. After you create the repo, you will need to check your code into the repository. 220 | 221 | \end{document} 222 | -------------------------------------------------------------------------------- /projects/project4/project4.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jieltan/OpenCompArchCourse/33b44f4b88cdd43930d4ccbdbbb82af914f43c22/projects/project4/project4.pdf -------------------------------------------------------------------------------- /projects/project4/tex/exception_spec.tex: -------------------------------------------------------------------------------- 1 | %***********************************************% 2 | % % 3 | % EECS 470 - RISC-V Privileged ISA Support % 4 | %<------------------> % 5 | % Last Modified by: % 6 | % Jielun Tan on 2019-10-21 % 7 | % % 8 | %***********************************************% 9 | 10 | %***********************************************% 11 | % Preamble % 12 | %***********************************************% 13 | 14 | \documentclass{article} 15 | 16 | \usepackage{ 17 | tikz, 18 | xcolor, 19 | colortbl, 20 | graphicx, 21 | amsmath, 22 | amssymb, 23 | mathrsfs, 24 | float, 25 | siunitx, 26 | fancyhdr, 27 | minted, 28 | url, 29 | listings 30 | } 31 | \usepackage{hyperref} 32 | \hypersetup{ 33 | colorlinks=true, 34 | linkcolor=blue, 35 | filecolor=magenta, 36 | urlcolor=cyan, 37 | } 38 | 39 | \usepackage{todonotes} 40 | \usepackage 41 | [left=1in,top=1in,right=1in,bottom=1in] 42 | {geometry} 43 | 44 | \pagestyle{fancy} 45 | \raggedright 46 | 47 | %--- Header ---% 48 | 49 | \newcommand{\courseNumber}{EECS 470} 50 | \newcommand{\courseTitle}{Computer Architecture} 51 | \newcommand{\university}{University of Michigan, Ann Arbor} 52 | 53 | 54 | 55 | \lhead{ 56 | \small{ 57 | \university 58 | } 59 | } 60 | \rhead{ 61 | \small{ 62 | Last updated by Jielun Tan, 10/2019 \hspace*{-1em} 63 | % Why is the above \hspace necessary? 64 | } 65 | } 66 | 67 | \newcommand{\shortbar}{ 68 | \vspace*{-12pt} 69 | \begin{center} 70 | \rule{5ex}{0.1pt} 71 | \end{center} 72 | } 73 | \newcommand{\lab}[1]{ 74 | \begin{center} 75 | \LARGE{ 76 | \vspace*{-12pt} 77 | EECS 470 - RISC-V Privileged ISA Support 78 | \shortbar 79 | } 80 | \end{center} 81 | } 82 | 83 | 84 | %***********************************************% 85 | % % 86 | % TikZ Definitions % 87 | % % 88 | %***********************************************% 89 | 90 | \usetikzlibrary{shapes,arrows} 91 | 92 | % Block Diagram Styles 93 | \tikzstyle{block} = [draw, fill=blue!20, rectangle, 94 | minimum height=3em, minimum width=6em] 95 | \tikzstyle{sum} = [draw, fill=blue!20, circle, node distance=2cm] 96 | \tikzstyle{input} = [coordinate] 97 | \tikzstyle{output} = [coordinate] 98 | \tikzstyle{branch} = [coordinate] 99 | \tikzstyle{pinstyle} = [pin edge={to-, thin, black}] 100 | 101 | % Signal Flow Graph Styles 102 | \tikzstyle{signal} = [draw, fill=blue!20, circle, 103 | minimum height=3em] 104 | \tikzstyle{state} = [draw, fill=blue!20, circle, 105 | minimum height=3em] 106 | 107 | %***********************************************% 108 | % % 109 | % Document % 110 | % % 111 | %***********************************************% 112 | 113 | \begin{document} 114 | \vspace*{-20pt} 115 | \lab{6} 116 | \vspace*{-20pt} 117 | 118 | \section*{Note:} 119 | \begin{itemize} 120 | \item This is a draft and contents are subjected to change 121 | % \todo[inline]{finish writing this, staff in the future} 122 | \end{itemize} 123 | 124 | \section{Introduction} 125 | Before reading this document, you should have already read the RISC-V Privileged ISA specifications, and if you haven't, you really should go read that first before to trying to understand anything here. We don't need to completely support all the features from the privileged ISA, as that would be an enormous amount of work with a lot of complexity, so this is the point that we go off-script and become only partially compliant to the spec. This is okay, since we control the software that's running on our design, we can guarantee certain behaviors. There are two main features in this project that requires privileged ISA support: exceptions and interrupts. You may choose to support either or both of them. For the rest of this document, we will refer supporting exceptions as \textbf{Exception Handling}, interrupts as \textbf{Interrupt Handling}, and both as \textbf{Trap Handling}. There are a couple additional features and instructions that needs to be implemented for these features. While we may not exactly measure your performance when the test program is trapping, you still want to optimize your datapath around it and report your time to context switch accordingly. In this case, a context switch consists from when a trap is taken to when the first instruction of the trap handler starts executing. 126 | \subsection{Zicsr Instructions} 127 | To support exceptions or interrupts, we need to support certain Control Status Registers (CSR). These set of registers control certain behaviors of the processors and their status affects the execution of certain instructions. The implementation provided in the "csr" branch of the starter code repository has a list of all the CSRs that we will use for the project and what their behaviors will be. Depending on what feature you are supporting, however, not all of them will be used. You do need to support all the CSR instructions, which handles the reading/writing of CSRs. There are a couple changes that we will make to the behaviors though: 128 | \begin{enumerate} 129 | \item Since we don't need to support different privilege modes, and we are using machine mode only, you have RW permissions to all the CSRs that you support, and reading or writing them should not cause any side effects 130 | \item The spec dictates that depending on the instruction, if your source/destination is the zero register, it should not read/write the register and will not cause any side effects. Since we don't have any side effects in the first place, you can choose to still read/write the register to make your implementation simpler 131 | %\item If you are reading an unsupported CSR however, it should trigger an exception. 132 | \end{enumerate} 133 | For an OoO implementation, the CSR instructions can be quite tricky. You may reference to \hyperlink{https://docs.boom-core.org/en/latest/sections/execution-stages.html\#control-status-register-instructions}{BOOM} as an example, but keep in mind that BOOM also full fledgedly support the privileged ISA while we don't. Here are a couple things that you still need to be careful of: 134 | \begin{enumerate} 135 | \item We highly recommend AGAINST renaming the CSRs. CSRs keep track of the status of the processor and updates themselves in case of certain events. Renaming them will require some of kind mapping check every time should anything other than a user specified CSR read/write modify the CSRs. For example, the \texttt{cycle} CSR is a counter of the number of cycles that increments every cycle. Do you really want to go through some kind of mapping check for that every cycle? 136 | \item To guarantee the atomicity of CSR operations, you CANNOT execute CSR instructions \textbf{speculatively}! This means you may not dispatch a CSR instruction unless your ROB is empty, OR you can guarantee that no in-flight instructions will cause a roll-back and cause or be affected by a change in other CSRs. Subsequently, no instruction following the CSR instruction can dispatch until the CSR instruction has retired, because it may be affected by the status of CSR before the change, i.e. reading certain memory regions after disabling/enabling memory protections. This will make dependency handling easier, since any dependency would have been already resolved. 137 | \end{enumerate} 138 | 139 | \subsection{Trap-Return Instructions} 140 | You need to support MRET to return from a trap. However, since we don't need to support privileged levels, you don't need to check the privilege bits in \texttt{mstatus} and can choose whether or not to update the privilege bits. However, you do still need to re-enable the global interrupt enable bits in \texttt{mstatus}. MRET should be implemented regardless of the implementation of \texttt{mstatus}. 141 | 142 | 143 | \section{Exception Handling} 144 | The purpose of exception handling is to trap-and-emulate instructions and thereby achieve full support of RV32IM, minus the system call instructions, ECALL and EBREAK. Furthermore, illegal instructions should trigger an exception and the exception handler will exit the program accordingly. Instructions that involve divisions, namely DIV, DIVU, REM and REMU will cause an exception and they will be emulated in software instead. Refer to the "csr" branch to see an example of an implementation in hardware and the associated software emulation. The pipeline has been modified to support these operations. Note that C runtime setup has been modified slightly, mainly to allocate 1KB of space for the exception handler to use as its own stack own space and store contexts. There are workarounds for that, but right now this is the easier way and we can modify it in the future. 145 | You should also support the following machine mode CSRs. 146 | \begin{itemize} 147 | \item \texttt{mepc} 148 | \item \texttt{mtvec} 149 | \item \texttt{mtval}\footnote{right now we are not supporting trapping on memory access errors, so \texttt{mtval} does not have to log the memory address that is causing the access error} 150 | \item \texttt{mcause} 151 | \item \texttt{mscratch} 152 | \end{itemize} 153 | 154 | Your implementation should produce the same outputs as the example implementation and you are expected to pass all programs provided along with the exception handler. 155 | 156 | % \section{Interrupt Handling} 157 | % \todo[inline]{to be determined} 158 | 159 | % \section{Trap Handling} 160 | % \todo[inline]{to be determined} 161 | \end{document} 162 | --------------------------------------------------------------------------------