├── .gitignore ├── README.md ├── lab-10 ├── code │ ├── alu.v │ ├── decoder_top.v │ ├── memory.v │ ├── register.v │ ├── top.v │ └── top_test.v ├── main-dump.S ├── main.S └── main.o ├── lab-2 ├── add_first.v ├── carry_generator.v ├── four_bit_addr.v ├── full_addr.v └── test.v ├── lab-3 ├── module_top.v └── simu.v ├── lab-4 ├── alu.v ├── register_heap.v ├── register_heap_top.v └── register_test.v ├── lab-5 ├── memory.v └── memory_test.v ├── lab-6 ├── README.md ├── decode │ ├── decode-dump.S │ ├── decode-dump.txt │ ├── decode.S │ └── decode.o ├── main ├── main.c ├── qemu-riscv32 ├── setup.sh ├── task-1 │ ├── hello │ ├── hello.c │ └── hello.s ├── task-2 │ ├── acc-dump.s │ ├── acc.o │ └── acc.s ├── task-3 │ ├── move-dump.s │ ├── move.o │ └── move.s └── task-4 │ ├── sum-self.o │ ├── sum-self.s │ ├── sum.c │ ├── sum.o │ └── sum.s ├── lab-7 ├── decoder_top.v └── simu.v └── lab-8 ├── code ├── alu.v ├── decoder_top.v ├── memory.v ├── register.v └── top.v ├── main-dump.S ├── main-dump.txt ├── main.S └── main.o /.gitignore: -------------------------------------------------------------------------------- 1 | .idea -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/README.md -------------------------------------------------------------------------------- /lab-10/code/alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-10/code/alu.v -------------------------------------------------------------------------------- /lab-10/code/decoder_top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/05/12 11:16:10 7 | // Design Name: 8 | // Module Name: decoder_top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module decoder_top( 24 | input PC_Write, 25 | input IR_Write, 26 | input clk_im, 27 | input [1:0] PC_s, 28 | input PC0_Write, 29 | input [31:0] F, 30 | output [31:0] imm32, 31 | output [4:0] rs1, 32 | output [4:0] rs2, 33 | output [4:0] rd, 34 | output [6:0] opcode, 35 | output [2:0] funct3, 36 | output [6:0] funct7, 37 | output [31:0] PC, 38 | output [31:0] inst, 39 | output [31:0] pc0 40 | // output [31:0] debug 41 | ); 42 | 43 | wire [31:0] inst_Code; 44 | wire [31:0] instr; 45 | wire [31:0] pc; 46 | wire [31:0] new_pc; 47 | wire [5:0] addr; 48 | assign PC = pc; 49 | assign inst = instr; 50 | 51 | // assign debug = inst_Code; 52 | 53 | wire [31:0]origin_pc; 54 | wire [31:0] jal_pc; 55 | wire [31:0] jalr_pc; 56 | wire [31:0] PC0_out; 57 | assign pc0 = PC0_out; 58 | 59 | adder addr_module( 60 | .pc(pc), 61 | .new_pc(origin_pc) 62 | ); 63 | 64 | PC0 PC0_module( 65 | .clk(clk_im), 66 | .PC0_Write(PC0_Write), 67 | .pc(pc), 68 | .PC0_out(PC0_out) 69 | ); 70 | 71 | assign jal_pc = PC0_out + imm32; 72 | assign jalr_pc = F; 73 | 74 | PC_select PC_select_module( 75 | .PC_s(PC_s), 76 | .origin_pc(origin_pc), 77 | .jal_pc(jal_pc), 78 | .jalr_pc(jalr_pc), 79 | .new_pc(new_pc) 80 | ); 81 | 82 | pc_reg pc_module( 83 | .PC_Write(PC_Write), 84 | .clk_im(clk_im), 85 | .now_pc(pc), 86 | .new_pc(new_pc), 87 | .addr(addr) 88 | ); 89 | 90 | RAM_B memory ( 91 | .clka(clk_im), // input wire clka 92 | .wea(0), // input wire [0 : 0] wea 93 | .addra(addr), // input wire [5 : 0] addra 94 | .dina(0), // input wire [31 : 0] dina 95 | .douta(inst_Code) // output wire [31 : 0] douta 96 | ); 97 | 98 | IR ir( 99 | .IR_Write(IR_Write), 100 | .clk_im(clk_im), 101 | .Inst_Code(inst_Code), 102 | .instr(instr) 103 | ); 104 | 105 | ID1 id1( 106 | .instr(instr), 107 | .rs1(rs1), 108 | .rs2(rs2), 109 | .rd(rd), 110 | .opcode(opcode), 111 | .funct3(funct3), 112 | .funct7(funct7), 113 | .imm(imm32) 114 | ); 115 | 116 | endmodule 117 | 118 | module IR( 119 | input IR_Write, 120 | input clk_im, 121 | input [31:0] Inst_Code, 122 | output [31:0] instr 123 | ); 124 | 125 | reg [31:0] ir; 126 | always@(negedge clk_im)begin 127 | if(IR_Write)ir = Inst_Code; 128 | end 129 | assign instr = ir; 130 | endmodule 131 | 132 | module adder( 133 | input [31:0] pc, 134 | output [31:0] new_pc 135 | ); 136 | reg [31:0] A = 0; 137 | always@(*)begin 138 | A = pc + 4; 139 | end 140 | assign new_pc = A; 141 | 142 | endmodule 143 | 144 | module PC0( 145 | input clk, 146 | input PC0_Write, 147 | input [31:0] pc, 148 | output [31:0]PC0_out 149 | ); 150 | 151 | reg [31:0] temp; 152 | always@(negedge clk)begin 153 | if(PC0_Write)temp = pc; 154 | end 155 | assign PC0_out = temp; 156 | endmodule 157 | 158 | module PC_select( 159 | input [1:0] PC_s, 160 | input [31:0] origin_pc, 161 | input [31:0] jal_pc, 162 | input [31:0] jalr_pc, 163 | output [31:0] new_pc 164 | ); 165 | 166 | reg [31:0] temp; 167 | always@(*)begin 168 | if(PC_s == 2'b00)temp = origin_pc; 169 | else if(PC_s == 2'b01)temp = jal_pc; 170 | else if(PC_s == 2'b10)temp = jalr_pc; 171 | end 172 | assign new_pc = temp; 173 | endmodule 174 | 175 | module pc_reg( 176 | input PC_Write, 177 | input clk_im, 178 | input [31:0] new_pc, 179 | output [31:0]now_pc, 180 | output [5:0] addr 181 | ); 182 | 183 | reg [31:0] pc = 0; 184 | 185 | always@(negedge clk_im)begin 186 | if(PC_Write)pc = new_pc; 187 | end 188 | assign now_pc = pc; 189 | assign addr = pc[7:2]; 190 | endmodule 191 | 192 | module ID1 ( 193 | input [31:0] instr, 194 | output [4:0] rs1, 195 | output [4:0] rs2, 196 | output [4:0] rd, 197 | output [6:0] opcode, 198 | output [2:0] funct3, 199 | output [6:0] funct7, 200 | output reg [31:0] imm 201 | ); 202 | 203 | assign rs1 = instr[19:15]; 204 | assign rs2 = instr[24:20]; 205 | assign rd = instr[11:7]; 206 | assign funct7 = instr[31:25]; 207 | assign funct3 = instr[14:12]; 208 | assign opcode = instr[6:0]; 209 | 210 | 211 | wire [31:0] I1imm = {27'b0,instr[24:20]}; 212 | wire [31:0] I2imm = {{21{instr[31]}}, instr[30:20]}; 213 | wire [31:0] Simm = {{21{instr[31]}}, instr[30:25], instr[11:7]}; 214 | wire [31:0] Bimm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; 215 | wire [31:0] Uimm = {instr[31:12], 12'b0}; 216 | wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; 217 | reg flag; 218 | initial flag = 0; 219 | always @(*)begin 220 | case(opcode) 221 | 7'b1101111: imm = Jimm; 222 | 7'b0110011: imm = 0; 223 | 7'b0010011: flag = 1; 224 | 7'b0000011: imm = I2imm; 225 | 7'b1100111: imm = I2imm; 226 | 7'b0100011: imm = Simm; 227 | 7'b1100011: imm = Bimm; 228 | 7'b0110111: imm = Uimm; 229 | 7'b0010111: imm = Uimm; 230 | endcase 231 | if(flag)begin 232 | case(funct3) 233 | 3'b001: imm = I1imm; 234 | 3'b101: imm = I1imm; 235 | default: imm = I2imm; 236 | endcase 237 | flag = 0; 238 | end 239 | end 240 | 241 | endmodule 242 | -------------------------------------------------------------------------------- /lab-10/code/memory.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/05/12 11:18:03 7 | // Design Name: 8 | // Module Name: memory 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module memory( 24 | input Mem_Write, 25 | input clk_dm, 26 | input [7:2] DM_Addr, 27 | input [1:0] MW_Data_s, 28 | output reg [31:0] M_R_Data 29 | ); 30 | 31 | parameter [7:0] data1 = 8'h12; 32 | reg [31:0] M_W_Data; 33 | wire [31:0] temp_R_Data; 34 | RAM_B ram ( 35 | .clka(clk_dm), // input wire clka 36 | .wea(Mem_Write), // input wire [0 : 0] wea 37 | .addra(DM_Addr[7:2]), // input wire [5 : 0] addra 38 | .dina(M_W_Data), // input wire [31 : 0] dina 39 | .douta(temp_R_Data) // output wire [31 : 0] douta 40 | ); 41 | always@(*)begin 42 | if(Mem_Write)begin 43 | case(MW_Data_s) 44 | 2'b00: M_W_Data = {24'b0,data1}; 45 | 2'b01: M_W_Data = {16'b0,data1,8'b0}; 46 | 2'b10: M_W_Data = {8'b0,data1,16'b0}; 47 | 3'b11: M_W_Data = {data1,24'b0}; 48 | endcase 49 | end 50 | else begin 51 | M_R_Data = temp_R_Data; 52 | end 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /lab-10/code/register.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/05/12 11:26:18 7 | // Design Name: 8 | // Module Name: register 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module register_heap( 23 | input Reg_Write, 24 | input clk_Regs, 25 | input rst_n, 26 | input [4:0] R_Addr_A, 27 | input [4:0] R_Addr_B, 28 | input [4:0] W_Addr, 29 | input [31:0] W_Data, 30 | output [31:0] R_Data_A, 31 | output [31:0] R_Data_B 32 | ); 33 | integer i; 34 | reg [31:0] REG_Files[0:31]; 35 | assign R_Data_A = REG_Files[R_Addr_A]; 36 | assign R_Data_B = REG_Files[R_Addr_B]; 37 | always @(negedge clk_Regs or negedge rst_n)begin 38 | if(!rst_n) begin 39 | for(i = 0 ; i < 32 ;i = i + 1)REG_Files[i] <= 0; 40 | end 41 | else begin 42 | if(Reg_Write && W_Addr != 0) 43 | REG_Files[W_Addr] <= W_Data; 44 | end 45 | end 46 | endmodule 47 | 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /lab-10/code/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-10/code/top.v -------------------------------------------------------------------------------- /lab-10/code/top_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/06/05 19:27:24 7 | // Design Name: 8 | // Module Name: top_test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module top_test( 24 | 25 | ); 26 | 27 | reg clk; 28 | reg rst_n; 29 | wire [3:0] FR; 30 | wire [31:0] PC; 31 | wire [31:0] inst; 32 | wire [31:0] W_Data; 33 | wire [31:0] A; 34 | wire [31:0] B; 35 | wire [31:0] F; 36 | wire [31:0] debug; 37 | wire [4:0] Next_ST; 38 | // wire [31:0] pc0; 39 | 40 | top uut( 41 | .clk(clk), 42 | .rst_n(rst_n), 43 | .FR(FR), 44 | .PC(PC), 45 | .inst(inst), 46 | .W_Data(W_Data), 47 | .A(A), 48 | .B(B), 49 | .F(F), 50 | .debug(debug), 51 | .Next_ST(Next_ST) 52 | // .pc0(pc0) 53 | ); 54 | 55 | always #3 clk = ~clk; 56 | 57 | initial begin 58 | clk = 0; 59 | rst_n = 1; 60 | #1 61 | rst_n = 0; 62 | #1 63 | rst_n = 1; 64 | 65 | end 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /lab-10/main-dump.S: -------------------------------------------------------------------------------- 1 | 2 | main.o: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text: 6 | 7 | 00000000
: 8 | 0: 01000513 li a0,16 9 | 4: 00306593 or a1,zero,3 10 | 8: 03004613 xor a2,zero,48 11 | c: 008000ef jal 14 12 | 10: 00062403 lw s0,0(a2) 13 | 14 | 00000014 : 15 | 14: 000502b3 add t0,a0,zero 16 | 18: 0005e333 or t1,a1,zero 17 | 1c: 000073b3 and t2,zero,zero 18 | 19 | 00000020 : 20 | 20: 0002ae03 lw t3,0(t0) 21 | 24: 01c383b3 add t2,t2,t3 22 | 28: 00428293 add t0,t0,4 23 | 2c: fff30313 add t1,t1,-1 24 | 30: 00030463 beqz t1,38 25 | 34: fedff06f j 20 26 | 27 | 00000038 : 28 | 38: 00762023 sw t2,0(a2) 29 | 3c: 00008067 ret 30 | 31 | -------------------------------------------------------------------------------- /lab-10/main.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-10/main.S -------------------------------------------------------------------------------- /lab-10/main.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-10/main.o -------------------------------------------------------------------------------- /lab-2/add_first.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/07 10:59:35 7 | // Design Name: 8 | // Module Name: add_first 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module add_first( 24 | 25 | ); 26 | endmodule 27 | -------------------------------------------------------------------------------- /lab-2/carry_generator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/07 11:19:11 7 | // Design Name: 8 | // Module Name: carry_generator 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module carry_generator( 24 | input [3:0] A , 25 | input [3:0] B , 26 | input Cin , 27 | output [3:1] C , 28 | output Cout 29 | ); 30 | 31 | wire [3:0] P; 32 | wire [3:0] G; 33 | 34 | 35 | assign G[0] = A[0] & B[0]; 36 | assign P[0] = A[0] + B[0]; 37 | assign G[1] = A[1] & B[1]; 38 | assign P[1] = A[1] + B[1]; 39 | assign G[2] = A[2] & B[2]; 40 | assign P[2] = A[2] + B[2]; 41 | assign G[3] = A[3] & B[3]; 42 | assign P[3] = A[3] + B[3]; 43 | 44 | 45 | assign C[1] = G[0] + (P[0] & Cin); 46 | assign C[2] = G[1] + (P[1] & G[0]) + (P[1] & P[0] & Cin); 47 | assign C[3] = G[2] + (P[2] & G[1]) + (P[2] & P[1] & G[0]) + (P[2] & P[1] & P[0] & Cin); 48 | assign Cout = G[3] + (P[3] & G[2]) + (P[3] & P[2] & G[1]) + (P[3] & P[2] & P[1] & G[0]) + (P[3] & P[2] & P[1] & P[0] & Cin); 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /lab-2/four_bit_addr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/07 11:18:30 7 | // Design Name: 8 | // Module Name: four_bit_addr 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module four_bit_addr( 24 | input [3:0] A , 25 | input [3:0] B , 26 | input Cin , 27 | output [3:0] F, 28 | output Cout 29 | ); 30 | wire [3:1] C; 31 | carry_generator u_carry_generator1(A,B,Cin,C,Cout); 32 | 33 | full_addr u_full_addr_1(A[0],B[0],Cin,F[0]); 34 | full_addr u_full_addr_2(A[1],B[1],C[1],F[1]); 35 | full_addr u_full_addr_3(A[2],B[2],C[2],F[2]); 36 | full_addr u_full_addr_4(A[3],B[3],C[3],F[3]); 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /lab-2/full_addr.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/07 11:18:07 7 | // Design Name: 8 | // Module Name: full_addr 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module full_addr( 24 | input A, 25 | input B, 26 | input C, 27 | output F 28 | ); 29 | assign F = A ^ B ^ C; 30 | endmodule 31 | -------------------------------------------------------------------------------- /lab-2/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/07 11:41:57 7 | // Design Name: 8 | // Module Name: test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module test(); 24 | reg [3:0] A; 25 | reg [3:0] B; 26 | reg Cin; 27 | wire [3:0] F; 28 | wire Cout; 29 | 30 | four_bit_addr uut(A,B,Cin,F,Cout); 31 | 32 | initial begin 33 | A = 4'b0000; 34 | B = 4'b0001; 35 | Cin = 1'b1; 36 | 37 | #200 38 | A = 4'b0110; 39 | B = 4'b0101; 40 | Cin = 1'b0; 41 | 42 | #200 43 | A = 4'b1000; 44 | B = 4'b0001; 45 | Cin = 1'b1; 46 | 47 | #200 48 | A = 4'b0100; 49 | B = 4'b0001; 50 | Cin = 1'b1; 51 | 52 | #200 53 | A = 4'b1110; 54 | B = 4'b1101; 55 | Cin = 1'b1; 56 | 57 | end 58 | endmodule 59 | -------------------------------------------------------------------------------- /lab-3/module_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-3/module_top.v -------------------------------------------------------------------------------- /lab-3/simu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/21 15:02:48 7 | // Design Name: 8 | // Module Name: simu 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module simu(); 24 | reg clk_A; 25 | reg clk_B; 26 | reg clk_F; 27 | reg [31:0]in; 28 | reg rst_n; 29 | wire [31:0]F; 30 | wire [3:0]Flags; 31 | 32 | module_top top(clk_A,clk_B,clk_F,in,rst_n,Flags,F); 33 | 34 | initial begin 35 | clk_A = 0; 36 | clk_B = 0; 37 | clk_F = 0; 38 | in = 32'b0; 39 | rst_n = 1; 40 | //1 41 | #5 42 | rst_n = 0; 43 | #5 44 | rst_n = 1; 45 | #5 46 | in = 1; 47 | #5 48 | clk_A = 1; 49 | #5 50 | clk_A = 0; 51 | #5 52 | in = 2; 53 | #5 54 | clk_B = 1; 55 | #5 56 | clk_B = 0; 57 | #5 58 | in = 0; 59 | #5 60 | clk_F = 1; 61 | #5 62 | clk_F = 0; 63 | //2 64 | #5 65 | rst_n = 0; 66 | #5 67 | rst_n = 1; 68 | #5 69 | in = 2; 70 | #5 71 | clk_A = 1; 72 | #5 73 | clk_A = 0; 74 | #5 75 | in = 2; 76 | #5 77 | clk_B = 1; 78 | #5 79 | clk_B = 0; 80 | #5 81 | in = 1; 82 | #5 83 | clk_F = 1; 84 | #5 85 | clk_F = 0; 86 | //3 87 | #5 88 | rst_n = 0; 89 | #5 90 | rst_n = 1; 91 | #5 92 | in = 4; 93 | #5 94 | clk_A = 1; 95 | #5 96 | clk_A = 0; 97 | #5 98 | in = 3; 99 | #5 100 | clk_B = 1; 101 | #5 102 | clk_B = 0; 103 | #5 104 | in = 2; 105 | #5 106 | clk_F = 1; 107 | #5 108 | clk_F = 0; 109 | //4 110 | #5 111 | rst_n = 0; 112 | #5 113 | rst_n = 1; 114 | #5 115 | in = 2; 116 | #5 117 | clk_A = 1; 118 | #5 119 | clk_A = 0; 120 | #5 121 | in = 3; 122 | #5 123 | clk_B = 1; 124 | #5 125 | clk_B = 0; 126 | #5 127 | in = 3; 128 | #5 129 | clk_F = 1; 130 | #5 131 | clk_F = 0; 132 | //5 133 | #5 134 | rst_n = 0; 135 | #5 136 | rst_n = 1; 137 | #5 138 | in = 5; 139 | #5 140 | clk_A = 1; 141 | #5 142 | clk_A = 0; 143 | #5 144 | in = 9; 145 | #5 146 | clk_B = 1; 147 | #5 148 | clk_B = 0; 149 | #5 150 | in = 4; 151 | #5 152 | clk_F = 1; 153 | #5 154 | clk_F = 0; 155 | //6 156 | #5 157 | rst_n = 0; 158 | #5 159 | rst_n = 1; 160 | #5 161 | in = 32'hffff_ffff; 162 | #5 163 | clk_A = 1; 164 | #5 165 | clk_A = 0; 166 | #5 167 | in = 32'h0000_0001; 168 | #5 169 | clk_B = 1; 170 | #5 171 | clk_B = 0; 172 | #5 173 | in = 2; 174 | #5 175 | clk_F = 1; 176 | #5 177 | clk_F = 0; 178 | 179 | //7 180 | #5 181 | rst_n = 0; 182 | #5 183 | rst_n = 1; 184 | #5 185 | in = 32'hffff_ffff; 186 | #5 187 | clk_A = 1; 188 | #5 189 | clk_A = 0; 190 | #5 191 | in = 32'h0000_0001; 192 | #5 193 | clk_B = 1; 194 | #5 195 | clk_B = 0; 196 | #5 197 | in = 3; 198 | #5 199 | clk_F = 1; 200 | #5 201 | clk_F = 0; 202 | 203 | // 8 204 | #5 205 | rst_n = 0; 206 | #5 207 | rst_n = 1; 208 | #5 209 | in = 32'hffff_ffff; 210 | #5 211 | clk_A = 1; 212 | #5 213 | clk_A = 0; 214 | #5 215 | in = 32'h0000_0001; 216 | #5 217 | clk_B = 1; 218 | #5 219 | clk_B = 0; 220 | #5 221 | in = 0; 222 | #5 223 | clk_F = 1; 224 | #5 225 | clk_F = 0; 226 | 227 | 228 | end 229 | endmodule 230 | -------------------------------------------------------------------------------- /lab-4/alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-4/alu.v -------------------------------------------------------------------------------- /lab-4/register_heap.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/14 13:56:35 7 | // Design Name: 8 | // Module Name: register_heap 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module register_heap( 24 | input Reg_Write, 25 | input clk_Regs, 26 | input rst_n, 27 | input [4:0] R_Addr_A, 28 | input [4:0] R_Addr_B, 29 | input [4:0] W_Addr, 30 | input [31:0] W_Data, 31 | output [31:0] R_Data_A, 32 | output [31:0] R_Data_B 33 | ); 34 | integer i; 35 | reg [31:0] REG_Files[0:31]; 36 | initial begin 37 | for(i = 0 ; i < 32 ;i = i + 1)REG_Files[i] = 0; 38 | REG_Files[1] = 2; 39 | end 40 | assign R_Data_A = REG_Files[R_Addr_A]; 41 | assign R_Data_B = REG_Files[R_Addr_B]; 42 | always @(posedge clk_Regs or negedge rst_n)begin 43 | if(!rst_n) begin 44 | for(i = 0 ; i < 32 ;i = i + 1)REG_Files[i] <= 0; 45 | end 46 | else begin 47 | if(Reg_Write && W_Addr != 0) 48 | REG_Files[W_Addr] <= W_Data; 49 | end 50 | end 51 | endmodule 52 | -------------------------------------------------------------------------------- /lab-4/register_heap_top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/21 11:45:53 7 | // Design Name: 8 | // Module Name: register_heap_top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module register_heap_top( 24 | input Reg_Write, 25 | input clk_WB, 26 | input clk_RR, 27 | input clk_F, 28 | input rst_n, 29 | input [4:0] R_Addr_A, 30 | input [4:0] R_Addr_B, 31 | input [4:0] W_Addr, 32 | input [3:0] ALU_OP, 33 | output [31:0] F, 34 | output [3:0] FR, 35 | output [31:0] debug 36 | ); 37 | assign debug = 0; 38 | wire [31:0] temp_A; 39 | wire [31:0] temp_B; 40 | wire [31:0] temp_F; 41 | reg [31:0] reg_F; 42 | reg [31:0] A; 43 | reg [31:0] B; 44 | 45 | register_heap u_register_heap( 46 | .Reg_Write(Reg_Write), 47 | .clk_Regs(clk_WB), 48 | .rst_n(rst_n), 49 | .R_Addr_A(R_Addr_A), 50 | .R_Addr_B(R_Addr_B), 51 | .W_Addr(W_Addr), 52 | .W_Data(F), 53 | .R_Data_A(temp_A), 54 | .R_Data_B(temp_B) 55 | ); 56 | 57 | always@(posedge clk_RR)begin 58 | A <= temp_A; 59 | B <= temp_B; 60 | end 61 | 62 | always@(posedge clk_F)begin 63 | reg_F <= temp_F; 64 | end 65 | assign F = reg_F; 66 | 67 | alu u_alu( 68 | .ALU_A(A), 69 | .ALU_B(B), 70 | .ALU_OP(ALU_OP), 71 | .F(temp_F), 72 | .ZF(FR[0]), 73 | .CF(FR[1]), 74 | .OF(FR[2]), 75 | .SF(FR[3]) 76 | ); 77 | 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /lab-4/register_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/21 14:27:07 7 | // Design Name: 8 | // Module Name: register_test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module register_test(); 24 | 25 | reg Reg_Write; 26 | reg clk_WB; 27 | reg clk_RR; 28 | reg clk_F; 29 | reg rst_n; 30 | reg [4:0] R_Addr_A; 31 | reg [4:0] R_Addr_B; 32 | reg [4:0] W_Addr; 33 | reg [3:0] ALU_OP; 34 | wire [31:0] F; 35 | wire [3:0] FR; 36 | wire [31:0] debug; 37 | 38 | register_heap_top uut( 39 | .Reg_Write(Reg_Write), 40 | .clk_WB(clk_WB), 41 | .clk_RR(clk_RR), 42 | .clk_F(clk_F), 43 | .rst_n(rst_n), 44 | .R_Addr_A(R_Addr_A), 45 | .R_Addr_B(R_Addr_B), 46 | .W_Addr(W_Addr), 47 | .ALU_OP(ALU_OP), 48 | .F(F), 49 | .FR(FR), 50 | .debug(debug) 51 | ); 52 | 53 | initial begin 54 | rst_n = 1; 55 | 56 | // 1 57 | #10 58 | R_Addr_A = 0; 59 | R_Addr_B = 1; 60 | clk_RR = 0; 61 | ALU_OP = 0; 62 | clk_F = 0; 63 | W_Addr = 2; 64 | clk_WB = 0; 65 | 66 | #10; 67 | clk_RR = 1; 68 | #10; 69 | clk_F = 1; 70 | #10; 71 | Reg_Write = 1; 72 | #10; 73 | clk_WB = 1; 74 | // 2 75 | #100; 76 | R_Addr_A = 1; 77 | R_Addr_B = 2; 78 | clk_RR = 0; 79 | ALU_OP = 0; 80 | clk_F = 0; 81 | W_Addr = 3; 82 | clk_WB = 0; 83 | #10; 84 | clk_RR = 1; 85 | #10; 86 | clk_F = 1; 87 | #10; 88 | Reg_Write = 1; 89 | #10; 90 | clk_WB = 1; 91 | end 92 | endmodule 93 | -------------------------------------------------------------------------------- /lab-5/memory.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/21 13:47:09 7 | // Design Name: 8 | // Module Name: memory 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module memory( 24 | input Mem_Write, 25 | input clk_dm, 26 | input [7:2] DM_Addr, 27 | input [1:0] MW_Data_s, 28 | output reg [31:0] M_R_Data 29 | ); 30 | 31 | parameter [7:0] data1 = 8'h12; 32 | reg [31:0] M_W_Data; 33 | wire [31:0] temp_R_Data; 34 | RAM_B ram ( 35 | .clka(clk_dm), // input wire clka 36 | .wea(Mem_Write), // input wire [0 : 0] wea 37 | .addra(DM_Addr[7:2]), // input wire [5 : 0] addra 38 | .dina(M_W_Data), // input wire [31 : 0] dina 39 | .douta(temp_R_Data) // output wire [31 : 0] douta 40 | ); 41 | always@(*)begin 42 | if(Mem_Write)begin 43 | case(MW_Data_s) 44 | 2'b00: M_W_Data = {24'b0,data1}; 45 | 2'b01: M_W_Data = {16'b0,data1,8'b0}; 46 | 2'b10: M_W_Data = {8'b0,data1,16'b0}; 47 | 3'b11: M_W_Data = {data1,24'b0}; 48 | endcase 49 | end 50 | else begin 51 | M_R_Data = temp_R_Data; 52 | end 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /lab-5/memory_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/04/21 14:08:05 7 | // Design Name: 8 | // Module Name: memory_test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module memory_test(); 24 | reg [7:2] DM_Addr; 25 | reg [1:0] MW_Data_s; 26 | reg Mem_Write; 27 | reg clk_dm; 28 | wire [31:0] M_R_Data; 29 | memory uut ( 30 | .DM_Addr(DM_Addr), 31 | .MW_Data_s(MW_Data_s), 32 | .Mem_Write(Mem_Write), 33 | .clk_dm(clk_dm), 34 | .M_R_Data(M_R_Data) 35 | ); 36 | always #20 clk_dm=~clk_dm; 37 | initial begin 38 | // Initialize Inputs 39 | DM_Addr = 0; 40 | MW_Data_s = 0; 41 | Mem_Write = 0; 42 | clk_dm = 0; 43 | #100; 44 | DM_Addr = 0; 45 | MW_Data_s = 0; 46 | Mem_Write = 0; 47 | #100; 48 | DM_Addr = 1; 49 | MW_Data_s = 0; 50 | Mem_Write = 0; 51 | #100; 52 | DM_Addr = 1; 53 | MW_Data_s = 1; 54 | Mem_Write = 1; 55 | #100; 56 | DM_Addr = 1; 57 | MW_Data_s = 0; 58 | Mem_Write = 0; 59 | end 60 | endmodule 61 | -------------------------------------------------------------------------------- /lab-6/README.md: -------------------------------------------------------------------------------- 1 | 为hdu的计组学生提供基本的环境，不需要再安装庞大的虚拟机，只需要一个ubuntu的系统即可。 2 | # 食用方法 3 | hdu提供的文档中的命令包含大量的别名，要想无痛的使用，需要配置别名。 4 | 运行`setup.sh`，然后再重新打开终端，它会自动为你配置好环境。 5 | ```bash 6 | chmod +x setup.sh 7 | ./setup.sh 8 | ``` 9 | 重新打开终端，就可以使用hdu提供的命令了。 10 | # docker部署（推荐） 11 | 由于libc的版本问题，只有ubuntu22.04才可以通过脚本安装环境，如果你的系统版本不是22.04，可以使用docker部署环境。 12 | ```bash 13 | docker pull skynesser/riscv32 14 | # 挂载本机的工作目录到容器中 15 | docker run --name risv32 -d -v {本机的工作目录}:/linux-riscv32 skynesser/riscv32 /bin/bash 16 | # 进入容器 17 | docker exec -it risv32 /bin/bash 18 | ``` -------------------------------------------------------------------------------- /lab-6/decode/decode-dump.S: -------------------------------------------------------------------------------- 1 | 2 | decode.o: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text: 6 | 7 | 00000000 <.text>: 8 | 0: 007302b3 add t0,t1,t2 9 | 4: 00331293 sll t0,t1,0x3 10 | 8: 00230293 add t0,t1,2 11 | c: 00c30283 lb t0,12(t1) 12 | 10: 00530223 sb t0,4(t1) 13 | 14: 00629463 bne t0,t1,1c <.text+0x1c> 14 | 18: 0000006f j 18 <.text+0x18> 15 | 1c: 008302e7 jalr t0,8(t1) 16 | 20: 000002ef jal t0,20 <.text+0x20> 17 | 24: 0000c2b7 lui t0,0xc 18 | -------------------------------------------------------------------------------- /lab-6/decode/decode-dump.txt: -------------------------------------------------------------------------------- 1 | 2 | decode.o: file format elf32-littleriscv 3 | 4 | Contents of section .text: 5 | 0000 b3027300 93123300 93022300 8302c300 ..s...3...#..... 6 | 0010 23025300 63946200 6f000000 e7028300 #.S.c.b.o....... 7 | 0020 ef020000 b7c20000 ........ 8 | Contents of section .riscv.attributes: 9 | 0000 412c0000 00726973 63760001 22000000 A,...riscv.."... 10 | 0010 05727633 32693270 315f6632 70325f64 .rv32i2p1_f2p2_d 11 | 0020 3270325f 7a696373 72327030 00 2p2_zicsr2p0. 12 | -------------------------------------------------------------------------------- /lab-6/decode/decode.S: -------------------------------------------------------------------------------- 1 | add t0,t1,t2 2 | slli t0,t1,3 3 | addi t0,t1,2 4 | lb t0,12(t1) 5 | sb t0,4(t1) 6 | beq t0,t1,12 7 | jalr t0,8(t1) 8 | jal t0,16 9 | lui t0,12 10 | -------------------------------------------------------------------------------- /lab-6/decode/decode.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-6/decode/decode.o -------------------------------------------------------------------------------- /lab-6/main: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-6/main -------------------------------------------------------------------------------- /lab-6/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int main() { 4 | printf("Hello, World!\n"); 5 | return 0; 6 | } -------------------------------------------------------------------------------- /lab-6/qemu-riscv32: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-6/qemu-riscv32 -------------------------------------------------------------------------------- /lab-6/setup.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | path=$(pwd) 4 | 5 | cat << EOF >> ~/.bashrc 6 | export PATH="$path:\$PATH" 7 | export PATH="${path}/riscv/bin:\$PATH" 8 | alias gccrv32="riscv32-unknown-elf-gcc" 9 | alias dumprv32="riscv32-unknown-elf-objdump" 10 | alias runrv32="qemu-riscv32" 11 | EOF 12 | curl -L -o riscv-gnu-toolchain.tar.gz https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.06.02/riscv32-elf-ubuntu-22.04-nightly-2023.06.02-nightly.tar.gz 13 | tar -xvf riscv-gnu-toolchain.tar.gz 14 | 15 | -------------------------------------------------------------------------------- /lab-6/task-1/hello: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-6/task-1/hello -------------------------------------------------------------------------------- /lab-6/task-1/hello.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | int main() { 4 | printf("hello world\n"); 5 | return 0; 6 | } -------------------------------------------------------------------------------- /lab-6/task-1/hello.s: -------------------------------------------------------------------------------- 1 | 2 | hello: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text: 6 | 7 | 00010094 : 8 | 10094: 1141 add sp,sp,-16 9 | 10096: 4581 li a1,0 10 | 10098: c422 sw s0,8(sp) 11 | 1009a: c606 sw ra,12(sp) 12 | 1009c: 842a mv s0,a0 13 | 1009e: 2c4d jal 10350 <__call_exitprocs> 14 | 100a0: 0301a503 lw a0,48(gp) # 13cd0 <_global_impure_ptr> 15 | 100a4: 5d5c lw a5,60(a0) 16 | 100a6: c391 beqz a5,100aa 17 | 100a8: 9782 jalr a5 18 | 100aa: 8522 mv a0,s0 19 | 100ac: 1fc020ef jal 122a8 <_exit> 20 | 21 | 000100b0 : 22 | 100b0: 00000793 li a5,0 23 | 100b4: c789 beqz a5,100be 24 | 100b6: 6541 lui a0,0x10 25 | 100b8: 69450513 add a0,a0,1684 # 10694 <__libc_fini_array> 26 | 100bc: ae89 j 1040e 27 | 100be: 8082 ret 28 | 29 | 000100c0 <_start>: 30 | 100c0: 00004197 auipc gp,0x4 31 | 100c4: be018193 add gp,gp,-1056 # 13ca0 <__global_pointer$> 32 | 100c8: 04418513 add a0,gp,68 # 13ce4 <__malloc_max_total_mem> 33 | 100cc: 09c18613 add a2,gp,156 # 13d3c <__BSS_END__> 34 | 100d0: 8e09 sub a2,a2,a0 35 | 100d2: 4581 li a1,0 36 | 100d4: 28c5 jal 101c4 37 | 100d6: 00000517 auipc a0,0x0 38 | 100da: 33850513 add a0,a0,824 # 1040e 39 | 100de: c511 beqz a0,100ea <_start+0x2a> 40 | 100e0: 00000517 auipc a0,0x0 41 | 100e4: 5b450513 add a0,a0,1460 # 10694 <__libc_fini_array> 42 | 100e8: 261d jal 1040e 43 | 100ea: 2885 jal 1015a <__libc_init_array> 44 | 100ec: 4502 lw a0,0(sp) 45 | 100ee: 004c add a1,sp,4 46 | 100f0: 4601 li a2,0 47 | 100f2: 20b1 jal 1013e
48 | 100f4: b745 j 10094 49 | 50 | 000100f6 <__do_global_dtors_aux>: 51 | 100f6: 1141 add sp,sp,-16 52 | 100f8: c422 sw s0,8(sp) 53 | 100fa: 0581c783 lbu a5,88(gp) # 13cf8 54 | 100fe: c606 sw ra,12(sp) 55 | 10100: ef91 bnez a5,1011c <__do_global_dtors_aux+0x26> 56 | 10102: 00000793 li a5,0 57 | 10106: cb81 beqz a5,10116 <__do_global_dtors_aux+0x20> 58 | 10108: 654d lui a0,0x13 59 | 1010a: 48c50513 add a0,a0,1164 # 1348c <__EH_FRAME_BEGIN__> 60 | 1010e: 00000097 auipc ra,0x0 61 | 10112: 000000e7 jalr zero # 0 62 | 10116: 4785 li a5,1 63 | 10118: 04f18c23 sb a5,88(gp) # 13cf8 64 | 1011c: 40b2 lw ra,12(sp) 65 | 1011e: 4422 lw s0,8(sp) 66 | 10120: 0141 add sp,sp,16 67 | 10122: 8082 ret 68 | 69 | 00010124 : 70 | 10124: 00000793 li a5,0 71 | 10128: cb91 beqz a5,1013c 72 | 1012a: 654d lui a0,0x13 73 | 1012c: 05c18593 add a1,gp,92 # 13cfc 74 | 10130: 48c50513 add a0,a0,1164 # 1348c <__EH_FRAME_BEGIN__> 75 | 10134: 00000317 auipc t1,0x0 76 | 10138: 00000067 jr zero # 0 77 | 1013c: 8082 ret 78 | 79 | 0001013e
: 80 | 1013e: 1141 add sp,sp,-16 81 | 10140: c606 sw ra,12(sp) 82 | 10142: c422 sw s0,8(sp) 83 | 10144: 0800 add s0,sp,16 84 | 10146: 67c9 lui a5,0x12 85 | 10148: 47c78513 add a0,a5,1148 # 1247c <__errno+0x8> 86 | 1014c: 2a61 jal 102e4 87 | 1014e: 4781 li a5,0 88 | 10150: 853e mv a0,a5 89 | 10152: 40b2 lw ra,12(sp) 90 | 10154: 4422 lw s0,8(sp) 91 | 10156: 0141 add sp,sp,16 92 | 10158: 8082 ret 93 | 94 | 0001015a <__libc_init_array>: 95 | 1015a: 1141 add sp,sp,-16 96 | 1015c: c422 sw s0,8(sp) 97 | 1015e: 67cd lui a5,0x13 98 | 10160: 644d lui s0,0x13 99 | 10162: c04a sw s2,0(sp) 100 | 10164: 49078793 add a5,a5,1168 # 13490 <__init_array_start> 101 | 10168: 49040713 add a4,s0,1168 # 13490 <__init_array_start> 102 | 1016c: c606 sw ra,12(sp) 103 | 1016e: c226 sw s1,4(sp) 104 | 10170: 40e78933 sub s2,a5,a4 105 | 10174: 00e78d63 beq a5,a4,1018e <__libc_init_array+0x34> 106 | 10178: 40295913 sra s2,s2,0x2 107 | 1017c: 49040413 add s0,s0,1168 108 | 10180: 4481 li s1,0 109 | 10182: 401c lw a5,0(s0) 110 | 10184: 0485 add s1,s1,1 111 | 10186: 0411 add s0,s0,4 112 | 10188: 9782 jalr a5 113 | 1018a: ff24ece3 bltu s1,s2,10182 <__libc_init_array+0x28> 114 | 1018e: 644d lui s0,0x13 115 | 10190: 67cd lui a5,0x13 116 | 10192: 49878793 add a5,a5,1176 # 13498 <__do_global_dtors_aux_fini_array_entry> 117 | 10196: 49040713 add a4,s0,1168 # 13490 <__init_array_start> 118 | 1019a: 40e78933 sub s2,a5,a4 119 | 1019e: 40295913 sra s2,s2,0x2 120 | 101a2: 00e78b63 beq a5,a4,101b8 <__libc_init_array+0x5e> 121 | 101a6: 49040413 add s0,s0,1168 122 | 101aa: 4481 li s1,0 123 | 101ac: 401c lw a5,0(s0) 124 | 101ae: 0485 add s1,s1,1 125 | 101b0: 0411 add s0,s0,4 126 | 101b2: 9782 jalr a5 127 | 101b4: ff24ece3 bltu s1,s2,101ac <__libc_init_array+0x52> 128 | 101b8: 40b2 lw ra,12(sp) 129 | 101ba: 4422 lw s0,8(sp) 130 | 101bc: 4492 lw s1,4(sp) 131 | 101be: 4902 lw s2,0(sp) 132 | 101c0: 0141 add sp,sp,16 133 | 101c2: 8082 ret 134 | 135 | 000101c4 : 136 | 101c4: 433d li t1,15 137 | 101c6: 872a mv a4,a0 138 | 101c8: 02c37363 bgeu t1,a2,101ee 139 | 101cc: 00f77793 and a5,a4,15 140 | 101d0: efbd bnez a5,1024e 141 | 101d2: e5ad bnez a1,1023c 142 | 101d4: ff067693 and a3,a2,-16 143 | 101d8: 8a3d and a2,a2,15 144 | 101da: 96ba add a3,a3,a4 145 | 101dc: c30c sw a1,0(a4) 146 | 101de: c34c sw a1,4(a4) 147 | 101e0: c70c sw a1,8(a4) 148 | 101e2: c74c sw a1,12(a4) 149 | 101e4: 0741 add a4,a4,16 150 | 101e6: fed76be3 bltu a4,a3,101dc 151 | 101ea: e211 bnez a2,101ee 152 | 101ec: 8082 ret 153 | 101ee: 40c306b3 sub a3,t1,a2 154 | 101f2: 068a sll a3,a3,0x2 155 | 101f4: 00000297 auipc t0,0x0 156 | 101f8: 9696 add a3,a3,t0 157 | 101fa: 00a68067 jr 10(a3) 158 | 101fe: 00b70723 sb a1,14(a4) 159 | 10202: 00b706a3 sb a1,13(a4) 160 | 10206: 00b70623 sb a1,12(a4) 161 | 1020a: 00b705a3 sb a1,11(a4) 162 | 1020e: 00b70523 sb a1,10(a4) 163 | 10212: 00b704a3 sb a1,9(a4) 164 | 10216: 00b70423 sb a1,8(a4) 165 | 1021a: 00b703a3 sb a1,7(a4) 166 | 1021e: 00b70323 sb a1,6(a4) 167 | 10222: 00b702a3 sb a1,5(a4) 168 | 10226: 00b70223 sb a1,4(a4) 169 | 1022a: 00b701a3 sb a1,3(a4) 170 | 1022e: 00b70123 sb a1,2(a4) 171 | 10232: 00b700a3 sb a1,1(a4) 172 | 10236: 00b70023 sb a1,0(a4) 173 | 1023a: 8082 ret 174 | 1023c: 0ff5f593 zext.b a1,a1 175 | 10240: 00859693 sll a3,a1,0x8 176 | 10244: 8dd5 or a1,a1,a3 177 | 10246: 01059693 sll a3,a1,0x10 178 | 1024a: 8dd5 or a1,a1,a3 179 | 1024c: b761 j 101d4 180 | 1024e: 00279693 sll a3,a5,0x2 181 | 10252: 00000297 auipc t0,0x0 182 | 10256: 9696 add a3,a3,t0 183 | 10258: 8286 mv t0,ra 184 | 1025a: fa8680e7 jalr -88(a3) 185 | 1025e: 8096 mv ra,t0 186 | 10260: 17c1 add a5,a5,-16 187 | 10262: 8f1d sub a4,a4,a5 188 | 10264: 963e add a2,a2,a5 189 | 10266: f8c374e3 bgeu t1,a2,101ee 190 | 1026a: b7a5 j 101d2 191 | 192 | 0001026c <_puts_r>: 193 | 1026c: 7139 add sp,sp,-64 194 | 1026e: dc22 sw s0,56(sp) 195 | 10270: 842a mv s0,a0 196 | 10272: 852e mv a0,a1 197 | 10274: da26 sw s1,52(sp) 198 | 10276: de06 sw ra,60(sp) 199 | 10278: 84ae mv s1,a1 200 | 1027a: 288d jal 102ec 201 | 1027c: 67c9 lui a5,0x12 202 | 1027e: 48878793 add a5,a5,1160 # 12488 <__errno+0x14> 203 | 10282: d43e sw a5,40(sp) 204 | 10284: 4785 li a5,1 205 | 10286: d63e sw a5,44(sp) 206 | 10288: 5c18 lw a4,56(s0) 207 | 1028a: 101c add a5,sp,32 208 | 1028c: 00150693 add a3,a0,1 209 | 10290: ca3e sw a5,20(sp) 210 | 10292: 4789 li a5,2 211 | 10294: d026 sw s1,32(sp) 212 | 10296: d22a sw a0,36(sp) 213 | 10298: ce36 sw a3,28(sp) 214 | 1029a: cc3e sw a5,24(sp) 215 | 1029c: 440c lw a1,8(s0) 216 | 1029e: cf15 beqz a4,102da <_puts_r+0x6e> 217 | 102a0: 00c59783 lh a5,12(a1) 218 | 102a4: 01279713 sll a4,a5,0x12 219 | 102a8: 00074b63 bltz a4,102be <_puts_r+0x52> 220 | 102ac: 51f8 lw a4,100(a1) 221 | 102ae: 6689 lui a3,0x2 222 | 102b0: 8fd5 or a5,a5,a3 223 | 102b2: 76f9 lui a3,0xffffe 224 | 102b4: 16fd add a3,a3,-1 # ffffdfff <__BSS_END__+0xfffea2c3> 225 | 102b6: 8f75 and a4,a4,a3 226 | 102b8: 00f59623 sh a5,12(a1) 227 | 102bc: d1f8 sw a4,100(a1) 228 | 102be: 0850 add a2,sp,20 229 | 102c0: 8522 mv a0,s0 230 | 102c2: 2119 jal 106c8 <__sfvwrite_r> 231 | 102c4: 50f2 lw ra,60(sp) 232 | 102c6: 5462 lw s0,56(sp) 233 | 102c8: 00153513 seqz a0,a0 234 | 102cc: 40a00533 neg a0,a0 235 | 102d0: 892d and a0,a0,11 236 | 102d2: 54d2 lw s1,52(sp) 237 | 102d4: 157d add a0,a0,-1 238 | 102d6: 6121 add sp,sp,64 239 | 102d8: 8082 ret 240 | 102da: 8522 mv a0,s0 241 | 102dc: c62e sw a1,12(sp) 242 | 102de: 2679 jal 1066c <__sinit> 243 | 102e0: 45b2 lw a1,12(sp) 244 | 102e2: bf7d j 102a0 <_puts_r+0x34> 245 | 246 | 000102e4 : 247 | 102e4: 85aa mv a1,a0 248 | 102e6: 0381a503 lw a0,56(gp) # 13cd8 <_impure_ptr> 249 | 102ea: b749 j 1026c <_puts_r> 250 | 251 | 000102ec : 252 | 102ec: 00357793 and a5,a0,3 253 | 102f0: 872a mv a4,a0 254 | 102f2: ef9d bnez a5,10330 255 | 102f4: 7f7f86b7 lui a3,0x7f7f8 256 | 102f8: f7f68693 add a3,a3,-129 # 7f7f7f7f <__BSS_END__+0x7f7e4243> 257 | 102fc: 55fd li a1,-1 258 | 102fe: 4310 lw a2,0(a4) 259 | 10300: 0711 add a4,a4,4 260 | 10302: 00d677b3 and a5,a2,a3 261 | 10306: 97b6 add a5,a5,a3 262 | 10308: 8fd1 or a5,a5,a2 263 | 1030a: 8fd5 or a5,a5,a3 264 | 1030c: feb789e3 beq a5,a1,102fe 265 | 10310: ffc74683 lbu a3,-4(a4) 266 | 10314: 40a707b3 sub a5,a4,a0 267 | 10318: ca8d beqz a3,1034a 268 | 1031a: ffd74683 lbu a3,-3(a4) 269 | 1031e: c29d beqz a3,10344 270 | 10320: ffe74503 lbu a0,-2(a4) 271 | 10324: 00a03533 snez a0,a0 272 | 10328: 953e add a0,a0,a5 273 | 1032a: 1579 add a0,a0,-2 274 | 1032c: 8082 ret 275 | 1032e: d2f9 beqz a3,102f4 276 | 10330: 00074783 lbu a5,0(a4) 277 | 10334: 0705 add a4,a4,1 278 | 10336: 00377693 and a3,a4,3 279 | 1033a: fbf5 bnez a5,1032e 280 | 1033c: 8f09 sub a4,a4,a0 281 | 1033e: fff70513 add a0,a4,-1 282 | 10342: 8082 ret 283 | 10344: ffd78513 add a0,a5,-3 284 | 10348: 8082 ret 285 | 1034a: ffc78513 add a0,a5,-4 286 | 1034e: 8082 ret 287 | 288 | 00010350 <__call_exitprocs>: 289 | 10350: 7179 add sp,sp,-48 290 | 10352: cc52 sw s4,24(sp) 291 | 10354: 0301aa03 lw s4,48(gp) # 13cd0 <_global_impure_ptr> 292 | 10358: d04a sw s2,32(sp) 293 | 1035a: d606 sw ra,44(sp) 294 | 1035c: 148a2903 lw s2,328(s4) 295 | 10360: d422 sw s0,40(sp) 296 | 10362: d226 sw s1,36(sp) 297 | 10364: ce4e sw s3,28(sp) 298 | 10366: ca56 sw s5,20(sp) 299 | 10368: c85a sw s6,16(sp) 300 | 1036a: c65e sw s7,12(sp) 301 | 1036c: c462 sw s8,8(sp) 302 | 1036e: 02090863 beqz s2,1039e <__call_exitprocs+0x4e> 303 | 10372: 8b2a mv s6,a0 304 | 10374: 8bae mv s7,a1 305 | 10376: 4a85 li s5,1 306 | 10378: 59fd li s3,-1 307 | 1037a: 00492483 lw s1,4(s2) 308 | 1037e: fff48413 add s0,s1,-1 309 | 10382: 00044e63 bltz s0,1039e <__call_exitprocs+0x4e> 310 | 10386: 048a sll s1,s1,0x2 311 | 10388: 94ca add s1,s1,s2 312 | 1038a: 020b8663 beqz s7,103b6 <__call_exitprocs+0x66> 313 | 1038e: 1044a783 lw a5,260(s1) 314 | 10392: 03778263 beq a5,s7,103b6 <__call_exitprocs+0x66> 315 | 10396: 147d add s0,s0,-1 316 | 10398: 14f1 add s1,s1,-4 317 | 1039a: ff3418e3 bne s0,s3,1038a <__call_exitprocs+0x3a> 318 | 1039e: 50b2 lw ra,44(sp) 319 | 103a0: 5422 lw s0,40(sp) 320 | 103a2: 5492 lw s1,36(sp) 321 | 103a4: 5902 lw s2,32(sp) 322 | 103a6: 49f2 lw s3,28(sp) 323 | 103a8: 4a62 lw s4,24(sp) 324 | 103aa: 4ad2 lw s5,20(sp) 325 | 103ac: 4b42 lw s6,16(sp) 326 | 103ae: 4bb2 lw s7,12(sp) 327 | 103b0: 4c22 lw s8,8(sp) 328 | 103b2: 6145 add sp,sp,48 329 | 103b4: 8082 ret 330 | 103b6: 00492783 lw a5,4(s2) 331 | 103ba: 40d4 lw a3,4(s1) 332 | 103bc: 17fd add a5,a5,-1 333 | 103be: 04878263 beq a5,s0,10402 <__call_exitprocs+0xb2> 334 | 103c2: 0004a223 sw zero,4(s1) 335 | 103c6: dae1 beqz a3,10396 <__call_exitprocs+0x46> 336 | 103c8: 18892783 lw a5,392(s2) 337 | 103cc: 008a9733 sll a4,s5,s0 338 | 103d0: 00492c03 lw s8,4(s2) 339 | 103d4: 8ff9 and a5,a5,a4 340 | 103d6: ef89 bnez a5,103f0 <__call_exitprocs+0xa0> 341 | 103d8: 9682 jalr a3 342 | 103da: 00492703 lw a4,4(s2) 343 | 103de: 148a2783 lw a5,328(s4) 344 | 103e2: 01871463 bne a4,s8,103ea <__call_exitprocs+0x9a> 345 | 103e6: fb2788e3 beq a5,s2,10396 <__call_exitprocs+0x46> 346 | 103ea: dbd5 beqz a5,1039e <__call_exitprocs+0x4e> 347 | 103ec: 893e mv s2,a5 348 | 103ee: b771 j 1037a <__call_exitprocs+0x2a> 349 | 103f0: 18c92783 lw a5,396(s2) 350 | 103f4: 0844a583 lw a1,132(s1) 351 | 103f8: 8f7d and a4,a4,a5 352 | 103fa: e719 bnez a4,10408 <__call_exitprocs+0xb8> 353 | 103fc: 855a mv a0,s6 354 | 103fe: 9682 jalr a3 355 | 10400: bfe9 j 103da <__call_exitprocs+0x8a> 356 | 10402: 00892223 sw s0,4(s2) 357 | 10406: b7c1 j 103c6 <__call_exitprocs+0x76> 358 | 10408: 852e mv a0,a1 359 | 1040a: 9682 jalr a3 360 | 1040c: b7f9 j 103da <__call_exitprocs+0x8a> 361 | 362 | 0001040e : 363 | 1040e: 85aa mv a1,a0 364 | 10410: 4681 li a3,0 365 | 10412: 4601 li a2,0 366 | 10414: 4501 li a0,0 367 | 10416: 4be0106f j 118d4 <__register_exitproc> 368 | 369 | 0001041a <__fp_lock>: 370 | 1041a: 4501 li a0,0 371 | 1041c: 8082 ret 372 | 373 | 0001041e <_cleanup_r>: 374 | 1041e: 65c9 lui a1,0x12 375 | 10420: 97658593 add a1,a1,-1674 # 11976 <_fclose_r> 376 | 10424: a535 j 10a50 <_fwalk_reent> 377 | 378 | 00010426 <__fp_unlock>: 379 | 10426: 4501 li a0,0 380 | 10428: 8082 ret 381 | 382 | 0001042a <__sinit.part.0>: 383 | 1042a: 1101 add sp,sp,-32 384 | 1042c: 67c1 lui a5,0x10 385 | 1042e: ce06 sw ra,28(sp) 386 | 10430: cc22 sw s0,24(sp) 387 | 10432: ca26 sw s1,20(sp) 388 | 10434: c84a sw s2,16(sp) 389 | 10436: c64e sw s3,12(sp) 390 | 10438: c452 sw s4,8(sp) 391 | 1043a: c256 sw s5,4(sp) 392 | 1043c: c05a sw s6,0(sp) 393 | 1043e: 4140 lw s0,4(a0) 394 | 10440: 41e78793 add a5,a5,1054 # 1041e <_cleanup_r> 395 | 10444: dd5c sw a5,60(a0) 396 | 10446: 2ec50713 add a4,a0,748 397 | 1044a: 478d li a5,3 398 | 1044c: 2ee52423 sw a4,744(a0) 399 | 10450: 2ef52223 sw a5,740(a0) 400 | 10454: 2e052023 sw zero,736(a0) 401 | 10458: 4791 li a5,4 402 | 1045a: 892a mv s2,a0 403 | 1045c: c45c sw a5,12(s0) 404 | 1045e: 4621 li a2,8 405 | 10460: 4581 li a1,0 406 | 10462: 00042023 sw zero,0(s0) 407 | 10466: 00042223 sw zero,4(s0) 408 | 1046a: 00042423 sw zero,8(s0) 409 | 1046e: 06042223 sw zero,100(s0) 410 | 10472: 00042823 sw zero,16(s0) 411 | 10476: 00042a23 sw zero,20(s0) 412 | 1047a: 00042c23 sw zero,24(s0) 413 | 1047e: 05c40513 add a0,s0,92 414 | 10482: 3389 jal 101c4 415 | 10484: 6b45 lui s6,0x11 416 | 10486: 00892483 lw s1,8(s2) 417 | 1048a: 6ac5 lui s5,0x11 418 | 1048c: 6a45 lui s4,0x11 419 | 1048e: 69c5 lui s3,0x11 420 | 10490: 6e2b0b13 add s6,s6,1762 # 116e2 <__sread> 421 | 10494: 71ea8a93 add s5,s5,1822 # 1171e <__swrite> 422 | 10498: 770a0a13 add s4,s4,1904 # 11770 <__sseek> 423 | 1049c: 7ba98993 add s3,s3,1978 # 117ba <__sclose> 424 | 104a0: 67c1 lui a5,0x10 425 | 104a2: 03642023 sw s6,32(s0) 426 | 104a6: 03542223 sw s5,36(s0) 427 | 104aa: 03442423 sw s4,40(s0) 428 | 104ae: 03342623 sw s3,44(s0) 429 | 104b2: cc40 sw s0,28(s0) 430 | 104b4: 07a5 add a5,a5,9 # 10009 431 | 104b6: c4dc sw a5,12(s1) 432 | 104b8: 4621 li a2,8 433 | 104ba: 4581 li a1,0 434 | 104bc: 0004a023 sw zero,0(s1) 435 | 104c0: 0004a223 sw zero,4(s1) 436 | 104c4: 0004a423 sw zero,8(s1) 437 | 104c8: 0604a223 sw zero,100(s1) 438 | 104cc: 0004a823 sw zero,16(s1) 439 | 104d0: 0004aa23 sw zero,20(s1) 440 | 104d4: 0004ac23 sw zero,24(s1) 441 | 104d8: 05c48513 add a0,s1,92 442 | 104dc: 31e5 jal 101c4 443 | 104de: 00c92403 lw s0,12(s2) 444 | 104e2: 000207b7 lui a5,0x20 445 | 104e6: 0364a023 sw s6,32(s1) 446 | 104ea: 0354a223 sw s5,36(s1) 447 | 104ee: 0344a423 sw s4,40(s1) 448 | 104f2: 0334a623 sw s3,44(s1) 449 | 104f6: ccc4 sw s1,28(s1) 450 | 104f8: 07c9 add a5,a5,18 # 20012 <__BSS_END__+0xc2d6> 451 | 104fa: c45c sw a5,12(s0) 452 | 104fc: 00042023 sw zero,0(s0) 453 | 10500: 00042223 sw zero,4(s0) 454 | 10504: 00042423 sw zero,8(s0) 455 | 10508: 06042223 sw zero,100(s0) 456 | 1050c: 00042823 sw zero,16(s0) 457 | 10510: 00042a23 sw zero,20(s0) 458 | 10514: 00042c23 sw zero,24(s0) 459 | 10518: 05c40513 add a0,s0,92 460 | 1051c: 4621 li a2,8 461 | 1051e: 4581 li a1,0 462 | 10520: 3155 jal 101c4 463 | 10522: 40f2 lw ra,28(sp) 464 | 10524: 03642023 sw s6,32(s0) 465 | 10528: 03542223 sw s5,36(s0) 466 | 1052c: 03442423 sw s4,40(s0) 467 | 10530: 03342623 sw s3,44(s0) 468 | 10534: cc40 sw s0,28(s0) 469 | 10536: 4462 lw s0,24(sp) 470 | 10538: 4785 li a5,1 471 | 1053a: 02f92c23 sw a5,56(s2) 472 | 1053e: 44d2 lw s1,20(sp) 473 | 10540: 4942 lw s2,16(sp) 474 | 10542: 49b2 lw s3,12(sp) 475 | 10544: 4a22 lw s4,8(sp) 476 | 10546: 4a92 lw s5,4(sp) 477 | 10548: 4b02 lw s6,0(sp) 478 | 1054a: 6105 add sp,sp,32 479 | 1054c: 8082 ret 480 | 481 | 0001054e <__sfmoreglue>: 482 | 1054e: 1141 add sp,sp,-16 483 | 10550: c226 sw s1,4(sp) 484 | 10552: 06800793 li a5,104 485 | 10556: fff58493 add s1,a1,-1 486 | 1055a: 02f484b3 mul s1,s1,a5 487 | 1055e: c04a sw s2,0(sp) 488 | 10560: 892e mv s2,a1 489 | 10562: c422 sw s0,8(sp) 490 | 10564: c606 sw ra,12(sp) 491 | 10566: 07448593 add a1,s1,116 492 | 1056a: 2ba9 jal 10ac4 <_malloc_r> 493 | 1056c: 842a mv s0,a0 494 | 1056e: c919 beqz a0,10584 <__sfmoreglue+0x36> 495 | 10570: 0531 add a0,a0,12 496 | 10572: 00042023 sw zero,0(s0) 497 | 10576: 01242223 sw s2,4(s0) 498 | 1057a: c408 sw a0,8(s0) 499 | 1057c: 06848613 add a2,s1,104 500 | 10580: 4581 li a1,0 501 | 10582: 3189 jal 101c4 502 | 10584: 40b2 lw ra,12(sp) 503 | 10586: 8522 mv a0,s0 504 | 10588: 4422 lw s0,8(sp) 505 | 1058a: 4492 lw s1,4(sp) 506 | 1058c: 4902 lw s2,0(sp) 507 | 1058e: 0141 add sp,sp,16 508 | 10590: 8082 ret 509 | 510 | 00010592 <__sfp>: 511 | 10592: 1101 add sp,sp,-32 512 | 10594: c84a sw s2,16(sp) 513 | 10596: 0301a903 lw s2,48(gp) # 13cd0 <_global_impure_ptr> 514 | 1059a: c64e sw s3,12(sp) 515 | 1059c: ce06 sw ra,28(sp) 516 | 1059e: 03892783 lw a5,56(s2) 517 | 105a2: cc22 sw s0,24(sp) 518 | 105a4: ca26 sw s1,20(sp) 519 | 105a6: 89aa mv s3,a0 520 | 105a8: cfbd beqz a5,10626 <__sfp+0x94> 521 | 105aa: 2e090913 add s2,s2,736 522 | 105ae: 54fd li s1,-1 523 | 105b0: 00492783 lw a5,4(s2) 524 | 105b4: 00892403 lw s0,8(s2) 525 | 105b8: 17fd add a5,a5,-1 526 | 105ba: 0007d763 bgez a5,105c8 <__sfp+0x36> 527 | 105be: a8b9 j 1061c <__sfp+0x8a> 528 | 105c0: 06840413 add s0,s0,104 529 | 105c4: 04978c63 beq a5,s1,1061c <__sfp+0x8a> 530 | 105c8: 00c41703 lh a4,12(s0) 531 | 105cc: 17fd add a5,a5,-1 532 | 105ce: fb6d bnez a4,105c0 <__sfp+0x2e> 533 | 105d0: 77c1 lui a5,0xffff0 534 | 105d2: 0785 add a5,a5,1 # ffff0001 <__BSS_END__+0xfffdc2c5> 535 | 105d4: c45c sw a5,12(s0) 536 | 105d6: 06042223 sw zero,100(s0) 537 | 105da: 00042023 sw zero,0(s0) 538 | 105de: 00042423 sw zero,8(s0) 539 | 105e2: 00042223 sw zero,4(s0) 540 | 105e6: 00042823 sw zero,16(s0) 541 | 105ea: 00042a23 sw zero,20(s0) 542 | 105ee: 00042c23 sw zero,24(s0) 543 | 105f2: 4621 li a2,8 544 | 105f4: 4581 li a1,0 545 | 105f6: 05c40513 add a0,s0,92 546 | 105fa: 36e9 jal 101c4 547 | 105fc: 02042823 sw zero,48(s0) 548 | 10600: 02042a23 sw zero,52(s0) 549 | 10604: 04042223 sw zero,68(s0) 550 | 10608: 04042423 sw zero,72(s0) 551 | 1060c: 40f2 lw ra,28(sp) 552 | 1060e: 8522 mv a0,s0 553 | 10610: 4462 lw s0,24(sp) 554 | 10612: 44d2 lw s1,20(sp) 555 | 10614: 4942 lw s2,16(sp) 556 | 10616: 49b2 lw s3,12(sp) 557 | 10618: 6105 add sp,sp,32 558 | 1061a: 8082 ret 559 | 1061c: 00092403 lw s0,0(s2) 560 | 10620: c411 beqz s0,1062c <__sfp+0x9a> 561 | 10622: 8922 mv s2,s0 562 | 10624: b771 j 105b0 <__sfp+0x1e> 563 | 10626: 854a mv a0,s2 564 | 10628: 3509 jal 1042a <__sinit.part.0> 565 | 1062a: b741 j 105aa <__sfp+0x18> 566 | 1062c: 1ac00593 li a1,428 567 | 10630: 854e mv a0,s3 568 | 10632: 2949 jal 10ac4 <_malloc_r> 569 | 10634: 842a mv s0,a0 570 | 10636: cd19 beqz a0,10654 <__sfp+0xc2> 571 | 10638: 0531 add a0,a0,12 572 | 1063a: 4791 li a5,4 573 | 1063c: 00042023 sw zero,0(s0) 574 | 10640: c05c sw a5,4(s0) 575 | 10642: c408 sw a0,8(s0) 576 | 10644: 1a000613 li a2,416 577 | 10648: 4581 li a1,0 578 | 1064a: 3ead jal 101c4 579 | 1064c: 00892023 sw s0,0(s2) 580 | 10650: 8922 mv s2,s0 581 | 10652: bfb9 j 105b0 <__sfp+0x1e> 582 | 10654: 00092023 sw zero,0(s2) 583 | 10658: 47b1 li a5,12 584 | 1065a: 00f9a023 sw a5,0(s3) 585 | 1065e: b77d j 1060c <__sfp+0x7a> 586 | 587 | 00010660 <_cleanup>: 588 | 10660: 0301a503 lw a0,48(gp) # 13cd0 <_global_impure_ptr> 589 | 10664: 65c9 lui a1,0x12 590 | 10666: 97658593 add a1,a1,-1674 # 11976 <_fclose_r> 591 | 1066a: a6dd j 10a50 <_fwalk_reent> 592 | 593 | 0001066c <__sinit>: 594 | 1066c: 5d1c lw a5,56(a0) 595 | 1066e: c391 beqz a5,10672 <__sinit+0x6> 596 | 10670: 8082 ret 597 | 10672: bb65 j 1042a <__sinit.part.0> 598 | 599 | 00010674 <__sfp_lock_acquire>: 600 | 10674: 8082 ret 601 | 602 | 00010676 <__sfp_lock_release>: 603 | 10676: 8082 ret 604 | 605 | 00010678 <__sinit_lock_acquire>: 606 | 10678: 8082 ret 607 | 608 | 0001067a <__sinit_lock_release>: 609 | 1067a: 8082 ret 610 | 611 | 0001067c <__fp_lock_all>: 612 | 1067c: 0381a503 lw a0,56(gp) # 13cd8 <_impure_ptr> 613 | 10680: 65c1 lui a1,0x10 614 | 10682: 41a58593 add a1,a1,1050 # 1041a <__fp_lock> 615 | 10686: aeb9 j 109e4 <_fwalk> 616 | 617 | 00010688 <__fp_unlock_all>: 618 | 10688: 0381a503 lw a0,56(gp) # 13cd8 <_impure_ptr> 619 | 1068c: 65c1 lui a1,0x10 620 | 1068e: 42658593 add a1,a1,1062 # 10426 <__fp_unlock> 621 | 10692: ae89 j 109e4 <_fwalk> 622 | 623 | 00010694 <__libc_fini_array>: 624 | 10694: 1141 add sp,sp,-16 625 | 10696: c422 sw s0,8(sp) 626 | 10698: 67cd lui a5,0x13 627 | 1069a: 644d lui s0,0x13 628 | 1069c: 49878793 add a5,a5,1176 # 13498 <__do_global_dtors_aux_fini_array_entry> 629 | 106a0: 49c40413 add s0,s0,1180 # 1349c <__fini_array_end> 630 | 106a4: 8c1d sub s0,s0,a5 631 | 106a6: c226 sw s1,4(sp) 632 | 106a8: c606 sw ra,12(sp) 633 | 106aa: 40245493 sra s1,s0,0x2 634 | 106ae: c881 beqz s1,106be <__libc_fini_array+0x2a> 635 | 106b0: 1471 add s0,s0,-4 636 | 106b2: 943e add s0,s0,a5 637 | 106b4: 401c lw a5,0(s0) 638 | 106b6: 14fd add s1,s1,-1 639 | 106b8: 1471 add s0,s0,-4 640 | 106ba: 9782 jalr a5 641 | 106bc: fce5 bnez s1,106b4 <__libc_fini_array+0x20> 642 | 106be: 40b2 lw ra,12(sp) 643 | 106c0: 4422 lw s0,8(sp) 644 | 106c2: 4492 lw s1,4(sp) 645 | 106c4: 0141 add sp,sp,16 646 | 106c6: 8082 ret 647 | 648 | 000106c8 <__sfvwrite_r>: 649 | 106c8: 461c lw a5,8(a2) 650 | 106ca: 20078f63 beqz a5,108e8 <__sfvwrite_r+0x220> 651 | 106ce: 00c59683 lh a3,12(a1) 652 | 106d2: 7179 add sp,sp,-48 653 | 106d4: d422 sw s0,40(sp) 654 | 106d6: cc52 sw s4,24(sp) 655 | 106d8: c85a sw s6,16(sp) 656 | 106da: d606 sw ra,44(sp) 657 | 106dc: d226 sw s1,36(sp) 658 | 106de: d04a sw s2,32(sp) 659 | 106e0: ce4e sw s3,28(sp) 660 | 106e2: ca56 sw s5,20(sp) 661 | 106e4: c65e sw s7,12(sp) 662 | 106e6: c462 sw s8,8(sp) 663 | 106e8: c266 sw s9,4(sp) 664 | 106ea: 0086f793 and a5,a3,8 665 | 106ee: 8b32 mv s6,a2 666 | 106f0: 8a2a mv s4,a0 667 | 106f2: 842e mv s0,a1 668 | 106f4: c3ad beqz a5,10756 <__sfvwrite_r+0x8e> 669 | 106f6: 499c lw a5,16(a1) 670 | 106f8: cfb9 beqz a5,10756 <__sfvwrite_r+0x8e> 671 | 106fa: 0026f793 and a5,a3,2 672 | 106fe: 000b2483 lw s1,0(s6) 673 | 10702: c7bd beqz a5,10770 <__sfvwrite_r+0xa8> 674 | 10704: 505c lw a5,36(s0) 675 | 10706: 4c4c lw a1,28(s0) 676 | 10708: 80000ab7 lui s5,0x80000 677 | 1070c: 4981 li s3,0 678 | 1070e: 4901 li s2,0 679 | 10710: c00aca93 xor s5,s5,-1024 680 | 10714: 864e mv a2,s3 681 | 10716: 8552 mv a0,s4 682 | 10718: 02090963 beqz s2,1074a <__sfvwrite_r+0x82> 683 | 1071c: 86ca mv a3,s2 684 | 1071e: 012af363 bgeu s5,s2,10724 <__sfvwrite_r+0x5c> 685 | 10722: 86d6 mv a3,s5 686 | 10724: 9782 jalr a5 687 | 10726: 1aa05963 blez a0,108d8 <__sfvwrite_r+0x210> 688 | 1072a: 008b2783 lw a5,8(s6) 689 | 1072e: 99aa add s3,s3,a0 690 | 10730: 40a90933 sub s2,s2,a0 691 | 10734: 8f89 sub a5,a5,a0 692 | 10736: 00fb2423 sw a5,8(s6) 693 | 1073a: 16078c63 beqz a5,108b2 <__sfvwrite_r+0x1ea> 694 | 1073e: 505c lw a5,36(s0) 695 | 10740: 4c4c lw a1,28(s0) 696 | 10742: 864e mv a2,s3 697 | 10744: 8552 mv a0,s4 698 | 10746: fc091be3 bnez s2,1071c <__sfvwrite_r+0x54> 699 | 1074a: 0004a983 lw s3,0(s1) 700 | 1074e: 0044a903 lw s2,4(s1) 701 | 10752: 04a1 add s1,s1,8 702 | 10754: b7c1 j 10714 <__sfvwrite_r+0x4c> 703 | 10756: 85a2 mv a1,s0 704 | 10758: 8552 mv a0,s4 705 | 1075a: 0a2010ef jal 117fc <__swsetup_r> 706 | 1075e: 18051363 bnez a0,108e4 <__sfvwrite_r+0x21c> 707 | 10762: 00c41683 lh a3,12(s0) 708 | 10766: 000b2483 lw s1,0(s6) 709 | 1076a: 0026f793 and a5,a3,2 710 | 1076e: fbd9 bnez a5,10704 <__sfvwrite_r+0x3c> 711 | 10770: 0016f793 and a5,a3,1 712 | 10774: e3e5 bnez a5,10854 <__sfvwrite_r+0x18c> 713 | 10776: 401c lw a5,0(s0) 714 | 10778: 4418 lw a4,8(s0) 715 | 1077a: 80000ab7 lui s5,0x80000 716 | 1077e: 4b81 li s7,0 717 | 10780: 4981 li s3,0 718 | 10782: fffaca93 not s5,s5 719 | 10786: 853e mv a0,a5 720 | 10788: 8c3a mv s8,a4 721 | 1078a: 0a098f63 beqz s3,10848 <__sfvwrite_r+0x180> 722 | 1078e: 2006f613 and a2,a3,512 723 | 10792: 18060b63 beqz a2,10928 <__sfvwrite_r+0x260> 724 | 10796: 8cba mv s9,a4 725 | 10798: 1ee9ea63 bltu s3,a4,1098c <__sfvwrite_r+0x2c4> 726 | 1079c: 4806f713 and a4,a3,1152 727 | 107a0: c73d beqz a4,1080e <__sfvwrite_r+0x146> 728 | 107a2: 4850 lw a2,20(s0) 729 | 107a4: 480c lw a1,16(s0) 730 | 107a6: 00161713 sll a4,a2,0x1 731 | 107aa: 9732 add a4,a4,a2 732 | 107ac: 40b78933 sub s2,a5,a1 733 | 107b0: 01f75c13 srl s8,a4,0x1f 734 | 107b4: 9c3a add s8,s8,a4 735 | 107b6: 00190793 add a5,s2,1 736 | 107ba: 401c5c13 sra s8,s8,0x1 737 | 107be: 97ce add a5,a5,s3 738 | 107c0: 8662 mv a2,s8 739 | 107c2: 00fc7463 bgeu s8,a5,107ca <__sfvwrite_r+0x102> 740 | 107c6: 8c3e mv s8,a5 741 | 107c8: 863e mv a2,a5 742 | 107ca: 4006f693 and a3,a3,1024 743 | 107ce: 1c068f63 beqz a3,109ac <__sfvwrite_r+0x2e4> 744 | 107d2: 85b2 mv a1,a2 745 | 107d4: 8552 mv a0,s4 746 | 107d6: 24fd jal 10ac4 <_malloc_r> 747 | 107d8: 8caa mv s9,a0 748 | 107da: 1e050f63 beqz a0,109d8 <__sfvwrite_r+0x310> 749 | 107de: 480c lw a1,16(s0) 750 | 107e0: 864a mv a2,s2 751 | 107e2: 0f5000ef jal 110d6 752 | 107e6: 00c45783 lhu a5,12(s0) 753 | 107ea: b7f7f793 and a5,a5,-1153 754 | 107ee: 0807e793 or a5,a5,128 755 | 107f2: 00f41623 sh a5,12(s0) 756 | 107f6: 012c8533 add a0,s9,s2 757 | 107fa: 412c07b3 sub a5,s8,s2 758 | 107fe: 01942823 sw s9,16(s0) 759 | 10802: 01842a23 sw s8,20(s0) 760 | 10806: c008 sw a0,0(s0) 761 | 10808: 8c4e mv s8,s3 762 | 1080a: c41c sw a5,8(s0) 763 | 1080c: 8cce mv s9,s3 764 | 1080e: 8666 mv a2,s9 765 | 10810: 85de mv a1,s7 766 | 10812: 20b000ef jal 1121c 767 | 10816: 4418 lw a4,8(s0) 768 | 10818: 401c lw a5,0(s0) 769 | 1081a: 894e mv s2,s3 770 | 1081c: 41870733 sub a4,a4,s8 771 | 10820: 97e6 add a5,a5,s9 772 | 10822: c418 sw a4,8(s0) 773 | 10824: c01c sw a5,0(s0) 774 | 10826: 4981 li s3,0 775 | 10828: 008b2783 lw a5,8(s6) 776 | 1082c: 9bca add s7,s7,s2 777 | 1082e: 412787b3 sub a5,a5,s2 778 | 10832: 00fb2423 sw a5,8(s6) 779 | 10836: cfb5 beqz a5,108b2 <__sfvwrite_r+0x1ea> 780 | 10838: 401c lw a5,0(s0) 781 | 1083a: 4418 lw a4,8(s0) 782 | 1083c: 00c41683 lh a3,12(s0) 783 | 10840: 853e mv a0,a5 784 | 10842: 8c3a mv s8,a4 785 | 10844: f40995e3 bnez s3,1078e <__sfvwrite_r+0xc6> 786 | 10848: 0004ab83 lw s7,0(s1) 787 | 1084c: 0044a983 lw s3,4(s1) 788 | 10850: 04a1 add s1,s1,8 789 | 10852: bf15 j 10786 <__sfvwrite_r+0xbe> 790 | 10854: 4a81 li s5,0 791 | 10856: 4501 li a0,0 792 | 10858: 4c01 li s8,0 793 | 1085a: 4981 li s3,0 794 | 1085c: 08098863 beqz s3,108ec <__sfvwrite_r+0x224> 795 | 10860: cd51 beqz a0,108fc <__sfvwrite_r+0x234> 796 | 10862: 87d6 mv a5,s5 797 | 10864: 8bce mv s7,s3 798 | 10866: 0137f363 bgeu a5,s3,1086c <__sfvwrite_r+0x1a4> 799 | 1086a: 8bbe mv s7,a5 800 | 1086c: 4008 lw a0,0(s0) 801 | 1086e: 481c lw a5,16(s0) 802 | 10870: 00842903 lw s2,8(s0) 803 | 10874: 4854 lw a3,20(s0) 804 | 10876: 00a7f563 bgeu a5,a0,10880 <__sfvwrite_r+0x1b8> 805 | 1087a: 9936 add s2,s2,a3 806 | 1087c: 09794963 blt s2,s7,1090e <__sfvwrite_r+0x246> 807 | 10880: 10dbc963 blt s7,a3,10992 <__sfvwrite_r+0x2ca> 808 | 10884: 505c lw a5,36(s0) 809 | 10886: 4c4c lw a1,28(s0) 810 | 10888: 8662 mv a2,s8 811 | 1088a: 8552 mv a0,s4 812 | 1088c: 9782 jalr a5 813 | 1088e: 892a mv s2,a0 814 | 10890: 04a05463 blez a0,108d8 <__sfvwrite_r+0x210> 815 | 10894: 412a8ab3 sub s5,s5,s2 816 | 10898: 4505 li a0,1 817 | 1089a: 020a8a63 beqz s5,108ce <__sfvwrite_r+0x206> 818 | 1089e: 008b2783 lw a5,8(s6) 819 | 108a2: 9c4a add s8,s8,s2 820 | 108a4: 412989b3 sub s3,s3,s2 821 | 108a8: 412787b3 sub a5,a5,s2 822 | 108ac: 00fb2423 sw a5,8(s6) 823 | 108b0: f7d5 bnez a5,1085c <__sfvwrite_r+0x194> 824 | 108b2: 4501 li a0,0 825 | 108b4: 50b2 lw ra,44(sp) 826 | 108b6: 5422 lw s0,40(sp) 827 | 108b8: 5492 lw s1,36(sp) 828 | 108ba: 5902 lw s2,32(sp) 829 | 108bc: 49f2 lw s3,28(sp) 830 | 108be: 4a62 lw s4,24(sp) 831 | 108c0: 4ad2 lw s5,20(sp) 832 | 108c2: 4b42 lw s6,16(sp) 833 | 108c4: 4bb2 lw s7,12(sp) 834 | 108c6: 4c22 lw s8,8(sp) 835 | 108c8: 4c92 lw s9,4(sp) 836 | 108ca: 6145 add sp,sp,48 837 | 108cc: 8082 ret 838 | 108ce: 85a2 mv a1,s0 839 | 108d0: 8552 mv a0,s4 840 | 108d2: 2d2010ef jal 11ba4 <_fflush_r> 841 | 108d6: d561 beqz a0,1089e <__sfvwrite_r+0x1d6> 842 | 108d8: 00c41783 lh a5,12(s0) 843 | 108dc: 0407e793 or a5,a5,64 844 | 108e0: 00f41623 sh a5,12(s0) 845 | 108e4: 557d li a0,-1 846 | 108e6: b7f9 j 108b4 <__sfvwrite_r+0x1ec> 847 | 108e8: 4501 li a0,0 848 | 108ea: 8082 ret 849 | 108ec: 0044a983 lw s3,4(s1) 850 | 108f0: 87a6 mv a5,s1 851 | 108f2: 04a1 add s1,s1,8 852 | 108f4: fe098ce3 beqz s3,108ec <__sfvwrite_r+0x224> 853 | 108f8: 0007ac03 lw s8,0(a5) 854 | 108fc: 864e mv a2,s3 855 | 108fe: 45a9 li a1,10 856 | 10900: 8562 mv a0,s8 857 | 10902: 2791 jal 11046 858 | 10904: c571 beqz a0,109d0 <__sfvwrite_r+0x308> 859 | 10906: 0505 add a0,a0,1 860 | 10908: 41850ab3 sub s5,a0,s8 861 | 1090c: bf99 j 10862 <__sfvwrite_r+0x19a> 862 | 1090e: 85e2 mv a1,s8 863 | 10910: 864a mv a2,s2 864 | 10912: 10b000ef jal 1121c 865 | 10916: 401c lw a5,0(s0) 866 | 10918: 85a2 mv a1,s0 867 | 1091a: 8552 mv a0,s4 868 | 1091c: 97ca add a5,a5,s2 869 | 1091e: c01c sw a5,0(s0) 870 | 10920: 284010ef jal 11ba4 <_fflush_r> 871 | 10924: d925 beqz a0,10894 <__sfvwrite_r+0x1cc> 872 | 10926: bf4d j 108d8 <__sfvwrite_r+0x210> 873 | 10928: 4814 lw a3,16(s0) 874 | 1092a: 02f6e863 bltu a3,a5,1095a <__sfvwrite_r+0x292> 875 | 1092e: 4850 lw a2,20(s0) 876 | 10930: 02c9e563 bltu s3,a2,1095a <__sfvwrite_r+0x292> 877 | 10934: 87ce mv a5,s3 878 | 10936: 013af363 bgeu s5,s3,1093c <__sfvwrite_r+0x274> 879 | 1093a: 87d6 mv a5,s5 880 | 1093c: 02c7e6b3 rem a3,a5,a2 881 | 10940: 5058 lw a4,36(s0) 882 | 10942: 4c4c lw a1,28(s0) 883 | 10944: 865e mv a2,s7 884 | 10946: 8552 mv a0,s4 885 | 10948: 40d786b3 sub a3,a5,a3 886 | 1094c: 9702 jalr a4 887 | 1094e: 892a mv s2,a0 888 | 10950: f8a054e3 blez a0,108d8 <__sfvwrite_r+0x210> 889 | 10954: 412989b3 sub s3,s3,s2 890 | 10958: bdc1 j 10828 <__sfvwrite_r+0x160> 891 | 1095a: 893a mv s2,a4 892 | 1095c: 00e9f363 bgeu s3,a4,10962 <__sfvwrite_r+0x29a> 893 | 10960: 894e mv s2,s3 894 | 10962: 853e mv a0,a5 895 | 10964: 864a mv a2,s2 896 | 10966: 85de mv a1,s7 897 | 10968: 0b5000ef jal 1121c 898 | 1096c: 4418 lw a4,8(s0) 899 | 1096e: 401c lw a5,0(s0) 900 | 10970: 41270733 sub a4,a4,s2 901 | 10974: 97ca add a5,a5,s2 902 | 10976: c418 sw a4,8(s0) 903 | 10978: c01c sw a5,0(s0) 904 | 1097a: ff69 bnez a4,10954 <__sfvwrite_r+0x28c> 905 | 1097c: 85a2 mv a1,s0 906 | 1097e: 8552 mv a0,s4 907 | 10980: 224010ef jal 11ba4 <_fflush_r> 908 | 10984: f931 bnez a0,108d8 <__sfvwrite_r+0x210> 909 | 10986: 412989b3 sub s3,s3,s2 910 | 1098a: bd79 j 10828 <__sfvwrite_r+0x160> 911 | 1098c: 8c4e mv s8,s3 912 | 1098e: 8cce mv s9,s3 913 | 10990: bdbd j 1080e <__sfvwrite_r+0x146> 914 | 10992: 865e mv a2,s7 915 | 10994: 85e2 mv a1,s8 916 | 10996: 087000ef jal 1121c 917 | 1099a: 4418 lw a4,8(s0) 918 | 1099c: 401c lw a5,0(s0) 919 | 1099e: 895e mv s2,s7 920 | 109a0: 41770733 sub a4,a4,s7 921 | 109a4: 97de add a5,a5,s7 922 | 109a6: c418 sw a4,8(s0) 923 | 109a8: c01c sw a5,0(s0) 924 | 109aa: b5ed j 10894 <__sfvwrite_r+0x1cc> 925 | 109ac: 8552 mv a0,s4 926 | 109ae: 145000ef jal 112f2 <_realloc_r> 927 | 109b2: 8caa mv s9,a0 928 | 109b4: e40511e3 bnez a0,107f6 <__sfvwrite_r+0x12e> 929 | 109b8: 480c lw a1,16(s0) 930 | 109ba: 8552 mv a0,s4 931 | 109bc: 332010ef jal 11cee <_free_r> 932 | 109c0: 00c41783 lh a5,12(s0) 933 | 109c4: 4731 li a4,12 934 | 109c6: 00ea2023 sw a4,0(s4) 935 | 109ca: f7f7f793 and a5,a5,-129 936 | 109ce: b739 j 108dc <__sfvwrite_r+0x214> 937 | 109d0: 00198793 add a5,s3,1 938 | 109d4: 8abe mv s5,a5 939 | 109d6: b579 j 10864 <__sfvwrite_r+0x19c> 940 | 109d8: 4731 li a4,12 941 | 109da: 00c41783 lh a5,12(s0) 942 | 109de: 00ea2023 sw a4,0(s4) 943 | 109e2: bded j 108dc <__sfvwrite_r+0x214> 944 | 945 | 000109e4 <_fwalk>: 946 | 109e4: 1101 add sp,sp,-32 947 | 109e6: c84a sw s2,16(sp) 948 | 109e8: c64e sw s3,12(sp) 949 | 109ea: c452 sw s4,8(sp) 950 | 109ec: c256 sw s5,4(sp) 951 | 109ee: c05a sw s6,0(sp) 952 | 109f0: ce06 sw ra,28(sp) 953 | 109f2: cc22 sw s0,24(sp) 954 | 109f4: ca26 sw s1,20(sp) 955 | 109f6: 8b2e mv s6,a1 956 | 109f8: 2e050a93 add s5,a0,736 957 | 109fc: 4a01 li s4,0 958 | 109fe: 4985 li s3,1 959 | 10a00: 597d li s2,-1 960 | 10a02: 004aa483 lw s1,4(s5) # 80000004 <__BSS_END__+0x7ffec2c8> 961 | 10a06: 008aa403 lw s0,8(s5) 962 | 10a0a: 14fd add s1,s1,-1 963 | 10a0c: 0204c363 bltz s1,10a32 <_fwalk+0x4e> 964 | 10a10: 00c45783 lhu a5,12(s0) 965 | 10a14: 14fd add s1,s1,-1 966 | 10a16: 00f9fa63 bgeu s3,a5,10a2a <_fwalk+0x46> 967 | 10a1a: 00e41783 lh a5,14(s0) 968 | 10a1e: 8522 mv a0,s0 969 | 10a20: 01278563 beq a5,s2,10a2a <_fwalk+0x46> 970 | 10a24: 9b02 jalr s6 971 | 10a26: 00aa6a33 or s4,s4,a0 972 | 10a2a: 06840413 add s0,s0,104 973 | 10a2e: ff2491e3 bne s1,s2,10a10 <_fwalk+0x2c> 974 | 10a32: 000aaa83 lw s5,0(s5) 975 | 10a36: fc0a96e3 bnez s5,10a02 <_fwalk+0x1e> 976 | 10a3a: 40f2 lw ra,28(sp) 977 | 10a3c: 4462 lw s0,24(sp) 978 | 10a3e: 44d2 lw s1,20(sp) 979 | 10a40: 4942 lw s2,16(sp) 980 | 10a42: 49b2 lw s3,12(sp) 981 | 10a44: 4a92 lw s5,4(sp) 982 | 10a46: 4b02 lw s6,0(sp) 983 | 10a48: 8552 mv a0,s4 984 | 10a4a: 4a22 lw s4,8(sp) 985 | 10a4c: 6105 add sp,sp,32 986 | 10a4e: 8082 ret 987 | 988 | 00010a50 <_fwalk_reent>: 989 | 10a50: 7179 add sp,sp,-48 990 | 10a52: d04a sw s2,32(sp) 991 | 10a54: ce4e sw s3,28(sp) 992 | 10a56: cc52 sw s4,24(sp) 993 | 10a58: ca56 sw s5,20(sp) 994 | 10a5a: c85a sw s6,16(sp) 995 | 10a5c: c65e sw s7,12(sp) 996 | 10a5e: d606 sw ra,44(sp) 997 | 10a60: d422 sw s0,40(sp) 998 | 10a62: d226 sw s1,36(sp) 999 | 10a64: 8aaa mv s5,a0 1000 | 10a66: 8bae mv s7,a1 1001 | 10a68: 2e050b13 add s6,a0,736 1002 | 10a6c: 4a01 li s4,0 1003 | 10a6e: 4985 li s3,1 1004 | 10a70: 597d li s2,-1 1005 | 10a72: 004b2483 lw s1,4(s6) 1006 | 10a76: 008b2403 lw s0,8(s6) 1007 | 10a7a: 14fd add s1,s1,-1 1008 | 10a7c: 0204c463 bltz s1,10aa4 <_fwalk_reent+0x54> 1009 | 10a80: 00c45783 lhu a5,12(s0) 1010 | 10a84: 14fd add s1,s1,-1 1011 | 10a86: 00f9fb63 bgeu s3,a5,10a9c <_fwalk_reent+0x4c> 1012 | 10a8a: 00e41783 lh a5,14(s0) 1013 | 10a8e: 85a2 mv a1,s0 1014 | 10a90: 8556 mv a0,s5 1015 | 10a92: 01278563 beq a5,s2,10a9c <_fwalk_reent+0x4c> 1016 | 10a96: 9b82 jalr s7 1017 | 10a98: 00aa6a33 or s4,s4,a0 1018 | 10a9c: 06840413 add s0,s0,104 1019 | 10aa0: ff2490e3 bne s1,s2,10a80 <_fwalk_reent+0x30> 1020 | 10aa4: 000b2b03 lw s6,0(s6) 1021 | 10aa8: fc0b15e3 bnez s6,10a72 <_fwalk_reent+0x22> 1022 | 10aac: 50b2 lw ra,44(sp) 1023 | 10aae: 5422 lw s0,40(sp) 1024 | 10ab0: 5492 lw s1,36(sp) 1025 | 10ab2: 5902 lw s2,32(sp) 1026 | 10ab4: 49f2 lw s3,28(sp) 1027 | 10ab6: 4ad2 lw s5,20(sp) 1028 | 10ab8: 4b42 lw s6,16(sp) 1029 | 10aba: 4bb2 lw s7,12(sp) 1030 | 10abc: 8552 mv a0,s4 1031 | 10abe: 4a62 lw s4,24(sp) 1032 | 10ac0: 6145 add sp,sp,48 1033 | 10ac2: 8082 ret 1034 | 1035 | 00010ac4 <_malloc_r>: 1036 | 10ac4: 7179 add sp,sp,-48 1037 | 10ac6: ce4e sw s3,28(sp) 1038 | 10ac8: d606 sw ra,44(sp) 1039 | 10aca: d422 sw s0,40(sp) 1040 | 10acc: d226 sw s1,36(sp) 1041 | 10ace: d04a sw s2,32(sp) 1042 | 10ad0: cc52 sw s4,24(sp) 1043 | 10ad2: ca56 sw s5,20(sp) 1044 | 10ad4: c85a sw s6,16(sp) 1045 | 10ad6: c65e sw s7,12(sp) 1046 | 10ad8: c462 sw s8,8(sp) 1047 | 10ada: c266 sw s9,4(sp) 1048 | 10adc: 00b58793 add a5,a1,11 1049 | 10ae0: 4759 li a4,22 1050 | 10ae2: 89aa mv s3,a0 1051 | 10ae4: 04f76f63 bltu a4,a5,10b42 <_malloc_r+0x7e> 1052 | 10ae8: 47c1 li a5,16 1053 | 10aea: 16b7ec63 bltu a5,a1,10c62 <_malloc_r+0x19e> 1054 | 10aee: 001000ef jal 112ee <__malloc_lock> 1055 | 10af2: 44c1 li s1,16 1056 | 10af4: 47e1 li a5,24 1057 | 10af6: 4589 li a1,2 1058 | 10af8: c2818913 add s2,gp,-984 # 138c8 <__malloc_av_> 1059 | 10afc: 97ca add a5,a5,s2 1060 | 10afe: 43c0 lw s0,4(a5) 1061 | 10b00: ff878713 add a4,a5,-8 1062 | 10b04: 22e40963 beq s0,a4,10d36 <_malloc_r+0x272> 1063 | 10b08: 405c lw a5,4(s0) 1064 | 10b0a: 4454 lw a3,12(s0) 1065 | 10b0c: 4410 lw a2,8(s0) 1066 | 10b0e: 9bf1 and a5,a5,-4 1067 | 10b10: 97a2 add a5,a5,s0 1068 | 10b12: 43d8 lw a4,4(a5) 1069 | 10b14: c654 sw a3,12(a2) 1070 | 10b16: c690 sw a2,8(a3) 1071 | 10b18: 00176713 or a4,a4,1 1072 | 10b1c: 854e mv a0,s3 1073 | 10b1e: c3d8 sw a4,4(a5) 1074 | 10b20: 7d0000ef jal 112f0 <__malloc_unlock> 1075 | 10b24: 00840513 add a0,s0,8 1076 | 10b28: 50b2 lw ra,44(sp) 1077 | 10b2a: 5422 lw s0,40(sp) 1078 | 10b2c: 5492 lw s1,36(sp) 1079 | 10b2e: 5902 lw s2,32(sp) 1080 | 10b30: 49f2 lw s3,28(sp) 1081 | 10b32: 4a62 lw s4,24(sp) 1082 | 10b34: 4ad2 lw s5,20(sp) 1083 | 10b36: 4b42 lw s6,16(sp) 1084 | 10b38: 4bb2 lw s7,12(sp) 1085 | 10b3a: 4c22 lw s8,8(sp) 1086 | 10b3c: 4c92 lw s9,4(sp) 1087 | 10b3e: 6145 add sp,sp,48 1088 | 10b40: 8082 ret 1089 | 10b42: ff87f493 and s1,a5,-8 1090 | 10b46: 1007ce63 bltz a5,10c62 <_malloc_r+0x19e> 1091 | 10b4a: 10b4ec63 bltu s1,a1,10c62 <_malloc_r+0x19e> 1092 | 10b4e: 2745 jal 112ee <__malloc_lock> 1093 | 10b50: 1f700793 li a5,503 1094 | 10b54: 2a97f063 bgeu a5,s1,10df4 <_malloc_r+0x330> 1095 | 10b58: 0094d793 srl a5,s1,0x9 1096 | 10b5c: 10078863 beqz a5,10c6c <_malloc_r+0x1a8> 1097 | 10b60: 4711 li a4,4 1098 | 10b62: 20f76f63 bltu a4,a5,10d80 <_malloc_r+0x2bc> 1099 | 10b66: 0064d793 srl a5,s1,0x6 1100 | 10b6a: 03978593 add a1,a5,57 1101 | 10b6e: 03878513 add a0,a5,56 1102 | 10b72: 00359693 sll a3,a1,0x3 1103 | 10b76: c2818913 add s2,gp,-984 # 138c8 <__malloc_av_> 1104 | 10b7a: 96ca add a3,a3,s2 1105 | 10b7c: 42c0 lw s0,4(a3) 1106 | 10b7e: 16e1 add a3,a3,-8 1107 | 10b80: 02868063 beq a3,s0,10ba0 <_malloc_r+0xdc> 1108 | 10b84: 463d li a2,15 1109 | 10b86: a031 j 10b92 <_malloc_r+0xce> 1110 | 10b88: 1a075463 bgez a4,10d30 <_malloc_r+0x26c> 1111 | 10b8c: 4440 lw s0,12(s0) 1112 | 10b8e: 00868963 beq a3,s0,10ba0 <_malloc_r+0xdc> 1113 | 10b92: 405c lw a5,4(s0) 1114 | 10b94: 9bf1 and a5,a5,-4 1115 | 10b96: 40978733 sub a4,a5,s1 1116 | 10b9a: fee657e3 bge a2,a4,10b88 <_malloc_r+0xc4> 1117 | 10b9e: 85aa mv a1,a0 1118 | 10ba0: 01092403 lw s0,16(s2) 1119 | 10ba4: c3018813 add a6,gp,-976 # 138d0 <__malloc_av_+0x8> 1120 | 10ba8: 17040363 beq s0,a6,10d0e <_malloc_r+0x24a> 1121 | 10bac: 405c lw a5,4(s0) 1122 | 10bae: 46bd li a3,15 1123 | 10bb0: 9bf1 and a5,a5,-4 1124 | 10bb2: 40978733 sub a4,a5,s1 1125 | 10bb6: 24e6c463 blt a3,a4,10dfe <_malloc_r+0x33a> 1126 | 10bba: 01092a23 sw a6,20(s2) 1127 | 10bbe: 01092823 sw a6,16(s2) 1128 | 10bc2: 20075f63 bgez a4,10de0 <_malloc_r+0x31c> 1129 | 10bc6: 1ff00713 li a4,511 1130 | 10bca: 00492503 lw a0,4(s2) 1131 | 10bce: 16f76963 bltu a4,a5,10d40 <_malloc_r+0x27c> 1132 | 10bd2: ff87f713 and a4,a5,-8 1133 | 10bd6: 0721 add a4,a4,8 1134 | 10bd8: 974a add a4,a4,s2 1135 | 10bda: 4314 lw a3,0(a4) 1136 | 10bdc: 0057d613 srl a2,a5,0x5 1137 | 10be0: 4785 li a5,1 1138 | 10be2: 00c797b3 sll a5,a5,a2 1139 | 10be6: 8d5d or a0,a0,a5 1140 | 10be8: ff870793 add a5,a4,-8 1141 | 10bec: c45c sw a5,12(s0) 1142 | 10bee: c414 sw a3,8(s0) 1143 | 10bf0: 00a92223 sw a0,4(s2) 1144 | 10bf4: c300 sw s0,0(a4) 1145 | 10bf6: c6c0 sw s0,12(a3) 1146 | 10bf8: 4025d793 sra a5,a1,0x2 1147 | 10bfc: 4605 li a2,1 1148 | 10bfe: 00f61633 sll a2,a2,a5 1149 | 10c02: 06c56c63 bltu a0,a2,10c7a <_malloc_r+0x1b6> 1150 | 10c06: 00a677b3 and a5,a2,a0 1151 | 10c0a: ef81 bnez a5,10c22 <_malloc_r+0x15e> 1152 | 10c0c: 0606 sll a2,a2,0x1 1153 | 10c0e: 99f1 and a1,a1,-4 1154 | 10c10: 00a677b3 and a5,a2,a0 1155 | 10c14: 0591 add a1,a1,4 1156 | 10c16: e791 bnez a5,10c22 <_malloc_r+0x15e> 1157 | 10c18: 0606 sll a2,a2,0x1 1158 | 10c1a: 00a677b3 and a5,a2,a0 1159 | 10c1e: 0591 add a1,a1,4 1160 | 10c20: dfe5 beqz a5,10c18 <_malloc_r+0x154> 1161 | 10c22: 48bd li a7,15 1162 | 10c24: 00359313 sll t1,a1,0x3 1163 | 10c28: 934a add t1,t1,s2 1164 | 10c2a: 851a mv a0,t1 1165 | 10c2c: 455c lw a5,12(a0) 1166 | 10c2e: 8e2e mv t3,a1 1167 | 10c30: 16f50863 beq a0,a5,10da0 <_malloc_r+0x2dc> 1168 | 10c34: 43d8 lw a4,4(a5) 1169 | 10c36: 843e mv s0,a5 1170 | 10c38: 47dc lw a5,12(a5) 1171 | 10c3a: 9b71 and a4,a4,-4 1172 | 10c3c: 409706b3 sub a3,a4,s1 1173 | 10c40: 16d8c763 blt a7,a3,10dae <_malloc_r+0x2ea> 1174 | 10c44: fe06c6e3 bltz a3,10c30 <_malloc_r+0x16c> 1175 | 10c48: 9722 add a4,a4,s0 1176 | 10c4a: 4354 lw a3,4(a4) 1177 | 10c4c: 4410 lw a2,8(s0) 1178 | 10c4e: 854e mv a0,s3 1179 | 10c50: 0016e693 or a3,a3,1 1180 | 10c54: c354 sw a3,4(a4) 1181 | 10c56: c65c sw a5,12(a2) 1182 | 10c58: c790 sw a2,8(a5) 1183 | 10c5a: 2d59 jal 112f0 <__malloc_unlock> 1184 | 10c5c: 00840513 add a0,s0,8 1185 | 10c60: b5e1 j 10b28 <_malloc_r+0x64> 1186 | 10c62: 47b1 li a5,12 1187 | 10c64: 00f9a023 sw a5,0(s3) 1188 | 10c68: 4501 li a0,0 1189 | 10c6a: bd7d j 10b28 <_malloc_r+0x64> 1190 | 10c6c: 20000693 li a3,512 1191 | 10c70: 04000593 li a1,64 1192 | 10c74: 03f00513 li a0,63 1193 | 10c78: bdfd j 10b76 <_malloc_r+0xb2> 1194 | 10c7a: 00892403 lw s0,8(s2) 1195 | 10c7e: 405c lw a5,4(s0) 1196 | 10c80: ffc7fb13 and s6,a5,-4 1197 | 10c84: 009b6763 bltu s6,s1,10c92 <_malloc_r+0x1ce> 1198 | 10c88: 409b0733 sub a4,s6,s1 1199 | 10c8c: 47bd li a5,15 1200 | 10c8e: 08e7c363 blt a5,a4,10d14 <_malloc_r+0x250> 1201 | 10c92: 04c1aa83 lw s5,76(gp) # 13cec <__malloc_top_pad> 1202 | 10c96: 03c1a703 lw a4,60(gp) # 13cdc <__malloc_sbrk_base> 1203 | 10c9a: 57fd li a5,-1 1204 | 10c9c: 01640a33 add s4,s0,s6 1205 | 10ca0: 9aa6 add s5,s5,s1 1206 | 10ca2: 2af70f63 beq a4,a5,10f60 <_malloc_r+0x49c> 1207 | 10ca6: 6785 lui a5,0x1 1208 | 10ca8: 07bd add a5,a5,15 # 100f 1209 | 10caa: 9abe add s5,s5,a5 1210 | 10cac: 77fd lui a5,0xfffff 1211 | 10cae: 00fafab3 and s5,s5,a5 1212 | 10cb2: 85d6 mv a1,s5 1213 | 10cb4: 854e mv a0,s3 1214 | 10cb6: 1f7000ef jal 116ac <_sbrk_r> 1215 | 10cba: 57fd li a5,-1 1216 | 10cbc: 8baa mv s7,a0 1217 | 10cbe: 18f50063 beq a0,a5,10e3e <_malloc_r+0x37a> 1218 | 10cc2: 17456c63 bltu a0,s4,10e3a <_malloc_r+0x376> 1219 | 10cc6: 07418c13 add s8,gp,116 # 13d14 <__malloc_current_mallinfo> 1220 | 10cca: 000c2583 lw a1,0(s8) 1221 | 10cce: 95d6 add a1,a1,s5 1222 | 10cd0: 00bc2023 sw a1,0(s8) 1223 | 10cd4: 872e mv a4,a1 1224 | 10cd6: 1eaa1063 bne s4,a0,10eb6 <_malloc_r+0x3f2> 1225 | 10cda: 01451793 sll a5,a0,0x14 1226 | 10cde: 1c079c63 bnez a5,10eb6 <_malloc_r+0x3f2> 1227 | 10ce2: 00892b83 lw s7,8(s2) 1228 | 10ce6: 015b07b3 add a5,s6,s5 1229 | 10cea: 0017e793 or a5,a5,1 1230 | 10cee: 00fba223 sw a5,4(s7) 1231 | 10cf2: 0481a683 lw a3,72(gp) # 13ce8 <__malloc_max_sbrked_mem> 1232 | 10cf6: 00b6f463 bgeu a3,a1,10cfe <_malloc_r+0x23a> 1233 | 10cfa: 04b1a423 sw a1,72(gp) # 13ce8 <__malloc_max_sbrked_mem> 1234 | 10cfe: 0441a683 lw a3,68(gp) # 13ce4 <__malloc_max_total_mem> 1235 | 10d02: 00b6f463 bgeu a3,a1,10d0a <_malloc_r+0x246> 1236 | 10d06: 04b1a223 sw a1,68(gp) # 13ce4 <__malloc_max_total_mem> 1237 | 10d0a: 845e mv s0,s7 1238 | 10d0c: aa25 j 10e44 <_malloc_r+0x380> 1239 | 10d0e: 00492503 lw a0,4(s2) 1240 | 10d12: b5dd j 10bf8 <_malloc_r+0x134> 1241 | 10d14: 0014e793 or a5,s1,1 1242 | 10d18: c05c sw a5,4(s0) 1243 | 10d1a: 94a2 add s1,s1,s0 1244 | 10d1c: 00992423 sw s1,8(s2) 1245 | 10d20: 00176713 or a4,a4,1 1246 | 10d24: 854e mv a0,s3 1247 | 10d26: c0d8 sw a4,4(s1) 1248 | 10d28: 23e1 jal 112f0 <__malloc_unlock> 1249 | 10d2a: 00840513 add a0,s0,8 1250 | 10d2e: bbed j 10b28 <_malloc_r+0x64> 1251 | 10d30: 4454 lw a3,12(s0) 1252 | 10d32: 4410 lw a2,8(s0) 1253 | 10d34: bbf1 j 10b10 <_malloc_r+0x4c> 1254 | 10d36: 47c0 lw s0,12(a5) 1255 | 10d38: 0589 add a1,a1,2 1256 | 10d3a: e68783e3 beq a5,s0,10ba0 <_malloc_r+0xdc> 1257 | 10d3e: b3e9 j 10b08 <_malloc_r+0x44> 1258 | 10d40: 0097d713 srl a4,a5,0x9 1259 | 10d44: 4691 li a3,4 1260 | 10d46: 0ee6f263 bgeu a3,a4,10e2a <_malloc_r+0x366> 1261 | 10d4a: 46d1 li a3,20 1262 | 10d4c: 24e6e363 bltu a3,a4,10f92 <_malloc_r+0x4ce> 1263 | 10d50: 05c70613 add a2,a4,92 1264 | 10d54: 05b70693 add a3,a4,91 1265 | 10d58: 060e sll a2,a2,0x3 1266 | 10d5a: 964a add a2,a2,s2 1267 | 10d5c: 4218 lw a4,0(a2) 1268 | 10d5e: 1661 add a2,a2,-8 1269 | 10d60: 00e61663 bne a2,a4,10d6c <_malloc_r+0x2a8> 1270 | 10d64: a401 j 10f64 <_malloc_r+0x4a0> 1271 | 10d66: 4718 lw a4,8(a4) 1272 | 10d68: 00e60663 beq a2,a4,10d74 <_malloc_r+0x2b0> 1273 | 10d6c: 4354 lw a3,4(a4) 1274 | 10d6e: 9af1 and a3,a3,-4 1275 | 10d70: fed7ebe3 bltu a5,a3,10d66 <_malloc_r+0x2a2> 1276 | 10d74: 4750 lw a2,12(a4) 1277 | 10d76: c450 sw a2,12(s0) 1278 | 10d78: c418 sw a4,8(s0) 1279 | 10d7a: c600 sw s0,8(a2) 1280 | 10d7c: c740 sw s0,12(a4) 1281 | 10d7e: bdad j 10bf8 <_malloc_r+0x134> 1282 | 10d80: 4751 li a4,20 1283 | 10d82: 0cf77d63 bgeu a4,a5,10e5c <_malloc_r+0x398> 1284 | 10d86: 05400713 li a4,84 1285 | 10d8a: 22f76063 bltu a4,a5,10faa <_malloc_r+0x4e6> 1286 | 10d8e: 00c4d793 srl a5,s1,0xc 1287 | 10d92: 06f78593 add a1,a5,111 # fffff06f <__BSS_END__+0xfffeb333> 1288 | 10d96: 06e78513 add a0,a5,110 1289 | 10d9a: 00359693 sll a3,a1,0x3 1290 | 10d9e: bbe1 j 10b76 <_malloc_r+0xb2> 1291 | 10da0: 0e05 add t3,t3,1 1292 | 10da2: 003e7793 and a5,t3,3 1293 | 10da6: 0521 add a0,a0,8 1294 | 10da8: c7f1 beqz a5,10e74 <_malloc_r+0x3b0> 1295 | 10daa: 455c lw a5,12(a0) 1296 | 10dac: b551 j 10c30 <_malloc_r+0x16c> 1297 | 10dae: 4410 lw a2,8(s0) 1298 | 10db0: 0014e593 or a1,s1,1 1299 | 10db4: c04c sw a1,4(s0) 1300 | 10db6: c65c sw a5,12(a2) 1301 | 10db8: c790 sw a2,8(a5) 1302 | 10dba: 94a2 add s1,s1,s0 1303 | 10dbc: 00992a23 sw s1,20(s2) 1304 | 10dc0: 00992823 sw s1,16(s2) 1305 | 10dc4: 0016e793 or a5,a3,1 1306 | 10dc8: 0104a623 sw a6,12(s1) 1307 | 10dcc: 0104a423 sw a6,8(s1) 1308 | 10dd0: c0dc sw a5,4(s1) 1309 | 10dd2: 9722 add a4,a4,s0 1310 | 10dd4: 854e mv a0,s3 1311 | 10dd6: c314 sw a3,0(a4) 1312 | 10dd8: 2b21 jal 112f0 <__malloc_unlock> 1313 | 10dda: 00840513 add a0,s0,8 1314 | 10dde: b3a9 j 10b28 <_malloc_r+0x64> 1315 | 10de0: 97a2 add a5,a5,s0 1316 | 10de2: 43d8 lw a4,4(a5) 1317 | 10de4: 854e mv a0,s3 1318 | 10de6: 00176713 or a4,a4,1 1319 | 10dea: c3d8 sw a4,4(a5) 1320 | 10dec: 2311 jal 112f0 <__malloc_unlock> 1321 | 10dee: 00840513 add a0,s0,8 1322 | 10df2: bb1d j 10b28 <_malloc_r+0x64> 1323 | 10df4: 0034d593 srl a1,s1,0x3 1324 | 10df8: 00848793 add a5,s1,8 1325 | 10dfc: b9f5 j 10af8 <_malloc_r+0x34> 1326 | 10dfe: 0014e693 or a3,s1,1 1327 | 10e02: c054 sw a3,4(s0) 1328 | 10e04: 94a2 add s1,s1,s0 1329 | 10e06: 00992a23 sw s1,20(s2) 1330 | 10e0a: 00992823 sw s1,16(s2) 1331 | 10e0e: 00176693 or a3,a4,1 1332 | 10e12: 0104a623 sw a6,12(s1) 1333 | 10e16: 0104a423 sw a6,8(s1) 1334 | 10e1a: c0d4 sw a3,4(s1) 1335 | 10e1c: 97a2 add a5,a5,s0 1336 | 10e1e: 854e mv a0,s3 1337 | 10e20: c398 sw a4,0(a5) 1338 | 10e22: 21f9 jal 112f0 <__malloc_unlock> 1339 | 10e24: 00840513 add a0,s0,8 1340 | 10e28: b301 j 10b28 <_malloc_r+0x64> 1341 | 10e2a: 0067d713 srl a4,a5,0x6 1342 | 10e2e: 03970613 add a2,a4,57 1343 | 10e32: 03870693 add a3,a4,56 1344 | 10e36: 060e sll a2,a2,0x3 1345 | 10e38: b70d j 10d5a <_malloc_r+0x296> 1346 | 10e3a: 07240763 beq s0,s2,10ea8 <_malloc_r+0x3e4> 1347 | 10e3e: 00892403 lw s0,8(s2) 1348 | 10e42: 405c lw a5,4(s0) 1349 | 10e44: 9bf1 and a5,a5,-4 1350 | 10e46: 40978733 sub a4,a5,s1 1351 | 10e4a: 0097e563 bltu a5,s1,10e54 <_malloc_r+0x390> 1352 | 10e4e: 47bd li a5,15 1353 | 10e50: ece7c2e3 blt a5,a4,10d14 <_malloc_r+0x250> 1354 | 10e54: 854e mv a0,s3 1355 | 10e56: 2969 jal 112f0 <__malloc_unlock> 1356 | 10e58: 4501 li a0,0 1357 | 10e5a: b1f9 j 10b28 <_malloc_r+0x64> 1358 | 10e5c: 05c78593 add a1,a5,92 1359 | 10e60: 05b78513 add a0,a5,91 1360 | 10e64: 00359693 sll a3,a1,0x3 1361 | 10e68: b339 j 10b76 <_malloc_r+0xb2> 1362 | 10e6a: 00832783 lw a5,8(t1) # 1013c 1363 | 10e6e: 15fd add a1,a1,-1 1364 | 10e70: 1c679863 bne a5,t1,11040 <_malloc_r+0x57c> 1365 | 10e74: 0035f793 and a5,a1,3 1366 | 10e78: 1361 add t1,t1,-8 1367 | 10e7a: fbe5 bnez a5,10e6a <_malloc_r+0x3a6> 1368 | 10e7c: 00492703 lw a4,4(s2) 1369 | 10e80: fff64793 not a5,a2 1370 | 10e84: 8ff9 and a5,a5,a4 1371 | 10e86: 00f92223 sw a5,4(s2) 1372 | 10e8a: 0606 sll a2,a2,0x1 1373 | 10e8c: dec7e7e3 bltu a5,a2,10c7a <_malloc_r+0x1b6> 1374 | 10e90: de0605e3 beqz a2,10c7a <_malloc_r+0x1b6> 1375 | 10e94: 00f67733 and a4,a2,a5 1376 | 10e98: e711 bnez a4,10ea4 <_malloc_r+0x3e0> 1377 | 10e9a: 0606 sll a2,a2,0x1 1378 | 10e9c: 00f67733 and a4,a2,a5 1379 | 10ea0: 0e11 add t3,t3,4 1380 | 10ea2: df65 beqz a4,10e9a <_malloc_r+0x3d6> 1381 | 10ea4: 85f2 mv a1,t3 1382 | 10ea6: bbbd j 10c24 <_malloc_r+0x160> 1383 | 10ea8: 07418c13 add s8,gp,116 # 13d14 <__malloc_current_mallinfo> 1384 | 10eac: 000c2703 lw a4,0(s8) 1385 | 10eb0: 9756 add a4,a4,s5 1386 | 10eb2: 00ec2023 sw a4,0(s8) 1387 | 10eb6: 03c1a683 lw a3,60(gp) # 13cdc <__malloc_sbrk_base> 1388 | 10eba: 57fd li a5,-1 1389 | 10ebc: 10f68463 beq a3,a5,10fc4 <_malloc_r+0x500> 1390 | 10ec0: 414b87b3 sub a5,s7,s4 1391 | 10ec4: 97ba add a5,a5,a4 1392 | 10ec6: 00fc2023 sw a5,0(s8) 1393 | 10eca: 007bfc93 and s9,s7,7 1394 | 10ece: 0a0c8363 beqz s9,10f74 <_malloc_r+0x4b0> 1395 | 10ed2: 6705 lui a4,0x1 1396 | 10ed4: 419b8bb3 sub s7,s7,s9 1397 | 10ed8: 00870593 add a1,a4,8 # 1008 1398 | 10edc: 0ba1 add s7,s7,8 1399 | 10ede: 419585b3 sub a1,a1,s9 1400 | 10ee2: 9ade add s5,s5,s7 1401 | 10ee4: 415585b3 sub a1,a1,s5 1402 | 10ee8: 177d add a4,a4,-1 1403 | 10eea: 00e5fa33 and s4,a1,a4 1404 | 10eee: 85d2 mv a1,s4 1405 | 10ef0: 854e mv a0,s3 1406 | 10ef2: 7ba000ef jal 116ac <_sbrk_r> 1407 | 10ef6: 57fd li a5,-1 1408 | 10ef8: 10f50663 beq a0,a5,11004 <_malloc_r+0x540> 1409 | 10efc: 41750533 sub a0,a0,s7 1410 | 10f00: 01450ab3 add s5,a0,s4 1411 | 10f04: 000c2703 lw a4,0(s8) 1412 | 10f08: 01792423 sw s7,8(s2) 1413 | 10f0c: 001ae793 or a5,s5,1 1414 | 10f10: 00ea05b3 add a1,s4,a4 1415 | 10f14: 00bc2023 sw a1,0(s8) 1416 | 10f18: 00fba223 sw a5,4(s7) 1417 | 10f1c: dd240be3 beq s0,s2,10cf2 <_malloc_r+0x22e> 1418 | 10f20: 46bd li a3,15 1419 | 10f22: 0b66f463 bgeu a3,s6,10fca <_malloc_r+0x506> 1420 | 10f26: 4058 lw a4,4(s0) 1421 | 10f28: ff4b0793 add a5,s6,-12 1422 | 10f2c: 9be1 and a5,a5,-8 1423 | 10f2e: 8b05 and a4,a4,1 1424 | 10f30: 8f5d or a4,a4,a5 1425 | 10f32: c058 sw a4,4(s0) 1426 | 10f34: 4615 li a2,5 1427 | 10f36: 00f40733 add a4,s0,a5 1428 | 10f3a: c350 sw a2,4(a4) 1429 | 10f3c: c710 sw a2,8(a4) 1430 | 10f3e: 00f6e563 bltu a3,a5,10f48 <_malloc_r+0x484> 1431 | 10f42: 004ba783 lw a5,4(s7) 1432 | 10f46: b375 j 10cf2 <_malloc_r+0x22e> 1433 | 10f48: 00840593 add a1,s0,8 1434 | 10f4c: 854e mv a0,s3 1435 | 10f4e: 5a1000ef jal 11cee <_free_r> 1436 | 10f52: 00892b83 lw s7,8(s2) 1437 | 10f56: 000c2583 lw a1,0(s8) 1438 | 10f5a: 004ba783 lw a5,4(s7) 1439 | 10f5e: bb51 j 10cf2 <_malloc_r+0x22e> 1440 | 10f60: 0ac1 add s5,s5,16 1441 | 10f62: bb81 j 10cb2 <_malloc_r+0x1ee> 1442 | 10f64: 8689 sra a3,a3,0x2 1443 | 10f66: 4785 li a5,1 1444 | 10f68: 00d797b3 sll a5,a5,a3 1445 | 10f6c: 8d5d or a0,a0,a5 1446 | 10f6e: 00a92223 sw a0,4(s2) 1447 | 10f72: b511 j 10d76 <_malloc_r+0x2b2> 1448 | 10f74: 015b85b3 add a1,s7,s5 1449 | 10f78: 40b005b3 neg a1,a1 1450 | 10f7c: 05d2 sll a1,a1,0x14 1451 | 10f7e: 0145da13 srl s4,a1,0x14 1452 | 10f82: 85d2 mv a1,s4 1453 | 10f84: 854e mv a0,s3 1454 | 10f86: 271d jal 116ac <_sbrk_r> 1455 | 10f88: 57fd li a5,-1 1456 | 10f8a: f6f519e3 bne a0,a5,10efc <_malloc_r+0x438> 1457 | 10f8e: 4a01 li s4,0 1458 | 10f90: bf95 j 10f04 <_malloc_r+0x440> 1459 | 10f92: 05400693 li a3,84 1460 | 10f96: 02e6ee63 bltu a3,a4,10fd2 <_malloc_r+0x50e> 1461 | 10f9a: 00c7d713 srl a4,a5,0xc 1462 | 10f9e: 06f70613 add a2,a4,111 1463 | 10fa2: 06e70693 add a3,a4,110 1464 | 10fa6: 060e sll a2,a2,0x3 1465 | 10fa8: bb4d j 10d5a <_malloc_r+0x296> 1466 | 10faa: 15400713 li a4,340 1467 | 10fae: 02f76e63 bltu a4,a5,10fea <_malloc_r+0x526> 1468 | 10fb2: 00f4d793 srl a5,s1,0xf 1469 | 10fb6: 07878593 add a1,a5,120 1470 | 10fba: 07778513 add a0,a5,119 1471 | 10fbe: 00359693 sll a3,a1,0x3 1472 | 10fc2: be55 j 10b76 <_malloc_r+0xb2> 1473 | 10fc4: 0371ae23 sw s7,60(gp) # 13cdc <__malloc_sbrk_base> 1474 | 10fc8: b709 j 10eca <_malloc_r+0x406> 1475 | 10fca: 4785 li a5,1 1476 | 10fcc: 00fba223 sw a5,4(s7) 1477 | 10fd0: b551 j 10e54 <_malloc_r+0x390> 1478 | 10fd2: 15400693 li a3,340 1479 | 10fd6: 02e6ed63 bltu a3,a4,11010 <_malloc_r+0x54c> 1480 | 10fda: 00f7d713 srl a4,a5,0xf 1481 | 10fde: 07870613 add a2,a4,120 1482 | 10fe2: 07770693 add a3,a4,119 1483 | 10fe6: 060e sll a2,a2,0x3 1484 | 10fe8: bb8d j 10d5a <_malloc_r+0x296> 1485 | 10fea: 55400713 li a4,1364 1486 | 10fee: 02f76d63 bltu a4,a5,11028 <_malloc_r+0x564> 1487 | 10ff2: 0124d793 srl a5,s1,0x12 1488 | 10ff6: 07d78593 add a1,a5,125 1489 | 10ffa: 07c78513 add a0,a5,124 1490 | 10ffe: 00359693 sll a3,a1,0x3 1491 | 11002: be95 j 10b76 <_malloc_r+0xb2> 1492 | 11004: 1ce1 add s9,s9,-8 1493 | 11006: 9ae6 add s5,s5,s9 1494 | 11008: 417a8ab3 sub s5,s5,s7 1495 | 1100c: 4a01 li s4,0 1496 | 1100e: bddd j 10f04 <_malloc_r+0x440> 1497 | 11010: 55400693 li a3,1364 1498 | 11014: 02e6e163 bltu a3,a4,11036 <_malloc_r+0x572> 1499 | 11018: 0127d713 srl a4,a5,0x12 1500 | 1101c: 07d70613 add a2,a4,125 1501 | 11020: 07c70693 add a3,a4,124 1502 | 11024: 060e sll a2,a2,0x3 1503 | 11026: bb15 j 10d5a <_malloc_r+0x296> 1504 | 11028: 3f800693 li a3,1016 1505 | 1102c: 07f00593 li a1,127 1506 | 11030: 07e00513 li a0,126 1507 | 11034: b689 j 10b76 <_malloc_r+0xb2> 1508 | 11036: 3f800613 li a2,1016 1509 | 1103a: 07e00693 li a3,126 1510 | 1103e: bb31 j 10d5a <_malloc_r+0x296> 1511 | 11040: 00492783 lw a5,4(s2) 1512 | 11044: b599 j 10e8a <_malloc_r+0x3c6> 1513 | 1514 | 00011046 : 1515 | 11046: 00357793 and a5,a0,3 1516 | 1104a: 0ff5f693 zext.b a3,a1 1517 | 1104e: c785 beqz a5,11076 1518 | 11050: fff60793 add a5,a2,-1 1519 | 11054: ce19 beqz a2,11072 1520 | 11056: 567d li a2,-1 1521 | 11058: a801 j 11068 1522 | 1105a: 0505 add a0,a0,1 1523 | 1105c: 00357713 and a4,a0,3 1524 | 11060: cf01 beqz a4,11078 1525 | 11062: 17fd add a5,a5,-1 1526 | 11064: 00c78763 beq a5,a2,11072 1527 | 11068: 00054703 lbu a4,0(a0) 1528 | 1106c: fed717e3 bne a4,a3,1105a 1529 | 11070: 8082 ret 1530 | 11072: 4501 li a0,0 1531 | 11074: 8082 ret 1532 | 11076: 87b2 mv a5,a2 1533 | 11078: 470d li a4,3 1534 | 1107a: 04f77263 bgeu a4,a5,110be 1535 | 1107e: 0ff5f593 zext.b a1,a1 1536 | 11082: 00859713 sll a4,a1,0x8 1537 | 11086: 95ba add a1,a1,a4 1538 | 11088: 01059713 sll a4,a1,0x10 1539 | 1108c: feff08b7 lui a7,0xfeff0 1540 | 11090: 80808837 lui a6,0x80808 1541 | 11094: 95ba add a1,a1,a4 1542 | 11096: eff88893 add a7,a7,-257 # fefefeff <__BSS_END__+0xfefdc1c3> 1543 | 1109a: 08080813 add a6,a6,128 # 80808080 <__BSS_END__+0x807f4344> 1544 | 1109e: 430d li t1,3 1545 | 110a0: a029 j 110aa 1546 | 110a2: 17f1 add a5,a5,-4 1547 | 110a4: 0511 add a0,a0,4 1548 | 110a6: 00f37c63 bgeu t1,a5,110be 1549 | 110aa: 4118 lw a4,0(a0) 1550 | 110ac: 8f2d xor a4,a4,a1 1551 | 110ae: 01170633 add a2,a4,a7 1552 | 110b2: fff74713 not a4,a4 1553 | 110b6: 8f71 and a4,a4,a2 1554 | 110b8: 01077733 and a4,a4,a6 1555 | 110bc: d37d beqz a4,110a2 1556 | 110be: 00f50733 add a4,a0,a5 1557 | 110c2: e789 bnez a5,110cc 1558 | 110c4: b77d j 11072 1559 | 110c6: 0505 add a0,a0,1 1560 | 110c8: faa705e3 beq a4,a0,11072 1561 | 110cc: 00054783 lbu a5,0(a0) 1562 | 110d0: fed79be3 bne a5,a3,110c6 1563 | 110d4: 8082 ret 1564 | 1565 | 000110d6 : 1566 | 110d6: 00b547b3 xor a5,a0,a1 1567 | 110da: 8b8d and a5,a5,3 1568 | 110dc: 00c508b3 add a7,a0,a2 1569 | 110e0: e7b1 bnez a5,1112c 1570 | 110e2: 478d li a5,3 1571 | 110e4: 04c7f463 bgeu a5,a2,1112c 1572 | 110e8: 00357793 and a5,a0,3 1573 | 110ec: 872a mv a4,a0 1574 | 110ee: ebb9 bnez a5,11144 1575 | 110f0: ffc8f613 and a2,a7,-4 1576 | 110f4: 40e606b3 sub a3,a2,a4 1577 | 110f8: 02000793 li a5,32 1578 | 110fc: 06d7c863 blt a5,a3,1116c 1579 | 11100: 86ae mv a3,a1 1580 | 11102: 87ba mv a5,a4 1581 | 11104: 02c77163 bgeu a4,a2,11126 1582 | 11108: 0006a803 lw a6,0(a3) 1583 | 1110c: 0791 add a5,a5,4 1584 | 1110e: 0691 add a3,a3,4 1585 | 11110: ff07ae23 sw a6,-4(a5) 1586 | 11114: fec7eae3 bltu a5,a2,11108 1587 | 11118: fff60793 add a5,a2,-1 1588 | 1111c: 8f99 sub a5,a5,a4 1589 | 1111e: 9bf1 and a5,a5,-4 1590 | 11120: 0791 add a5,a5,4 1591 | 11122: 973e add a4,a4,a5 1592 | 11124: 95be add a1,a1,a5 1593 | 11126: 01176663 bltu a4,a7,11132 1594 | 1112a: 8082 ret 1595 | 1112c: 872a mv a4,a0 1596 | 1112e: 03157e63 bgeu a0,a7,1116a 1597 | 11132: 0005c783 lbu a5,0(a1) 1598 | 11136: 0705 add a4,a4,1 1599 | 11138: 0585 add a1,a1,1 1600 | 1113a: fef70fa3 sb a5,-1(a4) 1601 | 1113e: fee89ae3 bne a7,a4,11132 1602 | 11142: 8082 ret 1603 | 11144: 0005c683 lbu a3,0(a1) 1604 | 11148: 0705 add a4,a4,1 1605 | 1114a: 00377793 and a5,a4,3 1606 | 1114e: fed70fa3 sb a3,-1(a4) 1607 | 11152: 0585 add a1,a1,1 1608 | 11154: dfd1 beqz a5,110f0 1609 | 11156: 0005c683 lbu a3,0(a1) 1610 | 1115a: 0705 add a4,a4,1 1611 | 1115c: 00377793 and a5,a4,3 1612 | 11160: fed70fa3 sb a3,-1(a4) 1613 | 11164: 0585 add a1,a1,1 1614 | 11166: fff9 bnez a5,11144 1615 | 11168: b761 j 110f0 1616 | 1116a: 8082 ret 1617 | 1116c: 1141 add sp,sp,-16 1618 | 1116e: c622 sw s0,12(sp) 1619 | 11170: 02000413 li s0,32 1620 | 11174: 0005a383 lw t2,0(a1) 1621 | 11178: 0045a283 lw t0,4(a1) 1622 | 1117c: 0085af83 lw t6,8(a1) 1623 | 11180: 00c5af03 lw t5,12(a1) 1624 | 11184: 0105ae83 lw t4,16(a1) 1625 | 11188: 0145ae03 lw t3,20(a1) 1626 | 1118c: 0185a303 lw t1,24(a1) 1627 | 11190: 01c5a803 lw a6,28(a1) 1628 | 11194: 5194 lw a3,32(a1) 1629 | 11196: 02470713 add a4,a4,36 1630 | 1119a: 40e607b3 sub a5,a2,a4 1631 | 1119e: fc772e23 sw t2,-36(a4) 1632 | 111a2: fe572023 sw t0,-32(a4) 1633 | 111a6: fff72223 sw t6,-28(a4) 1634 | 111aa: ffe72423 sw t5,-24(a4) 1635 | 111ae: ffd72623 sw t4,-20(a4) 1636 | 111b2: ffc72823 sw t3,-16(a4) 1637 | 111b6: fe672a23 sw t1,-12(a4) 1638 | 111ba: ff072c23 sw a6,-8(a4) 1639 | 111be: fed72e23 sw a3,-4(a4) 1640 | 111c2: 02458593 add a1,a1,36 1641 | 111c6: faf447e3 blt s0,a5,11174 1642 | 111ca: 86ae mv a3,a1 1643 | 111cc: 87ba mv a5,a4 1644 | 111ce: 02c77163 bgeu a4,a2,111f0 1645 | 111d2: 0006a803 lw a6,0(a3) 1646 | 111d6: 0791 add a5,a5,4 1647 | 111d8: 0691 add a3,a3,4 1648 | 111da: ff07ae23 sw a6,-4(a5) 1649 | 111de: fec7eae3 bltu a5,a2,111d2 1650 | 111e2: fff60793 add a5,a2,-1 1651 | 111e6: 8f99 sub a5,a5,a4 1652 | 111e8: 9bf1 and a5,a5,-4 1653 | 111ea: 0791 add a5,a5,4 1654 | 111ec: 973e add a4,a4,a5 1655 | 111ee: 95be add a1,a1,a5 1656 | 111f0: 01176563 bltu a4,a7,111fa 1657 | 111f4: 4432 lw s0,12(sp) 1658 | 111f6: 0141 add sp,sp,16 1659 | 111f8: 8082 ret 1660 | 111fa: 0005c783 lbu a5,0(a1) 1661 | 111fe: 0705 add a4,a4,1 1662 | 11200: 0585 add a1,a1,1 1663 | 11202: fef70fa3 sb a5,-1(a4) 1664 | 11206: fee887e3 beq a7,a4,111f4 1665 | 1120a: 0005c783 lbu a5,0(a1) 1666 | 1120e: 0705 add a4,a4,1 1667 | 11210: 0585 add a1,a1,1 1668 | 11212: fef70fa3 sb a5,-1(a4) 1669 | 11216: fee892e3 bne a7,a4,111fa 1670 | 1121a: bfe9 j 111f4 1671 | 1672 | 0001121c : 1673 | 1121c: 02a5f263 bgeu a1,a0,11240 1674 | 11220: 00c58733 add a4,a1,a2 1675 | 11224: 00e57e63 bgeu a0,a4,11240 1676 | 11228: 00c507b3 add a5,a0,a2 1677 | 1122c: ca1d beqz a2,11262 1678 | 1122e: fff74683 lbu a3,-1(a4) 1679 | 11232: 17fd add a5,a5,-1 1680 | 11234: 177d add a4,a4,-1 1681 | 11236: 00d78023 sb a3,0(a5) 1682 | 1123a: fef51ae3 bne a0,a5,1122e 1683 | 1123e: 8082 ret 1684 | 11240: 47bd li a5,15 1685 | 11242: 02c7e163 bltu a5,a2,11264 1686 | 11246: 87aa mv a5,a0 1687 | 11248: fff60693 add a3,a2,-1 1688 | 1124c: ce51 beqz a2,112e8 1689 | 1124e: 0685 add a3,a3,1 1690 | 11250: 96be add a3,a3,a5 1691 | 11252: 0005c703 lbu a4,0(a1) 1692 | 11256: 0785 add a5,a5,1 1693 | 11258: 0585 add a1,a1,1 1694 | 1125a: fee78fa3 sb a4,-1(a5) 1695 | 1125e: fed79ae3 bne a5,a3,11252 1696 | 11262: 8082 ret 1697 | 11264: 00b567b3 or a5,a0,a1 1698 | 11268: 8b8d and a5,a5,3 1699 | 1126a: ebbd bnez a5,112e0 1700 | 1126c: ff060893 add a7,a2,-16 1701 | 11270: ff08f893 and a7,a7,-16 1702 | 11274: 08c1 add a7,a7,16 1703 | 11276: 011507b3 add a5,a0,a7 1704 | 1127a: 86ae mv a3,a1 1705 | 1127c: 872a mv a4,a0 1706 | 1127e: 0006a803 lw a6,0(a3) 1707 | 11282: 06c1 add a3,a3,16 1708 | 11284: 0741 add a4,a4,16 1709 | 11286: ff072823 sw a6,-16(a4) 1710 | 1128a: ff46a803 lw a6,-12(a3) 1711 | 1128e: ff072a23 sw a6,-12(a4) 1712 | 11292: ff86a803 lw a6,-8(a3) 1713 | 11296: ff072c23 sw a6,-8(a4) 1714 | 1129a: ffc6a803 lw a6,-4(a3) 1715 | 1129e: ff072e23 sw a6,-4(a4) 1716 | 112a2: fcf71ee3 bne a4,a5,1127e 1717 | 112a6: 00c67713 and a4,a2,12 1718 | 112aa: 95c6 add a1,a1,a7 1719 | 112ac: 00f67813 and a6,a2,15 1720 | 112b0: cf0d beqz a4,112ea 1721 | 112b2: 86ae mv a3,a1 1722 | 112b4: 873e mv a4,a5 1723 | 112b6: 01078eb3 add t4,a5,a6 1724 | 112ba: 4e0d li t3,3 1725 | 112bc: 0006a303 lw t1,0(a3) 1726 | 112c0: 0711 add a4,a4,4 1727 | 112c2: 40ee88b3 sub a7,t4,a4 1728 | 112c6: fe672e23 sw t1,-4(a4) 1729 | 112ca: 0691 add a3,a3,4 1730 | 112cc: ff1e68e3 bltu t3,a7,112bc 1731 | 112d0: ffc80713 add a4,a6,-4 1732 | 112d4: 9b71 and a4,a4,-4 1733 | 112d6: 0711 add a4,a4,4 1734 | 112d8: 8a0d and a2,a2,3 1735 | 112da: 97ba add a5,a5,a4 1736 | 112dc: 95ba add a1,a1,a4 1737 | 112de: b7ad j 11248 1738 | 112e0: fff60693 add a3,a2,-1 1739 | 112e4: 87aa mv a5,a0 1740 | 112e6: b7a5 j 1124e 1741 | 112e8: 8082 ret 1742 | 112ea: 8642 mv a2,a6 1743 | 112ec: bfb1 j 11248 1744 | 1745 | 000112ee <__malloc_lock>: 1746 | 112ee: 8082 ret 1747 | 1748 | 000112f0 <__malloc_unlock>: 1749 | 112f0: 8082 ret 1750 | 1751 | 000112f2 <_realloc_r>: 1752 | 112f2: 7179 add sp,sp,-48 1753 | 112f4: d226 sw s1,36(sp) 1754 | 112f6: d606 sw ra,44(sp) 1755 | 112f8: d422 sw s0,40(sp) 1756 | 112fa: d04a sw s2,32(sp) 1757 | 112fc: ce4e sw s3,28(sp) 1758 | 112fe: cc52 sw s4,24(sp) 1759 | 11300: ca56 sw s5,20(sp) 1760 | 11302: c85a sw s6,16(sp) 1761 | 11304: c65e sw s7,12(sp) 1762 | 11306: c462 sw s8,8(sp) 1763 | 11308: 84b2 mv s1,a2 1764 | 1130a: 12058e63 beqz a1,11446 <_realloc_r+0x154> 1765 | 1130e: 842e mv s0,a1 1766 | 11310: 892a mv s2,a0 1767 | 11312: 3ff1 jal 112ee <__malloc_lock> 1768 | 11314: ffc42703 lw a4,-4(s0) 1769 | 11318: 00b48793 add a5,s1,11 1770 | 1131c: 46d9 li a3,22 1771 | 1131e: ff840a93 add s5,s0,-8 1772 | 11322: ffc77993 and s3,a4,-4 1773 | 11326: 0af6f763 bgeu a3,a5,113d4 <_realloc_r+0xe2> 1774 | 1132a: ff87fa13 and s4,a5,-8 1775 | 1132e: 0a07c663 bltz a5,113da <_realloc_r+0xe8> 1776 | 11332: 0a9a6463 bltu s4,s1,113da <_realloc_r+0xe8> 1777 | 11336: 0b49dc63 bge s3,s4,113ee <_realloc_r+0xfc> 1778 | 1133a: c2818c13 add s8,gp,-984 # 138c8 <__malloc_av_> 1779 | 1133e: 008c2603 lw a2,8(s8) 1780 | 11342: 013a86b3 add a3,s5,s3 1781 | 11346: 42dc lw a5,4(a3) 1782 | 11348: 12d60f63 beq a2,a3,11486 <_realloc_r+0x194> 1783 | 1134c: ffe7f613 and a2,a5,-2 1784 | 11350: 9636 add a2,a2,a3 1785 | 11352: 4250 lw a2,4(a2) 1786 | 11354: 8a05 and a2,a2,1 1787 | 11356: ee71 bnez a2,11432 <_realloc_r+0x140> 1788 | 11358: 9bf1 and a5,a5,-4 1789 | 1135a: 00f98633 add a2,s3,a5 1790 | 1135e: 09465363 bge a2,s4,113e4 <_realloc_r+0xf2> 1791 | 11362: 8b05 and a4,a4,1 1792 | 11364: e30d bnez a4,11386 <_realloc_r+0x94> 1793 | 11366: ff842b83 lw s7,-8(s0) 1794 | 1136a: 417a8bb3 sub s7,s5,s7 1795 | 1136e: 004ba703 lw a4,4(s7) 1796 | 11372: 9b71 and a4,a4,-4 1797 | 11374: 97ba add a5,a5,a4 1798 | 11376: 01378b33 add s6,a5,s3 1799 | 1137a: 234b5763 bge s6,s4,115a8 <_realloc_r+0x2b6> 1800 | 1137e: 00e98b33 add s6,s3,a4 1801 | 11382: 1d4b5063 bge s6,s4,11542 <_realloc_r+0x250> 1802 | 11386: 85a6 mv a1,s1 1803 | 11388: 854a mv a0,s2 1804 | 1138a: f3aff0ef jal 10ac4 <_malloc_r> 1805 | 1138e: 84aa mv s1,a0 1806 | 11390: 2c050763 beqz a0,1165e <_realloc_r+0x36c> 1807 | 11394: ffc42783 lw a5,-4(s0) 1808 | 11398: ff850713 add a4,a0,-8 1809 | 1139c: 9bf9 and a5,a5,-2 1810 | 1139e: 97d6 add a5,a5,s5 1811 | 113a0: 18e78c63 beq a5,a4,11538 <_realloc_r+0x246> 1812 | 113a4: ffc98613 add a2,s3,-4 1813 | 113a8: 02400793 li a5,36 1814 | 113ac: 1ec7eb63 bltu a5,a2,115a2 <_realloc_r+0x2b0> 1815 | 113b0: 474d li a4,19 1816 | 113b2: 16c76763 bltu a4,a2,11520 <_realloc_r+0x22e> 1817 | 113b6: 87aa mv a5,a0 1818 | 113b8: 8722 mv a4,s0 1819 | 113ba: 4314 lw a3,0(a4) 1820 | 113bc: c394 sw a3,0(a5) 1821 | 113be: 4354 lw a3,4(a4) 1822 | 113c0: c3d4 sw a3,4(a5) 1823 | 113c2: 4718 lw a4,8(a4) 1824 | 113c4: c798 sw a4,8(a5) 1825 | 113c6: 854a mv a0,s2 1826 | 113c8: 85a2 mv a1,s0 1827 | 113ca: 125000ef jal 11cee <_free_r> 1828 | 113ce: 854a mv a0,s2 1829 | 113d0: 3705 jal 112f0 <__malloc_unlock> 1830 | 113d2: a099 j 11418 <_realloc_r+0x126> 1831 | 113d4: 4a41 li s4,16 1832 | 113d6: f69a70e3 bgeu s4,s1,11336 <_realloc_r+0x44> 1833 | 113da: 47b1 li a5,12 1834 | 113dc: 00f92023 sw a5,0(s2) 1835 | 113e0: 4481 li s1,0 1836 | 113e2: a81d j 11418 <_realloc_r+0x126> 1837 | 113e4: 46dc lw a5,12(a3) 1838 | 113e6: 4698 lw a4,8(a3) 1839 | 113e8: 89b2 mv s3,a2 1840 | 113ea: c75c sw a5,12(a4) 1841 | 113ec: c798 sw a4,8(a5) 1842 | 113ee: 004aa783 lw a5,4(s5) 1843 | 113f2: 414986b3 sub a3,s3,s4 1844 | 113f6: 463d li a2,15 1845 | 113f8: 8b85 and a5,a5,1 1846 | 113fa: 013a8733 add a4,s5,s3 1847 | 113fe: 06d66263 bltu a2,a3,11462 <_realloc_r+0x170> 1848 | 11402: 0137e7b3 or a5,a5,s3 1849 | 11406: 00faa223 sw a5,4(s5) 1850 | 1140a: 435c lw a5,4(a4) 1851 | 1140c: 0017e793 or a5,a5,1 1852 | 11410: c35c sw a5,4(a4) 1853 | 11412: 854a mv a0,s2 1854 | 11414: 3df1 jal 112f0 <__malloc_unlock> 1855 | 11416: 84a2 mv s1,s0 1856 | 11418: 50b2 lw ra,44(sp) 1857 | 1141a: 5422 lw s0,40(sp) 1858 | 1141c: 5902 lw s2,32(sp) 1859 | 1141e: 49f2 lw s3,28(sp) 1860 | 11420: 4a62 lw s4,24(sp) 1861 | 11422: 4ad2 lw s5,20(sp) 1862 | 11424: 4b42 lw s6,16(sp) 1863 | 11426: 4bb2 lw s7,12(sp) 1864 | 11428: 4c22 lw s8,8(sp) 1865 | 1142a: 8526 mv a0,s1 1866 | 1142c: 5492 lw s1,36(sp) 1867 | 1142e: 6145 add sp,sp,48 1868 | 11430: 8082 ret 1869 | 11432: 8b05 and a4,a4,1 1870 | 11434: fb29 bnez a4,11386 <_realloc_r+0x94> 1871 | 11436: ff842b83 lw s7,-8(s0) 1872 | 1143a: 417a8bb3 sub s7,s5,s7 1873 | 1143e: 004ba703 lw a4,4(s7) 1874 | 11442: 9b71 and a4,a4,-4 1875 | 11444: bf2d j 1137e <_realloc_r+0x8c> 1876 | 11446: 5422 lw s0,40(sp) 1877 | 11448: 50b2 lw ra,44(sp) 1878 | 1144a: 5492 lw s1,36(sp) 1879 | 1144c: 5902 lw s2,32(sp) 1880 | 1144e: 49f2 lw s3,28(sp) 1881 | 11450: 4a62 lw s4,24(sp) 1882 | 11452: 4ad2 lw s5,20(sp) 1883 | 11454: 4b42 lw s6,16(sp) 1884 | 11456: 4bb2 lw s7,12(sp) 1885 | 11458: 4c22 lw s8,8(sp) 1886 | 1145a: 85b2 mv a1,a2 1887 | 1145c: 6145 add sp,sp,48 1888 | 1145e: e66ff06f j 10ac4 <_malloc_r> 1889 | 11462: 0147e7b3 or a5,a5,s4 1890 | 11466: 00faa223 sw a5,4(s5) 1891 | 1146a: 014a85b3 add a1,s5,s4 1892 | 1146e: 0016e693 or a3,a3,1 1893 | 11472: c1d4 sw a3,4(a1) 1894 | 11474: 435c lw a5,4(a4) 1895 | 11476: 05a1 add a1,a1,8 1896 | 11478: 854a mv a0,s2 1897 | 1147a: 0017e793 or a5,a5,1 1898 | 1147e: c35c sw a5,4(a4) 1899 | 11480: 06f000ef jal 11cee <_free_r> 1900 | 11484: b779 j 11412 <_realloc_r+0x120> 1901 | 11486: 9bf1 and a5,a5,-4 1902 | 11488: 013786b3 add a3,a5,s3 1903 | 1148c: 010a0613 add a2,s4,16 1904 | 11490: 18c6df63 bge a3,a2,1162e <_realloc_r+0x33c> 1905 | 11494: 8b05 and a4,a4,1 1906 | 11496: ee0718e3 bnez a4,11386 <_realloc_r+0x94> 1907 | 1149a: ff842b83 lw s7,-8(s0) 1908 | 1149e: 417a8bb3 sub s7,s5,s7 1909 | 114a2: 004ba703 lw a4,4(s7) 1910 | 114a6: 9b71 and a4,a4,-4 1911 | 114a8: 97ba add a5,a5,a4 1912 | 114aa: 01378b33 add s6,a5,s3 1913 | 114ae: eccb48e3 blt s6,a2,1137e <_realloc_r+0x8c> 1914 | 114b2: 00cba783 lw a5,12(s7) 1915 | 114b6: 008ba703 lw a4,8(s7) 1916 | 114ba: ffc98613 add a2,s3,-4 1917 | 114be: 02400693 li a3,36 1918 | 114c2: c75c sw a5,12(a4) 1919 | 114c4: c798 sw a4,8(a5) 1920 | 114c6: 008b8493 add s1,s7,8 1921 | 114ca: 1ac6e763 bltu a3,a2,11678 <_realloc_r+0x386> 1922 | 114ce: 474d li a4,19 1923 | 114d0: 87a6 mv a5,s1 1924 | 114d2: 00c77e63 bgeu a4,a2,114ee <_realloc_r+0x1fc> 1925 | 114d6: 4018 lw a4,0(s0) 1926 | 114d8: 47ed li a5,27 1927 | 114da: 00eba423 sw a4,8(s7) 1928 | 114de: 4058 lw a4,4(s0) 1929 | 114e0: 00eba623 sw a4,12(s7) 1930 | 114e4: 18c7ee63 bltu a5,a2,11680 <_realloc_r+0x38e> 1931 | 114e8: 0421 add s0,s0,8 1932 | 114ea: 010b8793 add a5,s7,16 1933 | 114ee: 4018 lw a4,0(s0) 1934 | 114f0: c398 sw a4,0(a5) 1935 | 114f2: 4058 lw a4,4(s0) 1936 | 114f4: c3d8 sw a4,4(a5) 1937 | 114f6: 4418 lw a4,8(s0) 1938 | 114f8: c798 sw a4,8(a5) 1939 | 114fa: 014b8733 add a4,s7,s4 1940 | 114fe: 414b0b33 sub s6,s6,s4 1941 | 11502: 00ec2423 sw a4,8(s8) 1942 | 11506: 001b6793 or a5,s6,1 1943 | 1150a: c35c sw a5,4(a4) 1944 | 1150c: 004ba783 lw a5,4(s7) 1945 | 11510: 854a mv a0,s2 1946 | 11512: 8b85 and a5,a5,1 1947 | 11514: 0147e7b3 or a5,a5,s4 1948 | 11518: 00fba223 sw a5,4(s7) 1949 | 1151c: 3bd1 jal 112f0 <__malloc_unlock> 1950 | 1151e: bded j 11418 <_realloc_r+0x126> 1951 | 11520: 4014 lw a3,0(s0) 1952 | 11522: 476d li a4,27 1953 | 11524: c114 sw a3,0(a0) 1954 | 11526: 4054 lw a3,4(s0) 1955 | 11528: c154 sw a3,4(a0) 1956 | 1152a: 0ec76763 bltu a4,a2,11618 <_realloc_r+0x326> 1957 | 1152e: 00840713 add a4,s0,8 1958 | 11532: 00850793 add a5,a0,8 1959 | 11536: b551 j 113ba <_realloc_r+0xc8> 1960 | 11538: ffc52783 lw a5,-4(a0) 1961 | 1153c: 9bf1 and a5,a5,-4 1962 | 1153e: 99be add s3,s3,a5 1963 | 11540: b57d j 113ee <_realloc_r+0xfc> 1964 | 11542: 00cba783 lw a5,12(s7) 1965 | 11546: 008ba703 lw a4,8(s7) 1966 | 1154a: ffc98613 add a2,s3,-4 1967 | 1154e: 02400693 li a3,36 1968 | 11552: c75c sw a5,12(a4) 1969 | 11554: c798 sw a4,8(a5) 1970 | 11556: 008b8493 add s1,s7,8 1971 | 1155a: 0ac6eb63 bltu a3,a2,11610 <_realloc_r+0x31e> 1972 | 1155e: 474d li a4,19 1973 | 11560: 87a6 mv a5,s1 1974 | 11562: 02c77663 bgeu a4,a2,1158e <_realloc_r+0x29c> 1975 | 11566: 4018 lw a4,0(s0) 1976 | 11568: 47ed li a5,27 1977 | 1156a: 00eba423 sw a4,8(s7) 1978 | 1156e: 4058 lw a4,4(s0) 1979 | 11570: 00eba623 sw a4,12(s7) 1980 | 11574: 0ec7f163 bgeu a5,a2,11656 <_realloc_r+0x364> 1981 | 11578: 441c lw a5,8(s0) 1982 | 1157a: 00fba823 sw a5,16(s7) 1983 | 1157e: 445c lw a5,12(s0) 1984 | 11580: 00fbaa23 sw a5,20(s7) 1985 | 11584: 06d60b63 beq a2,a3,115fa <_realloc_r+0x308> 1986 | 11588: 0441 add s0,s0,16 1987 | 1158a: 018b8793 add a5,s7,24 1988 | 1158e: 4018 lw a4,0(s0) 1989 | 11590: c398 sw a4,0(a5) 1990 | 11592: 4058 lw a4,4(s0) 1991 | 11594: c3d8 sw a4,4(a5) 1992 | 11596: 4418 lw a4,8(s0) 1993 | 11598: c798 sw a4,8(a5) 1994 | 1159a: 8426 mv s0,s1 1995 | 1159c: 89da mv s3,s6 1996 | 1159e: 8ade mv s5,s7 1997 | 115a0: b5b9 j 113ee <_realloc_r+0xfc> 1998 | 115a2: 85a2 mv a1,s0 1999 | 115a4: 39a5 jal 1121c 2000 | 115a6: b505 j 113c6 <_realloc_r+0xd4> 2001 | 115a8: 46dc lw a5,12(a3) 2002 | 115aa: 4698 lw a4,8(a3) 2003 | 115ac: ffc98613 add a2,s3,-4 2004 | 115b0: 02400693 li a3,36 2005 | 115b4: c75c sw a5,12(a4) 2006 | 115b6: c798 sw a4,8(a5) 2007 | 115b8: 008ba703 lw a4,8(s7) 2008 | 115bc: 00cba783 lw a5,12(s7) 2009 | 115c0: 008b8493 add s1,s7,8 2010 | 115c4: c75c sw a5,12(a4) 2011 | 115c6: c798 sw a4,8(a5) 2012 | 115c8: 04c6e463 bltu a3,a2,11610 <_realloc_r+0x31e> 2013 | 115cc: 474d li a4,19 2014 | 115ce: 87a6 mv a5,s1 2015 | 115d0: fac77fe3 bgeu a4,a2,1158e <_realloc_r+0x29c> 2016 | 115d4: 4018 lw a4,0(s0) 2017 | 115d6: 47ed li a5,27 2018 | 115d8: 00eba423 sw a4,8(s7) 2019 | 115dc: 4058 lw a4,4(s0) 2020 | 115de: 00eba623 sw a4,12(s7) 2021 | 115e2: 06c7fa63 bgeu a5,a2,11656 <_realloc_r+0x364> 2022 | 115e6: 4418 lw a4,8(s0) 2023 | 115e8: 02400793 li a5,36 2024 | 115ec: 00eba823 sw a4,16(s7) 2025 | 115f0: 4458 lw a4,12(s0) 2026 | 115f2: 00ebaa23 sw a4,20(s7) 2027 | 115f6: f8f619e3 bne a2,a5,11588 <_realloc_r+0x296> 2028 | 115fa: 4818 lw a4,16(s0) 2029 | 115fc: 020b8793 add a5,s7,32 2030 | 11600: 0461 add s0,s0,24 2031 | 11602: 00ebac23 sw a4,24(s7) 2032 | 11606: ffc42703 lw a4,-4(s0) 2033 | 1160a: 00ebae23 sw a4,28(s7) 2034 | 1160e: b741 j 1158e <_realloc_r+0x29c> 2035 | 11610: 85a2 mv a1,s0 2036 | 11612: 8526 mv a0,s1 2037 | 11614: 3121 jal 1121c 2038 | 11616: b751 j 1159a <_realloc_r+0x2a8> 2039 | 11618: 4418 lw a4,8(s0) 2040 | 1161a: c518 sw a4,8(a0) 2041 | 1161c: 4458 lw a4,12(s0) 2042 | 1161e: c558 sw a4,12(a0) 2043 | 11620: 04f60363 beq a2,a5,11666 <_realloc_r+0x374> 2044 | 11624: 01040713 add a4,s0,16 2045 | 11628: 01050793 add a5,a0,16 2046 | 1162c: b379 j 113ba <_realloc_r+0xc8> 2047 | 1162e: 9ad2 add s5,s5,s4 2048 | 11630: 414686b3 sub a3,a3,s4 2049 | 11634: 015c2423 sw s5,8(s8) 2050 | 11638: 0016e793 or a5,a3,1 2051 | 1163c: 00faa223 sw a5,4(s5) 2052 | 11640: ffc42783 lw a5,-4(s0) 2053 | 11644: 854a mv a0,s2 2054 | 11646: 84a2 mv s1,s0 2055 | 11648: 8b85 and a5,a5,1 2056 | 1164a: 0147e7b3 or a5,a5,s4 2057 | 1164e: fef42e23 sw a5,-4(s0) 2058 | 11652: 3979 jal 112f0 <__malloc_unlock> 2059 | 11654: b3d1 j 11418 <_realloc_r+0x126> 2060 | 11656: 0421 add s0,s0,8 2061 | 11658: 010b8793 add a5,s7,16 2062 | 1165c: bf0d j 1158e <_realloc_r+0x29c> 2063 | 1165e: 854a mv a0,s2 2064 | 11660: 3941 jal 112f0 <__malloc_unlock> 2065 | 11662: 4481 li s1,0 2066 | 11664: bb55 j 11418 <_realloc_r+0x126> 2067 | 11666: 4814 lw a3,16(s0) 2068 | 11668: 01840713 add a4,s0,24 2069 | 1166c: 01850793 add a5,a0,24 2070 | 11670: c914 sw a3,16(a0) 2071 | 11672: 4854 lw a3,20(s0) 2072 | 11674: c954 sw a3,20(a0) 2073 | 11676: b391 j 113ba <_realloc_r+0xc8> 2074 | 11678: 85a2 mv a1,s0 2075 | 1167a: 8526 mv a0,s1 2076 | 1167c: 3645 jal 1121c 2077 | 1167e: bdb5 j 114fa <_realloc_r+0x208> 2078 | 11680: 441c lw a5,8(s0) 2079 | 11682: 00fba823 sw a5,16(s7) 2080 | 11686: 445c lw a5,12(s0) 2081 | 11688: 00fbaa23 sw a5,20(s7) 2082 | 1168c: 00d60663 beq a2,a3,11698 <_realloc_r+0x3a6> 2083 | 11690: 0441 add s0,s0,16 2084 | 11692: 018b8793 add a5,s7,24 2085 | 11696: bda1 j 114ee <_realloc_r+0x1fc> 2086 | 11698: 4818 lw a4,16(s0) 2087 | 1169a: 020b8793 add a5,s7,32 2088 | 1169e: 00ebac23 sw a4,24(s7) 2089 | 116a2: 4858 lw a4,20(s0) 2090 | 116a4: 0461 add s0,s0,24 2091 | 116a6: 00ebae23 sw a4,28(s7) 2092 | 116aa: b591 j 114ee <_realloc_r+0x1fc> 2093 | 2094 | 000116ac <_sbrk_r>: 2095 | 116ac: 1141 add sp,sp,-16 2096 | 116ae: c422 sw s0,8(sp) 2097 | 116b0: c226 sw s1,4(sp) 2098 | 116b2: 842a mv s0,a0 2099 | 116b4: 852e mv a0,a1 2100 | 116b6: c606 sw ra,12(sp) 2101 | 116b8: 0401a823 sw zero,80(gp) # 13cf0 2102 | 116bc: 4bb000ef jal 12376 <_sbrk> 2103 | 116c0: 57fd li a5,-1 2104 | 116c2: 00f50763 beq a0,a5,116d0 <_sbrk_r+0x24> 2105 | 116c6: 40b2 lw ra,12(sp) 2106 | 116c8: 4422 lw s0,8(sp) 2107 | 116ca: 4492 lw s1,4(sp) 2108 | 116cc: 0141 add sp,sp,16 2109 | 116ce: 8082 ret 2110 | 116d0: 0501a783 lw a5,80(gp) # 13cf0 2111 | 116d4: dbed beqz a5,116c6 <_sbrk_r+0x1a> 2112 | 116d6: 40b2 lw ra,12(sp) 2113 | 116d8: c01c sw a5,0(s0) 2114 | 116da: 4422 lw s0,8(sp) 2115 | 116dc: 4492 lw s1,4(sp) 2116 | 116de: 0141 add sp,sp,16 2117 | 116e0: 8082 ret 2118 | 2119 | 000116e2 <__sread>: 2120 | 116e2: 1141 add sp,sp,-16 2121 | 116e4: c422 sw s0,8(sp) 2122 | 116e6: 842e mv s0,a1 2123 | 116e8: 00e59583 lh a1,14(a1) 2124 | 116ec: c606 sw ra,12(sp) 2125 | 116ee: 1eb000ef jal 120d8 <_read_r> 2126 | 116f2: 00054963 bltz a0,11704 <__sread+0x22> 2127 | 116f6: 483c lw a5,80(s0) 2128 | 116f8: 40b2 lw ra,12(sp) 2129 | 116fa: 97aa add a5,a5,a0 2130 | 116fc: c83c sw a5,80(s0) 2131 | 116fe: 4422 lw s0,8(sp) 2132 | 11700: 0141 add sp,sp,16 2133 | 11702: 8082 ret 2134 | 11704: 00c45783 lhu a5,12(s0) 2135 | 11708: 777d lui a4,0xfffff 2136 | 1170a: 177d add a4,a4,-1 # ffffefff <__BSS_END__+0xfffeb2c3> 2137 | 1170c: 8ff9 and a5,a5,a4 2138 | 1170e: 40b2 lw ra,12(sp) 2139 | 11710: 00f41623 sh a5,12(s0) 2140 | 11714: 4422 lw s0,8(sp) 2141 | 11716: 0141 add sp,sp,16 2142 | 11718: 8082 ret 2143 | 2144 | 0001171a <__seofread>: 2145 | 1171a: 4501 li a0,0 2146 | 1171c: 8082 ret 2147 | 2148 | 0001171e <__swrite>: 2149 | 1171e: 00c59783 lh a5,12(a1) 2150 | 11722: 1101 add sp,sp,-32 2151 | 11724: cc22 sw s0,24(sp) 2152 | 11726: ca26 sw s1,20(sp) 2153 | 11728: c84a sw s2,16(sp) 2154 | 1172a: c64e sw s3,12(sp) 2155 | 1172c: ce06 sw ra,28(sp) 2156 | 1172e: 1007f713 and a4,a5,256 2157 | 11732: 842e mv s0,a1 2158 | 11734: 84aa mv s1,a0 2159 | 11736: 8932 mv s2,a2 2160 | 11738: 89b6 mv s3,a3 2161 | 1173a: e315 bnez a4,1175e <__swrite+0x40> 2162 | 1173c: 777d lui a4,0xfffff 2163 | 1173e: 177d add a4,a4,-1 # ffffefff <__BSS_END__+0xfffeb2c3> 2164 | 11740: 8ff9 and a5,a5,a4 2165 | 11742: 00e41583 lh a1,14(s0) 2166 | 11746: 00f41623 sh a5,12(s0) 2167 | 1174a: 4462 lw s0,24(sp) 2168 | 1174c: 40f2 lw ra,28(sp) 2169 | 1174e: 86ce mv a3,s3 2170 | 11750: 864a mv a2,s2 2171 | 11752: 49b2 lw s3,12(sp) 2172 | 11754: 4942 lw s2,16(sp) 2173 | 11756: 8526 mv a0,s1 2174 | 11758: 44d2 lw s1,20(sp) 2175 | 1175a: 6105 add sp,sp,32 2176 | 1175c: a095 j 117c0 <_write_r> 2177 | 1175e: 00e59583 lh a1,14(a1) 2178 | 11762: 4689 li a3,2 2179 | 11764: 4601 li a2,0 2180 | 11766: 7a8000ef jal 11f0e <_lseek_r> 2181 | 1176a: 00c41783 lh a5,12(s0) 2182 | 1176e: b7f9 j 1173c <__swrite+0x1e> 2183 | 2184 | 00011770 <__sseek>: 2185 | 11770: 1141 add sp,sp,-16 2186 | 11772: c422 sw s0,8(sp) 2187 | 11774: 842e mv s0,a1 2188 | 11776: 00e59583 lh a1,14(a1) 2189 | 1177a: c606 sw ra,12(sp) 2190 | 1177c: 792000ef jal 11f0e <_lseek_r> 2191 | 11780: 57fd li a5,-1 2192 | 11782: 00f50f63 beq a0,a5,117a0 <__sseek+0x30> 2193 | 11786: 00c45783 lhu a5,12(s0) 2194 | 1178a: 6705 lui a4,0x1 2195 | 1178c: 40b2 lw ra,12(sp) 2196 | 1178e: 8fd9 or a5,a5,a4 2197 | 11790: 07c2 sll a5,a5,0x10 2198 | 11792: 87c1 sra a5,a5,0x10 2199 | 11794: c828 sw a0,80(s0) 2200 | 11796: 00f41623 sh a5,12(s0) 2201 | 1179a: 4422 lw s0,8(sp) 2202 | 1179c: 0141 add sp,sp,16 2203 | 1179e: 8082 ret 2204 | 117a0: 00c45783 lhu a5,12(s0) 2205 | 117a4: 777d lui a4,0xfffff 2206 | 117a6: 177d add a4,a4,-1 # ffffefff <__BSS_END__+0xfffeb2c3> 2207 | 117a8: 8ff9 and a5,a5,a4 2208 | 117aa: 07c2 sll a5,a5,0x10 2209 | 117ac: 87c1 sra a5,a5,0x10 2210 | 117ae: 40b2 lw ra,12(sp) 2211 | 117b0: 00f41623 sh a5,12(s0) 2212 | 117b4: 4422 lw s0,8(sp) 2213 | 117b6: 0141 add sp,sp,16 2214 | 117b8: 8082 ret 2215 | 2216 | 000117ba <__sclose>: 2217 | 117ba: 00e59583 lh a1,14(a1) 2218 | 117be: a249 j 11940 <_close_r> 2219 | 2220 | 000117c0 <_write_r>: 2221 | 117c0: 1141 add sp,sp,-16 2222 | 117c2: 872e mv a4,a1 2223 | 117c4: c422 sw s0,8(sp) 2224 | 117c6: c226 sw s1,4(sp) 2225 | 117c8: 85b2 mv a1,a2 2226 | 117ca: 842a mv s0,a0 2227 | 117cc: 8636 mv a2,a3 2228 | 117ce: 853a mv a0,a4 2229 | 117d0: c606 sw ra,12(sp) 2230 | 117d2: 0401a823 sw zero,80(gp) # 13cf0 2231 | 117d6: 3f3000ef jal 123c8 <_write> 2232 | 117da: 57fd li a5,-1 2233 | 117dc: 00f50763 beq a0,a5,117ea <_write_r+0x2a> 2234 | 117e0: 40b2 lw ra,12(sp) 2235 | 117e2: 4422 lw s0,8(sp) 2236 | 117e4: 4492 lw s1,4(sp) 2237 | 117e6: 0141 add sp,sp,16 2238 | 117e8: 8082 ret 2239 | 117ea: 0501a783 lw a5,80(gp) # 13cf0 2240 | 117ee: dbed beqz a5,117e0 <_write_r+0x20> 2241 | 117f0: 40b2 lw ra,12(sp) 2242 | 117f2: c01c sw a5,0(s0) 2243 | 117f4: 4422 lw s0,8(sp) 2244 | 117f6: 4492 lw s1,4(sp) 2245 | 117f8: 0141 add sp,sp,16 2246 | 117fa: 8082 ret 2247 | 2248 | 000117fc <__swsetup_r>: 2249 | 117fc: 0381a783 lw a5,56(gp) # 13cd8 <_impure_ptr> 2250 | 11800: 1141 add sp,sp,-16 2251 | 11802: c422 sw s0,8(sp) 2252 | 11804: c226 sw s1,4(sp) 2253 | 11806: c606 sw ra,12(sp) 2254 | 11808: 84aa mv s1,a0 2255 | 1180a: 842e mv s0,a1 2256 | 1180c: c399 beqz a5,11812 <__swsetup_r+0x16> 2257 | 1180e: 5f98 lw a4,56(a5) 2258 | 11810: cb29 beqz a4,11862 <__swsetup_r+0x66> 2259 | 11812: 00c41783 lh a5,12(s0) 2260 | 11816: 0087f713 and a4,a5,8 2261 | 1181a: cf21 beqz a4,11872 <__swsetup_r+0x76> 2262 | 1181c: 4818 lw a4,16(s0) 2263 | 1181e: c735 beqz a4,1188a <__swsetup_r+0x8e> 2264 | 11820: 0017f693 and a3,a5,1 2265 | 11824: ce91 beqz a3,11840 <__swsetup_r+0x44> 2266 | 11826: 4854 lw a3,20(s0) 2267 | 11828: 00042423 sw zero,8(s0) 2268 | 1182c: 4501 li a0,0 2269 | 1182e: 40d006b3 neg a3,a3 2270 | 11832: cc14 sw a3,24(s0) 2271 | 11834: cf11 beqz a4,11850 <__swsetup_r+0x54> 2272 | 11836: 40b2 lw ra,12(sp) 2273 | 11838: 4422 lw s0,8(sp) 2274 | 1183a: 4492 lw s1,4(sp) 2275 | 1183c: 0141 add sp,sp,16 2276 | 1183e: 8082 ret 2277 | 11840: 0027f693 and a3,a5,2 2278 | 11844: 4601 li a2,0 2279 | 11846: e291 bnez a3,1184a <__swsetup_r+0x4e> 2280 | 11848: 4850 lw a2,20(s0) 2281 | 1184a: c410 sw a2,8(s0) 2282 | 1184c: 4501 li a0,0 2283 | 1184e: f765 bnez a4,11836 <__swsetup_r+0x3a> 2284 | 11850: 0807f713 and a4,a5,128 2285 | 11854: d36d beqz a4,11836 <__swsetup_r+0x3a> 2286 | 11856: 0407e793 or a5,a5,64 2287 | 1185a: 00f41623 sh a5,12(s0) 2288 | 1185e: 557d li a0,-1 2289 | 11860: bfd9 j 11836 <__swsetup_r+0x3a> 2290 | 11862: 853e mv a0,a5 2291 | 11864: e09fe0ef jal 1066c <__sinit> 2292 | 11868: 00c41783 lh a5,12(s0) 2293 | 1186c: 0087f713 and a4,a5,8 2294 | 11870: f755 bnez a4,1181c <__swsetup_r+0x20> 2295 | 11872: 0107f713 and a4,a5,16 2296 | 11876: cb31 beqz a4,118ca <__swsetup_r+0xce> 2297 | 11878: 0047f713 and a4,a5,4 2298 | 1187c: e705 bnez a4,118a4 <__swsetup_r+0xa8> 2299 | 1187e: 4818 lw a4,16(s0) 2300 | 11880: 0087e793 or a5,a5,8 2301 | 11884: 00f41623 sh a5,12(s0) 2302 | 11888: ff41 bnez a4,11820 <__swsetup_r+0x24> 2303 | 1188a: 2807f693 and a3,a5,640 2304 | 1188e: 20000613 li a2,512 2305 | 11892: f8c687e3 beq a3,a2,11820 <__swsetup_r+0x24> 2306 | 11896: 85a2 mv a1,s0 2307 | 11898: 8526 mv a0,s1 2308 | 1189a: 257d jal 11f48 <__smakebuf_r> 2309 | 1189c: 00c41783 lh a5,12(s0) 2310 | 118a0: 4818 lw a4,16(s0) 2311 | 118a2: bfbd j 11820 <__swsetup_r+0x24> 2312 | 118a4: 580c lw a1,48(s0) 2313 | 118a6: c999 beqz a1,118bc <__swsetup_r+0xc0> 2314 | 118a8: 04040713 add a4,s0,64 2315 | 118ac: 00e58663 beq a1,a4,118b8 <__swsetup_r+0xbc> 2316 | 118b0: 8526 mv a0,s1 2317 | 118b2: 2935 jal 11cee <_free_r> 2318 | 118b4: 00c41783 lh a5,12(s0) 2319 | 118b8: 02042823 sw zero,48(s0) 2320 | 118bc: 4818 lw a4,16(s0) 2321 | 118be: fdb7f793 and a5,a5,-37 2322 | 118c2: 00042223 sw zero,4(s0) 2323 | 118c6: c018 sw a4,0(s0) 2324 | 118c8: bf65 j 11880 <__swsetup_r+0x84> 2325 | 118ca: 4725 li a4,9 2326 | 118cc: c098 sw a4,0(s1) 2327 | 118ce: 0407e793 or a5,a5,64 2328 | 118d2: b761 j 1185a <__swsetup_r+0x5e> 2329 | 2330 | 000118d4 <__register_exitproc>: 2331 | 118d4: 0301a703 lw a4,48(gp) # 13cd0 <_global_impure_ptr> 2332 | 118d8: 14872783 lw a5,328(a4) 2333 | 118dc: c3a1 beqz a5,1191c <__register_exitproc+0x48> 2334 | 118de: 43d8 lw a4,4(a5) 2335 | 118e0: 487d li a6,31 2336 | 118e2: 04e84d63 blt a6,a4,1193c <__register_exitproc+0x68> 2337 | 118e6: 00271813 sll a6,a4,0x2 2338 | 118ea: c11d beqz a0,11910 <__register_exitproc+0x3c> 2339 | 118ec: 01078333 add t1,a5,a6 2340 | 118f0: 08c32423 sw a2,136(t1) 2341 | 118f4: 1887a883 lw a7,392(a5) 2342 | 118f8: 4605 li a2,1 2343 | 118fa: 00e61633 sll a2,a2,a4 2344 | 118fe: 00c8e8b3 or a7,a7,a2 2345 | 11902: 1917a423 sw a7,392(a5) 2346 | 11906: 10d32423 sw a3,264(t1) 2347 | 1190a: 4689 li a3,2 2348 | 1190c: 00d50d63 beq a0,a3,11926 <__register_exitproc+0x52> 2349 | 11910: 0705 add a4,a4,1 2350 | 11912: c3d8 sw a4,4(a5) 2351 | 11914: 97c2 add a5,a5,a6 2352 | 11916: c78c sw a1,8(a5) 2353 | 11918: 4501 li a0,0 2354 | 1191a: 8082 ret 2355 | 1191c: 14c70793 add a5,a4,332 2356 | 11920: 14f72423 sw a5,328(a4) 2357 | 11924: bf6d j 118de <__register_exitproc+0xa> 2358 | 11926: 18c7a683 lw a3,396(a5) 2359 | 1192a: 0705 add a4,a4,1 2360 | 1192c: c3d8 sw a4,4(a5) 2361 | 1192e: 8ed1 or a3,a3,a2 2362 | 11930: 18d7a623 sw a3,396(a5) 2363 | 11934: 97c2 add a5,a5,a6 2364 | 11936: c78c sw a1,8(a5) 2365 | 11938: 4501 li a0,0 2366 | 1193a: 8082 ret 2367 | 1193c: 557d li a0,-1 2368 | 1193e: 8082 ret 2369 | 2370 | 00011940 <_close_r>: 2371 | 11940: 1141 add sp,sp,-16 2372 | 11942: c422 sw s0,8(sp) 2373 | 11944: c226 sw s1,4(sp) 2374 | 11946: 842a mv s0,a0 2375 | 11948: 852e mv a0,a1 2376 | 1194a: c606 sw ra,12(sp) 2377 | 1194c: 0401a823 sw zero,80(gp) # 13cf0 2378 | 11950: 12f000ef jal 1227e <_close> 2379 | 11954: 57fd li a5,-1 2380 | 11956: 00f50763 beq a0,a5,11964 <_close_r+0x24> 2381 | 1195a: 40b2 lw ra,12(sp) 2382 | 1195c: 4422 lw s0,8(sp) 2383 | 1195e: 4492 lw s1,4(sp) 2384 | 11960: 0141 add sp,sp,16 2385 | 11962: 8082 ret 2386 | 11964: 0501a783 lw a5,80(gp) # 13cf0 2387 | 11968: dbed beqz a5,1195a <_close_r+0x1a> 2388 | 1196a: 40b2 lw ra,12(sp) 2389 | 1196c: c01c sw a5,0(s0) 2390 | 1196e: 4422 lw s0,8(sp) 2391 | 11970: 4492 lw s1,4(sp) 2392 | 11972: 0141 add sp,sp,16 2393 | 11974: 8082 ret 2394 | 2395 | 00011976 <_fclose_r>: 2396 | 11976: 1141 add sp,sp,-16 2397 | 11978: c606 sw ra,12(sp) 2398 | 1197a: c422 sw s0,8(sp) 2399 | 1197c: c226 sw s1,4(sp) 2400 | 1197e: c04a sw s2,0(sp) 2401 | 11980: c989 beqz a1,11992 <_fclose_r+0x1c> 2402 | 11982: 842e mv s0,a1 2403 | 11984: 84aa mv s1,a0 2404 | 11986: c119 beqz a0,1198c <_fclose_r+0x16> 2405 | 11988: 5d1c lw a5,56(a0) 2406 | 1198a: cbad beqz a5,119fc <_fclose_r+0x86> 2407 | 1198c: 00c41783 lh a5,12(s0) 2408 | 11990: eb89 bnez a5,119a2 <_fclose_r+0x2c> 2409 | 11992: 40b2 lw ra,12(sp) 2410 | 11994: 4422 lw s0,8(sp) 2411 | 11996: 4901 li s2,0 2412 | 11998: 4492 lw s1,4(sp) 2413 | 1199a: 854a mv a0,s2 2414 | 1199c: 4902 lw s2,0(sp) 2415 | 1199e: 0141 add sp,sp,16 2416 | 119a0: 8082 ret 2417 | 119a2: 85a2 mv a1,s0 2418 | 119a4: 8526 mv a0,s1 2419 | 119a6: 28bd jal 11a24 <__sflush_r> 2420 | 119a8: 545c lw a5,44(s0) 2421 | 119aa: 892a mv s2,a0 2422 | 119ac: c791 beqz a5,119b8 <_fclose_r+0x42> 2423 | 119ae: 4c4c lw a1,28(s0) 2424 | 119b0: 8526 mv a0,s1 2425 | 119b2: 9782 jalr a5 2426 | 119b4: 04054a63 bltz a0,11a08 <_fclose_r+0x92> 2427 | 119b8: 00c45783 lhu a5,12(s0) 2428 | 119bc: 0807f793 and a5,a5,128 2429 | 119c0: ebb1 bnez a5,11a14 <_fclose_r+0x9e> 2430 | 119c2: 580c lw a1,48(s0) 2431 | 119c4: c989 beqz a1,119d6 <_fclose_r+0x60> 2432 | 119c6: 04040793 add a5,s0,64 2433 | 119ca: 00f58463 beq a1,a5,119d2 <_fclose_r+0x5c> 2434 | 119ce: 8526 mv a0,s1 2435 | 119d0: 2e39 jal 11cee <_free_r> 2436 | 119d2: 02042823 sw zero,48(s0) 2437 | 119d6: 406c lw a1,68(s0) 2438 | 119d8: c589 beqz a1,119e2 <_fclose_r+0x6c> 2439 | 119da: 8526 mv a0,s1 2440 | 119dc: 2e09 jal 11cee <_free_r> 2441 | 119de: 04042223 sw zero,68(s0) 2442 | 119e2: c93fe0ef jal 10674 <__sfp_lock_acquire> 2443 | 119e6: 00041623 sh zero,12(s0) 2444 | 119ea: c8dfe0ef jal 10676 <__sfp_lock_release> 2445 | 119ee: 40b2 lw ra,12(sp) 2446 | 119f0: 4422 lw s0,8(sp) 2447 | 119f2: 4492 lw s1,4(sp) 2448 | 119f4: 854a mv a0,s2 2449 | 119f6: 4902 lw s2,0(sp) 2450 | 119f8: 0141 add sp,sp,16 2451 | 119fa: 8082 ret 2452 | 119fc: c71fe0ef jal 1066c <__sinit> 2453 | 11a00: 00c41783 lh a5,12(s0) 2454 | 11a04: d7d9 beqz a5,11992 <_fclose_r+0x1c> 2455 | 11a06: bf71 j 119a2 <_fclose_r+0x2c> 2456 | 11a08: 00c45783 lhu a5,12(s0) 2457 | 11a0c: 597d li s2,-1 2458 | 11a0e: 0807f793 and a5,a5,128 2459 | 11a12: dbc5 beqz a5,119c2 <_fclose_r+0x4c> 2460 | 11a14: 480c lw a1,16(s0) 2461 | 11a16: 8526 mv a0,s1 2462 | 11a18: 2cd9 jal 11cee <_free_r> 2463 | 11a1a: b765 j 119c2 <_fclose_r+0x4c> 2464 | 2465 | 00011a1c : 2466 | 11a1c: 85aa mv a1,a0 2467 | 11a1e: 0381a503 lw a0,56(gp) # 13cd8 <_impure_ptr> 2468 | 11a22: bf91 j 11976 <_fclose_r> 2469 | 2470 | 00011a24 <__sflush_r>: 2471 | 11a24: 00c59783 lh a5,12(a1) 2472 | 11a28: 1101 add sp,sp,-32 2473 | 11a2a: cc22 sw s0,24(sp) 2474 | 11a2c: c64e sw s3,12(sp) 2475 | 11a2e: ce06 sw ra,28(sp) 2476 | 11a30: ca26 sw s1,20(sp) 2477 | 11a32: c84a sw s2,16(sp) 2478 | 11a34: 0087f713 and a4,a5,8 2479 | 11a38: 842e mv s0,a1 2480 | 11a3a: 89aa mv s3,a0 2481 | 11a3c: e361 bnez a4,11afc <__sflush_r+0xd8> 2482 | 11a3e: 6705 lui a4,0x1 2483 | 11a40: 80070713 add a4,a4,-2048 # 800 2484 | 11a44: 41d4 lw a3,4(a1) 2485 | 11a46: 8f5d or a4,a4,a5 2486 | 11a48: 00e59623 sh a4,12(a1) 2487 | 11a4c: 10d05363 blez a3,11b52 <__sflush_r+0x12e> 2488 | 11a50: 02842803 lw a6,40(s0) 2489 | 11a54: 08080c63 beqz a6,11aec <__sflush_r+0xc8> 2490 | 11a58: 83b1 srl a5,a5,0xc 2491 | 11a5a: 0009a483 lw s1,0(s3) 2492 | 11a5e: 8b85 and a5,a5,1 2493 | 11a60: 0009a023 sw zero,0(s3) 2494 | 11a64: 4c4c lw a1,28(s0) 2495 | 11a66: ebfd bnez a5,11b5c <__sflush_r+0x138> 2496 | 11a68: 4601 li a2,0 2497 | 11a6a: 4685 li a3,1 2498 | 11a6c: 854e mv a0,s3 2499 | 11a6e: 9802 jalr a6 2500 | 11a70: 57fd li a5,-1 2501 | 11a72: 862a mv a2,a0 2502 | 11a74: 10f50763 beq a0,a5,11b82 <__sflush_r+0x15e> 2503 | 11a78: 00c41703 lh a4,12(s0) 2504 | 11a7c: 02842803 lw a6,40(s0) 2505 | 11a80: 4c4c lw a1,28(s0) 2506 | 11a82: 8b11 and a4,a4,4 2507 | 11a84: c719 beqz a4,11a92 <__sflush_r+0x6e> 2508 | 11a86: 4058 lw a4,4(s0) 2509 | 11a88: 581c lw a5,48(s0) 2510 | 11a8a: 8e19 sub a2,a2,a4 2511 | 11a8c: c399 beqz a5,11a92 <__sflush_r+0x6e> 2512 | 11a8e: 5c5c lw a5,60(s0) 2513 | 11a90: 8e1d sub a2,a2,a5 2514 | 11a92: 4681 li a3,0 2515 | 11a94: 854e mv a0,s3 2516 | 11a96: 9802 jalr a6 2517 | 11a98: 57fd li a5,-1 2518 | 11a9a: 0cf51363 bne a0,a5,11b60 <__sflush_r+0x13c> 2519 | 11a9e: 0009a683 lw a3,0(s3) 2520 | 11aa2: 47f5 li a5,29 2521 | 11aa4: 08d7e963 bltu a5,a3,11b36 <__sflush_r+0x112> 2522 | 11aa8: dfc00737 lui a4,0xdfc00 2523 | 11aac: 1779 add a4,a4,-2 # dfbffffe <__BSS_END__+0xdfbec2c2> 2524 | 11aae: 40d75733 sra a4,a4,a3 2525 | 11ab2: 8b05 and a4,a4,1 2526 | 11ab4: 00c41783 lh a5,12(s0) 2527 | 11ab8: e349 bnez a4,11b3a <__sflush_r+0x116> 2528 | 11aba: 4810 lw a2,16(s0) 2529 | 11abc: 777d lui a4,0xfffff 2530 | 11abe: 7ff70713 add a4,a4,2047 # fffff7ff <__BSS_END__+0xfffebac3> 2531 | 11ac2: 8f7d and a4,a4,a5 2532 | 11ac4: 83b1 srl a5,a5,0xc 2533 | 11ac6: 00e41623 sh a4,12(s0) 2534 | 11aca: 00042223 sw zero,4(s0) 2535 | 11ace: c010 sw a2,0(s0) 2536 | 11ad0: 8b85 and a5,a5,1 2537 | 11ad2: e7f1 bnez a5,11b9e <__sflush_r+0x17a> 2538 | 11ad4: 580c lw a1,48(s0) 2539 | 11ad6: 0099a023 sw s1,0(s3) 2540 | 11ada: c989 beqz a1,11aec <__sflush_r+0xc8> 2541 | 11adc: 04040793 add a5,s0,64 2542 | 11ae0: 00f58463 beq a1,a5,11ae8 <__sflush_r+0xc4> 2543 | 11ae4: 854e mv a0,s3 2544 | 11ae6: 2421 jal 11cee <_free_r> 2545 | 11ae8: 02042823 sw zero,48(s0) 2546 | 11aec: 4501 li a0,0 2547 | 11aee: 40f2 lw ra,28(sp) 2548 | 11af0: 4462 lw s0,24(sp) 2549 | 11af2: 44d2 lw s1,20(sp) 2550 | 11af4: 4942 lw s2,16(sp) 2551 | 11af6: 49b2 lw s3,12(sp) 2552 | 11af8: 6105 add sp,sp,32 2553 | 11afa: 8082 ret 2554 | 11afc: 0105a903 lw s2,16(a1) 2555 | 11b00: fe0906e3 beqz s2,11aec <__sflush_r+0xc8> 2556 | 11b04: 4184 lw s1,0(a1) 2557 | 11b06: 8b8d and a5,a5,3 2558 | 11b08: 0125a023 sw s2,0(a1) 2559 | 11b0c: 412484b3 sub s1,s1,s2 2560 | 11b10: 4701 li a4,0 2561 | 11b12: e391 bnez a5,11b16 <__sflush_r+0xf2> 2562 | 11b14: 49d8 lw a4,20(a1) 2563 | 11b16: c418 sw a4,8(s0) 2564 | 11b18: 00904663 bgtz s1,11b24 <__sflush_r+0x100> 2565 | 11b1c: bfc1 j 11aec <__sflush_r+0xc8> 2566 | 11b1e: 992a add s2,s2,a0 2567 | 11b20: fc9056e3 blez s1,11aec <__sflush_r+0xc8> 2568 | 11b24: 505c lw a5,36(s0) 2569 | 11b26: 4c4c lw a1,28(s0) 2570 | 11b28: 86a6 mv a3,s1 2571 | 11b2a: 864a mv a2,s2 2572 | 11b2c: 854e mv a0,s3 2573 | 11b2e: 9782 jalr a5 2574 | 11b30: 8c89 sub s1,s1,a0 2575 | 11b32: fea046e3 bgtz a0,11b1e <__sflush_r+0xfa> 2576 | 11b36: 00c41783 lh a5,12(s0) 2577 | 11b3a: 0407e793 or a5,a5,64 2578 | 11b3e: 40f2 lw ra,28(sp) 2579 | 11b40: 00f41623 sh a5,12(s0) 2580 | 11b44: 4462 lw s0,24(sp) 2581 | 11b46: 44d2 lw s1,20(sp) 2582 | 11b48: 4942 lw s2,16(sp) 2583 | 11b4a: 49b2 lw s3,12(sp) 2584 | 11b4c: 557d li a0,-1 2585 | 11b4e: 6105 add sp,sp,32 2586 | 11b50: 8082 ret 2587 | 11b52: 5dd4 lw a3,60(a1) 2588 | 11b54: eed04ee3 bgtz a3,11a50 <__sflush_r+0x2c> 2589 | 11b58: 4501 li a0,0 2590 | 11b5a: bf51 j 11aee <__sflush_r+0xca> 2591 | 11b5c: 4830 lw a2,80(s0) 2592 | 11b5e: b715 j 11a82 <__sflush_r+0x5e> 2593 | 11b60: 00c41783 lh a5,12(s0) 2594 | 11b64: 4814 lw a3,16(s0) 2595 | 11b66: 777d lui a4,0xfffff 2596 | 11b68: 7ff70713 add a4,a4,2047 # fffff7ff <__BSS_END__+0xfffebac3> 2597 | 11b6c: 8f7d and a4,a4,a5 2598 | 11b6e: 83b1 srl a5,a5,0xc 2599 | 11b70: 00e41623 sh a4,12(s0) 2600 | 11b74: 00042223 sw zero,4(s0) 2601 | 11b78: c014 sw a3,0(s0) 2602 | 11b7a: 8b85 and a5,a5,1 2603 | 11b7c: dfa1 beqz a5,11ad4 <__sflush_r+0xb0> 2604 | 11b7e: c828 sw a0,80(s0) 2605 | 11b80: bf91 j 11ad4 <__sflush_r+0xb0> 2606 | 11b82: 0009a783 lw a5,0(s3) 2607 | 11b86: ee0789e3 beqz a5,11a78 <__sflush_r+0x54> 2608 | 11b8a: 4775 li a4,29 2609 | 11b8c: 00e78563 beq a5,a4,11b96 <__sflush_r+0x172> 2610 | 11b90: 4759 li a4,22 2611 | 11b92: fae792e3 bne a5,a4,11b36 <__sflush_r+0x112> 2612 | 11b96: 0099a023 sw s1,0(s3) 2613 | 11b9a: 4501 li a0,0 2614 | 11b9c: bf89 j 11aee <__sflush_r+0xca> 2615 | 11b9e: fa9d bnez a3,11ad4 <__sflush_r+0xb0> 2616 | 11ba0: c828 sw a0,80(s0) 2617 | 11ba2: bf0d j 11ad4 <__sflush_r+0xb0> 2618 | 2619 | 00011ba4 <_fflush_r>: 2620 | 11ba4: 1101 add sp,sp,-32 2621 | 11ba6: cc22 sw s0,24(sp) 2622 | 11ba8: ce06 sw ra,28(sp) 2623 | 11baa: 842a mv s0,a0 2624 | 11bac: c119 beqz a0,11bb2 <_fflush_r+0xe> 2625 | 11bae: 5d1c lw a5,56(a0) 2626 | 11bb0: cb89 beqz a5,11bc2 <_fflush_r+0x1e> 2627 | 11bb2: 00c59783 lh a5,12(a1) 2628 | 11bb6: ef89 bnez a5,11bd0 <_fflush_r+0x2c> 2629 | 11bb8: 40f2 lw ra,28(sp) 2630 | 11bba: 4462 lw s0,24(sp) 2631 | 11bbc: 4501 li a0,0 2632 | 11bbe: 6105 add sp,sp,32 2633 | 11bc0: 8082 ret 2634 | 11bc2: c62e sw a1,12(sp) 2635 | 11bc4: aa9fe0ef jal 1066c <__sinit> 2636 | 11bc8: 45b2 lw a1,12(sp) 2637 | 11bca: 00c59783 lh a5,12(a1) 2638 | 11bce: d7ed beqz a5,11bb8 <_fflush_r+0x14> 2639 | 11bd0: 8522 mv a0,s0 2640 | 11bd2: 4462 lw s0,24(sp) 2641 | 11bd4: 40f2 lw ra,28(sp) 2642 | 11bd6: 6105 add sp,sp,32 2643 | 11bd8: b5b1 j 11a24 <__sflush_r> 2644 | 2645 | 00011bda : 2646 | 11bda: cd1d beqz a0,11c18 2647 | 11bdc: 1101 add sp,sp,-32 2648 | 11bde: cc22 sw s0,24(sp) 2649 | 11be0: 842a mv s0,a0 2650 | 11be2: 0381a503 lw a0,56(gp) # 13cd8 <_impure_ptr> 2651 | 11be6: ce06 sw ra,28(sp) 2652 | 11be8: c119 beqz a0,11bee 2653 | 11bea: 5d1c lw a5,56(a0) 2654 | 11bec: cf91 beqz a5,11c08 2655 | 11bee: 00c41783 lh a5,12(s0) 2656 | 11bf2: e791 bnez a5,11bfe 2657 | 11bf4: 40f2 lw ra,28(sp) 2658 | 11bf6: 4462 lw s0,24(sp) 2659 | 11bf8: 4501 li a0,0 2660 | 11bfa: 6105 add sp,sp,32 2661 | 11bfc: 8082 ret 2662 | 11bfe: 85a2 mv a1,s0 2663 | 11c00: 4462 lw s0,24(sp) 2664 | 11c02: 40f2 lw ra,28(sp) 2665 | 11c04: 6105 add sp,sp,32 2666 | 11c06: bd39 j 11a24 <__sflush_r> 2667 | 11c08: c62a sw a0,12(sp) 2668 | 11c0a: a63fe0ef jal 1066c <__sinit> 2669 | 11c0e: 00c41783 lh a5,12(s0) 2670 | 11c12: 4532 lw a0,12(sp) 2671 | 11c14: d3e5 beqz a5,11bf4 2672 | 11c16: b7e5 j 11bfe 2673 | 11c18: 0301a503 lw a0,48(gp) # 13cd0 <_global_impure_ptr> 2674 | 11c1c: 65c9 lui a1,0x12 2675 | 11c1e: ba458593 add a1,a1,-1116 # 11ba4 <_fflush_r> 2676 | 11c22: e2ffe06f j 10a50 <_fwalk_reent> 2677 | 2678 | 00011c26 <_malloc_trim_r>: 2679 | 11c26: 1101 add sp,sp,-32 2680 | 11c28: c64e sw s3,12(sp) 2681 | 11c2a: cc22 sw s0,24(sp) 2682 | 11c2c: ca26 sw s1,20(sp) 2683 | 11c2e: c84a sw s2,16(sp) 2684 | 11c30: c452 sw s4,8(sp) 2685 | 11c32: ce06 sw ra,28(sp) 2686 | 11c34: 8a2e mv s4,a1 2687 | 11c36: 892a mv s2,a0 2688 | 11c38: c2818993 add s3,gp,-984 # 138c8 <__malloc_av_> 2689 | 11c3c: eb2ff0ef jal 112ee <__malloc_lock> 2690 | 11c40: 0089a703 lw a4,8(s3) 2691 | 11c44: 6785 lui a5,0x1 2692 | 11c46: fef78413 add s0,a5,-17 # fef 2693 | 11c4a: 4344 lw s1,4(a4) 2694 | 11c4c: 98f1 and s1,s1,-4 2695 | 11c4e: 9426 add s0,s0,s1 2696 | 11c50: 41440433 sub s0,s0,s4 2697 | 11c54: 8031 srl s0,s0,0xc 2698 | 11c56: 147d add s0,s0,-1 2699 | 11c58: 0432 sll s0,s0,0xc 2700 | 11c5a: 00f44b63 blt s0,a5,11c70 <_malloc_trim_r+0x4a> 2701 | 11c5e: 4581 li a1,0 2702 | 11c60: 854a mv a0,s2 2703 | 11c62: a4bff0ef jal 116ac <_sbrk_r> 2704 | 11c66: 0089a783 lw a5,8(s3) 2705 | 11c6a: 97a6 add a5,a5,s1 2706 | 11c6c: 00f50e63 beq a0,a5,11c88 <_malloc_trim_r+0x62> 2707 | 11c70: 854a mv a0,s2 2708 | 11c72: e7eff0ef jal 112f0 <__malloc_unlock> 2709 | 11c76: 40f2 lw ra,28(sp) 2710 | 11c78: 4462 lw s0,24(sp) 2711 | 11c7a: 44d2 lw s1,20(sp) 2712 | 11c7c: 4942 lw s2,16(sp) 2713 | 11c7e: 49b2 lw s3,12(sp) 2714 | 11c80: 4a22 lw s4,8(sp) 2715 | 11c82: 4501 li a0,0 2716 | 11c84: 6105 add sp,sp,32 2717 | 11c86: 8082 ret 2718 | 11c88: 408005b3 neg a1,s0 2719 | 11c8c: 854a mv a0,s2 2720 | 11c8e: a1fff0ef jal 116ac <_sbrk_r> 2721 | 11c92: 57fd li a5,-1 2722 | 11c94: 02f50963 beq a0,a5,11cc6 <_malloc_trim_r+0xa0> 2723 | 11c98: 07418793 add a5,gp,116 # 13d14 <__malloc_current_mallinfo> 2724 | 11c9c: 4398 lw a4,0(a5) 2725 | 11c9e: 0089a683 lw a3,8(s3) 2726 | 11ca2: 8c81 sub s1,s1,s0 2727 | 11ca4: 0014e493 or s1,s1,1 2728 | 11ca8: 8f01 sub a4,a4,s0 2729 | 11caa: 854a mv a0,s2 2730 | 11cac: c2c4 sw s1,4(a3) 2731 | 11cae: c398 sw a4,0(a5) 2732 | 11cb0: e40ff0ef jal 112f0 <__malloc_unlock> 2733 | 11cb4: 40f2 lw ra,28(sp) 2734 | 11cb6: 4462 lw s0,24(sp) 2735 | 11cb8: 44d2 lw s1,20(sp) 2736 | 11cba: 4942 lw s2,16(sp) 2737 | 11cbc: 49b2 lw s3,12(sp) 2738 | 11cbe: 4a22 lw s4,8(sp) 2739 | 11cc0: 4505 li a0,1 2740 | 11cc2: 6105 add sp,sp,32 2741 | 11cc4: 8082 ret 2742 | 11cc6: 4581 li a1,0 2743 | 11cc8: 854a mv a0,s2 2744 | 11cca: 9e3ff0ef jal 116ac <_sbrk_r> 2745 | 11cce: 0089a703 lw a4,8(s3) 2746 | 11cd2: 46bd li a3,15 2747 | 11cd4: 40e507b3 sub a5,a0,a4 2748 | 11cd8: f8f6dce3 bge a3,a5,11c70 <_malloc_trim_r+0x4a> 2749 | 11cdc: 03c1a683 lw a3,60(gp) # 13cdc <__malloc_sbrk_base> 2750 | 11ce0: 0017e793 or a5,a5,1 2751 | 11ce4: c35c sw a5,4(a4) 2752 | 11ce6: 8d15 sub a0,a0,a3 2753 | 11ce8: 06a1aa23 sw a0,116(gp) # 13d14 <__malloc_current_mallinfo> 2754 | 11cec: b751 j 11c70 <_malloc_trim_r+0x4a> 2755 | 2756 | 00011cee <_free_r>: 2757 | 11cee: 10058a63 beqz a1,11e02 <_free_r+0x114> 2758 | 11cf2: 1141 add sp,sp,-16 2759 | 11cf4: c422 sw s0,8(sp) 2760 | 11cf6: c226 sw s1,4(sp) 2761 | 11cf8: 842e mv s0,a1 2762 | 11cfa: 84aa mv s1,a0 2763 | 11cfc: c606 sw ra,12(sp) 2764 | 11cfe: df0ff0ef jal 112ee <__malloc_lock> 2765 | 11d02: ffc42503 lw a0,-4(s0) 2766 | 11d06: ff840713 add a4,s0,-8 2767 | 11d0a: ffe57793 and a5,a0,-2 2768 | 11d0e: 00f70633 add a2,a4,a5 2769 | 11d12: c2818593 add a1,gp,-984 # 138c8 <__malloc_av_> 2770 | 11d16: 4254 lw a3,4(a2) 2771 | 11d18: 0085a803 lw a6,8(a1) 2772 | 11d1c: 9af1 and a3,a3,-4 2773 | 11d1e: 12c80363 beq a6,a2,11e44 <_free_r+0x156> 2774 | 11d22: c254 sw a3,4(a2) 2775 | 11d24: 8905 and a0,a0,1 2776 | 11d26: 00d60833 add a6,a2,a3 2777 | 11d2a: e935 bnez a0,11d9e <_free_r+0xb0> 2778 | 11d2c: ff842303 lw t1,-8(s0) 2779 | 11d30: 00482803 lw a6,4(a6) 2780 | 11d34: 40670733 sub a4,a4,t1 2781 | 11d38: 00872883 lw a7,8(a4) 2782 | 11d3c: c3018513 add a0,gp,-976 # 138d0 <__malloc_av_+0x8> 2783 | 11d40: 979a add a5,a5,t1 2784 | 11d42: 00187813 and a6,a6,1 2785 | 11d46: 0ea88263 beq a7,a0,11e2a <_free_r+0x13c> 2786 | 11d4a: 00c72303 lw t1,12(a4) 2787 | 11d4e: 0068a623 sw t1,12(a7) 2788 | 11d52: 01132423 sw a7,8(t1) 2789 | 11d56: 10080f63 beqz a6,11e74 <_free_r+0x186> 2790 | 11d5a: 0017e693 or a3,a5,1 2791 | 11d5e: c354 sw a3,4(a4) 2792 | 11d60: c21c sw a5,0(a2) 2793 | 11d62: 1ff00693 li a3,511 2794 | 11d66: 04f6e963 bltu a3,a5,11db8 <_free_r+0xca> 2795 | 11d6a: ff87f693 and a3,a5,-8 2796 | 11d6e: 06a1 add a3,a3,8 2797 | 11d70: 41c8 lw a0,4(a1) 2798 | 11d72: 96ae add a3,a3,a1 2799 | 11d74: 4290 lw a2,0(a3) 2800 | 11d76: 0057d813 srl a6,a5,0x5 2801 | 11d7a: 4785 li a5,1 2802 | 11d7c: 010797b3 sll a5,a5,a6 2803 | 11d80: 8fc9 or a5,a5,a0 2804 | 11d82: ff868513 add a0,a3,-8 2805 | 11d86: c748 sw a0,12(a4) 2806 | 11d88: c710 sw a2,8(a4) 2807 | 11d8a: c1dc sw a5,4(a1) 2808 | 11d8c: c298 sw a4,0(a3) 2809 | 11d8e: c658 sw a4,12(a2) 2810 | 11d90: 4422 lw s0,8(sp) 2811 | 11d92: 40b2 lw ra,12(sp) 2812 | 11d94: 8526 mv a0,s1 2813 | 11d96: 4492 lw s1,4(sp) 2814 | 11d98: 0141 add sp,sp,16 2815 | 11d9a: d56ff06f j 112f0 <__malloc_unlock> 2816 | 11d9e: 00482503 lw a0,4(a6) 2817 | 11da2: 8905 and a0,a0,1 2818 | 11da4: c125 beqz a0,11e04 <_free_r+0x116> 2819 | 11da6: 0017e693 or a3,a5,1 2820 | 11daa: fed42e23 sw a3,-4(s0) 2821 | 11dae: c21c sw a5,0(a2) 2822 | 11db0: 1ff00693 li a3,511 2823 | 11db4: faf6fbe3 bgeu a3,a5,11d6a <_free_r+0x7c> 2824 | 11db8: 0097d693 srl a3,a5,0x9 2825 | 11dbc: 4611 li a2,4 2826 | 11dbe: 0ad66d63 bltu a2,a3,11e78 <_free_r+0x18a> 2827 | 11dc2: 0067d693 srl a3,a5,0x6 2828 | 11dc6: 03968513 add a0,a3,57 2829 | 11dca: 03868613 add a2,a3,56 2830 | 11dce: 050e sll a0,a0,0x3 2831 | 11dd0: 952e add a0,a0,a1 2832 | 11dd2: 4114 lw a3,0(a0) 2833 | 11dd4: 1561 add a0,a0,-8 2834 | 11dd6: 00d51663 bne a0,a3,11de2 <_free_r+0xf4> 2835 | 11dda: a8f1 j 11eb6 <_free_r+0x1c8> 2836 | 11ddc: 4694 lw a3,8(a3) 2837 | 11dde: 00d50663 beq a0,a3,11dea <_free_r+0xfc> 2838 | 11de2: 42d0 lw a2,4(a3) 2839 | 11de4: 9a71 and a2,a2,-4 2840 | 11de6: fec7ebe3 bltu a5,a2,11ddc <_free_r+0xee> 2841 | 11dea: 46c8 lw a0,12(a3) 2842 | 11dec: c748 sw a0,12(a4) 2843 | 11dee: c714 sw a3,8(a4) 2844 | 11df0: 4422 lw s0,8(sp) 2845 | 11df2: c518 sw a4,8(a0) 2846 | 11df4: 40b2 lw ra,12(sp) 2847 | 11df6: 8526 mv a0,s1 2848 | 11df8: 4492 lw s1,4(sp) 2849 | 11dfa: c6d8 sw a4,12(a3) 2850 | 11dfc: 0141 add sp,sp,16 2851 | 11dfe: cf2ff06f j 112f0 <__malloc_unlock> 2852 | 11e02: 8082 ret 2853 | 11e04: 97b6 add a5,a5,a3 2854 | 11e06: c3018513 add a0,gp,-976 # 138d0 <__malloc_av_+0x8> 2855 | 11e0a: 4614 lw a3,8(a2) 2856 | 11e0c: 08a68b63 beq a3,a0,11ea2 <_free_r+0x1b4> 2857 | 11e10: 00c62803 lw a6,12(a2) 2858 | 11e14: 0017e513 or a0,a5,1 2859 | 11e18: 00f70633 add a2,a4,a5 2860 | 11e1c: 0106a623 sw a6,12(a3) 2861 | 11e20: 00d82423 sw a3,8(a6) 2862 | 11e24: c348 sw a0,4(a4) 2863 | 11e26: c21c sw a5,0(a2) 2864 | 11e28: bf2d j 11d62 <_free_r+0x74> 2865 | 11e2a: 0c081d63 bnez a6,11f04 <_free_r+0x216> 2866 | 11e2e: 460c lw a1,8(a2) 2867 | 11e30: 4650 lw a2,12(a2) 2868 | 11e32: 96be add a3,a3,a5 2869 | 11e34: 0016e793 or a5,a3,1 2870 | 11e38: c5d0 sw a2,12(a1) 2871 | 11e3a: c60c sw a1,8(a2) 2872 | 11e3c: c35c sw a5,4(a4) 2873 | 11e3e: 9736 add a4,a4,a3 2874 | 11e40: c314 sw a3,0(a4) 2875 | 11e42: b7b9 j 11d90 <_free_r+0xa2> 2876 | 11e44: 8905 and a0,a0,1 2877 | 11e46: 96be add a3,a3,a5 2878 | 11e48: e909 bnez a0,11e5a <_free_r+0x16c> 2879 | 11e4a: ff842503 lw a0,-8(s0) 2880 | 11e4e: 8f09 sub a4,a4,a0 2881 | 11e50: 475c lw a5,12(a4) 2882 | 11e52: 4710 lw a2,8(a4) 2883 | 11e54: 96aa add a3,a3,a0 2884 | 11e56: c65c sw a5,12(a2) 2885 | 11e58: c790 sw a2,8(a5) 2886 | 11e5a: 0016e613 or a2,a3,1 2887 | 11e5e: 0401a783 lw a5,64(gp) # 13ce0 <__malloc_trim_threshold> 2888 | 11e62: c350 sw a2,4(a4) 2889 | 11e64: c598 sw a4,8(a1) 2890 | 11e66: f2f6e5e3 bltu a3,a5,11d90 <_free_r+0xa2> 2891 | 11e6a: 04c1a583 lw a1,76(gp) # 13cec <__malloc_top_pad> 2892 | 11e6e: 8526 mv a0,s1 2893 | 11e70: 3b5d jal 11c26 <_malloc_trim_r> 2894 | 11e72: bf39 j 11d90 <_free_r+0xa2> 2895 | 11e74: 97b6 add a5,a5,a3 2896 | 11e76: bf51 j 11e0a <_free_r+0x11c> 2897 | 11e78: 4651 li a2,20 2898 | 11e7a: 00d67e63 bgeu a2,a3,11e96 <_free_r+0x1a8> 2899 | 11e7e: 05400613 li a2,84 2900 | 11e82: 04d66463 bltu a2,a3,11eca <_free_r+0x1dc> 2901 | 11e86: 00c7d693 srl a3,a5,0xc 2902 | 11e8a: 06f68513 add a0,a3,111 2903 | 11e8e: 06e68613 add a2,a3,110 2904 | 11e92: 050e sll a0,a0,0x3 2905 | 11e94: bf35 j 11dd0 <_free_r+0xe2> 2906 | 11e96: 05c68513 add a0,a3,92 2907 | 11e9a: 05b68613 add a2,a3,91 2908 | 11e9e: 050e sll a0,a0,0x3 2909 | 11ea0: bf05 j 11dd0 <_free_r+0xe2> 2910 | 11ea2: c9d8 sw a4,20(a1) 2911 | 11ea4: c998 sw a4,16(a1) 2912 | 11ea6: 0017e693 or a3,a5,1 2913 | 11eaa: c748 sw a0,12(a4) 2914 | 11eac: c708 sw a0,8(a4) 2915 | 11eae: c354 sw a3,4(a4) 2916 | 11eb0: 973e add a4,a4,a5 2917 | 11eb2: c31c sw a5,0(a4) 2918 | 11eb4: bdf1 j 11d90 <_free_r+0xa2> 2919 | 11eb6: 0045a803 lw a6,4(a1) 2920 | 11eba: 8609 sra a2,a2,0x2 2921 | 11ebc: 4785 li a5,1 2922 | 11ebe: 00c797b3 sll a5,a5,a2 2923 | 11ec2: 0107e7b3 or a5,a5,a6 2924 | 11ec6: c1dc sw a5,4(a1) 2925 | 11ec8: b715 j 11dec <_free_r+0xfe> 2926 | 11eca: 15400613 li a2,340 2927 | 11ece: 00d66a63 bltu a2,a3,11ee2 <_free_r+0x1f4> 2928 | 11ed2: 00f7d693 srl a3,a5,0xf 2929 | 11ed6: 07868513 add a0,a3,120 2930 | 11eda: 07768613 add a2,a3,119 2931 | 11ede: 050e sll a0,a0,0x3 2932 | 11ee0: bdc5 j 11dd0 <_free_r+0xe2> 2933 | 11ee2: 55400613 li a2,1364 2934 | 11ee6: 00d66a63 bltu a2,a3,11efa <_free_r+0x20c> 2935 | 11eea: 0127d693 srl a3,a5,0x12 2936 | 11eee: 07d68513 add a0,a3,125 2937 | 11ef2: 07c68613 add a2,a3,124 2938 | 11ef6: 050e sll a0,a0,0x3 2939 | 11ef8: bde1 j 11dd0 <_free_r+0xe2> 2940 | 11efa: 3f800513 li a0,1016 2941 | 11efe: 07e00613 li a2,126 2942 | 11f02: b5f9 j 11dd0 <_free_r+0xe2> 2943 | 11f04: 0017e693 or a3,a5,1 2944 | 11f08: c354 sw a3,4(a4) 2945 | 11f0a: c21c sw a5,0(a2) 2946 | 11f0c: b551 j 11d90 <_free_r+0xa2> 2947 | 2948 | 00011f0e <_lseek_r>: 2949 | 11f0e: 1141 add sp,sp,-16 2950 | 11f10: 872e mv a4,a1 2951 | 11f12: c422 sw s0,8(sp) 2952 | 11f14: c226 sw s1,4(sp) 2953 | 11f16: 85b2 mv a1,a2 2954 | 11f18: 842a mv s0,a0 2955 | 11f1a: 8636 mv a2,a3 2956 | 11f1c: 853a mv a0,a4 2957 | 11f1e: c606 sw ra,12(sp) 2958 | 11f20: 0401a823 sw zero,80(gp) # 13cf0 2959 | 11f24: 2efd jal 12322 <_lseek> 2960 | 11f26: 57fd li a5,-1 2961 | 11f28: 00f50763 beq a0,a5,11f36 <_lseek_r+0x28> 2962 | 11f2c: 40b2 lw ra,12(sp) 2963 | 11f2e: 4422 lw s0,8(sp) 2964 | 11f30: 4492 lw s1,4(sp) 2965 | 11f32: 0141 add sp,sp,16 2966 | 11f34: 8082 ret 2967 | 11f36: 0501a783 lw a5,80(gp) # 13cf0 2968 | 11f3a: dbed beqz a5,11f2c <_lseek_r+0x1e> 2969 | 11f3c: 40b2 lw ra,12(sp) 2970 | 11f3e: c01c sw a5,0(s0) 2971 | 11f40: 4422 lw s0,8(sp) 2972 | 11f42: 4492 lw s1,4(sp) 2973 | 11f44: 0141 add sp,sp,16 2974 | 11f46: 8082 ret 2975 | 2976 | 00011f48 <__smakebuf_r>: 2977 | 11f48: 00c59783 lh a5,12(a1) 2978 | 11f4c: 7119 add sp,sp,-128 2979 | 11f4e: dca2 sw s0,120(sp) 2980 | 11f50: de86 sw ra,124(sp) 2981 | 11f52: daa6 sw s1,116(sp) 2982 | 11f54: d8ca sw s2,112(sp) 2983 | 11f56: d6ce sw s3,108(sp) 2984 | 11f58: d4d2 sw s4,104(sp) 2985 | 11f5a: 0027f713 and a4,a5,2 2986 | 11f5e: 842e mv s0,a1 2987 | 11f60: cf19 beqz a4,11f7e <__smakebuf_r+0x36> 2988 | 11f62: 04358793 add a5,a1,67 2989 | 11f66: c19c sw a5,0(a1) 2990 | 11f68: c99c sw a5,16(a1) 2991 | 11f6a: 4785 li a5,1 2992 | 11f6c: c9dc sw a5,20(a1) 2993 | 11f6e: 50f6 lw ra,124(sp) 2994 | 11f70: 5466 lw s0,120(sp) 2995 | 11f72: 54d6 lw s1,116(sp) 2996 | 11f74: 5946 lw s2,112(sp) 2997 | 11f76: 59b6 lw s3,108(sp) 2998 | 11f78: 5a26 lw s4,104(sp) 2999 | 11f7a: 6109 add sp,sp,128 3000 | 11f7c: 8082 ret 3001 | 11f7e: 00e59583 lh a1,14(a1) 3002 | 11f82: 84aa mv s1,a0 3003 | 11f84: 0605c663 bltz a1,11ff0 <__smakebuf_r+0xa8> 3004 | 11f88: 0030 add a2,sp,8 3005 | 11f8a: 2461 jal 12212 <_fstat_r> 3006 | 11f8c: 06054063 bltz a0,11fec <__smakebuf_r+0xa4> 3007 | 11f90: 47b2 lw a5,12(sp) 3008 | 11f92: 693d lui s2,0xf 3009 | 11f94: 6985 lui s3,0x1 3010 | 11f96: 00f97933 and s2,s2,a5 3011 | 11f9a: 77f9 lui a5,0xffffe 3012 | 11f9c: 993e add s2,s2,a5 3013 | 11f9e: 00193913 seqz s2,s2 3014 | 11fa2: 40000a13 li s4,1024 3015 | 11fa6: 80098993 add s3,s3,-2048 # 800 3016 | 11faa: 85d2 mv a1,s4 3017 | 11fac: 8526 mv a0,s1 3018 | 11fae: b17fe0ef jal 10ac4 <_malloc_r> 3019 | 11fb2: 00c41783 lh a5,12(s0) 3020 | 11fb6: c939 beqz a0,1200c <__smakebuf_r+0xc4> 3021 | 11fb8: 6741 lui a4,0x10 3022 | 11fba: 41e70713 add a4,a4,1054 # 1041e <_cleanup_r> 3023 | 11fbe: dcd8 sw a4,60(s1) 3024 | 11fc0: 0807e793 or a5,a5,128 3025 | 11fc4: 00f41623 sh a5,12(s0) 3026 | 11fc8: c008 sw a0,0(s0) 3027 | 11fca: c808 sw a0,16(s0) 3028 | 11fcc: 01442a23 sw s4,20(s0) 3029 | 11fd0: 06091163 bnez s2,12032 <__smakebuf_r+0xea> 3030 | 11fd4: 0137e7b3 or a5,a5,s3 3031 | 11fd8: 50f6 lw ra,124(sp) 3032 | 11fda: 00f41623 sh a5,12(s0) 3033 | 11fde: 5466 lw s0,120(sp) 3034 | 11fe0: 54d6 lw s1,116(sp) 3035 | 11fe2: 5946 lw s2,112(sp) 3036 | 11fe4: 59b6 lw s3,108(sp) 3037 | 11fe6: 5a26 lw s4,104(sp) 3038 | 11fe8: 6109 add sp,sp,128 3039 | 11fea: 8082 ret 3040 | 11fec: 00c41783 lh a5,12(s0) 3041 | 11ff0: 0807f793 and a5,a5,128 3042 | 11ff4: 4901 li s2,0 3043 | 11ff6: cb95 beqz a5,1202a <__smakebuf_r+0xe2> 3044 | 11ff8: 04000a13 li s4,64 3045 | 11ffc: 85d2 mv a1,s4 3046 | 11ffe: 8526 mv a0,s1 3047 | 12000: ac5fe0ef jal 10ac4 <_malloc_r> 3048 | 12004: 00c41783 lh a5,12(s0) 3049 | 12008: 4981 li s3,0 3050 | 1200a: f55d bnez a0,11fb8 <__smakebuf_r+0x70> 3051 | 1200c: 2007f713 and a4,a5,512 3052 | 12010: ff39 bnez a4,11f6e <__smakebuf_r+0x26> 3053 | 12012: 9bf1 and a5,a5,-4 3054 | 12014: 0027e793 or a5,a5,2 3055 | 12018: 04340713 add a4,s0,67 3056 | 1201c: 00f41623 sh a5,12(s0) 3057 | 12020: 4785 li a5,1 3058 | 12022: c018 sw a4,0(s0) 3059 | 12024: c818 sw a4,16(s0) 3060 | 12026: c85c sw a5,20(s0) 3061 | 12028: b799 j 11f6e <__smakebuf_r+0x26> 3062 | 1202a: 40000a13 li s4,1024 3063 | 1202e: 4981 li s3,0 3064 | 12030: bfad j 11faa <__smakebuf_r+0x62> 3065 | 12032: 00e41583 lh a1,14(s0) 3066 | 12036: 8526 mv a0,s1 3067 | 12038: 2c09 jal 1224a <_isatty_r> 3068 | 1203a: e501 bnez a0,12042 <__smakebuf_r+0xfa> 3069 | 1203c: 00c41783 lh a5,12(s0) 3070 | 12040: bf51 j 11fd4 <__smakebuf_r+0x8c> 3071 | 12042: 00c45783 lhu a5,12(s0) 3072 | 12046: 9bf1 and a5,a5,-4 3073 | 12048: 0017e793 or a5,a5,1 3074 | 1204c: 07c2 sll a5,a5,0x10 3075 | 1204e: 87c1 sra a5,a5,0x10 3076 | 12050: b751 j 11fd4 <__smakebuf_r+0x8c> 3077 | 3078 | 00012052 <__swhatbuf_r>: 3079 | 12052: 7159 add sp,sp,-112 3080 | 12054: d4a2 sw s0,104(sp) 3081 | 12056: 842e mv s0,a1 3082 | 12058: 00e59583 lh a1,14(a1) 3083 | 1205c: d2a6 sw s1,100(sp) 3084 | 1205e: d0ca sw s2,96(sp) 3085 | 12060: d686 sw ra,108(sp) 3086 | 12062: 84b2 mv s1,a2 3087 | 12064: 8936 mv s2,a3 3088 | 12066: 0205cb63 bltz a1,1209c <__swhatbuf_r+0x4a> 3089 | 1206a: 0030 add a2,sp,8 3090 | 1206c: 225d jal 12212 <_fstat_r> 3091 | 1206e: 02054763 bltz a0,1209c <__swhatbuf_r+0x4a> 3092 | 12072: 4732 lw a4,12(sp) 3093 | 12074: 67bd lui a5,0xf 3094 | 12076: 50b6 lw ra,108(sp) 3095 | 12078: 8ff9 and a5,a5,a4 3096 | 1207a: 7779 lui a4,0xffffe 3097 | 1207c: 97ba add a5,a5,a4 3098 | 1207e: 5426 lw s0,104(sp) 3099 | 12080: 0017b793 seqz a5,a5 3100 | 12084: 00f92023 sw a5,0(s2) # f000 3101 | 12088: 40000713 li a4,1024 3102 | 1208c: c098 sw a4,0(s1) 3103 | 1208e: 6505 lui a0,0x1 3104 | 12090: 5496 lw s1,100(sp) 3105 | 12092: 5906 lw s2,96(sp) 3106 | 12094: 80050513 add a0,a0,-2048 # 800 3107 | 12098: 6165 add sp,sp,112 3108 | 1209a: 8082 ret 3109 | 1209c: 00c45783 lhu a5,12(s0) 3110 | 120a0: 0807f793 and a5,a5,128 3111 | 120a4: cf91 beqz a5,120c0 <__swhatbuf_r+0x6e> 3112 | 120a6: 50b6 lw ra,108(sp) 3113 | 120a8: 5426 lw s0,104(sp) 3114 | 120aa: 4781 li a5,0 3115 | 120ac: 00f92023 sw a5,0(s2) 3116 | 120b0: 04000713 li a4,64 3117 | 120b4: c098 sw a4,0(s1) 3118 | 120b6: 5906 lw s2,96(sp) 3119 | 120b8: 5496 lw s1,100(sp) 3120 | 120ba: 4501 li a0,0 3121 | 120bc: 6165 add sp,sp,112 3122 | 120be: 8082 ret 3123 | 120c0: 50b6 lw ra,108(sp) 3124 | 120c2: 5426 lw s0,104(sp) 3125 | 120c4: 00f92023 sw a5,0(s2) 3126 | 120c8: 40000713 li a4,1024 3127 | 120cc: c098 sw a4,0(s1) 3128 | 120ce: 5906 lw s2,96(sp) 3129 | 120d0: 5496 lw s1,100(sp) 3130 | 120d2: 4501 li a0,0 3131 | 120d4: 6165 add sp,sp,112 3132 | 120d6: 8082 ret 3133 | 3134 | 000120d8 <_read_r>: 3135 | 120d8: 1141 add sp,sp,-16 3136 | 120da: 872e mv a4,a1 3137 | 120dc: c422 sw s0,8(sp) 3138 | 120de: c226 sw s1,4(sp) 3139 | 120e0: 85b2 mv a1,a2 3140 | 120e2: 842a mv s0,a0 3141 | 120e4: 8636 mv a2,a3 3142 | 120e6: 853a mv a0,a4 3143 | 120e8: c606 sw ra,12(sp) 3144 | 120ea: 0401a823 sw zero,80(gp) # 13cf0 3145 | 120ee: 2cb9 jal 1234c <_read> 3146 | 120f0: 57fd li a5,-1 3147 | 120f2: 00f50763 beq a0,a5,12100 <_read_r+0x28> 3148 | 120f6: 40b2 lw ra,12(sp) 3149 | 120f8: 4422 lw s0,8(sp) 3150 | 120fa: 4492 lw s1,4(sp) 3151 | 120fc: 0141 add sp,sp,16 3152 | 120fe: 8082 ret 3153 | 12100: 0501a783 lw a5,80(gp) # 13cf0 3154 | 12104: dbed beqz a5,120f6 <_read_r+0x1e> 3155 | 12106: 40b2 lw ra,12(sp) 3156 | 12108: c01c sw a5,0(s0) 3157 | 1210a: 4422 lw s0,8(sp) 3158 | 1210c: 4492 lw s1,4(sp) 3159 | 1210e: 0141 add sp,sp,16 3160 | 12110: 8082 ret 3161 | 3162 | 00012112 : 3163 | 12112: 1101 add sp,sp,-32 3164 | 12114: c84a sw s2,16(sp) 3165 | 12116: 0005a903 lw s2,0(a1) 3166 | 1211a: cc22 sw s0,24(sp) 3167 | 1211c: ca26 sw s1,20(sp) 3168 | 1211e: ce06 sw ra,28(sp) 3169 | 12120: c64e sw s3,12(sp) 3170 | 12122: c452 sw s4,8(sp) 3171 | 12124: 842e mv s0,a1 3172 | 12126: 84aa mv s1,a0 3173 | 12128: 02090763 beqz s2,12156 3174 | 1212c: 00092983 lw s3,0(s2) 3175 | 12130: 02098063 beqz s3,12150 3176 | 12134: 0009aa03 lw s4,0(s3) 3177 | 12138: 000a0963 beqz s4,1214a 3178 | 1213c: 000a2583 lw a1,0(s4) 3179 | 12140: c191 beqz a1,12144 3180 | 12142: 3fc1 jal 12112 3181 | 12144: 85d2 mv a1,s4 3182 | 12146: 8526 mv a0,s1 3183 | 12148: 365d jal 11cee <_free_r> 3184 | 1214a: 85ce mv a1,s3 3185 | 1214c: 8526 mv a0,s1 3186 | 1214e: 3645 jal 11cee <_free_r> 3187 | 12150: 85ca mv a1,s2 3188 | 12152: 8526 mv a0,s1 3189 | 12154: 3e69 jal 11cee <_free_r> 3190 | 12156: 85a2 mv a1,s0 3191 | 12158: 4462 lw s0,24(sp) 3192 | 1215a: 40f2 lw ra,28(sp) 3193 | 1215c: 4942 lw s2,16(sp) 3194 | 1215e: 49b2 lw s3,12(sp) 3195 | 12160: 4a22 lw s4,8(sp) 3196 | 12162: 8526 mv a0,s1 3197 | 12164: 44d2 lw s1,20(sp) 3198 | 12166: 6105 add sp,sp,32 3199 | 12168: b659 j 11cee <_free_r> 3200 | 3201 | 0001216a <_reclaim_reent>: 3202 | 1216a: 0381a783 lw a5,56(gp) # 13cd8 <_impure_ptr> 3203 | 1216e: 0aa78163 beq a5,a0,12210 <_reclaim_reent+0xa6> 3204 | 12172: 456c lw a1,76(a0) 3205 | 12174: 1101 add sp,sp,-32 3206 | 12176: ca26 sw s1,20(sp) 3207 | 12178: ce06 sw ra,28(sp) 3208 | 1217a: cc22 sw s0,24(sp) 3209 | 1217c: c84a sw s2,16(sp) 3210 | 1217e: c64e sw s3,12(sp) 3211 | 12180: 84aa mv s1,a0 3212 | 12182: c19d beqz a1,121a8 <_reclaim_reent+0x3e> 3213 | 12184: 4901 li s2,0 3214 | 12186: 08000993 li s3,128 3215 | 1218a: 012587b3 add a5,a1,s2 3216 | 1218e: 4380 lw s0,0(a5) 3217 | 12190: c419 beqz s0,1219e <_reclaim_reent+0x34> 3218 | 12192: 85a2 mv a1,s0 3219 | 12194: 4000 lw s0,0(s0) 3220 | 12196: 8526 mv a0,s1 3221 | 12198: 3e99 jal 11cee <_free_r> 3222 | 1219a: fc65 bnez s0,12192 <_reclaim_reent+0x28> 3223 | 1219c: 44ec lw a1,76(s1) 3224 | 1219e: 0911 add s2,s2,4 3225 | 121a0: ff3915e3 bne s2,s3,1218a <_reclaim_reent+0x20> 3226 | 121a4: 8526 mv a0,s1 3227 | 121a6: 36a1 jal 11cee <_free_r> 3228 | 121a8: 40ac lw a1,64(s1) 3229 | 121aa: c199 beqz a1,121b0 <_reclaim_reent+0x46> 3230 | 121ac: 8526 mv a0,s1 3231 | 121ae: 3681 jal 11cee <_free_r> 3232 | 121b0: 1484a403 lw s0,328(s1) 3233 | 121b4: cc01 beqz s0,121cc <_reclaim_reent+0x62> 3234 | 121b6: 14c48913 add s2,s1,332 3235 | 121ba: 01240963 beq s0,s2,121cc <_reclaim_reent+0x62> 3236 | 121be: 85a2 mv a1,s0 3237 | 121c0: 4000 lw s0,0(s0) 3238 | 121c2: 8526 mv a0,s1 3239 | 121c4: b2bff0ef jal 11cee <_free_r> 3240 | 121c8: fe891be3 bne s2,s0,121be <_reclaim_reent+0x54> 3241 | 121cc: 48ec lw a1,84(s1) 3242 | 121ce: c581 beqz a1,121d6 <_reclaim_reent+0x6c> 3243 | 121d0: 8526 mv a0,s1 3244 | 121d2: b1dff0ef jal 11cee <_free_r> 3245 | 121d6: 5c9c lw a5,56(s1) 3246 | 121d8: c78d beqz a5,12202 <_reclaim_reent+0x98> 3247 | 121da: 5cdc lw a5,60(s1) 3248 | 121dc: 8526 mv a0,s1 3249 | 121de: 9782 jalr a5 3250 | 121e0: 2e04a403 lw s0,736(s1) 3251 | 121e4: cc19 beqz s0,12202 <_reclaim_reent+0x98> 3252 | 121e6: 400c lw a1,0(s0) 3253 | 121e8: c199 beqz a1,121ee <_reclaim_reent+0x84> 3254 | 121ea: 8526 mv a0,s1 3255 | 121ec: 371d jal 12112 3256 | 121ee: 85a2 mv a1,s0 3257 | 121f0: 4462 lw s0,24(sp) 3258 | 121f2: 40f2 lw ra,28(sp) 3259 | 121f4: 4942 lw s2,16(sp) 3260 | 121f6: 49b2 lw s3,12(sp) 3261 | 121f8: 8526 mv a0,s1 3262 | 121fa: 44d2 lw s1,20(sp) 3263 | 121fc: 6105 add sp,sp,32 3264 | 121fe: af1ff06f j 11cee <_free_r> 3265 | 12202: 40f2 lw ra,28(sp) 3266 | 12204: 4462 lw s0,24(sp) 3267 | 12206: 44d2 lw s1,20(sp) 3268 | 12208: 4942 lw s2,16(sp) 3269 | 1220a: 49b2 lw s3,12(sp) 3270 | 1220c: 6105 add sp,sp,32 3271 | 1220e: 8082 ret 3272 | 12210: 8082 ret 3273 | 3274 | 00012212 <_fstat_r>: 3275 | 12212: 1141 add sp,sp,-16 3276 | 12214: 872e mv a4,a1 3277 | 12216: c422 sw s0,8(sp) 3278 | 12218: c226 sw s1,4(sp) 3279 | 1221a: 842a mv s0,a0 3280 | 1221c: 85b2 mv a1,a2 3281 | 1221e: 853a mv a0,a4 3282 | 12220: c606 sw ra,12(sp) 3283 | 12222: 0401a823 sw zero,80(gp) # 13cf0 3284 | 12226: 204d jal 122c8 <_fstat> 3285 | 12228: 57fd li a5,-1 3286 | 1222a: 00f50763 beq a0,a5,12238 <_fstat_r+0x26> 3287 | 1222e: 40b2 lw ra,12(sp) 3288 | 12230: 4422 lw s0,8(sp) 3289 | 12232: 4492 lw s1,4(sp) 3290 | 12234: 0141 add sp,sp,16 3291 | 12236: 8082 ret 3292 | 12238: 0501a783 lw a5,80(gp) # 13cf0 3293 | 1223c: dbed beqz a5,1222e <_fstat_r+0x1c> 3294 | 1223e: 40b2 lw ra,12(sp) 3295 | 12240: c01c sw a5,0(s0) 3296 | 12242: 4422 lw s0,8(sp) 3297 | 12244: 4492 lw s1,4(sp) 3298 | 12246: 0141 add sp,sp,16 3299 | 12248: 8082 ret 3300 | 3301 | 0001224a <_isatty_r>: 3302 | 1224a: 1141 add sp,sp,-16 3303 | 1224c: c422 sw s0,8(sp) 3304 | 1224e: c226 sw s1,4(sp) 3305 | 12250: 842a mv s0,a0 3306 | 12252: 852e mv a0,a1 3307 | 12254: c606 sw ra,12(sp) 3308 | 12256: 0401a823 sw zero,80(gp) # 13cf0 3309 | 1225a: 205d jal 12300 <_isatty> 3310 | 1225c: 57fd li a5,-1 3311 | 1225e: 00f50763 beq a0,a5,1226c <_isatty_r+0x22> 3312 | 12262: 40b2 lw ra,12(sp) 3313 | 12264: 4422 lw s0,8(sp) 3314 | 12266: 4492 lw s1,4(sp) 3315 | 12268: 0141 add sp,sp,16 3316 | 1226a: 8082 ret 3317 | 1226c: 0501a783 lw a5,80(gp) # 13cf0 3318 | 12270: dbed beqz a5,12262 <_isatty_r+0x18> 3319 | 12272: 40b2 lw ra,12(sp) 3320 | 12274: c01c sw a5,0(s0) 3321 | 12276: 4422 lw s0,8(sp) 3322 | 12278: 4492 lw s1,4(sp) 3323 | 1227a: 0141 add sp,sp,16 3324 | 1227c: 8082 ret 3325 | 3326 | 0001227e <_close>: 3327 | 1227e: 1141 add sp,sp,-16 3328 | 12280: c606 sw ra,12(sp) 3329 | 12282: c422 sw s0,8(sp) 3330 | 12284: 03900893 li a7,57 3331 | 12288: 00000073 ecall 3332 | 1228c: 842a mv s0,a0 3333 | 1228e: 00054763 bltz a0,1229c <_close+0x1e> 3334 | 12292: 40b2 lw ra,12(sp) 3335 | 12294: 8522 mv a0,s0 3336 | 12296: 4422 lw s0,8(sp) 3337 | 12298: 0141 add sp,sp,16 3338 | 1229a: 8082 ret 3339 | 1229c: 40800433 neg s0,s0 3340 | 122a0: 2ad1 jal 12474 <__errno> 3341 | 122a2: c100 sw s0,0(a0) 3342 | 122a4: 547d li s0,-1 3343 | 122a6: b7f5 j 12292 <_close+0x14> 3344 | 3345 | 000122a8 <_exit>: 3346 | 122a8: 05d00893 li a7,93 3347 | 122ac: 00000073 ecall 3348 | 122b0: 00054363 bltz a0,122b6 <_exit+0xe> 3349 | 122b4: a001 j 122b4 <_exit+0xc> 3350 | 122b6: 1141 add sp,sp,-16 3351 | 122b8: c422 sw s0,8(sp) 3352 | 122ba: 842a mv s0,a0 3353 | 122bc: c606 sw ra,12(sp) 3354 | 122be: 40800433 neg s0,s0 3355 | 122c2: 2a4d jal 12474 <__errno> 3356 | 122c4: c100 sw s0,0(a0) 3357 | 122c6: a001 j 122c6 <_exit+0x1e> 3358 | 3359 | 000122c8 <_fstat>: 3360 | 122c8: 7175 add sp,sp,-144 3361 | 122ca: c326 sw s1,132(sp) 3362 | 122cc: c706 sw ra,140(sp) 3363 | 122ce: 84ae mv s1,a1 3364 | 122d0: c522 sw s0,136(sp) 3365 | 122d2: 05000893 li a7,80 3366 | 122d6: 858a mv a1,sp 3367 | 122d8: 00000073 ecall 3368 | 122dc: 842a mv s0,a0 3369 | 122de: 00054b63 bltz a0,122f4 <_fstat+0x2c> 3370 | 122e2: 8526 mv a0,s1 3371 | 122e4: 858a mv a1,sp 3372 | 122e6: 2231 jal 123f2 <_conv_stat> 3373 | 122e8: 40ba lw ra,140(sp) 3374 | 122ea: 8522 mv a0,s0 3375 | 122ec: 442a lw s0,136(sp) 3376 | 122ee: 449a lw s1,132(sp) 3377 | 122f0: 6149 add sp,sp,144 3378 | 122f2: 8082 ret 3379 | 122f4: 40800433 neg s0,s0 3380 | 122f8: 2ab5 jal 12474 <__errno> 3381 | 122fa: c100 sw s0,0(a0) 3382 | 122fc: 547d li s0,-1 3383 | 122fe: b7d5 j 122e2 <_fstat+0x1a> 3384 | 3385 | 00012300 <_isatty>: 3386 | 12300: 7159 add sp,sp,-112 3387 | 12302: 002c add a1,sp,8 3388 | 12304: d686 sw ra,108(sp) 3389 | 12306: 37c9 jal 122c8 <_fstat> 3390 | 12308: 57fd li a5,-1 3391 | 1230a: 00f50863 beq a0,a5,1231a <_isatty+0x1a> 3392 | 1230e: 4532 lw a0,12(sp) 3393 | 12310: 50b6 lw ra,108(sp) 3394 | 12312: 8135 srl a0,a0,0xd 3395 | 12314: 8905 and a0,a0,1 3396 | 12316: 6165 add sp,sp,112 3397 | 12318: 8082 ret 3398 | 1231a: 50b6 lw ra,108(sp) 3399 | 1231c: 4501 li a0,0 3400 | 1231e: 6165 add sp,sp,112 3401 | 12320: 8082 ret 3402 | 3403 | 00012322 <_lseek>: 3404 | 12322: 1141 add sp,sp,-16 3405 | 12324: c606 sw ra,12(sp) 3406 | 12326: c422 sw s0,8(sp) 3407 | 12328: 03e00893 li a7,62 3408 | 1232c: 00000073 ecall 3409 | 12330: 842a mv s0,a0 3410 | 12332: 00054763 bltz a0,12340 <_lseek+0x1e> 3411 | 12336: 40b2 lw ra,12(sp) 3412 | 12338: 8522 mv a0,s0 3413 | 1233a: 4422 lw s0,8(sp) 3414 | 1233c: 0141 add sp,sp,16 3415 | 1233e: 8082 ret 3416 | 12340: 40800433 neg s0,s0 3417 | 12344: 2a05 jal 12474 <__errno> 3418 | 12346: c100 sw s0,0(a0) 3419 | 12348: 547d li s0,-1 3420 | 1234a: b7f5 j 12336 <_lseek+0x14> 3421 | 3422 | 0001234c <_read>: 3423 | 1234c: 1141 add sp,sp,-16 3424 | 1234e: c606 sw ra,12(sp) 3425 | 12350: c422 sw s0,8(sp) 3426 | 12352: 03f00893 li a7,63 3427 | 12356: 00000073 ecall 3428 | 1235a: 842a mv s0,a0 3429 | 1235c: 00054763 bltz a0,1236a <_read+0x1e> 3430 | 12360: 40b2 lw ra,12(sp) 3431 | 12362: 8522 mv a0,s0 3432 | 12364: 4422 lw s0,8(sp) 3433 | 12366: 0141 add sp,sp,16 3434 | 12368: 8082 ret 3435 | 1236a: 40800433 neg s0,s0 3436 | 1236e: 2219 jal 12474 <__errno> 3437 | 12370: c100 sw s0,0(a0) 3438 | 12372: 547d li s0,-1 3439 | 12374: b7f5 j 12360 <_read+0x14> 3440 | 3441 | 00012376 <_sbrk>: 3442 | 12376: 0541a703 lw a4,84(gp) # 13cf4 3443 | 1237a: 1141 add sp,sp,-16 3444 | 1237c: c606 sw ra,12(sp) 3445 | 1237e: 87aa mv a5,a0 3446 | 12380: ef01 bnez a4,12398 <_sbrk+0x22> 3447 | 12382: 0d600893 li a7,214 3448 | 12386: 4501 li a0,0 3449 | 12388: 00000073 ecall 3450 | 1238c: 567d li a2,-1 3451 | 1238e: 872a mv a4,a0 3452 | 12390: 02c50563 beq a0,a2,123ba <_sbrk+0x44> 3453 | 12394: 04a1aa23 sw a0,84(gp) # 13cf4 3454 | 12398: 0d600893 li a7,214 3455 | 1239c: 00e78533 add a0,a5,a4 3456 | 123a0: 00000073 ecall 3457 | 123a4: 0541a703 lw a4,84(gp) # 13cf4 3458 | 123a8: 97ba add a5,a5,a4 3459 | 123aa: 00f51863 bne a0,a5,123ba <_sbrk+0x44> 3460 | 123ae: 40b2 lw ra,12(sp) 3461 | 123b0: 04a1aa23 sw a0,84(gp) # 13cf4 3462 | 123b4: 853a mv a0,a4 3463 | 123b6: 0141 add sp,sp,16 3464 | 123b8: 8082 ret 3465 | 123ba: 286d jal 12474 <__errno> 3466 | 123bc: 40b2 lw ra,12(sp) 3467 | 123be: 47b1 li a5,12 3468 | 123c0: c11c sw a5,0(a0) 3469 | 123c2: 557d li a0,-1 3470 | 123c4: 0141 add sp,sp,16 3471 | 123c6: 8082 ret 3472 | 3473 | 000123c8 <_write>: 3474 | 123c8: 1141 add sp,sp,-16 3475 | 123ca: c606 sw ra,12(sp) 3476 | 123cc: c422 sw s0,8(sp) 3477 | 123ce: 04000893 li a7,64 3478 | 123d2: 00000073 ecall 3479 | 123d6: 842a mv s0,a0 3480 | 123d8: 00054763 bltz a0,123e6 <_write+0x1e> 3481 | 123dc: 40b2 lw ra,12(sp) 3482 | 123de: 8522 mv a0,s0 3483 | 123e0: 4422 lw s0,8(sp) 3484 | 123e2: 0141 add sp,sp,16 3485 | 123e4: 8082 ret 3486 | 123e6: 40800433 neg s0,s0 3487 | 123ea: 2069 jal 12474 <__errno> 3488 | 123ec: c100 sw s0,0(a0) 3489 | 123ee: 547d li s0,-1 3490 | 123f0: b7f5 j 123dc <_write+0x14> 3491 | 3492 | 000123f2 <_conv_stat>: 3493 | 123f2: 0185d703 lhu a4,24(a1) 3494 | 123f6: 0145d783 lhu a5,20(a1) 3495 | 123fa: 1141 add sp,sp,-16 3496 | 123fc: 01c5a283 lw t0,28(a1) 3497 | 12400: 0205af83 lw t6,32(a1) 3498 | 12404: 0305af03 lw t5,48(a1) 3499 | 12408: 0405ae83 lw t4,64(a1) 3500 | 1240c: 0385ae03 lw t3,56(a1) 3501 | 12410: 0485a303 lw t1,72(a1) 3502 | 12414: 04c5a383 lw t2,76(a1) 3503 | 12418: 0585a803 lw a6,88(a1) 3504 | 1241c: 05c5a883 lw a7,92(a1) 3505 | 12420: c622 sw s0,12(sp) 3506 | 12422: c426 sw s1,8(sp) 3507 | 12424: 4980 lw s0,16(a1) 3508 | 12426: 4584 lw s1,8(a1) 3509 | 12428: c24a sw s2,4(sp) 3510 | 1242a: 0005a903 lw s2,0(a1) 3511 | 1242e: 55b0 lw a2,104(a1) 3512 | 12430: 0742 sll a4,a4,0x10 3513 | 12432: 8fd9 or a5,a5,a4 3514 | 12434: 55f4 lw a3,108(a1) 3515 | 12436: 01251023 sh s2,0(a0) 3516 | 1243a: 00951123 sh s1,2(a0) 3517 | 1243e: c140 sw s0,4(a0) 3518 | 12440: c51c sw a5,8(a0) 3519 | 12442: 00551623 sh t0,12(a0) 3520 | 12446: 01f51723 sh t6,14(a0) 3521 | 1244a: 01e52823 sw t5,16(a0) 3522 | 1244e: 05d52623 sw t4,76(a0) 3523 | 12452: 05c52423 sw t3,72(a0) 3524 | 12456: 00652c23 sw t1,24(a0) 3525 | 1245a: 00752e23 sw t2,28(a0) 3526 | 1245e: 03052423 sw a6,40(a0) 3527 | 12462: 03152623 sw a7,44(a0) 3528 | 12466: dd10 sw a2,56(a0) 3529 | 12468: 4432 lw s0,12(sp) 3530 | 1246a: dd54 sw a3,60(a0) 3531 | 1246c: 44a2 lw s1,8(sp) 3532 | 1246e: 4912 lw s2,4(sp) 3533 | 12470: 0141 add sp,sp,16 3534 | 12472: 8082 ret 3535 | 3536 | 00012474 <__errno>: 3537 | 12474: 0381a503 lw a0,56(gp) # 13cd8 <_impure_ptr> 3538 | 12478: 8082 ret 3539 | -------------------------------------------------------------------------------- /lab-6/task-2/acc-dump.s: -------------------------------------------------------------------------------- 1 | 2 | acc.o: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text: 6 | 7 | 00000000
: 8 | 0: 000002b3 add t0,zero,zero 9 | 4: 00000333 add t1,zero,zero 10 | 8: 00a00393 li t2,10 11 | 12 | 0000000c : 13 | c: 04032e03 lw t3,64(t1) 14 | 10: 01c282b3 add t0,t0,t3 15 | 14: 00430313 add t1,t1,4 16 | 18: fff38393 add t2,t2,-1 17 | 1c: 00038463 beqz t2,24 18 | 20: fedff06f j c 19 | 20 | 00000024 : 21 | 24: 08502023 sw t0,128(zero) # 80 22 | -------------------------------------------------------------------------------- /lab-6/task-2/acc.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-6/task-2/acc.o -------------------------------------------------------------------------------- /lab-6/task-2/acc.s: -------------------------------------------------------------------------------- 1 | main: 2 | add t0,x0, x0 3 | add t1,x0, x0 4 | addi t2,x0, 10 5 | 6 | L1: 7 | lw t3,0x40(t1) 8 | add t0,t0,t3 9 | addi t1,t1,4 10 | addi t2,t2,-1 11 | beq t2,x0,L2 12 | j L1 13 | 14 | L2: 15 | sw t0, 0x80(x0) 16 | -------------------------------------------------------------------------------- /lab-6/task-3/move-dump.s: -------------------------------------------------------------------------------- 1 | 2 | move.o: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text: 6 | 7 | 00000000 : 8 | 0: 000502b3 add t0,a0,zero 9 | 4: 00058333 add t1,a1,zero 10 | 8: 000603b3 add t2,a2,zero 11 | 12 | 0000000c : 13 | c: 0002ae03 lw t3,0(t0) 14 | 10: 01c32023 sw t3,0(t1) 15 | 14: 00428293 add t0,t0,4 16 | 18: 00430313 add t1,t1,4 17 | 1c: fff38393 add t2,t2,-1 18 | 20: fe0396e3 bnez t2,c 19 | 24: 00008067 ret 20 | 21 | 00000028
: 22 | 28: 03000513 li a0,48 23 | 2c: 06000593 li a1,96 24 | 30: 00a00613 li a2,10 25 | 34: fcdff0ef jal 0 26 | -------------------------------------------------------------------------------- /lab-6/task-3/move.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-6/task-3/move.o -------------------------------------------------------------------------------- /lab-6/task-3/move.s: -------------------------------------------------------------------------------- 1 | BankMove: 2 | add t0,a0,zero; 3 | add t1,a1,zero; 4 | add t2,a2,zero; 5 | L1: lw t3,0(t0); 6 | sw t3,0(t1); 7 | addi t0,t0,4; 8 | addi t1,t1,4; 9 | addi t2,t2,-1; 10 | bne t2,zero,L1; 11 | jr ra 12 | main: 13 | addi a0,zero,0x30; 14 | addi a1,zero,0x60; 15 | addi a2,zero,10; 16 | jal BankMove 17 | -------------------------------------------------------------------------------- /lab-6/task-4/sum-self.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-6/task-4/sum-self.o -------------------------------------------------------------------------------- /lab-6/task-4/sum-self.s: -------------------------------------------------------------------------------- 1 | sum: 2 | addi a0, x0, 0 3 | addi a1, x0, 0 4 | loop: 5 | addi a0, a0, 1 6 | add a1, a1, a0 7 | bne a0, t0, loop 8 | jr ra 9 | main: 10 | addi t0, x0, 100 11 | jal sum 12 | add t1,x0, a1 13 | jr ra 14 | -------------------------------------------------------------------------------- /lab-6/task-4/sum.c: -------------------------------------------------------------------------------- 1 | int sum(int n){ 2 | int i,s = 0; 3 | for(int i = 0 ; i <= n ; i++){ 4 | s += i; 5 | } 6 | } 7 | 8 | int main(){ 9 | int x = 100; 10 | int y = sum(x); 11 | return 0; 12 | } 13 | -------------------------------------------------------------------------------- /lab-6/task-4/sum.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-6/task-4/sum.o -------------------------------------------------------------------------------- /lab-6/task-4/sum.s: -------------------------------------------------------------------------------- 1 | .file "sum.c" 2 | .option nopic 3 | .attribute arch, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0" 4 | .attribute unaligned_access, 0 5 | .attribute stack_align, 16 6 | .text 7 | .align 1 8 | .globl sum 9 | .type sum, @function 10 | sum: 11 | addi sp,sp,-48 12 | sw s0,44(sp) 13 | addi s0,sp,48 14 | sw a0,-36(s0) 15 | sw zero,-20(s0) 16 | sw zero,-24(s0) 17 | j .L2 18 | .L3: 19 | lw a4,-20(s0) 20 | lw a5,-24(s0) 21 | add a5,a4,a5 22 | sw a5,-20(s0) 23 | lw a5,-24(s0) 24 | addi a5,a5,1 25 | sw a5,-24(s0) 26 | .L2: 27 | lw a4,-24(s0) 28 | lw a5,-36(s0) 29 | ble a4,a5,.L3 30 | nop 31 | mv a0,a5 32 | lw s0,44(sp) 33 | addi sp,sp,48 34 | jr ra 35 | .size sum, .-sum 36 | .align 1 37 | .globl main 38 | .type main, @function 39 | main: 40 | addi sp,sp,-32 41 | sw ra,28(sp) 42 | sw s0,24(sp) 43 | addi s0,sp,32 44 | li a5,100 45 | sw a5,-20(s0) 46 | lw a0,-20(s0) 47 | call sum 48 | sw a0,-24(s0) 49 | li a5,0 50 | mv a0,a5 51 | lw ra,28(sp) 52 | lw s0,24(sp) 53 | addi sp,sp,32 54 | jr ra 55 | .size main, .-main 56 | .ident "GCC: (g2ee5e430018) 12.2.0" 57 | -------------------------------------------------------------------------------- /lab-7/decoder_top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/05/05 09:36:58 7 | // Design Name: 8 | // Module Name: decoder_top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module decoder_top( 24 | input PC_Write, 25 | input IR_Write, 26 | input clk_im, 27 | output [31:0] imm32, 28 | output [4:0] rs1, 29 | output [4:0] rs2, 30 | output [4:0] rd, 31 | output [6:0] opcode, 32 | output [2:0] funct3, 33 | output [6:0] funct7, 34 | 35 | output [31:0] debug 36 | ); 37 | 38 | wire [31:0] inst_Code; 39 | wire [31:0] instr; 40 | wire [31:0] pc; 41 | wire [31:0] new_pc; 42 | wire [5:0] addr; 43 | 44 | assign debug = inst_Code; 45 | 46 | 47 | adder addr_module( 48 | .pc(pc), 49 | .new_pc(new_pc) 50 | ); 51 | 52 | pc_reg pc_module( 53 | .PC_Write(PC_Write), 54 | .clk_im(clk_im), 55 | .now_pc(pc), 56 | .new_pc(new_pc), 57 | .addr(addr) 58 | ); 59 | 60 | RAM_B memory ( 61 | .clka(clk_im), // input wire clka 62 | .wea(0), // input wire [0 : 0] wea 63 | .addra(addr), // input wire [5 : 0] addra 64 | .dina(0), // input wire [31 : 0] dina 65 | .douta(inst_Code) // output wire [31 : 0] douta 66 | ); 67 | 68 | IR ir( 69 | .IR_Write(IR_Write), 70 | .clk_im(clk_im), 71 | .Inst_Code(inst_Code), 72 | .instr(instr) 73 | ); 74 | 75 | ID1 id1( 76 | .instr(instr), 77 | .rs1(rs1), 78 | .rs2(rs2), 79 | .rd(rd), 80 | .opcode(opcode), 81 | .funct3(funct3), 82 | .funct7(funct7), 83 | .imm(imm32) 84 | ); 85 | 86 | endmodule 87 | 88 | module IR( 89 | input IR_Write, 90 | input clk_im, 91 | input [31:0] Inst_Code, 92 | output [31:0] instr 93 | ); 94 | 95 | reg [31:0] ir; 96 | always@(negedge clk_im)begin 97 | if(IR_Write)ir = Inst_Code; 98 | end 99 | assign instr = ir; 100 | endmodule 101 | 102 | module adder( 103 | input [31:0] pc, 104 | output [31:0] new_pc 105 | ); 106 | reg [31:0] A = 0; 107 | always@(*)begin 108 | A = pc + 4; 109 | end 110 | assign new_pc = A; 111 | 112 | endmodule 113 | 114 | module pc_reg( 115 | input PC_Write, 116 | input clk_im, 117 | input [31:0] new_pc, 118 | output [31:0]now_pc, 119 | output [5:0] addr 120 | ); 121 | 122 | reg [31:0] pc = 0; 123 | 124 | always@(negedge clk_im)begin 125 | if(PC_Write)pc = new_pc; 126 | end 127 | assign now_pc = pc; 128 | assign addr = pc[7:2]; 129 | endmodule 130 | 131 | module ID1 ( 132 | input [31:0] instr, 133 | 134 | output [4:0] rs1, 135 | output [4:0] rs2, 136 | output [4:0] rd, 137 | output [6:0] opcode, 138 | output [2:0] funct3, 139 | output [6:0] funct7, 140 | 141 | output reg [31:0] imm 142 | ); 143 | 144 | assign rs1 = instr[19:15]; 145 | assign rs2 = instr[24:20]; 146 | assign rd = instr[11:7]; 147 | assign funct7 = instr[31:25]; 148 | assign funct3 = instr[14:12]; 149 | assign opcode = instr[6:0]; 150 | 151 | 152 | wire [31:0] I1imm = {27'b0,instr[24:20]}; 153 | wire [31:0] I2imm = {{21{instr[31]}}, instr[30:20]}; 154 | wire [31:0] Simm = {{21{instr[31]}}, instr[30:25], instr[11:7]}; 155 | wire [31:0] Bimm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; 156 | wire [31:0] Uimm = {instr[31:12], 12'b0}; 157 | wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; 158 | reg flag; 159 | initial flag = 0; 160 | always @(*)begin 161 | case(opcode) 162 | 7'b1101111: imm = Jimm; 163 | 7'b0110011: imm = 0; 164 | 7'b0010011: flag = 1; 165 | 7'b0000011: imm = I2imm; 166 | 7'b1100111: imm = I2imm; 167 | 7'b0100011: imm = Simm; 168 | 7'b1100011: imm = Bimm; 169 | 7'b0110111: imm = Uimm; 170 | 7'b0010111: imm = Uimm; 171 | endcase 172 | if(flag)begin 173 | case(funct3) 174 | 3'b001: imm = I1imm; 175 | 3'b101: imm = I1imm; 176 | default: imm = I2imm; 177 | endcase 178 | flag = 0; 179 | end 180 | end 181 | 182 | endmodule -------------------------------------------------------------------------------- /lab-7/simu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/05/05 18:30:41 7 | // Design Name: 8 | // Module Name: simu 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module simu(); 24 | reg PC_Write; 25 | reg IR_Write; 26 | reg clk_im; 27 | wire [31:0] imm32; 28 | wire [4:0] rs1; 29 | wire [4:0] rs2; 30 | wire [4:0] rd; 31 | wire [6:0] opcode; 32 | wire [2:0] funct3; 33 | wire [6:0] funct7; 34 | wire [31:0] debug; 35 | 36 | decoder_top uut( 37 | PC_Write, 38 | IR_Write, 39 | clk_im, 40 | imm32, 41 | rs1, 42 | rs2, 43 | rd, 44 | opcode, 45 | funct3, 46 | funct7, 47 | debug 48 | ); 49 | 50 | initial begin 51 | PC_Write = 1; 52 | IR_Write = 1; 53 | clk_im = 0; 54 | end 55 | 56 | always #40 begin 57 | clk_im = ~clk_im; 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /lab-8/code/alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-8/code/alu.v -------------------------------------------------------------------------------- /lab-8/code/decoder_top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/05/12 11:16:10 7 | // Design Name: 8 | // Module Name: decoder_top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module decoder_top( 24 | input PC_Write, 25 | input IR_Write, 26 | input clk_im, 27 | output [31:0] imm32, 28 | output [4:0] rs1, 29 | output [4:0] rs2, 30 | output [4:0] rd, 31 | output [6:0] opcode, 32 | output [2:0] funct3, 33 | output [6:0] funct7, 34 | output [31:0] PC, 35 | output [31:0] inst 36 | // output [31:0] debug 37 | ); 38 | 39 | wire [31:0] inst_Code; 40 | wire [31:0] instr; 41 | wire [31:0] pc; 42 | wire [31:0] new_pc; 43 | wire [5:0] addr; 44 | assign PC = pc; 45 | assign inst = instr; 46 | 47 | // assign debug = inst_Code; 48 | 49 | 50 | adder addr_module( 51 | .pc(pc), 52 | .new_pc(new_pc) 53 | ); 54 | 55 | pc_reg pc_module( 56 | .PC_Write(PC_Write), 57 | .clk_im(clk_im), 58 | .now_pc(pc), 59 | .new_pc(new_pc), 60 | .addr(addr) 61 | ); 62 | 63 | RAM_B memory ( 64 | .clka(clk_im), // input wire clka 65 | .wea(0), // input wire [0 : 0] wea 66 | .addra(addr), // input wire [5 : 0] addra 67 | .dina(0), // input wire [31 : 0] dina 68 | .douta(inst_Code) // output wire [31 : 0] douta 69 | ); 70 | 71 | IR ir( 72 | .IR_Write(IR_Write), 73 | .clk_im(clk_im), 74 | .Inst_Code(inst_Code), 75 | .instr(instr) 76 | ); 77 | 78 | ID1 id1( 79 | .instr(instr), 80 | .rs1(rs1), 81 | .rs2(rs2), 82 | .rd(rd), 83 | .opcode(opcode), 84 | .funct3(funct3), 85 | .funct7(funct7), 86 | .imm(imm32) 87 | ); 88 | 89 | endmodule 90 | 91 | module IR( 92 | input IR_Write, 93 | input clk_im, 94 | input [31:0] Inst_Code, 95 | output [31:0] instr 96 | ); 97 | 98 | reg [31:0] ir; 99 | always@(negedge clk_im)begin 100 | if(IR_Write)ir = Inst_Code; 101 | end 102 | assign instr = ir; 103 | endmodule 104 | 105 | module adder( 106 | input [31:0] pc, 107 | output [31:0] new_pc 108 | ); 109 | reg [31:0] A = 0; 110 | always@(*)begin 111 | A = pc + 4; 112 | end 113 | assign new_pc = A; 114 | 115 | endmodule 116 | 117 | module pc_reg( 118 | input PC_Write, 119 | input clk_im, 120 | input [31:0] new_pc, 121 | output [31:0]now_pc, 122 | output [5:0] addr 123 | ); 124 | 125 | reg [31:0] pc = 0; 126 | 127 | always@(negedge clk_im)begin 128 | if(PC_Write)pc = new_pc; 129 | end 130 | assign now_pc = pc; 131 | assign addr = pc[7:2]; 132 | endmodule 133 | 134 | module ID1 ( 135 | input [31:0] instr, 136 | 137 | output [4:0] rs1, 138 | output [4:0] rs2, 139 | output [4:0] rd, 140 | output [6:0] opcode, 141 | output [2:0] funct3, 142 | output [6:0] funct7, 143 | 144 | output reg [31:0] imm 145 | ); 146 | 147 | assign rs1 = instr[19:15]; 148 | assign rs2 = instr[24:20]; 149 | assign rd = instr[11:7]; 150 | assign funct7 = instr[31:25]; 151 | assign funct3 = instr[14:12]; 152 | assign opcode = instr[6:0]; 153 | 154 | 155 | wire [31:0] I1imm = {27'b0,instr[24:20]}; 156 | wire [31:0] I2imm = {{21{instr[31]}}, instr[30:20]}; 157 | wire [31:0] Simm = {{21{instr[31]}}, instr[30:25], instr[11:7]}; 158 | wire [31:0] Bimm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; 159 | wire [31:0] Uimm = {instr[31:12], 12'b0}; 160 | wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; 161 | reg flag; 162 | initial flag = 0; 163 | always @(*)begin 164 | case(opcode) 165 | 7'b1101111: imm = Jimm; 166 | 7'b0110011: imm = 0; 167 | 7'b0010011: flag = 1; 168 | 7'b0000011: imm = I2imm; 169 | 7'b1100111: imm = I2imm; 170 | 7'b0100011: imm = Simm; 171 | 7'b1100011: imm = Bimm; 172 | 7'b0110111: imm = Uimm; 173 | 7'b0010111: imm = Uimm; 174 | endcase 175 | if(flag)begin 176 | case(funct3) 177 | 3'b001: imm = I1imm; 178 | 3'b101: imm = I1imm; 179 | default: imm = I2imm; 180 | endcase 181 | flag = 0; 182 | end 183 | end 184 | 185 | endmodule 186 | -------------------------------------------------------------------------------- /lab-8/code/memory.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/05/12 11:18:03 7 | // Design Name: 8 | // Module Name: memory 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module memory( 24 | input Mem_Write, 25 | input clk_dm, 26 | input [7:2] DM_Addr, 27 | input [1:0] MW_Data_s, 28 | output reg [31:0] M_R_Data 29 | ); 30 | 31 | parameter [7:0] data1 = 8'h12; 32 | reg [31:0] M_W_Data; 33 | wire [31:0] temp_R_Data; 34 | RAM_B ram ( 35 | .clka(clk_dm), // input wire clka 36 | .wea(Mem_Write), // input wire [0 : 0] wea 37 | .addra(DM_Addr[7:2]), // input wire [5 : 0] addra 38 | .dina(M_W_Data), // input wire [31 : 0] dina 39 | .douta(temp_R_Data) // output wire [31 : 0] douta 40 | ); 41 | always@(*)begin 42 | if(Mem_Write)begin 43 | case(MW_Data_s) 44 | 2'b00: M_W_Data = {24'b0,data1}; 45 | 2'b01: M_W_Data = {16'b0,data1,8'b0}; 46 | 2'b10: M_W_Data = {8'b0,data1,16'b0}; 47 | 3'b11: M_W_Data = {data1,24'b0}; 48 | endcase 49 | end 50 | else begin 51 | M_R_Data = temp_R_Data; 52 | end 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /lab-8/code/register.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/05/12 11:26:18 7 | // Design Name: 8 | // Module Name: register 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module register_heap( 23 | input Reg_Write, 24 | input clk_Regs, 25 | input rst_n, 26 | input [4:0] R_Addr_A, 27 | input [4:0] R_Addr_B, 28 | input [4:0] W_Addr, 29 | input [31:0] W_Data, 30 | output [31:0] R_Data_A, 31 | output [31:0] R_Data_B 32 | ); 33 | integer i; 34 | reg [31:0] REG_Files[0:31]; 35 | assign R_Data_A = REG_Files[R_Addr_A]; 36 | assign R_Data_B = REG_Files[R_Addr_B]; 37 | always @(negedge clk_Regs or negedge rst_n)begin 38 | if(!rst_n) begin 39 | for(i = 0 ; i < 32 ;i = i + 1)REG_Files[i] <= 0; 40 | end 41 | else begin 42 | if(Reg_Write && W_Addr != 0) 43 | REG_Files[W_Addr] <= W_Data; 44 | end 45 | end 46 | endmodule 47 | 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /lab-8/code/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-8/code/top.v -------------------------------------------------------------------------------- /lab-8/main-dump.S: -------------------------------------------------------------------------------- 1 | 2 | main.o: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text: 6 | 7 | 00000000 <.text>: 8 | 0: 00230293 add t0,t1,2 9 | 4: 01000337 lui t1,0x1000 10 | 8: 005302b3 add t0,t1,t0 11 | c: 001e0e13 add t3,t3,1 12 | 10: 41c282b3 sub t0,t0,t3 13 | -------------------------------------------------------------------------------- /lab-8/main-dump.txt: -------------------------------------------------------------------------------- 1 | 2 | main.o: file format elf32-littleriscv 3 | 4 | Contents of section .text: 5 | 0000 93022300 37030001 b3025300 130e1e00 ..#.7.....S..... 6 | 0010 b382c241 ...A 7 | Contents of section .riscv.attributes: 8 | 0000 412c0000 00726973 63760001 22000000 A,...riscv.."... 9 | 0010 05727633 32693270 315f6632 70325f64 .rv32i2p1_f2p2_d 10 | 0020 3270325f 7a696373 72327030 00 2p2_zicsr2p0. 11 | -------------------------------------------------------------------------------- /lab-8/main.S: -------------------------------------------------------------------------------- 1 | addi t0,t1,2 2 | lui t1,0x1000 3 | add t0,t1,t0 4 | addi t3,t3,1 5 | sub t0,t0,t3 -------------------------------------------------------------------------------- /lab-8/main.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jking412/hdu-riscv32/999128bd4b0d63f5a99bb850a0ee442e47d48ba8/lab-8/main.o --------------------------------------------------------------------------------