├── 1_VerilogSourceCode ├── 1_CPUCore_src │ ├── ALU.v │ ├── BRAMModule │ │ ├── DataRam.v │ │ └── InstructionRam.v │ ├── BranchDecisionMaking.v │ ├── ControlUnit.v │ ├── DataExt.v │ ├── EXSegReg.v │ ├── HarzardUnit.v │ ├── IDSegReg.v │ ├── IFSegReg.v │ ├── ImmOperandUnit.v │ ├── MEMSegReg.v │ ├── NPC_Generator.v │ ├── Parameters.v │ ├── RV32Core.v │ ├── RegisterFile.v │ └── WBSegReg.v └── 2_Simulation │ └── testBench.v ├── 2_BRAMInputFileGenerator ├── ExampleCode │ ├── ASMCode │ │ ├── Fibonacci.S │ │ ├── Number2Ascii.S │ │ └── QuickSort.S │ └── RISCVTest_rv32ui │ │ ├── 1testAll.S │ │ ├── 2testAll.S │ │ ├── 3testAll.S │ │ ├── add.S │ │ ├── addi.S │ │ ├── and.S │ │ ├── andi.S │ │ ├── auipc.S │ │ ├── beq.S │ │ ├── bge.S │ │ ├── bgeu.S │ │ ├── blt.S │ │ ├── bltu.S │ │ ├── bne.S │ │ ├── fence_i.S │ │ ├── include │ │ ├── encoding.h │ │ ├── riscv_test.h │ │ └── test_macros.h │ │ ├── jal.S │ │ ├── jalr.S │ │ ├── lb.S │ │ ├── lbu.S │ │ ├── lh.S │ │ ├── lhu.S │ │ ├── lui.S │ │ ├── lw.S │ │ ├── or.S │ │ ├── ori.S │ │ ├── sb.S │ │ ├── sh.S │ │ ├── simple.S │ │ ├── sll.S │ │ ├── slli.S │ │ ├── slt.S │ │ ├── slti.S │ │ ├── sltiu.S │ │ ├── sltu.S │ │ ├── sra.S │ │ ├── srai.S │ │ ├── srl.S │ │ ├── srli.S │ │ ├── sub.S │ │ ├── sw.S │ │ ├── xor.S │ │ └── xori.S ├── Makefile └── Utils │ └── Bin2Data.c ├── 4_ProjectDesignFiles └── CPU设计图.pdf ├── 5_DetailDocuments ├── Lab1-CPU设计报告.docx ├── Lab1-CPU设计报告.pdf ├── Lab2-CPU代码实现验收标准和实验报告要求.docx ├── Lab2-CPU代码实现验收标准和实验报告要求.pdf ├── 夏昊珺-Lab1总结和Lab2讲解.pptx └── 资料 │ ├── RISC-V 指令集卷1-用户级指令-中文版.pdf │ ├── RISC-V 指令集卷2-特权级指令-中文版.pdf │ ├── RISCV指令集总览表格.pdf │ ├── The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf │ └── The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf ├── LICENSE └── README.md /1_VerilogSourceCode/1_CPUCore_src/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: ALU 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: ALU unit of RISCV CPU 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `include "Parameters.v" 13 | module ALU( 14 | input wire [31:0] Operand1, 15 | input wire [31:0] Operand2, 16 | input wire [3:0] AluContrl, 17 | output reg [31:0] AluOut 18 | ); 19 | endmodule 20 | 21 | //功能和接口说明 22 | //ALU接受两个操作数，根据AluContrl的不同，进行不同的计算操作，将计算结果输出到AluOut 23 | //AluContrl的类型定义在Parameters.v中 24 | //推荐格式： 25 | //case() 26 | // `ADD: AluOut<=Operand1 + Operand2; 27 | // ....... 28 | // default: AluOut <= 32'hxxxxxxxx; 29 | //endcase 30 | //实验要求 31 | //实现ALU模块 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/BRAMModule/DataRam.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB 4 | // Engineer: Xuan Wang (wgg@mail.ustc.edu.cn) 5 | // 6 | // Create Date: 2019/02/08 16:29:41 7 | // Design Name: RISCV-Pipline CPU 8 | // Module Name: InstructionRamWrapper 9 | // Target Devices: Nexys4 10 | // Tool Versions: Vivado 2017.4.1 11 | // Description: a Verilog-based ram which can be systhesis as BRAM 12 | // 13 | ////////////////////////////////////////////////////////////////////////////////// 14 | module DataRam( 15 | input clk, 16 | input [ 3:0] wea, web, 17 | input [31:2] addra, addrb, 18 | input [31:0] dina , dinb, 19 | output reg [31:0] douta, doutb 20 | ); 21 | initial begin douta=0; doutb=0; end 22 | 23 | wire addra_valid = ( addra[31:14]==18'h0 ); 24 | wire addrb_valid = ( addrb[31:14]==18'h0 ); 25 | wire [11:0] addral = addra[13:2]; 26 | wire [11:0] addrbl = addrb[13:2]; 27 | 28 | reg [31:0] ram_cell [0:4095]; 29 | 30 | initial begin // add simulation data here 31 | ram_cell[0] = 32'h00000000; 32 | // ...... 33 | end 34 | 35 | always @ (posedge clk) 36 | douta <= addra_valid ? ram_cell[addral] : 0; 37 | 38 | always @ (posedge clk) 39 | doutb <= addrb_valid ? ram_cell[addrbl] : 0; 40 | 41 | always @ (posedge clk) 42 | if(wea[0] & addra_valid) 43 | ram_cell[addral][ 7: 0] <= dina[ 7: 0]; 44 | 45 | always @ (posedge clk) 46 | if(wea[1] & addra_valid) 47 | ram_cell[addral][15: 8] <= dina[15: 8]; 48 | 49 | always @ (posedge clk) 50 | if(wea[2] & addra_valid) 51 | ram_cell[addral][23:16] <= dina[23:16]; 52 | 53 | always @ (posedge clk) 54 | if(wea[3] & addra_valid) 55 | ram_cell[addral][31:24] <= dina[31:24]; 56 | 57 | always @ (posedge clk) 58 | if(web[0] & addrb_valid) 59 | ram_cell[addrbl][ 7: 0] <= dinb[ 7: 0]; 60 | 61 | always @ (posedge clk) 62 | if(web[1] & addrb_valid) 63 | ram_cell[addrbl][15: 8] <= dinb[15: 8]; 64 | 65 | always @ (posedge clk) 66 | if(web[2] & addrb_valid) 67 | ram_cell[addrbl][23:16] <= dinb[23:16]; 68 | 69 | always @ (posedge clk) 70 | if(web[3] & addrb_valid) 71 | ram_cell[addrbl][31:24] <= dinb[31:24]; 72 | 73 | endmodule 74 | input clk, 75 | input [ 3:0] wea, web, 76 | input [31:2] addra, addrb, 77 | input [31:0] dina , dinb, 78 | output reg [31:0] douta, doutb 79 | //功能说明 80 | //同步读写bram，a、b双口可读写，a口用于CPU访问dataRam，b口用于外接debug_module进行读写 81 | //写使能为4bit，支持byte write 82 | //输入 83 | //clk 输入时钟 84 | //addra a口读写地址 85 | //dina a口写输入数据 86 | //wea a口写使能 87 | //addrb b口读写地址 88 | //dinb b口写输入数据 89 | //web b口写使能 90 | //输出 91 | //douta a口读数据 92 | //doutb b口读数据 93 | //实验要求 94 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/BRAMModule/InstructionRam.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB 4 | // Engineer: Xuan Wang (wgg@mail.ustc.edu.cn) 5 | // 6 | // Create Date: 2019/02/08 16:29:41 7 | // Design Name: RISCV-Pipline CPU 8 | // Module Name: InstructionRamWrapper 9 | // Target Devices: Nexys4 10 | // Tool Versions: Vivado 2017.4.1 11 | // Description: a Verilog-based ram which can be systhesis as BRAM 12 | // 13 | ////////////////////////////////////////////////////////////////////////////////// 14 | module InstructionRam( 15 | input clk, 16 | input web, 17 | input [31:2] addra, addrb, 18 | input [31:0] dinb, 19 | output reg [31:0] douta, doutb 20 | ); 21 | initial begin douta=0; doutb=0; end 22 | 23 | wire addra_valid = ( addra[31:14]==18'h0 ); 24 | wire addrb_valid = ( addrb[31:14]==18'h0 ); 25 | wire [11:0] addral = addra[13:2]; 26 | wire [11:0] addrbl = addrb[13:2]; 27 | 28 | reg [31:0] ram_cell [0:4095]; 29 | 30 | initial begin // you can add simulation instructions here 31 | ram_cell[0] = 32'h00000000; 32 | // ...... 33 | end 34 | 35 | always @ (posedge clk) 36 | douta <= addra_valid ? ram_cell[addral] : 0; 37 | 38 | always @ (posedge clk) 39 | doutb <= addrb_valid ? ram_cell[addrbl] : 0; 40 | 41 | always @ (posedge clk) 42 | if(web & addrb_valid) 43 | ram_cell[addrbl] <= dinb; 44 | 45 | endmodule 46 | 47 | //功能说明 48 | //同步读写bram，a口只读，用于取指，b口可读写，用于外接debug_module进行读写 49 | //写使能为1bit，不支持byte write 50 | //输入 51 | //clk 输入时钟 52 | //addra a口读地址 53 | //addrb b口读写地址 54 | //dinb b口写输入数据 55 | //web b口写使能 56 | //输出 57 | //douta a口读数据 58 | //doutb b口读数据 59 | //实验要求 60 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/BranchDecisionMaking.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB(Embeded System Lab） 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/03/14 12:03:15 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: BranchDecisionMaking 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Decide whether to branch 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `include "Parameters.v" 13 | module BranchDecisionMaking( 14 | input wire [2:0] BranchTypeE, 15 | input wire [31:0] Operand1,Operand2, 16 | output reg BranchE 17 | ); 18 | endmodule 19 | 20 | //功能和接口说明 21 | //BranchDecisionMaking接受两个操作数，根据BranchTypeE的不同，进行不同的判断，当分支应该taken时，令BranchE=1'b1 22 | //BranchTypeE的类型定义在Parameters.v中 23 | //推荐格式： 24 | //case() 25 | // `BEQ: ??? 26 | // ....... 27 | // default: BranchE<=1'b0; //NOBRANCH 28 | //endcase 29 | //实验要求 30 | //实现BranchDecisionMaking模块 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/ControlUnit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: ControlUnit 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: RISC-V Instruction Decoder 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `include "Parameters.v" 13 | module ControlUnit( 14 | input wire [6:0] Op, 15 | input wire [2:0] Fn3, 16 | input wire [6:0] Fn7, 17 | output wire JalD, 18 | output wire JalrD, 19 | output reg [2:0] RegWriteD, 20 | output wire MemToRegD, 21 | output reg [3:0] MemWriteD, 22 | output wire LoadNpcD, 23 | output reg [1:0] RegReadD, 24 | output reg [2:0] BranchTypeD, 25 | output reg [3:0] AluContrlD, 26 | output wire [1:0] AluSrc2D, 27 | output wire AluSrc1D, 28 | output reg [2:0] ImmType 29 | ); 30 | endmodule 31 | 32 | //功能说明 33 | //ControlUnit 是本CPU的指令译码器，组合逻辑电路 34 | //输入 35 | // Op 是指令的操作码部分 36 | // Fn3 是指令的func3部分 37 | // Fn7 是指令的func7部分 38 | //输出 39 | // JalD==1 表示Jal指令到达ID译码阶段 40 | // JalrD==1 表示Jalr指令到达ID译码阶段 41 | // RegWriteD 表示ID阶段的指令对应的 寄存器写入模式 ，所有模式定义在Parameters.v中 42 | // MemToRegD==1 表示ID阶段的指令需要将data memory读取的值写入寄存器, 43 | // MemWriteD 共4bit，采用独热码格式，对于data memory的32bit字按byte进行写入,MemWriteD=0001表示只写入最低1个byte，和xilinx bram的接口类似 44 | // LoadNpcD==1 表示将NextPC输出到ResultM 45 | // RegReadD[1]==1 表示A1对应的寄存器值被使用到了，RegReadD[0]==1表示A2对应的寄存器值被使用到了，用于forward的处理 46 | // BranchTypeD 表示不同的分支类型，所有类型定义在Parameters.v中 47 | // AluContrlD 表示不同的ALU计算功能，所有类型定义在Parameters.v中 48 | // AluSrc2D 表示Alu输入源2的选择 49 | // AluSrc1D 表示Alu输入源1的选择 50 | // ImmType 表示指令的立即数格式，所有类型定义在Parameters.v中 51 | //实验要求 52 | //实现ControlUnit模块 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/DataExt.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: qihao 5 | // Create Date: 03/09/2019 09:03:05 PM 6 | // Design Name: 7 | // Module Name: DataExt 8 | // Target Devices: 9 | // Tool Versions: 10 | // Description: 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | 13 | `include "Parameters.v" 14 | module DataExt( 15 | input wire [31:0] IN, 16 | input wire [1:0] LoadedBytesSelect, 17 | input wire [2:0] RegWriteW, 18 | output reg [31:0] OUT 19 | ); 20 | endmodule 21 | 22 | //功能说明 23 | //DataExt是用来处理非字对齐load的情形，同时根据load的不同模式对Data Mem中load的数进行符号或者无符号拓展，组合逻辑电路 24 | //输入 25 | //IN 是从Data Memory中load的32bit字 26 | //LoadedBytesSelect 等价于AluOutM[1:0]，是读Data Memory地址的低两位， 27 | //因为DataMemory是按字（32bit）进行访问的，所以需要把字节地址转化为字地址传给DataMem 28 | //DataMem一次返回一个字，低两位地址用来从32bit字中挑选出我们需要的字节 29 | //RegWriteW 表示不同的 寄存器写入模式 ，所有模式定义在Parameters.v中 30 | //输出 31 | //OUT表示要写入寄存器的最终值 32 | //实验要求 33 | //实现DataExt模块 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/EXSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: EXSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: ID-EX Segment Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module EXSegReg( 13 | input wire clk, 14 | input wire en, 15 | input wire clear, 16 | //Data Signals 17 | input wire [31:0] PCD, 18 | output reg [31:0] PCE, 19 | input wire [31:0] JalNPC, 20 | output reg [31:0] BrNPC, 21 | input wire [31:0] ImmD, 22 | output reg [31:0] ImmE, 23 | input wire [4:0] RdD, 24 | output reg [4:0] RdE, 25 | input wire [4:0] Rs1D, 26 | output reg [4:0] Rs1E, 27 | input wire [4:0] Rs2D, 28 | output reg [4:0] Rs2E, 29 | input wire [31:0] RegOut1D, 30 | output reg [31:0] RegOut1E, 31 | input wire [31:0] RegOut2D, 32 | output reg [31:0] RegOut2E, 33 | //Control Signals 34 | input wire JalrD, 35 | output reg JalrE, 36 | input wire [2:0] RegWriteD, 37 | output reg [2:0] RegWriteE, 38 | input wire MemToRegD, 39 | output reg MemToRegE, 40 | input wire [3:0] MemWriteD, 41 | output reg [3:0] MemWriteE, 42 | input wire LoadNpcD, 43 | output reg LoadNpcE, 44 | input wire [1:0] RegReadD, 45 | output reg [1:0] RegReadE, 46 | input wire [2:0] BranchTypeD, 47 | output reg [2:0] BranchTypeE, 48 | input wire [4:0] AluContrlD, 49 | output reg [4:0] AluContrlE, 50 | input wire AluSrc1D, 51 | output reg AluSrc1E, 52 | input wire [1:0] AluSrc2D, 53 | output reg [1:0] AluSrc2E 54 | ); 55 | initial begin 56 | PCE = 32'b0; 57 | BrNPC = 32'b0; 58 | ImmE = 32'b0; 59 | RdE = 32'b0; 60 | Rs1E = 5'b0; 61 | Rs2E = 5'b0; 62 | RegOut1E = 32'b0; 63 | RegOut2E = 32'b0; 64 | JalrE = 1'b0; 65 | RegWriteE = 1'b0; 66 | MemToRegE = 1'b0; 67 | MemWriteE = 1'b0; 68 | LoadNpcE = 1'b0; 69 | RegReadE = 2'b00; 70 | BranchTypeE = 3'b0; 71 | AluContrlE = 5'b0; 72 | AluSrc1E = 1'b0; 73 | AluSrc2E = 2'b0; 74 | end 75 | // 76 | always@(posedge clk) begin 77 | if(en) 78 | if(clear) 79 | begin 80 | PCE<=32'b0; 81 | BrNPC<=32'b0; 82 | ImmE<=32'b0; 83 | RdE<=32'b0; 84 | Rs1E<=5'b0; 85 | Rs2E<=5'b0; 86 | RegOut1E<=32'b0; 87 | RegOut2E<=32'b0; 88 | JalrE<=1'b0; 89 | RegWriteE<=1'b0; 90 | MemToRegE<=1'b0; 91 | MemWriteE<=1'b0; 92 | LoadNpcE<=1'b0; 93 | RegReadE<=2'b00; 94 | BranchTypeE = 3'b0; 95 | AluContrlE<=5'b0; 96 | AluSrc1E<=1'b0; 97 | AluSrc2E<=2'b0; 98 | end else begin 99 | PCE<=PCD; 100 | BrNPC<=JalNPC; 101 | ImmE<=ImmD; 102 | RdE<=RdD; 103 | Rs1E<=Rs1D; 104 | Rs2E<=Rs2D; 105 | RegOut1E<=RegOut1D; 106 | RegOut2E<=RegOut2D; 107 | JalrE<=JalrD; 108 | RegWriteE=RegWriteD; 109 | MemToRegE<=MemToRegD; 110 | MemWriteE<=MemWriteD; 111 | LoadNpcE<=LoadNpcD; 112 | RegReadE<=RegReadD; 113 | BranchTypeE = BranchTypeD; 114 | AluContrlE<=AluContrlD; 115 | AluSrc1E<=AluSrc1D; 116 | AluSrc2E<=AluSrc2D; 117 | end 118 | end 119 | 120 | endmodule 121 | 122 | //功能说明 123 | //本模块是支持同步清零的段寄存器，当EN==0时寄存器状态保持不变（也不会执行清零） 124 | //实验要求 125 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/HarzardUnit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia & Xuan Wang 5 | // Create Date: 2019/02/22 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: HarzardUnit 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Deal with harzards in pipline 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module HarzardUnit( 13 | input wire CpuRst, ICacheMiss, DCacheMiss, 14 | input wire BranchE, JalrE, JalD, 15 | input wire [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, 16 | input wire [1:0] RegReadE, 17 | input wire [2:0] MemToRegE, RegWriteM, RegWriteW, 18 | output reg StallF, FlushF, StallD, FlushD, StallE, FlushE, StallM, FlushM, StallW, FlushW, 19 | output reg [1:0] Forward1E, Forward2E 20 | ); 21 | //Stall and Flush signals generate 22 | 23 | //Forward Register Source 1 24 | 25 | //Forward Register Source 2 26 | 27 | endmodule 28 | 29 | //功能说明 30 | //HarzardUnit用来处理流水线冲突，通过插入气泡，forward以及冲刷流水段解决数据相关和控制相关，组合逻辑电路 31 | //可以最后实现。前期测试CPU正确性时，可以在每两条指令间插入四条空指令，然后直接把本模块输出定为，不forward，不stall，不flush 32 | //输入 33 | //CpuRst 外部信号，用来初始化CPU，当CpuRst==1时CPU全局复位清零（所有段寄存器flush），Cpu_Rst==0时cpu开始执行指令 34 | //ICacheMiss, DCacheMiss 为后续实验预留信号，暂时可以无视，用来处理cache miss 35 | //BranchE, JalrE, JalD 用来处理控制相关 36 | //Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW 用来处理数据相关，分别表示源寄存器1号码，源寄存器2号码，目标寄存器号码 37 | //RegReadE RegReadD[1]==1 表示A1对应的寄存器值被使用到了，RegReadD[0]==1表示A2对应的寄存器值被使用到了，用于forward的处理 38 | //RegWriteM, RegWriteW 用来处理数据相关，RegWrite!=3'b0说明对目标寄存器有写入操作 39 | //MemToRegE 表示Ex段当前指令 从Data Memory中加载数据到寄存器中 40 | //输出 41 | //StallF, FlushF, StallD, FlushD, StallE, FlushE, StallM, FlushM, StallW, FlushW 控制五个段寄存器进行stall（维持状态不变）和flush（清零） 42 | //Forward1E, Forward2E 控制forward 43 | //实验要求 44 | //实现HarzardUnit模块 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/IDSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia & Xuan Wang 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: IDSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: IF-ID Segment Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module IDSegReg( 13 | input wire clk, 14 | input wire clear, 15 | input wire en, 16 | //Instrution Memory Access 17 | input wire [31:0] A, 18 | output wire [31:0] RD, 19 | //Instruction Memory Debug 20 | input wire [31:0] A2, 21 | input wire [31:0] WD2, 22 | input wire [3:0] WE2, 23 | output wire [31:0] RD2, 24 | // 25 | input wire [31:0] PCF, 26 | output reg [31:0] PCD 27 | ); 28 | 29 | initial PCD = 0; 30 | always@(posedge clk) 31 | if(en) 32 | PCD <= clear ? 0: PCF; 33 | 34 | wire [31:0] RD_raw; 35 | InstructionRam InstructionRamInst ( 36 | .clk (), //请完善代码!!! 37 | .addra (), //请完善代码!!! 38 | .douta ( RD_raw ), 39 | .web ( |WE2 ), 40 | .addrb ( A2[31:2] ), 41 | .dinb ( WD2 ), 42 | .doutb ( RD2 ) 43 | ); 44 | // Add clear and stall support 45 | // if chip not enabled, output output last read result 46 | // else if chip clear, output 0 47 | // else output values from bram 48 | reg stall_ff= 1'b0; 49 | reg clear_ff= 1'b0; 50 | reg [31:0] RD_old=32'b0; 51 | always @ (posedge clk) 52 | begin 53 | stall_ff<=~en; 54 | clear_ff<=clear; 55 | RD_old<=RD_raw; 56 | end 57 | assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw ); 58 | 59 | endmodule 60 | 61 | //功能说明 62 | //IDSegReg是IF-ID段寄存器，同时包含了一个同步读写的Bram（此处你可以调用我们提供的InstructionRam， 63 | //它将会自动综合为block memory，你也可以替代性的调用xilinx的bram ip核）。 64 | //同步读memory 相当于 异步读memory 的输出外接D触发器，需要时钟上升沿才能读取数据。 65 | //此时如果再通过段寄存器缓存，那么需要两个时钟上升沿才能将数据传递到Ex段 66 | //因此在段寄存器模块中调用该同步memory，直接将输出传递到ID段组合逻辑 67 | //调用mem模块后输出为RD_raw，通过assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw ); 68 | //从而实现RD段寄存器stall和clear功能 69 | //实验要求 70 | //你需要补全上方代码，需补全的片段截取如下 71 | //InstructionRam InstructionRamInst ( 72 | // .clk (), //请完善代码 73 | // .addra (), //请完善代码 74 | // .douta ( RD_raw ), 75 | // .web ( |WE2 ), 76 | // .addrb ( A2[31:2] ), 77 | // .dinb ( WD2 ), 78 | // .doutb ( RD2 ) 79 | // ); 80 | //注意事项 81 | //输入到DataRam的addra是字地址，一个字32bit -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/IFSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: IFSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: PC Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module IFSegReg( 13 | input wire clk, 14 | input wire en, clear, 15 | input wire [31:0] PC_In, 16 | output reg [31:0] PCF 17 | ); 18 | initial PCF = 0; 19 | 20 | always@(posedge clk) 21 | if(en) begin 22 | if(clear) 23 | PCF <= 0; 24 | else 25 | PCF <= PC_In; 26 | end 27 | 28 | endmodule 29 | 30 | //功能说明 31 | //IDSegReg是IF-ID段寄存器 32 | //实验要求 33 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/ImmOperandUnit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: ImmOperandUnit 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Generate different type of Immediate Operand 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `include "Parameters.v" 13 | module ImmOperandUnit( 14 | input wire [31:7] In, 15 | input wire [2:0] Type, 16 | output reg [31:0] Out 17 | ); 18 | // 19 | always@(*) 20 | begin 21 | case(Type) 22 | `ITYPE: Out<={ {21{In[31]}}, In[30:20] }; 23 | //...... //请补全!!! 24 | default:Out<=32'hxxxxxxxx; 25 | endcase 26 | end 27 | 28 | endmodule 29 | 30 | //功能说明 31 | //ImmOperandUnit利用正在被译码的指令的部分编码值，生成不同类型的32bit立即数 32 | //输入 33 | //IN 是指令除了opcode以外的部分编码值 34 | //Type 表示立即数编码类型，全部类型定义在Parameters.v中 35 | //输出 36 | //OUT 表示指令对应的立即数32bit实际值 37 | //实验要求 38 | //补全ImmOperandUnit模块 39 | //待补全部分如下 40 | 41 | //always@(*) 42 | //begin 43 | // case(Type) 44 | // `ITYPE: Out<={ {21{In[31]}}, In[30:20] }; 45 | // //...... //请补全!!! 46 | // default:Out<=32'hxxxxxxxx; 47 | // endcase 48 | //end -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/MEMSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia & Xuan Wang 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: MEMSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: EX-MEM Segment Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module MEMSegReg( 13 | input wire clk, 14 | input wire en, 15 | input wire clear, 16 | //Data Signals 17 | input wire [31:0] AluOutE, 18 | output reg [31:0] AluOutM, 19 | input wire [31:0] ForwardData2, 20 | output reg [31:0] StoreDataM, 21 | input wire [4:0] RdE, 22 | output reg [4:0] RdM, 23 | input wire [31:0] PCE, 24 | output reg [31:0] PCM, 25 | //Control Signals 26 | input wire [2:0] RegWriteE, 27 | output reg [2:0] RegWriteM, 28 | input wire MemToRegE, 29 | output reg MemToRegM, 30 | input wire [3:0] MemWriteE, 31 | output reg [3:0] MemWriteM, 32 | input wire LoadNpcE, 33 | output reg LoadNpcM 34 | ); 35 | initial begin 36 | AluOutM = 0; 37 | StoreDataM = 0; 38 | RdM = 5'h0; 39 | PCM = 0; 40 | RegWriteM = 3'h0; 41 | MemToRegM = 1'b0; 42 | MemWriteM = 4'b0; 43 | LoadNpcM = 0; 44 | end 45 | 46 | always@(posedge clk) 47 | if(en) begin 48 | AluOutM <= clear ? 0 : AluOutE; 49 | StoreDataM <= clear ? 0 : ForwardData2; 50 | RdM <= clear ? 5'h0 : RdE; 51 | PCM <= clear ? 0 : PCE; 52 | RegWriteM <= clear ? 3'h0 : RegWriteE; 53 | MemToRegM <= clear ? 1'b0 : MemToRegE; 54 | MemWriteM <= clear ? 4'b0 : MemWriteE; 55 | LoadNpcM <= clear ? 0 : LoadNpcE; 56 | end 57 | 58 | endmodule 59 | 60 | //功能说明 61 | //MEMSegReg是EX-MEM段寄存器 62 | //实验要求 63 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/NPC_Generator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/03/14 11:21:33 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: NPC_Generator 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Choose Next PC value 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module NPC_Generator( 13 | input wire [31:0] PCF,JalrTarget, BranchTarget, JalTarget, 14 | input wire BranchE,JalD,JalrE, 15 | output reg [31:0] PC_In 16 | ); 17 | endmodule 18 | 19 | //功能说明 20 | //NPC_Generator是用来生成Next PC值得模块，根据不同的跳转信号选择不同的新PC值 21 | //输入 22 | //PCF 旧的PC值 23 | //JalrTarget jalr指令的对应的跳转目标 24 | //BranchTarget branch指令的对应的跳转目标 25 | //JalTarget jal指令的对应的跳转目标 26 | //BranchE==1 Ex阶段的Branch指令确定跳转 27 | //JalD==1 ID阶段的Jal指令确定跳转 28 | //JalrE==1 Ex阶段的Jalr指令确定跳转 29 | //输出 30 | //PC_In NPC的值 31 | //实验要求 32 | //实现NPC_Generator模块 33 | -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/Parameters.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Define some constant values 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | `ifndef CONST_VALUES 13 | `define CONST_VALUES 14 | //ALUContrl[3:0] 15 | `define SLL 4'd0 16 | `define SRL 4'd1 17 | `define SRA 4'd2 18 | `define ADD 4'd3 19 | `define SUB 4'd4 20 | `define XOR 4'd5 21 | `define OR 4'd6 22 | `define AND 4'd7 23 | `define SLT 4'd8 24 | `define SLTU 4'd9 25 | `define LUI 4'd10 26 | //BranchType[2:0] 27 | `define NOBRANCH 3'd0 28 | `define BEQ 3'd1 29 | `define BNE 3'd2 30 | `define BLT 3'd3 31 | `define BLTU 3'd4 32 | `define BGE 3'd5 33 | `define BGEU 3'd6 34 | //ImmType[2:0] 35 | `define RTYPE 3'd0 36 | `define ITYPE 3'd1 37 | `define STYPE 3'd2 38 | `define BTYPE 3'd3 39 | `define UTYPE 3'd4 40 | `define JTYPE 3'd5 41 | //RegWrite[2:0] six kind of ways to save values to Register 42 | `define NOREGWRITE 3'b0 // Do not write Register 43 | `define LB 3'd1 // load 8bit from Mem then signed extended to 32bit 44 | `define LH 3'd2 // load 16bit from Mem then signed extended to 32bit 45 | `define LW 3'd3 // write 32bit to Register 46 | `define LBU 3'd4 // load 8bit from Mem then unsigned extended to 32bit 47 | `define LHU 3'd5 // load 16bit from Mem then unsigned extended to 32bit 48 | `endif 49 | 50 | //功能说明 51 | //为了代码可读性，定义了常量值 52 | //实验要求 53 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/RV32Core.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB (Embeded System Lab) 4 | // Engineer: Haojun Xia , Xuan Wang , qihao 5 | // Create Date: 2019/02/08 16:29:41 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: RV32Core 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Top level of our CPU Core 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module RV32Core( 13 | input wire CPU_CLK, 14 | input wire CPU_RST, 15 | input wire [31:0] CPU_Debug_DataRAM_A2, 16 | input wire [31:0] CPU_Debug_DataRAM_WD2, 17 | input wire [3:0] CPU_Debug_DataRAM_WE2, 18 | output wire [31:0] CPU_Debug_DataRAM_RD2, 19 | input wire [31:0] CPU_Debug_InstRAM_A2, 20 | input wire [31:0] CPU_Debug_InstRAM_WD2, 21 | input wire [ 3:0] CPU_Debug_InstRAM_WE2, 22 | output wire [31:0] CPU_Debug_InstRAM_RD2 23 | ); 24 | //wire values definitions 25 | wire StallF, FlushF, StallD, FlushD, StallE, FlushE, StallM, FlushM, StallW, FlushW; 26 | wire [31:0] PC_In; 27 | wire [31:0] PCF; 28 | wire [31:0] Instr, PCD; 29 | wire JalD, JalrD, LoadNpcD, MemToRegD, AluSrc1D; 30 | wire [2:0] RegWriteD; 31 | wire [3:0] MemWriteD; 32 | wire [1:0] RegReadD; 33 | wire [2:0] BranchTypeD; 34 | wire [4:0] AluContrlD; 35 | wire [1:0] AluSrc2D; 36 | wire [2:0] RegWriteW; 37 | wire [4:0] RdW; 38 | wire [31:0] RegWriteData; 39 | wire [31:0] DM_RD_Ext; 40 | wire [2:0] ImmType; 41 | wire [31:0] ImmD; 42 | wire [31:0] JalNPC; 43 | wire [31:0] BrNPC; 44 | wire [31:0] ImmE; 45 | wire [6:0] OpCodeD, Funct7D; 46 | wire [2:0] Funct3D; 47 | wire [4:0] Rs1D, Rs2D, RdD; 48 | wire [4:0] Rs1E, Rs2E, RdE; 49 | wire [31:0] RegOut1D; 50 | wire [31:0] RegOut1E; 51 | wire [31:0] RegOut2D; 52 | wire [31:0] RegOut2E; 53 | wire JalrE; 54 | wire [2:0] RegWriteE; 55 | wire MemToRegE; 56 | wire [3:0] MemWriteE; 57 | wire LoadNpcE; 58 | wire [1:0] RegReadE; 59 | wire [2:0] BranchTypeE; 60 | wire [3:0] AluContrlE; 61 | wire AluSrc1E; 62 | wire [1:0] AluSrc2E; 63 | wire [31:0] Operand1; 64 | wire [31:0] Operand2; 65 | wire BranchE; 66 | wire [31:0] AluOutE; 67 | wire [31:0] AluOutM; 68 | wire [31:0] ForwardData1; 69 | wire [31:0] ForwardData2; 70 | wire [31:0] PCE; 71 | wire [31:0] StoreDataM; 72 | wire [4:0] RdM; 73 | wire [31:0] PCM; 74 | wire [2:0] RegWriteM; 75 | wire MemToRegM; 76 | wire [3:0] MemWriteM; 77 | wire LoadNpcM; 78 | wire [31:0] DM_RD; 79 | wire [31:0] ResultM; 80 | wire [31:0] ResultW; 81 | wire MemToRegW; 82 | wire [1:0] Forward1E; 83 | wire [1:0] Forward2E; 84 | wire [1:0] LoadedBytesSelect; 85 | //wire values assignments 86 | assign {Funct7D, Rs2D, Rs1D, Funct3D, RdD, OpCodeD} = Instr; 87 | assign JalNPC=ImmD+PCD; 88 | assign ForwardData1 = Forward1E[1]?(AluOutM):( Forward1E[0]?RegWriteData:RegOut1E ); 89 | assign Operand1 = AluSrc1E?PCE:ForwardData1; 90 | assign ForwardData2 = Forward2E[1]?(AluOutM):( Forward2E[0]?RegWriteData:RegOut2E ); 91 | assign Operand2 = AluSrc2E[1]?(ImmE):( AluSrc2E[0]?Rs2E:ForwardData2 ); 92 | assign ResultM = LoadNpcM ? (PCM+4) : AluOutM; 93 | assign RegWriteData = ~MemToRegW?ResultW:DM_RD_Ext; 94 | 95 | //Module connections 96 | // --------------------------------------------- 97 | // PC-IF 98 | // --------------------------------------------- 99 | NPC_Generator NPC_Generator1( 100 | .PCF(PCF), 101 | .JalrTarget(AluOutE), 102 | .BranchTarget(BrNPC), 103 | .JalTarget(JalNPC), 104 | .BranchE(BranchE), 105 | .JalD(JalD), 106 | .JalrE(JalrE), 107 | .PC_In(PC_In) 108 | ); 109 | 110 | IFSegReg IFSegReg1( 111 | .clk(CPU_CLK), 112 | .en(~StallF), 113 | .clear(FlushF), 114 | .PC_In(PC_In), 115 | .PCF(PCF) 116 | ); 117 | 118 | // --------------------------------------------- 119 | // ID stage 120 | // --------------------------------------------- 121 | IDSegReg IDSegReg1( 122 | .clk(CPU_CLK), 123 | .clear(FlushD), 124 | .en(~StallD), 125 | .A(PCF), 126 | .RD(Instr), 127 | .A2(CPU_Debug_InstRAM_A2), 128 | .WD2(CPU_Debug_InstRAM_WD2), 129 | .WE2(CPU_Debug_InstRAM_WE2), 130 | .RD2(CPU_Debug_InstRAM_RD2), 131 | .PCF(PCF), 132 | .PCD(PCD) 133 | ); 134 | 135 | ControlUnit ControlUnit1( 136 | .Op(OpCodeD), 137 | .Fn3(Funct3D), 138 | .Fn7(Funct7D), 139 | .JalD(JalD), 140 | .JalrD(JalrD), 141 | .RegWriteD(RegWriteD), 142 | .MemToRegD(MemToRegD), 143 | .MemWriteD(MemWriteD), 144 | .LoadNpcD(LoadNpcD), 145 | .RegReadD(RegReadD), 146 | .BranchTypeD(BranchTypeD), 147 | .AluContrlD(AluContrlD), 148 | .AluSrc1D(AluSrc1D), 149 | .AluSrc2D(AluSrc2D), 150 | .ImmType(ImmType) 151 | ); 152 | 153 | ImmOperandUnit ImmOperandUnit1( 154 | .In(Instr[31:7]), 155 | .Type(ImmType), 156 | .Out(ImmD) 157 | ); 158 | 159 | RegisterFile RegisterFile1( 160 | .clk(CPU_CLK), 161 | .rst(CPU_RST), 162 | .WE3(|RegWriteW), 163 | .A1(Rs1D), 164 | .A2(Rs2D), 165 | .A3(RdW), 166 | .WD3(RegWriteData), 167 | .RD1(RegOut1D), 168 | .RD2(RegOut2D) 169 | ); 170 | 171 | // --------------------------------------------- 172 | // EX stage 173 | // --------------------------------------------- 174 | EXSegReg EXSegReg1( 175 | .clk(CPU_CLK), 176 | .en(~StallE), 177 | .clear(FlushE), 178 | .PCD(PCD), 179 | .PCE(PCE), 180 | .JalNPC(JalNPC), 181 | .BrNPC(BrNPC), 182 | .ImmD(ImmD), 183 | .ImmE(ImmE), 184 | .RdD(RdD), 185 | .RdE(RdE), 186 | .Rs1D(Rs1D), 187 | .Rs1E(Rs1E), 188 | .Rs2D(Rs2D), 189 | .Rs2E(Rs2E), 190 | .RegOut1D(RegOut1D), 191 | .RegOut1E(RegOut1E), 192 | .RegOut2D(RegOut2D), 193 | .RegOut2E(RegOut2E), 194 | .JalrD(JalrD), 195 | .JalrE(JalrE), 196 | .RegWriteD(RegWriteD), 197 | .RegWriteE(RegWriteE), 198 | .MemToRegD(MemToRegD), 199 | .MemToRegE(MemToRegE), 200 | .MemWriteD(MemWriteD), 201 | .MemWriteE(MemWriteE), 202 | .LoadNpcD(LoadNpcD), 203 | .LoadNpcE(LoadNpcE), 204 | .RegReadD(RegReadD), 205 | .RegReadE(RegReadE), 206 | .BranchTypeD(BranchTypeD), 207 | .BranchTypeE(BranchTypeE), 208 | .AluContrlD(AluContrlD), 209 | .AluContrlE(AluContrlE), 210 | .AluSrc1D(AluSrc1D), 211 | .AluSrc1E(AluSrc1E), 212 | .AluSrc2D(AluSrc2D), 213 | .AluSrc2E(AluSrc2E) 214 | ); 215 | 216 | ALU ALU1( 217 | .Operand1(Operand1), 218 | .Operand2(Operand2), 219 | .AluContrl(AluContrlE), 220 | .AluOut(AluOutE) 221 | ); 222 | 223 | BranchDecisionMaking BranchDecisionMaking1( 224 | .BranchTypeE(BranchTypeE), 225 | .Operand1(Operand1), 226 | .Operand2(Operand2), 227 | .BranchE(BranchE) 228 | ); 229 | 230 | // --------------------------------------------- 231 | // MEM stage 232 | // --------------------------------------------- 233 | MEMSegReg MEMSegReg1( 234 | .clk(CPU_CLK), 235 | .en(~StallM), 236 | .clear(FlushM), 237 | .AluOutE(AluOutE), 238 | .AluOutM(AluOutM), 239 | .ForwardData2(ForwardData2), 240 | .StoreDataM(StoreDataM), 241 | .RdE(RdE), 242 | .RdM(RdM), 243 | .PCE(PCE), 244 | .PCM(PCM), 245 | .RegWriteE(RegWriteE), 246 | .RegWriteM(RegWriteM), 247 | .MemToRegE(MemToRegE), 248 | .MemToRegM(MemToRegM), 249 | .MemWriteE(MemWriteE), 250 | .MemWriteM(MemWriteM), 251 | .LoadNpcE(LoadNpcE), 252 | .LoadNpcM(LoadNpcM) 253 | ); 254 | 255 | // --------------------------------------------- 256 | // WB stage 257 | // --------------------------------------------- 258 | WBSegReg WBSegReg1( 259 | .clk(CPU_CLK), 260 | .en(~StallW), 261 | .clear(FlushW), 262 | .A(AluOutM), 263 | .WD(StoreDataM), 264 | .WE(MemWriteM), 265 | .RD(DM_RD), 266 | .LoadedBytesSelect(LoadedBytesSelect), 267 | .A2(CPU_Debug_DataRAM_A2), 268 | .WD2(CPU_Debug_DataRAM_WD2), 269 | .WE2(CPU_Debug_DataRAM_WE2), 270 | .RD2(CPU_Debug_DataRAM_RD2), 271 | .ResultM(ResultM), 272 | .ResultW(ResultW), 273 | .RdM(RdM), 274 | .RdW(RdW), 275 | .RegWriteM(RegWriteM), 276 | .RegWriteW(RegWriteW), 277 | .MemToRegM(MemToRegM), 278 | .MemToRegW(MemToRegW) 279 | ); 280 | 281 | DataExt DataExt1( 282 | .IN(DM_RD), 283 | .LoadedBytesSelect(LoadedBytesSelect), 284 | .RegWriteW(RegWriteW), 285 | .OUT(DM_RD_Ext) 286 | ); 287 | // --------------------------------------------- 288 | // Harzard Unit 289 | // --------------------------------------------- 290 | HarzardUnit HarzardUnit1( 291 | .CpuRst(CPU_RST), 292 | .BranchE(BranchE), 293 | .JalrE(JalrE), 294 | .JalD(JalD), 295 | .Rs1D(Rs1D), 296 | .Rs2D(Rs2D), 297 | .Rs1E(Rs1E), 298 | .Rs2E(Rs2E), 299 | .RegReadE(RegReadE), 300 | .MemToRegE(MemToRegE), 301 | .RdE(RdE), 302 | .RdM(RdM), 303 | .RegWriteM(RegWriteM), 304 | .RdW(RdW), 305 | .RegWriteW(RegWriteW), 306 | .ICacheMiss(1'b0), 307 | .DCacheMiss(1'b0), 308 | .StallF(StallF), 309 | .FlushF(FlushF), 310 | .StallD(StallD), 311 | .FlushD(FlushD), 312 | .StallE(StallE), 313 | .FlushE(FlushE), 314 | .StallM(StallM), 315 | .FlushM(FlushM), 316 | .StallW(StallW), 317 | .FlushW(FlushW), 318 | .Forward1E(Forward1E), 319 | .Forward2E(Forward2E) 320 | ); 321 | 322 | endmodule 323 | 324 | //功能说明 325 | //RV32I 指令集CPU的顶层模块 326 | //实验要求 327 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/RegisterFile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: RegisterFile 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module RegisterFile( 13 | input wire clk, 14 | input wire rst, 15 | input wire WE3, 16 | input wire [4:0] A1, 17 | input wire [4:0] A2, 18 | input wire [4:0] A3, 19 | input wire [31:0] WD3, 20 | output wire [31:0] RD1, 21 | output wire [31:0] RD2 22 | ); 23 | 24 | reg [31:0] RegFile[31:1]; 25 | integer i; 26 | // 27 | always@(negedge clk or posedge rst) 28 | begin 29 | if(rst) for(i=1;i<32;i=i+1) RegFile[i][31:0]<=32'b0; 30 | else if( (WE3==1'b1) && (A3!=5'b0) ) RegFile[A3]<=WD3; 31 | end 32 | // 33 | assign RD1= (A1==5'b0)?32'b0:RegFile[A1]; 34 | assign RD2= (A2==5'b0)?32'b0:RegFile[A2]; 35 | 36 | endmodule 37 | 38 | //功能说明 39 | //上升沿写入，异步读的寄存器堆，0号寄存器值始终为32'b0 40 | //在接入RV32Core时，输入为~clk，因此本模块时钟输入和其他部件始终相反 41 | //等价于例化本模块时正常接入时钟clk，同时修改代码为always@(negedge clk or negedge rst) 42 | //实验要求 43 | //无需修改 -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/WBSegReg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB（Embeded System Lab） 4 | // Engineer: Haojun Xia & Xuan Wang 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: WBSegReg 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: Write Back Segment Register 11 | ////////////////////////////////////////////////////////////////////////////////// 12 | module WBSegReg( 13 | input wire clk, 14 | input wire en, 15 | input wire clear, 16 | //Data Memory Access 17 | input wire [31:0] A, 18 | input wire [31:0] WD, 19 | input wire [3:0] WE, 20 | output wire [31:0] RD, 21 | output reg [1:0] LoadedBytesSelect, 22 | //Data Memory Debug 23 | input wire [31:0] A2, 24 | input wire [31:0] WD2, 25 | input wire [3:0] WE2, 26 | output wire [31:0] RD2, 27 | //input control signals 28 | input wire [31:0] ResultM, 29 | output reg [31:0] ResultW, 30 | input wire [4:0] RdM, 31 | output reg [4:0] RdW, 32 | //output constrol signals 33 | input wire [2:0] RegWriteM, 34 | output reg [2:0] RegWriteW, 35 | input wire MemToRegM, 36 | output reg MemToRegW 37 | ); 38 | 39 | // 40 | initial begin 41 | LoadedBytesSelect = 2'b00; 42 | RegWriteW = 1'b0; 43 | MemToRegW = 1'b0; 44 | ResultW = 0; 45 | RdW = 5'b0; 46 | end 47 | // 48 | always@(posedge clk) 49 | if(en) begin 50 | LoadedBytesSelect <= clear ? 2'b00 : A[1:0]; 51 | RegWriteW <= clear ? 1'b0 : RegWriteM; 52 | MemToRegW <= clear ? 1'b0 : MemToRegM; 53 | ResultW <= clear ? 0 : ResultM; 54 | RdW <= clear ? 5'b0 : RdM; 55 | end 56 | 57 | wire [31:0] RD_raw; 58 | DataRam DataRamInst ( 59 | .clk (???), //请补全 60 | .wea (???), //请补全 61 | .addra (???), //请补全 62 | .dina (???), //请补全 63 | .douta ( RD_raw ), 64 | .web ( WE2 ), 65 | .addrb ( A2[31:2] ), 66 | .dinb ( WD2 ), 67 | .doutb ( RD2 ) 68 | ); 69 | // Add clear and stall support 70 | // if chip not enabled, output output last read result 71 | // else if chip clear, output 0 72 | // else output values from bram 73 | reg stall_ff= 1'b0; 74 | reg clear_ff= 1'b0; 75 | reg [31:0] RD_old=32'b0; 76 | always @ (posedge clk) 77 | begin 78 | stall_ff<=~en; 79 | clear_ff<=clear; 80 | RD_old<=RD_raw; 81 | end 82 | assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw ); 83 | 84 | endmodule 85 | 86 | //功能说明 87 | //WBSegReg是Write Back段寄存器， 88 | //类似于IDSegReg.V中对Bram的调用和拓展，它同时包含了一个同步读写的Bram 89 | //（此处你可以调用我们提供的InstructionRam，它将会自动综合为block memory，你也可以替代性的调用xilinx的bram ip核）。 90 | //同步读memory 相当于 异步读memory 的输出外接D触发器，需要时钟上升沿才能读取数据。 91 | //此时如果再通过段寄存器缓存，那么需要两个时钟上升沿才能将数据传递到Ex段 92 | //因此在段寄存器模块中调用该同步memory，直接将输出传递到WB段组合逻辑 93 | //调用mem模块后输出为RD_raw，通过assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw ); 94 | //从而实现RD段寄存器stall和clear功能 95 | //实验要求 96 | //你需要补全上方代码，需补全的片段截取如下 97 | //DataRam DataRamInst ( 98 | // .clk (???), //请补全 99 | // .wea (???), //请补全 100 | // .addra (???), //请补全 101 | // .dina (???), //请补全 102 | // .douta ( RD_raw ), 103 | // .web ( WE2 ), 104 | // .addrb ( A2[31:2] ), 105 | // .dinb ( WD2 ), 106 | // .doutb ( RD2 ) 107 | //); 108 | //注意事项 109 | //输入到DataRam的addra是字地址，一个字32bit 110 | //请配合DataExt模块实现非字对齐字节load 111 | //请通过补全代码实现非字对齐store 112 | -------------------------------------------------------------------------------- /1_VerilogSourceCode/2_Simulation/testBench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: USTC ESLAB(Embeded System Lab) 4 | // Engineer: Haojun Xia 5 | // Create Date: 2019/02/08 6 | // Design Name: RISCV-Pipline CPU 7 | // Module Name: testBench 8 | // Target Devices: Nexys4 9 | // Tool Versions: Vivado 2017.4.1 10 | // Description: This testBench Help users to initial the bram content, by loading .data file and .inst file. 11 | // Then give signals to start the execution of our cpu 12 | // When all instructions finish their executions, this testBench will dump the Instruction Bram and Data Bram's content to .txt files 13 | // !!! ALL YOU NEED TO CHANGE IS 4 FILE PATH BELOW !!! 14 | // (they are all optional, you can run cpu without change paths here,if files are failed to open, we will not dump the content to .txt and will not try to initial your bram) 15 | ////////////////////////////////////////////////////////////////////////////////// 16 | `define DataRamContentLoadPath "F:\\VivadoWorkspace\\RISCV-CPU\\RISCV-CPU.srcs\\sources_1\\new\\SimFiles\\1testAll.data" 17 | `define InstRamContentLoadPath "F:\\VivadoWorkspace\\RISCV-CPU\\RISCV-CPU.srcs\\sources_1\\new\\SimFiles\\1testAll.inst" 18 | `define DataRamContentSavePath "F:\\VivadoWorkspace\\RISCV-CPU\\RISCV-CPU.srcs\\sources_1\\new\\SimFiles\\DataRamContent.txt" 19 | `define InstRamContentSavePath "F:\\VivadoWorkspace\\RISCV-CPU\\RISCV-CPU.srcs\\sources_1\\new\\SimFiles\\InstRamContent.txt" 20 | `define BRAMWORDS 4096 //a word is 32bit, so our bram is 4096*32bit 21 | 22 | module testBench( 23 | ); 24 | // 25 | reg CPU_CLK; 26 | reg CPU_RST; 27 | reg [31:0] CPU_Debug_DataRAM_A2; 28 | reg [31:0] CPU_Debug_DataRAM_WD2; 29 | reg [3:0] CPU_Debug_DataRAM_WE2; 30 | wire [31:0] CPU_Debug_DataRAM_RD2; 31 | reg [31:0] CPU_Debug_InstRAM_A2; 32 | reg [31:0] CPU_Debug_InstRAM_WD2; 33 | reg [3:0] CPU_Debug_InstRAM_WE2; 34 | wire [31:0] CPU_Debug_InstRAM_RD2; 35 | //generate clock signal 36 | always #1 CPU_CLK = ~CPU_CLK; 37 | // Connect the CPU core 38 | RV32Core RV32Core1( 39 | .CPU_CLK(CPU_CLK), 40 | .CPU_RST(CPU_RST), 41 | .CPU_Debug_DataRAM_A2(CPU_Debug_DataRAM_A2), 42 | .CPU_Debug_DataRAM_WD2(CPU_Debug_DataRAM_WD2), 43 | .CPU_Debug_DataRAM_WE2(CPU_Debug_DataRAM_WE2), 44 | .CPU_Debug_DataRAM_RD2(CPU_Debug_DataRAM_RD2), 45 | .CPU_Debug_InstRAM_A2(CPU_Debug_InstRAM_A2), 46 | .CPU_Debug_InstRAM_WD2(CPU_Debug_InstRAM_WD2), 47 | .CPU_Debug_InstRAM_WE2(CPU_Debug_InstRAM_WE2), 48 | .CPU_Debug_InstRAM_RD2(CPU_Debug_InstRAM_RD2) 49 | ); 50 | //define file handles 51 | integer LoadDataRamFile; 52 | integer LoadInstRamFile; 53 | integer SaveDataRamFile; 54 | integer SaveInstRamFile; 55 | // 56 | integer i; 57 | // 58 | initial 59 | begin 60 | $display("Initialing reg values..."); 61 | CPU_Debug_DataRAM_WD2 = 32'b0; 62 | CPU_Debug_DataRAM_WE2 = 4'b0; 63 | CPU_Debug_InstRAM_WD2 = 32'b0; 64 | CPU_Debug_InstRAM_WE2 = 4'b0; 65 | CPU_Debug_DataRAM_A2 = 32'b0; 66 | CPU_Debug_InstRAM_A2 = 32'b0; 67 | CPU_CLK=1'b0; 68 | CPU_RST = 1'b0; 69 | #10 70 | 71 | $display("Loading DataRam Content from file..."); 72 | LoadDataRamFile = $fopen(`DataRamContentLoadPath,"r"); 73 | if(LoadDataRamFile==0) 74 | $display("Failed to Open %s, Do Not Load DataRam values from file!",`DataRamContentLoadPath); 75 | else begin 76 | CPU_Debug_DataRAM_A2 = 32'h0; 77 | $fscanf(LoadDataRamFile,"%h",CPU_Debug_DataRAM_WD2); 78 | if($feof(LoadDataRamFile)) 79 | CPU_Debug_DataRAM_WE2 = 4'b0; 80 | else 81 | CPU_Debug_DataRAM_WE2 = 4'b1111; 82 | #10 83 | for(i=0;i<`BRAMWORDS;i=i+1) 84 | begin 85 | if($feof(LoadDataRamFile)) 86 | CPU_Debug_DataRAM_WE2 = 4'b0; 87 | else 88 | CPU_Debug_DataRAM_WE2 = 4'b1111; 89 | @(negedge CPU_CLK); 90 | CPU_Debug_DataRAM_A2 = CPU_Debug_DataRAM_A2+4; 91 | $fscanf(LoadDataRamFile,"%h",CPU_Debug_DataRAM_WD2); 92 | end 93 | $fclose(LoadDataRamFile); 94 | end 95 | 96 | $display("Loading InstRam Content from file..."); 97 | LoadInstRamFile = $fopen(`InstRamContentLoadPath,"r"); 98 | if(LoadInstRamFile==0) 99 | $display("Failed to Open %s, Do Not Load InstRam values from file!",`InstRamContentLoadPath); 100 | else begin 101 | CPU_Debug_InstRAM_A2 = 32'h0; 102 | $fscanf(LoadInstRamFile,"%h",CPU_Debug_InstRAM_WD2); 103 | if($feof(LoadInstRamFile)) 104 | CPU_Debug_InstRAM_WE2 = 4'b0; 105 | else 106 | CPU_Debug_InstRAM_WE2 = 4'b1111; 107 | #10 108 | for(i=0;i<`BRAMWORDS;i=i+1) 109 | begin 110 | if($feof(LoadInstRamFile)) 111 | CPU_Debug_InstRAM_WE2 = 4'b0; 112 | else 113 | CPU_Debug_InstRAM_WE2 = 4'b1111; 114 | @(negedge CPU_CLK); 115 | CPU_Debug_InstRAM_A2 = CPU_Debug_InstRAM_A2+4; 116 | $fscanf(LoadInstRamFile,"%h",CPU_Debug_InstRAM_WD2); 117 | end 118 | $fclose(LoadInstRamFile); 119 | end 120 | 121 | $display("Start Instruction Execution!"); 122 | #10; 123 | CPU_RST = 1'b1; 124 | #10; 125 | CPU_RST = 1'b0; 126 | #400000 // waiting for instruction Execution to End 127 | $display("Finish Instruction Execution!"); 128 | 129 | $display("Saving DataRam Content to file..."); 130 | CPU_Debug_DataRAM_A2 = 32'b0; 131 | #10 132 | SaveDataRamFile = $fopen(`DataRamContentSavePath,"w"); 133 | if(SaveDataRamFile==0) 134 | $display("Failed to Open %s, Do Not Save DataRam values to file!",`DataRamContentSavePath); 135 | else 136 | begin 137 | $fwrite(SaveDataRamFile,"i\tAddr\tAddr\tData\tData\n"); 138 | #10 139 | for(i=0;i<`BRAMWORDS;i=i+1) 140 | begin 141 | @(posedge CPU_CLK); 142 | $fwrite(SaveDataRamFile,"%4d\t%8h\t%4d\t%8h\t%4d\n",i,CPU_Debug_DataRAM_A2,CPU_Debug_DataRAM_A2,CPU_Debug_DataRAM_RD2,CPU_Debug_DataRAM_RD2); 143 | CPU_Debug_DataRAM_A2 = CPU_Debug_DataRAM_A2+4; 144 | end 145 | $fclose(SaveDataRamFile); 146 | end 147 | 148 | $display("Saving InstRam Content to file..."); 149 | SaveInstRamFile = $fopen(`InstRamContentSavePath,"w"); 150 | if(SaveInstRamFile==0) 151 | $display("Failed to Open %s, Do Not Save InstRam values to file!",`InstRamContentSavePath); 152 | else 153 | begin 154 | CPU_Debug_InstRAM_A2 = 32'b0; 155 | #10 156 | $fwrite(SaveInstRamFile,"i\tAddr\tAddr\tData\tData\n"); 157 | #10 158 | for(i=0;i<`BRAMWORDS;i=i+1) 159 | begin 160 | @(posedge CPU_CLK); 161 | $fwrite(SaveInstRamFile,"%4d\t%8h\t%4d\t%8h\t%4d\n",i,CPU_Debug_InstRAM_A2,CPU_Debug_InstRAM_A2,CPU_Debug_InstRAM_RD2,CPU_Debug_InstRAM_RD2); 162 | CPU_Debug_InstRAM_A2 = CPU_Debug_InstRAM_A2+4; 163 | end 164 | $fclose(SaveInstRamFile); 165 | end 166 | 167 | $display("Simulation Ended!"); 168 | $stop(); 169 | end 170 | 171 | endmodule 172 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/ASMCode/Fibonacci.S: -------------------------------------------------------------------------------- 1 | # 概述：递归计算斐波那契数列的第n个数 2 | # Author: WangXuan 3 | # 4 | # 系统要求：1、具有一个大小至少为0x400 Byte的数据RAM （该程序中，其高地址用作栈） 5 | # 2、请根据实际情况将a0设置为你的DataRam的地址，例如该系统中DataRam起始地址为0x00000000，则我第一个指令是lui a0, 0x00000 6 | # 7 | 8 | 9 | 10 | .org 0x0 11 | .global _start 12 | _start: 13 | lui a0, 0x00000 # 设置DataRam的起始地址为0x00000000，也用作被排序数组的起始地址是，即DataRam的起始地址 14 | addi sp, a0, 0x400 # 为栈分配0x400Byte的空间 15 | 16 | or t0, zero, 8 # t0 = 8 17 | jal ra, Fibonacci # 计算 fib(8)，正确结果= 34 = 0x22 18 | sw t1, (a0) # 计算结果放在DataRam的首地址 19 | 20 | infinity_loop: 21 | jal zero, infinity_loop # 排序结束，死循环 22 | 23 | 24 | 25 | Fibonacci: # 递归计算斐波那契数列的第n项， 26 | # n放在t0寄存器中 27 | # 结果放在t1寄存器中 28 | # 使用ra作为返回地址，并使用堆栈，堆栈指针为sp 29 | 30 | ori t4, zero, 3 # t4 = 3 31 | bgeu t0, t4, tag # if t0>=t4(3), jmp to tag 32 | ori t1, t0, 0 # t1 = t0 33 | jalr zero, ra, 0 # pc = ra 34 | 35 | tag: 36 | addi t0, t0, -1 # t0-- 37 | 38 | addi sp, sp, -4 # sp-=4 # push ra to stack 39 | sw ra, (sp) # mem[sp] = ra 40 | 41 | addi sp, sp, -4 # sp-=4 # push t0 to stack 42 | sw t0, (sp) # mem[sp] = t0 43 | 44 | jal ra, Fibonacci # 计算 Fib(n-1) 45 | 46 | lw t0, (sp) # t0=mem[sp] # pop t0 from stack 47 | addi t0, t0, -1 # t0-- 48 | 49 | sw t1, (sp) # mem[sp] = t1 50 | jal ra, Fibonacci # 计算 Fib(n-2) 51 | lw t2, (sp) # ra=mem[sp] # pop t2 from stack 52 | addi sp, sp, 4 # sp+=4 53 | add t1, t1, t2 # t1+=t2 54 | 55 | lw ra, (sp) # ra=mem[sp] # pop ra from stack 56 | addi sp, sp, 4 # sp+=4 57 | 58 | jalr zero, ra,0 # pc = ra 59 | 60 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/ASMCode/Number2Ascii.S: -------------------------------------------------------------------------------- 1 | # 概述：数字转十进制ASCII码 2 | # Author: WangXuan 3 | # 4 | # 系统要求：1、具有一个数据RAM 5 | # 2、测试该代码时，不需要初始化DataRam，只需要将指令流烧入InstrRam。 6 | # 3、请根据实际情况将a0设置为你的DataRam的地址，例如该系统中DataRam起始地址为0x00000000，则我将计算结果写入了0x00000000 7 | # 8 | 9 | 10 | .org 0x0 11 | .global _start 12 | _start: 13 | 14 | ori a0, zero, 1395 # a0 = 1395 15 | add a0, a0 , a0 # a0 = 2790 16 | add a0, a0 , a0 # a0 = 5580 17 | jal ra, Number2DecimalAscii # 调用函数Number2DecimalAscii计算 a0 的十进制ASCII，结果应该是 0x30383535，存在 a0 里 18 | 19 | lui t0, 0x00000 # t0 = 0x00000000 20 | sw a0, 0(t0) # a0写入(t0) 21 | infinity_loop: 22 | jal zero, infinity_loop # 死循环 23 | 24 | 25 | Number2DecimalAscii: 26 | # 函数:Number2DecimalAscii：计算a0里低13位二进制数对应的十进制的ASCII码，存放在a0里 27 | # 例: a0=0x12345678，其低13位为0x1678，即5752 28 | # 则调用该函数后 a0=0x32353735，因为0x32, 0x35, 0x37, 0x35分别为2 5 7 5 的ASCII码 29 | # 之所以使用低13位，因为13位二进制数取值范围位0~8191，不会超过4位十进制数 30 | # 改变数据RAM： 无 31 | # 改变的寄存器：a0, t0, t1, t2 32 | # 调用方法：使用 jal ra, Number2DecimalAscii 指令调用，因为返回时需要用到 ra 寄存器作为返回地址 33 | lui t0, 0x01fff # t0 = 0x01fff000 34 | srl t0, t0 , 12 # t0 = 0x00001fff 35 | and t0, a0 , t0 # t0 = t0 & a0 36 | lui a0, 0x30303 # a0 = 0x30303000 37 | ori a0, a0 , 0x030 # a0 = 0x30303030 38 | 39 | ori t1, zero, 1000 # t1 = 1000 40 | thousand: 41 | bltu t0, t1 , thousand_next # if t0<1000 jump to thousand_next 42 | addi t0, t0 , -1000 # t0 -= 1000 43 | addi a0, a0 , 0x1 # a0 += 0x00000001 44 | jal zero, thousand # jump to thousand 45 | thousand_next: 46 | 47 | ori t1, zero, 100 # t1 = 100 48 | hundred: 49 | bltu t0, t1 , hundred_next # if t0<100 jump to hundred_next 50 | addi t0, t0 , -100 # t0 -= 100 51 | addi a0, a0 , 0x100 # a0 += 0x00000100 52 | jal zero, hundred 53 | hundred_next: 54 | 55 | lui t2, 0x00010 # t2 = 0x00010000 56 | ori t1, zero, 10 # t1 = 10 57 | ten: 58 | bltu t0, t1 , ten_next # if t0<10 jump to ten_next 59 | addi t0, t0 , -10 # t0 -= 10 60 | add a0, a0 , t2 # a0 += 0x00010000 61 | jal zero, ten 62 | ten_next: 63 | 64 | lui t2, 0x01000 # t2 = 0x01000000 65 | ori t1, zero, 1 # t1 = 1 66 | one: 67 | bltu t0, t1 , one_next # if t0<1 jump to one_next 68 | addi t0, t0 , -1 # t0 -= 1 69 | add a0, a0 , t2 # a0 += 0x01000000 70 | jal zero, one 71 | one_next: 72 | jalr zero, ra, 0 73 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/ASMCode/QuickSort.S: -------------------------------------------------------------------------------- 1 | # 概述：对数组进行原地快速排序 2 | # Author: WangXuan 3 | # 4 | # 系统要求：1、具有一个大小至少为0x400 Byte的数据RAM （该程序中，其高地址用作栈，低地址用作被排序的数组） 5 | # 2、测试该代码时，不需要初始化DataRam，只需要将指令流烧入InstrRam。因为有一系列指令去准备被排序的数组。 6 | # 3、请根据实际情况将a0设置为你的DataRam的地址，例如该系统中DataRam起始地址为0x00000000，则第一条指令就是 lui a0, 0x00000 7 | # 8 | 9 | 10 | .org 0x0 11 | .global _start 12 | _start: 13 | 14 | main: # main函数开始，在DataRam里初始化一段数据，然后调用QuickSort进行排序，排序后进入死循环。请使用仿真或UART调试器查看排序后的数据 15 | lui a0, 0x00000 # 设置DataRam的起始地址为0x00000000，也用作被排序数组的起始地址，即DataRam的起始地址 16 | addi sp, a0 , 0x400 # 设置栈顶指针 17 | 18 | or a2, a0, zero 19 | 20 | addi t0, zero, -3 # 用一系列指令向a0里写入被排序的数组，可以是负数 21 | sw t0, (a2) 22 | addi a2, a2, 4 23 | addi t0, zero, -7 24 | sw t0, (a2) 25 | addi a2, a2, 4 26 | addi t0, zero, 6 27 | sw t0, (a2) 28 | addi a2, a2, 4 29 | addi t0, zero, 5 30 | sw t0, (a2) 31 | addi a2, a2, 4 32 | addi t0, zero, -2 33 | sw t0, (a2) 34 | addi a2, a2, 4 35 | addi t0, zero, 2 36 | sw t0, (a2) 37 | addi a2, a2, 4 38 | addi t0, zero, -9 39 | sw t0, (a2) 40 | addi a2, a2, 4 41 | addi t0, zero, -4 42 | sw t0, (a2) 43 | addi a2, a2, 4 44 | addi t0, zero, -6 45 | sw t0, (a2) 46 | addi a2, a2, 4 47 | addi t0, zero, 8 48 | sw t0, (a2) 49 | addi a2, a2, 4 50 | addi t0, zero, 1 51 | sw t0, (a2) 52 | addi a2, a2, 4 53 | addi t0, zero, -5 54 | sw t0, (a2) 55 | addi a2, a2, 4 56 | addi t0, zero, 7 57 | sw t0, (a2) 58 | addi a2, a2, 4 59 | addi t0, zero, 0 60 | sw t0, (a2) 61 | addi a2, a2, 4 62 | addi t0, zero, 3 63 | sw t0, (a2) 64 | addi a2, a2, 4 65 | addi t0, zero, -1 66 | sw t0, (a2) 67 | addi a2, a2, 4 68 | addi t0, zero, 4 69 | sw t0, (a2) 70 | addi a2, a2, 4 71 | addi t0, zero, 9 72 | sw t0, (a2) 73 | addi a2, a2, 4 74 | addi t0, zero, -8 75 | sw t0, (a2) 76 | 77 | 78 | or a1, zero, zero # 准备函数参数，a1=0 79 | sub a2, a2, a0 # 准备函数参数，a2=数组最后一个元素的地址偏移 80 | jal ra , QuickSort # 开始排序 81 | infinity_loop: 82 | jal zero, infinity_loop # 排序结束，死循环 83 | 84 | QuickSort: 85 | # 函数:QuickSort：以a0为基地址的原地升序快速排序，a1是start即开始下标，a2是end即结束下标 86 | # 例: a0=0x00000100，a1=0, a2=32，则计算从0x00000100开始的32个4Byte数的快速排序 87 | # 注: 以有符号数为比较标准。例如0xffffffff应该排在0x00000001前面，因为0xffffffff代表-1，比1要小 88 | # 之所以使用低13位，因为13位二进制数取值范围位0~8191，不会超过4位十进制数 89 | # 改变数据RAM： 除了被排序的数组外，还使用了以sp寄存器为栈顶指针的栈。使用栈的大小根据排序长度而不同，调用前合理设置sp的值以防爆栈 90 | # 改变的寄存器： t0, t1, t2, t3, t4 91 | 92 | bge a1, a2, QuickSortReturn # if a1>=a2, end<=start, jump to return 93 | or t1, a1, zero # t1=i=a1=start 94 | or t2, a2, zero # t2=j=a2=end 95 | add t0, a0, t1 # 96 | lw t0, (t0) # t0=key=lst[start] 97 | 98 | PartationStart: 99 | PartationFirstStart: # start of for loop 100 | bge t1, t2, PartationEnd # if i>=j, branch to next step 101 | add t3, a0, t2 # 102 | lw t3, (t3) # t3=lst[j] 103 | blt t3, t0, PartationFirstEnd # if lst[j]=j, branch to next step 112 | add t3, a0, t1 # 113 | lw t3, (t3) # t3=lst[i] 114 | blt t0, t3, PartationSecondEnd # if keystart){ 168 | # int i = start,j = end,key = lst[start]; 169 | # while(i < j){ 170 | # for (;i < j && key <= lst[j];j--); 171 | # lst[i] = lst[j]; 172 | # for (;i < j && key >= lst[i];i++); 173 | # lst[j] = lst[i]; 174 | # } 175 | # lst[i] = key; 176 | # QuickSort(lst, start, i - 1); 177 | # QuickSort(lst, i + 1, end); 178 | # } 179 | # } 180 | # 181 | # 182 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/add.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # add.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test add instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 ); 21 | TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 ); 22 | TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 ); 23 | 24 | TEST_RR_OP( 5, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); 25 | TEST_RR_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 ); 26 | TEST_RR_OP( 7, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); 27 | 28 | TEST_RR_OP( 8, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); 29 | TEST_RR_OP( 9, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); 30 | TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ); 31 | 32 | TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff ); 33 | TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); 34 | 35 | TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); 36 | TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 ); 37 | TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); 38 | 39 | TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ); 40 | 41 | #------------------------------------------------------------- 42 | # Source/Destination tests 43 | #------------------------------------------------------------- 44 | 45 | TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 ); 46 | TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 ); 47 | TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 ); 48 | 49 | #------------------------------------------------------------- 50 | # Bypassing tests 51 | #------------------------------------------------------------- 52 | 53 | TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 ); 54 | TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 ); 55 | TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 ); 56 | 57 | TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 ); 58 | TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 ); 59 | TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 ); 60 | TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 ); 61 | TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 ); 62 | TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 ); 63 | 64 | TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 ); 65 | TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 ); 66 | TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 ); 67 | TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 ); 68 | TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 ); 69 | TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 ); 70 | 71 | TEST_RR_ZEROSRC1( 35, add, 15, 15 ); 72 | TEST_RR_ZEROSRC2( 36, add, 32, 32 ); 73 | TEST_RR_ZEROSRC12( 37, add, 0 ); 74 | TEST_RR_ZERODEST( 38, add, 16, 30 ); 75 | 76 | TEST_PASSFAIL 77 | 78 | RVTEST_CODE_END 79 | 80 | .data 81 | RVTEST_DATA_BEGIN 82 | 83 | TEST_DATA 84 | 85 | RVTEST_DATA_END 86 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/addi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # addi.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test addi instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 ); 21 | TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 ); 22 | TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 ); 23 | 24 | TEST_IMM_OP( 5, addi, 0xfffffffffffff800, 0x0000000000000000, 0x800 ); 25 | TEST_IMM_OP( 6, addi, 0xffffffff80000000, 0xffffffff80000000, 0x000 ); 26 | TEST_IMM_OP( 7, addi, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 ); 27 | 28 | TEST_IMM_OP( 8, addi, 0x00000000000007ff, 0x00000000, 0x7ff ); 29 | TEST_IMM_OP( 9, addi, 0x000000007fffffff, 0x7fffffff, 0x000 ); 30 | TEST_IMM_OP( 10, addi, 0x00000000800007fe, 0x7fffffff, 0x7ff ); 31 | 32 | TEST_IMM_OP( 11, addi, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff ); 33 | TEST_IMM_OP( 12, addi, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 ); 34 | 35 | TEST_IMM_OP( 13, addi, 0xffffffffffffffff, 0x0000000000000000, 0xfff ); 36 | TEST_IMM_OP( 14, addi, 0x0000000000000000, 0xffffffffffffffff, 0x001 ); 37 | TEST_IMM_OP( 15, addi, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff ); 38 | 39 | TEST_IMM_OP( 16, addi, 0x0000000080000000, 0x7fffffff, 0x001 ); 40 | 41 | #------------------------------------------------------------- 42 | # Source/Destination tests 43 | #------------------------------------------------------------- 44 | 45 | TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 ); 46 | 47 | #------------------------------------------------------------- 48 | # Bypassing tests 49 | #------------------------------------------------------------- 50 | 51 | TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 ); 52 | TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 ); 53 | TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 ); 54 | 55 | TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 ); 56 | TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 ); 57 | TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 ); 58 | 59 | TEST_IMM_ZEROSRC1( 24, addi, 32, 32 ); 60 | TEST_IMM_ZERODEST( 25, addi, 33, 50 ); 61 | 62 | TEST_PASSFAIL 63 | 64 | RVTEST_CODE_END 65 | 66 | .data 67 | RVTEST_DATA_BEGIN 68 | 69 | TEST_DATA 70 | 71 | RVTEST_DATA_END 72 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/and.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # and.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test and instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 21 | TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 22 | TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 23 | TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 30 | TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 31 | TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 ); 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 38 | TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 39 | TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 40 | 41 | TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 42 | TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 43 | TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 44 | #TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 45 | #TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 46 | #TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 47 | 48 | #TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 49 | #TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 50 | #TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 51 | #TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); 52 | #TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); 53 | #TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); 54 | 55 | #TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 ); 56 | #TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff ); 57 | #TEST_RR_ZEROSRC12( 26, and, 0 ); 58 | #TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 ); 59 | 60 | TEST_PASSFAIL 61 | 62 | RVTEST_CODE_END 63 | 64 | .data 65 | RVTEST_DATA_BEGIN 66 | 67 | TEST_DATA 68 | 69 | RVTEST_DATA_END 70 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/andi.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # andi.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test andi instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f ); 21 | TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 ); 22 | TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f ); 23 | TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); 36 | TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); 37 | TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f ); 38 | 39 | TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); 40 | TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); 41 | TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f ); 42 | 43 | TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 ); 44 | TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f ); 45 | 46 | TEST_PASSFAIL 47 | 48 | RVTEST_CODE_END 49 | 50 | .data 51 | RVTEST_DATA_BEGIN 52 | 53 | TEST_DATA 54 | 55 | RVTEST_DATA_END 56 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/auipc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # auipc.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test auipc instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 10000, \ 17 | .align 3; \ 18 | lla a0, 1f + 10000; \ 19 | jal a1, 1f; \ 20 | 1: sub a0, a0, a1; \ 21 | ) 22 | 23 | TEST_CASE(3, a0, -10000, \ 24 | .align 3; \ 25 | lla a0, 1f - 10000; \ 26 | jal a1, 1f; \ 27 | 1: sub a0, a0, a1; \ 28 | ) 29 | 30 | TEST_PASSFAIL 31 | 32 | RVTEST_CODE_END 33 | 34 | .data 35 | RVTEST_DATA_BEGIN 36 | 37 | TEST_DATA 38 | 39 | RVTEST_DATA_END 40 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/beq.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # beq.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test beq instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, beq, 0, 0 ); 23 | TEST_BR2_OP_TAKEN( 3, beq, 1, 1 ); 24 | TEST_BR2_OP_TAKEN( 4, beq, -1, -1 ); 25 | 26 | TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 ); 27 | TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 ); 28 | TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 ); 29 | TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 ); 36 | TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 ); 37 | TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 ); 38 | TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 ); 39 | TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 ); 40 | TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 ); 41 | 42 | TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 ); 43 | TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 ); 44 | TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 ); 45 | TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 ); 46 | TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 ); 47 | TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 ); 48 | 49 | #------------------------------------------------------------- 50 | # Test delay slot instructions not executed nor bypassed 51 | #------------------------------------------------------------- 52 | 53 | TEST_CASE( 21, x1, 3, \ 54 | li x1, 1; \ 55 | beq x0, x0, 1f; \ 56 | addi x1, x1, 1; \ 57 | addi x1, x1, 1; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | 1: addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | ) 63 | 64 | TEST_PASSFAIL 65 | 66 | RVTEST_CODE_END 67 | 68 | .data 69 | RVTEST_DATA_BEGIN 70 | 71 | TEST_DATA 72 | 73 | RVTEST_DATA_END 74 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bge.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # bge.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test bge instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, bge, 0, 0 ); 23 | TEST_BR2_OP_TAKEN( 3, bge, 1, 1 ); 24 | TEST_BR2_OP_TAKEN( 4, bge, -1, -1 ); 25 | TEST_BR2_OP_TAKEN( 5, bge, 1, 0 ); 26 | TEST_BR2_OP_TAKEN( 6, bge, 1, -1 ); 27 | TEST_BR2_OP_TAKEN( 7, bge, -1, -2 ); 28 | 29 | TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 ); 30 | TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 ); 31 | TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 ); 32 | TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 ); 33 | 34 | #------------------------------------------------------------- 35 | # Bypassing tests 36 | #------------------------------------------------------------- 37 | 38 | TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 ); 39 | TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 ); 40 | TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 ); 41 | TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 ); 42 | TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 ); 43 | TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 ); 44 | 45 | TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 ); 46 | TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 ); 47 | TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 ); 48 | TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 ); 49 | TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 ); 50 | TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 ); 51 | 52 | #------------------------------------------------------------- 53 | # Test delay slot instructions not executed nor bypassed 54 | #------------------------------------------------------------- 55 | 56 | TEST_CASE( 24, x1, 3, \ 57 | li x1, 1; \ 58 | bge x1, x0, 1f; \ 59 | addi x1, x1, 1; \ 60 | addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | addi x1, x1, 1; \ 63 | 1: addi x1, x1, 1; \ 64 | addi x1, x1, 1; \ 65 | ) 66 | 67 | TEST_PASSFAIL 68 | 69 | RVTEST_CODE_END 70 | 71 | .data 72 | RVTEST_DATA_BEGIN 73 | 74 | TEST_DATA 75 | 76 | RVTEST_DATA_END 77 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bgeu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # bgeu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test bgeu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | #------------------------------------------------------------- 16 | # Branch tests 17 | #------------------------------------------------------------- 18 | 19 | # Each test checks both forward and backward branches 20 | 21 | TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 ); 22 | TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 ); 23 | TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff ); 24 | TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 ); 25 | TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe ); 26 | TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 ); 27 | 28 | TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 ); 29 | TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff ); 30 | TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff ); 31 | TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 ); 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); 38 | TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); 39 | TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); 40 | TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); 41 | TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); 42 | TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); 43 | 44 | TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); 45 | TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); 46 | TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); 47 | TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); 48 | TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); 49 | TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); 50 | 51 | #------------------------------------------------------------- 52 | # Test delay slot instructions not executed nor bypassed 53 | #------------------------------------------------------------- 54 | 55 | TEST_CASE( 24, x1, 3, \ 56 | li x1, 1; \ 57 | bgeu x1, x0, 1f; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | 1: addi x1, x1, 1; \ 63 | addi x1, x1, 1; \ 64 | ) 65 | 66 | TEST_PASSFAIL 67 | 68 | RVTEST_CODE_END 69 | 70 | .data 71 | RVTEST_DATA_BEGIN 72 | 73 | TEST_DATA 74 | 75 | RVTEST_DATA_END 76 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/blt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # blt.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test blt instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, blt, 0, 1 ); 23 | TEST_BR2_OP_TAKEN( 3, blt, -1, 1 ); 24 | TEST_BR2_OP_TAKEN( 4, blt, -2, -1 ); 25 | 26 | TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 ); 27 | TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 ); 28 | TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 ); 29 | TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 ); 36 | TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 ); 37 | TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 ); 38 | TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 ); 39 | TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 ); 40 | TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 ); 41 | 42 | TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 ); 43 | TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 ); 44 | TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 ); 45 | TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 ); 46 | TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 ); 47 | TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 ); 48 | 49 | #------------------------------------------------------------- 50 | # Test delay slot instructions not executed nor bypassed 51 | #------------------------------------------------------------- 52 | 53 | TEST_CASE( 21, x1, 3, \ 54 | li x1, 1; \ 55 | blt x0, x1, 1f; \ 56 | addi x1, x1, 1; \ 57 | addi x1, x1, 1; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | 1: addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | ) 63 | 64 | TEST_PASSFAIL 65 | 66 | RVTEST_CODE_END 67 | 68 | .data 69 | RVTEST_DATA_BEGIN 70 | 71 | TEST_DATA 72 | 73 | RVTEST_DATA_END 74 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # bltu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test bltu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 ); 23 | TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff ); 24 | TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff ); 25 | 26 | TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 ); 27 | TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe ); 28 | TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 ); 29 | TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff ); 36 | TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff ); 37 | TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff ); 38 | TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff ); 39 | TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff ); 40 | TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff ); 41 | 42 | TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff ); 43 | TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff ); 44 | TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff ); 45 | TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff ); 46 | TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff ); 47 | TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff ); 48 | 49 | #------------------------------------------------------------- 50 | # Test delay slot instructions not executed nor bypassed 51 | #------------------------------------------------------------- 52 | 53 | TEST_CASE( 21, x1, 3, \ 54 | li x1, 1; \ 55 | bltu x0, x1, 1f; \ 56 | addi x1, x1, 1; \ 57 | addi x1, x1, 1; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | 1: addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | ) 63 | 64 | TEST_PASSFAIL 65 | 66 | RVTEST_CODE_END 67 | 68 | .data 69 | RVTEST_DATA_BEGIN 70 | 71 | TEST_DATA 72 | 73 | RVTEST_DATA_END 74 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bne.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # bne.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test bne instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Branch tests 18 | #------------------------------------------------------------- 19 | 20 | # Each test checks both forward and backward branches 21 | 22 | TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); 23 | TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); 24 | TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); 25 | TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); 26 | 27 | TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); 28 | TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); 29 | TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 ); 36 | TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 ); 37 | TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 ); 38 | TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 ); 39 | TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 ); 40 | TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 ); 41 | 42 | TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 ); 43 | TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 ); 44 | TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 ); 45 | TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 ); 46 | TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 ); 47 | TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 ); 48 | 49 | #------------------------------------------------------------- 50 | # Test delay slot instructions not executed nor bypassed 51 | #------------------------------------------------------------- 52 | 53 | TEST_CASE( 21, x1, 3, \ 54 | li x1, 1; \ 55 | bne x1, x0, 1f; \ 56 | addi x1, x1, 1; \ 57 | addi x1, x1, 1; \ 58 | addi x1, x1, 1; \ 59 | addi x1, x1, 1; \ 60 | 1: addi x1, x1, 1; \ 61 | addi x1, x1, 1; \ 62 | ) 63 | 64 | TEST_PASSFAIL 65 | 66 | RVTEST_CODE_END 67 | 68 | .data 69 | RVTEST_DATA_BEGIN 70 | 71 | TEST_DATA 72 | 73 | RVTEST_DATA_END 74 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/fence_i.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # fence_i.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test self-modifying code and the fence.i instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | li a3, 111 17 | lh a0, insn 18 | lh a1, insn+2 19 | 20 | # test I$ hit 21 | .align 6 22 | sh a0, 1f, t0 23 | sh a1, 1f+2, t0 24 | fence.i 25 | 26 | 1: addi a3, a3, 222 27 | TEST_CASE( 2, a3, 444, nop ) 28 | 29 | # test prefetcher hit 30 | li a4, 100 31 | 1: addi a4, a4, -1 32 | bnez a4, 1b 33 | 34 | sh a0, 1f, t0 35 | sh a1, 1f+2, t0 36 | fence.i 37 | 38 | .align 6 39 | 1: addi a3, a3, 555 40 | TEST_CASE( 3, a3, 777, nop ) 41 | 42 | TEST_PASSFAIL 43 | 44 | RVTEST_CODE_END 45 | 46 | .data 47 | RVTEST_DATA_BEGIN 48 | 49 | TEST_DATA 50 | 51 | insn: 52 | addi a3, a3, 333 53 | 54 | RVTEST_DATA_END 55 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/include/riscv_test.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef _ENV_PHYSICAL_SINGLE_CORE_H 4 | #define _ENV_PHYSICAL_SINGLE_CORE_H 5 | 6 | #include "./encoding.h" 7 | 8 | //----------------------------------------------------------------------- 9 | // Begin Macro 10 | //----------------------------------------------------------------------- 11 | #define RVTEST_CODE_BEGIN \ 12 | .section .text; \ 13 | .align 6; \ 14 | .globl _start; \ 15 | _start: \ 16 | addi zero,zero, 0 17 | 18 | //----------------------------------------------------------------------- 19 | // End Macro 20 | //----------------------------------------------------------------------- 21 | 22 | #define RVTEST_CODE_END \ 23 | unimp 24 | 25 | //----------------------------------------------------------------------- 26 | // Pass/Fail Macro 27 | //----------------------------------------------------------------------- 28 | #define TESTNUM gp 29 | 30 | #define TEST_PASSFAIL \ 31 | bne x0, TESTNUM, pass; \ 32 | fail: \ 33 | RVTEST_FAIL; \ 34 | pass: \ 35 | RVTEST_PASS \ 36 | 37 | #define RVTEST_PASS \ 38 | li TESTNUM,1;\ 39 | finish1: jal x20,finish1 40 | 41 | #define RVTEST_FAIL \ 42 | finish2: jal x20,finish2 43 | 44 | //----------------------------------------------------------------------- 45 | // Data Section Macro 46 | //----------------------------------------------------------------------- 47 | 48 | #define EXTRA_DATA 49 | 50 | #define RVTEST_DATA_BEGIN \ 51 | EXTRA_DATA \ 52 | .pushsection .tohost,"aw",@progbits; \ 53 | .align 6; .global tohost; tohost: .dword 0; \ 54 | .align 6; .global fromhost; fromhost: .dword 0; \ 55 | .popsection; \ 56 | .align 4; .global begin_signature; begin_signature: 57 | 58 | #define RVTEST_DATA_END .align 4; .global end_signature; end_signature: 59 | 60 | #endif 61 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/include/test_macros.h: -------------------------------------------------------------------------------- 1 | // See LICENSE for license details. 2 | 3 | #ifndef __TEST_MACROS_SCALAR_H 4 | #define __TEST_MACROS_SCALAR_H 5 | 6 | 7 | #----------------------------------------------------------------------- 8 | # Helper macros 9 | #----------------------------------------------------------------------- 10 | 11 | #define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) 12 | 13 | #define TEST_CASE( testnum, testreg, correctval, code... ) \ 14 | test_ ## testnum: \ 15 | code; \ 16 | li x29, MASK_XLEN(correctval); \ 17 | li TESTNUM, testnum; \ 18 | bne testreg, x29, fail; 19 | 20 | # We use a macro hack to simpify code generation for various numbers 21 | # of bubble cycles. 22 | 23 | #define TEST_INSERT_NOPS_0 24 | #define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0 25 | #define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1 26 | #define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2 27 | #define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3 28 | #define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4 29 | #define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5 30 | #define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6 31 | #define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7 32 | #define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8 33 | #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9 34 | 35 | 36 | #----------------------------------------------------------------------- 37 | # RV64UI MACROS 38 | #----------------------------------------------------------------------- 39 | 40 | #----------------------------------------------------------------------- 41 | # Tests for instructions with immediate operand 42 | #----------------------------------------------------------------------- 43 | 44 | #define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) 45 | 46 | #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ 47 | TEST_CASE( testnum, x30, result, \ 48 | li x1, MASK_XLEN(val1); \ 49 | inst x30, x1, SEXT_IMM(imm); \ 50 | ) 51 | 52 | #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ 53 | TEST_CASE( testnum, x1, result, \ 54 | li x1, MASK_XLEN(val1); \ 55 | inst x1, x1, SEXT_IMM(imm); \ 56 | ) 57 | 58 | #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ 59 | TEST_CASE( testnum, x6, result, \ 60 | li x4, 0; \ 61 | 1: li x1, MASK_XLEN(val1); \ 62 | inst x30, x1, SEXT_IMM(imm); \ 63 | TEST_INSERT_NOPS_ ## nop_cycles \ 64 | addi x6, x30, 0; \ 65 | addi x4, x4, 1; \ 66 | li x5, 2; \ 67 | bne x4, x5, 1b \ 68 | ) 69 | 70 | #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ 71 | TEST_CASE( testnum, x30, result, \ 72 | li x4, 0; \ 73 | 1: li x1, MASK_XLEN(val1); \ 74 | TEST_INSERT_NOPS_ ## nop_cycles \ 75 | inst x30, x1, SEXT_IMM(imm); \ 76 | addi x4, x4, 1; \ 77 | li x5, 2; \ 78 | bne x4, x5, 1b \ 79 | ) 80 | 81 | #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \ 82 | TEST_CASE( testnum, x1, result, \ 83 | inst x1, x0, SEXT_IMM(imm); \ 84 | ) 85 | 86 | #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \ 87 | TEST_CASE( testnum, x0, 0, \ 88 | li x1, MASK_XLEN(val1); \ 89 | inst x0, x1, SEXT_IMM(imm); \ 90 | ) 91 | 92 | #----------------------------------------------------------------------- 93 | # Tests for an instruction with register operands 94 | #----------------------------------------------------------------------- 95 | 96 | #define TEST_R_OP( testnum, inst, result, val1 ) \ 97 | TEST_CASE( testnum, x30, result, \ 98 | li x1, val1; \ 99 | inst x30, x1; \ 100 | ) 101 | 102 | #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \ 103 | TEST_CASE( testnum, x1, result, \ 104 | li x1, val1; \ 105 | inst x1, x1; \ 106 | ) 107 | 108 | #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \ 109 | TEST_CASE( testnum, x6, result, \ 110 | li x4, 0; \ 111 | 1: li x1, val1; \ 112 | inst x30, x1; \ 113 | TEST_INSERT_NOPS_ ## nop_cycles \ 114 | addi x6, x30, 0; \ 115 | addi x4, x4, 1; \ 116 | li x5, 2; \ 117 | bne x4, x5, 1b \ 118 | ) 119 | 120 | #----------------------------------------------------------------------- 121 | # Tests for an instruction with register-register operands 122 | #----------------------------------------------------------------------- 123 | 124 | #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \ 125 | TEST_CASE( testnum, x30, result, \ 126 | li x1, MASK_XLEN(val1); \ 127 | li x2, MASK_XLEN(val2); \ 128 | inst x30, x1, x2; \ 129 | ) 130 | 131 | #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ 132 | TEST_CASE( testnum, x1, result, \ 133 | li x1, MASK_XLEN(val1); \ 134 | li x2, MASK_XLEN(val2); \ 135 | inst x1, x1, x2; \ 136 | ) 137 | 138 | #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ 139 | TEST_CASE( testnum, x2, result, \ 140 | li x1, MASK_XLEN(val1); \ 141 | li x2, MASK_XLEN(val2); \ 142 | inst x2, x1, x2; \ 143 | ) 144 | 145 | #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ 146 | TEST_CASE( testnum, x1, result, \ 147 | li x1, MASK_XLEN(val1); \ 148 | inst x1, x1, x1; \ 149 | ) 150 | 151 | #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \ 152 | TEST_CASE( testnum, x6, result, \ 153 | li x4, 0; \ 154 | 1: li x1, MASK_XLEN(val1); \ 155 | li x2, MASK_XLEN(val2); \ 156 | inst x30, x1, x2; \ 157 | TEST_INSERT_NOPS_ ## nop_cycles \ 158 | addi x6, x30, 0; \ 159 | addi x4, x4, 1; \ 160 | li x5, 2; \ 161 | bne x4, x5, 1b \ 162 | ) 163 | 164 | #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ 165 | TEST_CASE( testnum, x30, result, \ 166 | li x4, 0; \ 167 | 1: li x1, MASK_XLEN(val1); \ 168 | TEST_INSERT_NOPS_ ## src1_nops \ 169 | li x2, MASK_XLEN(val2); \ 170 | TEST_INSERT_NOPS_ ## src2_nops \ 171 | inst x30, x1, x2; \ 172 | addi x4, x4, 1; \ 173 | li x5, 2; \ 174 | bne x4, x5, 1b \ 175 | ) 176 | 177 | #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ 178 | TEST_CASE( testnum, x30, result, \ 179 | li x4, 0; \ 180 | 1: li x2, MASK_XLEN(val2); \ 181 | TEST_INSERT_NOPS_ ## src1_nops \ 182 | li x1, MASK_XLEN(val1); \ 183 | TEST_INSERT_NOPS_ ## src2_nops \ 184 | inst x30, x1, x2; \ 185 | addi x4, x4, 1; \ 186 | li x5, 2; \ 187 | bne x4, x5, 1b \ 188 | ) 189 | 190 | #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \ 191 | TEST_CASE( testnum, x2, result, \ 192 | li x1, MASK_XLEN(val); \ 193 | inst x2, x0, x1; \ 194 | ) 195 | 196 | #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \ 197 | TEST_CASE( testnum, x2, result, \ 198 | li x1, MASK_XLEN(val); \ 199 | inst x2, x1, x0; \ 200 | ) 201 | 202 | #define TEST_RR_ZEROSRC12( testnum, inst, result ) \ 203 | TEST_CASE( testnum, x1, result, \ 204 | inst x1, x0, x0; \ 205 | ) 206 | 207 | #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \ 208 | TEST_CASE( testnum, x0, 0, \ 209 | li x1, MASK_XLEN(val1); \ 210 | li x2, MASK_XLEN(val2); \ 211 | inst x0, x1, x2; \ 212 | ) 213 | 214 | #----------------------------------------------------------------------- 215 | # Test memory instructions 216 | #----------------------------------------------------------------------- 217 | 218 | #define TEST_LD_OP( testnum, inst, result, offset, base ) \ 219 | TEST_CASE( testnum, x30, result, \ 220 | la x1, base; \ 221 | inst x30, offset(x1); \ 222 | ) 223 | 224 | #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ 225 | TEST_CASE( testnum, x30, result, \ 226 | la x1, base; \ 227 | li x2, result; \ 228 | store_inst x2, offset(x1); \ 229 | load_inst x30, offset(x1); \ 230 | ) 231 | 232 | #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ 233 | test_ ## testnum: \ 234 | li TESTNUM, testnum; \ 235 | li x4, 0; \ 236 | 1: la x1, base; \ 237 | inst x30, offset(x1); \ 238 | TEST_INSERT_NOPS_ ## nop_cycles \ 239 | addi x6, x30, 0; \ 240 | li x29, result; \ 241 | bne x6, x29, fail; \ 242 | addi x4, x4, 1; \ 243 | li x5, 2; \ 244 | bne x4, x5, 1b; \ 245 | 246 | #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ 247 | test_ ## testnum: \ 248 | li TESTNUM, testnum; \ 249 | li x4, 0; \ 250 | 1: la x1, base; \ 251 | TEST_INSERT_NOPS_ ## nop_cycles \ 252 | inst x30, offset(x1); \ 253 | li x29, result; \ 254 | bne x30, x29, fail; \ 255 | addi x4, x4, 1; \ 256 | li x5, 2; \ 257 | bne x4, x5, 1b \ 258 | 259 | #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ 260 | test_ ## testnum: \ 261 | li TESTNUM, testnum; \ 262 | li x4, 0; \ 263 | 1: li x1, result; \ 264 | TEST_INSERT_NOPS_ ## src1_nops \ 265 | la x2, base; \ 266 | TEST_INSERT_NOPS_ ## src2_nops \ 267 | store_inst x1, offset(x2); \ 268 | load_inst x30, offset(x2); \ 269 | li x29, result; \ 270 | bne x30, x29, fail; \ 271 | addi x4, x4, 1; \ 272 | li x5, 2; \ 273 | bne x4, x5, 1b \ 274 | 275 | #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ 276 | test_ ## testnum: \ 277 | li TESTNUM, testnum; \ 278 | li x4, 0; \ 279 | 1: la x2, base; \ 280 | TEST_INSERT_NOPS_ ## src1_nops \ 281 | li x1, result; \ 282 | TEST_INSERT_NOPS_ ## src2_nops \ 283 | store_inst x1, offset(x2); \ 284 | load_inst x30, offset(x2); \ 285 | li x29, result; \ 286 | bne x30, x29, fail; \ 287 | addi x4, x4, 1; \ 288 | li x5, 2; \ 289 | bne x4, x5, 1b \ 290 | 291 | #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ 292 | test_ ## testnum: \ 293 | li TESTNUM, testnum; \ 294 | li x1, val1; \ 295 | li x2, val2; \ 296 | inst x1, x2, 2f; \ 297 | bne x0, TESTNUM, fail; \ 298 | 1: bne x0, TESTNUM, 3f; \ 299 | 2: inst x1, x2, 1b; \ 300 | bne x0, TESTNUM, fail; \ 301 | 3: 302 | 303 | #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ 304 | test_ ## testnum: \ 305 | li TESTNUM, testnum; \ 306 | li x1, val1; \ 307 | li x2, val2; \ 308 | inst x1, x2, 1f; \ 309 | bne x0, TESTNUM, 2f; \ 310 | 1: bne x0, TESTNUM, fail; \ 311 | 2: inst x1, x2, 1b; \ 312 | 3: 313 | 314 | #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ 315 | test_ ## testnum: \ 316 | li TESTNUM, testnum; \ 317 | li x4, 0; \ 318 | 1: li x1, val1; \ 319 | TEST_INSERT_NOPS_ ## src1_nops \ 320 | li x2, val2; \ 321 | TEST_INSERT_NOPS_ ## src2_nops \ 322 | inst x1, x2, fail; \ 323 | addi x4, x4, 1; \ 324 | li x5, 2; \ 325 | bne x4, x5, 1b \ 326 | 327 | #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ 328 | test_ ## testnum: \ 329 | li TESTNUM, testnum; \ 330 | li x4, 0; \ 331 | 1: li x2, val2; \ 332 | TEST_INSERT_NOPS_ ## src1_nops \ 333 | li x1, val1; \ 334 | TEST_INSERT_NOPS_ ## src2_nops \ 335 | inst x1, x2, fail; \ 336 | addi x4, x4, 1; \ 337 | li x5, 2; \ 338 | bne x4, x5, 1b \ 339 | 340 | #----------------------------------------------------------------------- 341 | # Test jump instructions 342 | #----------------------------------------------------------------------- 343 | 344 | #define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ 345 | test_ ## testnum: \ 346 | li TESTNUM, testnum; \ 347 | li x4, 0; \ 348 | 1: la x6, 2f; \ 349 | TEST_INSERT_NOPS_ ## nop_cycles \ 350 | inst x6; \ 351 | bne x0, TESTNUM, fail; \ 352 | 2: addi x4, x4, 1; \ 353 | li x5, 2; \ 354 | bne x4, x5, 1b \ 355 | 356 | #define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ 357 | test_ ## testnum: \ 358 | li TESTNUM, testnum; \ 359 | li x4, 0; \ 360 | 1: la x6, 2f; \ 361 | TEST_INSERT_NOPS_ ## nop_cycles \ 362 | inst x19, x6, 0; \ 363 | bne x0, TESTNUM, fail; \ 364 | 2: addi x4, x4, 1; \ 365 | li x5, 2; \ 366 | bne x4, x5, 1b \ 367 | 368 | 369 | #----------------------------------------------------------------------- 370 | # RV64UF MACROS 371 | #----------------------------------------------------------------------- 372 | 373 | #----------------------------------------------------------------------- 374 | # Tests floating-point instructions 375 | #----------------------------------------------------------------------- 376 | 377 | #define qNaNf 0f:7fc00000 378 | #define sNaNf 0f:7f800001 379 | #define qNaN 0d:7ff8000000000000 380 | #define sNaN 0d:7ff0000000000001 381 | 382 | #define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ 383 | test_ ## testnum: \ 384 | li TESTNUM, testnum; \ 385 | la a0, test_ ## testnum ## _data ;\ 386 | flw f0, 0(a0); \ 387 | flw f1, 4(a0); \ 388 | flw f2, 8(a0); \ 389 | lw a3, 12(a0); \ 390 | code; \ 391 | fsflags a1, x0; \ 392 | li a2, flags; \ 393 | bne a0, a3, fail; \ 394 | bne a1, a2, fail; \ 395 | .pushsection .data; \ 396 | .align 2; \ 397 | test_ ## testnum ## _data: \ 398 | .float val1; \ 399 | .float val2; \ 400 | .float val3; \ 401 | .result; \ 402 | .popsection 403 | 404 | #define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ 405 | test_ ## testnum: \ 406 | li TESTNUM, testnum; \ 407 | la a0, test_ ## testnum ## _data ;\ 408 | fld f0, 0(a0); \ 409 | fld f1, 8(a0); \ 410 | fld f2, 16(a0); \ 411 | ld a3, 24(a0); \ 412 | code; \ 413 | fsflags a1, x0; \ 414 | li a2, flags; \ 415 | bne a0, a3, fail; \ 416 | bne a1, a2, fail; \ 417 | .pushsection .data; \ 418 | .align 3; \ 419 | test_ ## testnum ## _data: \ 420 | .double val1; \ 421 | .double val2; \ 422 | .double val3; \ 423 | .result; \ 424 | .popsection 425 | 426 | // TODO: assign a separate mem location for the comparison address? 427 | #define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ 428 | test_ ## testnum: \ 429 | li TESTNUM, testnum; \ 430 | la a0, test_ ## testnum ## _data ;\ 431 | fld f0, 0(a0); \ 432 | fld f1, 8(a0); \ 433 | fld f2, 16(a0); \ 434 | lw a3, 24(a0); \ 435 | lw t1, 28(a0); \ 436 | code; \ 437 | fsflags a1, x0; \ 438 | li a2, flags; \ 439 | bne a0, a3, fail; \ 440 | bne t1, t2, fail; \ 441 | bne a1, a2, fail; \ 442 | .pushsection .data; \ 443 | .align 3; \ 444 | test_ ## testnum ## _data: \ 445 | .double val1; \ 446 | .double val2; \ 447 | .double val3; \ 448 | .result; \ 449 | .popsection 450 | 451 | #define TEST_FCVT_S_D32( testnum, result, val1 ) \ 452 | TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ 453 | fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) 454 | 455 | #define TEST_FCVT_S_D( testnum, result, val1 ) \ 456 | TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ 457 | fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3) 458 | 459 | #define TEST_FCVT_D_S( testnum, result, val1 ) \ 460 | TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \ 461 | fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3) 462 | 463 | #define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \ 464 | TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \ 465 | inst f3, f0; fmv.x.s a0, f3) 466 | 467 | #define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \ 468 | TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ 469 | inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) 470 | // ^: store computation result in address from a0, load high-word into t2 471 | 472 | #define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \ 473 | TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ 474 | inst f3, f0; fmv.x.d a0, f3) 475 | 476 | #define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ 477 | TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ 478 | inst f3, f0; fmv.x.s a0, f3) 479 | 480 | #define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ 481 | TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ 482 | inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) 483 | // ^: store computation result in address from a0, load high-word into t2 484 | 485 | #define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ 486 | TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ 487 | inst f3, f0; fmv.x.d a0, f3) 488 | 489 | #define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \ 490 | TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \ 491 | inst f3, f0, f1; fmv.x.s a0, f3) 492 | 493 | #define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \ 494 | TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ 495 | inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) 496 | // ^: store computation result in address from a0, load high-word into t2 497 | 498 | #define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \ 499 | TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ 500 | inst f3, f0, f1; fmv.x.d a0, f3) 501 | 502 | #define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \ 503 | TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \ 504 | inst f3, f0, f1, f2; fmv.x.s a0, f3) 505 | 506 | #define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \ 507 | TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \ 508 | inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) 509 | // ^: store computation result in address from a0, load high-word into t2 510 | 511 | #define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \ 512 | TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \ 513 | inst f3, f0, f1, f2; fmv.x.d a0, f3) 514 | 515 | #define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \ 516 | TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ 517 | inst a0, f0, rm) 518 | 519 | #define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \ 520 | TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ 521 | inst a0, f0, f1; li t2, 0) 522 | 523 | #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \ 524 | TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ 525 | inst a0, f0, rm) 526 | 527 | #define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \ 528 | TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \ 529 | inst a0, f0, f1) 530 | 531 | #define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \ 532 | TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ 533 | inst a0, f0, f1; li t2, 0) 534 | 535 | #define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \ 536 | TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ 537 | inst a0, f0, f1) 538 | 539 | #define TEST_FCLASS_S(testnum, correct, input) \ 540 | TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \ 541 | fclass.s a0, fa0) 542 | 543 | #define TEST_FCLASS_D32(testnum, correct, input) \ 544 | TEST_CASE(testnum, a0, correct, \ 545 | la a0, test_ ## testnum ## _data ;\ 546 | fld fa0, 0(a0); \ 547 | fclass.d a0, fa0) \ 548 | .pushsection .data; \ 549 | .align 3; \ 550 | test_ ## testnum ## _data: \ 551 | .dword input; \ 552 | .popsection 553 | 554 | #define TEST_FCLASS_D(testnum, correct, input) \ 555 | TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ 556 | fclass.d a0, fa0) 557 | 558 | #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \ 559 | test_ ## testnum: \ 560 | li TESTNUM, testnum; \ 561 | la a0, test_ ## testnum ## _data ;\ 562 | lw a3, 0(a0); \ 563 | li a0, val1; \ 564 | inst f0, a0; \ 565 | fsflags x0; \ 566 | fmv.x.s a0, f0; \ 567 | bne a0, a3, fail; \ 568 | .pushsection .data; \ 569 | .align 2; \ 570 | test_ ## testnum ## _data: \ 571 | .float result; \ 572 | .popsection 573 | 574 | #define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \ 575 | test_ ## testnum: \ 576 | li TESTNUM, testnum; \ 577 | la a0, test_ ## testnum ## _data ;\ 578 | lw a3, 0(a0); \ 579 | lw a4, 4(a0); \ 580 | li a1, val1; \ 581 | inst f0, a1; \ 582 | \ 583 | fsd f0, 0(a0); \ 584 | lw a1, 4(a0); \ 585 | lw a0, 0(a0); \ 586 | \ 587 | fsflags x0; \ 588 | bne a0, a3, fail; \ 589 | bne a1, a4, fail; \ 590 | .pushsection .data; \ 591 | .align 3; \ 592 | test_ ## testnum ## _data: \ 593 | .double result; \ 594 | .popsection 595 | 596 | #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \ 597 | test_ ## testnum: \ 598 | li TESTNUM, testnum; \ 599 | la a0, test_ ## testnum ## _data ;\ 600 | ld a3, 0(a0); \ 601 | li a0, val1; \ 602 | inst f0, a0; \ 603 | fsflags x0; \ 604 | fmv.x.d a0, f0; \ 605 | bne a0, a3, fail; \ 606 | .pushsection .data; \ 607 | .align 3; \ 608 | test_ ## testnum ## _data: \ 609 | .double result; \ 610 | .popsection 611 | 612 | // We need some special handling here to allow 64-bit comparison in 32-bit arch 613 | // TODO: find a better name and clean up when intended for general usage? 614 | #define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \ 615 | test_ ## testnum: \ 616 | code; \ 617 | la x31, test_ ## testnum ## _data ; \ 618 | lw x29, 0(x31); \ 619 | lw x31, 4(x31); \ 620 | li TESTNUM, testnum; \ 621 | bne testreg1, x29, fail;\ 622 | bne testreg2, x31, fail;\ 623 | .pushsection .data; \ 624 | .align 3; \ 625 | test_ ## testnum ## _data: \ 626 | .dword correctval; \ 627 | .popsection 628 | 629 | // ^ x30 is used in some other macros, to avoid issues we use x31 for upper word 630 | 631 | #----------------------------------------------------------------------- 632 | # Pass and fail code (assumes test num is in TESTNUM) 633 | #----------------------------------------------------------------------- 634 | 635 | #define TEST_PASSFAIL \ 636 | bne x0, TESTNUM, pass; \ 637 | fail: \ 638 | RVTEST_FAIL; \ 639 | pass: \ 640 | RVTEST_PASS \ 641 | 642 | 643 | #----------------------------------------------------------------------- 644 | # Test data section 645 | #----------------------------------------------------------------------- 646 | 647 | #define TEST_DATA 648 | 649 | #endif 650 | 651 | 652 | 653 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/jal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # jal.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test jal instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Test 2: Basic test 18 | #------------------------------------------------------------- 19 | 20 | test_2: 21 | li TESTNUM, 2 22 | li ra, 0 23 | 24 | jal x4, target_2 25 | linkaddr_2: 26 | nop 27 | nop 28 | 29 | j fail 30 | 31 | target_2: 32 | la x6, linkaddr_2 33 | bne x6, x4, fail 34 | 35 | #------------------------------------------------------------- 36 | # Test delay slot instructions not executed nor bypassed 37 | #------------------------------------------------------------- 38 | 39 | TEST_CASE( 3, ra, 3, \ 40 | li ra, 1; \ 41 | jal x0, 1f; \ 42 | addi ra, ra, 1; \ 43 | addi ra, ra, 1; \ 44 | addi ra, ra, 1; \ 45 | addi ra, ra, 1; \ 46 | 1: addi ra, ra, 1; \ 47 | addi ra, ra, 1; \ 48 | ) 49 | 50 | TEST_PASSFAIL 51 | 52 | RVTEST_CODE_END 53 | 54 | .data 55 | RVTEST_DATA_BEGIN 56 | 57 | TEST_DATA 58 | 59 | RVTEST_DATA_END 60 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/jalr.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # jalr.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test jalr instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Test 2: Basic test 18 | #------------------------------------------------------------- 19 | 20 | test_2: 21 | li TESTNUM, 2 22 | li t0, 0 23 | la t1, target_2 24 | 25 | jalr t0, t1, 0 26 | linkaddr_2: 27 | j fail 28 | 29 | target_2: 30 | la t1, linkaddr_2 31 | bne t0, t1, fail 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_JALR_SRC1_BYPASS( 4, 0, jalr ); 38 | TEST_JALR_SRC1_BYPASS( 5, 1, jalr ); 39 | TEST_JALR_SRC1_BYPASS( 6, 2, jalr ); 40 | 41 | #------------------------------------------------------------- 42 | # Test delay slot instructions not executed nor bypassed 43 | #------------------------------------------------------------- 44 | 45 | .option push 46 | .align 2 47 | .option norvc 48 | TEST_CASE( 7, t0, 4, \ 49 | li t0, 1; \ 50 | la t1, 1f; \ 51 | jr t1, -4; \ 52 | addi t0, t0, 1; \ 53 | addi t0, t0, 1; \ 54 | addi t0, t0, 1; \ 55 | addi t0, t0, 1; \ 56 | 1: addi t0, t0, 1; \ 57 | addi t0, t0, 1; \ 58 | ) 59 | .option pop 60 | 61 | TEST_PASSFAIL 62 | 63 | RVTEST_CODE_END 64 | 65 | .data 66 | RVTEST_DATA_BEGIN 67 | 68 | TEST_DATA 69 | 70 | RVTEST_DATA_END 71 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lb.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lb instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_LD_OP( 2, lb, 0xffffffffffffffff, 0, tdat ); 21 | TEST_LD_OP( 3, lb, 0x0000000000000000, 1, tdat ); 22 | TEST_LD_OP( 4, lb, 0xfffffffffffffff0, 2, tdat ); 23 | TEST_LD_OP( 5, lb, 0x000000000000000f, 3, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_LD_OP( 6, lb, 0xffffffffffffffff, -3, tdat4 ); 28 | TEST_LD_OP( 7, lb, 0x0000000000000000, -2, tdat4 ); 29 | TEST_LD_OP( 8, lb, 0xfffffffffffffff0, -1, tdat4 ); 30 | TEST_LD_OP( 9, lb, 0x000000000000000f, 0, tdat4 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0xffffffffffffffff, \ 35 | la x1, tdat; \ 36 | addi x1, x1, -32; \ 37 | lb x5, 32(x1); \ 38 | ) 39 | 40 | # Test with unaligned base 41 | 42 | TEST_CASE( 11, x5, 0x0000000000000000, \ 43 | la x1, tdat; \ 44 | addi x1, x1, -6; \ 45 | lb x5, 7(x1); \ 46 | ) 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); 53 | TEST_LD_DEST_BYPASS( 13, 1, lb, 0x000000000000000f, 1, tdat3 ); 54 | TEST_LD_DEST_BYPASS( 14, 2, lb, 0x0000000000000000, 1, tdat1 ); 55 | 56 | TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); 57 | TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x000000000000000f, 1, tdat3 ); 58 | TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x0000000000000000, 1, tdat1 ); 59 | 60 | #------------------------------------------------------------- 61 | # Test write-after-write hazard 62 | #------------------------------------------------------------- 63 | 64 | TEST_CASE( 18, x2, 2, \ 65 | la x5, tdat; \ 66 | lb x2, 0(x5); \ 67 | li x2, 2; \ 68 | ) 69 | 70 | TEST_CASE( 19, x2, 2, \ 71 | la x5, tdat; \ 72 | lb x2, 0(x5); \ 73 | nop; \ 74 | li x2, 2; \ 75 | ) 76 | 77 | TEST_PASSFAIL 78 | 79 | RVTEST_CODE_END 80 | 81 | .data 82 | RVTEST_DATA_BEGIN 83 | 84 | TEST_DATA 85 | 86 | tdat: 87 | tdat1: .byte 0xff 88 | tdat2: .byte 0x00 89 | tdat3: .byte 0xf0 90 | tdat4: .byte 0x0f 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lbu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lbu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lbu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0, tdat ); 21 | TEST_LD_OP( 3, lbu, 0x0000000000000000, 1, tdat ); 22 | TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2, tdat ); 23 | TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 ); 28 | TEST_LD_OP( 7, lbu, 0x0000000000000000, -2, tdat4 ); 29 | TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1, tdat4 ); 30 | TEST_LD_OP( 9, lbu, 0x000000000000000f, 0, tdat4 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x00000000000000ff, \ 35 | la x1, tdat; \ 36 | addi x1, x1, -32; \ 37 | lbu x5, 32(x1); \ 38 | ) 39 | 40 | # Test with unaligned base 41 | 42 | TEST_CASE( 11, x5, 0x0000000000000000, \ 43 | la x1, tdat; \ 44 | addi x1, x1, -6; \ 45 | lbu x5, 7(x1); \ 46 | ) 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 ); 53 | TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 ); 54 | TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 ); 55 | 56 | TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 ); 57 | TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 ); 58 | TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 ); 59 | 60 | #------------------------------------------------------------- 61 | # Test write-after-write hazard 62 | #------------------------------------------------------------- 63 | 64 | TEST_CASE( 18, x2, 2, \ 65 | la x5, tdat; \ 66 | lbu x2, 0(x5); \ 67 | li x2, 2; \ 68 | ) 69 | 70 | TEST_CASE( 19, x2, 2, \ 71 | la x5, tdat; \ 72 | lbu x2, 0(x5); \ 73 | nop; \ 74 | li x2, 2; \ 75 | ) 76 | 77 | TEST_PASSFAIL 78 | 79 | RVTEST_CODE_END 80 | 81 | .data 82 | RVTEST_DATA_BEGIN 83 | 84 | TEST_DATA 85 | 86 | tdat: 87 | tdat1: .byte 0xff 88 | tdat2: .byte 0x00 89 | tdat3: .byte 0xf0 90 | tdat4: .byte 0x0f 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lh.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lh instruction. 8 | # 9 | #include "./include/riscv_test.h" 10 | #include "./include/test_macros.h" 11 | 12 | 13 | RVTEST_CODE_BEGIN 14 | 15 | #------------------------------------------------------------- 16 | # Basic tests 17 | #------------------------------------------------------------- 18 | 19 | TEST_LD_OP( 2, lh, 0x00000000000000ff, 0, tdat ); 20 | TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2, tdat ); 21 | TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4, tdat ); 22 | TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat ); 23 | 24 | # Test with negative offset 25 | 26 | TEST_LD_OP( 6, lh, 0x00000000000000ff, -6, tdat4 ); 27 | TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4, tdat4 ); 28 | TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2, tdat4 ); 29 | TEST_LD_OP( 9, lh, 0xfffffffffffff00f, 0, tdat4 ); 30 | 31 | # Test with a negative base 32 | 33 | TEST_CASE( 10, x5, 0x00000000000000ff, \ 34 | la x1, tdat; \ 35 | addi x1, x1, -32; \ 36 | lh x5, 32(x1); \ 37 | ) 38 | 39 | # Test with unaligned base 40 | 41 | TEST_CASE( 11, x5, 0xffffffffffffff00, \ 42 | la x1, tdat; \ 43 | addi x1, x1, -5; \ 44 | lh x5, 7(x1); \ 45 | ) 46 | 47 | #------------------------------------------------------------- 48 | # Bypassing tests 49 | #------------------------------------------------------------- 50 | 51 | TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 ); 52 | TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); 53 | TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 ); 54 | 55 | TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 ); 56 | TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); 57 | TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 ); 58 | 59 | #------------------------------------------------------------- 60 | # Test write-after-write hazard 61 | #------------------------------------------------------------- 62 | 63 | TEST_CASE( 18, x2, 2, \ 64 | la x5, tdat; \ 65 | lh x2, 0(x5); \ 66 | li x2, 2; \ 67 | ) 68 | 69 | TEST_CASE( 19, x2, 2, \ 70 | la x5, tdat; \ 71 | lh x2, 0(x5); \ 72 | nop; \ 73 | li x2, 2; \ 74 | ) 75 | 76 | TEST_PASSFAIL 77 | 78 | RVTEST_CODE_END 79 | 80 | .data 81 | RVTEST_DATA_BEGIN 82 | 83 | TEST_DATA 84 | 85 | tdat: 86 | tdat1: .half 0x00ff 87 | tdat2: .half 0xff00 88 | tdat3: .half 0x0ff0 89 | tdat4: .half 0xf00f 90 | 91 | RVTEST_DATA_END 92 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lhu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lhu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lhu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0, tdat ); 21 | TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2, tdat ); 22 | TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4, tdat ); 23 | TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6, tdat4 ); 28 | TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4, tdat4 ); 29 | TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2, tdat4 ); 30 | TEST_LD_OP( 9, lhu, 0x000000000000f00f, 0, tdat4 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x00000000000000ff, \ 35 | la x1, tdat; \ 36 | addi x1, x1, -32; \ 37 | lhu x5, 32(x1); \ 38 | ) 39 | 40 | # Test with unaligned base 41 | 42 | TEST_CASE( 11, x5, 0x000000000000ff00, \ 43 | la x1, tdat; \ 44 | addi x1, x1, -5; \ 45 | lhu x5, 7(x1); \ 46 | ) 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); 53 | TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 ); 54 | TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 ); 55 | 56 | TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); 57 | TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 ); 58 | TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 ); 59 | 60 | #------------------------------------------------------------- 61 | # Test write-after-write hazard 62 | #------------------------------------------------------------- 63 | 64 | TEST_CASE( 18, x2, 2, \ 65 | la x5, tdat; \ 66 | lhu x2, 0(x5); \ 67 | li x2, 2; \ 68 | ) 69 | 70 | TEST_CASE( 19, x2, 2, \ 71 | la x5, tdat; \ 72 | lhu x2, 0(x5); \ 73 | nop; \ 74 | li x2, 2; \ 75 | ) 76 | 77 | TEST_PASSFAIL 78 | 79 | RVTEST_CODE_END 80 | 81 | .data 82 | RVTEST_DATA_BEGIN 83 | 84 | TEST_DATA 85 | 86 | tdat: 87 | tdat1: .half 0x00ff 88 | tdat2: .half 0xff00 89 | tdat3: .half 0x0ff0 90 | tdat4: .half 0xf00f 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lui.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lui.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lui instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 ); 21 | TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1); 22 | TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20); 23 | TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20); 24 | 25 | TEST_CASE( 6, x0, 0, lui x0, 0x80000 ); 26 | 27 | TEST_PASSFAIL 28 | 29 | RVTEST_CODE_END 30 | 31 | .data 32 | RVTEST_DATA_BEGIN 33 | 34 | TEST_DATA 35 | 36 | RVTEST_DATA_END 37 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lw instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0, tdat ); 21 | TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4, tdat ); 22 | TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8, tdat ); 23 | TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 ); 28 | TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8, tdat4 ); 29 | TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4, tdat4 ); 30 | TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0, tdat4 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x0000000000ff00ff, \ 35 | la x1, tdat; \ 36 | addi x1, x1, -32; \ 37 | lw x5, 32(x1); \ 38 | ) 39 | 40 | # Test with unaligned base 41 | 42 | TEST_CASE( 11, x5, 0xffffffffff00ff00, \ 43 | la x1, tdat; \ 44 | addi x1, x1, -3; \ 45 | lw x5, 7(x1); \ 46 | ) 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); 53 | TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); 54 | TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); 55 | 56 | TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); 57 | TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); 58 | TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); 59 | 60 | #------------------------------------------------------------- 61 | # Test write-after-write hazard 62 | #------------------------------------------------------------- 63 | 64 | TEST_CASE( 18, x2, 2, \ 65 | la x5, tdat; \ 66 | lw x2, 0(x5); \ 67 | li x2, 2; \ 68 | ) 69 | 70 | TEST_CASE( 19, x2, 2, \ 71 | la x5, tdat; \ 72 | lw x2, 0(x5); \ 73 | nop; \ 74 | li x2, 2; \ 75 | ) 76 | 77 | TEST_PASSFAIL 78 | 79 | RVTEST_CODE_END 80 | 81 | .data 82 | RVTEST_DATA_BEGIN 83 | 84 | TEST_DATA 85 | 86 | tdat: 87 | tdat1: .word 0x00ff00ff 88 | tdat2: .word 0xff00ff00 89 | tdat3: .word 0x0ff00ff0 90 | tdat4: .word 0xf00ff00f 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/or.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # or.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test or instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 21 | TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 22 | TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 23 | TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 30 | TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 31 | TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 ); 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 38 | TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 39 | TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 40 | 41 | TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 42 | TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 43 | TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 44 | TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 45 | TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 46 | TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 47 | 48 | TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 49 | TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 50 | TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 51 | TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); 52 | TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); 53 | TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); 54 | 55 | TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 ); 56 | TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff ); 57 | TEST_RR_ZEROSRC12( 26, or, 0 ); 58 | TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 ); 59 | 60 | TEST_PASSFAIL 61 | 62 | RVTEST_CODE_END 63 | 64 | .data 65 | RVTEST_DATA_BEGIN 66 | 67 | TEST_DATA 68 | 69 | RVTEST_DATA_END 70 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/ori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # ori.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test ori instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f ); 21 | TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); 22 | TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); 23 | TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); 36 | TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); 37 | TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 38 | 39 | TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); 40 | TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f ); 41 | TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 42 | 43 | TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 ); 44 | TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f ); 45 | 46 | TEST_PASSFAIL 47 | 48 | RVTEST_CODE_END 49 | 50 | .data 51 | RVTEST_DATA_BEGIN 52 | 53 | TEST_DATA 54 | 55 | RVTEST_DATA_END 56 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sb.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sb.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sb instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat ); 21 | TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat ); 22 | TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat ); 23 | TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_ST_OP( 6, lb, sb, 0xffffffffffffffaa, -3, tdat8 ); 28 | TEST_ST_OP( 7, lb, sb, 0x0000000000000000, -2, tdat8 ); 29 | TEST_ST_OP( 8, lb, sb, 0xffffffffffffffa0, -1, tdat8 ); 30 | TEST_ST_OP( 9, lb, sb, 0x000000000000000a, 0, tdat8 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x78, \ 35 | la x1, tdat9; \ 36 | li x2, 0x12345678; \ 37 | addi x4, x1, -32; \ 38 | sb x2, 32(x4); \ 39 | lb x5, 0(x1); \ 40 | ) 41 | 42 | # Test with unaligned base 43 | 44 | TEST_CASE( 11, x5, 0xffffffffffffff98, \ 45 | la x1, tdat9; \ 46 | li x2, 0x00003098; \ 47 | addi x1, x1, -6; \ 48 | sb x2, 7(x1); \ 49 | la x4, tdat10; \ 50 | lb x5, 0(x4); \ 51 | ) 52 | 53 | #------------------------------------------------------------- 54 | # Bypassing tests 55 | #------------------------------------------------------------- 56 | 57 | TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffffffffffdd, 0, tdat ); 58 | TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffffffffffcd, 1, tdat ); 59 | TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffffffffffcc, 2, tdat ); 60 | TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffffffffffbc, 3, tdat ); 61 | TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffffffffffbb, 4, tdat ); 62 | TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffffffffffab, 5, tdat ); 63 | 64 | TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat ); 65 | TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat ); 66 | TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat ); 67 | TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat ); 68 | TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat ); 69 | TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat ); 70 | 71 | li a0, 0xef 72 | la a1, tdat 73 | sb a0, 3(a1) 74 | 75 | TEST_PASSFAIL 76 | 77 | RVTEST_CODE_END 78 | 79 | .data 80 | RVTEST_DATA_BEGIN 81 | 82 | TEST_DATA 83 | 84 | tdat: 85 | tdat1: .byte 0xef 86 | tdat2: .byte 0xef 87 | tdat3: .byte 0xef 88 | tdat4: .byte 0xef 89 | tdat5: .byte 0xef 90 | tdat6: .byte 0xef 91 | tdat7: .byte 0xef 92 | tdat8: .byte 0xef 93 | tdat9: .byte 0xef 94 | tdat10: .byte 0xef 95 | 96 | RVTEST_DATA_END 97 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sh.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sh.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sh instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat ); 21 | TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat ); 22 | TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat ); 23 | TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 ); 28 | TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 ); 29 | TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 ); 30 | TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0, tdat8 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x5678, \ 35 | la x1, tdat9; \ 36 | li x2, 0x12345678; \ 37 | addi x4, x1, -32; \ 38 | sh x2, 32(x4); \ 39 | lh x5, 0(x1); \ 40 | ) 41 | 42 | # Test with unaligned base 43 | 44 | TEST_CASE( 11, x5, 0x3098, \ 45 | la x1, tdat9; \ 46 | li x2, 0x00003098; \ 47 | addi x1, x1, -5; \ 48 | sh x2, 7(x1); \ 49 | la x4, tdat10; \ 50 | lh x5, 0(x4); \ 51 | ) 52 | 53 | #------------------------------------------------------------- 54 | # Bypassing tests 55 | #------------------------------------------------------------- 56 | 57 | TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0, tdat ); 58 | TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2, tdat ); 59 | TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4, tdat ); 60 | TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat ); 61 | TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat ); 62 | TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat ); 63 | 64 | TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat ); 65 | TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat ); 66 | TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat ); 67 | TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat ); 68 | TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat ); 69 | TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat ); 70 | 71 | li a0, 0xbeef 72 | la a1, tdat 73 | sh a0, 6(a1) 74 | 75 | TEST_PASSFAIL 76 | 77 | RVTEST_CODE_END 78 | 79 | .data 80 | RVTEST_DATA_BEGIN 81 | 82 | TEST_DATA 83 | 84 | tdat: 85 | tdat1: .half 0xbeef 86 | tdat2: .half 0xbeef 87 | tdat3: .half 0xbeef 88 | tdat4: .half 0xbeef 89 | tdat5: .half 0xbeef 90 | tdat6: .half 0xbeef 91 | tdat7: .half 0xbeef 92 | tdat8: .half 0xbeef 93 | tdat9: .half 0xbeef 94 | tdat10: .half 0xbeef 95 | 96 | RVTEST_DATA_END 97 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/simple.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # simple.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This is the most basic self checking test. If your simulator does not 8 | # pass thiss then there is little chance that it will pass any of the 9 | # more complicated self checking tests. 10 | # 11 | 12 | #include "./include/riscv_test.h" 13 | #include "./include/test_macros.h" 14 | 15 | 16 | RVTEST_CODE_BEGIN 17 | 18 | RVTEST_PASS 19 | 20 | RVTEST_CODE_END 21 | 22 | .data 23 | RVTEST_DATA_BEGIN 24 | 25 | TEST_DATA 26 | 27 | RVTEST_DATA_END 28 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sll.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sll.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sll instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, sll, 0x0000000000000001, 0x0000000000000001, 0 ); 21 | TEST_RR_OP( 3, sll, 0x0000000000000002, 0x0000000000000001, 1 ); 22 | TEST_RR_OP( 4, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 23 | TEST_RR_OP( 5, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 24 | TEST_RR_OP( 6, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 25 | 26 | TEST_RR_OP( 7, sll, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); 27 | TEST_RR_OP( 8, sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); 28 | TEST_RR_OP( 9, sll, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); 29 | TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); 30 | TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 ); 31 | 32 | TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0 ); 33 | TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1 ); 34 | TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7 ); 35 | TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 ); 36 | TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 ); 37 | 38 | # Verify that shifts only use bottom six bits 39 | 40 | TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); 41 | TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); 42 | TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); 43 | TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); 44 | 45 | #if __riscv_xlen == 64 46 | TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff ); 47 | TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); 48 | TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); 49 | TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); 50 | #endif 51 | 52 | #------------------------------------------------------------- 53 | # Source/Destination tests 54 | #------------------------------------------------------------- 55 | 56 | TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 ); 57 | TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 ); 58 | TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 ); 59 | 60 | #------------------------------------------------------------- 61 | # Bypassing tests 62 | #------------------------------------------------------------- 63 | 64 | TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 65 | TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 66 | TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 67 | 68 | TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 69 | TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 70 | TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 71 | TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 72 | TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 73 | TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 74 | 75 | TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 76 | TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 77 | TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 78 | TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); 79 | TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); 80 | TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); 81 | 82 | TEST_RR_ZEROSRC1( 40, sll, 0, 15 ); 83 | TEST_RR_ZEROSRC2( 41, sll, 32, 32 ); 84 | TEST_RR_ZEROSRC12( 42, sll, 0 ); 85 | TEST_RR_ZERODEST( 43, sll, 1024, 2048 ); 86 | 87 | TEST_PASSFAIL 88 | 89 | RVTEST_CODE_END 90 | 91 | .data 92 | RVTEST_DATA_BEGIN 93 | 94 | TEST_DATA 95 | 96 | RVTEST_DATA_END 97 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # slli.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test slli instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, slli, 0x0000000000000001, 0x0000000000000001, 0 ); 21 | TEST_IMM_OP( 3, slli, 0x0000000000000002, 0x0000000000000001, 1 ); 22 | TEST_IMM_OP( 4, slli, 0x0000000000000080, 0x0000000000000001, 7 ); 23 | TEST_IMM_OP( 5, slli, 0x0000000000004000, 0x0000000000000001, 14 ); 24 | TEST_IMM_OP( 6, slli, 0x0000000080000000, 0x0000000000000001, 31 ); 25 | 26 | TEST_IMM_OP( 7, slli, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); 27 | TEST_IMM_OP( 8, slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); 28 | TEST_IMM_OP( 9, slli, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); 29 | TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); 30 | TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 ); 31 | 32 | TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0 ); 33 | TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1 ); 34 | TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7 ); 35 | TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 ); 36 | TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 ); 37 | 38 | #if __riscv_xlen == 64 39 | TEST_IMM_OP( 50, slli, 0x8000000000000000, 0x0000000000000001, 63 ); 40 | TEST_IMM_OP( 51, slli, 0xffffff8000000000, 0xffffffffffffffff, 39 ); 41 | TEST_IMM_OP( 52, slli, 0x0909080000000000, 0x0000000021212121, 43 ); 42 | #endif 43 | 44 | #------------------------------------------------------------- 45 | # Source/Destination tests 46 | #------------------------------------------------------------- 47 | 48 | TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 ); 49 | 50 | #------------------------------------------------------------- 51 | # Bypassing tests 52 | #------------------------------------------------------------- 53 | 54 | TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); 55 | TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); 56 | TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); 57 | 58 | TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); 59 | TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); 60 | TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); 61 | 62 | TEST_IMM_ZEROSRC1( 24, slli, 0, 31 ); 63 | TEST_IMM_ZERODEST( 25, slli, 33, 20 ); 64 | 65 | TEST_PASSFAIL 66 | 67 | RVTEST_CODE_END 68 | 69 | .data 70 | RVTEST_DATA_BEGIN 71 | 72 | TEST_DATA 73 | 74 | RVTEST_DATA_END 75 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slt.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # slt.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test slt instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, slt, 0, 0x0000000000000000, 0x0000000000000000 ); 21 | TEST_RR_OP( 3, slt, 0, 0x0000000000000001, 0x0000000000000001 ); 22 | TEST_RR_OP( 4, slt, 1, 0x0000000000000003, 0x0000000000000007 ); 23 | TEST_RR_OP( 5, slt, 0, 0x0000000000000007, 0x0000000000000003 ); 24 | 25 | TEST_RR_OP( 6, slt, 0, 0x0000000000000000, 0xffffffffffff8000 ); 26 | TEST_RR_OP( 7, slt, 1, 0xffffffff80000000, 0x0000000000000000 ); 27 | TEST_RR_OP( 8, slt, 1, 0xffffffff80000000, 0xffffffffffff8000 ); 28 | 29 | TEST_RR_OP( 9, slt, 1, 0x0000000000000000, 0x0000000000007fff ); 30 | TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 ); 31 | TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff ); 32 | 33 | TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff ); 34 | TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 ); 35 | 36 | TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff ); 37 | TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 ); 38 | TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff ); 39 | 40 | #------------------------------------------------------------- 41 | # Source/Destination tests 42 | #------------------------------------------------------------- 43 | 44 | TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 ); 45 | TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 ); 46 | TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 ); 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 ); 53 | TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 ); 54 | TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 ); 55 | 56 | TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 ); 57 | TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 ); 58 | TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 ); 59 | TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 ); 60 | TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 ); 61 | TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 ); 62 | 63 | TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 ); 64 | TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 ); 65 | TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 ); 66 | TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 ); 67 | TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 ); 68 | TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 ); 69 | 70 | TEST_RR_ZEROSRC1( 35, slt, 0, -1 ); 71 | TEST_RR_ZEROSRC2( 36, slt, 1, -1 ); 72 | TEST_RR_ZEROSRC12( 37, slt, 0 ); 73 | TEST_RR_ZERODEST( 38, slt, 16, 30 ); 74 | 75 | TEST_PASSFAIL 76 | 77 | RVTEST_CODE_END 78 | 79 | .data 80 | RVTEST_DATA_BEGIN 81 | 82 | TEST_DATA 83 | 84 | RVTEST_DATA_END 85 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slti.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # slti.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test slti instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, slti, 0, 0x0000000000000000, 0x000 ); 21 | TEST_IMM_OP( 3, slti, 0, 0x0000000000000001, 0x001 ); 22 | TEST_IMM_OP( 4, slti, 1, 0x0000000000000003, 0x007 ); 23 | TEST_IMM_OP( 5, slti, 0, 0x0000000000000007, 0x003 ); 24 | 25 | TEST_IMM_OP( 6, slti, 0, 0x0000000000000000, 0x800 ); 26 | TEST_IMM_OP( 7, slti, 1, 0xffffffff80000000, 0x000 ); 27 | TEST_IMM_OP( 8, slti, 1, 0xffffffff80000000, 0x800 ); 28 | 29 | TEST_IMM_OP( 9, slti, 1, 0x0000000000000000, 0x7ff ); 30 | TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 ); 31 | TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff ); 32 | 33 | TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff ); 34 | TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 ); 35 | 36 | TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff ); 37 | TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 ); 38 | TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff ); 39 | 40 | #------------------------------------------------------------- 41 | # Source/Destination tests 42 | #------------------------------------------------------------- 43 | 44 | TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 ); 45 | 46 | #------------------------------------------------------------- 47 | # Bypassing tests 48 | #------------------------------------------------------------- 49 | 50 | TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 ); 51 | TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 ); 52 | TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 ); 53 | 54 | TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 ); 55 | TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 ); 56 | TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 ); 57 | 58 | TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff ); 59 | TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff ); 60 | 61 | TEST_PASSFAIL 62 | 63 | RVTEST_CODE_END 64 | 65 | .data 66 | RVTEST_DATA_BEGIN 67 | 68 | TEST_DATA 69 | 70 | RVTEST_DATA_END 71 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sltiu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sltiu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sltiu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, sltiu, 0, 0x0000000000000000, 0x000 ); 21 | TEST_IMM_OP( 3, sltiu, 0, 0x0000000000000001, 0x001 ); 22 | TEST_IMM_OP( 4, sltiu, 1, 0x0000000000000003, 0x007 ); 23 | TEST_IMM_OP( 5, sltiu, 0, 0x0000000000000007, 0x003 ); 24 | 25 | TEST_IMM_OP( 6, sltiu, 1, 0x0000000000000000, 0x800 ); 26 | TEST_IMM_OP( 7, sltiu, 0, 0xffffffff80000000, 0x000 ); 27 | TEST_IMM_OP( 8, sltiu, 1, 0xffffffff80000000, 0x800 ); 28 | 29 | TEST_IMM_OP( 9, sltiu, 1, 0x0000000000000000, 0x7ff ); 30 | TEST_IMM_OP( 10, sltiu, 0, 0x000000007fffffff, 0x000 ); 31 | TEST_IMM_OP( 11, sltiu, 0, 0x000000007fffffff, 0x7ff ); 32 | 33 | TEST_IMM_OP( 12, sltiu, 0, 0xffffffff80000000, 0x7ff ); 34 | TEST_IMM_OP( 13, sltiu, 1, 0x000000007fffffff, 0x800 ); 35 | 36 | TEST_IMM_OP( 14, sltiu, 1, 0x0000000000000000, 0xfff ); 37 | TEST_IMM_OP( 15, sltiu, 0, 0xffffffffffffffff, 0x001 ); 38 | TEST_IMM_OP( 16, sltiu, 0, 0xffffffffffffffff, 0xfff ); 39 | 40 | #------------------------------------------------------------- 41 | # Source/Destination tests 42 | #------------------------------------------------------------- 43 | 44 | TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 ); 45 | 46 | #------------------------------------------------------------- 47 | # Bypassing tests 48 | #------------------------------------------------------------- 49 | 50 | TEST_IMM_DEST_BYPASS( 18, 0, sltiu, 0, 15, 10 ); 51 | TEST_IMM_DEST_BYPASS( 19, 1, sltiu, 1, 10, 16 ); 52 | TEST_IMM_DEST_BYPASS( 20, 2, sltiu, 0, 16, 9 ); 53 | 54 | TEST_IMM_SRC1_BYPASS( 21, 0, sltiu, 1, 11, 15 ); 55 | TEST_IMM_SRC1_BYPASS( 22, 1, sltiu, 0, 17, 8 ); 56 | TEST_IMM_SRC1_BYPASS( 23, 2, sltiu, 1, 12, 14 ); 57 | 58 | TEST_IMM_ZEROSRC1( 24, sltiu, 1, 0xfff ); 59 | TEST_IMM_ZERODEST( 25, sltiu, 0x00ff00ff, 0xfff ); 60 | 61 | TEST_PASSFAIL 62 | 63 | RVTEST_CODE_END 64 | 65 | .data 66 | RVTEST_DATA_BEGIN 67 | 68 | TEST_DATA 69 | 70 | RVTEST_DATA_END 71 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sltu.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sltu.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sltu instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, sltu, 0, 0x00000000, 0x00000000 ); 21 | TEST_RR_OP( 3, sltu, 0, 0x00000001, 0x00000001 ); 22 | TEST_RR_OP( 4, sltu, 1, 0x00000003, 0x00000007 ); 23 | TEST_RR_OP( 5, sltu, 0, 0x00000007, 0x00000003 ); 24 | 25 | TEST_RR_OP( 6, sltu, 1, 0x00000000, 0xffff8000 ); 26 | TEST_RR_OP( 7, sltu, 0, 0x80000000, 0x00000000 ); 27 | TEST_RR_OP( 8, sltu, 1, 0x80000000, 0xffff8000 ); 28 | 29 | TEST_RR_OP( 9, sltu, 1, 0x00000000, 0x00007fff ); 30 | TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 ); 31 | TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff ); 32 | 33 | TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff ); 34 | TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 ); 35 | 36 | TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff ); 37 | TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 ); 38 | TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff ); 39 | 40 | #------------------------------------------------------------- 41 | # Source/Destination tests 42 | #------------------------------------------------------------- 43 | 44 | TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 ); 45 | TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 ); 46 | TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 ); 47 | 48 | #------------------------------------------------------------- 49 | # Bypassing tests 50 | #------------------------------------------------------------- 51 | 52 | TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 ); 53 | TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 ); 54 | TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 ); 55 | 56 | TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 ); 57 | TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 ); 58 | TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 ); 59 | TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 ); 60 | TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 ); 61 | TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1, 9, 13 ); 62 | 63 | TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 ); 64 | TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1, 8, 13 ); 65 | TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 ); 66 | TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1, 7, 13 ); 67 | TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 ); 68 | TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1, 6, 13 ); 69 | 70 | TEST_RR_ZEROSRC1( 35, sltu, 1, -1 ); 71 | TEST_RR_ZEROSRC2( 36, sltu, 0, -1 ); 72 | TEST_RR_ZEROSRC12( 37, sltu, 0 ); 73 | TEST_RR_ZERODEST( 38, sltu, 16, 30 ); 74 | 75 | TEST_PASSFAIL 76 | 77 | RVTEST_CODE_END 78 | 79 | .data 80 | RVTEST_DATA_BEGIN 81 | 82 | TEST_DATA 83 | 84 | RVTEST_DATA_END 85 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sra.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sra.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sra instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, sra, 0xffffffff80000000, 0xffffffff80000000, 0 ); 21 | TEST_RR_OP( 3, sra, 0xffffffffc0000000, 0xffffffff80000000, 1 ); 22 | TEST_RR_OP( 4, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 23 | TEST_RR_OP( 5, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 24 | TEST_RR_OP( 6, sra, 0xffffffffffffffff, 0xffffffff80000001, 31 ); 25 | 26 | TEST_RR_OP( 7, sra, 0x000000007fffffff, 0x000000007fffffff, 0 ); 27 | TEST_RR_OP( 8, sra, 0x000000003fffffff, 0x000000007fffffff, 1 ); 28 | TEST_RR_OP( 9, sra, 0x0000000000ffffff, 0x000000007fffffff, 7 ); 29 | TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 ); 30 | TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 ); 31 | 32 | TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0 ); 33 | TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); 34 | TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7 ); 35 | TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); 36 | TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 ); 37 | 38 | # Verify that shifts only use bottom five bits 39 | 40 | TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 ); 41 | TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 ); 42 | TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 ); 43 | TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce ); 44 | TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff ); 45 | 46 | #------------------------------------------------------------- 47 | # Source/Destination tests 48 | #------------------------------------------------------------- 49 | 50 | TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 51 | TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 52 | TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 ); 53 | 54 | #------------------------------------------------------------- 55 | # Bypassing tests 56 | #------------------------------------------------------------- 57 | 58 | TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 59 | TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 60 | TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 61 | 62 | TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 63 | TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 64 | TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 65 | TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 66 | TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 67 | TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 68 | 69 | TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 70 | TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 71 | TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 72 | TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); 73 | TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 74 | TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); 75 | 76 | TEST_RR_ZEROSRC1( 40, sra, 0, 15 ); 77 | TEST_RR_ZEROSRC2( 41, sra, 32, 32 ); 78 | TEST_RR_ZEROSRC12( 42, sra, 0 ); 79 | TEST_RR_ZERODEST( 43, sra, 1024, 2048 ); 80 | 81 | TEST_PASSFAIL 82 | 83 | RVTEST_CODE_END 84 | 85 | .data 86 | RVTEST_DATA_BEGIN 87 | 88 | TEST_DATA 89 | 90 | RVTEST_DATA_END 91 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srai.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # srai.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test srai instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, srai, 0xffffff8000000000, 0xffffff8000000000, 0 ); 21 | TEST_IMM_OP( 3, srai, 0xffffffffc0000000, 0xffffffff80000000, 1 ); 22 | TEST_IMM_OP( 4, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); 23 | TEST_IMM_OP( 5, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 24 | TEST_IMM_OP( 6, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); 25 | 26 | TEST_IMM_OP( 7, srai, 0x000000007fffffff, 0x000000007fffffff, 0 ); 27 | TEST_IMM_OP( 8, srai, 0x000000003fffffff, 0x000000007fffffff, 1 ); 28 | TEST_IMM_OP( 9, srai, 0x0000000000ffffff, 0x000000007fffffff, 7 ); 29 | TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 ); 30 | TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 ); 31 | 32 | TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0 ); 33 | TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); 34 | TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7 ); 35 | TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); 36 | TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 ); 37 | 38 | #------------------------------------------------------------- 39 | # Source/Destination tests 40 | #------------------------------------------------------------- 41 | 42 | TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); 43 | 44 | #------------------------------------------------------------- 45 | # Bypassing tests 46 | #------------------------------------------------------------- 47 | 48 | TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); 49 | TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 50 | TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); 51 | 52 | TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); 53 | TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); 54 | TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); 55 | 56 | TEST_IMM_ZEROSRC1( 24, srai, 0, 4 ); 57 | TEST_IMM_ZERODEST( 25, srai, 33, 10 ); 58 | 59 | TEST_PASSFAIL 60 | 61 | RVTEST_CODE_END 62 | 63 | .data 64 | RVTEST_DATA_BEGIN 65 | 66 | TEST_DATA 67 | 68 | RVTEST_DATA_END 69 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srl.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # srl.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test srl instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | #define TEST_SRL(n, v, a) \ 21 | TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) 22 | 23 | TEST_SRL( 2, 0xffffffff80000000, 0 ); 24 | TEST_SRL( 3, 0xffffffff80000000, 1 ); 25 | TEST_SRL( 4, 0xffffffff80000000, 7 ); 26 | TEST_SRL( 5, 0xffffffff80000000, 14 ); 27 | TEST_SRL( 6, 0xffffffff80000001, 31 ); 28 | 29 | TEST_SRL( 7, 0xffffffffffffffff, 0 ); 30 | TEST_SRL( 8, 0xffffffffffffffff, 1 ); 31 | TEST_SRL( 9, 0xffffffffffffffff, 7 ); 32 | TEST_SRL( 10, 0xffffffffffffffff, 14 ); 33 | TEST_SRL( 11, 0xffffffffffffffff, 31 ); 34 | 35 | TEST_SRL( 12, 0x0000000021212121, 0 ); 36 | TEST_SRL( 13, 0x0000000021212121, 1 ); 37 | TEST_SRL( 14, 0x0000000021212121, 7 ); 38 | TEST_SRL( 15, 0x0000000021212121, 14 ); 39 | TEST_SRL( 16, 0x0000000021212121, 31 ); 40 | 41 | # Verify that shifts only use bottom five bits 42 | 43 | TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); 44 | TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); 45 | TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 ); 46 | TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce ); 47 | TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff ); 48 | 49 | #------------------------------------------------------------- 50 | # Source/Destination tests 51 | #------------------------------------------------------------- 52 | 53 | TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 ); 54 | TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 ); 55 | TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 ); 56 | 57 | #------------------------------------------------------------- 58 | # Bypassing tests 59 | #------------------------------------------------------------- 60 | 61 | TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 ); 62 | TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 ); 63 | TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 ); 64 | 65 | TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 ); 66 | TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 ); 67 | TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 ); 68 | TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 ); 69 | TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 ); 70 | TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 ); 71 | 72 | TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 ); 73 | TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 ); 74 | TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 ); 75 | TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 ); 76 | TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 ); 77 | TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 ); 78 | 79 | TEST_RR_ZEROSRC1( 40, srl, 0, 15 ); 80 | TEST_RR_ZEROSRC2( 41, srl, 32, 32 ); 81 | TEST_RR_ZEROSRC12( 42, srl, 0 ); 82 | TEST_RR_ZERODEST( 43, srl, 1024, 2048 ); 83 | 84 | TEST_PASSFAIL 85 | 86 | RVTEST_CODE_END 87 | 88 | .data 89 | RVTEST_DATA_BEGIN 90 | 91 | TEST_DATA 92 | 93 | RVTEST_DATA_END 94 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srli.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # srli.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test srli instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | #define TEST_SRL(n, v, a) \ 21 | TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) 22 | 23 | TEST_SRL( 2, 0xffffffff80000000, 0 ); 24 | TEST_SRL( 3, 0xffffffff80000000, 1 ); 25 | TEST_SRL( 4, 0xffffffff80000000, 7 ); 26 | TEST_SRL( 5, 0xffffffff80000000, 14 ); 27 | TEST_SRL( 6, 0xffffffff80000001, 31 ); 28 | 29 | TEST_SRL( 7, 0xffffffffffffffff, 0 ); 30 | TEST_SRL( 8, 0xffffffffffffffff, 1 ); 31 | TEST_SRL( 9, 0xffffffffffffffff, 7 ); 32 | TEST_SRL( 10, 0xffffffffffffffff, 14 ); 33 | TEST_SRL( 11, 0xffffffffffffffff, 31 ); 34 | 35 | TEST_SRL( 12, 0x0000000021212121, 0 ); 36 | TEST_SRL( 13, 0x0000000021212121, 1 ); 37 | TEST_SRL( 14, 0x0000000021212121, 7 ); 38 | TEST_SRL( 15, 0x0000000021212121, 14 ); 39 | TEST_SRL( 16, 0x0000000021212121, 31 ); 40 | 41 | #------------------------------------------------------------- 42 | # Source/Destination tests 43 | #------------------------------------------------------------- 44 | 45 | TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 ); 46 | 47 | #------------------------------------------------------------- 48 | # Bypassing tests 49 | #------------------------------------------------------------- 50 | 51 | TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7 ); 52 | TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 ); 53 | TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 ); 54 | 55 | TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7 ); 56 | TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 ); 57 | TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 ); 58 | 59 | TEST_IMM_ZEROSRC1( 24, srli, 0, 4 ); 60 | TEST_IMM_ZERODEST( 25, srli, 33, 10 ); 61 | 62 | TEST_PASSFAIL 63 | 64 | RVTEST_CODE_END 65 | 66 | .data 67 | RVTEST_DATA_BEGIN 68 | 69 | TEST_DATA 70 | 71 | RVTEST_DATA_END 72 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sub.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sub.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sub instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Arithmetic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); 21 | TEST_RR_OP( 3, sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 ); 22 | TEST_RR_OP( 4, sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 ); 23 | 24 | TEST_RR_OP( 5, sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 ); 25 | TEST_RR_OP( 6, sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); 26 | TEST_RR_OP( 7, sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 ); 27 | 28 | TEST_RR_OP( 8, sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff ); 29 | TEST_RR_OP( 9, sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); 30 | TEST_RR_OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff ); 31 | 32 | TEST_RR_OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff ); 33 | TEST_RR_OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 ); 34 | 35 | TEST_RR_OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff ); 36 | TEST_RR_OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 ); 37 | TEST_RR_OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff ); 38 | 39 | #------------------------------------------------------------- 40 | # Source/Destination tests 41 | #------------------------------------------------------------- 42 | 43 | TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 ); 44 | TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 ); 45 | TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 ); 46 | 47 | #------------------------------------------------------------- 48 | # Bypassing tests 49 | #------------------------------------------------------------- 50 | 51 | TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 ); 52 | TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 ); 53 | TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 ); 54 | 55 | TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 ); 56 | TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 ); 57 | TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 ); 58 | TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 ); 59 | TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 ); 60 | TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 ); 61 | 62 | TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 ); 63 | TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 ); 64 | TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 ); 65 | TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 ); 66 | TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 ); 67 | TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 ); 68 | 69 | TEST_RR_ZEROSRC1( 34, sub, 15, -15 ); 70 | TEST_RR_ZEROSRC2( 35, sub, 32, 32 ); 71 | TEST_RR_ZEROSRC12( 36, sub, 0 ); 72 | TEST_RR_ZERODEST( 37, sub, 16, 30 ); 73 | 74 | TEST_PASSFAIL 75 | 76 | RVTEST_CODE_END 77 | 78 | .data 79 | RVTEST_DATA_BEGIN 80 | 81 | TEST_DATA 82 | 83 | RVTEST_DATA_END 84 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sw.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # sw.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test sw instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0, tdat ); 21 | TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4, tdat ); 22 | TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8, tdat ); 23 | TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat ); 24 | 25 | # Test with negative offset 26 | 27 | TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 ); 28 | TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8, tdat8 ); 29 | TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4, tdat8 ); 30 | TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0, tdat8 ); 31 | 32 | # Test with a negative base 33 | 34 | TEST_CASE( 10, x5, 0x12345678, \ 35 | la x1, tdat9; \ 36 | li x2, 0x12345678; \ 37 | addi x4, x1, -32; \ 38 | sw x2, 32(x4); \ 39 | lw x5, 0(x1); \ 40 | ) 41 | 42 | # Test with unaligned base 43 | 44 | TEST_CASE( 11, x5, 0x58213098, \ 45 | la x1, tdat9; \ 46 | li x2, 0x58213098; \ 47 | addi x1, x1, -3; \ 48 | sw x2, 7(x1); \ 49 | la x4, tdat10; \ 50 | lw x5, 0(x4); \ 51 | ) 52 | 53 | #------------------------------------------------------------- 54 | # Bypassing tests 55 | #------------------------------------------------------------- 56 | 57 | TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0, tdat ); 58 | TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4, tdat ); 59 | TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8, tdat ); 60 | TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat ); 61 | TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat ); 62 | TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat ); 63 | 64 | TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat ); 65 | TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat ); 66 | TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat ); 67 | TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat ); 68 | TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat ); 69 | TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat ); 70 | 71 | TEST_PASSFAIL 72 | 73 | RVTEST_CODE_END 74 | 75 | .data 76 | RVTEST_DATA_BEGIN 77 | 78 | TEST_DATA 79 | 80 | tdat: 81 | tdat1: .word 0xdeadbeef 82 | tdat2: .word 0xdeadbeef 83 | tdat3: .word 0xdeadbeef 84 | tdat4: .word 0xdeadbeef 85 | tdat5: .word 0xdeadbeef 86 | tdat6: .word 0xdeadbeef 87 | tdat7: .word 0xdeadbeef 88 | tdat8: .word 0xdeadbeef 89 | tdat9: .word 0xdeadbeef 90 | tdat10: .word 0xdeadbeef 91 | 92 | RVTEST_DATA_END 93 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/xor.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # xor.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test xor instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 21 | TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 22 | TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 23 | TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 30 | TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 31 | TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 ); 32 | 33 | #------------------------------------------------------------- 34 | # Bypassing tests 35 | #------------------------------------------------------------- 36 | 37 | TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 38 | TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 39 | TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 40 | 41 | TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 42 | TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 43 | TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 44 | TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 45 | TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 46 | TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 47 | 48 | TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 49 | TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 50 | TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 51 | TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); 52 | TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); 53 | TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); 54 | 55 | TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 ); 56 | TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff ); 57 | TEST_RR_ZEROSRC12( 26, xor, 0 ); 58 | TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 ); 59 | 60 | TEST_PASSFAIL 61 | 62 | RVTEST_CODE_END 63 | 64 | .data 65 | RVTEST_DATA_BEGIN 66 | 67 | TEST_DATA 68 | 69 | RVTEST_DATA_END 70 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/xori.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # xori.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test xori instruction. 8 | # 9 | 10 | #include "./include/riscv_test.h" 11 | #include "./include/test_macros.h" 12 | 13 | 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Logical tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f ); 21 | TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); 22 | TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); 23 | TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 24 | 25 | #------------------------------------------------------------- 26 | # Source/Destination tests 27 | #------------------------------------------------------------- 28 | 29 | TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f ); 30 | 31 | #------------------------------------------------------------- 32 | # Bypassing tests 33 | #------------------------------------------------------------- 34 | 35 | TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); 36 | TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); 37 | TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 38 | 39 | TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); 40 | TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f ); 41 | TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); 42 | 43 | TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 ); 44 | TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f ); 45 | 46 | TEST_PASSFAIL 47 | 48 | RVTEST_CODE_END 49 | 50 | .data 51 | RVTEST_DATA_BEGIN 52 | 53 | TEST_DATA 54 | 55 | RVTEST_DATA_END 56 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/Makefile: -------------------------------------------------------------------------------- 1 | #Copyright (c) 2019 HaojunXia 2 | 3 | #This script can change .S Files into .inst & .data files which can be loaded by our FPGA's Block memories. 4 | #Decided upon which level of files you want, you can choose one of these commands listed below 5 | #make/make all: 6 | #change all .S files into .data & .inst files, meanwhile all intermediate files will be saved. 7 | #make DataAndInst: 8 | #dump both Data and Instructions and save them to .data files 9 | #make InstOnly: 10 | #dump ONLY Instructions and save them to .inst files 11 | #make OMFile: 12 | #assembly the .S files into .o files, then link the .o files into .om files 13 | #make OFile: 14 | #assembly the .S files into .o files 15 | #Other options: 16 | #make clean: 17 | #clean all files generated by this makefile, but do not delete .S files 18 | #make cleanASM: 19 | #clean all .S files 20 | 21 | #Deal with .S Files 22 | ASM_SOURCE = $(wildcard *.S) 23 | INSTONLY = $(patsubst %.S,%.inst,$(ASM_SOURCE)) 24 | DATAANDINST = $(patsubst %.S,%.data,$(ASM_SOURCE)) 25 | OMFILE = $(patsubst %.S,%.om,$(ASM_SOURCE)) 26 | OFILE = $(patsubst %.S,%.o,$(ASM_SOURCE)) 27 | all: InstOnly DataAndInst OMFile OFile 28 | InstOnly: $(INSTONLY) 29 | DataAndInst: $(DATAANDINST) 30 | OMFile: $(OMFILE) 31 | OFile: $(OFILE) 32 | 33 | #rules 34 | Bin2Data: ./Utils/Bin2Data.c 35 | gcc -o Bin2Data ./Utils/Bin2Data.c 36 | %.o: %.S 37 | riscv32-unknown-elf-gcc -c $< -o $@ -march=rv32i 38 | %.om: %.o 39 | riscv32-unknown-elf-ld $< -o $@ 40 | %-Data.bin: %.om 41 | riscv32-unknown-elf-objcopy -O binary $< $@ 42 | %-Inst.bin: %.om 43 | riscv32-unknown-elf-objcopy --dump-section .text=$@ $< 44 | %.data: %-Data.bin Bin2Data 45 | ./Bin2Data $< $@ 46 | %.inst: %-Inst.bin Bin2Data 47 | ./Bin2Data $< $@ 48 | clean: 49 | -rm -f *.o *.om *.bin *.data *.inst Bin2Data 50 | cleanASM: 51 | -rm -f *.S 52 | 53 | .SUFFIXES: 54 | 55 | -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/Utils/Bin2Data.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | void bytesToHexstring(char* bytes,int bytelength,char *hexstring,int hexstrlength) 5 | { 6 | char str2[16] = {'0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f'}; 7 | int i,j,b; 8 | char s1,s2; 9 | for (i=0,j=0;i>4); 12 | s1 = str2[b]; 13 | hexstring[j] = s1; 14 | b = 0x0f & bytes[i]; 15 | s2 = str2[b]; 16 | j++; 17 | hexstring[j] = s2; 18 | } 19 | } 20 | 21 | int main(int argc, char* argv[]) 22 | { 23 | char tmp[4]; 24 | char str[4*2+1]; 25 | if(argc!=3) 26 | { 27 | printf("Usage: ./BIN2BRAM BinFileName BRAMFileName\n"); 28 | exit(-1); 29 | } 30 | FILE* fp1=fopen(argv[1],"rb"); 31 | if(!fp1) 32 | { 33 | printf("File %s Doesn't Exist!\n",argv[1]); 34 | exit(-1); 35 | } 36 | FILE* fp2=fopen(argv[2],"wt"); 37 | if(!fp2) 38 | { 39 | printf("Failed to open File %s!\n",argv[2]); 40 | exit(-1); 41 | } 42 | // 43 | fread(tmp+3,sizeof(char),1,fp1); 44 | fread(tmp+2,sizeof(char),1,fp1); 45 | fread(tmp+1,sizeof(char),1,fp1); 46 | fread(tmp,sizeof(char),1,fp1); 47 | while(!feof(fp1)) 48 | { 49 | // 50 | bytesToHexstring(tmp,1,str,2); 51 | bytesToHexstring(tmp+1,1,str+2,2); 52 | bytesToHexstring(tmp+2,1,str+4,2); 53 | bytesToHexstring(tmp+3,1,str+6,2); 54 | fprintf(fp2,"%s\n",str); 55 | // 56 | fread(tmp+3,sizeof(char),1,fp1); 57 | fread(tmp+2,sizeof(char),1,fp1); 58 | fread(tmp+1,sizeof(char),1,fp1); 59 | fread(tmp,sizeof(char),1,fp1); 60 | } 61 | 62 | fclose(fp1); 63 | fclose(fp2); 64 | return 0; 65 | } 66 | -------------------------------------------------------------------------------- /4_ProjectDesignFiles/CPU设计图.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/adb391d983511e65417a548a62e1d4a666506756/4_ProjectDesignFiles/CPU设计图.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/Lab1-CPU设计报告.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/adb391d983511e65417a548a62e1d4a666506756/5_DetailDocuments/Lab1-CPU设计报告.docx -------------------------------------------------------------------------------- /5_DetailDocuments/Lab1-CPU设计报告.pdf: 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https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/adb391d983511e65417a548a62e1d4a666506756/5_DetailDocuments/资料/RISC-V 指令集卷2-特权级指令-中文版.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/RISCV指令集总览表格.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/adb391d983511e65417a548a62e1d4a666506756/5_DetailDocuments/资料/RISCV指令集总览表格.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/adb391d983511e65417a548a62e1d4a666506756/5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/adb391d983511e65417a548a62e1d4a666506756/5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 HaojunXia 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Computer Architecture 2019 Lab 2 | ===================== 3 | **此仓库用于发布体系结构课程2019年夏季学期的实验代码和要求，同时可用于学生的意见反馈。** 4 | 实验成绩占课程成绩的40%，实验验收方式主要为课堂当面验收和实验报告的提交。 5 | 本学期计划实验时长为10周 6 | * Lab1（4-5周）【15~20%】： 熟悉RISC-V指令集，完成RV32I指令集流水线CPU的设计报告； 7 | * Lab2（6-8周）【40%】： 配置和使用RISCV编译工具链；完成RV32I流水线CPU的Verilog代码；利用RISCV-test测试文件进行仿真和CPU功能验证 8 | * Lab3（第9周）【10%】： 将CPU烧写到FPGA上，并进行测试 9 | * Lab4（10-12周）【20~25%】： 进一步拓展流水线（待定，可能是要求实现分支预测器或简化Cache） 10 | * Lab5（第13周）【10%】：学习使用提供的Tomasulo软件模拟器和多Cache一致性软件模拟器，并完成实验报告 11 | 12 | ## 签到与补交 13 | * 学生总数220人左右，教室容量110，每周开两次实验课，内容完全一样，**可二选一参加** 14 | * 验收和报告**补交**在**一周内扣除20%成绩**，介于**一周两周之内补交扣除40%成绩**，**超过两周不予验收**。 15 | * **为了照顾对流水线不熟悉的学生和鼓励实验课出勤，每堂课设置签到。**（每次实验课开始15分钟后停止签到，实验课结束半小时前可以签离，每周两个实验时间段任选其一参加，有签到和签离就算当周满勤）。 16 | * **上周和本周连续两次满勤可以申请本周实验晚交一周不做扣分处理。**（比如Lab2阶段一验收是第6周，如果到了第6周实验课结束了实验还没做完，如果你第5周和第6周都满勤，可以在第6周签离时向助教申请晚交一周同时不扣分。）希望对流水线和verilog不熟悉的同学可以积极参与实验课，届时有问题多问问助教，助教可以一对一讲解或者统一指导。 17 | * **签到记录不以其他方式影响成绩** 18 | 19 | ## 助教统一讲解 20 | * 每周实验课的开始时间，**助教准点（14:30或18:30）**开始**本周实验指导**和**下周实验内容简单介绍** 21 | * 每次讲解5-20分钟 22 | 23 | ## 实验发布、验收和报告 24 | * **2019.3.17 Release Lab1** 25 | 请提交CPU设计报告 截止日期：2019.3.31 26 | 邮箱地址：USTC_CA2019@163.com 27 | 28 | * **2019.3.17 Release Lab2** 29 | 阶段一课堂验收 截止日期：2019.4.6 30 | 阶段二课堂验收 截止日期：2019.4.13 31 | 阶段三课堂验收 截止日期：2019.4.20 32 | 请提交实验2的实验报告 截止日期：2019.4.27 33 | 邮箱地址：USTC_CA2019@163.com 34 | 35 | ## 实验课安排 36 | * ~~lab1助教答疑 （教室容量110人，无签到）~~ 37 | ~~2019.3.21下午（14:30-17:00 电三楼406）~~ 38 | ~~2019.3.23晚（18:30-21:00 电三楼406）~~ 39 | 40 | * **lab1答案分析+Lab2预先讲解**（讲解大约20分钟）（教室容量110人，**有签到**） 41 | 2019.3.28下午（14:30-17:00 电三楼406） 42 | 2019.3.30晚（18:30-21:00 电三楼406） 43 | 44 | * lab2阶段一课堂验收时间（教室容量110人，**有签到**） 45 | 2019.4.4下午（14:30-17:00 电三楼406） 46 | 2019.4.6晚（18:30-21:00 电三楼406） 47 | 48 | * lab2阶段二课堂验收时间（教室容量110人，**有签到**） 49 | 2019.4.11下午（14:30-17:00 电三楼406） 50 | 2019.4.13晚（18:30-21:00 电三楼406） 51 | 52 | * lab2阶段三课堂验收时间（教室容量110人，**有签到**） 53 | 2019.4.18下午（14:30-17:00 电三楼406） 54 | 2019.4.20晚（18:30-21:00 电三楼406） 55 | 56 | ## 文件夹目录 57 | >**1_VerilogSourceCode** Verilog源代码 58 | >>**1_CPUCore_src CPU** CPU core的verilog代码 59 | >>**2_Simulation** 仿真用testBench代码 60 | > 61 | >**2_BRAMInputFileGenerator** 脚本文件，利用汇编文件生成对应的16进制指令流文件 62 | >**4_ProjectDesignFiles** 包含CPU的流水线模块设计图 63 | >**5_DetailDocuments** 包含每次实验的具体实验要求 64 | 65 | ## Quickstart 66 | * 新实验发布时会在群里面统一公告。 67 | * 动手做新实验时，请先进入**5_DetailDocuments**目录下，**查找本次实验对应的文档，并根据文档完成实验和试验报告。** 68 | 69 | ## 致谢 70 | 现在是2019年夏季学期学期初，体系结构课程实验刚刚开始了它的升级换代。 71 | 嵌入式系统实验室研一的同学们（部分也是体系结构课程的助教）正在努力地设计实验和提供资料。不过由于时间和能力有限，试验过程中可能存在一些问题，希望大家多多体谅，也欢迎大家在群里或者issue中提出宝贵的意见。 72 | 感谢ESLAB的同学们为本实验付出的努力，也感谢每一位参与实验的本科生的理解与支持。 --------------------------------------------------------------------------------