├── 1_VerilogSourceCode ├── 1_CPUCore_src │ ├── ALU.v │ ├── BRAMModule │ │ ├── DataRam.v │ │ └── InstructionRam.v │ ├── BranchDecisionMaking.v │ ├── ControlUnit.v │ ├── DataExt.v │ ├── EXSegReg.v │ ├── HarzardUnit.v │ ├── IDSegReg.v │ ├── IFSegReg.v │ ├── ImmOperandUnit.v │ ├── MEMSegReg.v │ ├── NPC_Generator.v │ ├── Parameters.v │ ├── RV32Core.v │ ├── RegisterFile.v │ └── WBSegReg.v └── 2_Simulation │ └── testBench.v ├── 2_BRAMInputFileGenerator ├── ExampleCode │ ├── ASMCode │ │ ├── Fibonacci.S │ │ ├── Number2Ascii.S │ │ └── QuickSort.S │ └── RISCVTest_rv32ui │ │ ├── 1testAll.S │ │ ├── 2testAll.S │ │ ├── 3testAll.S │ │ ├── add.S │ │ ├── addi.S │ │ ├── and.S │ │ ├── andi.S │ │ ├── auipc.S │ │ ├── beq.S │ │ ├── bge.S │ │ ├── bgeu.S │ │ ├── blt.S │ │ ├── bltu.S │ │ ├── bne.S │ │ ├── fence_i.S │ │ ├── include │ │ ├── encoding.h │ │ ├── riscv_test.h │ │ └── test_macros.h │ │ ├── jal.S │ │ ├── jalr.S │ │ ├── lb.S │ │ ├── lbu.S │ │ ├── lh.S │ │ ├── lhu.S │ │ ├── lui.S │ │ ├── lw.S │ │ ├── or.S │ │ ├── ori.S │ │ ├── sb.S │ │ ├── sh.S │ │ ├── simple.S │ │ ├── sll.S │ │ ├── slli.S │ │ ├── slt.S │ │ ├── slti.S │ │ ├── sltiu.S │ │ ├── sltu.S │ │ ├── sra.S │ │ ├── srai.S │ │ ├── srl.S │ │ ├── srli.S │ │ ├── sub.S │ │ ├── sw.S │ │ ├── xor.S │ │ └── xori.S ├── Makefile └── Utils │ └── Bin2Data.c ├── 4_ProjectDesignFiles └── CPU设计图.pdf ├── 5_DetailDocuments ├── Lab1-CPU设计报告.docx ├── Lab1-CPU设计报告.pdf ├── Lab2-CPU代码实现验收标准和实验报告要求.docx ├── Lab2-CPU代码实现验收标准和实验报告要求.pdf ├── 夏昊珺-Lab1总结和Lab2讲解.pptx └── 资料 │ ├── RISC-V 指令集卷1-用户级指令-中文版.pdf │ ├── RISC-V 指令集卷2-特权级指令-中文版.pdf │ ├── RISCV指令集总览表格.pdf │ ├── The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf │ └── The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf ├── LICENSE └── README.md /1_VerilogSourceCode/1_CPUCore_src/ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/ALU.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/BRAMModule/DataRam.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/DataRam.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/BRAMModule/InstructionRam.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/InstructionRam.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/BranchDecisionMaking.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/BranchDecisionMaking.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/ControlUnit.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/ControlUnit.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/DataExt.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/DataExt.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/EXSegReg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/EXSegReg.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/HarzardUnit.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/HarzardUnit.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/IDSegReg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/IDSegReg.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/IFSegReg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/IFSegReg.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/ImmOperandUnit.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/ImmOperandUnit.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/MEMSegReg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/MEMSegReg.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/NPC_Generator.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/NPC_Generator.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/Parameters.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/Parameters.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/RV32Core.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/RV32Core.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/RegisterFile.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/RegisterFile.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/1_CPUCore_src/WBSegReg.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/1_CPUCore_src/WBSegReg.v -------------------------------------------------------------------------------- /1_VerilogSourceCode/2_Simulation/testBench.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/1_VerilogSourceCode/2_Simulation/testBench.v -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/ASMCode/Fibonacci.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/ASMCode/Fibonacci.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/ASMCode/Number2Ascii.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/ASMCode/Number2Ascii.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/ASMCode/QuickSort.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/ASMCode/QuickSort.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/1testAll.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/1testAll.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/2testAll.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/2testAll.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/3testAll.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/3testAll.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/add.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/add.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/addi.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/addi.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/and.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/and.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/andi.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/andi.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/auipc.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/auipc.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/beq.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/beq.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bge.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bge.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bgeu.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bgeu.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/blt.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/blt.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bltu.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bltu.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bne.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/bne.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/fence_i.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/fence_i.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/include/encoding.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/include/encoding.h -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/include/riscv_test.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/include/riscv_test.h -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/include/test_macros.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/include/test_macros.h -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/jal.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/jal.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/jalr.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/jalr.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lb.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lb.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lbu.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lbu.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lh.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lh.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lhu.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lhu.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lui.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lui.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lw.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/lw.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/or.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/or.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/ori.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/ori.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sb.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sb.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sh.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sh.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/simple.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/simple.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sll.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sll.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slli.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slli.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slt.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slt.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slti.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/slti.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sltiu.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sltiu.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sltu.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sltu.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sra.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sra.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srai.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srai.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srl.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srl.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srli.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/srli.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sub.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sub.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sw.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/sw.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/xor.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/xor.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/xori.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/ExampleCode/RISCVTest_rv32ui/xori.S -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/Makefile -------------------------------------------------------------------------------- /2_BRAMInputFileGenerator/Utils/Bin2Data.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/2_BRAMInputFileGenerator/Utils/Bin2Data.c -------------------------------------------------------------------------------- /4_ProjectDesignFiles/CPU设计图.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/4_ProjectDesignFiles/CPU设计图.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/Lab1-CPU设计报告.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/Lab1-CPU设计报告.docx -------------------------------------------------------------------------------- /5_DetailDocuments/Lab1-CPU设计报告.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/Lab1-CPU设计报告.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/Lab2-CPU代码实现验收标准和实验报告要求.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/Lab2-CPU代码实现验收标准和实验报告要求.docx -------------------------------------------------------------------------------- /5_DetailDocuments/Lab2-CPU代码实现验收标准和实验报告要求.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/Lab2-CPU代码实现验收标准和实验报告要求.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/夏昊珺-Lab1总结和Lab2讲解.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/夏昊珺-Lab1总结和Lab2讲解.pptx -------------------------------------------------------------------------------- /5_DetailDocuments/资料/RISC-V 指令集卷1-用户级指令-中文版.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/资料/RISC-V 指令集卷1-用户级指令-中文版.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/RISC-V 指令集卷2-特权级指令-中文版.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/资料/RISC-V 指令集卷2-特权级指令-中文版.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/RISCV指令集总览表格.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/资料/RISCV指令集总览表格.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf -------------------------------------------------------------------------------- /5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/5_DetailDocuments/资料/The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jlpang1997/ComputerArchitectureLab/HEAD/README.md --------------------------------------------------------------------------------