├── .gitignore ├── COPYING ├── README.md ├── alu.v ├── alu_control.v ├── check-install.sh ├── cla_adder_4bit.v ├── cla_full_adder.v ├── control.v ├── cpu.v ├── dm.v ├── full_adder.v ├── half_adder.v ├── im.v ├── im_cached.v ├── im_slow.v ├── rc_adder.v ├── regm.v ├── regr.v └── test ├── .gitignore ├── Makefile ├── bin2hex.c ├── check-diff.pl ├── cla_adder_4bit_tb.v ├── cpu_tb.v ├── dm_tb.check ├── dm_tb.v ├── im_cached_tb.v ├── im_slow_tb.hex ├── im_slow_tb.v ├── t0001-final_value.fv.asm ├── t0001-final_value.fv.check ├── t0001-final_value.fv.hex ├── t0005-branch.asm ├── t0005-branch.check ├── t0005-branch.fv.asm ├── t0005-branch.fv.check ├── t0005-branch.fv.hex ├── t0005-branch.hex ├── t0006-jump.fv.asm ├── t0006-jump.fv.check ├── t0006-jump.fv.hex ├── t0011-operators.fv.asm ├── t0011-operators.fv.check ├── t0011-operators.fv.hex ├── t0020-stall.fv.asm ├── t0020-stall.fv.check ├── t0020-stall.fv.hex ├── t0021-stall.fv.asm ├── t0021-stall.fv.check ├── t0021-stall.fv.hex ├── t0030-lw_sw.fv.asm ├── t0030-lw_sw.fv.check ├── t0030-lw_sw.fv.hex └── t0050-hello.c /.gitignore: -------------------------------------------------------------------------------- 1 | *.bak 2 | *.htm 3 | *.log 4 | *.swp 5 | *.vcd 6 | *BAK* 7 | alu 8 | alu_control 9 | control 10 | cpu 11 | dm 12 | im 13 | im_cached 14 | im_slow 15 | log.txt 16 | pc 17 | pc_tb 18 | regm 19 | regr 20 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # NAME 2 | 3 | mips-cpu - A MIPS CPU written in Verilog 4 | 5 | # DESCRIPTION 6 | 7 | An implementation of a MIPS CPU written in Verilog. This project is in 8 | very early stages and currently only implements the most basic 9 | functionality of a MIPS CPU. 10 | 11 | - 32-bit MIPS processor 12 | 13 | - implemented in Verilog 14 | 15 | - 5 stage pipeline 16 | 17 | - static branch not taken branch predictor 18 | 19 | - branch detection in decode (stage 2) 20 | 21 | - supports stalls to avoid read after write (RAW) and other hazards 22 | 23 | - can forward from memory (stage 4) and write back (stage 5) 24 | to avoid stalls 25 | 26 | Much of the design was inspired by the book "Computer Organization and 27 | Design" by David A. Patterson and John L. Hennessy (4th ed. 2008). 28 | 29 | This project also includes a full set of test benches. These are 30 | invaluable as a quick check to verify that new changes have not 31 | disrupted previously working functionality. 32 | 33 | # REQUIREMENTS 34 | 35 | This project requires a Verilog simulator, such as [Icarus][iverilog], 36 | the Gcc compiler, and a Gcc MIPS cross compiler. To check if your 37 | system has the required programs installed run the `check-install.sh` 38 | script. 39 | 40 | $ ./check-install.sh 41 | Checking for required programs... 42 | mips-linux-gnu-objcopy 43 | mips-linux-gnu-as 44 | iverilog 45 | Please install the missing programs and retry. 46 | 47 | [iverilog]: http://iverilog.icarus.com 48 | 49 | # RUNNING TEST BENCHES 50 | 51 | The tests are located in the `verilog/test/` directory. Everything is 52 | built and run using the `make` command. 53 | 54 | make 55 | 56 | There are two parts to each test: the Verilog code, and the assembly 57 | code. The Verilog code uses a generic CPU test bench (`cpu_tb.v`) from 58 | which a specific test is built using a specific assembled .hex file. 59 | The .hex file is produced by assembling the .asm file using the Gcc MIPS 60 | cross compiler and converting it to ASCII hex suitable for use with 61 | Verilog. Then the Verilog code, using a simulator such as 62 | [Icarus Verilog][iverilog], can be run to execute the assembly 63 | instructions and produce a dump of its output (.out). Finally, the 64 | output file (.out) can be diffed against a known good output file 65 | (.check) to see if there are any differences. 66 | 67 | For more information about these steps refer the Makefile in `verilog/test/`. 68 | 69 | # AUTHOR 70 | 71 | Jeremiah Mahler
72 | 73 | 74 | # COPYRIGHT 75 | 76 | Copyright © 2015, Jeremiah Mahler. All Rights Reserved.
77 | This project is free software and released under 78 | the [GNU General Public License][gpl]. 79 | 80 | [gpl]: http://www.gnu.org/licenses/gpl.html 81 | -------------------------------------------------------------------------------- /alu.v: -------------------------------------------------------------------------------- 1 | `ifndef _alu 2 | `define _alu 3 | 4 | /*`include "rc_adder.v"*/ 5 | 6 | module alu( 7 | input [3:0] ctl, 8 | input [31:0] a, b, 9 | output reg [31:0] out, 10 | output zero); 11 | 12 | wire [31:0] sub_ab; 13 | wire [31:0] add_ab; 14 | wire oflow_add; 15 | wire oflow_sub; 16 | wire oflow; 17 | wire slt; 18 | 19 | assign zero = (0 == out); 20 | 21 | assign sub_ab = a - b; 22 | assign add_ab = a + b; 23 | /*rc_adder #(.N(32)) add0(.a(a), .b(b), .s(add_ab));*/ 24 | 25 | // overflow occurs (with 2s complement numbers) when 26 | // the operands have the same sign, but the sign of the result is 27 | // different. The actual sign is the opposite of the result. 28 | // It is also dependent on whether addition or subtraction is performed. 29 | assign oflow_add = (a[31] == b[31] && add_ab[31] != a[31]) ? 1 : 0; 30 | assign oflow_sub = (a[31] == b[31] && sub_ab[31] != a[31]) ? 1 : 0; 31 | 32 | assign oflow = (ctl == 4'b0010) ? oflow_add : oflow_sub; 33 | 34 | // set if less than, 2s compliment 32-bit numbers 35 | assign slt = oflow_sub ? ~(a[31]) : a[31]; 36 | 37 | always @(*) begin 38 | case (ctl) 39 | 4'd2: out <= add_ab; /* add */ 40 | 4'd0: out <= a & b; /* and */ 41 | 4'd12: out <= ~(a | b); /* nor */ 42 | 4'd1: out <= a | b; /* or */ 43 | 4'd7: out <= {{31{1'b0}}, slt}; /* slt */ 44 | 4'd6: out <= sub_ab; /* sub */ 45 | 4'd13: out <= a ^ b; /* xor */ 46 | default: out <= 0; 47 | endcase 48 | end 49 | 50 | endmodule 51 | 52 | `endif 53 | -------------------------------------------------------------------------------- /alu_control.v: -------------------------------------------------------------------------------- 1 | `ifndef _alu_control 2 | `define _alu_control 3 | 4 | module alu_control( 5 | input wire [5:0] funct, 6 | input wire [1:0] aluop, 7 | output reg [3:0] aluctl); 8 | 9 | reg [3:0] _funct; 10 | 11 | always @(*) begin 12 | case(funct[3:0]) 13 | 4'd0: _funct = 4'd2; /* add */ 14 | 4'd2: _funct = 4'd6; /* sub */ 15 | 4'd5: _funct = 4'd1; /* or */ 16 | 4'd6: _funct = 4'd13; /* xor */ 17 | 4'd7: _funct = 4'd12; /* nor */ 18 | 4'd10: _funct = 4'd7; /* slt */ 19 | default: _funct = 4'd0; 20 | endcase 21 | end 22 | 23 | always @(*) begin 24 | case(aluop) 25 | 2'd0: aluctl = 4'd2; /* add */ 26 | 2'd1: aluctl = 4'd6; /* sub */ 27 | 2'd2: aluctl = _funct; 28 | 2'd3: aluctl = 4'd2; /* add */ 29 | default: aluctl = 0; 30 | endcase 31 | end 32 | 33 | endmodule 34 | 35 | `endif 36 | -------------------------------------------------------------------------------- /check-install.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # NAME 5 | # 6 | # check-install.sh 7 | # 8 | # DESCRIPTION 9 | # 10 | # Run this script to check if the system has all the required 11 | # programs installed. 12 | # 13 | # Checking for required programs... 14 | # mips-linux-gnu-objcopy 15 | # mips-linux-gnu-as 16 | # iverilog 17 | # Please install the missing programs and retry. 18 | # 19 | 20 | error=0 21 | 22 | echo "Checking for required programs..." 23 | 24 | if ! which "gcc" >/dev/null ; then 25 | echo " gcc" 26 | error=1 27 | fi 28 | 29 | if ! which "mips-linux-gnu-objcopy" >/dev/null ; then 30 | echo " mips-linux-gnu-objcopy" 31 | error=1 32 | fi 33 | 34 | if ! which "mips-linux-gnu-as" >/dev/null ; then 35 | echo " mips-linux-gnu-as" 36 | error=1 37 | fi 38 | 39 | if ! which "mips-linux-gnu-gcc" >/dev/null ; then 40 | echo " gcc-mips-linux-gnu" 41 | echo " dpkg --add-architecture mips" 42 | echo " apt-get install gcc-mips-linux-gnu" 43 | error=1 44 | fi 45 | 46 | if ! which "iverilog" >/dev/null ; then 47 | echo " iverilog" 48 | error=1 49 | fi 50 | 51 | if [ "$error" -ne 0 ]; then 52 | echo "Please install the missing programs and retry." 53 | else 54 | echo "System looks ready" 55 | fi 56 | -------------------------------------------------------------------------------- /cla_adder_4bit.v: -------------------------------------------------------------------------------- 1 | /* 2 | * cla_adder_4bit.v - 4 bit carry lookahead adder 3 | */ 4 | 5 | `include "cla_full_adder.v" 6 | 7 | `ifndef _cla_adder_4bit 8 | `define _cla_adder_4bit 9 | 10 | module cla_adder_4bit( 11 | input wire [3:0] a, 12 | input wire [3:0] b, 13 | input wire c_in, 14 | output wire [3:0] s, 15 | output wire c_out); 16 | 17 | wire [4:0] c; 18 | wire [3:0] g, p; 19 | 20 | assign c[0] = c_in; 21 | assign c_out = c[4]; 22 | 23 | cla_full_adder add0(.a(a[0]), .b(b[0]), .c(c[0]), 24 | .g(g[0]), .p(p[0]), .s(s[0])); 25 | 26 | assign c[1] = g[0] | (p[0] & c[0]); 27 | 28 | cla_full_adder add1(.a(a[1]), .b(b[1]), .c(c[1]), 29 | .g(g[1]), .p(p[1]), .s(s[1])); 30 | 31 | /*assign c[2] = g[1] | (p[1] & c[1]);*/ 32 | assign c[2] = g[1] | (p[1] & (g[0] | (p[0] & c[0]))); 33 | 34 | cla_full_adder add2(.a(a[2]), .b(b[2]), .c(c[2]), 35 | .g(g[2]), .p(p[2]), .s(s[2])); 36 | 37 | /*assign c[3] = g[2] | (p[2] & c[2]);*/ 38 | assign c[3] = g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c[0]))))); 39 | 40 | cla_full_adder add3(.a(a[3]), .b(b[3]), .c(c[3]), 41 | .g(g[3]), .p(p[3]), .s(s[3])); 42 | 43 | /*assign c[4] = g[3] | (p[3] & c[3]);*/ 44 | assign c[4] = g[3] | (p[3] & 45 | (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c[0]))))))); 46 | 47 | endmodule 48 | 49 | `endif 50 | -------------------------------------------------------------------------------- /cla_full_adder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * cla_full_adder - 1 bit full adder for carry lookahead 3 | */ 4 | 5 | `ifndef _cla_full_adder 6 | `define _cla_full_adder 7 | 8 | module cla_full_adder( 9 | input a, 10 | input b, 11 | input c, 12 | output g, 13 | output p, 14 | output s); 15 | 16 | assign g = a & b; 17 | assign p = a ^ b; 18 | assign s = a ^ (b ^ c); 19 | 20 | endmodule 21 | 22 | `endif 23 | -------------------------------------------------------------------------------- /control.v: -------------------------------------------------------------------------------- 1 | `ifndef _control 2 | `define _control 3 | 4 | module control( 5 | input wire [5:0] opcode, 6 | output reg branch_eq, branch_ne, 7 | output reg [1:0] aluop, 8 | output reg memread, memwrite, memtoreg, 9 | output reg regdst, regwrite, alusrc, 10 | output reg jump); 11 | 12 | always @(*) begin 13 | /* defaults */ 14 | aluop[1:0] <= 2'b10; 15 | alusrc <= 1'b0; 16 | branch_eq <= 1'b0; 17 | branch_ne <= 1'b0; 18 | memread <= 1'b0; 19 | memtoreg <= 1'b0; 20 | memwrite <= 1'b0; 21 | regdst <= 1'b1; 22 | regwrite <= 1'b1; 23 | jump <= 1'b0; 24 | 25 | case (opcode) 26 | 6'b100011: begin /* lw */ 27 | memread <= 1'b1; 28 | regdst <= 1'b0; 29 | memtoreg <= 1'b1; 30 | aluop[1] <= 1'b0; 31 | alusrc <= 1'b1; 32 | end 33 | 6'b001000: begin /* addi */ 34 | regdst <= 1'b0; 35 | aluop[1] <= 1'b0; 36 | alusrc <= 1'b1; 37 | end 38 | 6'b000100: begin /* beq */ 39 | aluop[0] <= 1'b1; 40 | aluop[1] <= 1'b0; 41 | branch_eq <= 1'b1; 42 | regwrite <= 1'b0; 43 | end 44 | 6'b101011: begin /* sw */ 45 | memwrite <= 1'b1; 46 | aluop[1] <= 1'b0; 47 | alusrc <= 1'b1; 48 | regwrite <= 1'b0; 49 | end 50 | 6'b000101: begin /* bne */ 51 | aluop[0] <= 1'b1; 52 | aluop[1] <= 1'b0; 53 | branch_ne <= 1'b1; 54 | regwrite <= 1'b0; 55 | end 56 | 6'b000000: begin /* add */ 57 | end 58 | 6'b000010: begin /* j jump */ 59 | jump <= 1'b1; 60 | end 61 | endcase 62 | end 63 | endmodule 64 | 65 | `endif 66 | -------------------------------------------------------------------------------- /cpu.v: -------------------------------------------------------------------------------- 1 | /* 2 | * cpu. - five stage MIPS CPU. 3 | * 4 | * Many variables (wires) pass through several stages. 5 | * The naming convention used for each stage is 6 | * accomplished by appending the stage number (_s). 7 | * For example the variable named "data" which is 8 | * in stage 2 and stage 3 would be named as follows. 9 | * 10 | * wire data_s2; 11 | * wire data_s3; 12 | * 13 | * If the stage number is omitted it is assumed to 14 | * be at the stage at which the variable is first 15 | * established. 16 | */ 17 | 18 | `include "regr.v" 19 | `include "im.v" 20 | `include "regm.v" 21 | `include "control.v" 22 | `include "alu.v" 23 | `include "alu_control.v" 24 | `include "dm.v" 25 | 26 | `ifndef DEBUG_CPU_STAGES 27 | `define DEBUG_CPU_STAGES 0 28 | `endif 29 | 30 | module cpu( 31 | input wire clk); 32 | 33 | parameter NMEM = 20; // number in instruction memory 34 | parameter IM_DATA = "im_data.txt"; 35 | 36 | wire regwrite_s5; 37 | wire [4:0] wrreg_s5; 38 | wire [31:0] wrdata_s5; 39 | reg stall_s1_s2; 40 | 41 | // {{{ diagnostic outputs 42 | initial begin 43 | if (`DEBUG_CPU_STAGES) begin 44 | $display("if_pc, if_instr, id_regrs, id_regrt, ex_alua, ex_alub, ex_aluctl, mem_memdata, mem_memread, mem_memwrite, wb_regdata, wb_regwrite"); 45 | $monitor("%x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x, %x", 46 | pc, /* if_pc */ 47 | inst, /* if_instr */ 48 | data1, /* id_regrs */ 49 | data2, /* id_regrt */ 50 | data1_s3, /* data1_s3 */ 51 | alusrc_data2, /* alusrc_data2 */ 52 | aluctl, /* ex_aluctl */ 53 | data2_s4, /* mem_memdata */ 54 | memread_s4, /* mem_memread */ 55 | memwrite_s4, /* mem_memwrite */ 56 | wrdata_s5, /* wb_regdata */ 57 | regwrite_s5 /* wb_regwrite */ 58 | ); 59 | end 60 | end 61 | // }}} 62 | 63 | // {{{ flush control 64 | reg flush_s1, flush_s2, flush_s3; 65 | always @(*) begin 66 | flush_s1 <= 1'b0; 67 | flush_s2 <= 1'b0; 68 | flush_s3 <= 1'b0; 69 | if (pcsrc | jump_s4) begin 70 | flush_s1 <= 1'b1; 71 | flush_s2 <= 1'b1; 72 | flush_s3 <= 1'b1; 73 | end 74 | end 75 | // }}} 76 | 77 | // {{{ stage 1, IF (fetch) 78 | 79 | reg [31:0] pc; 80 | initial begin 81 | pc <= 32'd0; 82 | end 83 | 84 | wire [31:0] pc4; // PC + 4 85 | assign pc4 = pc + 4; 86 | 87 | always @(posedge clk) begin 88 | if (stall_s1_s2) 89 | pc <= pc; 90 | else if (pcsrc == 1'b1) 91 | pc <= baddr_s4; 92 | else if (jump_s4 == 1'b1) 93 | pc <= jaddr_s4; 94 | else 95 | pc <= pc4; 96 | end 97 | 98 | // pass PC + 4 to stage 2 99 | wire [31:0] pc4_s2; 100 | regr #(.N(32)) regr_pc4_s2(.clk(clk), 101 | .hold(stall_s1_s2), .clear(flush_s1), 102 | .in(pc4), .out(pc4_s2)); 103 | 104 | // instruction memory 105 | wire [31:0] inst; 106 | wire [31:0] inst_s2; 107 | im #(.NMEM(NMEM), .IM_DATA(IM_DATA)) 108 | im1(.clk(clk), .addr(pc), .data(inst)); 109 | regr #(.N(32)) regr_im_s2(.clk(clk), 110 | .hold(stall_s1_s2), .clear(flush_s1), 111 | .in(inst), .out(inst_s2)); 112 | 113 | // }}} 114 | 115 | // {{{ stage 2, ID (decode) 116 | 117 | // decode instruction 118 | wire [5:0] opcode; 119 | wire [4:0] rs; 120 | wire [4:0] rt; 121 | wire [4:0] rd; 122 | wire [15:0] imm; 123 | wire [4:0] shamt; 124 | wire [31:0] jaddr_s2; 125 | wire [31:0] seimm; // sign extended immediate 126 | // 127 | assign opcode = inst_s2[31:26]; 128 | assign rs = inst_s2[25:21]; 129 | assign rt = inst_s2[20:16]; 130 | assign rd = inst_s2[15:11]; 131 | assign imm = inst_s2[15:0]; 132 | assign shamt = inst_s2[10:6]; 133 | assign jaddr_s2 = {pc[31:28], inst_s2[25:0], {2{1'b0}}}; 134 | assign seimm = {{16{inst_s2[15]}}, inst_s2[15:0]}; 135 | 136 | // register memory 137 | wire [31:0] data1, data2; 138 | regm regm1(.clk(clk), .read1(rs), .read2(rt), 139 | .data1(data1), .data2(data2), 140 | .regwrite(regwrite_s5), .wrreg(wrreg_s5), 141 | .wrdata(wrdata_s5)); 142 | 143 | // pass rs to stage 3 (for forwarding) 144 | wire [4:0] rs_s3; 145 | regr #(.N(5)) regr_s2_rs(.clk(clk), .clear(1'b0), .hold(stall_s1_s2), 146 | .in(rs), .out(rs_s3)); 147 | 148 | // transfer register data to stage 3 149 | wire [31:0] data1_s3, data2_s3; 150 | regr #(.N(64)) reg_s2_mem(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2), 151 | .in({data1, data2}), 152 | .out({data1_s3, data2_s3})); 153 | 154 | // transfer seimm, rt, and rd to stage 3 155 | wire [31:0] seimm_s3; 156 | wire [4:0] rt_s3; 157 | wire [4:0] rd_s3; 158 | regr #(.N(32)) reg_s2_seimm(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2), 159 | .in(seimm), .out(seimm_s3)); 160 | regr #(.N(10)) reg_s2_rt_rd(.clk(clk), .clear(flush_s2), .hold(stall_s1_s2), 161 | .in({rt, rd}), .out({rt_s3, rd_s3})); 162 | 163 | // transfer PC + 4 to stage 3 164 | wire [31:0] pc4_s3; 165 | regr #(.N(32)) reg_pc4_s2(.clk(clk), .clear(1'b0), .hold(stall_s1_s2), 166 | .in(pc4_s2), .out(pc4_s3)); 167 | 168 | // control (opcode -> ...) 169 | wire regdst; 170 | wire branch_eq_s2; 171 | wire branch_ne_s2; 172 | wire memread; 173 | wire memwrite; 174 | wire memtoreg; 175 | wire [1:0] aluop; 176 | wire regwrite; 177 | wire alusrc; 178 | wire jump_s2; 179 | // 180 | control ctl1(.opcode(opcode), .regdst(regdst), 181 | .branch_eq(branch_eq_s2), .branch_ne(branch_ne_s2), 182 | .memread(memread), 183 | .memtoreg(memtoreg), .aluop(aluop), 184 | .memwrite(memwrite), .alusrc(alusrc), 185 | .regwrite(regwrite), .jump(jump_s2)); 186 | 187 | // shift left, seimm 188 | wire [31:0] seimm_sl2; 189 | assign seimm_sl2 = {seimm[29:0], 2'b0}; // shift left 2 bits 190 | // branch address 191 | wire [31:0] baddr_s2; 192 | assign baddr_s2 = pc4_s2 + seimm_sl2; 193 | 194 | // transfer the control signals to stage 3 195 | wire regdst_s3; 196 | wire memread_s3; 197 | wire memwrite_s3; 198 | wire memtoreg_s3; 199 | wire [1:0] aluop_s3; 200 | wire regwrite_s3; 201 | wire alusrc_s3; 202 | // A bubble is inserted by setting all the control signals 203 | // to zero (stall_s1_s2). 204 | regr #(.N(8)) reg_s2_control(.clk(clk), .clear(stall_s1_s2), .hold(1'b0), 205 | .in({regdst, memread, memwrite, 206 | memtoreg, aluop, regwrite, alusrc}), 207 | .out({regdst_s3, memread_s3, memwrite_s3, 208 | memtoreg_s3, aluop_s3, regwrite_s3, alusrc_s3})); 209 | 210 | wire branch_eq_s3, branch_ne_s3; 211 | regr #(.N(2)) branch_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0), 212 | .in({branch_eq_s2, branch_ne_s2}), 213 | .out({branch_eq_s3, branch_ne_s3})); 214 | 215 | wire [31:0] baddr_s3; 216 | regr #(.N(32)) baddr_s2_s3(.clk(clk), .clear(flush_s2), .hold(1'b0), 217 | .in(baddr_s2), .out(baddr_s3)); 218 | 219 | wire jump_s3; 220 | regr #(.N(1)) reg_jump_s3(.clk(clk), .clear(flush_s2), .hold(1'b0), 221 | .in(jump_s2), 222 | .out(jump_s3)); 223 | 224 | wire [31:0] jaddr_s3; 225 | regr #(.N(32)) reg_jaddr_s3(.clk(clk), .clear(flush_s2), .hold(1'b0), 226 | .in(jaddr_s2), .out(jaddr_s3)); 227 | // }}} 228 | 229 | // {{{ stage 3, EX (execute) 230 | 231 | // pass through some control signals to stage 4 232 | wire regwrite_s4; 233 | wire memtoreg_s4; 234 | wire memread_s4; 235 | wire memwrite_s4; 236 | regr #(.N(4)) reg_s3(.clk(clk), .clear(flush_s2), .hold(1'b0), 237 | .in({regwrite_s3, memtoreg_s3, memread_s3, 238 | memwrite_s3}), 239 | .out({regwrite_s4, memtoreg_s4, memread_s4, 240 | memwrite_s4})); 241 | 242 | // ALU 243 | // second ALU input can come from an immediate value or data 244 | wire [31:0] alusrc_data2; 245 | assign alusrc_data2 = (alusrc_s3) ? seimm_s3 : fw_data2_s3; 246 | // ALU control 247 | wire [3:0] aluctl; 248 | wire [5:0] funct; 249 | assign funct = seimm_s3[5:0]; 250 | alu_control alu_ctl1(.funct(funct), .aluop(aluop_s3), .aluctl(aluctl)); 251 | // ALU 252 | wire [31:0] alurslt; 253 | reg [31:0] fw_data1_s3; 254 | always @(*) 255 | case (forward_a) 256 | 2'd1: fw_data1_s3 = alurslt_s4; 257 | 2'd2: fw_data1_s3 = wrdata_s5; 258 | default: fw_data1_s3 = data1_s3; 259 | endcase 260 | wire zero_s3; 261 | alu alu1(.ctl(aluctl), .a(fw_data1_s3), .b(alusrc_data2), .out(alurslt), 262 | .zero(zero_s3)); 263 | wire zero_s4; 264 | regr #(.N(1)) reg_zero_s3_s4(.clk(clk), .clear(1'b0), .hold(1'b0), 265 | .in(zero_s3), .out(zero_s4)); 266 | 267 | // pass ALU result and zero to stage 4 268 | wire [31:0] alurslt_s4; 269 | regr #(.N(32)) reg_alurslt(.clk(clk), .clear(flush_s3), .hold(1'b0), 270 | .in({alurslt}), 271 | .out({alurslt_s4})); 272 | 273 | // pass data2 to stage 4 274 | wire [31:0] data2_s4; 275 | reg [31:0] fw_data2_s3; 276 | always @(*) 277 | case (forward_b) 278 | 2'd1: fw_data2_s3 = alurslt_s4; 279 | 2'd2: fw_data2_s3 = wrdata_s5; 280 | default: fw_data2_s3 = data2_s3; 281 | endcase 282 | regr #(.N(32)) reg_data2_s3(.clk(clk), .clear(flush_s3), .hold(1'b0), 283 | .in(fw_data2_s3), .out(data2_s4)); 284 | 285 | // write register 286 | wire [4:0] wrreg; 287 | wire [4:0] wrreg_s4; 288 | assign wrreg = (regdst_s3) ? rd_s3 : rt_s3; 289 | // pass to stage 4 290 | regr #(.N(5)) reg_wrreg(.clk(clk), .clear(flush_s3), .hold(1'b0), 291 | .in(wrreg), .out(wrreg_s4)); 292 | 293 | wire branch_eq_s4, branch_ne_s4; 294 | regr #(.N(2)) branch_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0), 295 | .in({branch_eq_s3, branch_ne_s3}), 296 | .out({branch_eq_s4, branch_ne_s4})); 297 | 298 | wire [31:0] baddr_s4; 299 | regr #(.N(32)) baddr_s3_s4(.clk(clk), .clear(flush_s3), .hold(1'b0), 300 | .in(baddr_s3), .out(baddr_s4)); 301 | 302 | wire jump_s4; 303 | regr #(.N(1)) reg_jump_s4(.clk(clk), .clear(flush_s3), .hold(1'b0), 304 | .in(jump_s3), 305 | .out(jump_s4)); 306 | 307 | wire [31:0] jaddr_s4; 308 | regr #(.N(32)) reg_jaddr_s4(.clk(clk), .clear(flush_s3), .hold(1'b0), 309 | .in(jaddr_s3), .out(jaddr_s4)); 310 | // }}} 311 | 312 | // {{{ stage 4, MEM (memory) 313 | 314 | // pass regwrite and memtoreg to stage 5 315 | wire memtoreg_s5; 316 | regr #(.N(2)) reg_regwrite_s4(.clk(clk), .clear(1'b0), .hold(1'b0), 317 | .in({regwrite_s4, memtoreg_s4}), 318 | .out({regwrite_s5, memtoreg_s5})); 319 | 320 | // data memory 321 | wire [31:0] rdata; 322 | dm dm1(.clk(clk), .addr(alurslt_s4[8:2]), .rd(memread_s4), .wr(memwrite_s4), 323 | .wdata(data2_s4), .rdata(rdata)); 324 | // pass read data to stage 5 325 | wire [31:0] rdata_s5; 326 | regr #(.N(32)) reg_rdata_s4(.clk(clk), .clear(1'b0), .hold(1'b0), 327 | .in(rdata), 328 | .out(rdata_s5)); 329 | 330 | // pass alurslt to stage 5 331 | wire [31:0] alurslt_s5; 332 | regr #(.N(32)) reg_alurslt_s4(.clk(clk), .clear(1'b0), .hold(1'b0), 333 | .in(alurslt_s4), 334 | .out(alurslt_s5)); 335 | 336 | // pass wrreg to stage 5 337 | regr #(.N(5)) reg_wrreg_s4(.clk(clk), .clear(1'b0), .hold(1'b0), 338 | .in(wrreg_s4), 339 | .out(wrreg_s5)); 340 | 341 | // branch 342 | reg pcsrc; 343 | always @(*) begin 344 | case (1'b1) 345 | branch_eq_s4: pcsrc <= zero_s4; 346 | branch_ne_s4: pcsrc <= ~(zero_s4); 347 | default: pcsrc <= 1'b0; 348 | endcase 349 | end 350 | // }}} 351 | 352 | // {{{ stage 5, WB (write back) 353 | 354 | assign wrdata_s5 = (memtoreg_s5 == 1'b1) ? rdata_s5 : alurslt_s5; 355 | 356 | // }}} 357 | 358 | // {{{ forwarding 359 | 360 | // stage 3 (MEM) -> stage 2 (EX) 361 | // stage 4 (WB) -> stage 2 (EX) 362 | 363 | reg [1:0] forward_a; 364 | reg [1:0] forward_b; 365 | always @(*) begin 366 | // If the previous instruction (stage 4) would write, 367 | // and it is a value we want to read (stage 3), forward it. 368 | 369 | // data1 input to ALU 370 | if ((regwrite_s4 == 1'b1) && (wrreg_s4 == rs_s3)) begin 371 | forward_a <= 2'd1; // stage 4 372 | end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rs_s3)) begin 373 | forward_a <= 2'd2; // stage 5 374 | end else 375 | forward_a <= 2'd0; // no forwarding 376 | 377 | // data2 input to ALU 378 | if ((regwrite_s4 == 1'b1) & (wrreg_s4 == rt_s3)) begin 379 | forward_b <= 2'd1; // stage 5 380 | end else if ((regwrite_s5 == 1'b1) && (wrreg_s5 == rt_s3)) begin 381 | forward_b <= 2'd2; // stage 5 382 | end else 383 | forward_b <= 2'd0; // no forwarding 384 | end 385 | // }}} 386 | 387 | // {{{ load use data hazard detection, signal stall 388 | 389 | /* If an operation in stage 4 (MEM) loads from memory (e.g. lw) 390 | * and the operation in stage 3 (EX) depends on this value, 391 | * a stall must be performed. The memory read cannot 392 | * be forwarded because memory access is too slow. It can 393 | * be forwarded from stage 5 (WB) after a stall. 394 | * 395 | * lw $1, 16($10) ; I-type, rt_s3 = $1, memread_s3 = 1 396 | * sw $1, 32($12) ; I-type, rt_s2 = $1, memread_s2 = 0 397 | * 398 | * lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1 399 | * sw $2, 32($1) ; I-type, rt_s2 = $2, rs_s2 = $1, memread_s2 = 0 400 | * 401 | * lw $1, 16($3) ; I-type, rt_s3 = $1, memread_s3 = 1 402 | * add $2, $1, $1 ; R-type, rs_s2 = $1, rt_s2 = $1, memread_s2 = 0 403 | */ 404 | always @(*) begin 405 | if (memread_s3 == 1'b1 && ((rt == rt_s3) || (rs == rt_s3)) ) begin 406 | stall_s1_s2 <= 1'b1; // perform a stall 407 | end else 408 | stall_s1_s2 <= 1'b0; // no stall 409 | end 410 | // }}} 411 | 412 | endmodule 413 | 414 | // vim:foldmethod=marker 415 | -------------------------------------------------------------------------------- /dm.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Data Memory. 3 | * 4 | * 32-bit data with a 7 bit address (128 entries). 5 | * 6 | * The read and write operations operate somewhat independently. 7 | * 8 | * Any time the read signal (rd) is high the data stored at the 9 | * given address (addr) will be placed on 'rdata'. 10 | * 11 | * Any time the write signal (wr) is high the data on 'wdata' will 12 | * be stored at the given address (addr). 13 | * 14 | * If a simultaneous read/write is performed the data written 15 | * can be immediately read out. 16 | */ 17 | 18 | `ifndef _dm 19 | `define _dm 20 | 21 | module dm( 22 | input wire clk, 23 | input wire [6:0] addr, 24 | input wire rd, wr, 25 | input wire [31:0] wdata, 26 | output wire [31:0] rdata); 27 | 28 | reg [31:0] mem [0:127]; // 32-bit memory with 128 entries 29 | 30 | always @(posedge clk) begin 31 | if (wr) begin 32 | mem[addr] <= wdata; 33 | end 34 | end 35 | 36 | assign rdata = wr ? wdata : mem[addr][31:0]; 37 | // During a write, avoid the one cycle delay by reading from 'wdata' 38 | 39 | endmodule 40 | 41 | `endif 42 | -------------------------------------------------------------------------------- /full_adder.v: -------------------------------------------------------------------------------- 1 | `ifndef _full_adder 2 | `define _full_adder 3 | 4 | module full_adder( 5 | input a, 6 | input b, 7 | input c_in, 8 | output s, 9 | output c); 10 | 11 | assign s = a ^ (b ^ c_in); 12 | assign c = (a & b) | (c_in & (a | b)); 13 | 14 | endmodule 15 | 16 | `endif 17 | -------------------------------------------------------------------------------- /half_adder.v: -------------------------------------------------------------------------------- 1 | `ifndef _half_adder 2 | `define _half_adder 3 | 4 | module half_adder( 5 | input a, 6 | input b, 7 | output s, 8 | output c); 9 | 10 | assign s = a ^ b; 11 | assign c = a & b; 12 | 13 | endmodule 14 | 15 | `endif 16 | -------------------------------------------------------------------------------- /im.v: -------------------------------------------------------------------------------- 1 | /* 2 | * im.v - instruction memory 3 | * 4 | * Given a 32-bit address the data is latched and driven 5 | * on the rising edge of the clock. 6 | * 7 | * Currently it supports 7 address bits resulting in 8 | * 128 bytes of memory. The lowest two bits are assumed 9 | * to be byte indexes and ignored. Bits 8 down to 2 10 | * are used to construct the address. 11 | * 12 | * The memory is initialized using the Verilog $readmemh 13 | * (read memory in hex format, ascii) operation. 14 | * The file to read from can be configured using .IM_DATA 15 | * parameter and it defaults to "im_data.txt". 16 | * The number of memory records can be specified using the 17 | * .NMEM parameter. This should be the same as the number 18 | * of lines in the file (wc -l im_data.txt). 19 | */ 20 | 21 | `ifndef _im 22 | `define _im 23 | 24 | module im( 25 | input wire clk, 26 | input wire [31:0] addr, 27 | output wire [31:0] data); 28 | 29 | parameter NMEM = 128; // Number of memory entries, 30 | // not the same as the memory size 31 | parameter IM_DATA = "im_data.txt"; // file to read data from 32 | 33 | reg [31:0] mem [0:127]; // 32-bit memory with 128 entries 34 | 35 | initial begin 36 | $readmemh(IM_DATA, mem, 0, NMEM-1); 37 | end 38 | 39 | assign data = mem[addr[8:2]][31:0]; 40 | endmodule 41 | 42 | `endif 43 | -------------------------------------------------------------------------------- /im_cached.v: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * im_cached 4 | * 5 | * Read only 4 block direct mapped cache with one 6 | * word (32-bit) blocks. 7 | * Interfaces to the slow instruction memory (im_slow). 8 | * 9 | * On the next clock edge after an address has been asserted, 10 | * data is valid and can be read if hit is high, otherwise 11 | * hit will be low and additional cycles will be needed to 12 | * retrieve the data from (slow) memory. 13 | */ 14 | 15 | `ifndef _im_cached 16 | `define _im_cached 17 | 18 | `include "im_slow.v" 19 | 20 | module im_cached( 21 | input wire clk, 22 | input wire [31:0] addr, 23 | output wire hit, 24 | output wire [31:0] data); 25 | 26 | // parameters to im_slow.v and im.v, 27 | // refer to the documentation of those modules 28 | parameter NMEM = 128; 29 | parameter IM_DATA = "im_data.txt"; 30 | parameter MEM_SIZE = 128; 31 | parameter ND = 3; 32 | 33 | wire rdy; 34 | wire [31:0] mem_data; 35 | 36 | im_slow #(.NMEM(NMEM), .IM_DATA(IM_DATA), .ND(ND)) 37 | ims1(.clk(clk), .addr(addr), .rdy(rdy), .data(mem_data)); 38 | 39 | // 40 | // ADDRESS 41 | // 31 4 3 2 1 0 42 | // +------------+-----------+-----+ 43 | // | tag | index | X X | 44 | // +------------+-----------+-----+ 45 | // 46 | // X X - byte index 47 | // 48 | // tag: 28 bits 49 | // index: 2 bits (4 blocks) 50 | // 51 | // BLOCK 52 | // 60 59 32 31 0 53 | // +---+---------+--------+ 54 | // | V | tag | word | 55 | // +---+---------+--------+ 56 | // 57 | 58 | // decode address 59 | //wire [1:0] byte_idx; 60 | wire [1:0] index; 61 | wire [27:0] addr_tag; 62 | // 63 | //assign byte_idx = addr[1:0]; 64 | assign index = addr[3:2]; 65 | assign addr_tag = addr[31:4]; 66 | 67 | reg [60:0] block; // selected block 68 | reg [60:0] block0; 69 | reg [60:0] block1; 70 | reg [60:0] block2; 71 | reg [60:0] block3; 72 | 73 | // initialize valid bit to false 74 | initial begin 75 | block0[60] = 1'b0; 76 | block1[60] = 1'b0; 77 | block2[60] = 1'b0; 78 | block3[60] = 1'b0; 79 | end 80 | 81 | // select block in cache to read from 82 | always @(*) begin 83 | case (index) 84 | 0: block = block0; 85 | 1: block = block1; 86 | 2: block = block2; 87 | //3: block = block3; 88 | default: block = block3; 89 | endcase 90 | end 91 | 92 | // decode block 93 | wire valid; 94 | wire [27:0] block_tag; 95 | //wire [31:0] block_data; 96 | // 97 | assign valid = block[60]; 98 | assign block_tag = block[59:32]; 99 | //assign block_data = block[31:0]; 100 | // 101 | //assign data = block_data; 102 | assign data = (rdy == 1'b1) ? mem_data : block[31:0]; 103 | 104 | // Update block from memory, 105 | // or hold current value. 106 | // 107 | // Anytime the address has been asserted long 108 | // enough for the memory to become ready (rdy) 109 | // the cache will be updated. 110 | always @(posedge clk) begin 111 | // default 112 | block0 <= block0; 113 | block1 <= block1; 114 | block2 <= block2; 115 | block3 <= block3; 116 | 117 | if (index == 2'd0 && rdy) 118 | block0 <= {1'b1, addr_tag, mem_data}; // { valid, tag, data } 119 | 120 | if (index == 2'd1 && rdy) 121 | block1 <= {1'b1, addr_tag, mem_data}; 122 | 123 | if (index == 2'd2 && rdy) 124 | block2 <= {1'b1, addr_tag, mem_data}; 125 | 126 | if (index == 2'd3 && rdy) 127 | block3 <= {1'b1, addr_tag, mem_data}; 128 | end 129 | 130 | assign hit = (rdy || (valid && (addr_tag == block_tag))) ? 1'b1 : 1'b0; 131 | 132 | endmodule 133 | 134 | `endif 135 | -------------------------------------------------------------------------------- /im_slow.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Slow version of Instruction Memory 3 | * 4 | * This slow version of instruction memory takes 5 | * several cycles (param ND) to produce a valid result (rdy = 1). 6 | * This attempts to be a more realistic representation of memory. 7 | * And this is useful along with a cache implementation. 8 | * 9 | * The operation is the same as 'im.v' except with the 10 | * addition of a 'rdy' signal which will be set after 11 | * the address has been held for ND (parameter ND) clock 12 | * cycles. ND must have a minimum size of 2. 13 | */ 14 | 15 | `ifndef _im_slow 16 | `define _im_slow 17 | 18 | `include "im.v" 19 | 20 | module im_slow( 21 | input wire clk, 22 | input wire [31:0] addr, 23 | output wire rdy, 24 | output wire [31:0] data); 25 | 26 | parameter NMEM = 128; // Number of memory entries, 27 | // not the same as the memory size 28 | parameter IM_DATA = "im_data.txt"; // file to read data from 29 | 30 | parameter MEM_SIZE = 128; 31 | 32 | parameter ND = 3; // address held delay 33 | 34 | // fast (no delay) instruction memory 35 | wire [31:0] raw_data; 36 | im #(.NMEM(NMEM), .IM_DATA(IM_DATA)) 37 | im1(.clk(clk), .addr(addr), .data(raw_data)); 38 | 39 | // The address must be held for ND clock cycles 40 | // before it is ready (rdy = 1). 41 | // 42 | // Here this is accomplished with a shift register. 43 | // When address is equal to the previous address 44 | // the lowest bit is set. When all the bits in 45 | // the shift register are set, the address has 46 | // been held long enough. 47 | // 48 | reg [31:0] last_addr; 49 | 50 | wire cur_equal; 51 | assign cur_equal = (last_addr == addr) ? 1'b1 : 1'b0; 52 | 53 | reg [ND-1:0] next_equals; 54 | wire [ND-1:0] equals; 55 | assign equals = {next_equals[ND-2:0], cur_equal}; 56 | 57 | always @(posedge clk) begin 58 | last_addr <= addr; 59 | 60 | next_equals <= equals; 61 | end 62 | 63 | // When all the equals bits are set, it is ready 64 | assign rdy = (&equals) ? 1'b1 : 1'b0; 65 | 66 | // only produce valid data when ready 67 | assign data = (rdy) ? raw_data : {32{1'b0}}; 68 | 69 | endmodule 70 | 71 | `endif 72 | -------------------------------------------------------------------------------- /rc_adder.v: -------------------------------------------------------------------------------- 1 | /* 2 | * rc_adder.v - ripple carry adder 3 | */ 4 | 5 | `include "full_adder.v" 6 | `include "half_adder.v" 7 | 8 | `ifndef _rc_adder 9 | `define _rc_adder 10 | 11 | module rc_adder( 12 | input wire [N-1:0] a, 13 | input wire [N-1:0] b, 14 | output wire [N-1:0] s, 15 | output wire c); 16 | 17 | parameter N = 32; /* number of bits */ 18 | 19 | wire [N-1:0] _c; 20 | 21 | assign c = _c[N-1]; 22 | 23 | half_adder add0(.a(a[0]), .b(b[0]), .s(s[0]), 24 | .c(_c[0])); 25 | 26 | genvar i; 27 | generate 28 | for (i = 1; i < N; i = i + 1) begin : gen_adder 29 | full_adder addN(.a(a[i]), .b(b[i]), .s(s[i]), 30 | .c_in(_c[i - 1]), .c(_c[i])); 31 | end 32 | endgenerate 33 | 34 | endmodule 35 | 36 | `endif 37 | -------------------------------------------------------------------------------- /regm.v: -------------------------------------------------------------------------------- 1 | /* 2 | * regm - register memory 3 | * 4 | * A 32-bit register memory. Two registers can be read at once. The 5 | * variables `read1` and `read2` specify which registers to read. The 6 | * output is placed in `data1` and `data2`. 7 | * 8 | * If `regwrite` is high, the value in `wrdata` will be written to the 9 | * register in `wrreg`. 10 | * 11 | * The register at address $zero is treated special, it ignores 12 | * assignment and the value read is always zero. 13 | * 14 | * If the register being read is the same as that being written, the 15 | * value being written will be available immediately without a one 16 | * cycle delay. 17 | * 18 | */ 19 | 20 | `ifndef _regm 21 | `define _regm 22 | 23 | `ifndef DEBUG_CPU_REG 24 | `define DEBUG_CPU_REG 0 25 | `endif 26 | 27 | module regm( 28 | input wire clk, 29 | input wire [4:0] read1, read2, 30 | output wire [31:0] data1, data2, 31 | input wire regwrite, 32 | input wire [4:0] wrreg, 33 | input wire [31:0] wrdata); 34 | 35 | reg [31:0] mem [0:31]; // 32-bit memory with 32 entries 36 | 37 | reg [31:0] _data1, _data2; 38 | 39 | initial begin 40 | if (`DEBUG_CPU_REG) begin 41 | $display(" $v0, $v1, $t0, $t1, $t2, $t3, $t4, $t5, $t6, $t7"); 42 | $monitor("%x, %x, %x, %x, %x, %x, %x, %x, %x, %x", 43 | mem[2][31:0], /* $v0 */ 44 | mem[3][31:0], /* $v1 */ 45 | mem[8][31:0], /* $t0 */ 46 | mem[9][31:0], /* $t1 */ 47 | mem[10][31:0], /* $t2 */ 48 | mem[11][31:0], /* $t3 */ 49 | mem[12][31:0], /* $t4 */ 50 | mem[13][31:0], /* $t5 */ 51 | mem[14][31:0], /* $t6 */ 52 | mem[15][31:0], /* $t7 */ 53 | ); 54 | end 55 | end 56 | 57 | always @(*) begin 58 | if (read1 == 5'd0) 59 | _data1 = 32'd0; 60 | else if ((read1 == wrreg) && regwrite) 61 | _data1 = wrdata; 62 | else 63 | _data1 = mem[read1][31:0]; 64 | end 65 | 66 | always @(*) begin 67 | if (read2 == 5'd0) 68 | _data2 = 32'd0; 69 | else if ((read2 == wrreg) && regwrite) 70 | _data2 = wrdata; 71 | else 72 | _data2 = mem[read2][31:0]; 73 | end 74 | 75 | assign data1 = _data1; 76 | assign data2 = _data2; 77 | 78 | always @(posedge clk) begin 79 | if (regwrite && wrreg != 5'd0) begin 80 | // write a non $zero register 81 | mem[wrreg] <= wrdata; 82 | end 83 | end 84 | endmodule 85 | 86 | `endif 87 | -------------------------------------------------------------------------------- /regr.v: -------------------------------------------------------------------------------- 1 | /* 2 | * NAME 3 | * 4 | * regr - register of data that can be held or cleared 5 | * 6 | * DESCRIPTION 7 | * 8 | * The regr (register) module can be used to store data in the current 9 | * cylcle so it will be output on the next cycle. Signals are also 10 | * provided to hold the data or clear it. The hold and clear signals 11 | * are both synchronous with the clock. 12 | * 13 | * The first example creates a 8-bit register. The clear and hold 14 | * signals are taken from elsewhere. 15 | * 16 | * wire [7:0] data_s1; 17 | * wire [7:0] data_s2; 18 | * 19 | * regr #(.N(8)) r1(.clk(clk), .clear(clear), .hold(hold), 20 | * .in(data_s1), .out(data_s2)) 21 | * 22 | * Multiple signals can be grouped together using array notation. 23 | * 24 | * regr #(.N(8)) r1(.clk(clk), .clear(clear), .hold(hold), 25 | * .in({x1, x2}), .out({y1, y2})) 26 | */ 27 | 28 | `ifndef _regr 29 | `define _regr 30 | 31 | module regr ( 32 | input clk, 33 | input clear, 34 | input hold, 35 | input wire [N-1:0] in, 36 | output reg [N-1:0] out); 37 | 38 | parameter N = 1; 39 | 40 | always @(posedge clk) begin 41 | if (clear) 42 | out <= {N{1'b0}}; 43 | else if (hold) 44 | out <= out; 45 | else 46 | out <= in; 47 | end 48 | endmodule 49 | 50 | `endif 51 | -------------------------------------------------------------------------------- /test/.gitignore: -------------------------------------------------------------------------------- 1 | *.out 2 | *.vcd 3 | t*-* 4 | !t*-*.check 5 | !t*-*.asm 6 | !t*-*.c 7 | *.text 8 | *.elf 9 | bin2hex 10 | cla_adder_4bit_tb 11 | -------------------------------------------------------------------------------- /test/Makefile: -------------------------------------------------------------------------------- 1 | 2 | OBJCOPY=mips-linux-gnu-objcopy 3 | AS=mips-linux-gnu-as 4 | GCC=mips-linux-gnu-gcc 5 | 6 | OBJS = $(shell ls t*.asm | sed -e 's/.asm//') 7 | OBJS += $(shell ls t*.c | sed -e 's/.c//') 8 | 9 | OUTS = $(shell ls t*.asm | sed -e 's/.asm/.out/') 10 | #OUTS = $(shell ls t*.c | sed -e 's/.c/.out/') 11 | 12 | HEXS = $(shell ls t*.asm | sed -e 's/.asm/.hex/') 13 | HEXS += $(shell ls t*.c | sed -e 's/.c/.hex/') 14 | 15 | all: $(OBJS) $(ELFS) $(OUTS) $(HEXS) check 16 | 17 | bin2hex: bin2hex.c 18 | gcc -Wall $< -o $@ 19 | 20 | # prevent Make from removing these intermediate files 21 | .PRECIOUS: %.elf %.text 22 | 23 | # To get a dump of the assembly code: 24 | #mips-linux-gnu-objdump --section=.text -D .elf 25 | 26 | # cancel implicit rule for .c -> (exe) 27 | %: %.c 28 | 29 | %.elf: %.c 30 | $(GCC) -O0 -mips32 -nostdlib -ffreestanding -o $@ $< 31 | 32 | %.elf: %.asm 33 | $(AS) -O0 -mips32 -o $@ $< 34 | 35 | # extract just the .text section 36 | %.text: %.elf 37 | $(OBJCOPY) -O binary --only-section=.text $< $@ 38 | 39 | %.hex: %.text bin2hex 40 | ./bin2hex $< > $@ 41 | 42 | # build the simulation executable 43 | %: %.hex cpu_tb.v 44 | iverilog -DIM_DATA_FILE="\"$<\"" \ 45 | -DNUM_IM_DATA=`wc -l $< | awk {'print $$1'}` \ 46 | -DDUMP_FILE="\"$@.vcd\"" \ 47 | -DDEBUG_CPU_STAGES="1" \ 48 | -I../ -g2005 \ 49 | -o $@ \ 50 | cpu_tb.v 51 | 52 | %.fv: %.fv.hex cpu_tb.v 53 | iverilog -DIM_DATA_FILE="\"$<\"" \ 54 | -DNUM_IM_DATA=`wc -l $< | awk {'print $$1'}` \ 55 | -DDUMP_FILE="\"$@.vcd\"" \ 56 | -DDEBUG_CPU_REG="1" \ 57 | -I../ -g2005 \ 58 | -o $@ \ 59 | cpu_tb.v 60 | 61 | %.out: % 62 | ./$< > $<.out 63 | 64 | %.fv.out: %.fv 65 | ./$< | tail -n 1 > $<.out 66 | 67 | check: 68 | ./check-diff.pl $(OUTS) 69 | 70 | clean: 71 | -rm -f $(OBJS) 72 | -rm -f *.vcd 73 | -rm -f *.out 74 | -rm -f t*.hex 75 | -rm -f *.elf 76 | -rm -f *.text 77 | -------------------------------------------------------------------------------- /test/bin2hex.c: -------------------------------------------------------------------------------- 1 | /* 2 | * NAME 3 | * 4 | * bin2hex 5 | * 6 | * DESCRIPTION 7 | * 8 | * Given a binary file, convert each byte to ascii hex, with one word 9 | * per line. 10 | * 11 | * bin2hex t0001-no_hazard.elf > t0001-no_hazard.hex 12 | * 13 | * Verilog simulators can read ascii hex values but not binary. This 14 | * program does this conversion so it can be used with Verilog. 15 | * 16 | * AUTHOR 17 | * 18 | * Jeremiah Mahler 19 | * 20 | */ 21 | 22 | #include 23 | #include 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | 30 | int main(int argc, char *argv[]) 31 | { 32 | uint8_t byte; 33 | int inputfd; 34 | ssize_t len; 35 | int n; 36 | int byte_nl = 4; /* break with newline every 4 bytes */ 37 | 38 | if (2 != argc) { 39 | fprintf(stderr, "usage: %s > \n", argv[0]); 40 | return 1; 41 | } 42 | 43 | inputfd = open(argv[1], O_RDONLY); 44 | if (inputfd < 0) { 45 | perror("open"); 46 | return 1; 47 | } 48 | 49 | n = 1; 50 | while (1) { 51 | len = read(inputfd, &byte, sizeof(byte)); 52 | if (len < 0) { 53 | perror("read"); 54 | return 1; 55 | } else if (0 == len) { 56 | break; 57 | } 58 | 59 | printf("%02X", byte); 60 | 61 | /* add newline every byte_nl bytes */ 62 | if (0 == n % byte_nl) { 63 | printf("\n"); 64 | } 65 | 66 | n++; 67 | } 68 | 69 | close(inputfd); 70 | 71 | return 0; 72 | } 73 | -------------------------------------------------------------------------------- /test/check-diff.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | use strict; 3 | 4 | =head1 5 | 6 | Given a set of output files, this will run a diff against the .check 7 | file. If they are the same the test passes, otherwise it fails. 8 | 9 | ./check-diff.pl t0001-no_hazard.out t0005-branch.out 10 | 11 | =cut 12 | 13 | my %test_info = ( 14 | passed => 0, 15 | failed => 0, 16 | ); 17 | 18 | foreach my $check_file_out (@ARGV) { 19 | my $check_file_check = $check_file_out; 20 | $check_file_check =~ s/\.out$/.check/; 21 | 22 | my $test_name = $check_file_out; 23 | $test_name =~ s/\.out$//; 24 | 25 | my $res = system("diff $check_file_out $check_file_check 1>/dev/null 2>&1"); 26 | 27 | if ($res) { 28 | print STDERR "test '$test_name' failed\n"; 29 | $test_info{'failed'}++; 30 | } else { 31 | $test_info{'passed'}++; 32 | } 33 | } 34 | 35 | $test_info{'total'} = $test_info{'passed'} + $test_info{'failed'}; 36 | 37 | print $test_info{'total'} . " tests run, " . $test_info{'passed'} . 38 | " passed, " . $test_info{'failed'} . " failed.\n"; 39 | 40 | -------------------------------------------------------------------------------- /test/cla_adder_4bit_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `include "cla_adder_4bit.v" 3 | 4 | module cla_adder_4bit_tb; 5 | 6 | integer i = 0; 7 | 8 | reg clk; 9 | 10 | reg [3:0] a, b; 11 | wire [3:0] s; 12 | wire c; 13 | 14 | cla_adder_4bit add0(.a(a), .b(b), .c_in(1'b0), .s(s), .c_out(c)); 15 | 16 | always begin 17 | clk <= ~clk; 18 | #5; 19 | end 20 | 21 | initial begin 22 | $dumpfile("cla_adder_4bit_tb.vcd"); 23 | $dumpvars(0, cla_adder_4bit_tb); 24 | 25 | clk <= 1'b0; 26 | 27 | a <= 4'd7; 28 | b <= 4'd6; 29 | @(posedge clk); 30 | 31 | a <= 4'd7; 32 | b <= 4'd8; 33 | @(posedge clk); 34 | 35 | a <= 4'd8; 36 | b <= 4'd8; 37 | @(posedge clk); 38 | 39 | a <= 4'd15; 40 | b <= 4'd8; 41 | @(posedge clk); 42 | 43 | for (i = 0; i < 3; i = i + 1) begin 44 | @(posedge clk); 45 | end 46 | 47 | $finish; 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /test/cpu_tb.v: -------------------------------------------------------------------------------- 1 | /* 2 | * NAME 3 | * 4 | * cpu_tb.v - generic cpu test bench 5 | * 6 | * DESCRIPTION 7 | * 8 | * This generic cpu test bench can be used to run a program, which is in 9 | * ASCII hex format, and output the results. 10 | * 11 | * Configuration is done by setting preprocessor defines at compile 12 | * time. The result is an executable for that specific test. 13 | * 14 | * iverilog -DIM_DATA_FILE="\"t0001-no_hazard.hex\"" \ 15 | * -DNUM_IM_DATA=`wc -l t0001-no_hazard.hex | awk {'print $$1'}` \ 16 | * -DDUMP_FILE="\"t0001-no_hazard.vcd\"" \ 17 | * -I../ -g2005 \ 18 | * -o t0001-no_hazard \ 19 | * cpu_tb.v 20 | * 21 | * Then it can be run in the usual manner. $monitor variables will be 22 | * output to STDOUT and a .vcd for use with Gtkwave will be output to 23 | * 'DUMP_FILE'. 24 | * 25 | * ./t0001-no_hazard > t0001-no_hazard.out 26 | */ 27 | 28 | `include "cpu.v" 29 | 30 | module cpu_tb; 31 | 32 | integer i = 0; 33 | 34 | reg clk; 35 | 36 | cpu #(.NMEM(`NUM_IM_DATA), .IM_DATA(`IM_DATA_FILE)) 37 | mips1(.clk(clk)); 38 | 39 | always begin 40 | clk <= ~clk; 41 | #5; 42 | end 43 | 44 | initial begin 45 | $dumpfile(`DUMP_FILE); 46 | $dumpvars(0, cpu_tb); 47 | 48 | clk <= 1'b0; 49 | 50 | /* cpu will $display output when `DEBUG_CPU_STAGES is on */ 51 | 52 | // Run all the lines, plus 5 extra to finish off the pipeline. 53 | for (i = 0; i < `NUM_IM_DATA + 5; i = i + 1) begin 54 | @(posedge clk); 55 | end 56 | 57 | $finish; 58 | end 59 | endmodule 60 | 61 | -------------------------------------------------------------------------------- /test/dm_tb.check: -------------------------------------------------------------------------------- 1 | addr, rd, wr, rdata, wdata 2 | VCD info: dumpfile dm_tb.vcd opened for output. 3 | 00, 0, 0, xxxxxxxx, xxxxxxxx 4 | 00, 0, 1, abcdef01, abcdef01 5 | 01, 0, 1, ffffaaaa, ffffaaaa 6 | 00, 1, 0, abcdef01, ffffaaaa 7 | 01, 1, 0, ffffaaaa, ffffaaaa 8 | 00, 1, 1, fefefefe, fefefefe 9 | -------------------------------------------------------------------------------- /test/dm_tb.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Data memory test bench for five stage MIPS CPU. 3 | * 4 | * Currently only runs for several cycles and 5 | * dumps a .vcd for Gtkwave. 6 | */ 7 | 8 | `include "dm.v" 9 | 10 | module dm_tb; 11 | 12 | reg clk; 13 | 14 | reg [6:0] addr; 15 | reg rd, wr; 16 | reg [31:0] wdata; 17 | wire [31:0] rdata; 18 | 19 | dm dm1(.clk(clk), .addr(addr), .rd(rd), .wr(wr), 20 | .rdata(rdata), .wdata(wdata)); 21 | 22 | always begin 23 | clk <= ~clk; 24 | #5; 25 | end 26 | 27 | initial begin 28 | $dumpfile("dm_tb.vcd"); 29 | $dumpvars(0, dm_tb); 30 | 31 | $display("addr, rd, wr, rdata, wdata"); 32 | $monitor("%x, %x, %x, %x, %x", addr, rd, wr, rdata, wdata); 33 | 34 | clk <= 1'b0; 35 | rd <= 1'b0; 36 | wr <= 1'b0; 37 | addr <= 7'd0; 38 | 39 | @(posedge clk); 40 | 41 | wdata <= 32'hABCDEF01; 42 | addr <= 7'd0; 43 | rd <= 1'b0; 44 | wr <= 1'b1; 45 | 46 | @(posedge clk); 47 | 48 | wdata <= 32'hFFFFAAAA; 49 | addr <= 7'd1; 50 | rd <= 1'b0; 51 | wr <= 1'b1; 52 | 53 | @(posedge clk); 54 | 55 | rd <= 1'b1; 56 | wr <= 1'b0; 57 | addr <= 7'd0; 58 | 59 | @(posedge clk); 60 | 61 | rd <= 1'b1; 62 | wr <= 1'b0; 63 | addr <= 7'd1; 64 | 65 | @(posedge clk); 66 | 67 | rd <= 1'b1; 68 | wr <= 1'b1; 69 | wdata <= 32'hFEFEFEFE; 70 | addr <= 7'd0; 71 | 72 | $finish; 73 | end 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /test/im_cached_tb.v: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Currently this just produces a dumpfile 4 | * suitable for Gtkwave (im_cached_tb.vcd). 5 | * 6 | * To build this filter run: 7 | * 8 | * $ make im_cached_tb.vcd 9 | * 10 | */ 11 | 12 | `include "im_cached.v" 13 | 14 | module im_cached_tb; 15 | 16 | integer i; 17 | 18 | reg clk; 19 | 20 | reg [31:0] addr; 21 | wire hit; 22 | wire [31:0] data; 23 | 24 | im_cached #(.IM_DATA("im_slow_tb.hex"), .NMEM(14), .ND(3)) 25 | im1(.clk(clk), .addr(addr), .hit(hit), .data(data)); 26 | 27 | always begin 28 | clk <= ~clk; 29 | #5; 30 | end 31 | 32 | initial begin 33 | $dumpfile("im_cached_tb.vcd"); 34 | $dumpvars(0, im_cached_tb); 35 | 36 | clk <= 1'b0; 37 | 38 | // try address zero 39 | addr <= 32'd0; 40 | @(posedge hit); 41 | 42 | @(posedge clk); 43 | 44 | // try some other address 45 | addr <= 32'd4; 46 | @(posedge hit); 47 | 48 | @(posedge clk); 49 | 50 | // briefly try some other address 51 | addr <= 32'd8; 52 | @(posedge clk); 53 | 54 | // try the original address, it should be in the cache 55 | addr <= 32'd0; 56 | @(posedge hit); 57 | 58 | @(posedge clk); 59 | 60 | $finish; 61 | end 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /test/im_slow_tb.hex: -------------------------------------------------------------------------------- 1 | 20100000 2 | 20090003 3 | 00000020 4 | 00000020 5 | 01295020 6 | AE090000 7 | 00000020 8 | AE0A0004 9 | 8E0B0000 10 | 8E0C0004 11 | 00000020 12 | 00000020 13 | 016C402A 14 | -------------------------------------------------------------------------------- /test/im_slow_tb.v: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Currently this just produces a dumpfile 4 | * suitable for Gtkwave (im_slow_tb.vcd). 5 | * 6 | * To build this filter run: 7 | * 8 | * $ make im_slow_tb.vcd 9 | * 10 | */ 11 | 12 | `include "im_slow.v" 13 | 14 | module im_slow_tb; 15 | 16 | integer i; 17 | 18 | reg clk; 19 | 20 | reg [31:0] addr; 21 | wire rdy; 22 | wire [31:0] data; 23 | 24 | im_slow #(.IM_DATA("im_slow_tb.hex"), .NMEM(14), .ND(3)) 25 | im1(.clk(clk), .addr(addr), .rdy(rdy), .data(data)); 26 | 27 | always begin 28 | clk <= ~clk; 29 | #5; 30 | end 31 | 32 | initial begin 33 | $dumpfile("im_slow_tb.vcd"); 34 | $dumpvars(0, im_slow_tb); 35 | 36 | //$display("addr, rd, wr, rdata, wdata"); 37 | //$monitor("%x, %x, %x, %x, %x", addr, rd, wr, rdata, wdata); 38 | 39 | clk <= 1'b0; 40 | addr <= 32'd0; 41 | 42 | for (i = 0; i < 5; i = i + 1) begin 43 | @(posedge clk); 44 | end 45 | 46 | addr <= 32'd4; 47 | @(posedge clk); 48 | @(posedge clk); 49 | 50 | addr <= 32'd8; 51 | 52 | @(posedge clk); 53 | @(posedge clk); 54 | @(posedge clk); 55 | @(posedge clk); 56 | 57 | $finish; 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /test/t0001-final_value.fv.asm: -------------------------------------------------------------------------------- 1 | addi $v0, $zero, 0 2 | addi $v1, $zero, 1 3 | addi $t0, $zero, 2 4 | addi $t1, $zero, 3 5 | addi $t2, $zero, 4 6 | addi $t3, $zero, 5 7 | addi $t4, $zero, 6 8 | addi $t5, $zero, 7 9 | addi $t6, $zero, 8 10 | addi $t7, $zero, 9 11 | -------------------------------------------------------------------------------- /test/t0001-final_value.fv.check: -------------------------------------------------------------------------------- 1 | 00000000, 00000001, 00000002, 00000003, 00000004, 00000005, 00000006, 00000007, 00000008, 00000009 2 | -------------------------------------------------------------------------------- /test/t0001-final_value.fv.hex: -------------------------------------------------------------------------------- 1 | 20020000 2 | 20030001 3 | 20080002 4 | 20090003 5 | 200A0004 6 | 200B0005 7 | 200C0006 8 | 200D0007 9 | 200E0008 10 | 200F0009 11 | 00000000 12 | 00000000 13 | -------------------------------------------------------------------------------- /test/t0005-branch.asm: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # t0005-branch.asm 4 | # 5 | # Perform branches (beq, bne) which would create hazards 6 | # and see if they are handled correctly. 7 | # 8 | 9 | # initial values 10 | addi $t0, $zero, 1 11 | addi $t1, $zero, 2 12 | 13 | # increment $t0 so it equals $t1 14 | addi $t0, $t0, 1 15 | 16 | beq $t0, $t1, skip1 17 | 18 | # these shouldn't get added 19 | # If they do, the third hex digit will be 1 20 | addi $t0, $t0, 256 21 | addi $t1, $t1, 256 22 | 23 | skip1: 24 | 25 | add $t0, $t0, $t1 # 2 + 2 = 4 26 | add $t1, $t0, $t1 # 4 + 2 = 6 27 | 28 | bne $t0, $t1, skip2 29 | 30 | # these shouldn't get added 31 | # If they do, the fourth hex digit will be 1 32 | addi $t0, $t0, 4096 33 | addi $t1, $t1, 4096 34 | 35 | skip2: 36 | 37 | # $t0 = 4, $t1 = 6 38 | 39 | # so the values show up in the dump 40 | add $t0, $zero, $t0 41 | add $t1, $zero, $t1 42 | -------------------------------------------------------------------------------- /test/t0005-branch.check: -------------------------------------------------------------------------------- 1 | if_pc, if_instr, id_regrs, id_regrt, ex_alua, ex_alub, ex_aluctl, mem_memdata, mem_memread, mem_memwrite, wb_regdata, wb_regwrite 2 | VCD info: dumpfile t0005-branch.vcd opened for output. 3 | 00000000, 20080001, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, x, xxxxxxxx, x, x, xxxxxxxx, x 4 | 00000004, 20090002, 00000000, xxxxxxxx, xxxxxxxx, xxxxxxxx, x, xxxxxxxx, x, x, xxxxxxxx, x 5 | 00000008, 21080001, 00000000, xxxxxxxx, 00000000, 00000001, 2, xxxxxxxx, x, x, xxxxxxxx, x 6 | 0000000c, 11090003, xxxxxxxx, xxxxxxxx, 00000000, 00000002, 2, xxxxxxxx, 0, 0, xxxxxxxx, x 7 | 00000010, 00000000, 00000001, xxxxxxxx, xxxxxxxx, 00000001, 2, xxxxxxxx, 0, 0, 00000001, 1 8 | 00000014, 21080100, 00000000, 00000000, 00000001, 00000002, 6, 00000001, 0, 0, 00000002, 1 9 | 00000018, 21290100, 00000002, 00000002, 00000000, 00000000, 2, 00000002, 0, 0, 00000002, 1 10 | 0000001c, 01094020, 00000000, 00000000, 00000000, 00000000, 2, 00000000, 0, 0, 00000000, 0 11 | 00000020, 01094820, 00000002, 00000002, 00000000, 00000000, 2, 00000000, 0, 0, 00000000, 0 12 | 00000024, 15090003, 00000002, 00000002, 00000002, 00000002, 2, 00000000, 0, 0, 00000000, 1 13 | 00000028, 00000000, 00000002, 00000002, 00000002, 00000002, 2, 00000002, 0, 0, 00000000, 1 14 | 0000002c, 21081000, 00000000, 00000000, 00000002, 00000006, 6, 00000002, 0, 0, 00000004, 1 15 | 00000030, 21291000, 00000004, 00000004, 00000000, 00000000, 2, 00000006, 0, 0, 00000006, 1 16 | 00000034, 00084020, 00000000, 00000000, 00000000, 00000000, 2, 00000000, 0, 0, fffffffe, 0 17 | 00000038, 00094820, 00000000, 00000004, 00000000, 00000000, 2, 00000000, 0, 0, 00000000, 0 18 | 0000003c, 00000000, 00000000, 00000006, 00000000, 00000004, 2, 00000000, 0, 0, 00000000, 1 19 | 00000040, xxxxxxxx, 00000000, 00000000, 00000000, 00000006, 2, 00000004, 0, 0, 00000000, 1 20 | 00000044, xxxxxxxx, xxxxxxxx, xxxxxxxx, 00000000, 00000000, 2, 00000006, 0, 0, 00000004, 1 21 | 00000048, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, 0, 00000000, 0, 0, 00000006, 1 22 | 0000004c, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, 0, xxxxxxxx, 0, 0, 00000000, 1 23 | 00000050, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, 0, xxxxxxxx, 0, 0, xxxxxxxx, 1 24 | 00000054, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, 0, xxxxxxxx, 0, 0, xxxxxxxx, 1 25 | -------------------------------------------------------------------------------- /test/t0005-branch.fv.asm: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # t0005-branch.fv.asm 4 | # 5 | # Perform branches (beq, bne) which would create hazards 6 | # and see if they are handled correctly. 7 | # 8 | 9 | # initial values 10 | addi $t0, $zero, 1 11 | addi $t1, $zero, 2 12 | 13 | # increment $t0 so it equals $t1 14 | addi $t0, $t0, 1 15 | 16 | beq $t0, $t1, skip1 17 | 18 | # these shouldn't get added 19 | # If they do, the third hex digit will be 1 20 | addi $t0, $t0, 256 21 | addi $t1, $t1, 256 22 | 23 | skip1: 24 | 25 | add $t0, $t0, $t1 # 2 + 2 = 4 26 | add $t1, $t0, $t1 # 4 + 2 = 6 27 | 28 | bne $t0, $t1, skip2 29 | 30 | # these shouldn't get added 31 | # If they do, the fourth hex digit will be 1 32 | addi $t0, $t0, 4096 33 | addi $t1, $t1, 4096 34 | 35 | skip2: 36 | 37 | # $t0 = 4, $t1 = 6 38 | -------------------------------------------------------------------------------- /test/t0005-branch.fv.check: -------------------------------------------------------------------------------- 1 | xxxxxxxx, xxxxxxxx, 00000004, 00000006, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx 2 | -------------------------------------------------------------------------------- /test/t0005-branch.fv.hex: -------------------------------------------------------------------------------- 1 | 20080001 2 | 20090002 3 | 21080001 4 | 11090003 5 | 00000000 6 | 21080100 7 | 21290100 8 | 01094020 9 | 01094820 10 | 15090003 11 | 00000000 12 | 21081000 13 | 21291000 14 | 00000000 15 | 00000000 16 | 00000000 17 | -------------------------------------------------------------------------------- /test/t0005-branch.hex: -------------------------------------------------------------------------------- 1 | 20080001 2 | 20090002 3 | 21080001 4 | 11090003 5 | 00000000 6 | 21080100 7 | 21290100 8 | 01094020 9 | 01094820 10 | 15090003 11 | 00000000 12 | 21081000 13 | 21291000 14 | 00084020 15 | 00094820 16 | 00000000 17 | -------------------------------------------------------------------------------- /test/t0006-jump.fv.asm: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # Test the jump operation. 4 | # 5 | 6 | # start: $t0 = 1 7 | addi $t0, $zero, 1 8 | 9 | # should skip adding 256 to $t0 10 | j skip1 11 | addi $t0, $t0, 256 12 | skip1: 13 | 14 | # $t0 = 2 15 | addi $t0, $t0, 1 16 | 17 | # should skip adding 512 to $t0 18 | j skip2 19 | addi $t0, $t0, 512 20 | skip2: 21 | 22 | # $t0 = 3 23 | addi $t0, $t0, 1 24 | -------------------------------------------------------------------------------- /test/t0006-jump.fv.check: -------------------------------------------------------------------------------- 1 | xxxxxxxx, xxxxxxxx, 00000003, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx 2 | -------------------------------------------------------------------------------- /test/t0006-jump.fv.hex: -------------------------------------------------------------------------------- 1 | 20080001 2 | 08000004 3 | 00000000 4 | 21080100 5 | 21080001 6 | 08000008 7 | 00000000 8 | 21080200 9 | 21080001 10 | 00000000 11 | 00000000 12 | 00000000 13 | -------------------------------------------------------------------------------- /test/t0011-operators.fv.asm: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # Test some binary operators. 4 | # 5 | 6 | # initial values 7 | addi $t0, $zero, 6 # (0110) 8 | addi $t1, $zero, 11 # (1011) 9 | 10 | # do some operations 11 | xor $t2, $t0, $t1 # 0110 ^ 1011 = 1101 12 | and $t3, $t0, $t1 # 0110 & 1011 = 0010 13 | or $t4, $t0, $t1 # 0110 | 1011 = 1111 14 | nor $t5, $t0, $t1 # ~(0110 | 1011) = 0000 15 | 16 | # $t0 = 6, $t1 = 11 (0xb), $t2 = 13 (0xd), $t3 = 2, $t4 = 15 (0xf), $t5 = 0 17 | -------------------------------------------------------------------------------- /test/t0011-operators.fv.check: -------------------------------------------------------------------------------- 1 | xxxxxxxx, xxxxxxxx, 00000006, 0000000b, 0000000d, 00000002, 0000000f, fffffff0, xxxxxxxx, xxxxxxxx 2 | -------------------------------------------------------------------------------- /test/t0011-operators.fv.hex: -------------------------------------------------------------------------------- 1 | 20080006 2 | 2009000B 3 | 01095026 4 | 01095824 5 | 01096025 6 | 01096827 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /test/t0020-stall.fv.asm: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # Test whether operations which require a stall and 4 | # forward work correctly. 5 | # 6 | 7 | # initial values 8 | addi $t0, $zero, 5 9 | addi $t1, $zero, 7 10 | addi $t2, $zero, 9 11 | 12 | # store words in memory 13 | sw $t0, 0($zero) # 5 14 | sw $t1, 4($zero) # 7 15 | 16 | # read the memory and perform an operation 17 | # *** stall and forward required *** 18 | lw $t2, 4($zero) # 7 19 | add $t3, $t0, $t2 # 5 + 7 = 12 20 | 21 | # $t0 = 5, $t1 = 7, $t2 = 7, $t3 = 12 (0x0c) 22 | -------------------------------------------------------------------------------- /test/t0020-stall.fv.check: -------------------------------------------------------------------------------- 1 | xxxxxxxx, xxxxxxxx, 00000005, 00000007, 00000007, 0000000c, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx 2 | -------------------------------------------------------------------------------- /test/t0020-stall.fv.hex: -------------------------------------------------------------------------------- 1 | 20080005 2 | 20090007 3 | 200A0009 4 | AC080000 5 | AC090004 6 | 8C0A0004 7 | 010A5820 8 | 00000000 9 | -------------------------------------------------------------------------------- /test/t0021-stall.fv.asm: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # Operations which are dependent on the results of previous operations 4 | # will require a stall or some other action to avoid a mis-calculation. 5 | # 6 | # Perform these dependent operations and see if they work. 7 | # 8 | 9 | # initial values 10 | addi $t0, $zero, 1 11 | addi $t1, $zero, 5 12 | addi $t2, $zero, 7 13 | 14 | add $t0, $t0, $t1 # $t0 = 1 + 5 = 6 15 | add $t1, $t0, $t1 # $t1 = 6 + 5 = 11 16 | add $t2, $t1, $t0 # $t2 = 11 + 6 = 17 17 | add $t0, $t2, $t1 # $t0 = 17 + 11 = 28 18 | 19 | # $t0 = 28 (0x1c), $t1 = 11 (0x0b), $t2 = 17 (0x11) 20 | -------------------------------------------------------------------------------- /test/t0021-stall.fv.check: -------------------------------------------------------------------------------- 1 | xxxxxxxx, xxxxxxxx, 0000001c, 0000000b, 00000011, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx 2 | -------------------------------------------------------------------------------- /test/t0021-stall.fv.hex: -------------------------------------------------------------------------------- 1 | 20080001 2 | 20090005 3 | 200A0007 4 | 01094020 5 | 01094820 6 | 01285020 7 | 01494020 8 | 00000000 9 | -------------------------------------------------------------------------------- /test/t0030-lw_sw.fv.asm: -------------------------------------------------------------------------------- 1 | 2 | # 3 | # Test the lw, and sw opertions. 4 | # 5 | 6 | addi $t0, $zero, 5 7 | addi $t1, $zero, 9 8 | 9 | sw $t0, 0($zero) # 5 10 | sw $t1, 4($zero) # 9 11 | 12 | lw $t0, 4($zero) # 9 13 | add $t0, $t0, $t1 # 9 + 9 = 18 14 | 15 | # $t0 = 18 (0x12), $t1 = 9 16 | -------------------------------------------------------------------------------- /test/t0030-lw_sw.fv.check: -------------------------------------------------------------------------------- 1 | xxxxxxxx, xxxxxxxx, 00000012, 00000009, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx, xxxxxxxx 2 | -------------------------------------------------------------------------------- /test/t0030-lw_sw.fv.hex: -------------------------------------------------------------------------------- 1 | 20080005 2 | 20090009 3 | AC080000 4 | AC090004 5 | 8C080004 6 | 01094020 7 | 00000000 8 | 00000000 9 | -------------------------------------------------------------------------------- /test/t0050-hello.c: -------------------------------------------------------------------------------- 1 | 2 | void main(void) { 3 | register int x asm("t0") = 0x100f; 4 | register int y asm("t1") = 0x10f0; 5 | register int z asm("t2"); 6 | 7 | z = x | y; 8 | } 9 | --------------------------------------------------------------------------------