├── README.md ├── reports ├── Multi-cycle 32-bit CPU.docx └── Multi-cycle 32-bit CPU.pdf ├── screenshots ├── Controller │ ├── controller1.png │ ├── controller2.png │ └── controller3.png ├── Datapath Components │ ├── SignExtendTest.png │ ├── holding_reg_test.png │ ├── jumpALU_test.png │ └── mux_1bit_test.png ├── Program 1 │ ├── cpu5.png │ ├── cpu6.png │ ├── cpu8.png │ └── cpu9.png └── Program 2 │ ├── cpu1.png │ ├── cpu10.png │ ├── cpu2.png │ ├── cpu3.png │ └── cpu4.png └── src ├── Implementation ├── DMem.v ├── IMem.v ├── MultiCycleCPU.v ├── controller.v ├── datapath.v ├── holding_reg.v ├── jumpALU.v ├── mux_1bit.v ├── mux_2bit.v ├── myALU.v ├── nbit_register_file.v ├── read_mux.v ├── sign_extend.v └── zero_extend.v └── Tests ├── MultiCycleCPU_test.v ├── controllerTest.v ├── holding_reg_test.v ├── jumpALU_test.v ├── mux_1bit_test.v ├── sign_extend_test.v └── zero_extend_test.v /README.md: -------------------------------------------------------------------------------- 1 | # 32-bit-Multicycle-CPU 2 | -------------------------------------------------------------------------------- /reports/Multi-cycle 32-bit CPU.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/reports/Multi-cycle 32-bit CPU.docx -------------------------------------------------------------------------------- /reports/Multi-cycle 32-bit CPU.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/reports/Multi-cycle 32-bit CPU.pdf -------------------------------------------------------------------------------- /screenshots/Controller/controller1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Controller/controller1.png -------------------------------------------------------------------------------- /screenshots/Controller/controller2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Controller/controller2.png -------------------------------------------------------------------------------- /screenshots/Controller/controller3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Controller/controller3.png -------------------------------------------------------------------------------- /screenshots/Datapath Components/SignExtendTest.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Datapath Components/SignExtendTest.png -------------------------------------------------------------------------------- /screenshots/Datapath Components/holding_reg_test.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Datapath Components/holding_reg_test.png -------------------------------------------------------------------------------- /screenshots/Datapath Components/jumpALU_test.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Datapath Components/jumpALU_test.png -------------------------------------------------------------------------------- /screenshots/Datapath Components/mux_1bit_test.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Datapath Components/mux_1bit_test.png -------------------------------------------------------------------------------- /screenshots/Program 1/cpu5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Program 1/cpu5.png -------------------------------------------------------------------------------- /screenshots/Program 1/cpu6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Program 1/cpu6.png -------------------------------------------------------------------------------- /screenshots/Program 1/cpu8.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Program 1/cpu8.png -------------------------------------------------------------------------------- /screenshots/Program 1/cpu9.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Program 1/cpu9.png -------------------------------------------------------------------------------- /screenshots/Program 2/cpu1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Program 2/cpu1.png -------------------------------------------------------------------------------- /screenshots/Program 2/cpu10.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Program 2/cpu10.png -------------------------------------------------------------------------------- /screenshots/Program 2/cpu2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Program 2/cpu2.png -------------------------------------------------------------------------------- /screenshots/Program 2/cpu3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Program 2/cpu3.png -------------------------------------------------------------------------------- /screenshots/Program 2/cpu4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/johnc219/32-bit-Multicycle-CPU/04f7d16a19c03dfd1faf715f860d8b148156bbba/screenshots/Program 2/cpu4.png -------------------------------------------------------------------------------- /src/Implementation/DMem.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:03:01 11/22/2014 7 | // Design Name: 8 | // Module Name: DMem 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | // DMem 22 | // 23 | // A module used to mimic the behavior of a computer's 24 | // data memory for EC413 Design Project. 25 | // 26 | // This behavioral code generates into single-port RAM on the FPGA. 27 | // Assume the memory contains garbage data (all Xs) until you have 28 | // overwritten it. 29 | // 30 | // ADDRESS_WIDTH: the number of memory addresses is 2 to the power 31 | // of this number. 32 | // 33 | // DATA_WIDTH: the size of each element in the memory. 34 | // 35 | // Number of word bits DATA_WIDTH. 36 | // 37 | module DMem(WriteData, // Input data into the memory 38 | MemData, // Output data from the memory 39 | Address, // Address of data to be read/written 40 | MemWrite, // When high, causes write to take place on posedge 41 | Clk); // Clock 42 | 43 | parameter ADDRESS_WIDTH = 16; 44 | parameter DATA_WIDTH = 32; 45 | 46 | //-------------Input Ports----------------------------- 47 | input [DATA_WIDTH-1:0] WriteData; 48 | input [ADDRESS_WIDTH-1:0] Address; 49 | input MemWrite; 50 | input Clk; 51 | //-------------Output Ports---------------------------- 52 | output [DATA_WIDTH-1:0] MemData; 53 | //-------------Wires----------------------------------- 54 | //-------------Other----------------------------------- 55 | reg [DATA_WIDTH-1:0] mem_contents [ADDRESS_WIDTH-1:0]; 56 | integer i; 57 | //------------Code Starts Here------------------------- 58 | 59 | assign MemData= mem_contents[Address]; 60 | 61 | always @(posedge Clk) 62 | begin 63 | if(MemWrite) 64 | begin 65 | mem_contents[Address] <= #5 WriteData; 66 | end 67 | end 68 | endmodule 69 | -------------------------------------------------------------------------------- /src/Implementation/IMem.v: -------------------------------------------------------------------------------- 1 | // IMem 2 | // 3 | // A module used to mimic Instruction memory, for the EC413 project. 4 | // Returns hardcoded instructions based on the current PC. 5 | // 6 | // Version2. Posted 7:30PM on Nov 27. 7 | // Fixed a false nop instruction and reg select fields in 1. 8 | // 9 | `timescale 1ns / 1ps 10 | // ---------------------------------------------------- 11 | // IMPORTANT! 12 | // Which test program to use: 13 | // - PROGRAM_1: first simple example. 14 | // 15 | // - PROGRAM_2: test remaining instructions 16 | // and corner cases. 17 | // - PROGRAM_3: optional LW/SW program. 18 | // 19 | `define PROGRAM_1 // <<<<<<<<<<<< CHANGE TEST PROGRAM HERE! 20 | // 21 | // Change the previous line to try a different program, 22 | // when available. 23 | // ---------------------------------------------------- 24 | 25 | module IMem(PC, // PC (address) of instruction in IMem 26 | Instruction); 27 | `ifdef PROGRAM_1 28 | parameter PROG_LENGTH= 22; 29 | `else 30 | `ifdef PROGRAM_2 31 | parameter PROG_LENGTH= 26; 32 | `else 33 | `ifdef PROGRAM_3 34 | parameter PROG_LENGTH= 12; 35 | `endif 36 | `endif 37 | `endif 38 | //-------------Input Ports----------------------------- 39 | input [31:0] PC; 40 | //-------------Output Ports---------------------------- 41 | output [31:0] Instruction; 42 | reg [31:0] Instruction; 43 | //------------Code Starts Here------------------------- 44 | always @(PC) 45 | begin 46 | case(PC) 47 | //----------------------------------------------------- 48 | `ifdef PROGRAM_1 49 | //----------------------------------------------------- 50 | 51 | // 52 | // PROGRAM_1: Basic Math, Branches and Jump Test 53 | // 54 | 55 | // 56 | // 1.1) First part: 57 | // Load values into: 58 | // $R0 = -1 59 | // $R1 = 0 60 | // $R2 = 2 61 | // Add $R0 and $R2 and get an answer in $R3: 62 | // -1 + 2 = 1 63 | // 64 | 65 | // LI $R0, 0xFFFF 66 | 0: Instruction= 32'b111001_00000_00000_1111111111111111; 67 | // LUI $R0, 0xFFFF 68 | 1: Instruction= 32'b111010_00000_00000_1111111111111111; 69 | // LI $R1, 0x0000 70 | 2: Instruction= 32'b111001_00001_00000_0000000000000000; 71 | // LUI $R1, 0x0000 72 | 3: Instruction= 32'b111010_00001_00000_0000000000000000; 73 | // LI $R2, 0x0002 74 | 4: Instruction= 32'b111001_00010_00000_0000000000000010; 75 | // LUI $R2, 0x0000 76 | 5: Instruction= 32'b111010_00010_00000_0000000000000000; 77 | // ADD $R3, $R0, $R2 78 | 6: Instruction= 32'b010010_00011_00000_00010_00000000000; 79 | 80 | // 81 | // 1.2) Second part: store and load, should store $R3 82 | // (contains 1) into address 5. Then load from 83 | // address 5 into register $R1. $R1 should then 84 | // contain 1. 85 | // 86 | 87 | // SWI $R3, [0x5] 88 | 7: Instruction= 32'b111100_00011_00000_0000000000000101; 89 | // LWI $R1, [0x5] 90 | 8: Instruction= 32'b111011_00001_00000_0000000000000101; 91 | 92 | 93 | // 94 | // 1.3) Third part: simple loop tests, to check branch 95 | // look at the PC and alu output to check 96 | // 97 | 98 | // LI $R23, 0x0000 99 | 9: Instruction= 32'b111001_10111_00000_0000000000000000; 100 | // ADDI $R0, $R0, 0x0001 101 | 10: Instruction= 32'b110010_00000_00000_0000000000000001; 102 | // SLT $R31, $R0, $R1 103 | 11: Instruction= 32'b010111_11111_00000_00001_00000000000; 104 | // BNE $R31, $R23, 0xFFFD 105 | //12: Instruction= 32'b100001_11111_10111_1111111111111101; 106 | // BEQ 107 | 12: Instruction= 32'b100000_00010_00001_1111111111111101; //`````````````` 108 | 109 | // LI $R23, 0x0003 110 | 13: Instruction= 32'b111001_10111_00000_0000000000000011; 111 | // ADDI $R24, $R24, 0x0001 112 | 14: Instruction= 32'b110010_11000_11000_0000000000000001; 113 | // BLT $R24, $R23, 0xFFFE 114 | //15: Instruction= 32'b100010_11000_10111_1111111111111110; 115 | 15: Instruction= 32'h00000000; //````````````````````````````````````````` 116 | 117 | 118 | // ADDI $R25, $R25, 0x0001 119 | 16: Instruction= 32'b110010_11001_11001_0000000000000001; 120 | // BLE $R25, $R23, 0xFFFE 121 | //17: Instruction= 32'b100011_11001_10111_1111111111111110; 122 | 17: Instruction= 32'h00000000; //````````````````````````````````````````` 123 | 124 | // J 21 / should skip the two addi 5 and go to addi 7 125 | 18: Instruction= 32'b000001_00000_00000_0000000000000010; 126 | // ADDI $R0, $R0, 0x0005 127 | 19: Instruction= 32'b110010_00000_00000_0000000000000101; 128 | // ADDI $R0, $R0, 0x0005 129 | 20: Instruction= 32'b110010_00000_00000_0000000000000101; 130 | // ADDI $R26, $R26, 0x0007 131 | 21: Instruction= 32'b110010_11010_11010_0000000000000111; 132 | // NOOP 133 | 22: Instruction= 32'b000000_00000_00000_0000000000000000; 134 | `else 135 | //----------------------------------------------------- 136 | `ifdef PROGRAM_2 137 | //----------------------------------------------------- 138 | 139 | // 140 | // PROGRAM_2: 141 | // Test all R-type and logical/arithmetic I-type instructions, 142 | // also test remaining untested instructions and additional 143 | // corner cases. 144 | // 145 | 146 | // 147 | // 2.1) First part: 148 | // Load values into: 149 | // $R0 = -2 (0xFFFFFFFE) 150 | // $R1 = 65537 (0x00010001) 151 | // $R2 = 1 (0x00000001) 152 | // 153 | 154 | // LI $R0, 0xFFFE 155 | 0: Instruction= 32'b111001_00000_00000_1111111111111110; 156 | // LUI $R0, 0xFFFF 157 | 1: Instruction= 32'b111010_00000_00000_1111111111111111; 158 | // LI $R1, 0x0001 159 | 2: Instruction= 32'b111001_00001_00000_0000000000000001; 160 | // LUI $R1, 0x0001 161 | 3: Instruction= 32'b111010_00001_00000_0000000000000001; 162 | // LI $R2, 0x0001 163 | 4: Instruction= 32'b111001_00010_00000_0000000000000001; 164 | // LUI $R2, 0x0000 165 | 5: Instruction= 32'b111010_00010_00000_0000000000000000; 166 | 167 | // 168 | // 2.2) Second part: 169 | // Run through all R-Type instructions 170 | // 171 | 172 | // MOV $R3, $R2: ALUOutput = 1 173 | 6: Instruction= 32'b010000_00011_00010_00000_00000000000; 174 | // NOT $R4, $R2: ALUOutput = (~0x00000001) = 0xFFFFFFFE 175 | 7: Instruction= 32'b010001_00100_00010_00000_00000000000; 176 | // ADD $R5, $R2, $R0: ALUOutput = 1 + (-2) = -1 (0xFFFFFFFF) 177 | 8: Instruction= 32'b010010_00101_00010_00000_00000000000; 178 | // SUB $R6, $R2, $R0: ALUOutput = 1 - (-2) = 3 179 | 9: Instruction= 32'b010011_00110_00010_00000_00000000000; 180 | // OR $R7, $R1, $R0: ALUOutput = (0x00010001 | 0xFFFFFFFE) = 0xFFFFFFFF 181 | 10: Instruction= 32'b010100_00111_00001_00000_00000000000; 182 | // AND $R8, $R1, $R0: ALUOutput = (0x00010001 & 0xFFFFFFFE) = 0x00010000 183 | 11: Instruction= 32'b010101_01000_00001_00000_00000000000; 184 | // XOR $R9, $R1, $R0: ALUOutput = (0x00010001 ^ 0xFFFFFFFE) = 0xFFFEFFFF 185 | 12: Instruction= 32'b010110_01001_00001_00000_00000000000; 186 | // SLT $R10, $R1, $R0: ALUOutput = (0x00010001 < -2) = 0 187 | 13: Instruction= 32'b010111_01010_00001_00000_00000000000; 188 | 189 | // 190 | // 2.3) Third part: 191 | // Run through all Logical/Arithmetic I-Type instructions 192 | // 193 | 194 | // ADDI $R12, $R2, 5: ALUOutput = 1 + 5 = 6 195 | 14: Instruction= 32'b110010_01100_00010_0000000000000101; 196 | // SUBI $R13, $R2, 5: ALUOutput = 1 - 5 = -4 197 | 15: Instruction= 32'b110011_01101_00010_0000000000000101; 198 | // ORI $R14, $R2, 5: ALUOutput = (0x00000001 | 0x0005) = 0x00000005 199 | 16: Instruction= 32'b110100_01110_00010_0000000000000101; 200 | // ANDI $R15, $R2, 5: ALUOutput = (0x00000001 & 0x0005) = 0x00000001 201 | 17: Instruction= 32'b110101_01111_00010_0000000000000101; 202 | // XORI $R16, $R2, 5: ALUOutput = (0x00000001 ^ 0x0005) = 0x00000004 203 | 18: Instruction= 32'b110110_10000_00010_0000000000000101; 204 | // SLTI $R17, $R2, 5: ALUOutput = (1 < 5) = 1 205 | 19: Instruction= 32'b110111_10001_00010_0000000000000101; 206 | 207 | // 208 | // 2.4) Fourth part: 209 | // LWI and SWI, test corner cases 210 | // 211 | 212 | // SWI $R3, [0x0000] (store 1 at address 0) 213 | 20: Instruction= 32'b111100_00011_00000_0000000000000000; 214 | // SWI $R4, [0x0000] (overwrite value of 1 with 0xFFFFFFFE at address 0) 215 | 21: Instruction= 32'b111100_00100_00000_0000000000000000; 216 | // SWI $R5, [0xFFFF] (store 0xFFFFFFFF at address 0xFFFF) 217 | 22: Instruction= 32'b111100_00101_00000_0000000000001111; 218 | // LWI $R19, [0x0000] (load 0xFFFFFFFE) 219 | 23: Instruction= 32'b111011_10011_00000_0000000000000000; 220 | // ADDI $R19, $R19, 1: ALUOutput = 0xFFFFFFFF 221 | 24: Instruction= 32'b110010_10011_10011_0000000000000001; 222 | // LWI $R19, [0xFFFF] (load 0xFFFFFFFF) 223 | 25: Instruction= 32'b111011_10011_00000_0000000000001111; 224 | // ADDI $R19, $R19, 1: ALUOutput = 0x00000000 225 | 26: Instruction= 32'b110010_10011_10011_0000000000000001; 226 | 227 | 228 | `else 229 | //----------------------------------------------------- 230 | `ifdef PROGRAM_3 231 | //----------------------------------------------------- 232 | 233 | // Simple LW and SW test. 234 | 235 | // 236 | // 3.1) First part: 237 | // Load values into: 238 | // $R0 = 0 (0x00000000) 239 | // $R1 = 10 (0x0000000A) 240 | // 241 | 242 | // LI $R0, 0x0000 243 | 0: Instruction= 32'b111001_00000_00000_0000000000000000; 244 | // LUI $R0, 0x0000 245 | 1: Instruction= 32'b111010_00000_00000_0000000000000000; 246 | // LI $R1, 0x000A 247 | 2: Instruction= 32'b111001_00001_00000_0000000000001010; 248 | // LUI $R1, 0x0000 249 | 3: Instruction= 32'b111010_00001_00000_0000000000000000; 250 | 251 | // 252 | // 3.2) Second part: 253 | // Loop with SW test. 254 | // Stores the following: 255 | // 256 | // Address 1: 0 257 | // Address 2: 1 258 | // ... 259 | // Address 9: 8 260 | // Address 10: 9 261 | // 262 | 263 | // SW $R0, $R0[0x1] 264 | 4: Instruction= 32'b111110_00000_00000_0000000000000001; 265 | // ADDI $R0, $R0, 0x0001 266 | 5: Instruction= 32'b110010_00000_00000_0000000000000001; 267 | // BLT $R0, $R1, 0xFFFD 268 | 6: Instruction= 32'b100010_00000_00001_1111111111111101; 269 | 270 | // 271 | // 3.3) Third part: 272 | // Loop with LW test. 273 | // Should output out of the ALU on instruction 11: 1, 2, ..., 10 274 | // 275 | 276 | // LI $R0, 0x0000 277 | 7: Instruction= 32'b111001_00000_00000_0000000000000000; 278 | // LUI $R0, 0x0000 279 | 8: Instruction= 32'b111010_00000_00000_0000000000000000; 280 | // LW $R19, $R0[0x0001] 281 | 9: Instruction= 32'b111101_10011_00000_0000000000000001; 282 | // ADDI $R19, $R19, 0x0001 283 | 10: Instruction= 32'b110010_10011_10011_0000000000000001; 284 | // ADDI $R0, $R0, 0x0001 285 | 11: Instruction= 32'b110010_00000_00000_0000000000000001; 286 | // BLT $R0, $R1 0xFFFC 287 | 12: Instruction= 32'b100001_11111_00000_1111111111111100; 288 | 289 | `endif 290 | `endif 291 | `endif 292 | default: Instruction= 0; //NOOP 293 | endcase 294 | end 295 | endmodule 296 | 297 | -------------------------------------------------------------------------------- /src/Implementation/MultiCycleCPU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: John Careaga 5 | // 6 | // Create Date: 00:04:40 11/23/2014 7 | // Design Name: 8 | // Module Name: MultiCycleCPU 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 23 | // ~~~~~~~~~~~~~~~~~~~~~~ CPU ~~~~~~~~~~~~~~~~~~~~~~~ // 24 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 25 | 26 | module MultiCycleCPU(clk, reset); 27 | // ~~~~~~~~~~~~~~~~~~~~~ INPUTS ~~~~~~~~~~~~~~~~~~~~~~ // 28 | 29 | input clk, reset; 30 | 31 | // ~~~~~~~~~~~~~~~~~~~~~ WIRES ~~~~~~~~~~~~~~~~~~~~~~~ // 32 | 33 | wire PCWrite, PCWriteCond, IRWrite, DMEMWrite, RegWrite, ALUSrcA, RegReadSel; 34 | wire [1:0] MemtoReg, ALUSrcB, PCSource; 35 | wire [3:0] ALUSel; 36 | wire [5:0] opcode; 37 | 38 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 39 | // ~~~~~~~~~~~~~~~~~~~~ DATAPATH ~~~~~~~~~~~~~~~~~~~~ // 40 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 41 | 42 | datapath cpu_datapath(clk, reset, PCWrite, PCWriteCond, IRWrite, DMEMWrite, 43 | RegWrite, ALUSrcA, RegReadSel, MemtoReg, ALUSrcB, 44 | PCSource, ALUSel, opcode); 45 | 46 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 47 | // ~~~~~~~~~~~~~~~~~~~ CONTROLLER ~~~~~~~~~~~~~~~~~~~ // 48 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 49 | 50 | controller cpu_controller(opcode, clk, reset, PCWrite, PCWriteCond, 51 | DMEMWrite, IRWrite, MemtoReg, PCSource, ALUSel, 52 | ALUSrcA, ALUSrcB, RegWrite, RegReadSel); 53 | endmodule 54 | -------------------------------------------------------------------------------- /src/Implementation/controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | //////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: John Careaga 5 | // 6 | // Create Date: 05:58:01 11/24/2014 7 | // Design Name: 8 | // Module Name: controller 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | //////////////////////////////////////////////////////////////////////////////// 21 | 22 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 23 | // ~~~~~~~~~~~~~~~~~~~ CONTROLLER ~~~~~~~~~~~~~~~~~~~ // 24 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 25 | 26 | module controller(opcode, clk, reset, PCWrite, PCWriteCond, DMEMWrite, IRWrite, 27 | MemtoReg, PCSource, ALUSel, ALUSrcA, ALUSrcB, RegWrite, 28 | RegReadSel); 29 | 30 | // ~~~~~~~~~~~~~~~~~~~ PORTS ~~~~~~~~~~~~~~~~~~~ // 31 | 32 | // opcode, clock, and reset inputs 33 | input [5:0] opcode; // from instruction register 34 | input clk, reset; 35 | 36 | // control signal outputs 37 | output reg PCWrite, PCWriteCond, DMEMWrite, IRWrite, ALUSrcA, RegWrite, RegReadSel; 38 | output reg [1:0] MemtoReg, PCSource, ALUSrcB; 39 | output reg [3:0] ALUSel; 40 | 41 | // ~~~~~~~~~~~~~~~~~~~ REGISTER ~~~~~~~~~~~~~~~~~~~ // 42 | 43 | // 4-bit state register 44 | reg [3:0] state; 45 | 46 | // ~~~~~~~~~~~~~~~~~~~ PARAMETERS ~~~~~~~~~~~~~~~~~~~ // 47 | 48 | // state parameters 49 | parameter s0 = 4'd0; 50 | parameter s1 = 4'd1; 51 | parameter s2 = 4'd2; 52 | parameter s3 = 4'd3; 53 | parameter s4 = 4'd4; 54 | parameter s5 = 4'd5; 55 | parameter s6 = 4'd6; 56 | parameter s7 = 4'd7; 57 | parameter s8 = 4'd8; 58 | parameter s9 = 4'd9; 59 | parameter s10 = 4'd10; 60 | parameter s11 = 4'd11; 61 | parameter s12 = 4'd12; 62 | parameter sR = 4'd13; // reset 63 | parameter s14 = 4'd14; 64 | 65 | // opcode[5:4] parameters 66 | parameter J = 2'b00; // Jump or NOP 67 | parameter R = 2'b01; // R-type 68 | parameter BR = 2'b10; // Branch 69 | parameter I = 2'b11; // I-type 70 | 71 | // I-type opcode[3:0] variations 72 | parameter ADDI = 4'b0010; 73 | parameter SUBI = 4'b0011; 74 | parameter ORI = 4'b0100; 75 | parameter ANDI = 4'b0101; 76 | parameter XORI = 4'b0110; 77 | parameter SLTI = 4'b0111; 78 | parameter LI = 4'b1001; 79 | parameter LUI = 4'b1010; 80 | parameter LWI = 4'b1011; 81 | parameter SWI = 4'b1100; 82 | 83 | // ~~~~~~~~~~~~~~~~~~~ STATE MACHINE ~~~~~~~~~~~~~~~~~~~ // 84 | 85 | // control state machine 86 | always @(posedge clk) begin 87 | 88 | // check for reset signal. If set, write zero to PC and switch to Reset State on next CC. 89 | if (reset) begin 90 | PCWrite <= 1; 91 | PCWriteCond <= 0; 92 | DMEMWrite <= 0; 93 | IRWrite <= 0; 94 | MemtoReg <= 0; 95 | PCSource <= 2'b11; // reset 96 | ALUSel <= 0; 97 | ALUSrcA <= 0; 98 | ALUSrcB <= 0; 99 | RegWrite <= 0; 100 | 101 | state <= sR; 102 | end 103 | else begin // if reset signal is not set, check state at pos edge 104 | case (state) 105 | 106 | // if in reset state (and reset signal not set), go to s0 (IF) 107 | sR: begin 108 | PCWrite <= 1; 109 | DMEMWrite <= 0; 110 | IRWrite <= 1; 111 | PCSource <= 2'b00; 112 | ALUSel <= 4'b0010; 113 | ALUSrcA <= 0; 114 | ALUSrcB <= 2'b01; 115 | RegWrite <= 0; 116 | PCWriteCond <= 0; 117 | 118 | state <= s0; 119 | end 120 | 121 | // if in s0, go to s1 (ID) 122 | s0: begin 123 | PCWrite <= 0; 124 | DMEMWrite <= 0; 125 | IRWrite <= 0; 126 | ALUSel <= 4'b0010; 127 | ALUSrcA <= 0; 128 | ALUSrcB <= 2'b10; 129 | RegWrite <= 0; 130 | RegReadSel <= 0; 131 | 132 | state <= s1; 133 | end 134 | 135 | // if in s1 (ID) check opcode from instruction register to determine new state 136 | s1: begin 137 | case (opcode[5:4]) 138 | // R-type opcode: go to s2 (R-type EX) 139 | R: begin 140 | PCWrite <= 0; 141 | DMEMWrite <= 0; 142 | IRWrite <= 0; 143 | ALUSel <= opcode[3:0]; 144 | ALUSrcA <= 1; 145 | ALUSrcB <= 2'b00; 146 | RegWrite <= 0; 147 | 148 | state <= s2; 149 | end 150 | 151 | // J-type or NOP 152 | J: begin 153 | // NOP: do nothing and go back to s0 (IF) for next instruction 154 | if (opcode[3:0] == 4'b0000) begin 155 | PCWrite <= 1; 156 | DMEMWrite <= 0; 157 | IRWrite <= 1; 158 | PCSource <= 2'b00; 159 | ALUSel <= 4'b0010; 160 | ALUSrcA <= 0; 161 | ALUSrcB <= 2'b01; 162 | RegWrite <= 0; 163 | PCWriteCond <= 0; 164 | 165 | state <= 0; 166 | end 167 | // Jump: go to s12 (jump completion) 168 | else begin 169 | PCWrite <= 1; 170 | DMEMWrite <= 0; 171 | IRWrite <= 0; 172 | PCSource <= 2'b10; 173 | RegWrite <= 0; 174 | 175 | state <= s12; 176 | end 177 | end 178 | 179 | // Branch: go to s14 ($R1 read) 180 | BR: begin 181 | PCWrite <= 0; 182 | DMEMWrite <= 0; 183 | IRWrite <= 0; 184 | ALUSel <= 4'b0010; 185 | ALUSrcA <= 0; 186 | ALUSrcB <= 2'b10; 187 | RegWrite <= 0; 188 | RegReadSel <= 1; // for R1 189 | 190 | state <= s14; 191 | end 192 | 193 | // I-type 194 | I: begin 195 | // go to s3 (EX for ALU I-type with sign extended immediate) 196 | if ((opcode[3:0] == ADDI) || (opcode[3:0] == SUBI) || (opcode[3:0] == SLTI)) begin 197 | PCWrite <= 0; 198 | DMEMWrite <= 0; 199 | IRWrite <= 0; 200 | ALUSel <= opcode[3:0]; 201 | ALUSrcA <= 1; 202 | ALUSrcB <= 2'b10; 203 | RegWrite <= 0; 204 | 205 | state <= s3; 206 | end 207 | 208 | // go to s4 (EX for ALU I-type with zero extended immediate) 209 | else if ((opcode[3:0] == ORI) || (opcode[3:0] == ANDI) || (opcode[3:0] == XORI)) begin 210 | PCWrite <= 0; 211 | DMEMWrite <= 0; 212 | IRWrite <= 0; 213 | ALUSel <= opcode[3:0]; 214 | ALUSrcA <= 1; 215 | ALUSrcB <= 2'b11; 216 | RegWrite <= 0; 217 | 218 | state <= s4; 219 | end 220 | 221 | // go to s5 (MEM access for LWI) 222 | else if (opcode[3:0] == LWI) begin 223 | PCWrite <= 0; 224 | DMEMWrite <= 0; 225 | IRWrite <= 0; 226 | RegWrite <= 0; 227 | 228 | state <= s5; 229 | end 230 | // go to s14 for R1 read 231 | else if ((opcode[3:0] == LI) || (opcode[3:0] == LUI) || (opcode[3:0] == SWI))begin 232 | PCWrite <= 0; 233 | DMEMWrite <= 0; 234 | IRWrite <= 0; 235 | ALUSel <= 4'b0010; 236 | ALUSrcA <= 0; 237 | ALUSrcB <= 2'b10; 238 | RegWrite <= 0; 239 | RegReadSel <= 1; // for R1 240 | 241 | state <= s14; 242 | end 243 | end 244 | endcase 245 | end 246 | 247 | // if in s2 (R-type EX) go to s6 (ALUOp write backs) 248 | s2: begin 249 | PCWrite <= 0; 250 | DMEMWrite <= 0; 251 | IRWrite <= 0; 252 | MemtoReg <= 2'b00; 253 | RegWrite <= 1; 254 | 255 | state <= s6; 256 | end 257 | 258 | // if in s3 (EX for Arithmetic I-type with sign extended Imm) go to s6 (ALUOp WB) 259 | s3: begin 260 | PCWrite <= 0; 261 | DMEMWrite <= 0; 262 | IRWrite <= 0; 263 | MemtoReg <= 2'b00; 264 | RegWrite <= 1; 265 | 266 | state <= s6; 267 | end 268 | 269 | // if in s4 (EX for Arithmetic I-type with zero extended Imm) go to s6 (ALUOp WB) 270 | s4: begin 271 | PCWrite <= 0; 272 | DMEMWrite <= 0; 273 | IRWrite <= 0; 274 | MemtoReg <= 2'b00; 275 | RegWrite <= 1; 276 | 277 | state <= s6; 278 | end 279 | 280 | // if in s5 (LWI MEM access) go to s7 (Reg File WB for LWI) 281 | s5: begin 282 | PCWrite <= 0; 283 | DMEMWrite <= 0; 284 | IRWrite <= 0; 285 | MemtoReg <= 2'b01; 286 | RegWrite <= 1; 287 | 288 | state <= s7; 289 | end 290 | 291 | // if in s6 (ALUOut WB) go back to s0 (IF) 292 | s6: begin 293 | PCWrite <= 1; 294 | DMEMWrite <= 0; 295 | IRWrite <= 1; 296 | PCSource <= 2'b00; 297 | ALUSel <= 4'b0010; 298 | ALUSrcA <= 0; 299 | ALUSrcB <= 2'b01; 300 | RegWrite <= 0; 301 | PCWriteCond <= 0; 302 | 303 | state <= s0; 304 | end 305 | 306 | // if in s7 (Reg Gile WB for LWI) go to s0 (IF) 307 | s7: begin 308 | PCWrite <= 1; 309 | DMEMWrite <= 0; 310 | IRWrite <= 1; 311 | PCSource <= 2'b00; 312 | ALUSel <= 4'b0010; 313 | ALUSrcA <= 0; 314 | ALUSrcB <= 2'b01; 315 | RegWrite <= 0; 316 | PCWriteCond <= 0; 317 | 318 | state <= s0; 319 | end 320 | 321 | // if in s8 (MEM write for SWI) go to s0 (IF) 322 | s8: begin 323 | PCWrite <= 1; 324 | DMEMWrite <= 0; 325 | IRWrite <= 1; 326 | PCSource <= 2'b00; 327 | ALUSel <= 4'b0010; 328 | ALUSrcA <= 0; 329 | ALUSrcB <= 2'b01; 330 | RegWrite <= 0; 331 | PCWriteCond <= 0; 332 | 333 | state <= s0; 334 | end 335 | 336 | // if in s9 (Reg WB for LI) go to s0 (IF) 337 | s9: begin 338 | PCWrite <= 1; 339 | DMEMWrite <= 0; 340 | IRWrite <= 1; 341 | PCSource <= 2'b00; 342 | ALUSel <= 4'b0010; 343 | ALUSrcA <= 0; 344 | ALUSrcB <= 2'b01; 345 | RegWrite <= 0; 346 | PCWriteCond <= 0; 347 | 348 | state <= s0; 349 | end 350 | 351 | // if in s10 (Reg WB for LUI) go to s0 (IF) 352 | s10: begin 353 | PCWrite <= 1; 354 | DMEMWrite <= 0; 355 | IRWrite <= 1; 356 | PCSource <= 2'b00; 357 | ALUSel <= 4'b0010; 358 | ALUSrcA <= 0; 359 | ALUSrcB <= 2'b01; 360 | RegWrite <= 0; 361 | PCWriteCond <= 0; 362 | 363 | state <= s0; 364 | end 365 | 366 | // if in s11 (Branch completion) go to s0 (IF) 367 | s11: begin 368 | PCWrite <= 1; 369 | DMEMWrite <= 0; 370 | IRWrite <= 1; 371 | PCSource <= 2'b00; 372 | ALUSel <= 4'b0010; 373 | ALUSrcA <= 0; 374 | ALUSrcB <= 2'b01; 375 | RegWrite <= 0; 376 | PCWriteCond <= 0; 377 | 378 | state <= s0; 379 | end 380 | 381 | // if in s12 (Jump completion) go to s0 (IF) 382 | s12: begin 383 | PCWrite <= 1; 384 | DMEMWrite <= 0; 385 | IRWrite <= 1; 386 | PCSource <= 2'b00; 387 | ALUSel <= 4'b0010; 388 | ALUSrcA <= 0; 389 | ALUSrcB <= 2'b01; 390 | RegWrite <= 0; 391 | PCWriteCond <= 0; 392 | 393 | state <= s0; 394 | end 395 | 396 | // if in R1 read 397 | s14: begin 398 | // if Branch, go to s11, branch completion 399 | if (opcode[5:4] == BR) begin 400 | PCWrite <= 0; 401 | PCWriteCond <= 1; 402 | DMEMWrite <= 0; 403 | IRWrite <= 0; 404 | PCSource <= 2'b01; 405 | ALUSel <= 4'b0011; 406 | ALUSrcA <= 1; 407 | ALUSrcB <= 2'b00; 408 | RegWrite <= 0; 409 | RegReadSel <= 1; 410 | 411 | state <= s11; 412 | end 413 | // if LI, go to s9 LI WB 414 | if (opcode[3:0] == LI) begin 415 | PCWrite <= 0; 416 | DMEMWrite <= 0; 417 | IRWrite <= 0; 418 | MemtoReg <= 2'b10; 419 | RegWrite <= 1; 420 | 421 | state <= s9; 422 | end 423 | // if LUI, go to s10 LUI WB 424 | else if (opcode[3:0] == LUI) begin 425 | PCWrite <= 0; 426 | DMEMWrite <= 0; 427 | IRWrite <= 0; 428 | MemtoReg <= 2'b11; 429 | RegWrite <= 1; 430 | 431 | state <= s10; 432 | end 433 | // if SWI, go to s8, Mem Access 434 | else if (opcode[3:0] == SWI) begin 435 | PCWrite <= 0; 436 | DMEMWrite <= 1; 437 | IRWrite <= 0; 438 | RegWrite <= 0; 439 | 440 | state <= s8; 441 | end 442 | end 443 | // go to s0 444 | default: begin 445 | PCWrite <= 1; 446 | DMEMWrite <= 0; 447 | IRWrite <= 1; 448 | PCSource <= 2'b00; 449 | ALUSel <= 4'b0010; 450 | ALUSrcA <= 0; 451 | ALUSrcB <= 2'b01; 452 | RegWrite <= 0; 453 | PCWriteCond <= 0; 454 | 455 | state <= s0; 456 | end 457 | endcase 458 | end 459 | end 460 | endmodule 461 | -------------------------------------------------------------------------------- /src/Implementation/datapath.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: John Careaga 5 | // 6 | // Create Date: 06:17:16 11/24/2014 7 | // Design Name: 8 | // Module Name: datapath 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 23 | // ~~~~~~~~~~~~~~~~~~~ DATAPATH ~~~~~~~~~~~~~~~~~~~ // 24 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 25 | 26 | module datapath(clk, reset, PCWrite, PCWriteCond, IRWrite, DMEMWrite, RegWrite, 27 | ALUSrcA, RegReadSel, MemtoReg, ALUSrcB, PCSource, ALUSel, 28 | opcode); 29 | 30 | // ~~~~~~~~~~~~~~~~~~~ PORTS ~~~~~~~~~~~~~~~~~~~ // 31 | 32 | input PCWrite, PCWriteCond, IRWrite, DMEMWrite, RegWrite, ALUSrcA, RegReadSel /* 0 for R3, 1 for R1*/; 33 | input [1:0] MemtoReg, ALUSrcB, PCSource; 34 | input [3:0] ALUSel; 35 | input clk, reset; 36 | output [5:0] opcode; 37 | 38 | // ~~~~~~~~~~~~~~~~~~~ PARAMETERS ~~~~~~~~~~~~~~~~~~~ // 39 | 40 | parameter word_size = 32; 41 | 42 | // ~~~~~~~~~~~~~~~~~~~ WIRES ~~~~~~~~~~~~~~~~~~~ // 43 | 44 | // PC 45 | wire [word_size-1:0] PCin; 46 | wire [word_size-1:0] PCout; 47 | 48 | // Instruction Memory 49 | wire [word_size-1:0] IMout; 50 | 51 | // Instruction Register 52 | wire [word_size-1:0] IRout; 53 | wire [15:0] immediate; 54 | 55 | // Data Memory 56 | wire [word_size-1:0] DMout; 57 | 58 | // Memory Data Register 59 | wire [word_size-1:0] MDRout; 60 | 61 | // Sign/Zero Extension 62 | wire [word_size-1:0] immZE, immSE; 63 | 64 | // Reg File 65 | wire [4:0] read_sel_1, read_sel_2, write_address; 66 | wire [word_size-1:0] write_data; 67 | wire [word_size-1:0] read_data_1, read_data_2; 68 | 69 | // A and B outputs 70 | wire [word_size-1:0] Aout, Bout; 71 | 72 | // Jump ALU 73 | wire [word_size-1:0] jump_target; 74 | 75 | // ALU 76 | wire [word_size-1:0] sourceA, sourceB; 77 | wire [word_size-1:0] ALU_wire; 78 | wire zero; 79 | 80 | // ALUOut 81 | wire [word_size-1:0] ALUOut_wire; 82 | 83 | // ~~~~~~~~~~~~~~~~~~~ PC WRITE SIGNAL ~~~~~~~~~~~~~~~~~~~ // 84 | 85 | wire w1; 86 | and and1(w1, PCWriteCond, zero); 87 | or or1(PCWrite_datapath, w1, PCWrite); 88 | 89 | // ~~~~~~~~~~~~~~~~~~~ ASSIGNMENTS ~~~~~~~~~~~~~~~~~~~ // 90 | 91 | assign opcode = IRout[31:26]; 92 | assign immediate = IRout[15:0]; 93 | assign write_address = IRout[25:21]; // R1 94 | assign read_sel_1 = IRout[20:16]; // R2 95 | 96 | // ~~~~~~~~~~~~~~~~~~~ MEMORY ~~~~~~~~~~~~~~~~~~~ // 97 | 98 | // INSTRUCTION MEM 99 | IMem IM(PCout, IMout); 100 | 101 | // DATA MEM 102 | DMem DM(Bout, DMout, immediate, DMEMWrite, clk); 103 | 104 | // MEM DATA REGISTER 105 | holding_reg MDR(MDRout, DMout, 1'b1, clk, reset); 106 | 107 | // Reg File 108 | nbit_register_file RF(write_data, 109 | read_data_1, read_data_2, 110 | read_sel_1, read_sel_2, 111 | write_address, RegWrite, clk); 112 | 113 | // ~~~~~~~~~~~~~~~~~~~ INTERNAL REGISTERS ~~~~~~~~~~~~~~~~~~~ // 114 | 115 | // PC 116 | holding_reg PC(PCout, PCin, PCWrite_datapath, clk, reset); 117 | 118 | // INSTRUCTION REGISTER 119 | holding_reg IR(IRout, IMout, IRWrite, clk, reset); 120 | 121 | // A and B 122 | holding_reg A(Aout, read_data_1, 1'b1, clk, reset); 123 | holding_reg B(Bout, read_data_2, 1'b1, clk, reset); 124 | 125 | // ALUOut Register 126 | holding_reg ALUOut(ALUOut_wire, ALU_wire, 1'b1, clk, reset); 127 | 128 | // ~~~~~~~~~~~~~~~~~~~ EXTENDERS ~~~~~~~~~~~~~~~~~~~ // 129 | 130 | // ZE(imm) and SE(imm) 131 | zero_extend ZE(immediate, immZE); 132 | sign_extend SE(immediate, immSE); 133 | 134 | // ~~~~~~~~~~~~~~~~~~~ MULTIPLEXERS ~~~~~~~~~~~~~~~~~~~ // 135 | 136 | // Reg File inputs 137 | read_mux read_sel_mux(read_sel_2, IRout[15:11], IRout[25:21], RegReadSel); //B is R3 or R1 138 | mux_2bit write_data_mux(write_data, ALUOut_wire, MDRout, {read_data_2[31:16],immediate}, {immediate,read_data_2[15:0]}, MemtoReg); 139 | 140 | // ALU inputs 141 | mux_1bit ALUSrcA_mux(sourceA, PCout, Aout, ALUSrcA); // alusrca = 0 -> sourceA = pc 142 | mux_2bit ALUSrcB_mux(sourceB, Bout, 32'd1, immSE, immZE, ALUSrcB); 143 | 144 | //PC source mux 145 | mux_2bit PC_mux(PCin, ALU_wire, ALUOut_wire, jump_target, 32'h00000000, PCSource); 146 | 147 | // ~~~~~~~~~~~~~~~~~~~ JUMP ALU ~~~~~~~~~~~~~~~~~~~ // 148 | 149 | //jump_target, inputPC, offset 150 | jumpALU jALU(jump_target, PCout, immSE); 151 | 152 | // ~~~~~~~~~~~~~~~~~~~ MAIN ALU ~~~~~~~~~~~~~~~~~~~ // 153 | 154 | // ALU 155 | myALU mainALU(ALU_wire, zero, sourceA, sourceB, ALUSel); 156 | endmodule 157 | -------------------------------------------------------------------------------- /src/Implementation/holding_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:25:48 11/22/2014 7 | // Design Name: 8 | // Module Name: holding_reg 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // Registers for PC, IR, A, B, ALUOut 23 | module holding_reg(output_data, input_data, write, clk, reset); 24 | // data size 25 | parameter word_size = 32; 26 | // inputs 27 | input [word_size-1:0] input_data; 28 | input write, clk, reset; 29 | 30 | // outputs 31 | output [word_size-1:0] output_data; 32 | 33 | // Register content and output assignment 34 | reg [word_size-1:0] content; 35 | assign output_data = content; 36 | 37 | // update regisiter contents 38 | always @(posedge clk) begin 39 | if (reset) begin 40 | content <= 0; 41 | end 42 | else if (write) begin 43 | content <= input_data; 44 | end 45 | end 46 | endmodule 47 | -------------------------------------------------------------------------------- /src/Implementation/jumpALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:45:54 11/22/2014 7 | // Design Name: 8 | // Module Name: jumpALU 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // ALU for jump target calculations 23 | module jumpALU(jump_target, inputPC, offset); 24 | parameter word_size = 32; 25 | 26 | // inputs and outpust 27 | input [word_size-1:0] inputPC, offset; 28 | output [word_size-1:0] jump_target; 29 | 30 | // assign target 31 | assign jump_target = inputPC + offset; 32 | endmodule 33 | -------------------------------------------------------------------------------- /src/Implementation/mux_1bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:31:38 11/22/2014 7 | // Design Name: 8 | // Module Name: mux_1bit 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // Mulitiplexer for selecting from two 32-bit inputs 23 | module mux_1bit(output_data, input_data0, input_data1, select); 24 | parameter word_size = 32; 25 | 26 | // inputs 27 | input select; 28 | input [word_size-1:0] input_data0, input_data1; 29 | 30 | // output 31 | output reg [word_size-1:0] output_data; 32 | 33 | // select the input 34 | always @(select or input_data0 or input_data1) begin 35 | case (select) 36 | 0: output_data <= input_data0; 37 | 1: output_data <= input_data1; 38 | default: output_data <= 0; 39 | endcase 40 | end 41 | endmodule 42 | -------------------------------------------------------------------------------- /src/Implementation/mux_2bit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:14:37 11/22/2014 7 | // Design Name: 8 | // Module Name: mux_2bit 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // Multiplexer for choosing between four 32-bit inputs 23 | module mux_2bit(output_data, input_data0, input_data1, input_data2, input_data3, select); 24 | parameter word_size = 32; 25 | 26 | // inputs 27 | input [1:0] select; 28 | input [word_size-1:0] input_data0, input_data1, input_data2, input_data3; 29 | 30 | // output 31 | output reg [word_size-1:0] output_data; 32 | 33 | // select the input 34 | always @(input_data0 or input_data1 or input_data2 or input_data3 or select) begin 35 | case (select) 36 | 0: output_data <= input_data0; 37 | 1: output_data <= input_data1; 38 | 2: output_data <= input_data2; 39 | 3: output_data <= input_data3; 40 | default: output_data <= 0; 41 | endcase 42 | end 43 | endmodule 44 | -------------------------------------------------------------------------------- /src/Implementation/myALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 23:26:51 11/22/2014 7 | // Design Name: 8 | // Module Name: myALU 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // Main ALU 23 | module myALU(output_data, zero, sourceA, sourceB, ALUSel); 24 | parameter word_size = 32; 25 | 26 | // inputs 27 | input [word_size-1:0] sourceA, sourceB; 28 | input [3:0] ALUSel; 29 | 30 | // outputs 31 | output reg [word_size-1:0] output_data; 32 | output reg zero; 33 | 34 | // if any input changes, update output 35 | always @(sourceA, sourceB, ALUSel) begin 36 | // operation depends on ALUSel input 37 | case (ALUSel) 38 | 4'h0: output_data = sourceA; 39 | 4'h1: output_data = ~sourceA; 40 | 4'h2: output_data = sourceA + sourceB; 41 | 4'h3: begin 42 | output_data = sourceA - sourceB; 43 | if ((sourceA - sourceB) == 0) begin 44 | zero = 1; 45 | end 46 | else begin 47 | zero = 0; 48 | end 49 | end 50 | 4'h4: output_data = sourceA | sourceB; 51 | 4'h5: output_data = sourceA & sourceB; 52 | 4'h6: output_data = sourceA ^ sourceB; 53 | 4'h7: output_data = ($signed(sourceA) < $signed(sourceB))? 1 : 0; 54 | default: output_data = 0; 55 | endcase 56 | end 57 | endmodule 58 | -------------------------------------------------------------------------------- /src/Implementation/nbit_register_file.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:37:55 11/22/2014 7 | // Design Name: 8 | // Module Name: nbit_register_file 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | // This can be used to replace the original nbit_register_file in lab6. 22 | // In iSim you can actually expand this reg_file to view the contents in it. 23 | 24 | module nbit_register_file(write_data, 25 | read_data_1, read_data_2, 26 | read_sel_1, read_sel_2, 27 | write_address, RegWrite, clk); 28 | 29 | parameter data_width = 32; 30 | parameter select_width = 5; 31 | 32 | input clk, RegWrite; 33 | input [data_width-1:0] write_data; 34 | input [4:0] read_sel_1, read_sel_2, write_address; 35 | output [data_width-1:0] read_data_1, read_data_2; 36 | 37 | reg [data_width-1:0] register_file [0:data_width-1]; 38 | 39 | // for loop initializes all registers to 0, no need to rst 40 | integer i; 41 | initial begin 42 | for (i = 0; i < 32; i = i + 1) begin 43 | register_file[i] = 32'd0; 44 | end 45 | end 46 | 47 | 48 | assign read_data_1 = register_file[read_sel_1]; 49 | assign read_data_2 = register_file[read_sel_2]; 50 | 51 | 52 | always @ (posedge clk) begin 53 | if (RegWrite) 54 | register_file[write_address] <= write_data; 55 | end 56 | endmodule 57 | -------------------------------------------------------------------------------- /src/Implementation/read_mux.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 02:33:22 11/23/2014 7 | // Design Name: 8 | // Module Name: read_mux 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // Register 2 read select multiplexer 23 | module read_mux(output_data, input_data0, input_data1, select); 24 | parameter word_size = 5; 25 | 26 | // inputs 27 | input select; 28 | input [word_size-1:0] input_data0, input_data1; 29 | 30 | // output 31 | output reg [word_size-1:0] output_data; 32 | 33 | // select the input 34 | always @(select or input_data0 or input_data1) begin 35 | case (select) 36 | 0: output_data <= input_data0; 37 | 1: output_data <= input_data1; 38 | default: output_data <= 0; 39 | endcase 40 | end 41 | endmodule 42 | -------------------------------------------------------------------------------- /src/Implementation/sign_extend.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:02:19 11/22/2014 7 | // Design Name: 8 | // Module Name: sign_extend 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // sign extend module 23 | module sign_extend(input_data, output_data); 24 | // parameters 25 | parameter word_size = 32; 26 | parameter imm_size = 16; 27 | 28 | // inputs and outputs 29 | input [imm_size-1:0] input_data; 30 | output [word_size-1:0] output_data; 31 | 32 | // output assignment 33 | assign output_data = $signed(input_data); 34 | endmodule 35 | -------------------------------------------------------------------------------- /src/Implementation/zero_extend.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:23:40 11/22/2014 7 | // Design Name: 8 | // Module Name: zero_extend 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // zero extend module 23 | module zero_extend(input_data, output_data); 24 | // parameters 25 | parameter word_size = 32; 26 | parameter imm_size = 16; 27 | 28 | // input and output 29 | input [imm_size-1:0] input_data; 30 | output [word_size-1:0] output_data; 31 | 32 | // output assignment 33 | assign output_data = $unsigned(input_data); 34 | endmodule 35 | -------------------------------------------------------------------------------- /src/Tests/MultiCycleCPU_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: John Careaga 6 | // 7 | // Create Date: 06:29:06 11/24/2014 8 | // Design Name: MultiCycleCPU 9 | // Module Name: /ad/eng/users/j/o/johnc219/EC413/MultiCycleCPU3/MultiCycleCPU_test3b.v 10 | // Project Name: MultiCycleCPU3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: MultiCycleCPU 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 26 | // ~~~~~~~~~~~~~~~~~~~ CPU TEST BENCH ~~~~~~~~~~~~~~~~~~~ // 27 | // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // 28 | 29 | module MultiCycleCPU_test; 30 | 31 | // Inputs 32 | reg clk; 33 | reg reset; 34 | 35 | // Instantiate the Unit Under Test (UUT) 36 | MultiCycleCPU uut ( 37 | .clk(clk), 38 | .reset(reset) 39 | ); 40 | always 41 | #5 clk = ~clk; 42 | initial begin 43 | // Initialize Inputs 44 | clk = 0; 45 | reset = 1; 46 | 47 | // Wait 100 ns for global reset to finish 48 | #100; 49 | 50 | // Add stimulus here 51 | reset <= 0; // drop reset 52 | #1245; // wait for program to execute 53 | 54 | reset <= 1; // reset cpu 55 | #40; 56 | reset <= 0; // program restarts 57 | end 58 | 59 | endmodule 60 | -------------------------------------------------------------------------------- /src/Tests/controllerTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 15:52:00 12/02/2014 8 | // Design Name: controller 9 | // Module Name: /ad/eng/users/j/o/johnc219/EC413/MultiCycleCPU3/controllerTest3.v 10 | // Project Name: MultiCycleCPU3 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: controller 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module controllerTest; 26 | 27 | // Inputs 28 | reg [5:0] opcode; 29 | reg clk; 30 | reg reset; 31 | 32 | // Outputs 33 | wire PCWrite; 34 | wire PCWriteCond; 35 | wire DMEMWrite; 36 | wire IRWrite; 37 | wire [1:0] MemtoReg; 38 | wire [1:0] PCSource; 39 | wire [3:0] ALUSel; 40 | wire ALUSrcA; 41 | wire [1:0] ALUSrcB; 42 | wire RegWrite; 43 | wire RegReadSel; 44 | 45 | // Instantiate the Unit Under Test (UUT) 46 | controller uut ( 47 | .opcode(opcode), 48 | .clk(clk), 49 | .reset(reset), 50 | .PCWrite(PCWrite), 51 | .PCWriteCond(PCWriteCond), 52 | .DMEMWrite(DMEMWrite), 53 | .IRWrite(IRWrite), 54 | .MemtoReg(MemtoReg), 55 | .PCSource(PCSource), 56 | .ALUSel(ALUSel), 57 | .ALUSrcA(ALUSrcA), 58 | .ALUSrcB(ALUSrcB), 59 | .RegWrite(RegWrite), 60 | .RegReadSel(RegReadSel) 61 | ); 62 | 63 | always 64 | #5 clk = ~clk; 65 | 66 | initial begin 67 | // Initialize Inputs 68 | opcode = 0; 69 | clk = 0; 70 | reset = 1; 71 | 72 | // Wait 100 ns for global reset to finish 73 | #100; 74 | 75 | // Add stimulus here 76 | // clear reset 77 | reset = 0; 78 | 79 | // type //FN // state sequence 80 | 81 | // R-TYPE 82 | opcode <= 6'b010000; //MOV 0 1 2 6 83 | #55; 84 | opcode <= 6'b010001; //NOT 0 1 2 6 85 | #40; 86 | opcode <= 6'b010010; //ADD 0 1 2 6 87 | #40; 88 | opcode <= 6'b010011; //SUB 0 1 2 6 89 | #40; 90 | opcode <= 6'b010100; //OR 0 1 2 6 91 | #40; 92 | opcode <= 6'b010101; //AND 0 1 2 6 93 | #40; 94 | opcode <= 6'b010110; //XOR 0 1 2 6 95 | #40; 96 | opcode <= 6'b010111; //SLT 0 1 2 6 97 | 98 | 99 | // JUMP 100 | opcode <= 6'b000001; // J 0 1 14 12 101 | #30; 102 | // BRANCH 103 | opcode <= 6'b100000; //BEQ 0 1 14 11 104 | #30; 105 | // I-type 106 | opcode <= 6'b110010; // ADDI 0 1 3 6 107 | #40; 108 | opcode <= 6'b110011; // SUBI 0 1 3 6 109 | #40; 110 | opcode <= 6'b110100; // ORI 0 1 4 6 111 | #40; 112 | opcode <= 6'b110101; // ANDI 0 1 4 6 113 | #40; 114 | opcode <= 6'b110110; // XORI 0 1 4 6 115 | #40; 116 | opcode <= 6'b110111; // SLTI 0 1 3 6 117 | #40; 118 | opcode <= 6'b111001; // LI 0 1 14 9 119 | #40; 120 | opcode <= 6'b111010; // LUI 0 1 14 10 121 | #40; 122 | opcode <= 6'b111011; // LWI 0 1 5 7 123 | #40; 124 | opcode <= 6'b111100; // SWI 0 1 14 8 125 | #40; 126 | reset <= 1; 127 | #20; 128 | reset <= 0; 129 | opcode <= 6'b000000; // NOP 0 1 130 | 131 | end 132 | 133 | endmodule 134 | -------------------------------------------------------------------------------- /src/Tests/holding_reg_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 21:38:46 11/22/2014 8 | // Design Name: holding_reg 9 | // Module Name: /ad/eng/users/j/o/johnc219/EC413/MultiCycleCPU/holding_reg_test.v 10 | // Project Name: MultiCycleCPU 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: holding_reg 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module holding_reg_test; 26 | 27 | // Inputs 28 | reg [31:0] input_data; 29 | reg write; 30 | reg clk; 31 | reg reset; 32 | 33 | // Outputs 34 | wire [31:0] output_data; 35 | 36 | // Instantiate the Unit Under Test (UUT) 37 | holding_reg uut ( 38 | .output_data(output_data), 39 | .input_data(input_data), 40 | .write(write), 41 | .clk(clk), 42 | .reset(reset) 43 | ); 44 | 45 | always 46 | #5 clk = ~clk; 47 | 48 | initial begin 49 | // Initialize Inputs 50 | input_data = 0; 51 | write = 0; 52 | clk = 0; 53 | reset = 1; 54 | 55 | // Wait 100 ns for global reset to finish 56 | #100; 57 | 58 | // Add stimulus here 59 | reset <= 0; 60 | 61 | input_data <= 32'hF0F0F0F0; // no write 62 | #15; 63 | 64 | input_data <= 32'hAFAFAFAF; 65 | write <= 1; // writing enabled 66 | #15; 67 | 68 | reset <= 1; // clear contents 69 | #26; 70 | 71 | reset <= 0; 72 | end 73 | 74 | endmodule 75 | 76 | -------------------------------------------------------------------------------- /src/Tests/jumpALU_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 23:52:28 11/22/2014 8 | // Design Name: jumpALU 9 | // Module Name: /ad/eng/users/j/o/johnc219/EC413/MultiCycleCPU/jumpALU_test.v 10 | // Project Name: MultiCycleCPU 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: jumpALU 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module jumpALU_test; 26 | 27 | // Inputs 28 | reg [31:0] inputPC; 29 | reg [31:0] offset; 30 | 31 | // Outputs 32 | wire [31:0] jump_target; 33 | 34 | // Instantiate the Unit Under Test (UUT) 35 | jumpALU uut ( 36 | .jump_target(jump_target), 37 | .inputPC(inputPC), 38 | .offset(offset) 39 | ); 40 | 41 | initial begin 42 | // Initialize Inputs 43 | inputPC = 0; 44 | offset = 0; 45 | 46 | // Wait 100 ns for global reset to finish 47 | #100; 48 | 49 | // Add stimulus here 50 | inputPC = 32'h0000000E; // 13 51 | offset = 32'h00000001; // 1 52 | #20; 53 | 54 | offset = 32'hFFFFFFFF; // -1 55 | end 56 | 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /src/Tests/mux_1bit_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 22:39:02 11/22/2014 8 | // Design Name: mux_1bit 9 | // Module Name: /ad/eng/users/j/o/johnc219/EC413/MultiCycleCPU/mux_1bit_test.v 10 | // Project Name: MultiCycleCPU 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: mux_1bit 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module mux_1bit_test; 26 | 27 | // Inputs 28 | reg [31:0] input_data0; 29 | reg [31:0] input_data1; 30 | reg select; 31 | 32 | // Outputs 33 | wire [31:0] output_data; 34 | 35 | // Instantiate the Unit Under Test (UUT) 36 | mux_1bit uut ( 37 | .output_data(output_data), 38 | .input_data0(input_data0), 39 | .input_data1(input_data1), 40 | .select(select) 41 | ); 42 | 43 | initial begin 44 | // Initialize Inputs 45 | input_data0 = 0; 46 | input_data1 = 0; 47 | select = 0; 48 | 49 | // Wait 100 ns for global reset to finish 50 | #100; 51 | 52 | // Add stimulus here 53 | input_data0 = 32'hFFFF0000; // input 0 54 | input_data1 = 32'h0000FFFF; // input 1 55 | #20; 56 | 57 | select = 1; // change selected input 58 | #20; 59 | 60 | input_data0 = 32'h88888888; // change input 0 61 | input_data1 = 32'hFEFEFEFE; // change input 1 62 | 63 | #20; 64 | select = 0; // change selected inpu 65 | end 66 | 67 | endmodule 68 | 69 | -------------------------------------------------------------------------------- /src/Tests/sign_extend_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 22:17:00 11/22/2014 8 | // Design Name: sign_extend 9 | // Module Name: /ad/eng/users/j/o/johnc219/EC413/MultiCycleCPU/sign_extend_test.v 10 | // Project Name: MultiCycleCPU 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: sign_extend 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module sign_extend_test; 26 | 27 | // Inputs 28 | reg [15:0] input_data; 29 | 30 | // Outputs 31 | wire [31:0] output_data; 32 | 33 | // Instantiate the Unit Under Test (UUT) 34 | sign_extend uut ( 35 | .input_data(input_data), 36 | .output_data(output_data) 37 | ); 38 | 39 | initial begin 40 | // Initialize Inputs 41 | input_data = 0; 42 | 43 | // Wait 100 ns for global reset to finish 44 | #100; 45 | 46 | // Add stimulus here 47 | input_data = 16'hFFFF; // negative number 48 | #20; 49 | 50 | input_data = 16'h7FFF; // positive number 51 | end 52 | 53 | endmodule 54 | 55 | -------------------------------------------------------------------------------- /src/Tests/zero_extend_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 22:25:49 11/22/2014 8 | // Design Name: zero_extend 9 | // Module Name: /ad/eng/users/j/o/johnc219/EC413/MultiCycleCPU/zero_extend_test.v 10 | // Project Name: MultiCycleCPU 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: zero_extend 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module zero_extend_test; 26 | 27 | // Inputs 28 | reg [15:0] input_data; 29 | 30 | // Outputs 31 | wire [31:0] output_data; 32 | 33 | // Instantiate the Unit Under Test (UUT) 34 | zero_extend uut ( 35 | .input_data(input_data), 36 | .output_data(output_data) 37 | ); 38 | 39 | initial begin 40 | // Initialize Inputs 41 | input_data = 0; 42 | 43 | // Wait 100 ns for global reset to finish 44 | #100; 45 | 46 | // Add stimulus here 47 | input_data = 16'hFFFF; // negative number 48 | #20; 49 | 50 | input_data = 16'h7FFF; // positive number 51 | end 52 | 53 | endmodule 54 | 55 | --------------------------------------------------------------------------------