├── .gitignore ├── book ├── programs │ ├── src │ │ ├── .gitignore │ │ ├── li │ │ │ ├── .gitignore │ │ │ ├── run.sh │ │ │ ├── li.S │ │ │ ├── Makefile │ │ │ ├── li.lst │ │ │ └── li.out │ │ ├── mv │ │ │ ├── .gitignore │ │ │ ├── run.sh │ │ │ ├── mv.S │ │ │ ├── mv.lst │ │ │ ├── Makefile │ │ │ └── mv.out │ │ ├── mvzero │ │ │ ├── .gitignore │ │ │ ├── run.sh │ │ │ ├── mv.S │ │ │ ├── mv.lst │ │ │ ├── Makefile │ │ │ └── mv.out │ │ ├── nop │ │ │ ├── .gitignore │ │ │ ├── run.sh │ │ │ ├── nop.lst │ │ │ ├── nop.S │ │ │ ├── Makefile │ │ │ └── nop.out │ │ ├── ebreak │ │ │ ├── .gitignore │ │ │ ├── ebreak.S │ │ │ ├── ebreak.lst │ │ │ ├── run.sh │ │ │ ├── Makefile │ │ │ └── ebreak.out │ │ ├── Makefile │ │ └── Make.rules │ └── chapter.tex ├── colors.tex ├── .gitignore ├── elements │ ├── zero4regs.S │ ├── zero4regs.out │ └── chapter.tex ├── Makefile ├── float │ ├── erroraccumulation.c │ ├── cleandecimal.c │ ├── powersoftwo.c │ ├── errorcompensation.c │ ├── powersoftwo.out │ ├── cleandecimal.out │ ├── erroraccumulation.out │ ├── errorcompensation.out │ └── chapter.tex ├── amodes │ └── chapter.tex ├── copyright │ └── chapter.tex ├── rv32 │ └── insn │ │ └── lui.tex ├── toolchain │ └── chapter.tex ├── binary │ └── rvddt_memdump.out ├── rv32m │ └── chapter.tex ├── preface │ └── chapter.tex ├── rvalp.tex ├── bibliography.bib ├── install │ └── chapter.tex ├── glossary.tex ├── ascii │ └── chapter.tex ├── priv │ └── chapter.tex ├── preamble.tex ├── insnsummary │ └── chapter.tex ├── refcard │ └── chapter.tex ├── intro │ └── chapter.tex └── license │ └── chapter.tex ├── Makefile ├── texlib ├── index.ist ├── ENote.sty ├── MyFigs.sty └── MyVerbatim.sty ├── Make.rules ├── README.md └── LICENSE /.gitignore: -------------------------------------------------------------------------------- 1 | *.swp 2 | -------------------------------------------------------------------------------- /book/programs/src/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | -------------------------------------------------------------------------------- /book/programs/src/li/.gitignore: -------------------------------------------------------------------------------- 1 | li 2 | -------------------------------------------------------------------------------- /book/programs/src/mv/.gitignore: -------------------------------------------------------------------------------- 1 | mv 2 | -------------------------------------------------------------------------------- /book/programs/src/mvzero/.gitignore: -------------------------------------------------------------------------------- 1 | mv 2 | -------------------------------------------------------------------------------- /book/programs/src/nop/.gitignore: -------------------------------------------------------------------------------- 1 | nop 2 | -------------------------------------------------------------------------------- /book/programs/src/ebreak/.gitignore: -------------------------------------------------------------------------------- 1 | ebreak 2 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | TOP=. 2 | 3 | SUBDIRS=book 4 | 5 | include $(TOP)/Make.rules 6 | -------------------------------------------------------------------------------- /book/programs/src/li/run.sh: -------------------------------------------------------------------------------- 1 | prompt="$" 2 | cmd="rvddt -f li.bin" 3 | echo "$prompt $cmd" 4 | $cmd <: 4 | 0: 00100073 ebreak 5 | -------------------------------------------------------------------------------- /book/programs/src/ebreak/run.sh: -------------------------------------------------------------------------------- 1 | prompt="$" 2 | cmd="rvddt -f ebreak.bin" 3 | echo "$prompt $cmd" 4 | $cmd <: 4 | 0: 00000e13 li t3,0 5 | 4: 00100073 ebreak 6 | -------------------------------------------------------------------------------- /texlib/index.ist: -------------------------------------------------------------------------------- 1 | % Style for makeindex 2 | % This style simply adds a bolded letter for each part of the alphabet 3 | heading_prefix "{\\bfseries " 4 | heading_suffix "\\hfil}\\nopagebreak\n" 5 | headings_flag 1 6 | -------------------------------------------------------------------------------- /book/programs/src/nop/nop.lst: -------------------------------------------------------------------------------- 1 | nop: file format elf32-littleriscv 2 | Disassembly of section .text: 3 | 00000000 <_start>: 4 | 0: 00000013 nop 5 | 4: 00000013 nop 6 | 8: 00100073 ebreak 7 | -------------------------------------------------------------------------------- /book/programs/src/mv/mv.S: -------------------------------------------------------------------------------- 1 | .text # put this into the text section 2 | .align 2 # align to a multiple of 4 3 | .globl _start 4 | 5 | _start: 6 | addi t3, t4, 0 # t3 = t4 7 | mv t3, t4 # t3 = t4 8 | 9 | ebreak 10 | -------------------------------------------------------------------------------- /book/programs/src/mv/mv.lst: -------------------------------------------------------------------------------- 1 | mv: file format elf32-littleriscv 2 | Disassembly of section .text: 3 | 00000000 <_start>: 4 | 0: 000e8e13 mv t3,t4 5 | 4: 000e8e13 mv t3,t4 6 | 8: 00100073 ebreak 7 | -------------------------------------------------------------------------------- /book/colors.tex: -------------------------------------------------------------------------------- 1 | % These are color styles used in the figures in this book. 2 | \definecolor{c_lightblue}{HTML}{B0E0FF} 3 | \definecolor{c_lightred}{HTML}{FFE0E0} 4 | \definecolor{c_lightyellow}{HTML}{FFE060} 5 | \definecolor{c_lightgreen}{HTML}{C0FFC0} 6 | -------------------------------------------------------------------------------- /book/programs/src/nop/nop.S: -------------------------------------------------------------------------------- 1 | .text # put this into the text section 2 | .align 2 # align to a multiple of 4 3 | .globl _start 4 | 5 | _start: 6 | addi x0, x0, 0 # these two instructions assemble into the same thing! 7 | nop 8 | 9 | ebreak 10 | -------------------------------------------------------------------------------- /book/programs/src/li/li.S: -------------------------------------------------------------------------------- 1 | .text # put this into the text section 2 | .align 2 # align to a multiple of 4 3 | .globl _start 4 | 5 | _start: 6 | li t0, 0x12345678 7 | li t1, 0x11111fff 8 | li t1, 0 9 | li t1, -1 10 | li t1, 1 11 | li t1, 0xf1f1f1f1 12 | ebreak 13 | -------------------------------------------------------------------------------- /book/.gitignore: -------------------------------------------------------------------------------- 1 | rvalp.aux 2 | rvalp.brf 3 | rvalp.idx 4 | rvalp.ilg 5 | rvalp.ind 6 | rvalp.lof 7 | rvalp.log 8 | rvalp.pdf 9 | rvalp.toc 10 | rvalp.bbl 11 | rvalp.blg 12 | rvalp.out 13 | *.aux 14 | rvalp.glg 15 | rvalp.glo 16 | rvalp.gls 17 | rvalp.glsdefs 18 | rvalp.ist 19 | *.bak 20 | out-rvalp.pdf 21 | -------------------------------------------------------------------------------- /book/programs/src/li/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PROG=li 3 | 4 | all:: $(PROG).out $(PROG).lst 5 | 6 | $(PROG).out:: $(PROG).bin 7 | ./run.sh > $@ 2>&1 8 | 9 | $(PROG).bin:: $(PROG) 10 | 11 | clean:: 12 | rm -f $(PROG) *.o *.lst *.bin *.srec *.out 13 | 14 | TOP=.. 15 | include $(TOP)/Make.rules 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /book/programs/src/mv/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PROG=mv 3 | 4 | all:: $(PROG).out $(PROG).lst 5 | 6 | $(PROG).out:: $(PROG).bin 7 | ./run.sh > $@ 2>&1 8 | 9 | $(PROG).bin:: $(PROG) 10 | 11 | clean:: 12 | rm -f $(PROG) *.o *.lst *.bin *.srec *.out 13 | 14 | TOP=.. 15 | include $(TOP)/Make.rules 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /book/programs/src/nop/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PROG=nop 3 | 4 | all:: $(PROG).out $(PROG).lst 5 | 6 | $(PROG).out:: $(PROG).bin 7 | ./run.sh > $@ 2>&1 8 | 9 | $(PROG).bin:: $(PROG) 10 | 11 | clean:: 12 | rm -f $(PROG) *.o *.lst *.bin *.srec *.out 13 | 14 | TOP=.. 15 | include $(TOP)/Make.rules 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /book/programs/src/ebreak/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PROG=ebreak 3 | 4 | all:: $(PROG).out $(PROG).lst 5 | 6 | $(PROG).out:: $(PROG).bin 7 | ./run.sh > $@ 2>&1 8 | 9 | $(PROG).bin:: $(PROG) 10 | 11 | clean:: 12 | rm -f $(PROG) *.o *.lst *.bin *.srec *.out 13 | 14 | TOP=.. 15 | include $(TOP)/Make.rules 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /book/programs/src/mvzero/Makefile: -------------------------------------------------------------------------------- 1 | 2 | PROG=mv 3 | 4 | all:: $(PROG).out $(PROG).lst 5 | 6 | $(PROG).out:: $(PROG).bin 7 | ./run.sh > $@ 2>&1 8 | 9 | $(PROG).bin:: $(PROG) 10 | 11 | clean:: 12 | rm -f $(PROG) *.o *.lst *.bin *.srec *.out 13 | 14 | TOP=.. 15 | include $(TOP)/Make.rules 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /book/elements/zero4regs.S: -------------------------------------------------------------------------------- 1 | .text # put this into the text section 2 | .align 2 # align to 2^2 3 | .globl _start 4 | _start: 5 | addi x28, x0, 0 # set register x28 to zero 6 | addi x29, x0, 0 # set register x29 to zero 7 | addi x30, x0, 0 # set register x30 to zero 8 | addi x31, x0, 0 # set register x31 to zero 9 | -------------------------------------------------------------------------------- /book/Makefile: -------------------------------------------------------------------------------- 1 | SUBDIRS= 2 | # programs/src 3 | 4 | TOP=.. 5 | include $(TOP)/Make.rules 6 | 7 | TEXPATH=float:intro:rv32:copyright:license:elements:binary:programs/src 8 | 9 | all:: rvalp.pdf 10 | 11 | clean:: 12 | rm -f rvalp.pdf */*.aux $(LATEX_CLEANFILES) 13 | 14 | rvalp.pdf:: *.tex bibliography.bib 15 | 16 | spell: 17 | #find . -name "*.tex" -exec aspell --lang=en --mode=tex check "{}" \; 18 | find . -name "*.tex" -exec aspell --mode=tex check "{}" \; 19 | -------------------------------------------------------------------------------- /book/float/erroraccumulation.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | union floatbin 6 | { 7 | unsigned int i; 8 | float f; 9 | }; 10 | int main() 11 | { 12 | union floatbin x, y; 13 | int i; 14 | 15 | x.f = .1; 16 | while (x.f <= 2.0) 17 | { 18 | y.f = -x.f; 19 | printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); 20 | x.f += .1; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /book/float/cleandecimal.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | union floatbin 6 | { 7 | unsigned int i; 8 | float f; 9 | }; 10 | int main() 11 | { 12 | union floatbin x, y; 13 | int i; 14 | 15 | x.f = 10; 16 | while (x.f <= 10000000000000.0) 17 | { 18 | y.f = -x.f; 19 | printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); 20 | x.f = x.f*10.0; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /book/float/powersoftwo.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | union floatbin 6 | { 7 | unsigned int i; 8 | float f; 9 | }; 10 | int main() 11 | { 12 | union floatbin x; 13 | union floatbin y; 14 | int i; 15 | x.f = 1.0; 16 | while (x.f > 1.0/1024.0) 17 | { 18 | y.f = -x.f; 19 | printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); 20 | x.f = x.f/2.0; 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /book/float/errorcompensation.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | union floatbin 6 | { 7 | unsigned int i; 8 | float f; 9 | }; 10 | int main() 11 | { 12 | union floatbin x, y; 13 | int i; 14 | 15 | i = 1; 16 | while (i <= 20) 17 | { 18 | x.f = i/10.0; 19 | y.f = -x.f; 20 | printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); 21 | i++; 22 | } 23 | return(0); 24 | } 25 | -------------------------------------------------------------------------------- /book/programs/src/li/li.lst: -------------------------------------------------------------------------------- 1 | li: file format elf32-littleriscv 2 | Disassembly of section .text: 3 | 00000000 <_start>: 4 | 0: 123452b7 lui t0,0x12345 5 | 4: 67828293 addi t0,t0,1656 # 12345678 <__global_pointer$+0x12343e50> 6 | 8: 11112337 lui t1,0x11112 7 | c: fff30313 addi t1,t1,-1 # 11111fff <__global_pointer$+0x111107d7> 8 | 10: 00000313 li t1,0 9 | 14: fff00313 li t1,-1 10 | 18: 00100313 li t1,1 11 | 1c: f1f1f337 lui t1,0xf1f1f 12 | 20: 1f130313 addi t1,t1,497 # f1f1f1f1 <__global_pointer$+0xf1f1d9c9> 13 | 24: 00100073 ebreak 14 | -------------------------------------------------------------------------------- /book/amodes/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Addressing Modes} 2 | 3 | 4 | A box showing +/- 2KB regions for \reg{gp} addressing with 5 | LB, LBU, SB, LH, LHU, SH, LW, and SW instructions. 6 | 7 | \BeginTikzPicture 8 | \draw(1.5,0) node{.data}; 9 | \draw[->] (3,0) -- (4,0); % right arrow 10 | 11 | \draw(2,10) node{gp}; 12 | \draw[->] (3,10) -- (4,10); % right arrow 13 | 14 | 15 | % \draw(0,15) node{+2KB}; 16 | % \draw(0,5) node{-2KB}; 17 | \draw[->] (6,9) -- (6,1); % up arrow 18 | \draw[->] (6,11) -- (6,19); % down arrow 19 | 20 | 21 | \draw(6,20) node{\tt 0x8fff}; 22 | \draw(6,10) node{\tt 0x8800}; 23 | \draw(6,0) node{\tt 0x8000}; 24 | \EndTikzPicture 25 | 26 | -------------------------------------------------------------------------------- /book/float/powersoftwo.out: -------------------------------------------------------------------------------- 1 | 1.0000000000 = 3f800000 -1.0000000000 = bf800000 2 | 0.5000000000 = 3f000000 -0.5000000000 = bf000000 3 | 0.2500000000 = 3e800000 -0.2500000000 = be800000 4 | 0.1250000000 = 3e000000 -0.1250000000 = be000000 5 | 0.0625000000 = 3d800000 -0.0625000000 = bd800000 6 | 0.0312500000 = 3d000000 -0.0312500000 = bd000000 7 | 0.0156250000 = 3c800000 -0.0156250000 = bc800000 8 | 0.0078125000 = 3c000000 -0.0078125000 = bc000000 9 | 0.0039062500 = 3b800000 -0.0039062500 = bb800000 10 | 0.0019531250 = 3b000000 -0.0019531250 = bb000000 11 | -------------------------------------------------------------------------------- /book/float/cleandecimal.out: -------------------------------------------------------------------------------- 1 | 10.0000000000 = 41200000 -10.0000000000 = c1200000 2 | 100.0000000000 = 42c80000 -100.0000000000 = c2c80000 3 | 1000.0000000000 = 447a0000 -1000.0000000000 = c47a0000 4 | 10000.0000000000 = 461c4000 -10000.0000000000 = c61c4000 5 | 100000.0000000000 = 47c35000 -100000.0000000000 = c7c35000 6 | 1000000.0000000000 = 49742400 -1000000.0000000000 = c9742400 7 | 10000000.0000000000 = 4b189680 -10000000.0000000000 = cb189680 8 | 100000000.0000000000 = 4cbebc20 -100000000.0000000000 = ccbebc20 9 | 1000000000.0000000000 = 4e6e6b28 -1000000000.0000000000 = ce6e6b28 10 | 10000000000.0000000000 = 501502f9 -10000000000.0000000000 = d01502f9 11 | 99999997952.0000000000 = 51ba43b7 -99999997952.0000000000 = d1ba43b7 12 | 999999995904.0000000000 = 5368d4a5 -999999995904.0000000000 = d368d4a5 13 | 9999999827968.0000000000 = 551184e7 -9999999827968.0000000000 = d51184e7 14 | -------------------------------------------------------------------------------- /book/copyright/chapter.tex: -------------------------------------------------------------------------------- 1 | \thispagestyle{plain} 2 | 3 | Copyright \copyright\ 2018, 2019, 2020 John Winans 4 | 5 | This document is made available under a Creative Commons Attribution 4.0 6 | International License. See \autoref{license} for more information. 7 | 8 | Download your own copy of this book from github here: 9 | \url{https://github.com/johnwinans/rvalp}. 10 | 11 | This document may contain inaccuracies or errors. The author provides no 12 | guarantee regarding the accuracy of this document's contents. If you 13 | discover that this document contains errors, please notify the author. 14 | 15 | \enote{Need to say something about trademarks for things mentioned in this 16 | text} 17 | 18 | 19 | ARM\rtm{} is a registered trademark of ARM Limited in the 20 | EU and other countries. 21 | 22 | IBM\rtm{} is a trademarks or registered trademark of International Business Machines 23 | Corporation in the United States, other countries, or both. 24 | 25 | Intel\rtm{} and Pentium\rtm{} are trademarks of Intel Corporation or its subsidiaries 26 | in the U.S. and/or other countries. 27 | -------------------------------------------------------------------------------- /book/programs/src/ebreak/ebreak.out: -------------------------------------------------------------------------------- 1 | $ rvddt -f ebreak.bin 2 | sp initialized to top of memory: 0x0000fff0 3 | Loading 'ebreak.bin' to 0x0 4 | This is rvddt. Enter ? for help. 5 | ddt> d 0 16 6 | 00000000: 73 00 10 00 a5 a5 a5 a5 a5 a5 a5 a5 a5 a5 a5 a5 *s...............* 7 | ddt> r 8 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 9 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 10 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 11 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 12 | pc 00000000 13 | ddt> ti 0 1000 14 | 00000000: ebreak 15 | ddt> ti 16 | 00000000: ebreak 17 | ddt> g 0 18 | 00000000: ebreak 19 | ddt> r 20 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 21 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 22 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 23 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 24 | pc 00000000 25 | ddt> x 26 | -------------------------------------------------------------------------------- /book/rv32/insn/lui.tex: -------------------------------------------------------------------------------- 1 | \DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111} 2 | 3 | \begin{verbatim} 4 | 00010074: 000032b7 lui x5, 0x3 // x5 = 0x3000 5 | reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0 6 | reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 7 | reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 8 | reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 9 | pc: 00010078 10 | \end{verbatim} 11 | 12 | \DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111} 13 | 14 | \begin{verbatim} 15 | 00010078: fffff2b7 lui x5, 0xfffff // x5 = 0xfffff000 16 | reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0 17 | reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 18 | reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 19 | reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 20 | pc: 0001007c 21 | \end{verbatim} 22 | -------------------------------------------------------------------------------- /book/programs/src/Make.rules: -------------------------------------------------------------------------------- 1 | 2 | ARCH=riscv32-unknown-elf 3 | 4 | CC=$(ARCH)-gcc 5 | AS=$(ARCH)-as 6 | LD=$(ARCH)-ld 7 | OBJCOPY=$(ARCH)-objcopy 8 | OBJDUMP=$(ARCH)-objdump 9 | SIZE=$(ARCH)-size 10 | 11 | #LDFLAGS+=-nostdlib -Wl,-Ttext=0x0,-Tdata=0x8000 12 | LDFLAGS+=-nostdlib -Wl,-Ttext=0x0 13 | 14 | CFLAGS+=-ffreestanding -fno-pic 15 | CFLAGS+=-march=rv32i -mabi=ilp32 16 | CFLAGS+=-Wl,--no-relax # see: https://github.com/riscv/riscv-gcc/issues/120 17 | 18 | ASFLAGS+=$(CFLAGS) 19 | 20 | CLEAN_DIRS=$(SUBDIRS:%=clean-%) 21 | ALL_DIRS=$(SUBDIRS:%=all-%) 22 | 23 | .PHONY: all clean world $(CLEAN_DIRS) $(ALL_DIRS) 24 | 25 | 26 | %.bin : % 27 | $(OBJCOPY) $< -O binary $@ 28 | 29 | %.lst : % 30 | $(OBJDUMP) -dr $< | grep -v '^$$' > $<.lst 31 | 32 | % : %.o 33 | $(LINK.c) $(LDFLAGS) -o $@ $^ $(LDLIBS) 34 | $(SIZE) -x -A $@ 35 | 36 | %.s: %.c 37 | $(COMPILE.c) -S -o $@ $< 38 | 39 | %.srec: % 40 | $(OBJCOPY) $< -O srec $@ 41 | 42 | 43 | 44 | 45 | all:: $(ALL_DIRS) 46 | 47 | clean:: $(CLEAN_DIRS) 48 | 49 | $(ALL_DIRS):: 50 | $(MAKE) -C $(@:all-%=%) all 51 | 52 | $(CLEAN_DIRS):: 53 | $(MAKE) -C $(@:clean-%=%) clean 54 | 55 | world:: clean all 56 | -------------------------------------------------------------------------------- /book/programs/src/nop/nop.out: -------------------------------------------------------------------------------- 1 | $ rvddt -f nop.bin 2 | sp initialized to top of memory: 0x0000fff0 3 | Loading 'nop.bin' to 0x0 4 | This is rvddt. Enter ? for help. 5 | ddt> d 0 16 6 | 00000000: 13 00 00 00 13 00 00 00 73 00 10 00 a5 a5 a5 a5 *........s.......* 7 | ddt> r 8 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 9 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 10 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 11 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 12 | pc 00000000 13 | ddt> ti 0 1000 14 | 00000000: 00000013 addi x0, x0, 0 # x0 = 0x00000000 = 0x00000000 + 0x00000000 15 | 00000004: 00000013 addi x0, x0, 0 # x0 = 0x00000000 = 0x00000000 + 0x00000000 16 | 00000008: ebreak 17 | ddt> r 18 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 19 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 20 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 21 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 22 | pc 00000008 23 | ddt> x 24 | -------------------------------------------------------------------------------- /book/float/erroraccumulation.out: -------------------------------------------------------------------------------- 1 | 0.1000000015 = 3dcccccd -0.1000000015 = bdcccccd 2 | 0.2000000030 = 3e4ccccd -0.2000000030 = be4ccccd 3 | 0.3000000119 = 3e99999a -0.3000000119 = be99999a 4 | 0.4000000060 = 3ecccccd -0.4000000060 = becccccd 5 | 0.5000000000 = 3f000000 -0.5000000000 = bf000000 6 | 0.6000000238 = 3f19999a -0.6000000238 = bf19999a 7 | 0.7000000477 = 3f333334 -0.7000000477 = bf333334 8 | 0.8000000715 = 3f4cccce -0.8000000715 = bf4cccce 9 | 0.9000000954 = 3f666668 -0.9000000954 = bf666668 10 | 1.0000001192 = 3f800001 -1.0000001192 = bf800001 11 | 1.1000001431 = 3f8cccce -1.1000001431 = bf8cccce 12 | 1.2000001669 = 3f99999b -1.2000001669 = bf99999b 13 | 1.3000001907 = 3fa66668 -1.3000001907 = bfa66668 14 | 1.4000002146 = 3fb33335 -1.4000002146 = bfb33335 15 | 1.5000002384 = 3fc00002 -1.5000002384 = bfc00002 16 | 1.6000002623 = 3fcccccf -1.6000002623 = bfcccccf 17 | 1.7000002861 = 3fd9999c -1.7000002861 = bfd9999c 18 | 1.8000003099 = 3fe66669 -1.8000003099 = bfe66669 19 | 1.9000003338 = 3ff33336 -1.9000003338 = bff33336 20 | -------------------------------------------------------------------------------- /book/toolchain/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Using The RISC-V GNU Toolchain} 2 | 3 | This chapter discusses using the GNU toolchain elements to 4 | experiment with the material in this book. 5 | 6 | See \autoref{chapter:install} if you do not already have the 7 | GNU crosscompiler toolchain available on your system. 8 | 9 | 10 | Discuss the choice of ilp32 as well as what the other variations would do. 11 | 12 | Discuss rv32im and note that the details are found in \autoref{chapter:RV32}. 13 | 14 | Discuss installing and using one of the RISC-V simulators 15 | here. 16 | 17 | Describe the pre-processor, compiler, assembler and linker. 18 | 19 | Source, object, and binary files 20 | 21 | Assembly syntax (label: mnemonic op1, op2, op3 \# comment). 22 | 23 | text, data, bss, stack 24 | 25 | Labels and scope. 26 | 27 | Forward \& backward references to throw-away labels. 28 | 29 | The entry address of an application. 30 | 31 | .s file contain assembler code. 32 | .S (or .sx) files contain assembler code that must be preprocessed.~\cite[p.~29]{gcc:2017} 33 | 34 | Pre-processing conditional assembly using \#if. 35 | 36 | Building with \verb@-mabi=ilp32 -march=rv32i -mno-fdiv -mno-div@ to match 37 | the config options on the toolchain. 38 | 39 | Linker scripts. 40 | 41 | Makefiles 42 | 43 | objdump 44 | 45 | nm 46 | 47 | hexdump -C 48 | -------------------------------------------------------------------------------- /book/binary/rvddt_memdump.out: -------------------------------------------------------------------------------- 1 | ddt> d 0x00002600 2 | 00002600: 93 05 00 00 13 06 00 00 93 06 00 00 13 07 00 00 *................* 3 | 00002610: 93 07 00 00 93 08 d0 05 73 00 00 00 63 54 05 02 *........s...cT..* 4 | 00002620: 13 01 01 ff 23 24 81 00 13 04 05 00 23 26 11 00 *....#$......#&..* 5 | 00002630: 33 04 80 40 97 00 00 00 e7 80 40 01 23 20 85 00 *3..@......@.# ..* 6 | 00002640: 6f 00 00 00 6f 00 00 00 b7 87 00 00 03 a5 07 43 *o...o..........C* 7 | 00002650: 67 80 00 00 00 00 00 00 76 61 6c 3d 00 00 00 00 *g.......val=....* 8 | 00002660: 00 00 00 00 80 84 2e 41 1f 85 45 41 80 40 9a 44 *.......A..EA.@.D* 9 | 00002670: 4f 11 f3 c3 6e 8a 67 41 20 1b 00 00 20 1b 00 00 *O...n.gA ... ...* 10 | 00002680: 44 1b 00 00 14 1b 00 00 14 1b 00 00 04 1c 00 00 *D...............* 11 | 00002690: 44 1b 00 00 14 1b 00 00 04 1c 00 00 14 1b 00 00 *D...............* 12 | 000026a0: 44 1b 00 00 10 1b 00 00 10 1b 00 00 10 1b 00 00 *D...............* 13 | 000026b0: 04 1c 00 00 54 1f 00 00 54 1f 00 00 d4 1f 00 00 *....T...T.......* 14 | 000026c0: 4c 1f 00 00 4c 1f 00 00 34 20 00 00 d4 1f 00 00 *L...L...4 ......* 15 | 000026d0: 4c 1f 00 00 34 20 00 00 4c 1f 00 00 d4 1f 00 00 *L...4 ..L.......* 16 | 000026e0: 48 1f 00 00 48 1f 00 00 48 1f 00 00 34 20 00 00 *H...H...H...4 ..* 17 | 000026f0: 00 01 02 02 03 03 03 03 04 04 04 04 04 04 04 04 *................* 18 | -------------------------------------------------------------------------------- /book/float/errorcompensation.out: -------------------------------------------------------------------------------- 1 | 0.1000000015 = 3dcccccd -0.1000000015 = bdcccccd 2 | 0.2000000030 = 3e4ccccd -0.2000000030 = be4ccccd 3 | 0.3000000119 = 3e99999a -0.3000000119 = be99999a 4 | 0.4000000060 = 3ecccccd -0.4000000060 = becccccd 5 | 0.5000000000 = 3f000000 -0.5000000000 = bf000000 6 | 0.6000000238 = 3f19999a -0.6000000238 = bf19999a 7 | 0.6999999881 = 3f333333 -0.6999999881 = bf333333 8 | 0.8000000119 = 3f4ccccd -0.8000000119 = bf4ccccd 9 | 0.8999999762 = 3f666666 -0.8999999762 = bf666666 10 | 1.0000000000 = 3f800000 -1.0000000000 = bf800000 11 | 1.1000000238 = 3f8ccccd -1.1000000238 = bf8ccccd 12 | 1.2000000477 = 3f99999a -1.2000000477 = bf99999a 13 | 1.2999999523 = 3fa66666 -1.2999999523 = bfa66666 14 | 1.3999999762 = 3fb33333 -1.3999999762 = bfb33333 15 | 1.5000000000 = 3fc00000 -1.5000000000 = bfc00000 16 | 1.6000000238 = 3fcccccd -1.6000000238 = bfcccccd 17 | 1.7000000477 = 3fd9999a -1.7000000477 = bfd9999a 18 | 1.7999999523 = 3fe66666 -1.7999999523 = bfe66666 19 | 1.8999999762 = 3ff33333 -1.8999999762 = bff33333 20 | 2.0000000000 = 40000000 -2.0000000000 = c0000000 21 | -------------------------------------------------------------------------------- /book/programs/src/mv/mv.out: -------------------------------------------------------------------------------- 1 | $ rvddt -f mv.bin 2 | sp initialized to top of memory: 0x0000fff0 3 | Loading 'mv.bin' to 0x0 4 | This is rvddt. Enter ? for help. 5 | ddt> d 0 16 6 | 00000000: 13 8e 0e 00 13 8e 0e 00 73 00 10 00 a5 a5 a5 a5 *........s.......* 7 | ddt> t 0 1000 8 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 9 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 10 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 11 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 12 | pc 00000000 13 | 00000000: 000e8e13 addi x28, x29, 0 # x28 = 0xf0f0f0f0 = 0xf0f0f0f0 + 0x00000000 14 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 15 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 16 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 17 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 18 | pc 00000004 19 | 00000004: 000e8e13 addi x28, x29, 0 # x28 = 0xf0f0f0f0 = 0xf0f0f0f0 + 0x00000000 20 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 21 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 22 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 23 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 24 | pc 00000008 25 | 00000008: ebreak 26 | ddt> x 27 | -------------------------------------------------------------------------------- /texlib/ENote.sty: -------------------------------------------------------------------------------- 1 | \NeedsTeXFormat{LaTeX2e} 2 | \ProvidesPackage{ENote} 3 | [2002/03/23 v1 4 | John Winans's editor notes facilities% 5 | ] 6 | % 7 | % A simple way to provide book-editor notes that can be 8 | % automatically turned off. 9 | % 10 | %\newcommand{\enote}[1]{\marginpar{\raggedright\small\sffamily \ding{209} Note: \vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} 11 | %\newcommand{\enote}[1]{\mbox{}\marginpar{\raggedright\small\sffamily Editor's Note: \vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} 12 | \newcommand{\enote}[1]{\mbox{}\marginpar{\raggedright\small\sffamily \ding{253} Fix Me:\vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} 13 | 14 | \newcommand{\marginwarn}[1]{\mbox{}\marginpar{\raggedright\small\sffamily Warning: \vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} 15 | 16 | \newcommand{\margingood}[1]{\mbox{}\marginpar{\raggedright\small\sffamily Handy Tip: \vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} 17 | 18 | \newcommand{\marginnote}[1]{\mbox{}\marginpar{\raggedright\small\sffamily Note: \vskip 3pt \hrule \vskip 1pt \scriptsize\slshape #1 \vskip 1pt \hrule}} 19 | 20 | \newcommand\markbad{\ding{209} } 21 | \newcommand\markgood{\ding{253} } 22 | 23 | \newcommand\dmarginwarn[1]{\mbox{}\marginpar{\fbox{\parbox{\marginparwidth}{\raggedright\markbad #1}}}} 24 | \newcommand\dmargingood[1]{\mbox{}\marginpar{\fbox{\parbox{\marginparwidth}{\raggedright\markgood #1}}}} 25 | 26 | \endinput 27 | -------------------------------------------------------------------------------- /texlib/MyFigs.sty: -------------------------------------------------------------------------------- 1 | \NeedsTeXFormat{LaTeX2e} 2 | \ProvidesPackage{MyFigs} 3 | [2002/03/23 v1 4 | John Winans's graphic figure includer facilities% 5 | ] 6 | % 7 | % #1 = file name 8 | % #2 = caption 9 | % #3 = label 10 | % 11 | \newenvironment{EpsFig}[3]{% 12 | \begin{figure} \begin{center} \includegraphics[]{#1} \end{center} \caption{#2} \label{#3}}% 13 | {\end{figure}} 14 | \newenvironment{EpsFig1}[3]{% 15 | \begin{figure} \includegraphics[width=\textwidth]{#1} \caption{#2} \label{#3}}% 16 | {\end{figure}} 17 | 18 | \newenvironment{EpsFig2}[3]{% 19 | \begin{figure} \includegraphics[width=\fullwidth]{#1} \caption{#2} \label{#3}}% 20 | {\end{figure}} 21 | 22 | \newenvironment{EpsFigRot}[3]{% 23 | \begin{sidewaysfigure}\epsfig{height=\MySidewaysFigWidth,file=#1} \caption{#2} \label{#3}}% 24 | {\end{sidewaysfigure}} 25 | 26 | 27 | % #1 = file name 28 | % #2 = caption 29 | % #3 = includegraphics parms 30 | \newcommand{\GraphicFigFloating}[3]{% 31 | \begin{figure} \begin{center} \includegraphics[#3]{#1} \end{center} \caption{#2} \label{detokenize{Graphic:#2}}% 32 | \end{figure}} 33 | 34 | \newcommand{\GraphicFig}[3]{% 35 | \begin{minipage}{\textwidth} \begin{center} \includegraphics[#3]{#1} \captionof{figure}{#2}\label{detokenize{Graphic:#1}} \end{center} \end{minipage}% 36 | } 37 | 38 | \newcommand{\xGraphicFig}[3]{% 39 | \begin{center} \includegraphics[#3]{#1} \captionof{figure}{#2}\label{detokenize{Graphic:#1}} \end{center} % 40 | } 41 | 42 | \newcommand{\GraphicFigRef}[1]{% 43 | \autoref{detokenize{Graphic:#1}}% 44 | } 45 | 46 | 47 | \endinput 48 | -------------------------------------------------------------------------------- /book/programs/src/mvzero/mv.out: -------------------------------------------------------------------------------- 1 | $ rvddt -f mv.bin 2 | sp initialized to top of memory: 0x0000fff0 3 | Loading 'mv.bin' to 0x0 4 | This is rvddt. Enter ? for help. 5 | ddt> a 6 | ddt> d 0 16 7 | 00000000: 13 0e 00 00 73 00 10 00 a5 a5 a5 a5 a5 a5 a5 a5 *....s...........* 8 | ddt> t 0 1000 9 | zero x0 00000000 ra x1 f0f0f0f0 sp x2 0000fff0 gp x3 f0f0f0f0 10 | tp x4 f0f0f0f0 t0 x5 f0f0f0f0 t1 x6 f0f0f0f0 t2 x7 f0f0f0f0 11 | s0 x8 f0f0f0f0 s1 x9 f0f0f0f0 a0 x10 f0f0f0f0 a1 x11 f0f0f0f0 12 | a2 x12 f0f0f0f0 a3 x13 f0f0f0f0 a4 x14 f0f0f0f0 a5 x15 f0f0f0f0 13 | a6 x16 f0f0f0f0 a7 x17 f0f0f0f0 s2 x18 f0f0f0f0 s3 x19 f0f0f0f0 14 | s4 x20 f0f0f0f0 s5 x21 f0f0f0f0 s6 x22 f0f0f0f0 s7 x23 f0f0f0f0 15 | s8 x24 f0f0f0f0 s9 x25 f0f0f0f0 s10 x26 f0f0f0f0 s11 x27 f0f0f0f0 16 | t3 x28 f0f0f0f0 t4 x29 f0f0f0f0 t5 x30 f0f0f0f0 t6 x31 f0f0f0f0 17 | pc 00000000 18 | 00000000: 00000e13 addi t3, zero, 0 # t3 = 0x00000000 = 0x00000000 + 0x00000000 19 | zero x0 00000000 ra x1 f0f0f0f0 sp x2 0000fff0 gp x3 f0f0f0f0 20 | tp x4 f0f0f0f0 t0 x5 f0f0f0f0 t1 x6 f0f0f0f0 t2 x7 f0f0f0f0 21 | s0 x8 f0f0f0f0 s1 x9 f0f0f0f0 a0 x10 f0f0f0f0 a1 x11 f0f0f0f0 22 | a2 x12 f0f0f0f0 a3 x13 f0f0f0f0 a4 x14 f0f0f0f0 a5 x15 f0f0f0f0 23 | a6 x16 f0f0f0f0 a7 x17 f0f0f0f0 s2 x18 f0f0f0f0 s3 x19 f0f0f0f0 24 | s4 x20 f0f0f0f0 s5 x21 f0f0f0f0 s6 x22 f0f0f0f0 s7 x23 f0f0f0f0 25 | s8 x24 f0f0f0f0 s9 x25 f0f0f0f0 s10 x26 f0f0f0f0 s11 x27 f0f0f0f0 26 | t3 x28 00000000 t4 x29 f0f0f0f0 t5 x30 f0f0f0f0 t6 x31 f0f0f0f0 27 | pc 00000004 28 | 00000004: ebreak 29 | ddt> x 30 | -------------------------------------------------------------------------------- /Make.rules: -------------------------------------------------------------------------------- 1 | TEXLIB=$(TOP)/texlib 2 | 3 | # BEFORE including this file, you must define: TEXPATH 4 | 5 | 6 | # This only works if there is at least one tag in the git repo 7 | #GIT_SHOW_FORMAT=%ae %ci 8 | GIT_SHOW_FORMAT=%ci 9 | LATEXFLAGS="\newcommand\GitFileName{"`pwd | sed -e 's|^.*rvalp/|\\\textasciitilde/rvalp/|'`/"}\newcommand\GitDescription{"`git describe --long --dirty; git show -s --format='$(GIT_SHOW_FORMAT)';`"}\newcommand\GitRevision{"`git describe --long --dirty`"}\input{$<}" 10 | 11 | LATEX_CLEANFILES = *.aux *.log *.dvi *.toc *.lof *.bbl *.blg *.ind *.ilg *.idx *.glo *.glg *.gls *.glsdefs *.out *.ist *.brf 12 | 13 | .SUFFIXES: .tex .pdf .eps .fig .dot .png 14 | 15 | .tex.pdf: 16 | ( export TEXINPUTS=$(TEXPATH):$(TEXLIB)::; \ 17 | BIBINPUTS=${TEXINPUTS}; export BIBINPUTS; \ 18 | pdflatex $(LATEXFLAGS) $<; \ 19 | cp $@ out-$@; \ 20 | bibtex ${<:.tex=}; \ 21 | makeindex -s $(TEXLIB)/index.ist ${<:.tex=}; \ 22 | pdflatex $(LATEXFLAGS) $<; \ 23 | cp $@ out-$@; \ 24 | pdflatex $(LATEXFLAGS) $<;\ 25 | cp $@ out-$@; ) 26 | 27 | #makeglossaries ${<:.tex=}; \ 28 | 29 | .fig.eps: 30 | fig2dev -L eps $< > $@ 31 | 32 | .fig.pdf: 33 | fig2dev -L pdftex $< > $@ 34 | 35 | 36 | # Rules for converting dot files into png files 37 | .dot.png: 38 | dot -Tpng -o $@ $< 39 | 40 | .dot.pdf: 41 | dot -Tpdf -o $@ $< 42 | 43 | 44 | 45 | # Rules for walking a tree of Makefiles 46 | # Add a prefix to each directory name to make unique versions for all, clean,... 47 | CLEAN_DIRS=$(SUBDIRS:%=clean-%) 48 | ALL_DIRS=$(SUBDIRS:%=all-%) 49 | 50 | .PHONY: all clean world doc $(CLEAN_DIRS) $(ALL_DIRS) 51 | 52 | all:: $(ALL_DIRS) 53 | 54 | clean:: $(CLEAN_DIRS) 55 | 56 | # for each dir, do a make all 57 | $(ALL_DIRS):: 58 | $(MAKE) -C $(@:all-%=%) all 59 | 60 | # for each dir, do a make clean 61 | $(CLEAN_DIRS):: 62 | $(MAKE) -C $(@:clean-%=%) clean 63 | 64 | world:: clean all 65 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # rvalp 2 | 3 | RISC-V Assembly Language Programming 4 | 5 | This is an attempt to create a book on RISC-V programming in assembly language. 6 | 7 | See the Releases page for pre-made PDF versions: https://github.com/johnwinans/rvalp/releases 8 | 9 | Pull requests are welcome. 10 | 11 | I will release PDFs after useful improvements from time to time into the releases area for those 12 | that don't wish to build their own. 13 | 14 | You can find the rvddt simulator mentioned in the text here: https://github.com/johnwinans/rvddt 15 | 16 | I developed this using LaTeX via texlive. LaTeX is very portable. You should 17 | be able to tinker with it on most any platform. 18 | 19 | On Ubuntu 20.04 and 18.04 LTS, loading the following packages worked for me: 20 | 21 | sudo apt install make 22 | sudo apt install git 23 | sudo apt install texlive-latex-extra 24 | 25 | I suspect the same (above) would work on 16.04 as well. 26 | 27 | Then clone and build this repo: 28 | 29 | git clone https://github.com/johnwinans/rvalp.git 30 | cd rvalp 31 | make world 32 | 33 | # Related Projects 34 | 35 | The RISC-V simulator that I use to generate figures: https://github.com/johnwinans/rvddt 36 | 37 | A RISC-V simulator with more advanced features (but is also more complicated): https://github.com/johnwinans/riscv-toolchain-install-guide 38 | 39 | The toolchain used to assemble and compile programs in this book: https://github.com/riscv/riscv-gnu-toolchain 40 | 41 | 42 | See Appendix A of rvalp for the precise details on how I downloaded and build each of these tools on Linux. 43 | 44 | Note: During the great on-line COVID school year I recorded some lectures 45 | on RISC-V that use this book as a reference. 46 | These lectures appear in the following YouTube playlists: 47 | 48 | * [RISC-V Lectures From NIU CSCI 463](https://www.youtube.com/playlist?list=PL3by7evD3F53Dz2RiB47Ztp9l_piGVuus) 49 | * [The Whole NIU CSCI 463 Spring 2021 Playlist](https://www.youtube.com/playlist?list=PL3by7evD3F50NMukhaMqNdOt4pUHXT2Vo) 50 | -------------------------------------------------------------------------------- /book/elements/zero4regs.out: -------------------------------------------------------------------------------- 1 | [winans@w510 src]$ ./rvddt -f ../examples/load4regs.bin 2 | Loading '../examples/load4regs.bin' to 0x0 3 | ddt> t4 4 | x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 5 | x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 6 | x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 7 | x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 8 | pc: 00000000 9 | 00000000: 00000e13 addi x28, x0, 0 # x28 = 0x00000000 = 0x00000000 + 0x00000000 10 | x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 11 | x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 12 | x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 13 | x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 14 | pc: 00000004 15 | 00000004: 00000e93 addi x29, x0, 0 # x29 = 0x00000000 = 0x00000000 + 0x00000000 16 | x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 17 | x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 18 | x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 19 | x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 00000000 f0f0f0f0 f0f0f0f0 20 | pc: 00000008 21 | 00000008: 00000f13 addi x30, x0, 0 # x30 = 0x00000000 = 0x00000000 + 0x00000000 22 | x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 23 | x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 24 | x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 25 | x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 00000000 00000000 f0f0f0f0 26 | pc: 0000000c 27 | 0000000c: 00000f93 addi x31, x0, 0 # x31 = 0x00000000 = 0x00000000 + 0x00000000 28 | ddt> r 29 | x0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 30 | x8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 31 | x16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 32 | x24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 00000000 00000000 00000000 00000000 33 | pc: 00000010 34 | ddt> x 35 | [winans@w510 src]$ 36 | -------------------------------------------------------------------------------- /book/rv32m/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{RV32M Standard Extension} 2 | \label{chapter:rv32m} 3 | \index{RV32M} 4 | 5 | \section{Introduction} 6 | 7 | 8 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 9 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 10 | 11 | 12 | 32-bit integer multiply and divide instructions. 13 | 14 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 15 | \subsection{MUL rd, rs1, rs2} 16 | \index{Instruction!MUL} 17 | 18 | Multiply \reg{rs1} by \reg{rs2} and store the least significant 32-bits 19 | of the result in \reg{rd}. 20 | 21 | \DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011} 22 | 23 | 24 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 25 | \subsection{MULH rd, rs1, rs2} 26 | \index{Instruction!MULH} 27 | 28 | \DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011} 29 | 30 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 31 | \subsection{MULHS rd, rs1, rs2} 32 | \index{Instruction!MULHS} 33 | 34 | \DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011} 35 | 36 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 37 | \subsection{MULHU rd, rs1, rs2} 38 | \index{Instruction!MULHU} 39 | 40 | \DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011} 41 | 42 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 43 | \subsection{DIV rd, rs1, rs2} 44 | \index{Instruction!DIV} 45 | 46 | \DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011} 47 | 48 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 49 | \subsection{DIVU rd, rs1, rs2} 50 | \index{Instruction!DIVU} 51 | 52 | \DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011} 53 | 54 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 55 | \subsection{REM rd, rs1, rs2} 56 | \index{Instruction!REM} 57 | 58 | \DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011} 59 | 60 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 61 | \subsection{REMU rd, rs1, rs2} 62 | \index{Instruction!REMU} 63 | 64 | \DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011} 65 | -------------------------------------------------------------------------------- /book/preface/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Preface} 2 | \label{chapter:Preface} 3 | 4 | I set out to write this book because I couldn't find it in a single volume elsewhere. 5 | 6 | The closest published work on this topic appear to be select portions of 7 | {\em The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2}\cite{rvismv1v22:2017}, 8 | {The RISC-V Reader}\cite{riscvreader:2017}, and 9 | {Computer Organization and Design RISC-V Edition: The Hardware Software Interface}\cite{codriscv:2017}. 10 | 11 | There {\em are} some terse guides on the Internet that are suitable 12 | for those who already know an assembly language. With all the (deserved) 13 | excitement brewing over system organization (and the need to compress the 14 | time out of university courses targeting assembly language 15 | programming~\cite{Decker:1985:MAT:989369.989375}), 16 | it is no surprise that RISC-V texts for the beginning assembly programmer 17 | are not (yet) available. 18 | 19 | When I started in computing, I learned how to count in binary 20 | in a high school electronics course using data sheets for integrated 21 | circuits such as the 74191\cite{ttl74191:1979} and 74154\cite{ttl74154:1979} 22 | prior to knowing that assembly language even existed. 23 | 24 | I learned assembly language from data sheets and texts, that are still sitting on 25 | my shelves today, such as: 26 | \begin{itemize} 27 | \item The MCS-85 User's Manual\cite{mcs85:1978} 28 | \item The EDTASM Manual\cite{edtasm:1978} 29 | \item The MC68000 User's Manual\cite{mc68000:1980} 30 | \item Assembler Language With ASSIST\cite{assist:1983} 31 | \item IBM System/370 Principals of Operation\cite{poo:1980} 32 | \item OS/VS-DOS/VSE-VM/370 Assembler Language\cite{assembler370:1979} 33 | %\item The Series 32000 Databook\cite{ns32k:1986} 34 | \item \ldots\ and several others 35 | \end{itemize} 36 | 37 | All of these manuals discuss each CPU instruction in excruciating detail 38 | with both a logical and narrative description. For RISC-V this is 39 | also the case for the {\em RISC-V Reader}\cite{riscvreader:2017} and the 40 | {\em Computer Organization and Design RISC-V Edition}\cite{codriscv:2017} books 41 | and is also present in this text (I consider that to be the minimal 42 | level of responsibility.) 43 | 44 | Where I hope this text will differentiate itself from the existing RISC-V 45 | titles is in its attempt to address the needs of those learning assembly 46 | language for the first time. To this end I have primed this project with 47 | some of the curriculum material I created when teaching assembly language 48 | programming in the late '80s. 49 | -------------------------------------------------------------------------------- /book/rvalp.tex: -------------------------------------------------------------------------------- 1 | %\documentclass[oneside,draft,letterpaper]{book} 2 | %\documentclass[letterpaper]{book} 3 | \documentclass[oneside,letterpaper]{book} 4 | 5 | 6 | \input{preamble} 7 | \input{colors} 8 | \input{insnformats} 9 | 10 | \usepackage{ENote} 11 | 12 | %\usepackage{showframe} 13 | 14 | \hypersetup{ 15 | pdfauthor={John Winans}, 16 | pdftitle={RISC-V Assembly Language Programming (Draft \GitRevision{})}, 17 | pdfkeywords={RISC-V} {Assembler} 18 | } 19 | 20 | \makeindex 21 | 22 | %\makeglossaries 23 | \makenoidxglossaries 24 | \include{glossary} 25 | 26 | %\includeonly{refcard/chapter} 27 | 28 | \begin{document} 29 | \include{indexrefs} % The see-references for the index 30 | 31 | % Why does this (apparently) have to go here???? 32 | \newlength{\fullwidth} 33 | \setlength{\fullwidth}{\the\textwidth} 34 | \addtolength{\fullwidth}{\the\marginparsep} 35 | \addtolength{\fullwidth}{\the\marginparwidth} 36 | 37 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 38 | \frontmatter 39 | 40 | \title{RISC-V\\Assembly Language Programming\\{\normalsize (Draft \GitRevision{})}} 41 | \author{John Winans\\ \href{mailto:jwinans@niu.edu}{\sf jwinans@niu.edu}} 42 | %\date{May } 43 | 44 | \maketitle 45 | 46 | \include{copyright/chapter} 47 | \tableofcontents 48 | %\listoffigures 49 | 50 | \setlength{\parskip}{10pt} 51 | 52 | \include{preface/chapter} 53 | \mainmatter 54 | 55 | %\include{preface/chapter} 56 | 57 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 58 | 59 | % there should be one include here for each chapter 60 | 61 | %\part{Introduction} 62 | 63 | \include{intro/chapter} 64 | \include{binary/chapter} 65 | \include{elements/chapter} 66 | \include{programs/chapter} 67 | \include{rv32/chapter} 68 | 69 | %\include{priv/chapter} 70 | %\include{rv32m/chapter} 71 | 72 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 73 | % These 'chapters' are lettered rather than numbered 74 | 75 | \appendix 76 | %\include{insnsummary/chapter} % no longer neded with expanded refcard 77 | \include{install/chapter} 78 | %\include{toolchain/chapter} 79 | \include{float/chapter} 80 | \include{ascii/chapter} 81 | \include{license/chapter} 82 | 83 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 84 | \backmatter 85 | % putting a chapter here causes it to be unnumbered 86 | 87 | \bibliography{bibliography} 88 | \addcontentsline{toc}{chapter}{Bibliography} 89 | \nocite{*} % force all bib items to file appear even if not cited 90 | %\bibliographystyle{alpha} 91 | \bibliographystyle{ieeetr} 92 | 93 | %\phantomsection 94 | \glsaddall 95 | \printnoidxglossaries 96 | %\printglossary 97 | 98 | 99 | \phantomsection 100 | \addcontentsline{toc}{chapter}{\indexname} 101 | \printindex 102 | 103 | \include{refcard/chapter} 104 | 105 | \end{document} 106 | -------------------------------------------------------------------------------- /texlib/MyVerbatim.sty: -------------------------------------------------------------------------------- 1 | \NeedsTeXFormat{LaTeX2e} 2 | \ProvidesPackage{MyVerbatim} 3 | [2002/03/23 v1 4 | John Winans's verbatim facilities% 5 | ] 6 | \newlength{\bvwidth} 7 | \setlength{\bvwidth}{\textwidth} 8 | %\addtolength{\bvwidth}{\marginparsep} 9 | %\addtolength{\bvwidth}{\marginparwidth} 10 | %\addtolength{\bvwidth}{-7pt} 11 | \addtolength{\bvwidth}{-1pt} 12 | 13 | % A low quality boxed verbatim environment 14 | %\newenvironment{boxedverbatim}% 15 | % {\VerbatimEnvironment \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% 16 | % {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{1mm}\noindent\fbox{\TheSbox}} 17 | 18 | % A figure-generating boxed verbatim environment 19 | % 20 | % #1: Filename 21 | % #2: Caption 22 | % #3: Label 23 | \newcommand\VFTitle{X} 24 | \newcommand\VFCaption{X} 25 | \newcommand\VFLabel{X} 26 | 27 | % \begin{Code}{The Title} 28 | % xxx 29 | % \end{Code} 30 | \newenvironment{Code}[1]{% 31 | \renewcommand\VFTitle{#1}% 32 | \VerbatimEnvironment% 33 | \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% 34 | {\end{Verbatim}\end{minipage}\end{Sbox} \bigskip\noindent\setlength{\fboxsep}{.5mm}\framebox[\bvwidth][l]{\textsf{\small\bfseries\VFTitle}}\\ 35 | \framebox[\bvwidth][l]{\TheSbox}\bigskip} 36 | 37 | % This only exists so that we can show a Code environment within one 38 | \newenvironment{CodeAlt}[1]{% 39 | \renewcommand\VFTitle{#1}% 40 | \VerbatimEnvironment% 41 | \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% 42 | {\end{Verbatim}\end{minipage}\end{Sbox} \bigskip\noindent\setlength{\fboxsep}{.5mm}\framebox[\bvwidth][l]{\textsf{\small\bfseries\VFTitle}}\\ 43 | \framebox[\bvwidth][l]{\TheSbox}\bigskip} 44 | 45 | \newenvironment{CodeFig}[3]{% 46 | \renewcommand\VFTitle{#1}% 47 | \renewcommand\VFCaption{#2}% 48 | \renewcommand\VFLabel{#3}% 49 | \VerbatimEnvironment% 50 | \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% 51 | {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{.5mm}\begin{figure}[ht]\framebox[\bvwidth][l]{\textsf{\small\bfseries\VFTitle}}\\ 52 | \framebox[\bvwidth][l]{\TheSbox}\caption{\VFCaption}\label{\VFLabel}\end{figure}} 53 | 54 | % This only exists so that we can show a CodeFig environment within one 55 | \newenvironment{CodeFigAlt}[3]{% 56 | \renewcommand\VFTitle{#1}% 57 | \renewcommand\VFCaption{#2}% 58 | \renewcommand\VFLabel{#3}% 59 | \VerbatimEnvironment% 60 | \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% 61 | {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{.5mm}\begin{figure}[ht]\framebox[\bvwidth][l]{\textsf{\small\bfseries\VFTitle}}\\ 62 | \framebox[\bvwidth][l]{\TheSbox}\caption{\VFCaption}\label{\VFLabel}\end{figure}} 63 | 64 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 65 | \newenvironment{CodeFigB}[2]{% 66 | \renewcommand\VFCaption{#1}% 67 | \renewcommand\VFLabel{#2}% 68 | \VerbatimEnvironment% 69 | \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% 70 | {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{.5mm}\begin{figure}[ht]\framebox[\bvwidth][l]{\TheSbox}\caption{\VFCaption}\label{\VFLabel}\end{figure}} 71 | 72 | \newenvironment{CodeFigBAlt}[2]{% 73 | \renewcommand\VFCaption{#1}% 74 | \renewcommand\VFLabel{#2}% 75 | \VerbatimEnvironment% 76 | \begin{Sbox}\begin{minipage}{\bvwidth}\footnotesize\begin{Verbatim}}% 77 | {\end{Verbatim}\end{minipage}\end{Sbox} \setlength{\fboxsep}{.5mm}\begin{figure}[ht]\framebox[\bvwidth][l]{\TheSbox}\caption{\VFCaption}\label{\VFLabel}\end{figure}} 78 | 79 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 80 | % 81 | % Define verbatim things each with their own type. 82 | % 83 | 84 | \newcommand\email{\begingroup \urlstyle{sf}\Url} 85 | \newcommand\filename{\begingroup \urlstyle{sf}\Url} 86 | \newcommand\code{\begingroup \urlstyle{tt}\Url} 87 | 88 | \endinput 89 | -------------------------------------------------------------------------------- /book/programs/src/li/li.out: -------------------------------------------------------------------------------- 1 | $ rvddt -f li.bin 2 | sp initialized to top of memory: 0x0000fff0 3 | Loading 'li.bin' to 0x0 4 | This is rvddt. Enter ? for help. 5 | ddt> d 0 16 6 | 00000000: b7 52 34 12 93 82 82 67 37 23 11 11 13 03 f3 ff *.R4....g7#......* 7 | ddt> t 0 1000 8 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 9 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 10 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 11 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 12 | pc 00000000 13 | 00000000: 123452b7 lui x5, 0x12345 # x5 = 0x12345000 14 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 12345000 f0f0f0f0 f0f0f0f0 15 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 16 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 17 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 18 | pc 00000004 19 | 00000004: 67828293 addi x5, x5, 1656 # x5 = 0x12345678 = 0x12345000 + 0x00000678 20 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 12345678 f0f0f0f0 f0f0f0f0 21 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 22 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 23 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 24 | pc 00000008 25 | 00000008: 11112337 lui x6, 0x11112 # x6 = 0x11112000 26 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 12345678 11112000 f0f0f0f0 27 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 28 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 29 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 30 | pc 0000000c 31 | 0000000c: fff30313 addi x6, x6, -1 # x6 = 0x11111fff = 0x11112000 + 0xffffffff 32 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 12345678 11111fff f0f0f0f0 33 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 34 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 35 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 36 | pc 00000010 37 | 00000010: 00000313 addi x6, x0, 0 # x6 = 0x00000000 = 0x00000000 + 0x00000000 38 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 12345678 00000000 f0f0f0f0 39 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 40 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 41 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 42 | pc 00000014 43 | 00000014: fff00313 addi x6, x0, -1 # x6 = 0xffffffff = 0x00000000 + 0xffffffff 44 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 12345678 ffffffff f0f0f0f0 45 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 46 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 47 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 48 | pc 00000018 49 | 00000018: 00100313 addi x6, x0, 1 # x6 = 0x00000001 = 0x00000000 + 0x00000001 50 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 12345678 00000001 f0f0f0f0 51 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 52 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 53 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 54 | pc 0000001c 55 | 0000001c: f1f1f337 lui x6, 0xf1f1f # x6 = 0xf1f1f000 56 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 12345678 f1f1f000 f0f0f0f0 57 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 58 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 59 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 60 | pc 00000020 61 | 00000020: 1f130313 addi x6, x6, 497 # x6 = 0xf1f1f1f1 = 0xf1f1f000 + 0x000001f1 62 | x0 00000000 f0f0f0f0 0000fff0 f0f0f0f0 f0f0f0f0 12345678 f1f1f1f1 f0f0f0f0 63 | x8 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 64 | x16 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 65 | x24 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 66 | pc 00000024 67 | 00000024: ebreak 68 | ddt> x 69 | -------------------------------------------------------------------------------- /book/bibliography.bib: -------------------------------------------------------------------------------- 1 | @string{IETF="Internet Engineering Task Force"} 2 | 3 | @manual{rvismv1v22:2017, 4 | title = "\href{https://github.com/riscv/riscv-isa-manual}{The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2}", 5 | organization = "\href{https://riscv.org/}{RISC-V Foundation}", 6 | year = 2017, 7 | month = 5, 8 | note = {Editors Andrew Waterman and Krste Asanovi\'c} 9 | } 10 | 11 | @manual{rvismv2:2017, 12 | title = "\href{https://github.com/riscv/riscv-isa-manual}{The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 1.10}", 13 | organization = "\href{https://riscv.org/}{RISC-V Foundation}", 14 | year = 2017, 15 | month = 5, 16 | note = {Editors Andrew Waterman and Krste Asanovi\'c} 17 | } 18 | 19 | 20 | @manual{rvpsabi:2017, 21 | title = "\href{https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md}{RISC-V ELF psABI specification}", 22 | author = {Palmer Dabbelt and Stefan O'Rear and Kito Cheng and Andrew Waterman and Michael Clark and Alex Bradbury and David Horner and Max Nordlund and Karsten Merker}, 23 | year = 2017 24 | 25 | } 26 | 27 | 28 | @book{riscvreader:2017, 29 | title = {The RISC-V Reader: An Open Architecture Atlas}, 30 | author = {David Patterson and Andrew Waterman}, 31 | publisher = {Strawberry Canyon}, 32 | month = 11, 33 | year = 2017, 34 | note = {ISBN: 978-0999249116} 35 | } 36 | 37 | @book{codriscv:2017, 38 | title = {Computer Organization and Design RISC-V Edition: The Hardware Software Interface}, 39 | author = {David Patterson and John Hennessy}, 40 | publisher = {Morgan Kaufmann}, 41 | month = 4, 42 | year = 2017, 43 | note = {ISBN: 978-0128122754} 44 | 45 | 46 | @book{gcc:2017, 47 | title = "\href{https://gcc.gnu.org/onlinedocs/}{Using the GNU Compiler Collection (For GCC version 7.3.0)}", 48 | author = {Richard M. Stallman and the GCC Developer Community}, 49 | publisher = {GNU Press}, 50 | address = {Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA}, 51 | year = 2017 52 | } 53 | 54 | 55 | @article{Decker:1985:MAT:989369.989375, 56 | author = {Decker, William F.}, 57 | title = {A Modern Approach to Teaching Computer Organization and Assembly Language Programming}, 58 | journal = {SIGCSE Bull.}, 59 | issue_date = {December 1985}, 60 | volume = {17}, 61 | number = {4}, 62 | month = 12, 63 | year = {1985}, 64 | issn = {0097-8418}, 65 | pages = {38--44}, 66 | numpages = {7}, 67 | url = {http://doi.acm.org/10.1145/989369.989375}, 68 | doi = {10.1145/989369.989375}, 69 | acmid = {989375}, 70 | publisher = {ACM}, 71 | address = {New York, NY, USA} 72 | } 73 | 74 | 75 | @manual{mcs85:1978, 76 | title = {MCS-85 User's Manual}, 77 | organization = {Intel}, 78 | month = 9, 79 | year = 1978 80 | } 81 | 82 | @manual{edtasm:1978, 83 | title = {TRS-80 Editor/Assembler Operation and Reference Manual}, 84 | organization = {Radio Shack}, 85 | year = 1978 86 | } 87 | 88 | @manual{mc68000:1980, 89 | title = {MC68000 16--bit Microprocessor User's Manual}, 90 | edition = {2nd}, 91 | organization = {Motorola}, 92 | month = 1, 93 | year = 1980, 94 | note = {MC68000UM(AD2)} 95 | } 96 | @manual{ns32k:1986, 97 | title = {Series 32000 Databook}, 98 | organization = {National Semiconductor Coprporation}, 99 | year = 1986 100 | } 101 | 102 | @book{assist:1983, 103 | title = {Assembler Language With ASSIST}, 104 | author = {Ross A. Overbeek and W. E. Singletary}, 105 | edition = {2nd}, 106 | publisher = {Science Research Associates, Inc.}, 107 | year = 1983 108 | } 109 | 110 | @manual{poo:1980, 111 | title = {IBM System/370 Principals of Operation}, 112 | edition = {7th}, 113 | organization = {IBM}, 114 | month = 3, 115 | year = 1980 116 | } 117 | 118 | @manual{assembler370:1979, 119 | title = {OS/VS-DOS/VSE-VM/370 Assembler Language}, 120 | edition = {6th}, 121 | organization = {IBM}, 122 | month = 3, 123 | year = 1979 124 | } 125 | 126 | 127 | @manual{ttl74154:1979, 128 | title = "\href{http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sdls056&fileType=pdf}{SN54154, SN74154 4--line to 16--line Decoders/Demultiplexers}", 129 | organization = {Texas Instruments}, 130 | month = 12, 131 | year = 1972 132 | } 133 | 134 | @manual{ttl74191:1979, 135 | title = "\href{http://www.ti.com/lit/ds/symlink/sn74ls191.pdf}{SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 Synchronous Up/Down Counters With Down/Up Mode Control}", 136 | organization = {Texas Instruments}, 137 | month = 3, 138 | year = 1988 139 | } 140 | 141 | 142 | 143 | @Misc{IEN137, 144 | author = "Danny Cohen", 145 | title = "\href{http://www.ietf.org/rfc/ien/ien137.txt}{IEN 137, On Holy Wars and a Plea for Peace}", 146 | month = apr, 147 | year = "1980", 148 | note = "This note discusses the Big-Endian/Little-Endian 149 | byte/bit-order controversy, but did not settle it. A 150 | decade later, David V. James in ``Multiplexed Buses: 151 | The Endian Wars Continue'', {\em IEEE Micro}, {\bf 152 | 10}(3), 9--21 (1990) continued the discussion.", 153 | %%% URL = "http://www.ietf.org/rfc/ien/ien137.txt", 154 | } 155 | 156 | 157 | @misc{subtrahend, 158 | title = {Definition of Subtrahend}, 159 | howpublished = {\href{https://www.mathsisfun.com/definitions/subtrahend.html}{www.mathsisfun.com/definitions/subtrahend.html}}, 160 | note = {Accessed: 2018-06-02} 161 | } 162 | 163 | @article{ieee:754, 164 | author={}, 165 | journal={IEEE Std 754-2019 (Revision of IEEE 754-2008)}, 166 | title={IEEE Standard for Floating-Point Arithmetic}, 167 | year={2019}, 168 | volume={}, 169 | number={}, 170 | pages={1-84},} 171 | 172 | -------------------------------------------------------------------------------- /book/install/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Installing a RISC-V Toolchain} 2 | \label{chapter:install} 3 | 4 | All of the software presented in this text was assembled/compiled 5 | using the GNU toolchain and executed using the rvddt simulator on 6 | a Linux (Ubuntu 20.04 LTS) operating system. 7 | 8 | The installation instructions provided here were last tested on 9 | on March 5, 2021. 10 | 11 | It is expected that these tools will evolve over time. See the 12 | respective documentation web sites for the latest news and options 13 | for installing them. 14 | 15 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 16 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 17 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 18 | \section{The GNU Toolchain} 19 | 20 | \enote{It would be good to find some Mac and Windows users to write 21 | and test proper variations on this section to address those systems. 22 | Pull requests, welcome!}% 23 | In order to install custom code in a location that will not cause 24 | interference with other applications (and allow for easy hacking and 25 | cleanup), these will install the toolchain under 26 | a private directory: \verb@~/projects/riscv/install@. At any time 27 | you can remove everything and start over by executing the following 28 | command: 29 | 30 | \begin{tty} 31 | rm -rf ~/projects/riscv/install 32 | \end{tty} 33 | 34 | \begin{tcolorbox} 35 | Be {\em very} careful how you type the above \verb@rm@ command. 36 | If typed incorrectly, it could irreversibly remove many of your files! 37 | \end{tcolorbox} 38 | 39 | Before building the toolchain, a number of utilities must be present on 40 | your system. The following will install those that are needed: 41 | 42 | \begin{minipage}{\textwidth} 43 | \begin{tty} 44 | sudo apt install autoconf automake autotools-dev curl python3 python-dev libmpc-dev \ 45 | libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf \ 46 | libtool patchutils bc zlib1g-dev libexpat-dev 47 | \end{tty} 48 | \end{minipage} 49 | 50 | Note that the above \verb@apt@ command is the only operation that should 51 | be performed as root. All other commands should be executed as a regular 52 | user. This will eliminate the possibility of clobbering system files that 53 | should not be touched when tinkering with the toolchain applications. 54 | 55 | \enote{Discuss the choice of ilp32 as well as what the other variations 56 | would do.}% 57 | To download, compile and install the toolchain: 58 | 59 | \begin{minipage}{\textwidth} 60 | \begin{tty} 61 | mkdir -p ~/projects/riscv 62 | cd ~/projects/riscv 63 | git clone https://github.com/riscv/riscv-gnu-toolchain 64 | cd riscv-gnu-toolchain 65 | INS_DIR=~/projects/riscv/install/rv32i 66 | ./configure --prefix=$INS_DIR \ 67 | --with-multilib-generator="rv32i-ilp32--;rv32imafd-ilp32--;rv32ima-ilp32--" 68 | make 69 | \end{tty} 70 | \end{minipage} 71 | 72 | After building the toolchain, make it available by putting it into 73 | your PATH by adding the following to the end of your \verb@.bashrc@ file: 74 | 75 | \begin{tty} 76 | export PATH=$PATH:$INS_DIR 77 | \end{tty} 78 | 79 | For this \verb@PATH@ change to take place, start a new terminal or paste the 80 | same \verb@export@ command into your existing terminal. 81 | 82 | 83 | 84 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 85 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 86 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 87 | \section{rvddt} 88 | 89 | Download and install the rvddt simulator by executing the following 90 | commands. 91 | Building the rvddt example programs will verify that the GNU toolchain 92 | has been built and installed properly. 93 | 94 | \begin{minipage}{\textwidth} 95 | %git clone git@github.com:johnwinans/rvddt.git 96 | \begin{tty} 97 | cd ~/projects/riscv 98 | git clone https://github.com/johnwinans/rvddt.git 99 | cd rvddt/src 100 | make world 101 | cd ../examples 102 | make world 103 | \end{tty} 104 | \end{minipage} 105 | 106 | After building rvddt, make it available by putting it into your PATH 107 | by adding the following to the end of your \verb@.bashrc@ file: 108 | 109 | \begin{tty} 110 | export PATH=$PATH:~/projects/riscv/rvddt/src 111 | \end{tty} 112 | 113 | For this \verb@PATH@ change to take place, start a new terminal or paste the 114 | same \verb@export@ command into your existing terminal. 115 | 116 | 117 | Test the rvddt build by executing one of the examples: 118 | 119 | \begin{minipage}{\textwidth} 120 | \begin{tty} 121 | winans@ux410:~/projects/riscv/rvddt/examples$ rvddt -f counter/counter.bin 122 | sp initialized to top of memory: 0x0000fff0 123 | Loading 'counter/counter.bin' to 0x0 124 | This is rvddt. Enter ? for help. 125 | ddt> ti 0 1000 126 | 00000000: 00300293 addi x5, x0, 3 # x5 = 0x00000003 = 0x00000000 + 0x00000003 127 | 00000004: 00000313 addi x6, x0, 0 # x6 = 0x00000000 = 0x00000000 + 0x00000000 128 | 00000008: 00130313 addi x6, x6, 1 # x6 = 0x00000001 = 0x00000000 + 0x00000001 129 | 0000000c: fe534ee3 blt x6, x5, -4 # pc = (0x1 < 0x3) ? 0x8 : 0x10 130 | 00000008: 00130313 addi x6, x6, 1 # x6 = 0x00000002 = 0x00000001 + 0x00000001 131 | 0000000c: fe534ee3 blt x6, x5, -4 # pc = (0x2 < 0x3) ? 0x8 : 0x10 132 | 00000008: 00130313 addi x6, x6, 1 # x6 = 0x00000003 = 0x00000002 + 0x00000001 133 | 0000000c: fe534ee3 blt x6, x5, -4 # pc = (0x3 < 0x3) ? 0x8 : 0x10 134 | 00000010: ebreak 135 | ddt> x 136 | winans@ux410:~/projects/riscv/rvddt/examples$ 137 | \end{tty} 138 | \end{minipage} 139 | 140 | 141 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 142 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 143 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 144 | \section{qemu} 145 | 146 | You can download and install the RV32 qemu simulator by executing 147 | the following commands. 148 | 149 | At the time of this writing (2021-06) I use release v5.0.0. 150 | Release v5.2.0 has issues that confuse GDB when printing the registers 151 | and v6.0.0 has different CPU types that I have had trouble with when 152 | executing privileged instructions. 153 | 154 | \begin{minipage}{\textwidth} 155 | \begin{tty} 156 | INS_DIR=~/projects/riscv/install/rv32i 157 | cd ~/projects/riscv 158 | git clone git@github.com:qemu/qemu.git 159 | cd qemu 160 | git checkout v5.0.0 161 | ./configure --target-list=riscv32-softmmu --prefix=${INS_DIR} 162 | make -j4 163 | make install 164 | \end{tty} 165 | \end{minipage} 166 | 167 | -------------------------------------------------------------------------------- /book/glossary.tex: -------------------------------------------------------------------------------- 1 | \newglossaryentry{latex} 2 | { 3 | name=LaTeX, 4 | description={Is a mark up language specially suited 5 | for scientific documents} 6 | } 7 | 8 | \newglossaryentry{binary} 9 | { 10 | name=binary, 11 | description={Something that has two parts or states. In computing 12 | these two states are represented by the numbers one and zero or 13 | by the conditions true and false and can be stored in one \gls{bit}} 14 | } 15 | \newglossaryentry{hexadecimal} 16 | { 17 | name=hexadecimal, 18 | description={A base-16 numbering system whose digits are 0123456789abcdef. 19 | The hex digits (\gls{hit}s) are not case-sensitive} 20 | } 21 | \newglossaryentry{bit} 22 | { 23 | name=bit, 24 | description={One binary digit} 25 | } 26 | \newglossaryentry{hit} 27 | { 28 | name={hit}, 29 | description={One \gls{hexadecimal} digit} 30 | } 31 | \newglossaryentry{nybble} 32 | { 33 | name={nybble}, 34 | description={Half of a {\em \gls{byte}} is a {\em nybble} 35 | (sometimes spelled nibble.) Another word for {\em \gls{hit}}} 36 | } 37 | \newglossaryentry{byte} 38 | { 39 | name=byte, 40 | description={A \gls{binary} value represented by 8 \gls{bit}s} 41 | } 42 | \newglossaryentry{halfword} 43 | { 44 | name={halfword}, 45 | description={A \gls{binary} value represented by 16 \gls{bit}s} 46 | } 47 | \newglossaryentry{fullword} 48 | { 49 | name={fullword}, 50 | description={A \gls{binary} value represented by 32 \gls{bit}s} 51 | } 52 | \newglossaryentry{doubleword} 53 | { 54 | name={doubleword}, 55 | description={A \gls{binary} value represented by 64 \gls{bit}s} 56 | } 57 | \newglossaryentry{quadword} 58 | { 59 | name={quadword}, 60 | description={A \gls{binary} value represented by 128 \gls{bit}s} 61 | } 62 | \newglossaryentry{HighOrderBits} 63 | { 64 | name={high order bits}, 65 | description={Some number of \acrshort{msb}s} 66 | } 67 | \newglossaryentry{LowOrderBits} 68 | { 69 | name={low order bits}, 70 | description={Some number of \acrshort{lsb}s} 71 | } 72 | 73 | \newglossaryentry{xlen} 74 | { 75 | name=XLEN, 76 | description={The number of bits a RISC-V x integer \gls{register} 77 | (such as x0). For RV32 XLEN=32, RV64 XLEN=64 and so on} 78 | } 79 | \newglossaryentry{rv32} 80 | { 81 | name=RV32, 82 | description={Short for RISC-V 32. The number 32 refers to the \gls{xlen}} 83 | } 84 | \newglossaryentry{rv64} 85 | { 86 | name=RV64, 87 | description={Short for RISC-V 64. The number 64 refers to the \gls{xlen}} 88 | } 89 | \newglossaryentry{overflow} 90 | { 91 | name=overflow, 92 | description={The situation where the result of an addition or 93 | subtraction operation is approaching positive or negative 94 | infinity and exceeds the number of bits allotted to contain 95 | the result. This is typically caused by high-order truncation} 96 | } 97 | \newglossaryentry{underflow} 98 | { 99 | name=underflow, 100 | description={The situation where the result of an addition or 101 | subtraction operation is approaching zero and exceeds the number 102 | of bits allotted to contain the result. This is typically 103 | caused by low-order truncation} 104 | } 105 | 106 | \newglossaryentry{MachineLanguage} 107 | { 108 | name={machine language}, 109 | description={The instructions that are executed by a CPU that are expressed 110 | in the form of \gls{binary} values} 111 | } 112 | \newglossaryentry{register} 113 | { 114 | name={register}, 115 | description={A unit of storage inside a CPU with the capacity of \gls{xlen} \gls{bit}s} 116 | } 117 | \newglossaryentry{program} 118 | { 119 | name={program}, 120 | description={A ordered list of one or more instructions} 121 | } 122 | \newglossaryentry{address} 123 | { 124 | name={address}, 125 | description={A numeric value used to uniquely identify each \gls{byte} of main memory} 126 | } 127 | \newglossaryentry{alignment} 128 | { 129 | name={alignment}, 130 | description={Refers to a range of numeric values that begin 131 | at a multiple of some number. Primarily used when referring to 132 | a memory address. For example an alignment of two refers to one 133 | or more addresses starting at even address and continuing onto 134 | subsequent adjacent, increasing memory addresses} 135 | } 136 | \newglossaryentry{exception} 137 | { 138 | name={exception}, 139 | description={An error encountered by the CPU while executing an instruction 140 | that can not be completed} 141 | } 142 | 143 | \newglossaryentry{bigendian} 144 | { 145 | name={big-endian}, 146 | description={A number format where the most significant values are 147 | printed to the left of the lesser significant values. This is the 148 | method that everyone uses to write decimal numbers every day} 149 | } 150 | \newglossaryentry{littleendian} 151 | { 152 | name={little-endian}, 153 | description={A number format where the least significant values are 154 | printed to the left of the more significant values. This is the 155 | opposite ordering that everyone learns in grade school when learning 156 | how to count. For example, the \gls{bigendian} number written as ``1234'' 157 | would be written in little endian form as ``4321''} 158 | } 159 | \newglossaryentry{rvddt} 160 | { 161 | name={rvddt}, 162 | description={A RV32I simulator and debugging tool inspired by the 163 | simplicity of the Dynamic Debugging Tool (ddt) that was part of 164 | the CP/M operating system} 165 | } 166 | \newglossaryentry{mnemonic} 167 | { 168 | name={mnemonic}, 169 | description={A method used to remember something. In the case of 170 | assembly language, each machine instruction is given a name 171 | so the programmer need not memorize the binary values of each 172 | machine instruction} 173 | } 174 | \newglossaryentry{thread} 175 | { 176 | name={thread}, 177 | description={An stream of instructions. When plural, it is 178 | used to refer to the ability of a CPU to execute multiple 179 | instruction streams at the same time} 180 | } 181 | \newglossaryentry{ascii} 182 | { 183 | name={ASCII}, 184 | description={American Standard Code for Information Interchange. 185 | See \autoref{chapter:ascii}} 186 | } 187 | \newglossaryentry{place-value} 188 | { 189 | name={place value}, 190 | description={the numerical value that a digit has as a result of its {\em position} within a number. 191 | For example, the digit 2 in the decimal number 123 is in the ten's place and its place value is 20} 192 | } 193 | 194 | 195 | \newacronym{hart}{hart}{Hardware Thread} 196 | \newacronym{msb}{MSB}{Most Significant Bit} 197 | \newacronym{lsb}{LSB}{Least Significant Bit} 198 | \newacronym{isa}{ISA}{Instruction Set Architecture} 199 | \newacronym{cpu}{CPU}{Central Processing Unit} 200 | \newacronym{ram}{RAM}{Random Access Memory} 201 | \newacronym{rom}{ROM}{Read Only Memory} 202 | %\newacronym{ascii}{ASCII}{American Standard Code for Information Interchange} 203 | -------------------------------------------------------------------------------- /book/ascii/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{The ASCII Character Set} 2 | \label{chapter:ascii} 3 | \index{ASCII} 4 | 5 | A slightly abridged version of the Linux ``ASCII'' man(1) page. 6 | 7 | \section{NAME} 8 | 9 | ascii - ASCII character set encoded in octal, decimal, and hexadecimal 10 | 11 | \section{DESCRIPTION} 12 | 13 | ASCII is the American Standard Code for Information Interchange. It is 14 | a 7-bit code. Many 8-bit codes (e.g., ISO 8859-1) contain ASCII as 15 | their lower half. The international counterpart of ASCII is known as 16 | ISO 646-IRV. 17 | 18 | The following table contains the 128 ASCII characters. 19 | 20 | C program '\verb@\X@' escapes are noted. 21 | 22 | \begin{verbatim} 23 | Oct Dec Hex Char Oct Dec Hex Char 24 | ------------------------------------------------------------------------ 25 | 000 0 00 NUL '\0' (null character) 100 64 40 @ 26 | 001 1 01 SOH (start of heading) 101 65 41 A 27 | 002 2 02 STX (start of text) 102 66 42 B 28 | 003 3 03 ETX (end of text) 103 67 43 C 29 | 004 4 04 EOT (end of transmission) 104 68 44 D 30 | 005 5 05 ENQ (enquiry) 105 69 45 E 31 | 006 6 06 ACK (acknowledge) 106 70 46 F 32 | 007 7 07 BEL '\a' (bell) 107 71 47 G 33 | 010 8 08 BS '\b' (backspace) 110 72 48 H 34 | 011 9 09 HT '\t' (horizontal tab) 111 73 49 I 35 | 012 10 0A LF '\n' (new line) 112 74 4A J 36 | 013 11 0B VT '\v' (vertical tab) 113 75 4B K 37 | 014 12 0C FF '\f' (form feed) 114 76 4C L 38 | 015 13 0D CR '\r' (carriage ret) 115 77 4D M 39 | 016 14 0E SO (shift out) 116 78 4E N 40 | 017 15 0F SI (shift in) 117 79 4F O 41 | 020 16 10 DLE (data link escape) 120 80 50 P 42 | 021 17 11 DC1 (device control 1) 121 81 51 Q 43 | 022 18 12 DC2 (device control 2) 122 82 52 R 44 | 023 19 13 DC3 (device control 3) 123 83 53 S 45 | 024 20 14 DC4 (device control 4) 124 84 54 T 46 | 025 21 15 NAK (negative ack.) 125 85 55 U 47 | 026 22 16 SYN (synchronous idle) 126 86 56 V 48 | 027 23 17 ETB (end of trans. blk) 127 87 57 W 49 | 030 24 18 CAN (cancel) 130 88 58 X 50 | 031 25 19 EM (end of medium) 131 89 59 Y 51 | 032 26 1A SUB (substitute) 132 90 5A Z 52 | 033 27 1B ESC (escape) 133 91 5B [ 53 | 034 28 1C FS (file separator) 134 92 5C \ '\\' 54 | 035 29 1D GS (group separator) 135 93 5D ] 55 | 036 30 1E RS (record separator) 136 94 5E ^ 56 | 037 31 1F US (unit separator) 137 95 5F _ 57 | 040 32 20 SPACE 140 96 60 ` 58 | 041 33 21 ! 141 97 61 a 59 | 042 34 22 " 142 98 62 b 60 | 043 35 23 # 143 99 63 c 61 | 044 36 24 $ 144 100 64 d 62 | 045 37 25 % 145 101 65 e 63 | 046 38 26 & 146 102 66 f 64 | 047 39 27 ' 147 103 67 g 65 | 050 40 28 ( 150 104 68 h 66 | 051 41 29 ) 151 105 69 i 67 | 052 42 2A * 152 106 6A j 68 | 053 43 2B + 153 107 6B k 69 | 054 44 2C , 154 108 6C l 70 | 055 45 2D - 155 109 6D m 71 | 056 46 2E . 156 110 6E n 72 | 057 47 2F / 157 111 6F o 73 | 060 48 30 0 160 112 70 p 74 | 061 49 31 1 161 113 71 q 75 | 062 50 32 2 162 114 72 r 76 | 063 51 33 3 163 115 73 s 77 | 064 52 34 4 164 116 74 t 78 | 065 53 35 5 165 117 75 u 79 | 066 54 36 6 166 118 76 v 80 | 067 55 37 7 167 119 77 w 81 | 070 56 38 8 170 120 78 x 82 | 071 57 39 9 171 121 79 y 83 | 072 58 3A : 172 122 7A z 84 | 073 59 3B ; 173 123 7B { 85 | 074 60 3C < 174 124 7C | 86 | 075 61 3D = 175 125 7D } 87 | 076 62 3E > 176 126 7E ~ 88 | 077 63 3F ? 177 127 7F DEL 89 | \end{verbatim} 90 | 91 | \subsection{Tables} 92 | For convenience, below are more compact tables in hex and decimal. 93 | 94 | \begin{verbatim} 95 | 2 3 4 5 6 7 30 40 50 60 70 80 90 100 110 120 96 | ------------- --------------------------------- 97 | 0: 0 @ P ` p 0: ( 2 < F P Z d n x 98 | 1: ! 1 A Q a q 1: ) 3 = G Q [ e o y 99 | 2: " 2 B R b r 2: * 4 > H R \ f p z 100 | 3: # 3 C S c s 3: ! + 5 ? I S ] g q { 101 | 4: $ 4 D T d t 4: " , 6 @ J T ^ h r | 102 | 5: % 5 E U e u 5: # - 7 A K U _ i s } 103 | 6: & 6 F V f v 6: $ . 8 B L V ` j t ~ 104 | 7: ' 7 G W g w 7: % / 9 C M W a k u DEL 105 | 8: ( 8 H X h x 8: & 0 : D N X b l v 106 | 9: ) 9 I Y i y 9: ' 1 ; E O Y c m w 107 | A: * : J Z j z 108 | B: + ; K [ k { 109 | C: , < L \ l | 110 | D: - = M ] m } 111 | E: . > N ^ n ~ 112 | F: / ? O _ o DEL 113 | \end{verbatim} 114 | 115 | \section{NOTES} 116 | \subsection{History} 117 | 118 | An ascii manual page appeared in Version 7 of AT\&T UNIX. 119 | 120 | On older terminals, the underscore code is displayed as a left arrow, 121 | called backarrow, the caret is displayed as an up-arrow and the 122 | vertical bar has a hole in the middle. 123 | 124 | Uppercase and lowercase characters differ by just one bit and the ASCII 125 | character 2 differs from the double quote by just one bit, too. That 126 | made it much easier to encode characters mechanically or with a 127 | non-microcontroller-based electronic keyboard and that pairing was found on 128 | old teletypes. 129 | 130 | The ASCII standard was published by the United States of America 131 | Standards Institute (USASI) in 1968. 132 | 133 | \section{COLOPHON} 134 | 135 | This page is part of release 4.04 of the Linux man-pages project. A 136 | description of the project, information about reporting bugs, and the 137 | latest version of this page, can be found at 138 | \url{http://www.kernel.org/doc/man-pages/}. 139 | -------------------------------------------------------------------------------- /book/priv/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Privileged Instructions} 2 | \label{chapter:privileged} 3 | 4 | \section{Introduction} 5 | 6 | {\em XXX NOTE: This is a first draft of what is being detailed in the previous chapter} 7 | 8 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 9 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 10 | 11 | \subsection{CSRRW rd, csr, rs1} 12 | \index{Instruction!CSRRW} 13 | 14 | The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in 15 | the CSRs and integer registers. CSRRW reads the old value of the CSR, 16 | zero-extends the value to XLEN bits, then writes it to integer register rd. 17 | The initial value in rs1 is written to the CSR. If rd=x0, then the 18 | instruction shall not read the CSR and shall not cause any of the 19 | side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017} 20 | 21 | \DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011} 22 | 23 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 24 | \subsection{CSRRS rd, csr, rs1} 25 | \index{Instruction!CSRRS} 26 | 27 | The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value 28 | of the CSR, zero-extends the value to XLEN bits, and writes it to integer 29 | register rd. The initial value in integer register rs1 is treated as a bit 30 | mask that specifies bit positions to be set in the CSR. Any bit that 31 | is high in rs1 will cause the corresponding bit to be set in the CSR, 32 | if that CSR bit is writable. Other bits in the CSR are unaffected (though 33 | CSRs might have side effects when written).~\cite[p.~22]{rvismv1v22:2017} 34 | 35 | If rs1=x0, then the instruction will not write 36 | to the CSR at all, and so shall not cause any of the side effects that 37 | might otherwise occur on a CSR write, such as raising illegal instruction 38 | exceptions on accesses to read-only CSRs. Note that if rs1 specifies a 39 | register holding a zero value other than x0, the instruction will still 40 | attempt to write the unmodified value back to the CSR and will cause any 41 | attendant side effects.~\cite[p.~22]{rvismv1v22:2017} 42 | 43 | \DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011} 44 | 45 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 46 | \subsection{CSRRC rd, csr, rs1} 47 | \index{Instruction!CSRRC} 48 | 49 | The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value 50 | of the CSR, zero-extends the value to XLEN bits, and writes it to integer 51 | register rd. The initial value in integer register rs1 is treated as a 52 | bit mask that specifies bit positions to be cleared in the CSR. Any bit 53 | that is high in rs1 will cause the corresponding bit to be cleared in 54 | the CSR, if that CSR bit is writable. Other bits in the CSR are 55 | unaffected.~\cite[p.~22]{rvismv1v22:2017} 56 | 57 | If rs1=x0, then the instruction will not write 58 | to the CSR at all, and so shall not cause any of the side effects that 59 | might otherwise occur on a CSR write, such as raising illegal instruction 60 | exceptions on accesses to read-only CSRs. Note that if rs1 specifies a 61 | register holding a zero value other than x0, the instruction will still 62 | attempt to write the unmodified value back to the CSR and will cause any 63 | attendant side effects.~\cite[p.~22]{rvismv1v22:2017} 64 | 65 | \DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011} 66 | 67 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 68 | \subsection{CSRRWI rd, csr, imm} 69 | \index{Instruction!CSRRWI} 70 | 71 | This instruction is the same as CSRRW except a 5-bit unsigned (zero-extended) 72 | immediate value is used rather than the value from a register. 73 | 74 | \DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011} 75 | 76 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 77 | \subsection{CSRRSI rd, csr, rs1} 78 | \index{Instruction!CSRRSI} 79 | 80 | This instruction is the same as CSRRS except a 5-bit unsigned (zero-extended) 81 | immediate value is used rather than the value from a register. 82 | 83 | If the uimm[4:0] field is zero, then this instruction will not 84 | write to the CSR, and shall not cause any of the side effects that 85 | might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then 86 | the instruction shall not read the CSR and shall not cause any 87 | of the side-effects that might occur on a CSR 88 | read.~\cite[p.~22]{rvismv1v22:2017} 89 | 90 | \DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011} 91 | 92 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 93 | \subsection{CSRRCI rd, csr, rs1} 94 | \index{Instruction!CSRRCI} 95 | 96 | This instruction is the same as CSRRC except a 5-bit unsigned (zero-extended) 97 | immediate value is used rather than the value from a register. 98 | 99 | If the uimm[4:0] field is zero, then this instruction will not 100 | write to the CSR, and shall not cause any of the side effects that 101 | might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then 102 | the instruction shall not read the CSR and shall not cause any 103 | of the side-effects that might occur on a CSR 104 | read.~\cite[p.~22]{rvismv1v22:2017} 105 | 106 | \DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011} 107 | 108 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 109 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 110 | \section{RV32M Standard Extension} 111 | \index{RV32M} 112 | 113 | 32-bit integer multiply and divide instructions. 114 | 115 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 116 | \subsection{MUL rd, rs1, rs2} 117 | \index{Instruction!MUL} 118 | 119 | Multiply \reg{rs1} by \reg{rs2} and store the least significant 32-bits 120 | of the result in \reg{rd}. 121 | 122 | \DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011} 123 | 124 | 125 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 126 | \subsection{MULH rd, rs1, rs2} 127 | \index{Instruction!MULH} 128 | 129 | \DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011} 130 | 131 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 132 | \subsection{MULHS rd, rs1, rs2} 133 | \index{Instruction!MULHS} 134 | 135 | \DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011} 136 | 137 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 138 | \subsection{MULHU rd, rs1, rs2} 139 | \index{Instruction!MULHU} 140 | 141 | \DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011} 142 | 143 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 144 | \subsection{DIV rd, rs1, rs2} 145 | \index{Instruction!DIV} 146 | 147 | \DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011} 148 | 149 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 150 | \subsection{DIVU rd, rs1, rs2} 151 | \index{Instruction!DIVU} 152 | 153 | \DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011} 154 | 155 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 156 | \subsection{REM rd, rs1, rs2} 157 | \index{Instruction!REM} 158 | 159 | \DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011} 160 | 161 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 162 | \subsection{REMU rd, rs1, rs2} 163 | \index{Instruction!REMU} 164 | 165 | \DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011} 166 | 167 | 168 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 169 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 170 | \section{RV32A Standard Extension} 171 | \index{RV32A} 172 | 173 | 32-bit atomic operations. 174 | 175 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 176 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 177 | \section{RV32F Standard Extension} 178 | \index{RV32F} 179 | 180 | 32-bit IEEE floating point instructions. 181 | 182 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 183 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 184 | \section{RV32D Standard Extension} 185 | \index{RV32D} 186 | 187 | 64-bit IEEE floating point instructions. 188 | -------------------------------------------------------------------------------- /book/elements/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{The Elements of a Assembly Language Program} 2 | \label{chapter:elements} 3 | 4 | \section{Assembly Language Statements} 5 | 6 | Introduce the assembly language grammar. 7 | \begin{itemize} 8 | \item Statement = 1 line of text containing an instruction or directive. 9 | \item Instruction = label, mnemonic, operands, comment. 10 | \item Directive = Used to control the operation of the assembler. 11 | \end{itemize} 12 | 13 | \section{Memory Layout} 14 | 15 | Is this a good place to introduce the text, data, bss, heap and stack regions? 16 | 17 | Or does that belong in a new section/chapter that discusses addressing modes? 18 | 19 | 20 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 21 | \section{A Sample Program Source Listing} 22 | 23 | A simple program that illustrates how this text presents 24 | program source code is seen in \listingRef{zero4regs.S}. 25 | This program will place a zero in each of the 4 registers 26 | named x28, x29, x30 and x31. 27 | 28 | \listing{zero4regs.S}{Setting four registers to zero.} 29 | 30 | This program listing illustrates a number of things: 31 | \begin{itemize} 32 | \item Listings are identified by the name of the file within which 33 | they are stored. This listing is from a file named: \verb@zero4regs.S@. 34 | \item The assembly language programs discussed in this text will be saved 35 | in files that end with: \verb@.S@ (Alternately you can use \verb@.sx@ 36 | on systems that don't understand the difference between upper and 37 | lowercase letters.\footnote{The author of this text prefers to avoid 38 | using such systems.}) 39 | \item A description of the listing's purpose appears under the name of the 40 | file. The description of \listingRef{zero4regs.S} is 41 | {\em Setting four registers to zero.} 42 | \item The lines of the listing are numbered on the left margin for 43 | easy reference. 44 | \item An assembly program consists of lines of plain text. 45 | \item The RISC-V ISA does not provide an operation that will simply 46 | set a register to a numeric value. To accomplish our goal this 47 | program will add zero to zero and place the sum in in each of the 48 | four registers. 49 | \item The lines that start with a dot `.' (on lines 1, 2 and 3) are 50 | called {\em assembler directives} as they tell the assembler itself 51 | how we want it to translate the following {\em assembly language instructions} 52 | into {\em machine language instructions.} 53 | \item Line 4 shows a {\em label} named {\em \_start}. The colon 54 | at the end is the indicator to the assembler that causes it to 55 | recognize the preceding characters as a label. 56 | \item Lines 5-8 are the four assembly language instructions that 57 | make up the program. Each instruction in this program 58 | consists of four {\em fields}. (Different instructions can have 59 | a different number of fields.) The fields on line 5 are: 60 | 61 | \begin{itemize} 62 | \item [addi] The instruction mnemonic. It indicates the operation 63 | that the CPU will perform. 64 | \item [x28] The {\em destination} register that will receive the 65 | sum when the {\em addi} instruction is finished. The names of 66 | the 32 registers are expressed as x0 -- x31. 67 | \item [x0] One of the addends of the sum operation. (The x0 register 68 | will always contain the value zero. It can never be changed.) 69 | \item [0] The second addend is the number zero. 70 | \item [\# set \ldots] Any text anywhere in a RISC-V assembly language 71 | program that starts with the pound-sign is ignored by the assembler. 72 | They are used to place a {\em comment} in the program to help 73 | the reader better understand the motive of the programmer. 74 | \end{itemize} 75 | \end{itemize} 76 | 77 | 78 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 79 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 80 | \section{Running a Program With rvddt} 81 | \index{rvddt} 82 | 83 | To illustrate what a CPU does when it executes instructions this text 84 | will use the \gls{rvddt} simulator to display shows sequence of events 85 | and the binary values involved. This simulator supports the RV32I ISA 86 | and has a configurable amount of memory.% 87 | \footnote{The {\em rvddt} simulator was written to generate the listings for 88 | this text. It is similar to the fancier {\em spike} simulator. 89 | Given the simplicity of the RV32I ISA, rvddt is less than 1700 lines of C++ 90 | and was written in one (long) afternoon.} 91 | 92 | \listingRef{zero4regs.out} shows the operation of the four 93 | {\em addi} instructions from \listingRef{zero4regs.S} when it is executed 94 | in trace-mode. 95 | 96 | \listing{zero4regs.out}{Running a program with the rvddt simulator} 97 | 98 | \begin{itemize} 99 | \item [$\ell$ 1] This listing includes the command-line that shows how the simulator 100 | was executed to load a file containing the machine instructions (aka 101 | machine code) from the assembler. 102 | \item [$\ell$ 2] A message from the simulator indicating that it loaded the machine 103 | code into simulated memory at address 0. 104 | \item [$\ell$ 3] This line shows the prompt from the debugger and the command 105 | \verb@t4@ that the user entered to request that the simulator trace 106 | the execution of four instructions. 107 | \item [$\ell$ 4-8] Prior to executing the first instruction, the state of the 108 | CPU registers is displayed. 109 | \item [$\ell$ 4] The values in registers 0, 1, 2, 3, 4, 5, 6 and 7 are printed 110 | from left to right in \gls{bigendian}, \gls{hexadecimal} form. 111 | The double-space gap in the middle of the line is a reference 112 | to make it easier to visually navigate across the line without being 113 | forced to count the values from the far left when seeking the value 114 | of, say, x5. 115 | \item [$\ell$ 5-7] The values of registers 8--31 are printed. 116 | \item [$\ell$ 8] The {\em program counter} (\reg{pc}) register is printed. 117 | It contains the address of the instruction that the CPU will execute. 118 | After each instruction, the \reg{pc} will either advance four bytes 119 | ahead or be set to another value by a branch instruction as discussed above. 120 | \item [$\ell$ 9] A four-byte instruction is fetched from memory at the address 121 | in the \reg{pc} register, is decoded and printed. From left to right 122 | the fields shown on this line are: 123 | 124 | \begin{itemize} 125 | 126 | \item [00000000] The memory address from which the instruction was 127 | fetched. This address is displayed in \gls{bigendian}, 128 | \gls{hexadecimal} form. 129 | \item [00000e13] The machine code of the instruction displayed in 130 | \gls{bigendian}, \gls{hexadecimal} form. 131 | \item [addi] The mnemonic for the machine instruction. 132 | \item [x28] The \reg{rd} field of the addi instruction. 133 | \item [x0] The \reg{rs1} field of the addi instruction that 134 | holds one of the two addends of the operation. 135 | \item [0] The \reg{imm} field of the addi instruction that 136 | holds the second of the two addends of the operation. 137 | \item [\# \ldots] A simulator-generated comment that explains 138 | what the instruction is doing. For this instruction it indicates 139 | that \reg{x28} will have the value zero stored into it as a result 140 | of performing the addition: $0+0$. 141 | \end{itemize} 142 | 143 | \item [$\ell$ 10-14] These lines are printed as the prelude while tracing the 144 | second instruction. Lines 7 and 13 show that \reg{x28} has changed 145 | from \verb@f0f0f0f0@ to \verb@00000000@ as a result of executing the 146 | first instruction and lines 8 and 14 show that the \reg{pc} has 147 | advanced from zero (the location of the first instruction) to 148 | four, where the second instruction will be fetched. None of the 149 | rest of the registers have changed values. 150 | \item [$\ell$ 15] The second instruction decoded executed and described. 151 | This time register \reg{x29} will be assigned a value. 152 | \item [$\ell$ 16-27] The third and fourth instructions are traced. 153 | \item [$\ell$ 28] Tracing has completed. The simulator prints its prompt 154 | and the user enters the `r' command to see the register state 155 | after the fourth instruction has completed executing. 156 | \item [$\ell$ 29-33] Following the fourth instruction it can be observed 157 | that registers \reg{x28}, \reg{x29}, \reg{x30} and \reg{x31} 158 | have been set to zero and that the \reg{pc} has advanced from 159 | zero to four, then eight, then 12 (the hex value for 12 is c) 160 | and then to 16 (which, in hex, is 10). 161 | \item [$\ell$ 34] The simulator exit command `x' is entered by the user and 162 | the terminal displays the shell prompt. 163 | 164 | \end{itemize} 165 | -------------------------------------------------------------------------------- /book/preamble.tex: -------------------------------------------------------------------------------- 1 | 2 | \oddsidemargin=.82in 3 | %\evensidemargin=1.82in 4 | \evensidemargin=1.72in 5 | 6 | %\topmargin=-.5in 7 | \headheight=12pt 8 | \headsep=20pt 9 | 10 | %\hoffset=-1.2in % for 8.5x11 11 | \hoffset=-1.1in % for 8.5x11 12 | 13 | %\voffset=-1.15in % for 8.5x11 14 | \voffset=-.8in % for 8.5x11 15 | 16 | %\textheight=9.75in % for 8.5x11 17 | \textheight=9in % for 8.5x11 18 | %\textheight=8.75in % for 8.5x11 19 | 20 | \textwidth=6.1in % for 8.5x11 21 | %\textwidth=6.25in % for 8.5x11 22 | 23 | \marginparsep=7pt 24 | %\marginparwidth=71pt 25 | %\marginparwidth=1.25in 26 | %\marginparwidth=1.5in 27 | \marginparwidth=1.25in 28 | \footskip=36pt 29 | \marginparpush=5pt 30 | 31 | 32 | \usepackage{ifthen} 33 | \usepackage{stringstrings} % so can count characters in a string 34 | \usepackage{xstring} % so can count characters in a string 35 | 36 | \usepackage[pass]{geometry} 37 | \usepackage{color} % Necessary for colored links 38 | 39 | % load makeidx BEFORE hyperref to make the index clickable 40 | % load makeidx AFTER hyperref if want to use showidx 41 | \usepackage{makeidx} 42 | \usepackage[pagebackref]{hyperref} 43 | \hypersetup{ 44 | colorlinks=true, %set true if you want colored links 45 | linkcolor=blue %choose some color if you want links to stand out 46 | } 47 | 48 | \usepackage{scrextend} % so can use \footref 49 | 50 | % don't say subsection and subsubsection in auto-references 51 | \let\subsectionautorefname\sectionautorefname 52 | \let\subsubsectionautorefname\sectionautorefname 53 | 54 | %\usepackage{makeidx,showidx} % showidx breaks hyperref when loaded before hyperref 55 | 56 | 57 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 58 | % for one-sided on left margin 59 | \usepackage{lineno} 60 | \linenumbers 61 | \setlength\linenumbersep{.8cm} 62 | 63 | % for two-sided on inside margin 64 | %\usepackage[switch*,pagewise]{lineno} 65 | %\linenumbers 66 | %\runningpagewiselinenumbers 67 | 68 | %\renewcommand\linenumberfont{\normalfont\tiny\sffamily\bfseries\color{violet}} 69 | 70 | % lineno is screwy for displayed equations 71 | %\let\oldequation\equation 72 | %\let\oldendequation\endequation 73 | %\renewenvironment{equation} 74 | % {\linenomathNonumbers\oldequation} 75 | % {\oldendequation\endlinenomath} 76 | % 77 | %\setlength\linenumbersep{6mm} 78 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 79 | 80 | 81 | %\usepackage{url} 82 | 83 | \usepackage{lastpage} 84 | \usepackage{fancyhdr} 85 | 86 | \usepackage{amsmath} 87 | \numberwithin{equation}{section} 88 | \usepackage{amsfonts} % I hear these are also good to load 89 | \usepackage{amssymb} % I hear these are also good to load 90 | 91 | %\usepackage{picture} 92 | %\usepackage{epstopdf} 93 | %\usepackage{graphicx} 94 | \usepackage{epsfig} 95 | \usepackage{tikz-timing} 96 | \usepackage{tikz} 97 | %\usepackage{timing} 98 | \usepackage{float} 99 | \usepackage{fancyvrb} 100 | 101 | %\usepackage{caption} 102 | \usepackage[hypcap=true]{caption} % point to top of figure rather than caption in \hyperref 103 | 104 | \usepackage{placeins} 105 | 106 | \usepackage{listings} 107 | 108 | \usepackage[toc]{glossaries} 109 | %\renewcommand*{\glsclearpage}{} 110 | 111 | \usepackage{pifont} 112 | \usepackage{layout} 113 | 114 | \usepackage{xcolor} 115 | \usepackage{textcomp} % for the trademark symbol 116 | 117 | %\usepackage[obeyspaces]{url} 118 | \usepackage{fink} % deprecated in favor of currfile 119 | %\usepackage{currfile} % dut... doesn't emit the local include path properly 120 | 121 | \usepackage{MyFigs} 122 | 123 | \def\code#1{\url{#1}} 124 | 125 | % The exercise environment 126 | \usepackage{exercise} 127 | 128 | \renewcommand{\ExerciseHeader}{% 129 | \textbf{\large\ExerciseHeaderDifficulty\ExerciseName\ % 130 | \ExerciseHeaderNB\ExerciseHeaderTitle\ExerciseHeaderOrigin}\medskip} 131 | 132 | \renewcommand{\ExePartHeader}{% 133 | \medskip\emph{\large\ExePartHeaderDifficulty\ExePartName % 134 | \ExePartHeaderNB \ExePartHeaderTitle\\ 135 | }} 136 | 137 | %\renewcommand{\ExePartHeader}{% 138 | %\medskip\emph{\large\ExePartHeaderDifficulty Part \ExePartHeaderNB % 139 | %\quad \ExePartName\ExePartHeaderTitle}} 140 | 141 | 142 | 143 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 144 | %\DefineVerbatimEnvironment% 145 | %{Code}{Verbatim} 146 | %{frame=single,numbers=left,numbersep=2mm,framesep=3mm} 147 | %%%,numbersep=2mm,frame=lines,framerule=0.8mm,framesep=5mm 148 | 149 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 150 | % [1] = filename to include 151 | % [2] = title of the code sample 152 | % A label will be generated as: Code:#1 153 | %\newcommand{\xxxx}[2]{% 154 | % \label{Code:#1} % 155 | % \VerbatimInput[frame=single,numbers=left,numbersep=2mm,framesep=3mm,label={#2}]{#1}} 156 | 157 | %\newcommand{\theListingFontFamily}{\ttfamily\small} 158 | \newcommand{\theListingFontFamily}{\ttfamily\footnotesize} 159 | %\newcommand{\theListingFontFamily}{\ttfamily\scriptsize} 160 | 161 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 162 | % [1] = place for additional listing parameters, default: language=C 163 | % [2] = filepath 164 | % [3] = Description of the listing 165 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 166 | \newcommand{\listing}[3][language=C]{% 167 | \lstinputlisting[ % 168 | numbers=left,numberstyle=\tiny,stepnumber=1,numbersep=8pt, % 169 | breaklines=true, % 170 | frame=single % 171 | showtabs=false, % 172 | basicstyle=\theListingFontFamily, % 173 | showstringspaces=false, % 174 | tabsize=4, % 175 | showlines=true, % show all blank lines 176 | #1, % 177 | captionpos=t,frame=tblr,label={lst:\detokenize{#2}},caption={{\tt \detokenize{#2}}\\\hspace{\textwidth}{\small #3}}]{\detokenize{#2}}} 178 | 179 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 180 | \newcommand{\listingRef}[1]{\autoref{lst:\detokenize{#1}}} 181 | 182 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 183 | \lstnewenvironment{tty} 184 | {\lstset{language=sh, % 185 | numbers=left,numberstyle=\tiny,stepnumber=1,numbersep=8pt, % 186 | breaklines=true, % 187 | frame=single, % 188 | showtabs=false, % 189 | basicstyle=\theListingFontFamily, % 190 | showstringspaces=false, % 191 | tabsize=4, % 192 | showlines=true, % show all blank lines 193 | basicstyle=\theListingFontFamily}} 194 | {} 195 | 196 | 197 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 198 | % A footer that shall appear on every page 199 | 200 | %\newcommand{\MyFoot}{{\sf\scriptsize Copyright \copyright\ 2014, 2015 John Winans. All Rights Reserved}\\ 201 | %\vspace{.05in} 202 | %\scriptsize\FooterText} 203 | 204 | \newcommand{\MyFoot}{\scriptsize\FooterText} 205 | 206 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 207 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 208 | \pagestyle{fancy} 209 | 210 | % supress normal headings and footers 211 | \fancyhf{} 212 | 213 | % heading and footing rules 214 | \renewcommand{\headrulewidth}{1pt} 215 | \renewcommand{\footrulewidth}{1pt} 216 | 217 | 218 | %\def\DiscardOneCharacter#1{} 219 | % Sub-footer that shows the version control version string in the lfoot defined above 220 | \ifdefined\GitFileName 221 | % \newcommand{\FooterText}{\tt \GitFileName \currfilename\\ 222 | \newcommand{\FooterText}{\tt \GitFileName \finkpath\\ 223 | \GitDescription} 224 | \else 225 | \newcommand{\FooterText}{\emph{--UNKNOWN--}} 226 | \fi 227 | 228 | %\lhead{\leftmark} 229 | %\rhead{\rightmark} 230 | \fancyhead[LE]{\leftmark} 231 | \fancyhead[RO]{\rightmark} 232 | 233 | \newcommand{\PageNumber}{Page \thepage\ of \pageref*{LastPage}} 234 | %\rfoot{Page \thepage\ of \pageref{LastPage}} 235 | %\lfoot{\MyFoot} 236 | 237 | \fancyfoot[LE,RO]{\PageNumber} 238 | \fancyfoot[RE,LO]{\MyFoot} 239 | 240 | 241 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 242 | % override the plain page style so the first page of a 243 | % chapter still has a footer on it (but no header). 244 | 245 | \fancypagestyle{plain}{% 246 | \renewcommand{\headrulewidth}{0pt} % 247 | \fancyhf{} % clear all header and footer fields 248 | \fancyfoot[LE,RO]{\PageNumber} 249 | \fancyfoot[RE,LO]{\MyFoot} 250 | %\lfoot{\MyFoot} % 251 | %\rfoot{Page \thepage\ of \pageref*{LastPage}} 252 | } 253 | 254 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 255 | 256 | \setlength{\parindent}{0pt} 257 | \setlength{\parskip}{.51em} 258 | 259 | % How deep should we enumerate the section/subsection/subsubsections 260 | % 3=all the way 261 | \setcounter{secnumdepth}{3} 262 | 263 | % How many section-levels to show in the TOC. 264 | % 4=all of them 265 | %\setcounter{tocdepth}{4} 266 | \setcounter{tocdepth}{1} 267 | 268 | 269 | 270 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 271 | % Presentation styles for things like names links and 272 | % window objects in figures. 273 | 274 | % how should we present a window name 275 | \newcommand{\windowname}[1]{{\em #1}} 276 | 277 | % How should we present the name of an object in a figure 278 | % that can be interacted with. 279 | \newcommand{\linkname}[1]{{\bf #1}} 280 | 281 | 282 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 283 | % fix some annoying things 284 | 285 | \newcommand{\tm}{\textsuperscript{TM}} 286 | \newcommand{\rtm}{\textsuperscript{\textregistered}} 287 | 288 | 289 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 290 | % A command to make a colored background box whilst in math mode: 291 | \newcommand{\MathHilight}[1]{\colorbox{yellow}{\ensuremath{#1}}} 292 | 293 | \usepackage{tcolorbox} 294 | %\tcbset{colback=blue!20!white} 295 | \tcbset{colback=green!20!white} 296 | 297 | -------------------------------------------------------------------------------- /book/insnsummary/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Instruction Set Summary} 2 | 3 | \enote{Once the RV32I section is re-factored, it may end up turning into this.} 4 | 5 | \TDrawInsnTypeUPicture 6 | {Load Upper Immediate} 7 | {lui rd, imm} 8 | {lui t0, 3} 9 | {\tt% 10 | rd $\leftarrow$ pc + sx(imm<<1)\\ 11 | pc $\leftarrow$ pc + 4} 12 | {00000000000000000011001010110111} 13 | 14 | \TDrawInsnTypeUPicture 15 | {Add Upper Immediate PC} 16 | {auipc rd, imm} 17 | {auipc t0, 3} 18 | {\tt% 19 | rd $\leftarrow$ pc + zr(imm)\\ 20 | pc $\leftarrow$ pc + 4} 21 | {000000000000000000110010101xxxxx} 22 | 23 | \TDrawInsnTypeJPicture 24 | {Jump And Link} 25 | {jal rd, imm} 26 | {jal x7, .+16} 27 | {\tt% 28 | rd $\leftarrow$ pc + 4\\ 29 | pc $\leftarrow$ pc + sx(imm<<1)} 30 | {00000001000000000000001111101111} 31 | 32 | \TDrawInsnTypeIPicture 33 | {Jump And Link Register} 34 | {jalr rd, rs1, imm} 35 | {jalr x1, x7, 4} 36 | {\tt% 37 | rd $\leftarrow$ pc + 4\\ 38 | pc $\leftarrow$ (rs1 + sx(imm)) \& \textasciitilde{}1} 39 | {00000000010000111000000011100111} 40 | 41 | \enote{These branches (and likely other insns) are not encoded properly!} 42 | \TDrawInsnTypeBPicture 43 | {Branch Equal} 44 | {beq rs1, rs2, imm} 45 | {beq x3, x15, 2064} 46 | {\tt pc $\leftarrow$ (rs1==rs2) ? pc+sx(imm[12:1]<<1) : pc+4} 47 | {00000000111100011000100011100011} 48 | 49 | \TDrawInsnTypeBPicture 50 | {Branch Not Equal} 51 | {bne rs1, rs2, imm} 52 | {bne x3, x15, 2064} 53 | {\tt pc $\leftarrow$ (rs1!=rs2) ? pc+sx(imm[12:1]<<1) : pc+4} 54 | {00000000111100011001100011100011} 55 | 56 | \TDrawInsnTypeBPicture 57 | {Branch Less Than} 58 | {blt rs1, rs2, imm} 59 | {blt x3, x15, 2064} 60 | {\tt pc $\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4} 68 | {00000000111100011101100011100011} 69 | 70 | \TDrawInsnTypeBPicture 71 | {Branch Less Than Unsigned} 72 | {bltu rs1, rs2, imm} 73 | {bltu x3, x15, 2064} 74 | {\tt pc $\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4} 82 | {00000000111100011111100011100011} 83 | 84 | \TDrawInsnTypeIPicture 85 | {Load Byte} 86 | {lb rd, imm(rs1)} 87 | {lb x7, 4(x3)} 88 | {\tt% 89 | rd $\leftarrow$ sx(m8(rs1+sx(imm)))\\ 90 | pc $\leftarrow$ pc+4} 91 | {00000000010000011000001110000011} 92 | 93 | \TDrawInsnTypeIPicture 94 | {Load Halfword} 95 | {lh rd, imm(rs1)} 96 | {lh x7, 4(x3)} 97 | {\tt% 98 | rd $\leftarrow$ sx(m16(rs1+sx(imm)))\\ 99 | pc $\leftarrow$ pc+4} 100 | {00000000010000011001001110000011} 101 | 102 | \TDrawInsnTypeIPicture 103 | {Load Word} 104 | {lw rd, imm(rs1)} 105 | {lw x7, 4(x3)} 106 | {\tt% 107 | rd $\leftarrow$ sx(m32(rs1+sx(imm)))\\ 108 | pc $\leftarrow$ pc+4} 109 | {00000000010000011010001110000011} 110 | 111 | \TDrawInsnTypeIPicture 112 | {Load Byte Unsigned} 113 | {lbu rd, imm(rs1)} 114 | {lbu x7, 4(x3)} 115 | {\tt% 116 | rd $\leftarrow$ zx(m8(rs1+sx(imm)))\\ 117 | pc $\leftarrow$ pc+4} 118 | {00000000010000011100001110000011} 119 | 120 | \TDrawInsnTypeIPicture 121 | {Load Halfword Unsigned} 122 | {lhu rd, imm(rs1)} 123 | {lhu x7, 4(x3)} 124 | {\tt% 125 | rd $\leftarrow$ zx(m16(rs1+sx(imm)))\\ 126 | pc $\leftarrow$ pc+4} 127 | {00000000010000011101001110000011} 128 | 129 | \TDrawInsnTypeSPicture 130 | {Store Byte} 131 | {sb rs2, imm(rs1)} 132 | {sb x3, 19(x15)} 133 | {\tt% 134 | m8(rs1+sx(imm)) $\leftarrow$ rs2[7:0]\\ 135 | pc $\leftarrow$ pc+4} 136 | {00000000111100011000100110100011} 137 | 138 | \TDrawInsnTypeSPicture 139 | {Store Halfword} 140 | {sh rs2, imm(rs1)} 141 | {sh x3, 19(x15)} 142 | {\tt% 143 | m16(rs1+sx(imm)) $\leftarrow$ rs2[15:0]\\ 144 | pc $\leftarrow$ pc+4} 145 | {00000000111100011001100110100011} 146 | 147 | \TDrawInsnTypeSPicture 148 | {Store Word} 149 | {sw rs2, imm(rs1)} 150 | {sw x3, 19(x15)} 151 | {\tt% 152 | m16(rs1+sx(imm)) $\leftarrow$ rs2[31:0]\\ 153 | pc $\leftarrow$ pc+4} 154 | {00000000111100011010100110100011} 155 | 156 | \TDrawInsnTypeIPicture 157 | {Add Immediate} 158 | {addi rd, rs1, imm} 159 | {addi x1, x7, 4} 160 | {\tt% 161 | rd $\leftarrow$ rs1+sx(imm)\\ 162 | pc $\leftarrow$ pc+4} 163 | {00000000010000111000000010010011} 164 | 165 | \TDrawInsnTypeIPicture 166 | {Set Less Than Immediate} 167 | {slti rd, rs1, imm} 168 | {slti x1, x7, 4} 169 | {\tt% 170 | rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\ 171 | pc $\leftarrow$ pc+4} 172 | {00000000010000111010000010010011} 173 | 174 | \TDrawInsnTypeIPicture 175 | {Set Less Than Immediate Unsigned} 176 | {sltiu rd, rs1, imm} 177 | {sltiu x1, x7, 4} 178 | {\tt% 179 | rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\ 180 | pc $\leftarrow$ pc+4} 181 | {00000000010000111011000010010011} 182 | 183 | \TDrawInsnTypeIPicture 184 | {Exclusive Or Immediate} 185 | {xori rd, rs1, imm} 186 | {xori x1, x7, 4} 187 | {\tt% 188 | rd $\leftarrow$ rs1 \^{} sx(imm)\\ 189 | pc $\leftarrow$ pc+4} 190 | {00000000010000111100000010010011} 191 | 192 | \TDrawInsnTypeIPicture 193 | {Or Immediate} 194 | {ori rd, rs1, imm} 195 | {ori x1, x7, 4} 196 | {\tt% 197 | rd $\leftarrow$ rs1 | sx(imm)\\ 198 | pc $\leftarrow$ pc+4} 199 | {00000000010000111110000010010011} 200 | 201 | \TDrawInsnTypeIPicture 202 | {And Immediate} 203 | {andi rd, rs1, imm} 204 | {andi x1, x7, 4} 205 | {\tt% 206 | rd $\leftarrow$ rs1 \& sx(imm)\\ 207 | pc $\leftarrow$ pc+4} 208 | {00000000010000111111000010010011} 209 | 210 | 211 | \TDrawInsnTypeRShiftPicture 212 | {Shift Left Logical Immediate} 213 | {slli rd, rs1, shamt} 214 | {slli x7, x3, 2} 215 | {\tt% 216 | rd $\leftarrow$ rs1 << shamt\\ 217 | pc $\leftarrow$ pc+4} 218 | {00000000001000011001001110100011} 219 | 220 | 221 | \TDrawInsnTypeRShiftPicture 222 | {Shift Right Logical Immediate} 223 | {srli rd, rs1, shamt} 224 | {srli x7, x3, 2} 225 | {\tt% 226 | rd $\leftarrow$ rs1 >> shamt\\ 227 | pc $\leftarrow$ pc+4} 228 | {00000000001000011101001110010011} 229 | 230 | \TDrawInsnTypeRShiftPicture 231 | {Shift Right Arithmetic Immediate} 232 | {srai rd, rs1, shamt} 233 | {srai x7, x3, 2} 234 | {\tt% 235 | rd $\leftarrow$ rs1 >> shamt\\ 236 | pc $\leftarrow$ pc+4} 237 | {01000000001000011101001110010011} 238 | 239 | \TDrawInsnTypeRPicture 240 | {Add} 241 | {add rd, rs1, rs2} 242 | {add x7, x3, x31} 243 | {\tt% 244 | rd $\leftarrow$ rs1 + rs2\\ 245 | pc $\leftarrow$ pc+4} 246 | {00000001111100011000001110110011} 247 | 248 | \TDrawInsnTypeRPicture 249 | {Subtract} 250 | {sub rd, rs1, rs2} 251 | {SUB x7, x3, x31} 252 | {\tt% 253 | rd $\leftarrow$ rs1 - rs2\\ 254 | pc $\leftarrow$ pc+4} 255 | {01000001111100011000001110110011} 256 | 257 | \TDrawInsnTypeRPicture 258 | {Shift Left Logical} 259 | {sll rd, rs1, rs2} 260 | {sll x7, x3, x31} 261 | {\tt% 262 | rd $\leftarrow$ rs1 << rs2\\ 263 | pc $\leftarrow$ pc+4} 264 | {00000001111100011001001110110011} 265 | 266 | \TDrawInsnTypeRPicture 267 | {Set Less Than} 268 | {slt rd, rs1, rs2} 269 | {slt x7, x3, x31} 270 | {\tt% 271 | rd $\leftarrow$ rs1 < rs2) ? 1 : 0\\ 272 | pc $\leftarrow$ pc+4} 273 | {00000001111100011010001110110011} 274 | 275 | \TDrawInsnTypeRPicture 276 | {Set Less Than Unsigned} 277 | {sltu rd, rs1, rs2} 278 | {sltu x7, x3, x31} 279 | {\tt% 280 | rd $\leftarrow$ (rs1 < rs2) ? 1 : 0\\ 281 | pc $\leftarrow$ pc+4} 282 | {00000001111100011011001110110011} 283 | 284 | \TDrawInsnTypeRPicture 285 | {Exclusive Or} 286 | {xor rd, rs1, rs2} 287 | {xor x7, x3, x31} 288 | {\tt% 289 | rd $\leftarrow$ rs1 \^{} rs2\\ 290 | pc $\leftarrow$ pc+4} 291 | {00000001111100011100001110110011} 292 | 293 | \TDrawInsnTypeRPicture 294 | {Shift Right Logical} 295 | {srl rd, rs1, rs2} 296 | {srl x7, x3, x31} 297 | {\tt% 298 | rd $\leftarrow$ rs1 >> rs2\\ 299 | pc $\leftarrow$ pc+4} 300 | {00000001111100011101001110110011} 301 | 302 | \TDrawInsnTypeRPicture 303 | {Shift Right Arithmetic} 304 | {sra rd, rs1, rs2} 305 | {sra x7, x3, x31} 306 | {\tt% 307 | rd $\leftarrow$ rs1 >> rs2\\ 308 | pc $\leftarrow$ pc+4} 309 | {01000001111100011101001110110011} 310 | 311 | \TDrawInsnTypeRPicture 312 | {Or} 313 | {or rd, rs1, rs2} 314 | {or x7, x3, x31} 315 | {\tt% 316 | rd $\leftarrow$ rs1 | rs2\\ 317 | pc $\leftarrow$ pc+4} 318 | {00000001111100011101001110110011} 319 | 320 | \TDrawInsnTypeRPicture 321 | {And} 322 | {and rd, rs1, rs2} 323 | {and x7, x3, x31} 324 | {\tt% 325 | rd $\leftarrow$ rs1 \& rs2\\ 326 | pc $\leftarrow$ pc+4} 327 | {00000001111100011110001110110011} 328 | 329 | %\DrawInsnTypeFPicture{FENCE iorw, iorw}{00001111111100000000000000001111} 330 | %\DrawInsnTypeFPicture{FENCE.I}{00000000000000000001000000001111} 331 | %\DrawInsnTypeEPicture{ECALL}{00000000000000000000000001110011} 332 | %\DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011} 333 | %\DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011} 334 | %\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011} 335 | %\DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011} 336 | %\DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011} 337 | %\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011} 338 | %\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011} 339 | %\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011} 340 | %\DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011} 341 | %\DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011} 342 | %\DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011} 343 | %\DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011} 344 | %\DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011} 345 | %\DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011} 346 | %\DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011} 347 | -------------------------------------------------------------------------------- /book/refcard/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{RV32I Reference Cards}% 2 | \nolinenumbers% 3 | \vspace{-1cm} 4 | {\small% 5 | \begin{tabular}{|ll|c|l|l|} 6 | \hline 7 | \multicolumn{2}{|c|}{Usage Template} & Type & Description & Detailed Description \\ 8 | \hline 9 | \hline 10 | add & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:add]{Add} & {\tt rd $\leftarrow$ rs1 + rs2, pc $\leftarrow$ pc+4}\\ 11 | \hline 12 | addi & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:addi]{Add Immediate} & {\tt rd $\leftarrow$ rs1 + \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\ 13 | \hline 14 | and & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:and]{And} & {\tt rd $\leftarrow$ rs1 $\land$ rs2, pc $\leftarrow$ pc+4}\\ 15 | \hline 16 | andi & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:andi]{And Immediate} & {\tt rd $\leftarrow$ rs1 $\land$ \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\ 17 | \hline 18 | auipc & rd, imm & \hyperref[insnformat:utype]{U} & \hyperref[insn:auipc]{Add Upper Immediate to PC} & {\tt rd $\leftarrow$ pc + \hyperref[imm.u:decode]{imm\_u}, pc $\leftarrow$ pc+4}\\ 19 | \hline 20 | beq & rs1, rs2, \hyperref[pcrel.13]{pcrel\_13} & \hyperref[insnformat:btype]{B} & \hyperref[insn:beq]{Branch Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1==rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\ 21 | \hline 22 | bge & rs1, rs2, \hyperref[pcrel.13]{pcrel\_13} & \hyperref[insnformat:btype]{B} & \hyperref[insn:bge]{Branch Greater or Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1>=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\ 23 | \hline 24 | bgeu & rs1, rs2, \hyperref[pcrel.13]{pcrel\_13} & \hyperref[insnformat:btype]{B} & \hyperref[insn:bgeu]{Branch Greater or Equal Unsigned} & {\tt pc $\leftarrow$ pc + (\verb@(rs1>=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\ 25 | \hline 26 | blt & rs1, rs2, \hyperref[pcrel.13]{pcrel\_13} & \hyperref[insnformat:btype]{B} & \hyperref[insn:blt]{Branch Less Than} & {\tt pc $\leftarrow$ pc + (\verb@(rs1> (rs2\%\hyperref[XLEN]{XLEN}), pc $\leftarrow$ pc+4}\\ 85 | \hline 86 | srai & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srai]{Shift Right Arithmetic Immediate} & {\tt rd $\leftarrow$ rs1 >> \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\ 87 | \hline 88 | srl & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:srl]{Shift Right Logical} & {\tt rd $\leftarrow$ rs1 >> (rs2\%\hyperref[XLEN]{XLEN}), pc $\leftarrow$ pc+4}\\ 89 | \hline 90 | srli & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srli]{Shift Right Logical Immediate} & {\tt rd $\leftarrow$ rs1 >> \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\ 91 | \hline 92 | sub & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sub]{Subtract} & {\tt rd $\leftarrow$ rs1 - rs2, pc $\leftarrow$ pc+4}\\ 93 | \hline 94 | sw & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sw]{Store Word} & {\tt \hyperref[memory:m32]{m32}(rs1+\hyperref[imm.s:decode]{imm\_s}) $\leftarrow$ rs2[31:0], pc $\leftarrow$ pc+4}\\ 95 | \hline 96 | xor & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:xor]{Exclusive Or} & {\tt rd $\leftarrow$ rs1 $\oplus$ rs2, pc $\leftarrow$ pc+4}\\ 97 | \hline 98 | xori & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:xori]{Exclusive Or Immediate} & {\tt rd $\leftarrow$ rs1 $\oplus$ \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\ 99 | \hline 100 | \end{tabular} 101 | }% 102 | \newpage 103 | {\Large RV32I Base Instruction Set Encoding}~\cite[p.~104]{rvismv1v22:2017} 104 | 105 | %\DrawAllInsnTypes 106 | \DrawAllInsnOps 107 | \newpage% 108 | \thispagestyle{empty}% 109 | %\newgeometry{left=1.3in,width=8.1in,height=13in,top=1in,bottom=0in}% 110 | \newgeometry{left=0in,width=8in,height=10.5in,vmargin=0in,hmargin=0in,layouthoffset=1.35in,layoutvoffset=1in}% 111 | %\resizebox{8in}{!}{\rotatebox{90}{\DrawAllInsnOps}} 112 | %\resizebox{8in}{!}{\rotatebox{90}{\DrawGCAllInsnOps}} 113 | \resizebox{8in}{10.7in}{\rotatebox{90}{\DrawGCAllInsnOps}} 114 | 115 | \newpage% 116 | \thispagestyle{empty}% 117 | \resizebox{8in}{!}{ 118 | \rotatebox{-90}{ 119 | \DrawInsnRibbons 120 | } 121 | } 122 | \restoregeometry 123 | -------------------------------------------------------------------------------- /book/float/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Floating Point Numbers} 2 | \label{chapter:floatingpoint} 3 | 4 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 5 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 6 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 7 | \section{IEEE-754 Floating Point Number Representation} 8 | \label{chapter::floatingpoint} 9 | 10 | This section provides an overview of the IEEE-754 32-bit binary floating 11 | point format.\cite{ieee:754} 12 | 13 | \begin{itemize} 14 | \item Recall that the place values for integer binary numbers are: 15 | \begin{verbatim} 16 | ... 128 64 32 16 8 4 2 1 17 | \end{verbatim} 18 | \item We can extend this to the right in binary similar to the way we do for 19 | decimal numbers: 20 | \begin{verbatim} 21 | ... 128 64 32 16 8 4 2 1 . 1/2 1/4 1/8 1/16 1/32 1/64 1/128 ... 22 | \end{verbatim} 23 | The `.' in a binary number is a binary point, not a decimal point. 24 | 25 | \item We use scientific notation as in $2.7 \times 10^{-47}$ to express either 26 | small fractions or large numbers when we are not concerned every last digit 27 | needed to represent the entire, exact, value of a number. 28 | 29 | \item The format of a number in scientific notation is $mantissa \times base^{exponent}$ 30 | 31 | \item In binary we have $mantissa \times 2^{exponent}$ 32 | 33 | \item IEEE-754 format requires binary numbers to be {\em normalized} to 34 | $1.significand \times 2^{exponent}$ where the {\em significand} 35 | is the portion of the {\em mantissa} that is to the right of the binary-point. 36 | 37 | \begin{itemize} 38 | \item The unnormalized binary value of $-2.625$ is $-10.101$ 39 | \item The normalized value of $-2.625$ is $-1.0101 \times 2^1$ 40 | \end{itemize} 41 | 42 | \item We need not store the `1.' part because {\em all} normalized floating 43 | point numbers will start that way. Thus we can save memory when storing 44 | normalized values by inserting a `1.' to the left of significand. 45 | 46 | 47 | 48 | \DrawBitBoxIEEEFloat{11000000001010000000000000000000} 49 | 50 | 51 | %{ 52 | %\small 53 | %\setlength{\unitlength}{.15in} 54 | %\begin{picture}(32,4)(0,0) 55 | % \put(0,1){\line(1,0){32}} % bottom line 56 | % \put(0,2){\line(1,0){32}} % top line 57 | % 58 | % \put(0,1){\line(0,1){2}} % left vertical 59 | % \put(0,2){\makebox(1,1){\tiny 31}} % left end bit number marker 60 | % 61 | % \put(32,1){\line(0,1){2}} % vertical right end 62 | % \put(31,2){\makebox(1,1){\tiny 0}} % right end bit number marker 63 | % 64 | % \put(0,0){\makebox(1,1){\small sign}} 65 | % \put(1,0){\makebox(8,1){\small exponent}} 66 | % \put(9,0){\makebox(23,1){\small significand}} 67 | % 68 | % \put(0,1){\makebox(1,1){1}} % sign 69 | % 70 | % \put(1,1){\line(0,1){2}} % seperator 71 | % \put(1,2){\makebox(1,1){\tiny 30}} % bit marker 72 | % 73 | % \put(1,1){\makebox(1,1){1}} % exponent 74 | % \put(2,1){\makebox(1,1){0}} 75 | % \put(3,1){\makebox(1,1){0}} 76 | % \put(4,1){\makebox(1,1){0}} 77 | % \put(5,1){\makebox(1,1){0}} 78 | % \put(6,1){\makebox(1,1){0}} 79 | % \put(7,1){\makebox(1,1){0}} 80 | % \put(8,1){\makebox(1,1){0}} 81 | % 82 | % \put(8,2){\makebox(1,1){\tiny 23}} % bit marker 83 | % \put(9,1){\line(0,1){2}} % seperator 84 | % \put(9,2){\makebox(1,1){\tiny 22}} % bit marker 85 | % 86 | % \put(9,1){\makebox(1,1){0}} 87 | % \put(10,1){\makebox(1,1){1}} 88 | % \put(11,1){\makebox(1,1){0}} 89 | % \put(12,1){\makebox(1,1){1}} 90 | % \put(13,1){\makebox(1,1){0}} 91 | % \put(14,1){\makebox(1,1){0}} 92 | % \put(15,1){\makebox(1,1){0}} 93 | % \put(16,1){\makebox(1,1){0}} 94 | % \put(17,1){\makebox(1,1){0}} 95 | % \put(18,1){\makebox(1,1){0}} 96 | % \put(19,1){\makebox(1,1){0}} 97 | % \put(20,1){\makebox(1,1){0}} 98 | % \put(21,1){\makebox(1,1){0}} 99 | % \put(22,1){\makebox(1,1){0}} 100 | % \put(23,1){\makebox(1,1){0}} 101 | % \put(24,1){\makebox(1,1){0}} 102 | % \put(25,1){\makebox(1,1){0}} 103 | % \put(26,1){\makebox(1,1){0}} 104 | % \put(27,1){\makebox(1,1){0}} 105 | % \put(28,1){\makebox(1,1){0}} 106 | % \put(29,1){\makebox(1,1){0}} 107 | % \put(30,1){\makebox(1,1){0}} 108 | % \put(31,1){\makebox(1,1){0}} 109 | %\end{picture} 110 | %} 111 | 112 | %\item $-((1 + \frac{1}{4} + \frac{1}{16}) \times 2^{128-127}) = -(1 \frac{5}{16} \times 2^{1}) = -(1.3125 \times 2^{1}) = -2.625$ 113 | \item $-((1 + \frac{1}{4} + \frac{1}{16}) \times 2^{128-127}) = -((1 + \frac{1}{4} + \frac{1}{16}) \times 2^1) = -(2 + \frac{1}{2} + \frac{1}{8}) = -(2 + .5 + .125) = -2.625$ 114 | 115 | \item IEEE-754 formats: 116 | 117 | \begin{tabular}{|l|l|l|} 118 | \hline 119 | & IEEE-754 32-bit & IEEE-754 64-bit \\ 120 | \hline 121 | sign & 1 bit & 1 bit \\ 122 | exponent & 8 bits (excess-127) & 11 bits (excess-1023) \\ 123 | mantissa & 23 bits & 52 bits \\ 124 | max exponent & 127 & 1023 \\ 125 | min exponent & -126 & -1022 \\ 126 | \hline 127 | \end{tabular} 128 | 129 | \item When the exponent is all ones, the significand is all zeros, and 130 | the sign is zero, the number represents positive infinity. 131 | 132 | \item When the exponent is all ones, the significand is all zeros, and 133 | the sign is one, the number represents negative infinity. 134 | 135 | \item Observe that the binary representation of a pair of IEEE-754 numbers 136 | (when one or both are positive) can be compared for magnitude 137 | by treating them as if they are two's complement signed integers. 138 | This is because an IEEE number is stored in {\em signed magnitude} format and 139 | therefore positive floating point values will grow upward and downward in the 140 | same fashion as for unsigned integers and that since negative floating point 141 | values will have its MSB set, they will `appear` to be less than a positive 142 | floating point value. 143 | 144 | When comparing two negative IEEE float values by treating them both as two's 145 | complement signed integers, the order will be reversed because IEEE float values 146 | with larger (that is, increasingly negative) magnitudes will appear to decrease 147 | in value when interpreted as signed integers. 148 | 149 | This works this way because excess notation is used in the format of the 150 | exponent and why the significand's sign bit is located on the left of 151 | the exponent.\footnote{I know this is true and was done on purpose because 152 | Bill Cody, chairman of IEEE committee P754 that designed the IEEE-754 standard, 153 | told me so personally circa 1991.} 154 | 155 | \item Note that zero is a special case number. Recall that a normalized 156 | number has an implied 1-bit to the left of the significand\ldots\ which 157 | means that there is no way to represent zero! 158 | Zero is represented by an exponent of all-zeros and a significand of 159 | all-zeros. This definition allows for a positive and a negative zero 160 | if we observe that the sign can be either 1 or 0. 161 | 162 | \item On the number-line, numbers between zero and the smallest fraction in 163 | either direction are in the {\em \gls{underflow}} areas. 164 | \enote{Need to add the standard lecture number-line diagram showing 165 | where the over/under-flow areas are and why.} 166 | 167 | \item On the number line, numbers greater than the mantissa of all-ones and the 168 | largest exponent allowed are in the {\em \gls{overflow}} areas. 169 | 170 | \item Note that numbers have a higher resolution on the number line when the 171 | exponent is smaller. 172 | 173 | \item The largest and smallest possible exponent values are reserved to represent 174 | things requiring special cases. For example, the infinities, values representing 175 | ``not a number'' (such as the result of dividing by zero), and for a way to represent 176 | values that are not normalized. For more information on special cases see \cite{ieee:754}. 177 | 178 | \end{itemize} 179 | 180 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 181 | \subsection{Floating Point Number Accuracy} 182 | Due to the finite number of bits used to store the value of a floating point 183 | number, it is not possible to represent every one of the infinite values 184 | on the real number line. The following C programs illustrate this point. 185 | 186 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 187 | \subsubsection{Powers Of Two} 188 | Just like the integer numbers, the powers of two that have bits to represent 189 | them can be represented perfectly\ldots\ as can their sums (provided that the 190 | significand requires no more than 23 bits.) 191 | 192 | \listing{powersoftwo.c}{Precise Powers of Two} 193 | \listing{powersoftwo.out}{Output from {\tt powersoftwo.c}} 194 | 195 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 196 | \subsubsection{Clean Decimal Numbers} 197 | When dealing with decimal values, you will find that they don't map simply 198 | into binary floating point values. 199 | % (the same holds true for binary integer numbers). 200 | 201 | Note how the decimal numbers are not accurately represented as they get larger. 202 | The decimal number on line 10 of \listingRef{cleandecimal.out} 203 | can be perfectly represented in IEEE format. However, a problem arises in 204 | the 11Th loop iteration. It is due to the fact that the 205 | binary number can not be represented accurately in IEEE format. Its least 206 | significant bits were truncated in a best-effort attempt at rounding the value 207 | off in order to fit the value into the bits provided. This is an example of 208 | {\em low order truncation}. Once this happens, the value of \verb@x.f@ is 209 | no longer as precise as it could be given more bits in which to save its value. 210 | 211 | \listing{cleandecimal.c}{Print Clean Decimal Numbers} 212 | \listing{cleandecimal.out}{Output from {\tt cleandecimal.c}} 213 | 214 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 215 | \subsubsection{Accumulation of Error} 216 | These rounding errors can be exaggerated when the number we multiply 217 | the \verb@x.f@ value by is, itself, something that can not be accurately 218 | represented in IEEE 219 | form.\footnote{Applications requiring accurate decimal values, such as 220 | financial accounting systems, can use a packed-decimal numeric format 221 | to avoid unexpected oddities caused by the use of binary numbers.} 222 | \enote{In a lecture one would show that one tenth is a repeating 223 | non-terminating binary number that gets truncated. This discussion 224 | should be reproduced here in text form.} 225 | 226 | For example, if we multiply our \verb@x.f@ value by $\frac{1}{10}$ each time, 227 | we can never be accurate and we start accumulating errors immediately. 228 | 229 | \listing{erroraccumulation.c}{Accumulation of Error} 230 | \listing{erroraccumulation.out}{Output from {\tt erroraccumulation.c}} 231 | 232 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 233 | \subsection{Reducing Error Accumulation} 234 | In order to use floating point numbers in a program without causing 235 | excessive rounding problems an algorithm can be redesigned such that the 236 | accumulation is eliminated. 237 | This example is similar to the previous one, but this time we recalculate the 238 | desired value from a known-accurate integer value. 239 | Some rounding errors remain present, but they can not accumulate. 240 | 241 | \listing{errorcompensation.c}{Accumulation of Error} 242 | \listing{errorcompensation.out}{Output from {\tt erroraccumulation.c}} 243 | -------------------------------------------------------------------------------- /book/intro/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Introduction} 2 | \label{chapter:Introduction} 3 | 4 | At its core, a digital computer has at least one \acrfull{cpu}. A 5 | CPU executes a continuous stream of instructions called a \gls{program}. 6 | These program instructions are expressed in what is called 7 | \gls{MachineLanguage}. Each machine language instruction is a \gls{binary} value. 8 | In order to provide a method to simplify the management of machine language 9 | programs a symbolic mapping is provided where a \gls{mnemonic} can be used to 10 | specify each machine instruction and any of its parameters\ldots\ rather 11 | than require that programs be expressed as a series of binary values. 12 | A set of mnemonics, parameters and rules for specifying their use for 13 | the purpose of programming a CPU is called an {\em Assembly Language}. 14 | 15 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 16 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 17 | \section{The Digital Computer} 18 | 19 | There are different types of computers. A {\em digital} computer is 20 | the type that most people think of when they hear the word {\em computer}. 21 | Other varieties of computers include {\em analog} and {\em quantum}. 22 | 23 | A digital computer is one that processes data represented 24 | using numeric values (digits), most commonly expressed in binary 25 | (ones and zeros) form. 26 | 27 | This text focuses on digital computing. 28 | 29 | A typical digital computer is composed of storage systems (memory, disc 30 | drives, USB drives, etc.), a CPU (with one or more cores), input peripherals 31 | (a keyboard and mouse) and output peripherals (display, printer or speakers.) 32 | 33 | \subsection{Storage Systems} 34 | 35 | Computer storage systems are used to hold the data and instructions 36 | for the CPU. 37 | 38 | Types of computer storage can be classified into two categories: 39 | {\em volatile} and {\em non-volatile}. 40 | 41 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 42 | \subsubsection{Volatile Storage} 43 | \label{VolatileStorage} 44 | 45 | Volatile storage is characterized by the fact that it will lose its 46 | contents (forget) any time that it is powered off. 47 | 48 | \index{register} 49 | One type of volatile storage is provided inside the CPU itself in 50 | small blocks called \glspl{register}. These registers are used to 51 | hold individual data values that can be manipulated by the instructions 52 | that are executed by the CPU. 53 | 54 | Another type of volatile storage is {\em main memory} 55 | (sometimes called \acrshort{ram}) 56 | Main memory is connected to a computer's CPU and is used to hold 57 | the data and instructions that can not fit into the CPU registers. 58 | 59 | Typically, a CPU's registers can hold tens of data values while 60 | the main memory can contain many billions of data values. 61 | 62 | To keep track of the data values, each register is assigned a number and 63 | the main memory is broken up into small blocks called \gls{byte}s that 64 | each assigned a number called an \gls{address} 65 | (an {\em address} is often referred to as a {\em location.} 66 | 67 | A CPU can process data in a register at a speed that can be an order 68 | of magnitude faster than the rate that it can process (specifically, 69 | transfer data and instructions to and from) the main memory. 70 | 71 | Register storage costs an order of magnitude more to manufacture than 72 | main memory. While it is desirable to have many registers, the economics 73 | dictate that the vast majority of volatile computer storage be provided 74 | in its main memory. As a result, optimizing the copying of data between 75 | the registers and main memory is a desirable trait of good programs. 76 | 77 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 78 | \subsubsection{Non-Volatile Storage} 79 | 80 | Non-volatile storage is characterized by the fact that it will {\em NOT} 81 | lose its contents when it is powered off. 82 | 83 | Common types of non-volatile storage are disc drives, 84 | \acrshort{rom} flash cards and USB 85 | drives. Prices can vary widely depending on size and transfer speeds. 86 | 87 | It is typical for a computer system's non-volatile storage to operate 88 | more slowly than its main memory. 89 | 90 | This text will focus on volatile storage. 91 | %is not particularly concerned with non-volatile storage. 92 | 93 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 94 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 95 | \subsection{CPU} 96 | \index{CPU} 97 | 98 | \enote{Add a block diagram of the CPU components described here.} 99 | The \acrshort{cpu} is a collection of registers and circuitry designed to 100 | manipulate the register data and to exchange data and instructions with the 101 | main memory. The instructions that are read from the main memory tell 102 | the CPU to perform various mathematical and logical operations on the data 103 | in its registers and where to save the results of those operations. 104 | 105 | \subsubsection{Execution Unit} 106 | 107 | The part of a CPU that coordinates all aspects of the operations of each 108 | instruction is called the {\em execution unit.} It is what performs the transfers 109 | of instructions and data between the CPU and the main memory and tells the 110 | registers when they are supposed to either store or recall data being transferred. 111 | The execution unit also controls the ALU (Arithmetic and Logic Unit). 112 | 113 | \subsubsection{Arithmetic and Logic Unit} 114 | \index{ALU} 115 | 116 | When an instruction manipulates data by performing things like an {\em addition}, 117 | {\em subtraction}, {\em comparison} or other similar operations , the ALU is what 118 | will calculate the sum, difference, and so on\ldots\ under the control of the 119 | execution unit. 120 | 121 | 122 | 123 | \subsubsection{Registers} 124 | \index{register} 125 | 126 | In the RV32 CPU there are 31 general purpose registers that each contain 32 \gls{bit}s 127 | (where each bit is one \gls{binary} digit value of one or zero) and a number 128 | of special-purpose registers. 129 | Each of the general purpose registers is given a name such as \reg{x1}, \reg{x2}, 130 | \ldots\ on up to \reg{x31} ({\em general purpose} refers to the fact that the 131 | {\em CPU itself} does not prescribe any particular function to any of these registers.) 132 | Two important special-purpose registers are \reg{x0} and \reg{pc}. 133 | 134 | Register \reg{x0} will always represent the value zero or logical {\em false} 135 | no matter what. If any instruction tries to change the value in \reg{x0} the 136 | operation will fail. The need for {\em zero} is so common that, other than the 137 | fact that it is hard-wired to zero, the \reg{x0} register is made available as 138 | if it were otherwise a general purpose register.% 139 | \footnote{Having a special 140 | {\em zero} register allows the total set of instructions that the CPU can execute 141 | to be simplified. Thus reducing its complexity, power consumption and cost.} 142 | 143 | The \reg{pc} register is called the {\em program counter}. The CPU uses it to 144 | remember the memory address where its program instructions are located. 145 | 146 | The term XLEN refer to the width of an integer register in bits (either 32, 64, or 128.) 147 | The number of bits in each register is defined by the \acrfull{isa}. 148 | 149 | \subsubsection{Harts} 150 | \index{hart} 151 | 152 | Analogous to a {\em core} in other types of CPUs, a {\em \acrshort{hart}} 153 | (hardware \gls{thread}) in a RISC-V CPU refers to the collection of 32 registers, 154 | instruction execution unit and ALU.\cite[p.~20]{rvismv1v22:2017} 155 | 156 | When more than one hart is present in a CPU, a different stream of instructions can 157 | be executed on each hart all at the same time. 158 | Programs that are written to take advantage of this are called {\em multithreaded}. 159 | 160 | This text will primarily focus on CPUs that have only one hart. 161 | 162 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 163 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 164 | \subsection{Peripherals} 165 | 166 | A {\em peripheral} is a device that is not a CPU or main memory. They are 167 | typically used to transfer information/data into and out of the 168 | main memory. 169 | 170 | This text is not concerned with the peripherals of a computer 171 | system other than in sections where instructions are discussed with the 172 | purpose of addressing the needs of a peripheral device. Such 173 | instructions are used to initiate, execute and/or synchronize data transfers. 174 | 175 | 176 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 177 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 178 | \section{Instruction Set Architecture} 179 | \index{ISA} 180 | 181 | The catalog of rules that describes the details of the instructions 182 | and features that a given CPU provides is called an \acrfull{isa}. 183 | 184 | An ISA is typically expressed in terms of the specific meaning of 185 | each binary instruction that a CPU can recognize and how it will 186 | process each one. 187 | 188 | The RISC-V ISA is defined as a set of modules. The purpose of 189 | dividing the ISA into modules is to allow an implementer to select which 190 | features to incorporate into a CPU design.\cite[p.~4]{rvismv1v22:2017} 191 | 192 | Any given RISC-V implementation must provide one of the {\em base} 193 | modules and zero or more of the {\em extension} modules.\cite[p.~4]{rvismv1v22:2017} 194 | 195 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 196 | \subsection{RV Base Modules} 197 | \index{RV32I} 198 | 199 | The base modules are RV32I (32-bit general purpose), 200 | RV32E (32-bit embedded), RV64I (64-bit general purpose) 201 | and RV128I (128-bit general purpose).\cite[p.~4]{rvismv1v22:2017} 202 | 203 | These base modules provide the minimal functional set of integer operations 204 | needed to execute a useful application. The differing bit-widths address 205 | the needs of different main-memory sizes. 206 | 207 | This text primarily focuses on the RV32I base module and how to program it. 208 | 209 | 210 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 211 | \subsection{Extension Modules} 212 | 213 | RISC-V extension modules may be included by an implementer interested 214 | in optimizing a design for one or more purposes.\cite[p.~4]{rvismv1v22:2017} 215 | 216 | \index{RV32M}% 217 | \index{RV32A}% 218 | \index{RV32F}% 219 | \index{RV32D}% 220 | \index{RV32Q}% 221 | \index{RV32C}% 222 | Available extension modules include M (integer math), A (atomic), 223 | F (32-bit floating point), D (64-bit floating point), 224 | Q (128-bit floating point), C (compressed size instructions) and others. 225 | 226 | \index{RV32G}% 227 | The extension name {\em G} is used to represent the combined set of IMAFD 228 | extensions as it is expected to be a common combination. 229 | 230 | 231 | 232 | 233 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 234 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 235 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 236 | \section{How the CPU Executes a Program} 237 | 238 | The process of executing a program is continuous repeats of a series of 239 | \index{instruction cycle}{\em instruction cycles} that are each comprised 240 | of a {\em fetch}, {\em decode} and {\em execute} phase. 241 | 242 | The current status of a CPU hart is entirely embodied in the data values that 243 | are stored in its registers at any moment in time. Of particular interest 244 | to an executing program is the \reg{pc} register. The \reg{pc} contains 245 | the memory address containing the instruction that the CPU is currently 246 | executing.\footnote{In the RISC-V ISA the \reg{pc} register points to the 247 | {\em current} instruction where in most other designs, the \reg{pc} 248 | register points to the {\em next} instruction.} 249 | 250 | For this to work, the instructions to be executed must have been previously 251 | stored in adjacent main memory locations and the address of the first instruction 252 | placed into the \reg{pc} register. 253 | 254 | 255 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 256 | \subsection{Instruction Fetch} 257 | \index{instruction fetch} 258 | 259 | In order to {\em fetch} an instruction from the main memory the CPU 260 | will update the address in the \reg{pc} register and then request that 261 | the main memory return the value of the data stored at that address. 262 | \footnote{RV32I instructions are more than one byte in size, but 263 | this general description is suitable for now.} 264 | 265 | %must have a method to identify which instruction should be fetched and 266 | %a method to fetch it. 267 | 268 | %Given that the main memory is broken up and that each of its bytes is 269 | %assigned an address, the \reg{pc} is used to hold the address of the 270 | %location where the next instruction to execute is located. 271 | 272 | %Given an instruction address, the CPU can request that the main memory 273 | %locate and return the value of the data stored there using what is called 274 | %a {\em memory read} operation and then the CPU can treat that {\em fetched} 275 | %value as an instruction and execute it. 276 | 277 | 278 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 279 | \subsection{Instruction Decode} 280 | \index{instruction decode} 281 | 282 | Once an instruction has been fetched, it must be inspected to determine what 283 | operation(s) are to be performed. This means inspecting the portions of the 284 | instruction that dictate which registers are involved and what that, if 285 | anything, ALU should do. 286 | 287 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 288 | \subsection{Instruction Execute} 289 | \index{instruction execute} 290 | 291 | Typical instructions do things like add a number to the value 292 | currently stored in one of the registers or store the contents of a 293 | register into the main memory at some given address. 294 | 295 | Part of every instruction is a notion of what should be done next. 296 | 297 | Most of the time an instruction will complete by indicating that 298 | the CPU should proceed to fetch and execute the instruction at the next 299 | larger main memory address. In these cases the \reg{pc} is incremented 300 | to point to the memory address after the current instruction. 301 | 302 | Any parameters that an instruction requires must either be part of 303 | the instruction itself or read from (or stored into) one or more of the 304 | general purpose registers. 305 | 306 | Some instructions can specify that the CPU proceed to execute an 307 | instruction at an address other than the one that follows itself. 308 | This class of instructions have names like {\em jump} and {\em branch} 309 | and are available in a variety of different styles. 310 | 311 | The RISC-V ISA uses the word {\em jump} to refer to an {\em unconditional} 312 | change in the sequential processing of instructions and the word 313 | {\em branch} to refer to a {\em conditional} change. 314 | 315 | Conditional branch instructions can be used to tell the CPU to 316 | do things like: 317 | 318 | \begin{quote} 319 | If the value in x8 is currently less than the value in x24 then 320 | proceed to the instruction at the next main memory address, otherwise 321 | branch to an instruction at a different address. 322 | \end{quote} 323 | 324 | This type of instruction can therefore result in one of two different 325 | actions pending the result of the 326 | comparison.\footnote{This is the fundamental method used by a CPU 327 | to make decisions.} 328 | 329 | Once the instruction execution phase has completed, the next instruction 330 | cycle will be performed using the new value in the \reg{pc} register. 331 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Attribution 4.0 International 2 | 3 | ======================================================================= 4 | 5 | Creative Commons Corporation ("Creative Commons") is not a law firm and 6 | does not provide legal services or legal advice. Distribution of 7 | Creative Commons public licenses does not create a lawyer-client or 8 | other relationship. Creative Commons makes its licenses and related 9 | information available on an "as-is" basis. Creative Commons gives no 10 | warranties regarding its licenses, any material licensed under their 11 | terms and conditions, or any related information. Creative Commons 12 | disclaims all liability for damages resulting from their use to the 13 | fullest extent possible. 14 | 15 | Using Creative Commons Public Licenses 16 | 17 | Creative Commons public licenses provide a standard set of terms and 18 | conditions that creators and other rights holders may use to share 19 | original works of authorship and other material subject to copyright 20 | and certain other rights specified in the public license below. The 21 | following considerations are for informational purposes only, are not 22 | exhaustive, and do not form part of our licenses. 23 | 24 | Considerations for licensors: Our public licenses are 25 | intended for use by those authorized to give the public 26 | permission to use material in ways otherwise restricted by 27 | copyright and certain other rights. Our licenses are 28 | irrevocable. Licensors should read and understand the terms 29 | and conditions of the license they choose before applying it. 30 | Licensors should also secure all rights necessary before 31 | applying our licenses so that the public can reuse the 32 | material as expected. Licensors should clearly mark any 33 | material not subject to the license. This includes other CC- 34 | licensed material, or material used under an exception or 35 | limitation to copyright. More considerations for licensors: 36 | wiki.creativecommons.org/Considerations_for_licensors 37 | 38 | Considerations for the public: By using one of our public 39 | licenses, a licensor grants the public permission to use the 40 | licensed material under specified terms and conditions. If 41 | the licensor's permission is not necessary for any reason--for 42 | example, because of any applicable exception or limitation to 43 | copyright--then that use is not regulated by the license. Our 44 | licenses grant only permissions under copyright and certain 45 | other rights that a licensor has authority to grant. Use of 46 | the licensed material may still be restricted for other 47 | reasons, including because others have copyright or other 48 | rights in the material. A licensor may make special requests, 49 | such as asking that all changes be marked or described. 50 | Although not required by our licenses, you are encouraged to 51 | respect those requests where reasonable. More_considerations 52 | for the public: 53 | wiki.creativecommons.org/Considerations_for_licensees 54 | 55 | ======================================================================= 56 | 57 | Creative Commons Attribution 4.0 International Public License 58 | 59 | By exercising the Licensed Rights (defined below), You accept and agree 60 | to be bound by the terms and conditions of this Creative Commons 61 | Attribution 4.0 International Public License ("Public License"). To the 62 | extent this Public License may be interpreted as a contract, You are 63 | granted the Licensed Rights in consideration of Your acceptance of 64 | these terms and conditions, and the Licensor grants You such rights in 65 | consideration of benefits the Licensor receives from making the 66 | Licensed Material available under these terms and conditions. 67 | 68 | 69 | Section 1 -- Definitions. 70 | 71 | a. Adapted Material means material subject to Copyright and Similar 72 | Rights that is derived from or based upon the Licensed Material 73 | and in which the Licensed Material is translated, altered, 74 | arranged, transformed, or otherwise modified in a manner requiring 75 | permission under the Copyright and Similar Rights held by the 76 | Licensor. For purposes of this Public License, where the Licensed 77 | Material is a musical work, performance, or sound recording, 78 | Adapted Material is always produced where the Licensed Material is 79 | synched in timed relation with a moving image. 80 | 81 | b. Adapter's License means the license You apply to Your Copyright 82 | and Similar Rights in Your contributions to Adapted Material in 83 | accordance with the terms and conditions of this Public License. 84 | 85 | c. Copyright and Similar Rights means copyright and/or similar rights 86 | closely related to copyright including, without limitation, 87 | performance, broadcast, sound recording, and Sui Generis Database 88 | Rights, without regard to how the rights are labeled or 89 | categorized. For purposes of this Public License, the rights 90 | specified in Section 2(b)(1)-(2) are not Copyright and Similar 91 | Rights. 92 | 93 | d. Effective Technological Measures means those measures that, in the 94 | absence of proper authority, may not be circumvented under laws 95 | fulfilling obligations under Article 11 of the WIPO Copyright 96 | Treaty adopted on December 20, 1996, and/or similar international 97 | agreements. 98 | 99 | e. Exceptions and Limitations means fair use, fair dealing, and/or 100 | any other exception or limitation to Copyright and Similar Rights 101 | that applies to Your use of the Licensed Material. 102 | 103 | f. Licensed Material means the artistic or literary work, database, 104 | or other material to which the Licensor applied this Public 105 | License. 106 | 107 | g. Licensed Rights means the rights granted to You subject to the 108 | terms and conditions of this Public License, which are limited to 109 | all Copyright and Similar Rights that apply to Your use of the 110 | Licensed Material and that the Licensor has authority to license. 111 | 112 | h. Licensor means the individual(s) or entity(ies) granting rights 113 | under this Public License. 114 | 115 | i. Share means to provide material to the public by any means or 116 | process that requires permission under the Licensed Rights, such 117 | as reproduction, public display, public performance, distribution, 118 | dissemination, communication, or importation, and to make material 119 | available to the public including in ways that members of the 120 | public may access the material from a place and at a time 121 | individually chosen by them. 122 | 123 | j. Sui Generis Database Rights means rights other than copyright 124 | resulting from Directive 96/9/EC of the European Parliament and of 125 | the Council of 11 March 1996 on the legal protection of databases, 126 | as amended and/or succeeded, as well as other essentially 127 | equivalent rights anywhere in the world. 128 | 129 | k. You means the individual or entity exercising the Licensed Rights 130 | under this Public License. Your has a corresponding meaning. 131 | 132 | 133 | Section 2 -- Scope. 134 | 135 | a. License grant. 136 | 137 | 1. Subject to the terms and conditions of this Public License, 138 | the Licensor hereby grants You a worldwide, royalty-free, 139 | non-sublicensable, non-exclusive, irrevocable license to 140 | exercise the Licensed Rights in the Licensed Material to: 141 | 142 | a. reproduce and Share the Licensed Material, in whole or 143 | in part; and 144 | 145 | b. produce, reproduce, and Share Adapted Material. 146 | 147 | 2. Exceptions and Limitations. For the avoidance of doubt, where 148 | Exceptions and Limitations apply to Your use, this Public 149 | License does not apply, and You do not need to comply with 150 | its terms and conditions. 151 | 152 | 3. Term. The term of this Public License is specified in Section 153 | 6(a). 154 | 155 | 4. Media and formats; technical modifications allowed. The 156 | Licensor authorizes You to exercise the Licensed Rights in 157 | all media and formats whether now known or hereafter created, 158 | and to make technical modifications necessary to do so. The 159 | Licensor waives and/or agrees not to assert any right or 160 | authority to forbid You from making technical modifications 161 | necessary to exercise the Licensed Rights, including 162 | technical modifications necessary to circumvent Effective 163 | Technological Measures. For purposes of this Public License, 164 | simply making modifications authorized by this Section 2(a) 165 | (4) never produces Adapted Material. 166 | 167 | 5. Downstream recipients. 168 | 169 | a. Offer from the Licensor -- Licensed Material. Every 170 | recipient of the Licensed Material automatically 171 | receives an offer from the Licensor to exercise the 172 | Licensed Rights under the terms and conditions of this 173 | Public License. 174 | 175 | b. No downstream restrictions. You may not offer or impose 176 | any additional or different terms or conditions on, or 177 | apply any Effective Technological Measures to, the 178 | Licensed Material if doing so restricts exercise of the 179 | Licensed Rights by any recipient of the Licensed 180 | Material. 181 | 182 | 6. No endorsement. Nothing in this Public License constitutes or 183 | may be construed as permission to assert or imply that You 184 | are, or that Your use of the Licensed Material is, connected 185 | with, or sponsored, endorsed, or granted official status by, 186 | the Licensor or others designated to receive attribution as 187 | provided in Section 3(a)(1)(A)(i). 188 | 189 | b. Other rights. 190 | 191 | 1. Moral rights, such as the right of integrity, are not 192 | licensed under this Public License, nor are publicity, 193 | privacy, and/or other similar personality rights; however, to 194 | the extent possible, the Licensor waives and/or agrees not to 195 | assert any such rights held by the Licensor to the limited 196 | extent necessary to allow You to exercise the Licensed 197 | Rights, but not otherwise. 198 | 199 | 2. Patent and trademark rights are not licensed under this 200 | Public License. 201 | 202 | 3. To the extent possible, the Licensor waives any right to 203 | collect royalties from You for the exercise of the Licensed 204 | Rights, whether directly or through a collecting society 205 | under any voluntary or waivable statutory or compulsory 206 | licensing scheme. In all other cases the Licensor expressly 207 | reserves any right to collect such royalties. 208 | 209 | 210 | Section 3 -- License Conditions. 211 | 212 | Your exercise of the Licensed Rights is expressly made subject to the 213 | following conditions. 214 | 215 | a. Attribution. 216 | 217 | 1. If You Share the Licensed Material (including in modified 218 | form), You must: 219 | 220 | a. retain the following if it is supplied by the Licensor 221 | with the Licensed Material: 222 | 223 | i. identification of the creator(s) of the Licensed 224 | Material and any others designated to receive 225 | attribution, in any reasonable manner requested by 226 | the Licensor (including by pseudonym if 227 | designated); 228 | 229 | ii. a copyright notice; 230 | 231 | iii. a notice that refers to this Public License; 232 | 233 | iv. a notice that refers to the disclaimer of 234 | warranties; 235 | 236 | v. a URI or hyperlink to the Licensed Material to the 237 | extent reasonably practicable; 238 | 239 | b. indicate if You modified the Licensed Material and 240 | retain an indication of any previous modifications; and 241 | 242 | c. indicate the Licensed Material is licensed under this 243 | Public License, and include the text of, or the URI or 244 | hyperlink to, this Public License. 245 | 246 | 2. You may satisfy the conditions in Section 3(a)(1) in any 247 | reasonable manner based on the medium, means, and context in 248 | which You Share the Licensed Material. For example, it may be 249 | reasonable to satisfy the conditions by providing a URI or 250 | hyperlink to a resource that includes the required 251 | information. 252 | 253 | 3. If requested by the Licensor, You must remove any of the 254 | information required by Section 3(a)(1)(A) to the extent 255 | reasonably practicable. 256 | 257 | 4. If You Share Adapted Material You produce, the Adapter's 258 | License You apply must not prevent recipients of the Adapted 259 | Material from complying with this Public License. 260 | 261 | 262 | Section 4 -- Sui Generis Database Rights. 263 | 264 | Where the Licensed Rights include Sui Generis Database Rights that 265 | apply to Your use of the Licensed Material: 266 | 267 | a. for the avoidance of doubt, Section 2(a)(1) grants You the right 268 | to extract, reuse, reproduce, and Share all or a substantial 269 | portion of the contents of the database; 270 | 271 | b. if You include all or a substantial portion of the database 272 | contents in a database in which You have Sui Generis Database 273 | Rights, then the database in which You have Sui Generis Database 274 | Rights (but not its individual contents) is Adapted Material; and 275 | 276 | c. You must comply with the conditions in Section 3(a) if You Share 277 | all or a substantial portion of the contents of the database. 278 | 279 | For the avoidance of doubt, this Section 4 supplements and does not 280 | replace Your obligations under this Public License where the Licensed 281 | Rights include other Copyright and Similar Rights. 282 | 283 | 284 | Section 5 -- Disclaimer of Warranties and Limitation of Liability. 285 | 286 | a. UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE 287 | EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS 288 | AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF 289 | ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, 290 | IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, 291 | WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR 292 | PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, 293 | ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT 294 | KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT 295 | ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. 296 | 297 | b. TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE 298 | TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, 299 | NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, 300 | INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, 301 | COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR 302 | USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN 303 | ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR 304 | DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR 305 | IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. 306 | 307 | c. The disclaimer of warranties and limitation of liability provided 308 | above shall be interpreted in a manner that, to the extent 309 | possible, most closely approximates an absolute disclaimer and 310 | waiver of all liability. 311 | 312 | 313 | Section 6 -- Term and Termination. 314 | 315 | a. This Public License applies for the term of the Copyright and 316 | Similar Rights licensed here. However, if You fail to comply with 317 | this Public License, then Your rights under this Public License 318 | terminate automatically. 319 | 320 | b. Where Your right to use the Licensed Material has terminated under 321 | Section 6(a), it reinstates: 322 | 323 | 1. automatically as of the date the violation is cured, provided 324 | it is cured within 30 days of Your discovery of the 325 | violation; or 326 | 327 | 2. upon express reinstatement by the Licensor. 328 | 329 | For the avoidance of doubt, this Section 6(b) does not affect any 330 | right the Licensor may have to seek remedies for Your violations 331 | of this Public License. 332 | 333 | c. For the avoidance of doubt, the Licensor may also offer the 334 | Licensed Material under separate terms or conditions or stop 335 | distributing the Licensed Material at any time; however, doing so 336 | will not terminate this Public License. 337 | 338 | d. Sections 1, 5, 6, 7, and 8 survive termination of this Public 339 | License. 340 | 341 | 342 | Section 7 -- Other Terms and Conditions. 343 | 344 | a. The Licensor shall not be bound by any additional or different 345 | terms or conditions communicated by You unless expressly agreed. 346 | 347 | b. Any arrangements, understandings, or agreements regarding the 348 | Licensed Material not stated herein are separate from and 349 | independent of the terms and conditions of this Public License. 350 | 351 | 352 | Section 8 -- Interpretation. 353 | 354 | a. For the avoidance of doubt, this Public License does not, and 355 | shall not be interpreted to, reduce, limit, restrict, or impose 356 | conditions on any use of the Licensed Material that could lawfully 357 | be made without permission under this Public License. 358 | 359 | b. To the extent possible, if any provision of this Public License is 360 | deemed unenforceable, it shall be automatically reformed to the 361 | minimum extent necessary to make it enforceable. If the provision 362 | cannot be reformed, it shall be severed from this Public License 363 | without affecting the enforceability of the remaining terms and 364 | conditions. 365 | 366 | c. No term or condition of this Public License will be waived and no 367 | failure to comply consented to unless expressly agreed to by the 368 | Licensor. 369 | 370 | d. Nothing in this Public License constitutes or may be interpreted 371 | as a limitation upon, or waiver of, any privileges and immunities 372 | that apply to the Licensor or You, including from the legal 373 | processes of any jurisdiction or authority. 374 | 375 | 376 | ======================================================================= 377 | 378 | Creative Commons is not a party to its public 379 | licenses. Notwithstanding, Creative Commons may elect to apply one of 380 | its public licenses to material it publishes and in those instances 381 | will be considered the “Licensor.” The text of the Creative Commons 382 | public licenses is dedicated to the public domain under the CC0 Public 383 | Domain Dedication. Except for the limited purpose of indicating that 384 | material is shared under a Creative Commons public license or as 385 | otherwise permitted by the Creative Commons policies published at 386 | creativecommons.org/policies, Creative Commons does not authorize the 387 | use of the trademark "Creative Commons" or any other trademark or logo 388 | of Creative Commons without its prior written consent including, 389 | without limitation, in connection with any unauthorized modifications 390 | to any of its public licenses or any other arrangements, 391 | understandings, or agreements concerning use of licensed material. For 392 | the avoidance of doubt, this paragraph does not form part of the 393 | public licenses. 394 | 395 | Creative Commons may be contacted at creativecommons.org. 396 | 397 | -------------------------------------------------------------------------------- /book/license/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Attribution 4.0 International} 2 | \label{license} 3 | 4 | \begin{scriptsize} 5 | 6 | Creative Commons Corporation ("Creative Commons") is not a law firm and 7 | does not provide legal services or legal advice. Distribution of 8 | Creative Commons public licenses does not create a lawyer-client or 9 | other relationship. Creative Commons makes its licenses and related 10 | information available on an "as-is" basis. Creative Commons gives no 11 | warranties regarding its licenses, any material licensed under their 12 | terms and conditions, or any related information. Creative Commons 13 | disclaims all liability for damages resulting from their use to the 14 | fullest extent possible. 15 | 16 | \subsection*{Using Creative Commons Public Licenses} 17 | 18 | Creative Commons public licenses provide a standard set of terms and 19 | conditions that creators and other rights holders may use to share 20 | original works of authorship and other material subject to copyright 21 | and certain other rights specified in the public license below. The 22 | following considerations are for informational purposes only, are not 23 | exhaustive, and do not form part of our licenses. 24 | 25 | Considerations for licensors: Our public licenses are 26 | intended for use by those authorized to give the public 27 | permission to use material in ways otherwise restricted by 28 | copyright and certain other rights. Our licenses are 29 | irrevocable. Licensors should read and understand the terms 30 | and conditions of the license they choose before applying it. 31 | Licensors should also secure all rights necessary before 32 | applying our licenses so that the public can reuse the 33 | material as expected. Licensors should clearly mark any 34 | material not subject to the license. This includes other 35 | CC-licensed material, or material used under an exception or 36 | limitation to copyright. More considerations for licensors: 37 | \url{http://wiki.creativecommons.org/Considerations_for_licensors} 38 | 39 | Considerations for the public: By using one of our public 40 | licenses, a licensor grants the public permission to use the 41 | licensed material under specified terms and conditions. If 42 | the licensor's permission is not necessary for any reason-for 43 | example, because of any applicable exception or limitation to 44 | copyright-then that use is not regulated by the license. Our 45 | licenses grant only permissions under copyright and certain 46 | other rights that a licensor has authority to grant. Use of 47 | the licensed material may still be restricted for other 48 | reasons, including because others have copyright or other 49 | rights in the material. A licensor may make special requests, 50 | such as asking that all changes be marked or described. 51 | Although not required by our licenses, you are encouraged to 52 | respect those requests where reasonable. More considerations 53 | for the public: 54 | \url{http://wiki.creativecommons.org/Considerations_for_licensees}\\ 55 | 56 | \hrule 57 | 58 | \subsection*{Creative Commons Attribution 4.0 International Public License} 59 | 60 | By exercising the Licensed Rights (defined below), You accept and agree 61 | to be bound by the terms and conditions of this Creative Commons 62 | Attribution 4.0 International Public License ("Public License"). To the 63 | extent this Public License may be interpreted as a contract, You are 64 | granted the Licensed Rights in consideration of Your acceptance of 65 | these terms and conditions, and the Licensor grants You such rights in 66 | consideration of benefits the Licensor receives from making the 67 | Licensed Material available under these terms and conditions. 68 | 69 | 70 | \subsection*{Section 1. Definitions} 71 | 72 | \begin{itemize} 73 | \item[a.] Adapted Material means material subject to Copyright and Similar 74 | Rights that is derived from or based upon the Licensed Material 75 | and in which the Licensed Material is translated, altered, 76 | arranged, transformed, or otherwise modified in a manner requiring 77 | permission under the Copyright and Similar Rights held by the 78 | Licensor. For purposes of this Public License, where the Licensed 79 | Material is a musical work, performance, or sound recording, 80 | Adapted Material is always produced where the Licensed Material is 81 | synched in timed relation with a moving image. 82 | 83 | \item[b.] Adapter's License means the license You apply to Your Copyright 84 | and Similar Rights in Your contributions to Adapted Material in 85 | accordance with the terms and conditions of this Public License. 86 | 87 | \item[c.] Copyright and Similar Rights means copyright and/or similar rights 88 | closely related to copyright including, without limitation, 89 | performance, broadcast, sound recording, and Sui Generis Database 90 | Rights, without regard to how the rights are labeled or 91 | categorized. For purposes of this Public License, the rights 92 | specified in Section 2(b)(1)-(2) are not Copyright and Similar 93 | Rights. 94 | 95 | \item[d.] Effective Technological Measures means those measures that, in the 96 | absence of proper authority, may not be circumvented under laws 97 | fulfilling obligations under Article 11 of the WIPO Copyright 98 | Treaty adopted on December 20, 1996, and/or similar international 99 | agreements. 100 | 101 | \item[e.] Exceptions and Limitations means fair use, fair dealing, and/or 102 | any other exception or limitation to Copyright and Similar Rights 103 | that applies to Your use of the Licensed Material. 104 | 105 | \item[f.] Licensed Material means the artistic or literary work, database, 106 | or other material to which the Licensor applied this Public 107 | License. 108 | 109 | \item[g.] Licensed Rights means the rights granted to You subject to the 110 | terms and conditions of this Public License, which are limited to 111 | all Copyright and Similar Rights that apply to Your use of the 112 | Licensed Material and that the Licensor has authority to license. 113 | 114 | \item[h.] Licensor means the individual(s) or entity(ies) granting rights 115 | under this Public License. 116 | 117 | \item[i.] Share means to provide material to the public by any means or 118 | process that requires permission under the Licensed Rights, such 119 | as reproduction, public display, public performance, distribution, 120 | dissemination, communication, or importation, and to make material 121 | available to the public including in ways that members of the 122 | public may access the material from a place and at a time 123 | individually chosen by them. 124 | 125 | \item[j.] Sui Generis Database Rights means rights other than copyright 126 | resulting from Directive 96/9/EC of the European Parliament and of 127 | the Council of 11 March 1996 on the legal protection of databases, 128 | as amended and/or succeeded, as well as other essentially 129 | equivalent rights anywhere in the world. 130 | 131 | \item[k.] You means the individual or entity exercising the Licensed Rights 132 | under this Public License. Your has a corresponding meaning. 133 | \end{itemize} 134 | 135 | \subsection*{Section 2. Scope} 136 | 137 | \begin{itemize} 138 | \item[a.] License grant. 139 | 140 | \begin{itemize} 141 | \item[1.] Subject to the terms and conditions of this Public License, 142 | the Licensor hereby grants You a worldwide, royalty-free, 143 | non-sublicensable, non-exclusive, irrevocable license to 144 | exercise the Licensed Rights in the Licensed Material to: 145 | 146 | \begin{itemize} 147 | \item[a.] reproduce and Share the Licensed Material, in whole or 148 | in part; and 149 | 150 | \item[b.] produce, reproduce, and Share Adapted Material. 151 | \end{itemize} 152 | 153 | \item[2.] Exceptions and Limitations. For the avoidance of doubt, where 154 | Exceptions and Limitations apply to Your use, this Public 155 | License does not apply, and You do not need to comply with 156 | its terms and conditions. 157 | 158 | \item[3.] Term. The term of this Public License is specified in Section 159 | 6(a). 160 | 161 | \item[4.] Media and formats; technical modifications allowed. The 162 | Licensor authorizes You to exercise the Licensed Rights in 163 | all media and formats whether now known or hereafter created, 164 | and to make technical modifications necessary to do so. The 165 | Licensor waives and/or agrees not to assert any right or 166 | authority to forbid You from making technical modifications 167 | necessary to exercise the Licensed Rights, including 168 | technical modifications necessary to circumvent Effective 169 | Technological Measures. For purposes of this Public License, 170 | simply making modifications authorized by this Section 2(a) 171 | (4) never produces Adapted Material. 172 | 173 | \item[5.] Downstream recipients. 174 | 175 | \begin{itemize} 176 | \item[a.] Offer from the Licensor -- Licensed Material. Every 177 | recipient of the Licensed Material automatically 178 | receives an offer from the Licensor to exercise the 179 | Licensed Rights under the terms and conditions of this 180 | Public License. 181 | 182 | \item[b.] No downstream restrictions. You may not offer or impose 183 | any additional or different terms or conditions on, or 184 | apply any Effective Technological Measures to, the 185 | Licensed Material if doing so restricts exercise of the 186 | Licensed Rights by any recipient of the Licensed 187 | Material. 188 | \end{itemize} 189 | 190 | \item[6.] No endorsement. Nothing in this Public License constitutes or 191 | may be construed as permission to assert or imply that You 192 | are, or that Your use of the Licensed Material is, connected 193 | with, or sponsored, endorsed, or granted official status by, 194 | the Licensor or others designated to receive attribution as 195 | provided in Section 3(a)(1)(A)(i). 196 | \end{itemize} 197 | 198 | \item[b.] Other rights. 199 | 200 | \begin{itemize} 201 | \item[1.] Moral rights, such as the right of integrity, are not 202 | licensed under this Public License, nor are publicity, 203 | privacy, and/or other similar personality rights; however, to 204 | the extent possible, the Licensor waives and/or agrees not to 205 | assert any such rights held by the Licensor to the limited 206 | extent necessary to allow You to exercise the Licensed 207 | Rights, but not otherwise. 208 | 209 | \item[2.] Patent and trademark rights are not licensed under this 210 | Public License. 211 | 212 | \item[3.] To the extent possible, the Licensor waives any right to 213 | collect royalties from You for the exercise of the Licensed 214 | Rights, whether directly or through a collecting society 215 | under any voluntary or waivable statutory or compulsory 216 | licensing scheme. In all other cases the Licensor expressly 217 | reserves any right to collect such royalties. 218 | \end{itemize} 219 | \end{itemize} 220 | 221 | 222 | \subsection*{Section 3. License Conditions} 223 | 224 | Your exercise of the Licensed Rights is expressly made subject to the 225 | following conditions. 226 | 227 | \begin{itemize} 228 | \item[a.] Attribution. 229 | 230 | \begin{itemize} 231 | \item[1.] If You Share the Licensed Material (including in modified 232 | form), You must: 233 | 234 | \begin{itemize} 235 | \item[a.] retain the following if it is supplied by the Licensor 236 | with the Licensed Material: 237 | 238 | \begin{itemize} 239 | \item[i.] identification of the creator(s) of the Licensed 240 | Material and any others designated to receive 241 | attribution, in any reasonable manner requested by 242 | the Licensor (including by pseudonym if 243 | designated); 244 | 245 | \item[ii.] a copyright notice; 246 | 247 | \item[iii.] a notice that refers to this Public License; 248 | 249 | \item[iv.] a notice that refers to the disclaimer of 250 | warranties; 251 | 252 | \item[v.] a URI or hyperlink to the Licensed Material to the 253 | extent reasonably practicable; 254 | \end{itemize} 255 | 256 | \item[b.] indicate if You modified the Licensed Material and 257 | retain an indication of any previous modifications; and 258 | 259 | \item[c.] indicate the Licensed Material is licensed under this 260 | Public License, and include the text of, or the URI or 261 | hyperlink to, this Public License. 262 | \end{itemize} 263 | 264 | \item[2.] You may satisfy the conditions in Section 3(a)(1) in any 265 | reasonable manner based on the medium, means, and context in 266 | which You Share the Licensed Material. For example, it may be 267 | reasonable to satisfy the conditions by providing a URI or 268 | hyperlink to a resource that includes the required 269 | information. 270 | 271 | \item[3.] If requested by the Licensor, You must remove any of the 272 | information required by Section 3(a)(1)(A) to the extent 273 | reasonably practicable. 274 | 275 | \item[4.] If You Share Adapted Material You produce, the Adapter's 276 | License You apply must not prevent recipients of the Adapted 277 | Material from complying with this Public License. 278 | \end{itemize} 279 | \end{itemize} 280 | 281 | 282 | \subsection*{Section 4. Sui Generis Database Rights} 283 | 284 | Where the Licensed Rights include Sui Generis Database Rights that 285 | apply to Your use of the Licensed Material: 286 | 287 | \begin{itemize} 288 | \item[a.] for the avoidance of doubt, Section 2(a)(1) grants You the right 289 | to extract, reuse, reproduce, and Share all or a substantial 290 | portion of the contents of the database; 291 | 292 | \item[b.] if You include all or a substantial portion of the database 293 | contents in a database in which You have Sui Generis Database 294 | Rights, then the database in which You have Sui Generis Database 295 | Rights (but not its individual contents) is Adapted Material; and 296 | 297 | \item[c.] You must comply with the conditions in Section 3(a) if You Share 298 | all or a substantial portion of the contents of the database. 299 | \end{itemize} 300 | 301 | For the avoidance of doubt, this Section 4 supplements and does not 302 | replace Your obligations under this Public License where the Licensed 303 | Rights include other Copyright and Similar Rights. 304 | 305 | 306 | \subsection*{Section 5. Disclaimer of Warranties and Limitation of Liability} 307 | 308 | \begin{itemize} 309 | \item[a.] UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE 310 | EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS 311 | AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF 312 | ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, 313 | IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, 314 | WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR 315 | PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, 316 | ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT 317 | KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT 318 | ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. 319 | 320 | \item[b.] TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE 321 | TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, 322 | NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, 323 | INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, 324 | COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR 325 | USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN 326 | ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR 327 | DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR 328 | IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. 329 | 330 | \item[c.] The disclaimer of warranties and limitation of liability provided 331 | above shall be interpreted in a manner that, to the extent 332 | possible, most closely approximates an absolute disclaimer and 333 | waiver of all liability. 334 | \end{itemize} 335 | 336 | 337 | \subsection*{Section 6. Term and Termination} 338 | 339 | \begin{itemize} 340 | \item[a.] This Public License applies for the term of the Copyright and 341 | Similar Rights licensed here. However, if You fail to comply with 342 | this Public License, then Your rights under this Public License 343 | terminate automatically. 344 | 345 | \item[b.] Where Your right to use the Licensed Material has terminated under 346 | Section 6(a), it reinstates: 347 | 348 | \begin{itemize} 349 | \item[1.] automatically as of the date the violation is cured, provided 350 | it is cured within 30 days of Your discovery of the 351 | violation; or 352 | 353 | \item[2.] upon express reinstatement by the Licensor. 354 | \end{itemize} 355 | 356 | For the avoidance of doubt, this Section 6(b) does not affect any 357 | right the Licensor may have to seek remedies for Your violations 358 | of this Public License. 359 | 360 | \item[c.] For the avoidance of doubt, the Licensor may also offer the 361 | Licensed Material under separate terms or conditions or stop 362 | distributing the Licensed Material at any time; however, doing so 363 | will not terminate this Public License. 364 | 365 | \item[d.] Sections 1, 5, 6, 7, and 8 survive termination of this Public 366 | License. 367 | \end{itemize} 368 | 369 | 370 | \subsection*{Section 7. Other Terms and Conditions} 371 | 372 | \begin{itemize} 373 | \item[a.] The Licensor shall not be bound by any additional or different 374 | terms or conditions communicated by You unless expressly agreed. 375 | 376 | \item[b.] Any arrangements, understandings, or agreements regarding the 377 | Licensed Material not stated herein are separate from and 378 | independent of the terms and conditions of this Public License. 379 | \end{itemize} 380 | 381 | \subsection*{Section 8. Interpretation} 382 | 383 | \begin{itemize} 384 | \item[a.] For the avoidance of doubt, this Public License does not, and 385 | shall not be interpreted to, reduce, limit, restrict, or impose 386 | conditions on any use of the Licensed Material that could lawfully 387 | be made without permission under this Public License. 388 | 389 | \item[b.] To the extent possible, if any provision of this Public License is 390 | deemed unenforceable, it shall be automatically reformed to the 391 | minimum extent necessary to make it enforceable. If the provision 392 | cannot be reformed, it shall be severed from this Public License 393 | without affecting the enforceability of the remaining terms and 394 | conditions. 395 | 396 | \item[c.] No term or condition of this Public License will be waived and no 397 | failure to comply consented to unless expressly agreed to by the 398 | Licensor. 399 | 400 | \item[d.] Nothing in this Public License constitutes or may be interpreted 401 | as a limitation upon, or waiver of, any privileges and immunities 402 | that apply to the Licensor or You, including from the legal 403 | processes of any jurisdiction or authority.\\ 404 | \end{itemize} 405 | 406 | \hrule 407 | 408 | Creative Commons is not a party to its public 409 | licenses. Notwithstanding, Creative Commons may elect to apply one of 410 | its public licenses to material it publishes and in those instances 411 | will be considered the Licensor. The text of the Creative Commons 412 | public licenses is dedicated to the public domain under the CC0 Public 413 | Domain Dedication. Except for the limited purpose of indicating that 414 | material is shared under a Creative Commons public license or as 415 | otherwise permitted by the Creative Commons policies published at 416 | \url{http://creativecommons.org/policies}, Creative Commons does not authorize the 417 | use of the trademark ``Creative Commons'' or any other trademark or logo 418 | of Creative Commons without its prior written consent including, 419 | without limitation, in connection with any unauthorized modifications 420 | to any of its public licenses or any other arrangements, 421 | understandings, or agreements concerning use of licensed material. For 422 | the avoidance of doubt, this paragraph does not form part of the 423 | public licenses. 424 | 425 | Creative Commons may be contacted at \url{http://creativecommons.org}. 426 | 427 | \end{scriptsize} 428 | -------------------------------------------------------------------------------- /book/programs/chapter.tex: -------------------------------------------------------------------------------- 1 | \chapter{Writing RISC-V Programs} 2 | 3 | \enote{Introduce the ISA register names and aliases in here?}% 4 | This chapter introduces each of the RV32I instructions by developing programs 5 | that demonstrate their usefulness. 6 | 7 | 8 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 9 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 10 | \section{Use {\tt ebreak} to Stop \rvddt{} Execution} 11 | \index{Instruction!ebreak} 12 | \label{uguide:ebreak} 13 | 14 | It is a good idea to learn how to stop before learning how to go! 15 | 16 | The \insn{ebreak} instruction exists for the sole purpose of transferring control back 17 | to a debugging environment.\cite[p.~24]{rvismv1v22:2017} 18 | 19 | When \rvddt{} executes an \insn{ebreak} instruction, it will immediately terminate any 20 | executing {\em trace} or {\em go} command currently executing and return to the 21 | command prompt without advancing the \reg{pc} register. 22 | 23 | The machine language encoding shows that \insn{ebreak} has no operands. 24 | 25 | \DrawInsnTypeEPicture{ebreak}{00000000000100000000000001110011} 26 | 27 | \listingRef{ebreak/ebreak.out} demonstrates that since \rvddt{} does 28 | not advance the \reg{pc} when it encounters an \insn{ebreak} instruction, 29 | subsequent {\em trace} and/or {\em go} commands will re-execute the same \insn{ebreak} 30 | and halt the simulation again (and again). 31 | This feature is intended to help prevent overzealous users from accidently 32 | running past the end of a code fragment.\footnote{This was one of the first {\em enhancements} 33 | I needed for myself \tt:-)} 34 | 35 | \listing{ebreak/ebreak.S}{A one-line \insn{ebreak} program.} 36 | 37 | \listing{ebreak/ebreak.out}{\insn{ebreak} stopps \rvddt{} without advancing \reg{pc}.} 38 | 39 | 40 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 41 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 42 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 43 | \section{Using the \insn{addi} Instruction} 44 | \index{Instruction!addi} 45 | \label{uguide:addi} 46 | 47 | \enote{Define what constant and immediate values are somewhere.}% 48 | The detailed description of how the \insn{addi} instruction is executed 49 | is that it: 50 | \begin{enumerate} 51 | \item Sign-extends the immediate operand. 52 | \item Add the sign-extended immediate operand to the contents of the \reg{rs1} register. 53 | \item Store the sum in the \reg{rd} register. 54 | \item Add four to the \reg{pc} register (point to the next instruction.) 55 | \end{enumerate} 56 | 57 | In the following example \reg{rs1} = \reg{x28}, \reg{rd} = \reg{x29} and 58 | the immediate operand is -1. 59 | 60 | \DrawInsnTypeIPicture{addi x29, x28, -1}{11111111111111100000111010010011} 61 | 62 | Depending on the values of the fields in this instruction a number of 63 | different operations can be performed. The most obvious is that it 64 | can add things. But it can also be used to copy registers, set a 65 | register to zero and even, when you need to, accomplish nothing. 66 | 67 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 68 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 69 | \subsection{No Operation} 70 | \index{Instruction!nop} 71 | 72 | It might seem odd but it is sometimes important to be able to execute 73 | an instruction that accomplishes nothing while simply advancing the 74 | \reg{pc} to the next instruction. One reason for this is to fill 75 | unused memory between two instructions in a program.% 76 | \footnote{This can happen during the evolution of one portion of code 77 | that reduces in size but has to continue to fit into a system without 78 | altering any other code\ldots\ or sometimes you just need to waste 79 | a small amount of time in a device driver.} 80 | 81 | An instruction that accomplishes nothing is called a \insn{nop} 82 | (sometimes systems call these \insn{noop}). The name means 83 | {\em no operation}. 84 | The intent of a \insn{nop} is to execute without having any side effects 85 | other than to advance the \reg{pc} register. 86 | 87 | The \insn{addi} instruction can serve as a \insn{nop} by coding it like this: 88 | 89 | \DrawInsnTypeIPicture{addi x0, x0, 0}{00000000000000000000000000010011} 90 | 91 | The result will be to add zero to zero and discard the result (because you 92 | can never store a value into the x0 register.) 93 | 94 | The RISC-V assembler provides a pseudoinstruction specifically for this 95 | purpose that you can use to improve the readability of your code. Note 96 | that the \insn{addi} and \insn{nop} instructions in \listingRef{nop/nop.S} 97 | are assembled into the exact same binary machine instructions 98 | as can be seen by comparing it to 99 | \verb@objdump@ \listingRef{nop/nop.lst}, 100 | and \verb@rvddt@ \listingRef{nop/nop.out} output. 101 | 102 | %(The \hex{00000013} you can see are stored at addresses \hex{0} and \hex{4}) 103 | %as seen by looking at the \verb@objdump@ listing in \listingRef{nop/nop.lst}. 104 | %In fact, you can see that objdump shows both instructions as a \insn{nop} 105 | %while \listingRef{nop/nop.out} shows that \rvddt{} displays both as 106 | %\verb@addi x0, x0, 0@. 107 | 108 | \listing{nop/nop.S}{Demonstrate that \insn{addi} can be used as a \insn{nop}.} 109 | 110 | \index{objdump} 111 | \listing{nop/nop.lst}{Using \insn{addi} to perform a \insn{nop}} 112 | 113 | \listing{nop/nop.out}{Using \insn{addi} to perform a \insn{nop}} 114 | 115 | 116 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 117 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 118 | \subsection{Copying the Contents of One Register to Another} 119 | 120 | By adding zero to one register and storing the sum in another register 121 | the \insn{addi} instruction can be used to copy the value stored in one 122 | register to another register. The following instruction will copy 123 | the contents of \reg{t4} into \reg{t3}. 124 | 125 | \DrawInsnTypeIPicture{addi t3, t4, 0}{00000000000011101000111000010011} 126 | 127 | \index{Instruction!mv} 128 | This is a commonly required operation. To make your intent clear 129 | you may use the \insn{mv} pseudoinstruction for this purpose. 130 | 131 | \listingRef{mv/mv.S} shows the source of a program that is dumped in 132 | \listingRef{mv/mv.lst} illustrating that the assembler has generated the 133 | same machine instruction (\hex{000e8e13} at addresses \hex{0} and \hex{4}) 134 | for both of the instructions. 135 | 136 | \listing{mv/mv.S}{Comparing \insn{addi} to \insn{mv}} 137 | 138 | \listing{mv/mv.lst}{An objdump of an \insn{addi} and \insn{mv} Instruction.} 139 | 140 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 141 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 142 | \subsection{Setting a Register to Zero} 143 | 144 | Recall that \reg{x0} always contains the value zero. Any register 145 | can be set to zero by copying the contents of \reg{x0} using \insn{mv} 146 | (aka \insn{addi}).% 147 | \footnote{There are other pseudoinstructions (such as \insn{li}) that can also 148 | turn into an \insn{addi} instruction. Objdump might display `{\tt addi t3,x0,0}' 149 | as `{\tt mv t3,x0}' or `{\tt li t3,0}'.} 150 | 151 | For example, to set \reg{t3} to zero: 152 | 153 | \DrawInsnTypeIPicture{addi t3, x0, 0}{00000000000000000000111000010011} 154 | 155 | \listing{mvzero/mv.S}{Using \insn{mv} (aka \insn{addi}) to zero-out a register.} 156 | 157 | \listingRef{mvzero/mv.out} traces the execution of the program in 158 | \listingRef{mvzero/mv.S} showing how \reg{t3} is changed from \hex{f0f0f0f0} 159 | (seen on $\ell 16$) to \hex{00000000} (seen on $\ell 26$.) 160 | 161 | \listing{mvzero/mv.out}{Setting \reg{t3} to zero.} 162 | 163 | 164 | 165 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 166 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 167 | \subsection{Adding a 12-bit Signed Value} 168 | 169 | 170 | \DrawInsnTypeIPicture{addi x1, x7, 4}{00000000010000111000000010010011} 171 | 172 | 173 | {\small 174 | \begin{verbatim} 175 | addi t0, zero, 4 # t0 = 4 176 | addi t0, t0, 100 # t0 = 104 177 | 178 | addi t0, zero, 0x123 # t0 = 0x123 179 | addi t0, t0, 0xfff # t0 = 0x122 (subtract 1) 180 | 181 | addi t0, zero, 0xfff # t0 = 0xffffffff (-1) (diagram out the chaining carry) 182 | # refer back to the overflow/truncation discussion in binary chapter 183 | 184 | addi x0, x0, 0 # no operation (pseudo: nop) 185 | addi rd, rs, 0 # copy reg rs to rd (pseudo: mv rd, rs) 186 | \end{verbatim} 187 | } 188 | 189 | 190 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 191 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 192 | \section{todo} 193 | 194 | Ideas for the order of introducing instructions. 195 | 196 | 197 | \section{Other Instructions With Immediate Operands} 198 | 199 | \label{uguide:andi} 200 | \label{uguide:ori} 201 | \label{uguide:xori} 202 | \label{uguide:slti} 203 | \label{uguide:sltiu} 204 | \label{uguide:srai} 205 | \label{uguide:slli} 206 | \label{uguide:srli} 207 | {\small 208 | \begin{verbatim} 209 | andi 210 | ori 211 | xori 212 | 213 | slti 214 | sltiu 215 | srai 216 | slli 217 | srli 218 | \end{verbatim} 219 | } 220 | 221 | \section{Transferring Data Between Registers and Memory} 222 | 223 | RV is a load-store architecture. This means that the only way that the 224 | CPU can interact with the memory is via the {\em load} and {\em store} 225 | instructions. All other data manipulation must be performed on register 226 | values. 227 | 228 | Copying values from memory to a register (first examples using regs set with addi): 229 | \label{uguide:lb} 230 | \label{uguide:lh} 231 | \label{uguide:lw} 232 | \label{uguide:lbu} 233 | \label{uguide:lhu} 234 | {\small 235 | \begin{verbatim} 236 | lb 237 | lh 238 | lw 239 | lbu 240 | lhu 241 | \end{verbatim} 242 | } 243 | 244 | Copying values from a register to memory: 245 | \label{uguide:sb} 246 | \label{uguide:sh} 247 | \label{uguide:sw} 248 | {\small 249 | \begin{verbatim} 250 | sb 251 | sh 252 | sw 253 | \end{verbatim} 254 | } 255 | 256 | \section{RR operations} 257 | \label{uguide:add} 258 | \label{uguide:sub} 259 | \label{uguide:and} 260 | \label{uguide:or} 261 | \label{uguide:sra} 262 | \label{uguide:srl} 263 | \label{uguide:sll} 264 | \label{uguide:xor} 265 | \label{uguide:sltu} 266 | \label{uguide:slt} 267 | {\small 268 | \begin{verbatim} 269 | add 270 | sub 271 | and 272 | or 273 | sra 274 | srl 275 | sll 276 | xor 277 | sltu 278 | slt 279 | \end{verbatim} 280 | } 281 | 282 | 283 | \section{Setting registers to large values using lui with addi} 284 | 285 | \label{uguide:lui} 286 | \label{uguide:auipc} 287 | {\small 288 | \begin{verbatim} 289 | addi // useful for values from -2048 to 2047 290 | lui // useful for loading any multiple of 0x1000 291 | 292 | Setting a register to any other value must be done using a combo of insns: 293 | 294 | auipc // Load an address relative the the current PC (see la pseudo) 295 | addi 296 | 297 | lui // Load constant into into bits 31:12 (see li pseudo) 298 | addi // add a constant to fill in bits 11:0 299 | if bit 11 is set then need to +1 the lui value to compensate 300 | \end{verbatim} 301 | } 302 | 303 | 304 | \section{Labels and Branching} 305 | 306 | Start to introduce addressing here? 307 | 308 | \label{uguide:beq} 309 | \label{uguide:bne} 310 | \label{uguide:blt} 311 | \label{uguide:bge} 312 | \label{uguide:bltu} 313 | \label{uguide:bgeu} 314 | \label{uguide:bgt} 315 | \label{uguide:ble} 316 | \label{uguide:bgtu} 317 | \label{uguide:beqz} 318 | \label{uguide:bnez} 319 | \label{uguide:blez} 320 | \label{uguide:bgez} 321 | \label{uguide:bltz} 322 | \label{uguide:bgtz} 323 | {\small 324 | \begin{verbatim} 325 | beq 326 | bne 327 | blt 328 | bge 329 | bltu 330 | bgeu 331 | 332 | bgt rs, rt, offset # pseudo for: blt rt, rs, offset (reverse the operands) 333 | ble rs, rt, offset # pseudo for: bge rt, rs, offset (reverse the operands) 334 | bgtu rs, rt, offset # pseudo for: bltu rt, rs, offset (reverse the operands) 335 | bleu rs, rt, offset # pseudo for: bgeu rt, rs, offset (reverse the operands) 336 | 337 | beqz rs, offset # pseudo for: beq rs, x0, offset 338 | bnez rs, offset # pseudo for: bne rs, x0, offset 339 | blez rs, offset # pseudo for: bge x0, rs, offset 340 | bgez rs, offset # pseudo for: bge rs, x0, offset 341 | bltz rs, offset # pseudo for: blt rs, x0, offset 342 | bgtz rs, offset # pseudo for: blt x0, rs, offset 343 | \end{verbatim} 344 | } 345 | 346 | 347 | 348 | \section{Jumps} 349 | 350 | Introduce and present subroutines but not nesting until introduce stack operations. 351 | 352 | \label{uguide:jal} 353 | \label{uguide:jalr} 354 | {\small 355 | \begin{verbatim} 356 | jal 357 | jalr 358 | \end{verbatim} 359 | } 360 | 361 | 362 | 363 | \section{Pseudoinstructions} 364 | 365 | {\small 366 | \begin{verbatim} 367 | li rd,constant 368 | lui rd,(constant + 0x00000800) >> 12 369 | addi rd,rd,(constant & 0x00000fff) 370 | 371 | la rd,label 372 | auipc rd,((label-.) + 0x00000800) >> 12 373 | addi rd,rd,((label-(.-4)) & 0x00000fff) 374 | 375 | l{b|h|w} rd,label 376 | auipc rd,((label-.) + 0x00000800) >> 12 377 | l{b|h|w} rd,((label-(.-4)) & 0x00000fff)(rd) 378 | 379 | s{b|h|w} rd,label,rt # rt used as a temp reg for the operation (default=x6) 380 | auipc rt,((label-.) + 0x00000800) >> 12 381 | s{b|h|w} rd,((label-(.-4)) & 0x00000fff)(rt) 382 | 383 | call label auipc x1,((label-.) + 0x00000800) >> 12 384 | jalr x1,((label-(.-4)) & 0x00000fff)(x1) 385 | 386 | tail label,rt # rt used as a temp reg for the operation (default=x6) 387 | auipc rt,((label-.) + 0x00000800) >> 12 388 | jalr x0,((label-(.-4)) & 0x00000fff)(rt) 389 | 390 | mv rd,rs addi rd,rs,0 391 | 392 | j label jal x0,label 393 | jal label jal x1,label 394 | jr rs jalr x0,0(rs) 395 | jalr rs jalr x1,0(rs) 396 | ret jalr x0,0(x1) 397 | \end{verbatim} 398 | } 399 | 400 | \subsection{The {\tt li} Pseudoinstruction} 401 | 402 | Note that the {\tt li} pseudoinstruction includes an (effectively) conditional addition 403 | of 1 to the immediate operand 404 | in the {\tt lui} instruction. This is because the immediate operand in the 405 | {\tt addi} instruction is sign-extended before it is added to \verb@rd@. 406 | If the immediate operand to the {\tt addi} has its most-significant-bit set to 1 then 407 | it will have the effect of subtracting 1 from the operand in the \verb@lui@ instruction. 408 | 409 | Consider the case of putting the value {\tt 0x12345800} into register {\tt x5}: 410 | 411 | {\small 412 | \begin{verbatim} 413 | li x5,0x12345800 414 | \end{verbatim} 415 | } 416 | {\color{red} 417 | A naive (incorrect) solution might be: 418 | {\small 419 | \begin{verbatim} 420 | lui x5,0x12345 // x5 = 0x12345000 421 | addi x5,x5,0x800 // x5 = 0x12345000 + sx(0x800) = 0x12345000 + 0xfffff800 = 0x12344800 422 | \end{verbatim} 423 | } 424 | The result of the above code is that an incorrect value has been placed into x5. 425 | } 426 | 427 | To remedy this problem, the value used in the {\tt lui} instruction can be altered 428 | (by adding 1 to its operand) to compensate for the sign-extention in the {\tt addi} 429 | instruction: 430 | {\small 431 | \begin{verbatim} 432 | lui x5,0x12346 // x5 = 0x12346000 (note: this is 0x12345800 + 0x0800) 433 | addi x5,x5,0x800 // x5 = 0x12346000 + sx(0x800) = 0x12346000 + 0xfffff800 = 0x12345800 434 | \end{verbatim} 435 | } 436 | 437 | Keep in mind that the {\tt li} pseudoinstruction must {\em only} increment the operand 438 | of the {\tt lui} instruction when it is known that the operand of the subsequent 439 | {\tt addi} instruction will be a negative number. 440 | 441 | \enote{Add a ribbon diagram of this?}% 442 | By adding {\tt 0x00000800} to the immediate operand of the {\tt lui} instruction in 443 | this example, a carry-bit into bit-12 will be set to {\tt 1} iff the value in 444 | bits 11-0 will be treated as a negative value in the subsequent {\tt addi} instruction. 445 | In other words, when bit-11 is set to {\tt 1} in the immediate operand of the {\tt li} 446 | pseudoinstruction, the immediate operand of the {\tt lui} instruction will be 447 | incremented by {\tt 1}. 448 | 449 | Consider the case where we wish to put the value {\tt 0x12345700} into register {\tt x5}: 450 | {\small 451 | \begin{verbatim} 452 | lui x5,0x12345 // x5 = 0x12345000 (note that 0x12345700 + 0x0800 = 0x12345f00) 453 | addi x5,x5,0x700 // x5 = 0x12345000 + sx(0x700) = 0x12345000 + 0x00000700 = 0x12345700 454 | \end{verbatim} 455 | } 456 | The sign-extension in this example performed by the {\tt addi} instruction will convert the 457 | {\tt 0x700} to {\tt 0x00000700} before the addition. 458 | 459 | Observe that {\tt 0x12345700+0x0800 = 0x12345f00} and therefore, after shifting 460 | to the right, the least significant {\tt 0xf00} is truncated, leaving {\tt 0x12345} as 461 | the immediate operand of the {\tt lui} instruction. The addition of 462 | {\tt 0x0800} in this example has no effect on the immediate operand of the {\tt lui} 463 | instruction because bit-11 in the original value {\tt 0x12345700} is zero. 464 | 465 | A general algorithm for implementing the {\tt li rd,constant} pseudoinstruction is: 466 | 467 | {\small 468 | \begin{verbatim} 469 | lui rd,(constant + 0x00000800) >> 12 470 | addi rd,rd,(constant & 0x00000fff) // the 12-bit immediate is sign extended 471 | \end{verbatim} 472 | } 473 | 474 | \enote{Find a proper citation for this.}% 475 | Note that on RV64 and RV128 systems, the {\tt lui} places the immediate operand into 476 | bits 31-12 and then sign-extends the result to {\tt XLEN} bits. 477 | 478 | 479 | 480 | 481 | 482 | 483 | 484 | 485 | 486 | \subsection{The {\tt la} Pseudoinstruction} 487 | 488 | The \verb@la@ (and others that use \verb@auipc@ such as 489 | the \verb@l{b|h|w}@, \verb@s{b|h|w}@, \verb@call@, and \verb@tail@) pseudoinstructions 490 | also compensate for a sign-ended negative number when adding a 12-bit immediate 491 | operand. The only difference is that these use a \verb@pc@-relative addressing mode. 492 | 493 | For example, consider the task of putting an address represented by the label \verb@var1@ 494 | into register x10: 495 | 496 | {\small 497 | \begin{verbatim} 498 | 00010040 la x10,var1 499 | 00010048 ... # note that the la pseudoinstruction expands into 8 bytes 500 | ... 501 | 502 | var1: 503 | 00010900 .word 999 # a 32-bit integer constant stored in memory at address var1 504 | \end{verbatim} 505 | } 506 | The \verb@la@ instruction in this example will expand into: 507 | {\small 508 | \begin{verbatim} 509 | 00010040 auipc x10,((var1-.) + 0x00000800) >> 12 510 | 00010044 addi x10,x10,((var1-(.-4)) & 0x00000fff) 511 | \end{verbatim} 512 | } 513 | 514 | Note that \verb@auipc@ will shift the immediate operand to the left 12 bits and then 515 | add that to the \verb@pc@ register (see \autoref{insn:auipc}.) 516 | 517 | The assembler will calculate the value of \verb@(var1-.)@ by subtracting the address 518 | represented by the label \verb@var1@ from the address of the current instruction 519 | (which is expressed as '.') resulting in the number of bytes from the current instruction 520 | to the target label\ldots{} which is \verb@0x000008c0@. 521 | 522 | Therefore the expanded pseudoinstruction example will become: 523 | {\small 524 | \begin{verbatim} 525 | 00010040 auipc x10,((0x00010900 - 0x00010040) + 0x00000800) >> 12 526 | 00010044 addi x10,x10,((0x00010900 - (0x00010044 - 4)) & 0x00000fff) # note the extra -4 here! 527 | \end{verbatim} 528 | } 529 | After performing the subtractions, it will reduce to this: 530 | {\small 531 | \begin{verbatim} 532 | 00010040 auipc x10,(0x000008c0 + 0x00000800) >> 12 533 | 00010044 addi x10,x10,(0x000008c0 & 0x00000fff) 534 | \end{verbatim} 535 | } 536 | Continuing to reduce the math operations we get: 537 | {\small 538 | \begin{verbatim} 539 | 00010040 auipc x10,0x00001 # 0x000008c0 + 0x00000800 = 0x000010c0 540 | 00010044 addi x10,x10,0x8c0 541 | \end{verbatim} 542 | } 543 | 544 | Note that the \verb@la@ pseudoinstruction exhibits the same sort of technique as 545 | the \verb@li@ in that 546 | if/when the immediate operand of the \verb@addi@ instruction has its most significant 547 | bit set then the operand in the \verb@auipc@ has to be incremented by 1 to compensate. 548 | 549 | 550 | 551 | 552 | 553 | 554 | 555 | 556 | \section{Relocation} 557 | 558 | Because expressions that refer to constants and address labels are common in 559 | assembly language programs, a shorthand notation is available for calculating 560 | the pairs of values that are used in the implementation of things like the 561 | \verb@li@ and \verb@la@ pseudoinstructions (that have to be written to 562 | compensate for the sign-extension that will take place in the immediate operand 563 | that appears in instructions like \verb@addi@ and \verb@jalr@.) 564 | 565 | \subsection{Absolute Addresses} 566 | 567 | To refer to an absolute value, the following operators can be used: 568 | {\small 569 | \begin{verbatim} 570 | %hi(constant) // becomes: (constant + 0x00000800) >> 12 571 | %lo(constant) // becomes: (constant & 0x00000fff) 572 | \end{verbatim} 573 | } 574 | 575 | Thus, the \verb@li@ pseudoinstruction can, therefore, be expressed like this: 576 | 577 | {\small 578 | \begin{verbatim} 579 | li rd,constant lui rd,%hi(constant) 580 | addi rd,rd,%lo(constant) 581 | \end{verbatim} 582 | } 583 | 584 | 585 | 586 | \subsection{PC-Relative Addresses} 587 | 588 | The following can be used for PC-relative addresses: 589 | {\small 590 | \begin{verbatim} 591 | %pcrel_hi(symbol) // becomes: ((symbol-.) + 0x0800) >> 12 592 | %pcrel_lo(lab) // becomes: ((symbol-lab) & 0x00000fff) 593 | \end{verbatim} 594 | } 595 | 596 | Note the subtlety involved with the \verb@lab@ on \verb@%pcrel_lo@. It is needed to 597 | determine the address of the instruction that contains the corresponding \verb@%pcrel_hi@. 598 | (The label \verb@lab@ MUST be on a line that used a \verb@%pcrel_hi()@ or get an 599 | error from the assembler.) 600 | 601 | Thus, the \verb@la rd,label@ pseudoinstruction can be expressed like this: 602 | {\small 603 | \begin{verbatim} 604 | xxx: auipc rd,%pcrel_hi(label) 605 | addi rd,rd,%pcrel_lo(xxx) // the xxx tells pcrel_lo where to find the matching pcrel_hi 606 | \end{verbatim} 607 | } 608 | 609 | Examples of using the \verb@auipc@ \& \verb@addi@ together with \verb@%pcrel_hi()@ and 610 | \verb@%pcrel_lo()@: 611 | 612 | {\small 613 | \begin{verbatim} 614 | xxx: auipc t1,%pcrel_hi(yyy) // ((yyy-.) + 0x0800) >> 12 615 | addi t1,t1,%pcrel_lo(xxx) // ((yyy-xxx) & 0x00000fff) 616 | ... 617 | yyy: // the address: yyy is saved into t1 above 618 | ... 619 | \end{verbatim} 620 | } 621 | 622 | 623 | Referencing the same \verb@%pcrel_hi@ in multiple subsequent uses of \verb@%pcrel_lo@ is legal: 624 | {\small 625 | \begin{verbatim} 626 | label: auipc t1,%pcrel_hi(symbol) 627 | addi t2,t1,%pcrel_lo(label) // t2 = symbol 628 | addi t3,t1,%pcrel_lo(label) // t3 = symbol 629 | lw t4,%pcrel_lo(label)(t1) // t4 = fetch value from memory at 'symbol' 630 | addi t4,t4,123 // t4 = t4 + 123 631 | sw t4,%pcrel_lo(label)(t1) // store t4 back into memory at 'symbol' 632 | \end{verbatim} 633 | } 634 | 635 | 636 | 637 | 638 | 639 | \section{Relaxation} 640 | 641 | %\enote{I'm not sure I want to get into the details of how this is done. Just assume it works.}% 642 | In the simplest of terms, {\em Relaxation} refers to the ability of the 643 | linker (not the compiler!) to determine if/when the instructions that 644 | were generated with the \verb@xxx_hi@ and \verb@xxx_lo@ operators are 645 | unneeded (and thus waste execution time and memory) and can therefore 646 | be removed. 647 | 648 | However, doing so is not trivial as it will result in moving things around 649 | in memory, possibly changing the values of address labels in the 650 | already-assembled program! Therefore, while the motivation for 651 | rexation is obvious, the process of implementing it is non-trivial. 652 | 653 | See: \url{https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md} 654 | --------------------------------------------------------------------------------