├── .github └── FUNDING.yml ├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── cc └── exp_lut.cc ├── doc ├── DC_removal.pdf ├── ay_model.v ├── conn.md ├── lab.ods └── resistors.ods ├── hdl ├── filter │ ├── jt49_dcrm.v │ ├── jt49_dcrm2.v │ ├── jt49_dly.v │ └── jt49_mave.v ├── jt49.v ├── jt49_bus.v ├── jt49_cen.v ├── jt49_div.v ├── jt49_eg.v ├── jt49_exp.v └── jt49_noise.v ├── lab ├── dual │ └── dual.ino ├── io │ └── io.ino ├── kicad │ ├── .gitignore │ ├── arduino.kicad_pcb │ ├── arduino.kicad_prl │ ├── arduino.kicad_pro │ ├── arduino.kicad_sch │ └── sym-lib-table ├── sweep │ └── sweep.ino └── ym2203 │ ├── DS1Z_QuickPrint20.png │ ├── DS1Z_QuickPrint23.png │ └── ym2203_setup.jpeg ├── lut ├── go.mod └── main.go ├── syn └── quartus │ └── jt49.qip └── ver ├── clkdiv ├── go └── test.v ├── comp ├── cmd.hex ├── gather.f ├── go.sh ├── parser.awk ├── test.v └── test_cmd ├── dcrm ├── go.sh └── test.v ├── eg ├── go └── test.v ├── model ├── sim.sh ├── test.v ├── tnzso16.bin ├── tnzso16.v └── tnzso16.vcd └── top ├── gather.f ├── go └── test.v /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | github: jotego 2 | patreon: jotego 3 | custom: ["https://www.paypal.me/topapate"] 4 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | */history/* 2 | history/* 3 | sim 4 | *.lxt 5 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jotego/jt49/7f6abfd08a2af9a92dbd5b32c71ea773248a77e2/.gitmodules -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # JT49 FPGA Clone of YM2149 hardware by Jose Tejada (@topapate) 2 | 3 | You can show your appreciation through 4 | 5 | * [Patreon](https://patreon.com/jotego), by supporting open source retro releases 6 | 7 | YM2149 compatible Verilog core, with emphasis on FPGA implementation as part of JT12 in order to recreate the YM2203 part. 8 | 9 | ## Documentation 10 | 11 | - [AY-3-8910 Data Manual](https://archive.org/details/AY-3-8910-8912_Feb-1979/page/n51/mode/2up) 12 | - [AY-3-8919 Reverse Engineered](https://github.com/lvd2/ay-3-8910_reverse_engineered) 13 | - [YM2149](https://archive.org/details/bitsavers_yamahaYM21_3070829) 14 | 15 | ## Using JT49 in a git project 16 | 17 | If you are using JT49 in a git project, the best way to add it to your project is: 18 | 19 | 1. Optionally fork JT49's repository to your own GitHub account 20 | 2. Add it as a submodule to your git project: `git submodule add https://github.com/jotego/jt49.git` 21 | 3. Now you can refer to the RTL files in **jt49/hdl** 22 | 23 | The advantages of a using a git submodule are: 24 | 25 | 1. Your project contains a reference to a commit of the JT49 repository 26 | 2. As long as you do not manually update the JT49 submodule, it will keep pointing to the same commit 27 | 3. Each time you make a commit in your project, it will include a pointer to the JT49 commit used. So you will always know the JT49 that worked for you 28 | 4. If JT49 is updated and you want to get the changes, simply update the submodule using git. The new JT49 commit used will be annotated in your project's next commit. So the history of your project will reflect that change too. 29 | 5. JT49 files will be intact and you will use the files without altering them. 30 | 31 | ## Usage 32 | 33 | There are two top level files you can use: 34 | - **jt49_bus**: presents the expected AY-3-8910 interface 35 | - **jt49**: presents a simplified interface, ideal to embed. This is the one used by jt12 36 | 37 | clk_en cannot be set to 1 for correct operation. The design assumes that there will be at least one empty clock cycle between every two clk_en high clock cycles. 38 | 39 | ## Files for Simulation and Synthesis 40 | 41 | When used inside a [JTFRAME](https://github.com/jotego/jtframe) project, you can use the [yaml](hdl/jt49.yaml) file provided. If you are using this repository on its own, there is a [qip](syn/quartus/jt49.qip) for Intel Quartus available. 42 | 43 | It is recommended to use this repository as a [git submodule](https://git-scm.com/book/en/v2/Git-Tools-Submodules) in your project. 44 | 45 | 46 | ## Port Description jt49 47 | 48 | Name | Direction | Width | Purpose 49 | ---------|-----------|-------|------------------------------------- 50 | rst_n | input | | active-low asynchronous reset signal 51 | clk | input | | clock 52 | clk_en | input | | clock enable. It cannot be a permanent 1 53 | addr | input | 4 | selects the register to access to 54 | cs_n | input | | chip-select, active low 55 | wr_n | input | | active-low write signal 56 | din | input | 8 | data to write to registers 57 | sel | input | | input clock is further divided by 2 when low 58 | dout | output | 8 | data read from registers. Updated when cs_n is low 59 | sound | output | 10 | Unsigned combined output of the three channels 60 | A | output | 8 | Unsigned output of channel A 61 | B | output | 8 | Unsigned output of channel B 62 | C | output | 8 | Unsigned output of channel C 63 | 64 | The module is not designed to be used at full clk speed. The clock enable input signal should divide the clock at least by two. This is needed because the volume LUT is shared for all three channels and the pipeline does not include wait states for the LUT as wait states happen naturally when clk_en is used. 65 | 66 | The ports of **jt49_bus** replace the CPU interface with that of the original AY-3-8910. 67 | 68 | Name | Direction | Width | Purpose 69 | ---------|-----------|-------|------------------------------------- 70 | rst_n | input | | active-low asynchronous reset signal 71 | clk | input | | clock 72 | clk_en | input | | clock enable. It cannot be a permanent 1 73 | bdir | input | | bdir pin of AY-3-8910 74 | bc1 | input | | bc1 pin of AY-3-8910 75 | din | input | 8 | data to write to registers 76 | sel | input | | input clock is further divided by 2 when low 77 | dout | output | 8 | data read from registers. Updated when cs_n is low 78 | sound | output | 10 | Unsigned combined output of the three channels 79 | A | output | 8 | Unsigned output of channel A 80 | B | output | 8 | Unsigned output of channel B 81 | C | output | 8 | Unsigned output of channel C 82 | IOA_in | input | 8 | I/O port A, input side 83 | IOA_in | output | 8 | I/O port A, output side 84 | IOB_in | input | 8 | I/O port B, input side 85 | IOB_in | output | 8 | I/O port B, output side 86 | 87 | ## Comparison with AY-3-8910 Verilog Model 88 | 89 | A simulation test bench of jt49 vs the AY-3-8910 model (available in the doc folder via a git submodule) is available in folder ver/comp. The simulation uses a simple text file to enter arbitrary commands (test_cmd). The command file is converted to hexadecimal by parser.awk and used in simulation. The following parameters were tested: 90 | 91 | Item | Compliance | Remarks 92 | ---------------------|------------------|------------------------------- 93 | channel period | Yes | Tested: 0, 1 and FFFF values 94 | noise period | Yes | Tested: 0, 7 and 1F values 95 | envelope shape | Yes | Tested all 16 shapes 96 | envelope period | Yes | Tested 0 and FFF values 97 | 98 | ## Resistor Load Modelling 99 | 100 | The YM2149 was used to measure the output circuitry. According to AY-3-8910 schematics, there are 16 NMOS devices for each channel. Depending on the amplitude settings, only one of them will be active. These numbers render values that agree with the datasheet and measurements: 101 | 102 | - Rload = 1 kOhm 103 | - Smallest Ron = 900 Ohm (for level=15) 104 | - Largest Roff = 3 MOhm (for level=0) 105 | - Scale factor from one MOS to the next = 1.55 106 | 107 | Each output level is the combination of one MOS being on and the rest off, so they combine into a single impedance, which then forms a resistor divider with the load. 108 | 109 | The output MOS will hold its impedance even if an extra 1V is added at the load resistor (reducing the MOS headroom) 110 | 111 | ## Non Linear Effects 112 | 113 | - Channel mixing effects by short circuiting the outputs in AY-3-8910 are not modelled 114 | - Non linearity in YM2203 when shorting all outputs is modeled via parameter YM2203_LUMPED 115 | 116 | Non linear effects depend on the way the chip is connected and its model. See [the connection list](doc/conn.md). 117 | 118 | ## Related Projects 119 | 120 | Other sound chips from the same author 121 | 122 | Chip | Repository 123 | -----------------------|------------ 124 | YM2203, YM2612, YM2610 | [JT12](https://github.com/jotego/jt12) 125 | YM2151 | [JT51](https://github.com/jotego/jt51) 126 | YM3526 | [JTOPL](https://github.com/jotego/jtopl) 127 | YM2149 | [JT49](https://github.com/jotego/jt49) 128 | sn76489an | [JT89](https://github.com/jotego/jt89) 129 | OKI 6295 | [JT6295](https://github.com/jotego/jt6295) 130 | OKI MSM5205 | [JT5205](https://github.com/jotego/jt5205) 131 | NEC uPN7759 | [JT7759](https://github.com/jotego/jt7759) -------------------------------------------------------------------------------- /cc/exp_lut.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | using namespace std; 5 | 6 | int main() { 7 | float ex[4] = {4,6,8,13}; 8 | int lut[4][32]; 9 | for( int i=0; i<4; i++ ) { 10 | float f=255; 11 | float e=1.0/pow(2, 1.0/ex[i] ); 12 | // cout << e << '\n'; 13 | lut[i][31]=255; 14 | for(int j=30; j>0; j-- ) { 15 | f=f*e; 16 | lut[i][j] = (int)f; 17 | } 18 | lut[i][0]=0; 19 | } 20 | for( int i=0; i<4; i++) 21 | for( int j=0; j<32; j++ ) { 22 | int v = (i<<5)|j; 23 | cout << "\tlut[" << v << "] = 8'd" << lut[i][j] << ";\n"; 24 | } 25 | } -------------------------------------------------------------------------------- /doc/DC_removal.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jotego/jt49/7f6abfd08a2af9a92dbd5b32c71ea773248a77e2/doc/DC_removal.pdf -------------------------------------------------------------------------------- /doc/ay_model.v: -------------------------------------------------------------------------------- 1 | // (c) 2019 deathsoft, lvd 2 | 3 | // This verilog model of the AY chip was made from the transistor-level schematics 4 | // recreated by deathsoft. He used high-resolution photos of the AY's decapped die. 5 | // 6 | // The purpose of this model is to be as close to the schematics as possible, 7 | // wihout ever trying to be synthesizable. Suitable only for simulations! 8 | // 9 | // As a consequence, the timing delays are used explicitly, however they do not 10 | // relate in any way to the timing delays of the real chip. They are used only 11 | // to achieve correct signal precedence in the places where this is important, 12 | // like flip-flops or asynchronous self-reset circuits. 13 | // 14 | // Sound output is not analog (obviously!), instead codes 0..15 are used: 15 | // 0 -- AY DAC output is disconnected (no current), 16 | // 1..15 -- AY DAC output sources corresponding current level. 17 | // Every current level is determined by the size of the corresponding transistor. There are 18 | // 15 transistors in total, only one of them is open at output levels 1..15 and no one at level 0. 19 | // 20 | // You need additional table lookups to convert these 0..15 levels to appropriate sound values. 21 | 22 | // naming conventions: 23 | // While in the schematics all names are upper-case, here they all are lower-case. 24 | // 25 | // When name in schematics starts with / (inverse), here we use first _ (underscore), like 26 | // "/A9" becomes "_a9" 27 | // 28 | // When there is obviously a bus of some type, it is bus also in verilog, like all 29 | // DA0, DA1,..., DA7 become "wire [7:0] da" 30 | 31 | /* This file is part of AY-3-8910 restoration and preservation project. 32 | 33 | AY-3-8910 restoration and preservation project is free software: you 34 | can redistribute it and/or modify it under the terms of the 35 | GNU General Public License as published by the Free Software Foundation, 36 | either version 3 of the License, or (at your option) any later version. 37 | 38 | AY-3-8910 restoration and preservation project is distributed in the 39 | hope that it will be useful, but WITHOUT ANY WARRANTY; without even 40 | the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 41 | PURPOSE. See the GNU General Public License for more details. 42 | 43 | You should have received a copy of the GNU General Public License 44 | along with Foobar. If not, see . 45 | */ 46 | 47 | 48 | 49 | `timescale 100ns/1ns // arbitrary values, with the exception that the second time value must be 50 | // 1/100 of the first one. 51 | 52 | 53 | module ay_model 54 | ( 55 | // clock & reset 56 | input wire clk, // Simple clock, AY outputs sound at clk/8 rate. 57 | // For example: at 1.75 MHz clock, sound rate will be 218.75 kHz 58 | 59 | input wire _rst, // Negative asynchronous reset. When _rst=0, chip is under reset. 60 | // The reset will set all AY registers to zero, 61 | // initialize phases of tone and noise generators, 62 | // and initialize the phase of internal clk->clk/8 divider. 63 | 64 | // bus & control 65 | inout wire [7:0] da, // 8 bit I/O bus 66 | // 67 | input wire bdir, // Asynchronous bus control signals. The AY captures data for the internal registers from 'da' bus 68 | input wire bc2, // by driving enables on internal latches asynchronously by these signals. 69 | input wire bc1, // Short help on using those signals: 70 | // 71 | // {bdir, bc2, bc1} | bus operation 72 | // -----------------+--------------- 73 | // either of | Select register (number is da[3:0]) for subsequent read or write. 74 | // 0 0 1 | Selection only succeedes when da[7:4]==0, 75 | // 1 0 0 | a8=1 and _a9=0, otherwise AY gets 'unselected', 76 | // 1 1 1 | i.e. it won't react on subsequent reads or writes. 77 | // -----------------+--------------- 78 | // 1 1 0 | write the contents of the 'da' bus into the previously selected AY register 79 | // -----------------+--------------- 80 | // 0 1 1 | read contents of the previously selected AY register to the 'da' bus 81 | // -----------------+--------------- 82 | // any other values | ignore anything on the bus and do not change selected register (idle state) 83 | 84 | input wire a8, // additional selection signals, see above 85 | input wire _a9, // 86 | 87 | // gpio 88 | inout wire [7:0] ioa, // bidirectional GPIO pins. 89 | inout wire [7:0] iob, // Unlike it is in real AY, there are no pullups on these pins. 90 | // If you need some, try using 'tri1' instead of 'wire' 91 | // for the signals that connect here. 92 | 93 | // test pins 94 | output wire test1, // outputs the frequency that drives envelope state machine, 95 | // its frequency is Fclk/(16*envelope_period). 96 | 97 | input wire test2, // put here 1'b0 for normal work. Otherwise 98 | // AY won't do any register reads or writes, while 99 | // the register selections will still work. 100 | 101 | // sound outputs (see comments above) 102 | output wire [3:0] ch_a, // Logical sound levels, from 0 to 15. 103 | output wire [3:0] ch_b, // You need an additional table lookup if you want real 104 | output wire [3:0] ch_c // sound levels. 105 | // Because AY is an asynchronous design and because here we 106 | // emulate the delays of internal latches where it is necessary, 107 | // there are glitches on these pins. 108 | ); 109 | 110 | 111 | wire rst_1; // actual internal reset 112 | 113 | wire f1,_f1; // internal clock phases 114 | 115 | wire cnt_clk; // short clk strobe 116 | 117 | wire _bdir, _bc2, _bc1; // internal copies of bdir/bc2/bc1 118 | wire bdir_1, bc2_1, bc1_1; 119 | 120 | wire psg_cs, _psg_cs; 121 | 122 | wire da_latch_wr, _da_latch_wr; 123 | 124 | wire psg_sel, _psg_sel; 125 | 126 | wire _da_out_en; 127 | wire reg_wr, _reg_wr, reg_wr_2; 128 | 129 | wire [3:0] d_latch_1; 130 | wire [3:0] _d_latch_1; 131 | 132 | wire _internal_sel; 133 | 134 | wire sel_r0, sel_r1, sel_r2, sel_r3, 135 | sel_r4, sel_r5, sel_r6, sel_r7, 136 | sel_r10, sel_r11, sel_r12, sel_r13, 137 | sel_r14, sel_r15; 138 | 139 | wire _sel_r16, _sel_r17; 140 | 141 | wire [7:0] b; 142 | 143 | wire [7:0] r7_b; // tone/noise enable 144 | 145 | wire [4:0] noise_period; // noise period 146 | wire [4:0] _noise_period; 147 | 148 | wire noise_carry_out; 149 | 150 | wire noise_latch_up_phase, noise_latch_dn_phase; 151 | 152 | wire pre_f4; 153 | wire _f4,f4; 154 | 155 | 156 | wire [15:0] env_period; // envelope period 157 | wire [15:0] _env_period; 158 | 159 | wire [3:0] env_mode; // envelope mode 160 | 161 | wire env_rst; // envelope reset 162 | 163 | wire ep_rst; // envelope period counter reset 164 | 165 | wire env_carry_out; // from period counter 166 | 167 | wire env_phase_up; 168 | wire env_phase_dn; 169 | 170 | wire f_env; // envelope frequency 171 | 172 | wire [3:0] e; // envelope volume level 173 | wire [3:0] e_mx; // pre-envelope 174 | 175 | wire _env_en; 176 | 177 | wire sel_ea; 178 | wire _sel_ea; 179 | 180 | wire f_env_dis; // enable envelope state machine clocking 181 | 182 | wire env_clk_up; 183 | wire env_clk_dn; 184 | 185 | 186 | 187 | 188 | wire _r7_b6_1, _r7_b7_1; // dir bits for GPIO 189 | wire wr_r16_1, _en_r16_rd; //extra signals to control GPIO registers 190 | wire wr_r17_1, _en_r17_rd; // 191 | 192 | wire noise; // noise bitstream 193 | 194 | wire [16:0] noise_reg; // noise latches 195 | 196 | 197 | 198 | 199 | 200 | /* RESET conditioning */ 201 | assign rst_1 = ~_rst; 202 | 203 | 204 | 205 | /* CLOCK preconditioning and division */ 206 | wire int_clk_n, int_clk_nn; 207 | 208 | wire int_clk_up,int_clk_dn; // inputs to division chain 209 | 210 | assign int_clk_n = ~clk; 211 | assign int_clk_nn = ~int_clk_n; 212 | 213 | ay_model_rs_ff in_clk_conditioning 214 | ( 215 | .reset( int_clk_nn ), 216 | . set( int_clk_n ), 217 | .q ( int_clk_dn ), 218 | ._q ( int_clk_up ) 219 | ); 220 | 221 | wire int_clk_div2_up, int_clk_div2_dn; 222 | 223 | ay_model_clk_ff ckdiv2 224 | ( 225 | .up_phase(int_clk_up), 226 | .dn_phase(int_clk_dn), 227 | .set(1'b0), 228 | .rst(rst_1), 229 | 230 | .q_up(int_clk_div2_up), 231 | .q_dn(int_clk_div2_dn) 232 | ); 233 | 234 | wire int_clk_div4_up, int_clk_div4_dn; 235 | 236 | ay_model_clk_ff ckdiv4 237 | ( 238 | .up_phase(int_clk_div2_up), 239 | .dn_phase(int_clk_div2_dn), 240 | .set(1'b0), 241 | .rst(rst_1), 242 | 243 | .q_up(int_clk_div4_up), 244 | .q_dn(int_clk_div4_dn) 245 | ); 246 | 247 | wire int_clk_div8_up, int_clk_div8_dn; 248 | 249 | ay_model_clk_ff ckdiv8 250 | ( 251 | .up_phase(int_clk_div4_up), 252 | .dn_phase(int_clk_div4_dn), 253 | .set(1'b0), 254 | .rst(rst_1), 255 | 256 | .q_up(int_clk_div8_up), 257 | .q_dn(int_clk_div8_dn) 258 | ); 259 | 260 | // make output phases 261 | ay_model_rs_ff main_clk_phases 262 | ( 263 | .reset(int_clk_div8_up), 264 | . set(int_clk_div8_dn), 265 | . q(_f1), 266 | . _q( f1) 267 | ); 268 | 269 | // make strobe 270 | assign cnt_clk = ~(int_clk_div2_up | int_clk_div4_up | int_clk_div8_dn); 271 | 272 | 273 | 274 | 275 | /* internal copies of BDIR BC1 BC2 */ 276 | assign _bdir = ~bdir; 277 | assign _bc2 = ~bc2; 278 | assign _bc1 = ~bc1; 279 | 280 | assign bdir_1 = ~_bdir; 281 | assign bc2_1 = ~_bc2; 282 | assign bc1_1 = ~_bc1; 283 | 284 | 285 | 286 | 287 | /* PSG_CS and /PSG_CS */ 288 | wire int__a9_1, int__a8; 289 | wire int_da7_4; 290 | 291 | assign int__a9_1 = _a9; 292 | assign int__a8 = ~a8; 293 | 294 | assign int_da7_4 = |da[7:4]; 295 | 296 | assign psg_cs = ~(int__a9_1 | int__a8 | int_da7_4); 297 | assign _psg_cs = ~psg_cs; 298 | 299 | 300 | 301 | /* DA_LATCH_WR and /DA_LATCH_WR */ 302 | wire int_bsigs_001, // goes to 1 when {bdir,bc2,bc1} have corresponding pattern 303 | int_bsigs_111, 304 | int_bsigs_100; 305 | 306 | wire int_bsigs_wracc; 307 | 308 | assign int_bsigs_001 = ~( bdir_1 | bc2_1 | _bc1 ); 309 | assign int_bsigs_111 = ~( _bdir | _bc2 | _bc1 ); 310 | assign int_bsigs_100 = ~( _bdir | bc2_1 | bc1_1 ); 311 | 312 | assign int_bsigs_wracc = ~( int_bsigs_001 | int_bsigs_111 | int_bsigs_100 ); 313 | 314 | assign da_latch_wr = ~( _psg_cs | int_bsigs_wracc ); 315 | assign _da_latch_wr = ~da_latch_wr; 316 | 317 | 318 | 319 | /* PSG_SEL and /PSG_SEL */ 320 | wire int_psgwren_ffset, 321 | int_psgwren_ffrst; 322 | 323 | wire int_psgwren_q; 324 | 325 | assign int_psgwren_ffset = ~( int_bsigs_wracc | psg_cs ); 326 | assign int_psgwren_ffrst = da_latch_wr; 327 | 328 | ay_model_rs_ff make_psg_sel 329 | ( 330 | .reset(int_psgwren_ffrst), 331 | . set(int_psgwren_ffset | rst_1), 332 | . q(int_psgwren_q ), 333 | . _q( ) 334 | ); 335 | 336 | assign psg_sel = ~( int_psgwren_q | int_psgwren_ffrst ); 337 | assign _psg_sel = ~psg_sel; 338 | 339 | 340 | 341 | /* /DA_OUT_EN, REG_WR and /REG_WR */ 342 | wire int_psg_wr, int_psg_rd; 343 | 344 | wire int_pre_wr; 345 | 346 | assign int_psg_wr = ~(test2 | _bdir | _bc2 | bc1_1); // 110 347 | assign int_psg_rd = ~(test2 | bdir_1 | _bc2 | _bc1 ); // 011 348 | 349 | assign _da_out_en = ~(int_psg_rd & psg_sel); 350 | 351 | assign int_pre_wr = ~(psg_sel & int_psg_wr); 352 | 353 | assign reg_wr = ~(int_pre_wr & (~rst_1)); 354 | 355 | assign _reg_wr = ~reg_wr; 356 | 357 | 358 | 359 | /* REG_WR_2 */ 360 | assign reg_wr_2 = ~_reg_wr; 361 | 362 | 363 | 364 | /* D0_LATCH_1, /D0_LATCH_1, ..., D3_LATCH_1, /D3_LATCH_1 */ 365 | wire [3:0] int_reg_addr_pos; 366 | wire [3:0] int_reg_addr_neg; 367 | 368 | ay_model_latch 369 | #( 370 | .WIDTH(4) 371 | ) 372 | regaddr_latch 373 | ( 374 | .load ( da_latch_wr), 375 | .store(_da_latch_wr), 376 | 377 | .d(~da[3:0]), 378 | . q(int_reg_addr_neg), 379 | ._q(int_reg_addr_pos) 380 | ); 381 | 382 | assign d_latch_1 = ~( {4{rst_1}} | int_reg_addr_neg); 383 | assign _d_latch_1 = ~( {4{rst_1}} | int_reg_addr_pos); 384 | 385 | 386 | 387 | /* /INTERNAL_SEL */ 388 | assign _internal_sel = ~(psg_sel | rst_1); 389 | 390 | 391 | 392 | /* SEL_R*, /SEL_R16, /SEL_R17 */ 393 | assign sel_r0 = ~(_internal_sel | d_latch_1[3] | d_latch_1[2] | d_latch_1[1] | d_latch_1[0]); 394 | assign sel_r1 = ~(_internal_sel | d_latch_1[3] | d_latch_1[2] | d_latch_1[1] | _d_latch_1[0]); 395 | assign sel_r2 = ~(_internal_sel | d_latch_1[3] | d_latch_1[2] | _d_latch_1[1] | d_latch_1[0]); 396 | assign sel_r3 = ~(_internal_sel | d_latch_1[3] | d_latch_1[2] | _d_latch_1[1] | _d_latch_1[0]); 397 | assign sel_r4 = ~(_internal_sel | d_latch_1[3] | _d_latch_1[2] | d_latch_1[1] | d_latch_1[0]); 398 | assign sel_r5 = ~(_internal_sel | d_latch_1[3] | _d_latch_1[2] | d_latch_1[1] | _d_latch_1[0]); 399 | assign sel_r6 = ~(_internal_sel | d_latch_1[3] | _d_latch_1[2] | _d_latch_1[1] | d_latch_1[0]); 400 | assign sel_r7 = ~(_internal_sel | d_latch_1[3] | _d_latch_1[2] | _d_latch_1[1] | _d_latch_1[0]); 401 | assign sel_r10 = ~(_internal_sel | _d_latch_1[3] | d_latch_1[2] | d_latch_1[1] | d_latch_1[0]); 402 | assign sel_r11 = ~(_internal_sel | _d_latch_1[3] | d_latch_1[2] | d_latch_1[1] | _d_latch_1[0]); 403 | assign sel_r12 = ~(_internal_sel | _d_latch_1[3] | d_latch_1[2] | _d_latch_1[1] | d_latch_1[0]); 404 | assign sel_r13 = ~(_internal_sel | _d_latch_1[3] | d_latch_1[2] | _d_latch_1[1] | _d_latch_1[0]); 405 | assign sel_r14 = ~(_internal_sel | _d_latch_1[3] | _d_latch_1[2] | d_latch_1[1] | d_latch_1[0]); 406 | assign sel_r15 = ~(_internal_sel | _d_latch_1[3] | _d_latch_1[2] | d_latch_1[1] | _d_latch_1[0]); 407 | 408 | assign _sel_r16 = (_internal_sel | _d_latch_1[3] | _d_latch_1[2] | _d_latch_1[1] | d_latch_1[0]); 409 | assign _sel_r17 = (_internal_sel | _d_latch_1[3] | _d_latch_1[2] | _d_latch_1[1] | _d_latch_1[0]); 410 | 411 | 412 | 413 | /* B7..B0 <> DA7..DA0 */ 414 | assign b = _psg_sel ? 8'd0 : (_reg_wr ? 8'bZ : da); 415 | 416 | assign da = _da_out_en ? 8'bZ : b; 417 | 418 | 419 | 420 | /* R7_B0..7 */ 421 | ay_model_rw_latch reg7 422 | ( 423 | .gate (sel_r7), 424 | .write(reg_wr), 425 | .store(_reg_wr), 426 | 427 | .d(b), 428 | 429 | . q(r7_b), 430 | ._q() 431 | ); 432 | 433 | 434 | /* noise period */ 435 | ay_model_rw_latch #( .WIDTH(5) ) reg6 436 | ( 437 | .gate (sel_r6), 438 | .write(reg_wr_2), 439 | .store(_reg_wr), 440 | 441 | .d(b[4:0]), 442 | 443 | . q( noise_period), 444 | ._q(_noise_period) 445 | ); 446 | 447 | /* envelope period */ 448 | ay_model_rw_latch reg13 449 | ( 450 | .gate (sel_r13), 451 | .write(reg_wr), 452 | .store(_reg_wr), 453 | 454 | .d(b), 455 | 456 | . q( env_period[7:0]), 457 | ._q(_env_period[7:0]) 458 | ); 459 | ay_model_rw_latch reg14 460 | ( 461 | .gate (sel_r14), 462 | .write(reg_wr), 463 | .store(_reg_wr), 464 | 465 | .d(b), 466 | 467 | . q( env_period[15:8]), 468 | ._q(_env_period[15:8]) 469 | ); 470 | 471 | /* envelope mode */ 472 | ay_model_rw_latch #( .WIDTH(4) ) reg15 473 | ( 474 | .gate (sel_r15), 475 | .write(reg_wr), 476 | .store(_reg_wr), 477 | 478 | .d(b[3:0]), 479 | 480 | . q(env_mode), 481 | ._q() 482 | ); 483 | 484 | 485 | 486 | /* GPIO */ 487 | assign _r7_b6_1 = ~r7_b[6]; 488 | assign _r7_b7_1 = ~r7_b[7]; 489 | 490 | assign wr_r16_1 = ~(_sel_r16 | _reg_wr); 491 | assign wr_r17_1 = ~(_sel_r17 | _reg_wr); 492 | 493 | assign _en_r16_rd = _sel_r16 | reg_wr; 494 | assign _en_r17_rd = _sel_r17 | reg_wr; 495 | 496 | ay_model_gpio ioa_block 497 | ( 498 | .b (b ), 499 | .io(ioa), 500 | 501 | ._reg_wr (_reg_wr ), 502 | .wr_reg_1 (wr_r16_1 ), 503 | ._r7_b_1 (_r7_b6_1 ), 504 | ._en_reg_rd(_en_r16_rd) 505 | ); 506 | 507 | ay_model_gpio iob_block 508 | ( 509 | .b (b ), 510 | .io(iob), 511 | 512 | ._reg_wr (_reg_wr ), 513 | .wr_reg_1 (wr_r17_1 ), 514 | ._r7_b_1 (_r7_b7_1 ), 515 | ._en_reg_rd(_en_r17_rd) 516 | ); 517 | 518 | 519 | 520 | /* AY channels */ 521 | ay_model_channel channel_a 522 | ( 523 | . f1 ( f1), 524 | ._f1 (_f1), 525 | .cnt_clk(cnt_clk), 526 | 527 | .rst_1(rst_1), 528 | 529 | . reg_wr( reg_wr), 530 | ._reg_wr(_reg_wr), 531 | .sel_tone_lo(sel_r0), 532 | .sel_tone_hi(sel_r1), 533 | .sel_vol (sel_r10), 534 | 535 | .b(b), 536 | 537 | ._noise_en(r7_b[3]), 538 | ._tone_en (r7_b[0]), 539 | 540 | .e (e ), 541 | .noise(noise), 542 | 543 | .sound(ch_a) 544 | ); 545 | 546 | ay_model_channel channel_b 547 | ( 548 | . f1 ( f1), 549 | ._f1 (_f1), 550 | .cnt_clk(cnt_clk), 551 | 552 | .rst_1(rst_1), 553 | 554 | . reg_wr( reg_wr), 555 | ._reg_wr(_reg_wr), 556 | .sel_tone_lo(sel_r2), 557 | .sel_tone_hi(sel_r3), 558 | .sel_vol (sel_r11), 559 | 560 | .b(b), 561 | 562 | ._noise_en(r7_b[4]), 563 | ._tone_en (r7_b[1]), 564 | 565 | .e (e ), 566 | .noise(noise), 567 | 568 | .sound(ch_b) 569 | ); 570 | 571 | ay_model_channel channel_c 572 | ( 573 | . f1 ( f1), 574 | ._f1 (_f1), 575 | .cnt_clk(cnt_clk), 576 | 577 | .rst_1(rst_1), 578 | 579 | . reg_wr( reg_wr), 580 | ._reg_wr(_reg_wr), 581 | .sel_tone_lo(sel_r4), 582 | .sel_tone_hi(sel_r5), 583 | .sel_vol (sel_r12), 584 | 585 | .b(b), 586 | 587 | ._noise_en(r7_b[5]), 588 | ._tone_en (r7_b[2]), 589 | 590 | .e (e ), 591 | .noise(noise), 592 | 593 | .sound(ch_c) 594 | ); 595 | 596 | 597 | 598 | /* noise generation */ 599 | ay_model_rs_ff noise_clk_conditioning 600 | ( 601 | .reset(_f1), 602 | . set(rst_1 | (cnt_clk & noise_carry_out)), 603 | 604 | . q(noise_latch_up_phase), 605 | ._q(noise_latch_dn_phase) 606 | ); 607 | // 608 | ay_model_clk_ff noise_shift_clk_gen 609 | ( 610 | .up_phase(noise_latch_up_phase), 611 | .dn_phase(noise_latch_dn_phase), 612 | .set(1'b0), 613 | .rst(rst_1), 614 | 615 | .q_up(pre_f4), 616 | .q_dn() 617 | ); 618 | // 619 | ay_model_rs_ff noise_shift_clk_cond 620 | ( 621 | .reset( pre_f4), 622 | . set(~pre_f4), 623 | . q(_f4), 624 | ._q( f4) 625 | ); 626 | // 627 | ay_model_counter #( .WIDTH(5) ) noise_counter 628 | ( 629 | . f1( f1), 630 | ._f1(_f1), 631 | .rst(noise_latch_up_phase), 632 | 633 | . period( noise_period), 634 | ._period(_noise_period), 635 | 636 | .carry_out(noise_carry_out) 637 | ); 638 | // noise LFSR 639 | ay_model_shiftreg noise_shift_reg 640 | ( 641 | ._f(_f4), 642 | . f( f4), 643 | 644 | .rst(rst_1), 645 | 646 | .shift_in( (noise_reg[16] ^ noise_reg[13]) | (~|noise_reg) ), 647 | 648 | .result( noise_reg ) 649 | ); 650 | // 651 | assign noise = ~noise_reg[16]; 652 | 653 | 654 | 655 | 656 | 657 | // envelope generation 658 | assign env_rst = reg_wr & sel_r15; 659 | // 660 | 661 | 662 | // clock conditioning flipflop 663 | ay_model_rs_ff env_cntr_clk_conditioning 664 | ( 665 | .reset(_f1), 666 | . set(env_rst | (cnt_clk & env_carry_out)), 667 | 668 | . q(env_phase_up), 669 | ._q(env_phase_dn) 670 | ); 671 | 672 | // env freq output latch 673 | ay_model_clk_ff env_output 674 | ( 675 | .up_phase(env_phase_up), 676 | .dn_phase(env_phase_dn), 677 | .set(1'b0), 678 | .rst(env_rst), 679 | 680 | .q_up(), 681 | .q_dn(f_env) 682 | ); 683 | // 684 | assign ep_rst = ~env_phase_dn; 685 | // 686 | ay_model_counter #( .WIDTH(16) ) env_counter 687 | ( 688 | . f1( f1), 689 | ._f1(_f1), 690 | .rst(ep_rst), 691 | 692 | . period( env_period), 693 | ._period(_env_period), 694 | 695 | .carry_out(env_carry_out) 696 | ); 697 | 698 | 699 | 700 | 701 | // envelope state machine 702 | 703 | wire pre_clk; 704 | // 705 | assign pre_clk = ~(f_env_dis | f_env); 706 | // 707 | ay_model_rs_ff env_st_clk_conditioning 708 | ( 709 | .reset(~(env_rst | pre_clk)), 710 | . set( env_rst | pre_clk ), 711 | 712 | . q(env_clk_up), 713 | ._q(env_clk_dn) 714 | ); 715 | 716 | // e_mx FFs 717 | wire [3:0] emx; 718 | wire [3:0] _emx; 719 | // 720 | ay_model_clk_ff e0_mx 721 | ( 722 | .up_phase(env_clk_up), 723 | .dn_phase(env_clk_dn), 724 | .set(f_env_dis), 725 | .rst(env_rst), 726 | 727 | .q_up( emx[0]), 728 | .q_dn(_emx[0]) 729 | ); 730 | ay_model_clk_ff e1_mx 731 | ( 732 | .up_phase( emx[0]), 733 | .dn_phase(_emx[0]), 734 | .set(f_env_dis), 735 | .rst(env_rst), 736 | 737 | .q_up( emx[1]), 738 | .q_dn(_emx[1]) 739 | ); 740 | ay_model_clk_ff e2_mx 741 | ( 742 | .up_phase( emx[1]), 743 | .dn_phase(_emx[1]), 744 | .set(f_env_dis), 745 | .rst(env_rst), 746 | 747 | .q_up( emx[2]), 748 | .q_dn(_emx[2]) 749 | ); 750 | ay_model_clk_ff e3_mx 751 | ( 752 | .up_phase( emx[2]), 753 | .dn_phase(_emx[2]), 754 | .set(f_env_dis), 755 | .rst(env_rst), 756 | 757 | .q_up( emx[3]), 758 | .q_dn(_emx[3]) 759 | ); 760 | 761 | 762 | // decay/attack 763 | wire da_up, da_dn; 764 | wire pre_selea; 765 | // 766 | ay_model_clk_ff env_decay_attack 767 | ( 768 | .up_phase( emx[3] & env_mode[1]), 769 | .dn_phase(_emx[3]), 770 | .set(1'b0), 771 | .rst(env_rst), 772 | 773 | .q_up(da_up), 774 | .q_dn(da_dn) 775 | ); 776 | // 777 | assign pre_selea = env_mode[2] ? da_dn : da_up; 778 | // 779 | ay_model_rs_ff sel_ea_ff 780 | ( 781 | .reset(~pre_selea), 782 | . set( pre_selea), 783 | 784 | . q(_sel_ea), 785 | ._q( sel_ea) 786 | ); 787 | 788 | 789 | // hold 790 | ay_model_clk_ff env_hold 791 | ( 792 | .up_phase( emx[3] & env_mode[0]), 793 | .dn_phase(_emx[3]), 794 | .set(1'b0), 795 | .rst(env_rst), 796 | 797 | .q_up(), 798 | .q_dn(f_env_dis) 799 | ); 800 | 801 | 802 | // continue 803 | wire cont_up_phase; 804 | wire cont_q_up; 805 | // 806 | ay_model_clk_ff env_cont 807 | ( 808 | .up_phase(cont_up_phase), 809 | .dn_phase(_emx[3]), 810 | .set(1'b0), 811 | .rst(env_rst), 812 | 813 | .q_up(cont_q_up), 814 | .q_dn() 815 | ); 816 | // 817 | assign _env_en = ~(cont_q_up | env_mode[3]); 818 | // 819 | assign #0.01 cont_up_phase = ~(_env_en | (~emx[3])); 820 | 821 | 822 | 823 | 824 | // e_mx 825 | assign e_mx = sel_ea ? emx : _emx; 826 | 827 | // final envelope level 828 | assign e = ~(e_mx | {4{_env_en}}); 829 | 830 | 831 | 832 | // test_1 pin 833 | assign test_1 = f_env; 834 | 835 | endmodule 836 | 837 | 838 | 839 | 840 | 841 | 842 | 843 | 844 | module ay_model_channel // one of three identical AY channels 845 | ( 846 | input wire f1, // 847 | input wire _f1, // clock phases 848 | input wire cnt_clk, // 849 | 850 | input wire rst_1, // reset 851 | 852 | 853 | input wire reg_wr, // common write/store strobes 854 | input wire _reg_wr, 855 | 856 | input wire sel_tone_lo, // select for tone low register 857 | input wire sel_tone_hi, // tone high 858 | 859 | input wire sel_vol, // volume register 860 | 861 | 862 | inout wire [7:0] b, // internal AY bidir bus 863 | 864 | 865 | input wire _noise_en, // from mixer register 866 | input wire _tone_en, // 867 | 868 | input wire [3:0] e, // from envelope generator 869 | 870 | input wire noise, // from noise generator 871 | 872 | 873 | output wire [3:0] sound // output data, 0 -- cutoff, 1..15 -- corresponding DAC values 874 | ); 875 | wire [3:0] volume; 876 | wire env_ena; 877 | 878 | wire [11:0] period; 879 | wire [11:0] _period; 880 | 881 | wire tone; 882 | wire snd; 883 | 884 | 885 | 886 | /* volume latch */ 887 | ay_model_rw_latch #( .WIDTH(4) ) volume_reg 888 | ( 889 | .gate (sel_vol), 890 | .write( reg_wr), 891 | .store(_reg_wr), 892 | 893 | .d(b[3:0]), 894 | . q(volume), 895 | ._q() 896 | ); 897 | 898 | /* env enable latch */ 899 | ay_model_rw_latch #( .WIDTH(1) ) env_reg 900 | ( 901 | .gate (sel_vol), 902 | .write( reg_wr), 903 | .store(_reg_wr), 904 | 905 | .d(b[4]), 906 | . q(env_ena), 907 | ._q() 908 | ); 909 | 910 | /* period low latch */ 911 | ay_model_rw_latch #( .WIDTH(8) ) period_low_reg 912 | ( 913 | .gate (sel_tone_lo), 914 | .write( reg_wr), 915 | .store(_reg_wr), 916 | 917 | .d(b), 918 | . q( period[7:0]), 919 | ._q(_period[7:0]) 920 | ); 921 | 922 | /* period high latch */ 923 | ay_model_rw_latch #( .WIDTH(4) ) period_high_reg 924 | ( 925 | .gate (sel_tone_hi), 926 | .write( reg_wr), 927 | .store(_reg_wr), 928 | 929 | .d(b[3:0]), 930 | . q( period[11:8]), 931 | ._q(_period[11:8]) 932 | ); 933 | 934 | 935 | 936 | /* SND_* signal */ 937 | wire int_noise_gated; 938 | wire int_tone_gated; 939 | 940 | assign int_noise_gated = ~(noise | _noise_en); 941 | 942 | assign int_tone_gated = ~(tone | _tone_en); 943 | 944 | assign snd = ~(int_noise_gated | int_tone_gated); 945 | 946 | 947 | 948 | /* DAC output */ 949 | wire [3:0] int_volume; 950 | wire [3:0] int_volume_n; 951 | wire int_snd_n; 952 | 953 | assign int_volume = env_ena ? e : volume; 954 | 955 | assign int_volume_n = ~int_volume; 956 | 957 | assign int_snd_n = ~snd; 958 | 959 | assign sound = ~(int_volume_n | {4{int_snd_n}}); 960 | 961 | 962 | 963 | /* period counter */ 964 | wire carry_out; 965 | 966 | wire tone_latch_up_phase; 967 | wire tone_latch_dn_phase; 968 | 969 | wire counter_rst; 970 | 971 | 972 | 973 | // clock conditioning flipflop 974 | ay_model_rs_ff clk_conditioning 975 | ( 976 | .reset(_f1), 977 | . set(rst_1 | (cnt_clk & carry_out)), 978 | 979 | . q(tone_latch_up_phase), 980 | ._q(tone_latch_dn_phase) 981 | ); 982 | 983 | // tone output latch 984 | ay_model_clk_ff tone_output 985 | ( 986 | .up_phase(tone_latch_up_phase), 987 | .dn_phase(tone_latch_dn_phase), 988 | .set(1'b0), 989 | .rst(rst_1), 990 | 991 | .q_up(tone), 992 | .q_dn() 993 | ); 994 | 995 | // period counter reset 996 | assign counter_rst = ~tone_latch_dn_phase; 997 | 998 | 999 | ay_model_counter #( .WIDTH(12) ) channel_counter 1000 | ( 1001 | . f1( f1), 1002 | ._f1(_f1), 1003 | .rst(counter_rst), 1004 | 1005 | . period( period), 1006 | ._period(_period), 1007 | 1008 | .carry_out(carry_out) 1009 | ); 1010 | 1011 | 1012 | endmodule 1013 | 1014 | 1015 | 1016 | 1017 | 1018 | 1019 | module ay_model_gpio // one of two identical AY gpio ports 1020 | ( 1021 | inout wire [7:0] b, 1022 | inout tri1 [7:0] io, 1023 | 1024 | input wire _reg_wr, 1025 | input wire wr_reg_1, 1026 | input wire _r7_b_1, 1027 | input wire _en_reg_rd 1028 | ); 1029 | wire [7:0] int_output; 1030 | 1031 | ay_model_latch out_latch 1032 | ( 1033 | .d(b), 1034 | .load(wr_reg_1), 1035 | .store(_reg_wr), 1036 | .q(int_output), 1037 | ._q() 1038 | ); 1039 | 1040 | assign io = _r7_b_1 ? 8'hZZ : int_output; // out data 1041 | 1042 | assign b = _en_reg_rd ? 8'hZZ : io; // in data 1043 | 1044 | endmodule 1045 | 1046 | 1047 | 1048 | 1049 | 1050 | 1051 | 1052 | 1053 | 1054 | 1055 | module ay_model_rs_ff // RS-flipflop 1056 | ( 1057 | input wire reset, 1058 | input wire set, 1059 | 1060 | output reg q, 1061 | output reg _q 1062 | ); 1063 | always @* 1064 | q <= #0.01 ~(_q | reset); 1065 | 1066 | always @* 1067 | _q <= #0.01 ~( q | set); 1068 | endmodule 1069 | 1070 | 1071 | 1072 | module ay_model_clk_ff // clock flipflop 1073 | #( 1074 | parameter UP_RST = 1 1075 | ) 1076 | ( 1077 | input wire up_phase, // upper (on schematics) phase 1078 | input wire dn_phase, // lower (on schematics) phase 1079 | input wire set, // upper gate clear signal 1080 | input wire rst, 1081 | 1082 | output reg q_up, // upper and lower (on schematics) outputs 1083 | output reg q_dn // 1084 | ); 1085 | wire up_store; // modelled passgates that feed NAND inputs of main gates 1086 | wire dn_store; // 1087 | 1088 | wire int_up_rst; 1089 | 1090 | assign int_up_rst = UP_RST ? rst : 1'b0; 1091 | 1092 | assign up_store = int_up_rst ? 1'b0 : ( dn_phase ? q_up : 1'b0 ); 1093 | 1094 | assign dn_store = dn_phase ? q_dn : 1'b0; 1095 | 1096 | always @* 1097 | q_up <= #0.01 (~q_dn) & (~set) & (~(up_phase & up_store)) & (~(int_up_rst & dn_phase)); 1098 | 1099 | always @* 1100 | q_dn <= #0.01 (~q_up) & (~rst) & (~(dn_store & up_phase)); 1101 | endmodule 1102 | 1103 | 1104 | 1105 | 1106 | 1107 | module ay_model_latch // 2-phase latch 1108 | #( 1109 | parameter WIDTH=8 1110 | ) 1111 | ( 1112 | input wire load, // when 1, latch is transparent 1113 | input wire store, // when 1, latch stores its last value 1114 | 1115 | input wire [WIDTH-1:0] d, 1116 | output wire [WIDTH-1:0] q, 1117 | output wire [WIDTH-1:0] _q 1118 | ); 1119 | 1120 | wire [WIDTH-1:0] inwire; 1121 | 1122 | 1123 | assign inwire = load ? d : {WIDTH{1'b0}}; 1124 | assign inwire = store ? q : {WIDTH{1'b0}}; 1125 | 1126 | assign _q = ~inwire; 1127 | assign q = ~_q; 1128 | 1129 | endmodule 1130 | 1131 | 1132 | 1133 | module ay_model_rw_latch // readable and writable latch 1134 | #( 1135 | parameter WIDTH=8 1136 | ) 1137 | ( 1138 | input wire gate, // input gating 1139 | input wire write, // write strobe (REG_WR on schematics) 1140 | input wire store, // store strobe (/REG_WR on schematics) 1141 | 1142 | inout wire [WIDTH-1:0] d, 1143 | output reg [WIDTH-1:0] q, 1144 | output wire [WIDTH-1:0] _q 1145 | ); 1146 | wire d_oe; 1147 | 1148 | assign d = d_oe ? q : {WIDTH{1'bZ}}; 1149 | assign d_oe = store & gate; 1150 | 1151 | assign _q = ~q; 1152 | 1153 | 1154 | always @* 1155 | if( gate && write ) 1156 | q <= d; 1157 | 1158 | endmodule 1159 | 1160 | 1161 | 1162 | module ay_model_counter // async resettable counter with a comparator 1163 | #( 1164 | parameter WIDTH=0 1165 | ) 1166 | ( 1167 | input wire f1, 1168 | input wire _f1, // clocking phases 1169 | 1170 | input wire rst, // async reset 1171 | 1172 | input wire [WIDTH-1:0] period, 1173 | input wire [WIDTH-1:0] _period, // inverse copy of period 1174 | 1175 | output wire carry_out // 1 when counter value is greater than period 1176 | ); 1177 | 1178 | wire [WIDTH-1:0] cnt_up; 1179 | wire [WIDTH-1:0] cnt_dn; 1180 | 1181 | wire [WIDTH-1: 0] i; 1182 | wire [WIDTH-1:-1] c; 1183 | 1184 | genvar g; 1185 | 1186 | 1187 | 1188 | // first flipflop 1189 | ay_model_clk_ff #( .UP_RST(0) ) counter_bit_0 1190 | ( 1191 | .up_phase(_f1), 1192 | .dn_phase( f1), 1193 | .set(1'b0), 1194 | .rst(rst), 1195 | 1196 | .q_up(cnt_up[0]), 1197 | .q_dn(cnt_dn[0]) 1198 | 1199 | ); 1200 | // remaining flipflops 1201 | generate 1202 | for(g=1;g=period) 1220 | assign c[-1]=1'b1; 1221 | 1222 | assign i[WIDTH-1:0] = ~( c[WIDTH-2:-1] | (cnt_dn & _period)); 1223 | assign c[WIDTH-1:0] = ~( i | (cnt_up & period)); 1224 | 1225 | assign carry_out = c[WIDTH-1]; 1226 | 1227 | 1228 | 1229 | 1230 | endmodule 1231 | 1232 | 1233 | 1234 | module ay_model_shiftreg 1235 | #( 1236 | parameter WIDTH=17 1237 | ) 1238 | ( 1239 | input wire _f, 1240 | input wire f, 1241 | input wire rst, 1242 | 1243 | input wire shift_in, 1244 | output wire [WIDTH-1:0] result 1245 | ); 1246 | 1247 | wire [WIDTH-1:0] shin; 1248 | 1249 | wire [WIDTH-1:0] l1; 1250 | wire [WIDTH-1:0] l2; 1251 | 1252 | 1253 | // shift in 1254 | assign shin = { l2[WIDTH-2:0], shift_in }; 1255 | 1256 | assign l1 = rst ? {WIDTH{1'b0}} : (_f ? shin : {WIDTH{1'b0}}); 1257 | 1258 | assign l2 = f ? l1 : {WIDTH{1'b0}}; 1259 | 1260 | assign result = l2; 1261 | 1262 | endmodule 1263 | 1264 | -------------------------------------------------------------------------------- /doc/conn.md: -------------------------------------------------------------------------------- 1 | # Connectivity Cases 2 | 3 | Definitions: 4 | 5 | - **Per channel**: resistor from channel output to ground (kOhm) 6 | - **Join res**: resistors joining from ch. output to a net common to all channels (kOhm) 7 | - **Lump res**: resistor from the common net to ground (kOhm) 8 | - **ac**: ac coupling capacitor, in uF 9 | 10 | Game | Chip Model | Per ch. | Join R. | Lump | ac | Remarks 11 | ------------------------|-----------------|---------|---------|-------|-----|---------- 12 | Ghosts'n Goblins | YM2203 | 1 | 4.7 | 2 | 10 | 13 | Robocop | YM2203 | 10 | 56 | 1 | 10 | 14 | Combat School | YM2203 | | 3.2 | 1 | 4.7| one ac cap for all channels 15 | Bubble Bobble | YM2203 | | shorted | 1 | 10 | single cap for all chips 16 | The New Zealand Story | YM2203 | | shorted | 1 | 0.1 | Applies to other boards of the same series (JTKIWI core) 17 | 1942 | AY-3-8910 | 10 | 220 | 2 | 10 | 18 | Karate Champ | AY-3-8910 | 1 | | 1 | 1 | ch. C of chip 1A 19 | Karate Champ | AY-3-8910 | | shorted | 1 | 1 | ch. B/C of chip 1A, all of chip 3A (5 ch.) 20 | Roc'n Rope | AY-3-8910 | 6.1 | | | 1 | all ch. connected to a virtual ground 21 | 22 | Bubble Bobble is misconnected. Due to YM2203's buffered output, shorting all channels will make the higher output voltage dominate at any time. -------------------------------------------------------------------------------- /doc/lab.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jotego/jt49/7f6abfd08a2af9a92dbd5b32c71ea773248a77e2/doc/lab.ods -------------------------------------------------------------------------------- /doc/resistors.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jotego/jt49/7f6abfd08a2af9a92dbd5b32c71ea773248a77e2/doc/resistors.ods -------------------------------------------------------------------------------- /hdl/filter/jt49_dcrm.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 15-Jan-2019 19 | 20 | */ 21 | 22 | // DC removal filter 23 | // input is unsigned 24 | // output is signed 25 | /* verilator tracing_off */ 26 | module jt49_dcrm( 27 | input clk, 28 | input cen, 29 | input rst, 30 | input [7:0] din, 31 | output reg signed [7:0] dout 32 | ); 33 | 34 | wire signed [7:0] ave0, ave1; 35 | 36 | jt49_mave u_mave0( 37 | .clk ( clk ), 38 | .cen ( cen ), 39 | .rst ( rst ), 40 | .din ( {1'b0, din[7:1] } ), 41 | .dout ( ave0 ) 42 | ); 43 | 44 | jt49_mave u_mave1( 45 | .clk ( clk ), 46 | .cen ( cen ), 47 | .rst ( rst ), 48 | .din ( ave0 ), 49 | .dout ( ave1 ) 50 | ); 51 | 52 | always @(posedge clk) 53 | if( cen ) 54 | dout <= ({1'b0,din} - {ave1,1'b0})>>>1; 55 | 56 | endmodule -------------------------------------------------------------------------------- /hdl/filter/jt49_dcrm2.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 15-Jan-2019 19 | 20 | */ 21 | 22 | // DC removal filter 23 | // input is unsigned 24 | // output is signed 25 | 26 | module jt49_dcrm2 #(parameter sw=8) ( 27 | input clk, 28 | input cen, 29 | input rst, 30 | input [sw-1:0] din, 31 | output signed [sw-1:0] dout 32 | ); 33 | 34 | localparam DW=10; // width of the decimal portion 35 | 36 | reg signed [sw+DW:0] integ, exact, error; 37 | //reg signed [2*(9+DW)-1:0] mult; 38 | // wire signed [sw+DW:0] plus1 = { {sw+DW{1'b0}},1'b1}; 39 | reg signed [sw:0] pre_dout; 40 | // reg signed [sw+DW:0] dout_ext; 41 | reg signed [sw:0] q; 42 | 43 | always @(*) begin 44 | exact = integ+error; 45 | q = exact[sw+DW:DW]; 46 | pre_dout = { 1'b0, din } - q; 47 | //dout_ext = { pre_dout, {DW{1'b0}} }; 48 | //mult = dout_ext; 49 | end 50 | 51 | assign dout = pre_dout[sw-1:0]; 52 | 53 | always @(posedge clk) 54 | if( rst ) begin 55 | integ <= {sw+DW+1{1'b0}}; 56 | error <= {sw+DW+1{1'b0}}; 57 | end else if( cen ) begin 58 | /* verilator lint_off WIDTH */ 59 | integ <= integ + pre_dout; //mult[sw+DW*2:DW]; 60 | /* verilator lint_on WIDTH */ 61 | error <= exact-{q, {DW{1'b0}}}; 62 | end 63 | 64 | endmodule -------------------------------------------------------------------------------- /hdl/filter/jt49_dly.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 15-Jan-2019 19 | 20 | */ 21 | 22 | // Delay stage 23 | // use for long delays 24 | 25 | module jt49_dly #(parameter DW=8, depth=10)( 26 | input clk, 27 | input cen, 28 | input rst, 29 | input [7:0] din, 30 | output reg [7:0] dout, 31 | output reg [7:0] pre_dout 32 | 33 | ); 34 | 35 | reg [depth-1:0] rdpos, wrpos; 36 | 37 | 38 | // memory 39 | reg [DW-1:0] ram[0:2**depth-1]; 40 | always @(posedge clk) 41 | if(rst) 42 | pre_dout <= {DW{1'b0}}; 43 | else begin 44 | pre_dout <= ram[rdpos]; 45 | if( cen ) ram[wrpos] <= din; 46 | end 47 | 48 | `ifdef SIMULATION 49 | integer k; 50 | initial begin 51 | for(k=0;k<=2**depth-1;k=k+1) 52 | ram[k] = 0; 53 | end 54 | `endif 55 | 56 | always @(posedge clk) 57 | if( rst ) begin 58 | rdpos <= { {depth-1{1'b0}}, 1'b1}; 59 | wrpos <= {depth{1'b1}}; 60 | dout <= {DW{1'b0}}; 61 | end else if(cen) begin 62 | dout <= pre_dout; 63 | rdpos <= rdpos+1'b1; 64 | wrpos <= wrpos+1'b1; 65 | end 66 | 67 | endmodule // jt49_dly -------------------------------------------------------------------------------- /hdl/filter/jt49_mave.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 15-Jan-2019 19 | 20 | */ 21 | 22 | // Moving averager 23 | 24 | module jt49_mave #(parameter depth=8, DW=8)( 25 | input clk, 26 | input cen, 27 | input rst, 28 | input signed [DW-1:0] din, 29 | output signed [DW-1:0] dout 30 | ); 31 | 32 | wire [DW-1:0] dly0; 33 | wire [DW-1:0] pre_dly0; 34 | 35 | jt49_dly #(.depth(depth),.DW(DW)) u_dly0( 36 | .clk ( clk ), 37 | .cen ( cen ), 38 | .rst ( rst ), 39 | .din ( din ), 40 | .dout ( dly0 ), 41 | .pre_dout ( pre_dly0 ) 42 | ); 43 | 44 | // moving average 45 | // D=2048 46 | reg signed [DW:0] diff; 47 | reg signed [DW+depth-1:0] sum; 48 | 49 | 50 | always @(posedge clk) 51 | if( rst ) begin 52 | diff <= {DW+1{1'd0}}; 53 | sum <= {DW+depth+1{1'd0}}; 54 | end else if(cen) begin 55 | diff <= {1'b0,din } - { 1'b0, dly0 }; 56 | sum <= { {depth{diff[DW]}}, diff } + sum; 57 | end 58 | assign dout = sum[DW+depth-1:depth]; 59 | 60 | endmodule -------------------------------------------------------------------------------- /hdl/jt49.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 10-Nov-2018 19 | 20 | Based on sqmusic, by the same author 21 | 22 | */ 23 | /* verilator coverage_off */ 24 | module jt49 ( // note that input ports are not multiplexed 25 | input rst_n, 26 | input clk, // signal on positive edge 27 | input clk_en /* synthesis direct_enable = 1 */, 28 | input [3:0] addr, 29 | input cs_n, 30 | input wr_n, // write 31 | input [7:0] din, 32 | input sel, // if sel is low, the clock is divided by 2 33 | output reg [7:0] dout, 34 | output reg [9:0] sound, // combined channel output 35 | output reg [7:0] A, // linearised channel output 36 | output reg [7:0] B, 37 | output reg [7:0] C, 38 | output sample, 39 | 40 | input [7:0] IOA_in, 41 | output [7:0] IOA_out, 42 | output IOA_oe, 43 | 44 | input [7:0] IOB_in, 45 | output [7:0] IOB_out, 46 | output IOB_oe 47 | ); 48 | 49 | parameter [2:0] COMP=3'b000; 50 | parameter YM2203_LUMPED=0; 51 | parameter CLKDIV=3; 52 | wire [2:0] comp = COMP; 53 | 54 | reg [ 7:0] regarray[15:0]; 55 | wire [ 7:0] port_A, port_B; 56 | wire [11:0] periodA, periodB, periodC; 57 | 58 | wire [4:0] envelope; 59 | wire bitA, bitB, bitC; 60 | wire noise; 61 | reg Amix, Bmix, Cmix; 62 | 63 | wire cen16, cen256; 64 | 65 | assign IOA_out = regarray[14]; 66 | assign IOB_out = regarray[15]; 67 | assign port_A = IOA_in; 68 | assign port_B = IOB_in; 69 | assign IOA_oe = regarray[7][6]; 70 | assign IOB_oe = regarray[7][7]; 71 | assign sample = cen16; 72 | assign periodA = { regarray[1][3:0], regarray[0][7:0] }; 73 | assign periodB = { regarray[3][3:0], regarray[2][7:0] }; 74 | assign periodC = { regarray[5][3:0], regarray[4][7:0] }; 75 | 76 | 77 | jt49_cen #(.CLKDIV(CLKDIV)) u_cen( 78 | .clk ( clk ), 79 | .rst_n ( rst_n ), 80 | .cen ( clk_en ), 81 | .sel ( sel ), 82 | .cen16 ( cen16 ), 83 | .cen256 ( cen256 ) 84 | ); 85 | 86 | // internal modules operate at clk/16 87 | jt49_div #(12) u_chA( 88 | .clk ( clk ), 89 | .rst_n ( rst_n ), 90 | .cen ( cen16 ), 91 | .period ( periodA ), 92 | .div ( bitA ) 93 | ); 94 | 95 | jt49_div #(12) u_chB( 96 | .clk ( clk ), 97 | .rst_n ( rst_n ), 98 | .cen ( cen16 ), 99 | .period ( periodB ), 100 | .div ( bitB ) 101 | ); 102 | 103 | jt49_div #(12) u_chC( 104 | .clk ( clk ), 105 | .rst_n ( rst_n ), 106 | .cen ( cen16 ), 107 | .period ( periodC ), 108 | .div ( bitC ) 109 | ); 110 | 111 | jt49_noise u_ng( 112 | .clk ( clk ), 113 | .cen ( cen16 ), 114 | .rst_n ( rst_n ), 115 | .period ( regarray[6][4:0] ), 116 | .noise ( noise ) 117 | ); 118 | 119 | // envelope generator 120 | wire eg_step; 121 | wire [15:0] eg_period = {regarray[4'hc],regarray[4'hb]}; 122 | wire null_period = eg_period == 16'h0; 123 | 124 | jt49_div #(16) u_envdiv( 125 | .clk ( clk ), 126 | .cen ( cen256 ), 127 | .rst_n ( rst_n ), 128 | .period ( eg_period ), 129 | .div ( eg_step ) 130 | ); 131 | 132 | reg eg_restart; 133 | 134 | jt49_eg u_env( 135 | .clk ( clk ), 136 | .cen ( cen256 ), 137 | .step ( eg_step ), 138 | .rst_n ( rst_n ), 139 | .restart ( eg_restart ), 140 | .null_period( null_period ), 141 | .ctrl ( regarray[4'hD][3:0] ), 142 | .env ( envelope ) 143 | ); 144 | 145 | reg [4:0] logA, logB, logC, log; 146 | wire [7:0] lin; 147 | 148 | jt49_exp u_exp( 149 | .clk ( clk ), 150 | .comp ( comp ), 151 | .din ( log ), 152 | .dout ( lin ) 153 | ); 154 | 155 | wire [4:0] volA = { regarray[ 8][3:0], regarray[ 8][3] }; 156 | wire [4:0] volB = { regarray[ 9][3:0], regarray[ 9][3] }; 157 | wire [4:0] volC = { regarray[10][3:0], regarray[10][3] }; 158 | wire use_envA = regarray[ 8][4]; 159 | wire use_envB = regarray[ 9][4]; 160 | wire use_envC = regarray[10][4]; 161 | wire use_noA = regarray[ 7][3]; 162 | wire use_noB = regarray[ 7][4]; 163 | wire use_noC = regarray[ 7][5]; 164 | 165 | reg [3:0] acc_st; 166 | 167 | always @(posedge clk) if( clk_en ) begin 168 | Amix <= (noise|use_noA) & (bitA|regarray[7][0]); 169 | Bmix <= (noise|use_noB) & (bitB|regarray[7][1]); 170 | Cmix <= (noise|use_noC) & (bitC|regarray[7][2]); 171 | 172 | logA <= !Amix ? 5'd0 : (use_envA ? envelope : volA ); 173 | logB <= !Bmix ? 5'd0 : (use_envB ? envelope : volB ); 174 | logC <= !Cmix ? 5'd0 : (use_envC ? envelope : volC ); 175 | end 176 | 177 | reg [9:0] acc; 178 | wire [9:0] elin; 179 | 180 | assign elin = {2'd0,lin}; 181 | 182 | always @(posedge clk, negedge rst_n) begin 183 | if( !rst_n ) begin 184 | acc_st <= 4'b1; 185 | acc <= 10'd0; 186 | A <= 8'd0; 187 | B <= 8'd0; 188 | C <= 8'd0; 189 | sound <= 10'd0; 190 | end else if(clk_en) begin 191 | acc_st <= { acc_st[2:0], acc_st[3] }; 192 | // Lumping the channel outputs for YM2203 will cause only the higher 193 | // voltage to pass throuh, as the outputs seem to use a source follower. 194 | acc <= YM2203_LUMPED==1 ? (acc>elin ? acc : elin) : acc + elin; 195 | case( acc_st ) 196 | 4'b0001: begin 197 | log <= logA; 198 | acc <= 10'd0; 199 | sound <= acc; 200 | end 201 | 4'b0010: begin 202 | A <= lin; 203 | log <= logB; 204 | end 205 | 4'b0100: begin 206 | B <= lin; 207 | log <= logC; 208 | end 209 | 4'b1000: begin // last sum 210 | C <= lin; 211 | end 212 | default:; 213 | endcase 214 | end 215 | end 216 | 217 | reg [7:0] read_mask; 218 | 219 | always @(*) 220 | case(addr) 221 | 4'h0,4'h2,4'h4,4'h7,4'hb,4'hc,4'he,4'hf: 222 | read_mask = 8'hff; 223 | 4'h1,4'h3,4'h5,4'hd: 224 | read_mask = 8'h0f; 225 | 4'h6,4'h8,4'h9,4'ha: 226 | read_mask = 8'h1f; 227 | endcase // addr 228 | 229 | // register array 230 | wire write; 231 | reg last_write; 232 | wire wr_edge = write & ~last_write; 233 | 234 | assign write = !wr_n && !cs_n; 235 | 236 | always @(posedge clk, negedge rst_n) begin 237 | if( !rst_n ) begin 238 | dout <= 8'd0; 239 | last_write <= 0; 240 | eg_restart <= 0; 241 | regarray[0]<=8'd0; regarray[4]<=8'd0; regarray[ 8]<=8'd0; regarray[12]<=8'd0; 242 | regarray[1]<=8'd0; regarray[5]<=8'd0; regarray[ 9]<=8'd0; regarray[13]<=8'd0; 243 | regarray[2]<=8'd0; regarray[6]<=8'd0; regarray[10]<=8'd0; regarray[14]<=8'd0; 244 | regarray[3]<=8'd0; regarray[7]<=8'd0; regarray[11]<=8'd0; regarray[15]<=8'd0; 245 | end else begin 246 | last_write <= write; 247 | // Data read 248 | case( addr ) 249 | 4'he: dout <= port_A; 250 | 4'hf: dout <= port_B; 251 | default: dout <= regarray[ addr ] & read_mask; 252 | endcase 253 | // Data write 254 | if( write ) begin 255 | regarray[addr] <= din; 256 | if ( addr == 4'hD && wr_edge ) eg_restart <= 1; 257 | end else begin 258 | eg_restart <= 0; 259 | end 260 | end 261 | end 262 | 263 | endmodule 264 | -------------------------------------------------------------------------------- /hdl/jt49_bus.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 28-Jan-2019 19 | 20 | Based on sqmusic, by the same author 21 | 22 | */ 23 | 24 | // This is a wrapper with the BDIR/BC1 pins 25 | /* verilator coverage_off */ 26 | module jt49_bus ( // note that input ports are not multiplexed 27 | input rst_n, 28 | input clk, // signal on positive edge 29 | input clk_en /* synthesis direct_enable = 1 */, 30 | // bus control pins of original chip 31 | input bdir, 32 | input bc1, 33 | input [7:0] din, 34 | 35 | input sel, // if sel is low, the clock is divided by 2 36 | output [7:0] dout, 37 | output [9:0] sound, // combined channel output 38 | output [7:0] A, // linearised channel output 39 | output [7:0] B, 40 | output [7:0] C, 41 | output sample, 42 | 43 | input [7:0] IOA_in, 44 | output [7:0] IOA_out, 45 | output IOA_oe, 46 | 47 | input [7:0] IOB_in, 48 | output [7:0] IOB_out, 49 | output IOB_oe 50 | ); 51 | 52 | parameter [2:0] COMP=3'b000; 53 | 54 | reg wr_n, cs_n; 55 | reg [3:0] addr; 56 | reg addr_ok; 57 | reg [7:0] din_latch; 58 | 59 | always @(posedge clk) 60 | if( !rst_n ) begin 61 | wr_n <= 1'b1; 62 | cs_n <= 1'b1; 63 | addr <= 4'd0; 64 | addr_ok <= 1'b1; 65 | end else begin // I/O cannot use clk_en 66 | // addr must be 67 | case( {bdir,bc1} ) 68 | 2'b00: { wr_n, cs_n } <= 2'b11; 69 | 2'b01: { wr_n, cs_n } <= addr_ok ? 2'b10 : 2'b11; 70 | 2'b10: begin 71 | { wr_n, cs_n } <= addr_ok ? 2'b00 : 2'b11; 72 | din_latch <= din; 73 | end 74 | 2'b11: begin 75 | { wr_n, cs_n } <= 2'b11; 76 | addr <= din[3:0]; 77 | addr_ok <= din[7:4] == 4'd0; 78 | end 79 | endcase // {bdir,bc1} 80 | end 81 | 82 | jt49 #(.COMP(COMP)) u_jt49( // note that input ports are not multiplexed 83 | .rst_n ( rst_n ), 84 | .clk ( clk ), // signal on positive edge 85 | .clk_en ( clk_en ), // clock enable on negative edge 86 | .addr ( addr[3:0] ), 87 | .cs_n ( cs_n ), 88 | .wr_n ( wr_n ), // write 89 | .din ( din_latch ), 90 | .sel ( sel ), // if sel is low, the clock is divided by 2 91 | .dout ( dout ), 92 | .sound ( sound ), // combined channel output 93 | .sample ( sample ), 94 | .A ( A ), // linearised channel output 95 | .B ( B ), 96 | .C ( C ), 97 | .IOA_in ( IOA_in ), 98 | .IOA_out( IOA_out ), 99 | .IOA_oe ( IOA_oe ), 100 | .IOB_in ( IOB_in ), 101 | .IOB_out( IOB_out ), 102 | .IOB_oe ( IOB_oe ) 103 | ); 104 | 105 | endmodule // jt49_bus -------------------------------------------------------------------------------- /hdl/jt49_cen.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 10-Nov-2018 19 | 20 | Based on sqmusic, by the same author 21 | 22 | */ 23 | /* verilator coverage_off */ 24 | module jt49_cen( 25 | input clk, 26 | input rst_n, 27 | input cen, // base clock enable signal 28 | input sel, // when low, divide by 2 once more 29 | output reg cen16, 30 | output reg cen256 31 | ); 32 | 33 | reg [9:0] cencnt; 34 | parameter CLKDIV = 3; // use 3 for standalone JT49 or 2 35 | localparam eg = CLKDIV; //8; 36 | 37 | wire toggle16 = sel ? ~|cencnt[CLKDIV-1:0] : ~|cencnt[CLKDIV:0]; 38 | wire toggle256= sel ? ~|cencnt[eg-2:0] : ~|cencnt[eg-1:0]; 39 | 40 | 41 | always @(posedge clk, negedge rst_n) begin 42 | if(!rst_n) 43 | cencnt <= 10'd0; 44 | else begin 45 | if(cen) cencnt <= cencnt+10'd1; 46 | end 47 | end 48 | 49 | always @(posedge clk) begin 50 | cen16 <= cen & toggle16; 51 | cen256 <= cen & toggle256; 52 | end 53 | 54 | 55 | endmodule // jt49_cen 56 | -------------------------------------------------------------------------------- /hdl/jt49_div.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 10-Nov-2018 19 | 20 | Based on sqmusic, by the same author 21 | 22 | */ 23 | 24 | /* verilator coverage_off */ 25 | module jt49_div #(parameter W=12 )( 26 | (* direct_enable *) input cen, 27 | input clk, // this is the divided down clock from the core 28 | input rst_n, 29 | input [W-1:0] period, 30 | output reg div 31 | ); 32 | 33 | reg [W-1:0]count; 34 | 35 | wire [W-1:0] one = { {W-1{1'b0}}, 1'b1}; 36 | 37 | always @(posedge clk, negedge rst_n ) begin 38 | if( !rst_n) begin 39 | count <= one; 40 | div <= 1'b0; 41 | end else if(cen) begin 42 | if( count>=period ) begin 43 | count <= one; 44 | div <= ~div; 45 | end else begin 46 | count <= count + one ; 47 | end 48 | if(period==0) div<=0; 49 | end 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /hdl/jt49_eg.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 10-Nov-2018 19 | 20 | Based on sqmusic, by the same author 21 | 22 | */ 23 | /* verilator coverage_off */ 24 | module jt49_eg( 25 | (* direct_enable *) input cen, 26 | input clk, // this is the divided down clock from the core 27 | input step, 28 | input null_period, 29 | input rst_n, 30 | input restart, 31 | input [3:0] ctrl, 32 | output reg [4:0]env 33 | ); 34 | 35 | reg inv, stop; 36 | reg [4:0] gain; 37 | 38 | wire CONT = ctrl[3]; 39 | wire ATT = ctrl[2]; 40 | wire ALT = ctrl[1]; 41 | wire HOLD = ctrl[0]; 42 | 43 | wire will_hold = !CONT || HOLD; 44 | 45 | always @(posedge clk) 46 | if( cen ) env <= inv ? ~gain : gain; 47 | 48 | reg last_step; 49 | wire step_edge = (step && !last_step) || null_period; 50 | wire will_invert = (!CONT&&ATT) || (CONT&&ALT); 51 | reg rst_latch, rst_clr; 52 | 53 | always @(posedge clk) begin 54 | if( restart ) rst_latch <= 1; 55 | else if(rst_clr ) rst_latch <= 0; 56 | end 57 | 58 | always @( posedge clk, negedge rst_n ) 59 | if( !rst_n) begin 60 | gain <= 5'h1F; 61 | inv <= 0; 62 | stop <= 0; 63 | rst_clr <= 0; 64 | end 65 | else if( cen ) begin 66 | last_step <= step; 67 | if( rst_latch ) begin 68 | gain <= 5'h1F; 69 | inv <= ATT; 70 | stop <= 1'b0; 71 | rst_clr <= 1; 72 | end 73 | else begin 74 | rst_clr <= 0; 75 | if (step_edge && !stop) begin 76 | if( gain==5'h00 ) begin 77 | if( will_hold ) 78 | stop <= 1'b1; 79 | else 80 | gain <= gain-5'b1; 81 | if( will_invert ) inv<=~inv; 82 | end 83 | else gain <= gain-5'b1; 84 | end 85 | end 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /hdl/jt49_exp.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 10-Nov-2018 19 | 20 | Based on sqmusic, by the same author 21 | 22 | */ 23 | 24 | // Compression vs dynamic range 25 | // 0 -> 43.6dB 26 | // 1 -> 29.1 27 | // 2 -> 21.8 28 | // 3 -> 13.4 29 | /* verilator coverage_off */ 30 | module jt49_exp( 31 | input clk, 32 | input [2:0] comp, // compression 33 | input [4:0] din, 34 | output reg [7:0] dout 35 | ); 36 | 37 | reg [7:0] lut[0:159]; 38 | 39 | always @(posedge clk) 40 | dout <= lut[ {comp,din} ]; 41 | 42 | initial begin 43 | lut[0] = 8'd0; 44 | lut[1] = 8'd1; 45 | lut[2] = 8'd1; 46 | lut[3] = 8'd1; 47 | lut[4] = 8'd2; 48 | lut[5] = 8'd2; 49 | lut[6] = 8'd3; 50 | lut[7] = 8'd3; 51 | lut[8] = 8'd4; 52 | lut[9] = 8'd5; 53 | lut[10] = 8'd6; 54 | lut[11] = 8'd7; 55 | lut[12] = 8'd9; 56 | lut[13] = 8'd11; 57 | lut[14] = 8'd13; 58 | lut[15] = 8'd15; 59 | lut[16] = 8'd18; 60 | lut[17] = 8'd22; 61 | lut[18] = 8'd26; 62 | lut[19] = 8'd31; 63 | lut[20] = 8'd37; 64 | lut[21] = 8'd45; 65 | lut[22] = 8'd53; 66 | lut[23] = 8'd63; 67 | lut[24] = 8'd75; 68 | lut[25] = 8'd90; 69 | lut[26] = 8'd107; 70 | lut[27] = 8'd127; 71 | lut[28] = 8'd151; 72 | lut[29] = 8'd180; 73 | lut[30] = 8'd214; 74 | lut[31] = 8'd255; 75 | lut[32] = 8'd0; 76 | lut[33] = 8'd7; 77 | lut[34] = 8'd8; 78 | lut[35] = 8'd10; 79 | lut[36] = 8'd11; 80 | lut[37] = 8'd12; 81 | lut[38] = 8'd14; 82 | lut[39] = 8'd15; 83 | lut[40] = 8'd17; 84 | lut[41] = 8'd20; 85 | lut[42] = 8'd22; 86 | lut[43] = 8'd25; 87 | lut[44] = 8'd28; 88 | lut[45] = 8'd31; 89 | lut[46] = 8'd35; 90 | lut[47] = 8'd40; 91 | lut[48] = 8'd45; 92 | lut[49] = 8'd50; 93 | lut[50] = 8'd56; 94 | lut[51] = 8'd63; 95 | lut[52] = 8'd71; 96 | lut[53] = 8'd80; 97 | lut[54] = 8'd90; 98 | lut[55] = 8'd101; 99 | lut[56] = 8'd113; 100 | lut[57] = 8'd127; 101 | lut[58] = 8'd143; 102 | lut[59] = 8'd160; 103 | lut[60] = 8'd180; 104 | lut[61] = 8'd202; 105 | lut[62] = 8'd227; 106 | lut[63] = 8'd255; 107 | lut[64] = 8'd0; 108 | lut[65] = 8'd18; 109 | lut[66] = 8'd20; 110 | lut[67] = 8'd22; 111 | lut[68] = 8'd24; 112 | lut[69] = 8'd26; 113 | lut[70] = 8'd29; 114 | lut[71] = 8'd31; 115 | lut[72] = 8'd34; 116 | lut[73] = 8'd37; 117 | lut[74] = 8'd41; 118 | lut[75] = 8'd45; 119 | lut[76] = 8'd49; 120 | lut[77] = 8'd53; 121 | lut[78] = 8'd58; 122 | lut[79] = 8'd63; 123 | lut[80] = 8'd69; 124 | lut[81] = 8'd75; 125 | lut[82] = 8'd82; 126 | lut[83] = 8'd90; 127 | lut[84] = 8'd98; 128 | lut[85] = 8'd107; 129 | lut[86] = 8'd116; 130 | lut[87] = 8'd127; 131 | lut[88] = 8'd139; 132 | lut[89] = 8'd151; 133 | lut[90] = 8'd165; 134 | lut[91] = 8'd180; 135 | lut[92] = 8'd196; 136 | lut[93] = 8'd214; 137 | lut[94] = 8'd233; 138 | lut[95] = 8'd255; 139 | lut[96] = 8'd0; 140 | lut[97] = 8'd51; 141 | lut[98] = 8'd54; 142 | lut[99] = 8'd57; 143 | lut[100] = 8'd60; 144 | lut[101] = 8'd63; 145 | lut[102] = 8'd67; 146 | lut[103] = 8'd70; 147 | lut[104] = 8'd74; 148 | lut[105] = 8'd78; 149 | lut[106] = 8'd83; 150 | lut[107] = 8'd87; 151 | lut[108] = 8'd92; 152 | lut[109] = 8'd97; 153 | lut[110] = 8'd103; 154 | lut[111] = 8'd108; 155 | lut[112] = 8'd114; 156 | lut[113] = 8'd120; 157 | lut[114] = 8'd127; 158 | lut[115] = 8'd134; 159 | lut[116] = 8'd141; 160 | lut[117] = 8'd149; 161 | lut[118] = 8'd157; 162 | lut[119] = 8'd166; 163 | lut[120] = 8'd175; 164 | lut[121] = 8'd185; 165 | lut[122] = 8'd195; 166 | lut[123] = 8'd206; 167 | lut[124] = 8'd217; 168 | lut[125] = 8'd229; 169 | lut[126] = 8'd241; 170 | lut[127] = 8'd255; 171 | lut[128] = 8'd0; 172 | lut[129] = 8'd8; 173 | lut[130] = 8'd10; 174 | lut[131] = 8'd12; 175 | lut[132] = 8'd16; 176 | lut[133] = 8'd22; 177 | lut[134] = 8'd29; 178 | lut[135] = 8'd35; 179 | lut[136] = 8'd44; 180 | lut[137] = 8'd50; 181 | lut[138] = 8'd56; 182 | lut[139] = 8'd60; 183 | lut[140] = 8'd64; 184 | lut[141] = 8'd85; 185 | lut[142] = 8'd97; 186 | lut[143] = 8'd103; 187 | lut[144] = 8'd108; 188 | lut[145] = 8'd120; 189 | lut[146] = 8'd127; 190 | lut[147] = 8'd134; 191 | lut[148] = 8'd141; 192 | lut[149] = 8'd149; 193 | lut[150] = 8'd157; 194 | lut[151] = 8'd166; 195 | lut[152] = 8'd175; 196 | lut[153] = 8'd185; 197 | lut[154] = 8'd195; 198 | lut[155] = 8'd206; 199 | lut[156] = 8'd217; 200 | lut[157] = 8'd229; 201 | lut[158] = 8'd241; 202 | lut[159] = 8'd255; 203 | 204 | end 205 | endmodule 206 | -------------------------------------------------------------------------------- /hdl/jt49_noise.v: -------------------------------------------------------------------------------- 1 | /* This file is part of JT49. 2 | 3 | JT49 is free software: you can redistribute it and/or modify 4 | it under the terms of the GNU General Public License as published by 5 | the Free Software Foundation, either version 3 of the License, or 6 | (at your option) any later version. 7 | 8 | JT49 is distributed in the hope that it will be useful, 9 | but WITHOUT ANY WARRANTY; without even the implied warranty of 10 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 | GNU General Public License for more details. 12 | 13 | You should have received a copy of the GNU General Public License 14 | along with JT49. If not, see . 15 | 16 | Author: Jose Tejada Gomez. Twitter: @topapate 17 | Version: 1.0 18 | Date: 10-Nov-2018 19 | 20 | Based on sqmusic, by the same author 21 | 22 | */ 23 | 24 | /* verilator coverage_off */ 25 | module jt49_noise( 26 | (* direct_enable *) input cen, 27 | input clk, 28 | input rst_n, 29 | input [4:0] period, 30 | output reg noise 31 | ); 32 | 33 | reg [5:0]count; 34 | reg [16:0]poly17; 35 | wire poly17_zero = poly17==17'b0; 36 | wire noise_en; 37 | reg last_en; 38 | 39 | wire noise_up = noise_en && !last_en; 40 | 41 | always @(posedge clk ) if(cen) begin 42 | noise <= ~poly17[0]; 43 | end 44 | 45 | always @( posedge clk, negedge rst_n ) 46 | if( !rst_n ) 47 | poly17 <= 17'd0; 48 | else if( cen ) begin 49 | last_en <= noise_en; 50 | if( noise_up ) 51 | poly17 <= { poly17[0] ^ poly17[3] ^ poly17_zero, poly17[16:1] }; 52 | end 53 | 54 | jt49_div #(5) u_div( 55 | .clk ( clk ), 56 | .cen ( cen ), 57 | .rst_n ( rst_n ), 58 | .period ( period ), 59 | .div ( noise_en ) 60 | ); 61 | 62 | endmodule -------------------------------------------------------------------------------- /lab/dual/dual.ino: -------------------------------------------------------------------------------- 1 | // Drives two channels with overlapping amplitudes 2 | 3 | const int A0PIN=8, // PB0 4 | WRPIN=9, // PB1 5 | ICPIN=10; // PB2 6 | 7 | void setup() { 8 | // Set ports B and D as an output 9 | DDRD=0xff; 10 | DDRB=0x07; 11 | // PSG 12 | psg_setup(); 13 | } 14 | 15 | void wrDout(int v, int a0 ) { 16 | PORTD=v; 17 | a0=(a0&1)|4; // keep IC high (bit 2) 18 | PORTB=a0; // WR low 19 | PORTB=a0|0x02; // WR high 20 | // delay(1); 21 | } 22 | 23 | void wrReg( int r, int v) { 24 | wrDout(r,0); 25 | wrDout(v,1); 26 | } 27 | 28 | void psg_setup() { 29 | // reset - if not c 30 | digitalWrite(ICPIN,0); 31 | delay(100); 32 | digitalWrite(ICPIN,1); 33 | delay(100); 34 | 35 | wrReg(1,0xf); 36 | wrReg(0,0x80); 37 | wrReg(3,0xf); 38 | wrReg(5,0x80); 39 | wrReg(2,0xf); 40 | wrReg(4,0x80); 41 | 42 | // wrReg(0x2d,0); // pre scaler 658 kHz 43 | // wrReg(0x2e,0); // pre scaler 1.3 MHz 44 | wrReg(0x21,0); // no test 45 | wrReg(0x2f,0); // pre scaler 2.0 MHz, SSG=full clock 46 | wrReg(7, 0370 ); // tone enabled, IO ports as outputs 47 | wrReg(6, 0x1f ); // noise 48 | 49 | for(int k=010; k<013;k++ ) wrReg( k, 15 ); 50 | wrReg(011,13); 51 | delay(11); 52 | } 53 | 54 | int edge() { 55 | static int last=0; 56 | int b = (PINB>>5)&1; 57 | int edge = b && !last; 58 | last = b; 59 | return edge; 60 | } 61 | 62 | void loop() { 63 | static unsigned old=0, volB=0; 64 | unsigned amp = analogRead(A0)>>2; 65 | // if( edge() ) volB += 4; 66 | // // volB = volB==15 ? 0 : (volB<<1)|1; 67 | // wrReg( 011, volB ); // volume channel B 68 | // wrReg( 0xf, volB ); // show on YM2203's port B 69 | if( old!= amp ) wrReg(2,0x80|(amp>>3)); 70 | old=amp; 71 | delay(20); 72 | } 73 | 74 | -------------------------------------------------------------------------------- /lab/io/io.ino: -------------------------------------------------------------------------------- 1 | const int A0PIN=8, // PB0 2 | WRPIN=9, // PB1 3 | ICPIN=10; // PB2 4 | 5 | void setup() { 6 | // Set ports B and D as an output 7 | DDRD=0xff; 8 | DDRB=0xff; 9 | // PSG 10 | psg_setup(); 11 | } 12 | 13 | void wrDout(int v, int a0 ) { 14 | PORTD=v; 15 | a0=(a0&1)|4; // keep IC high (bit 2) 16 | PORTB=a0; // WR low 17 | PORTB=a0|0x02; // WR high 18 | // delay(1); 19 | } 20 | 21 | void wrReg( int r, int v) { 22 | wrDout(r,0); 23 | wrDout(v,1); 24 | } 25 | 26 | void psg_setup() { 27 | // reset - if not c 28 | digitalWrite(ICPIN,0); 29 | delay(100); 30 | digitalWrite(ICPIN,1); 31 | delay(100); 32 | 33 | wrReg(1,0xf); 34 | wrReg(0,0x95); 35 | wrReg(3,0xd); 36 | wrReg(5,0xab); 37 | wrReg(2,0x6); 38 | wrReg(4,0x53); 39 | 40 | // wrReg(0x2d,0); // pre scaler 658 kHz 41 | // wrReg(0x2e,0); // pre scaler 1.3 MHz 42 | wrReg(0x21,0); // no test 43 | wrReg(0x2f,0); // pre scaler 2.0 MHz, SSG=full clock 44 | wrReg(7, 0376 ); // tone enabled, IO ports as outputs 45 | // wrReg(7, 0334 ); // noise enabled, IO ports as outputs 46 | wrReg(6, 0x1f ); // noise 47 | wrReg( 010, 0 ); 48 | wrReg( 011, 0 ); 49 | wrReg( 012, 0 ); 50 | 51 | 52 | wrReg( 010, 15 ); 53 | wrReg( 011, 0 ); 54 | wrReg( 012, 0 ); 55 | delay(11); 56 | } 57 | 58 | void loop() { 59 | int amp = analogRead(A0)>>6; 60 | wrReg( 0xf, amp ); // show on port B 61 | wrReg( 010, amp ); // volume channel A 62 | delay(20); 63 | } 64 | 65 | -------------------------------------------------------------------------------- /lab/kicad/.gitignore: -------------------------------------------------------------------------------- 1 | fp-info-cache 2 | -------------------------------------------------------------------------------- /lab/kicad/arduino.kicad_prl: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "active_layer": 0, 4 | "active_layer_preset": "All Layers", 5 | "auto_track_width": true, 6 | "hidden_netclasses": [], 7 | "hidden_nets": [], 8 | "high_contrast_mode": 0, 9 | "net_color_mode": 1, 10 | "opacity": { 11 | "images": 0.6, 12 | "pads": 1.0, 13 | "tracks": 1.0, 14 | "vias": 1.0, 15 | "zones": 0.6 16 | }, 17 | "selection_filter": { 18 | "dimensions": true, 19 | "footprints": true, 20 | "graphics": true, 21 | "keepouts": true, 22 | "lockedItems": false, 23 | "otherItems": true, 24 | "pads": true, 25 | "text": true, 26 | "tracks": true, 27 | "vias": true, 28 | "zones": true 29 | }, 30 | "visible_items": [ 31 | 0, 32 | 1, 33 | 2, 34 | 3, 35 | 4, 36 | 5, 37 | 8, 38 | 9, 39 | 10, 40 | 11, 41 | 12, 42 | 13, 43 | 15, 44 | 16, 45 | 17, 46 | 18, 47 | 19, 48 | 20, 49 | 21, 50 | 22, 51 | 23, 52 | 24, 53 | 25, 54 | 26, 55 | 27, 56 | 28, 57 | 29, 58 | 30, 59 | 32, 60 | 33, 61 | 34, 62 | 35, 63 | 36, 64 | 39, 65 | 40 66 | ], 67 | "visible_layers": "fffffff_ffffffff", 68 | "zone_display_mode": 0 69 | }, 70 | "git": { 71 | "repo_password": "", 72 | "repo_type": "", 73 | "repo_username": "", 74 | "ssh_key": "" 75 | }, 76 | "meta": { 77 | "filename": "arduino.kicad_prl", 78 | "version": 3 79 | }, 80 | "project": { 81 | "files": [] 82 | } 83 | } 84 | -------------------------------------------------------------------------------- /lab/kicad/arduino.kicad_pro: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "3dviewports": [], 4 | "design_settings": { 5 | "defaults": { 6 | "apply_defaults_to_fp_fields": false, 7 | "apply_defaults_to_fp_shapes": false, 8 | "apply_defaults_to_fp_text": false, 9 | "board_outline_line_width": 0.05, 10 | "copper_line_width": 0.2, 11 | "copper_text_italic": false, 12 | "copper_text_size_h": 1.5, 13 | "copper_text_size_v": 1.5, 14 | "copper_text_thickness": 0.3, 15 | "copper_text_upright": false, 16 | "courtyard_line_width": 0.05, 17 | "dimension_precision": 4, 18 | "dimension_units": 3, 19 | "dimensions": { 20 | "arrow_length": 1270000, 21 | "extension_offset": 500000, 22 | "keep_text_aligned": true, 23 | "suppress_zeroes": false, 24 | "text_position": 0, 25 | "units_format": 1 26 | }, 27 | "fab_line_width": 0.1, 28 | "fab_text_italic": false, 29 | "fab_text_size_h": 1.0, 30 | "fab_text_size_v": 1.0, 31 | "fab_text_thickness": 0.15, 32 | "fab_text_upright": false, 33 | "other_line_width": 0.1, 34 | "other_text_italic": false, 35 | "other_text_size_h": 1.0, 36 | "other_text_size_v": 1.0, 37 | "other_text_thickness": 0.15, 38 | "other_text_upright": false, 39 | "pads": { 40 | "drill": 0.762, 41 | "height": 1.524, 42 | "width": 1.524 43 | }, 44 | "silk_line_width": 0.1, 45 | "silk_text_italic": false, 46 | "silk_text_size_h": 1.0, 47 | "silk_text_size_v": 1.0, 48 | "silk_text_thickness": 0.1, 49 | "silk_text_upright": false, 50 | "zones": { 51 | "min_clearance": 0.5 52 | } 53 | }, 54 | "diff_pair_dimensions": [], 55 | "drc_exclusions": [], 56 | "meta": { 57 | "version": 2 58 | }, 59 | "rule_severities": { 60 | "annular_width": "error", 61 | "clearance": "error", 62 | "connection_width": "warning", 63 | "copper_edge_clearance": "error", 64 | "copper_sliver": "warning", 65 | "courtyards_overlap": "error", 66 | "diff_pair_gap_out_of_range": "error", 67 | "diff_pair_uncoupled_length_too_long": "error", 68 | "drill_out_of_range": "error", 69 | "duplicate_footprints": "warning", 70 | "extra_footprint": "warning", 71 | "footprint": "error", 72 | "footprint_symbol_mismatch": "warning", 73 | "footprint_type_mismatch": "ignore", 74 | "hole_clearance": "error", 75 | "hole_near_hole": "error", 76 | "holes_co_located": "warning", 77 | "invalid_outline": "error", 78 | "isolated_copper": "warning", 79 | "item_on_disabled_layer": "error", 80 | "items_not_allowed": "error", 81 | "length_out_of_range": "error", 82 | "lib_footprint_issues": "warning", 83 | "lib_footprint_mismatch": "warning", 84 | "malformed_courtyard": "error", 85 | "microvia_drill_out_of_range": "error", 86 | "missing_courtyard": "ignore", 87 | "missing_footprint": "warning", 88 | "net_conflict": "warning", 89 | "npth_inside_courtyard": "ignore", 90 | "padstack": "warning", 91 | "pth_inside_courtyard": "ignore", 92 | "shorting_items": "error", 93 | "silk_edge_clearance": "warning", 94 | "silk_over_copper": "warning", 95 | "silk_overlap": "warning", 96 | "skew_out_of_range": "error", 97 | "solder_mask_bridge": "error", 98 | "starved_thermal": "error", 99 | "text_height": "warning", 100 | "text_thickness": "warning", 101 | "through_hole_pad_without_hole": "error", 102 | "too_many_vias": "error", 103 | "track_dangling": "warning", 104 | "track_width": "error", 105 | "tracks_crossing": "error", 106 | "unconnected_items": "error", 107 | "unresolved_variable": "error", 108 | "via_dangling": "warning", 109 | "zones_intersect": "error" 110 | }, 111 | "rules": { 112 | "max_error": 0.005, 113 | "min_clearance": 0.0, 114 | "min_connection": 0.0, 115 | "min_copper_edge_clearance": 0.5, 116 | "min_hole_clearance": 0.25, 117 | "min_hole_to_hole": 0.25, 118 | "min_microvia_diameter": 0.2, 119 | "min_microvia_drill": 0.1, 120 | "min_resolved_spokes": 2, 121 | "min_silk_clearance": 0.0, 122 | "min_text_height": 0.8, 123 | "min_text_thickness": 0.08, 124 | "min_through_hole_diameter": 0.3, 125 | "min_track_width": 0.0, 126 | "min_via_annular_width": 0.1, 127 | "min_via_diameter": 0.5, 128 | "solder_mask_to_copper_clearance": 0.0, 129 | "use_height_for_length_calcs": true 130 | }, 131 | "teardrop_options": [ 132 | { 133 | "td_onpadsmd": true, 134 | "td_onroundshapesonly": false, 135 | "td_ontrackend": false, 136 | "td_onviapad": true 137 | } 138 | ], 139 | "teardrop_parameters": [ 140 | { 141 | "td_allow_use_two_tracks": true, 142 | "td_curve_segcount": 0, 143 | "td_height_ratio": 1.0, 144 | "td_length_ratio": 0.5, 145 | "td_maxheight": 2.0, 146 | "td_maxlen": 1.0, 147 | "td_on_pad_in_zone": false, 148 | "td_target_name": "td_round_shape", 149 | "td_width_to_size_filter_ratio": 0.9 150 | }, 151 | { 152 | "td_allow_use_two_tracks": true, 153 | "td_curve_segcount": 0, 154 | "td_height_ratio": 1.0, 155 | "td_length_ratio": 0.5, 156 | "td_maxheight": 2.0, 157 | "td_maxlen": 1.0, 158 | "td_on_pad_in_zone": false, 159 | "td_target_name": "td_rect_shape", 160 | "td_width_to_size_filter_ratio": 0.9 161 | }, 162 | { 163 | "td_allow_use_two_tracks": true, 164 | "td_curve_segcount": 0, 165 | "td_height_ratio": 1.0, 166 | "td_length_ratio": 0.5, 167 | "td_maxheight": 2.0, 168 | "td_maxlen": 1.0, 169 | "td_on_pad_in_zone": false, 170 | "td_target_name": "td_track_end", 171 | "td_width_to_size_filter_ratio": 0.9 172 | } 173 | ], 174 | "track_widths": [], 175 | "tuning_pattern_settings": { 176 | "diff_pair_defaults": { 177 | "corner_radius_percentage": 80, 178 | "corner_style": 1, 179 | "max_amplitude": 1.0, 180 | "min_amplitude": 0.2, 181 | "single_sided": false, 182 | "spacing": 1.0 183 | }, 184 | "diff_pair_skew_defaults": { 185 | "corner_radius_percentage": 80, 186 | "corner_style": 1, 187 | "max_amplitude": 1.0, 188 | "min_amplitude": 0.2, 189 | "single_sided": false, 190 | "spacing": 0.6 191 | }, 192 | "single_track_defaults": { 193 | "corner_radius_percentage": 80, 194 | "corner_style": 1, 195 | "max_amplitude": 1.0, 196 | "min_amplitude": 0.2, 197 | "single_sided": false, 198 | "spacing": 0.6 199 | } 200 | }, 201 | "via_dimensions": [], 202 | "zones_allow_external_fillets": false 203 | }, 204 | "ipc2581": { 205 | "dist": "", 206 | "distpn": "", 207 | "internal_id": "", 208 | "mfg": "", 209 | "mpn": "" 210 | }, 211 | "layer_presets": [], 212 | "viewports": [] 213 | }, 214 | "boards": [], 215 | "cvpcb": { 216 | "equivalence_files": [] 217 | }, 218 | "erc": { 219 | "erc_exclusions": [], 220 | "meta": { 221 | "version": 0 222 | }, 223 | "pin_map": [ 224 | [ 225 | 0, 226 | 0, 227 | 0, 228 | 0, 229 | 0, 230 | 0, 231 | 1, 232 | 0, 233 | 0, 234 | 0, 235 | 0, 236 | 2 237 | ], 238 | [ 239 | 0, 240 | 2, 241 | 0, 242 | 1, 243 | 0, 244 | 0, 245 | 1, 246 | 0, 247 | 2, 248 | 2, 249 | 2, 250 | 2 251 | ], 252 | [ 253 | 0, 254 | 0, 255 | 0, 256 | 0, 257 | 0, 258 | 0, 259 | 1, 260 | 0, 261 | 1, 262 | 0, 263 | 1, 264 | 2 265 | ], 266 | [ 267 | 0, 268 | 1, 269 | 0, 270 | 0, 271 | 0, 272 | 0, 273 | 1, 274 | 1, 275 | 2, 276 | 1, 277 | 1, 278 | 2 279 | ], 280 | [ 281 | 0, 282 | 0, 283 | 0, 284 | 0, 285 | 0, 286 | 0, 287 | 1, 288 | 0, 289 | 0, 290 | 0, 291 | 0, 292 | 2 293 | ], 294 | [ 295 | 0, 296 | 0, 297 | 0, 298 | 0, 299 | 0, 300 | 0, 301 | 0, 302 | 0, 303 | 0, 304 | 0, 305 | 0, 306 | 2 307 | ], 308 | [ 309 | 1, 310 | 1, 311 | 1, 312 | 1, 313 | 1, 314 | 0, 315 | 1, 316 | 1, 317 | 1, 318 | 1, 319 | 1, 320 | 2 321 | ], 322 | [ 323 | 0, 324 | 0, 325 | 0, 326 | 1, 327 | 0, 328 | 0, 329 | 1, 330 | 0, 331 | 0, 332 | 0, 333 | 0, 334 | 2 335 | ], 336 | [ 337 | 0, 338 | 2, 339 | 1, 340 | 2, 341 | 0, 342 | 0, 343 | 1, 344 | 0, 345 | 2, 346 | 2, 347 | 2, 348 | 2 349 | ], 350 | [ 351 | 0, 352 | 2, 353 | 0, 354 | 1, 355 | 0, 356 | 0, 357 | 1, 358 | 0, 359 | 2, 360 | 0, 361 | 0, 362 | 2 363 | ], 364 | [ 365 | 0, 366 | 2, 367 | 1, 368 | 1, 369 | 0, 370 | 0, 371 | 1, 372 | 0, 373 | 2, 374 | 0, 375 | 0, 376 | 2 377 | ], 378 | [ 379 | 2, 380 | 2, 381 | 2, 382 | 2, 383 | 2, 384 | 2, 385 | 2, 386 | 2, 387 | 2, 388 | 2, 389 | 2, 390 | 2 391 | ] 392 | ], 393 | "rule_severities": { 394 | "bus_definition_conflict": "error", 395 | "bus_entry_needed": "error", 396 | "bus_to_bus_conflict": "error", 397 | "bus_to_net_conflict": "error", 398 | "conflicting_netclasses": "error", 399 | "different_unit_footprint": "error", 400 | "different_unit_net": "error", 401 | "duplicate_reference": "error", 402 | "duplicate_sheet_names": "error", 403 | "endpoint_off_grid": "warning", 404 | "extra_units": "error", 405 | "global_label_dangling": "warning", 406 | "hier_label_mismatch": "error", 407 | "label_dangling": "error", 408 | "lib_symbol_issues": "warning", 409 | "missing_bidi_pin": "warning", 410 | "missing_input_pin": "warning", 411 | "missing_power_pin": "error", 412 | "missing_unit": "warning", 413 | "multiple_net_names": "warning", 414 | "net_not_bus_member": "warning", 415 | "no_connect_connected": "warning", 416 | "no_connect_dangling": "warning", 417 | "pin_not_connected": "error", 418 | "pin_not_driven": "error", 419 | "pin_to_pin": "warning", 420 | "power_pin_not_driven": "error", 421 | "similar_labels": "warning", 422 | "simulation_model_issue": "ignore", 423 | "unannotated": "error", 424 | "unit_value_mismatch": "error", 425 | "unresolved_variable": "error", 426 | "wire_dangling": "error" 427 | } 428 | }, 429 | "libraries": { 430 | "pinned_footprint_libs": [], 431 | "pinned_symbol_libs": [] 432 | }, 433 | "meta": { 434 | "filename": "arduino.kicad_pro", 435 | "version": 1 436 | }, 437 | "net_settings": { 438 | "classes": [ 439 | { 440 | "bus_width": 12, 441 | "clearance": 0.2, 442 | "diff_pair_gap": 0.25, 443 | "diff_pair_via_gap": 0.25, 444 | "diff_pair_width": 0.2, 445 | "line_style": 0, 446 | "microvia_diameter": 0.3, 447 | "microvia_drill": 0.1, 448 | "name": "Default", 449 | "pcb_color": "rgba(0, 0, 0, 0.000)", 450 | "schematic_color": "rgba(0, 0, 0, 0.000)", 451 | "track_width": 0.2, 452 | "via_diameter": 0.6, 453 | "via_drill": 0.3, 454 | "wire_width": 6 455 | } 456 | ], 457 | "meta": { 458 | "version": 3 459 | }, 460 | "net_colors": null, 461 | "netclass_assignments": null, 462 | "netclass_patterns": [] 463 | }, 464 | "pcbnew": { 465 | "last_paths": { 466 | "gencad": "", 467 | "idf": "", 468 | "netlist": "", 469 | "plot": "", 470 | "pos_files": "", 471 | "specctra_dsn": "", 472 | "step": "", 473 | "svg": "", 474 | "vrml": "" 475 | }, 476 | "page_layout_descr_file": "" 477 | }, 478 | "schematic": { 479 | "annotate_start_num": 0, 480 | "bom_export_filename": "", 481 | "bom_fmt_presets": [], 482 | "bom_fmt_settings": { 483 | "field_delimiter": ",", 484 | "keep_line_breaks": false, 485 | "keep_tabs": false, 486 | "name": "CSV", 487 | "ref_delimiter": ",", 488 | "ref_range_delimiter": "", 489 | "string_delimiter": "\"" 490 | }, 491 | "bom_presets": [], 492 | "bom_settings": { 493 | "exclude_dnp": false, 494 | "fields_ordered": [ 495 | { 496 | "group_by": false, 497 | "label": "Reference", 498 | "name": "Reference", 499 | "show": true 500 | }, 501 | { 502 | "group_by": true, 503 | "label": "Value", 504 | "name": "Value", 505 | "show": true 506 | }, 507 | { 508 | "group_by": false, 509 | "label": "Datasheet", 510 | "name": "Datasheet", 511 | "show": true 512 | }, 513 | { 514 | "group_by": false, 515 | "label": "Footprint", 516 | "name": "Footprint", 517 | "show": true 518 | }, 519 | { 520 | "group_by": false, 521 | "label": "Qty", 522 | "name": "${QUANTITY}", 523 | "show": true 524 | }, 525 | { 526 | "group_by": true, 527 | "label": "DNP", 528 | "name": "${DNP}", 529 | "show": true 530 | } 531 | ], 532 | "filter_string": "", 533 | "group_symbols": true, 534 | "name": "Grouped By Value", 535 | "sort_asc": true, 536 | "sort_field": "Reference" 537 | }, 538 | "connection_grid_size": 50.0, 539 | "drawing": { 540 | "dashed_lines_dash_length_ratio": 12.0, 541 | "dashed_lines_gap_length_ratio": 3.0, 542 | "default_line_thickness": 6.0, 543 | "default_text_size": 50.0, 544 | "field_names": [], 545 | "intersheets_ref_own_page": false, 546 | "intersheets_ref_prefix": "", 547 | "intersheets_ref_short": false, 548 | "intersheets_ref_show": false, 549 | "intersheets_ref_suffix": "", 550 | "junction_size_choice": 3, 551 | "label_size_ratio": 0.375, 552 | "operating_point_overlay_i_precision": 3, 553 | "operating_point_overlay_i_range": "~A", 554 | "operating_point_overlay_v_precision": 3, 555 | "operating_point_overlay_v_range": "~V", 556 | "overbar_offset_ratio": 1.23, 557 | "pin_symbol_size": 25.0, 558 | "text_offset_ratio": 0.15 559 | }, 560 | "legacy_lib_dir": "", 561 | "legacy_lib_list": [], 562 | "meta": { 563 | "version": 1 564 | }, 565 | "net_format_name": "", 566 | "page_layout_descr_file": "", 567 | "plot_directory": "", 568 | "spice_current_sheet_as_root": false, 569 | "spice_external_command": "spice \"%I\"", 570 | "spice_model_current_sheet_as_root": true, 571 | "spice_save_all_currents": false, 572 | "spice_save_all_dissipations": false, 573 | "spice_save_all_voltages": false, 574 | "subpart_first_id": 65, 575 | "subpart_id_separator": 0 576 | }, 577 | "sheets": [ 578 | [ 579 | "d1a73334-7268-43b7-b5b2-0910889be86d", 580 | "Root" 581 | ] 582 | ], 583 | "text_variables": {} 584 | } 585 | -------------------------------------------------------------------------------- /lab/kicad/sym-lib-table: -------------------------------------------------------------------------------- 1 | ../../../../jtkicad/sym-lib-table -------------------------------------------------------------------------------- /lab/sweep/sweep.ino: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | pin connections 4 | 5 | Arduino | YM2203 | Use 6 | ----------|---------|----- 7 | 2 | 40 | D0 8 | 3 | 2 | D1 9 | 4 | 3 | D2 10 | 5 | 4 | D3 11 | 6 | 5 | D4 12 | 7 | 6 | D5 13 | 8 | 7 | D6 14 | 9 | 38 | phi M 15 | 10 | 8 | D7 16 | 11 | 37 | A0 17 | 12 | 35 | /WR 18 | 13 | 24 | /IC (reset) 19 | A0 | 20 | resistor (channel A) 20 | 21 | Other YM2203 pins 22 | 23 | YM2203 | Connection 24 | -------|-------------- 25 | 1 | GND (ground) 26 | 9-16 | NC 27 | 17 | GND 28 | 18-19 | NC/short to 20 (channels B, C) 29 | 39 | NC 30 | 36 | VCC (/RD) 31 | 34 | GND (/CS)R_US 32 | 25-33 | NC 33 | 22-23 | NC 34 | 21 | VCC (supply) 35 | 36 | Measure: 37 | 38 | Run the program for each of these configurations: 39 | 40 | 1. Connect channel A to 1 kOhm, leave channels B,C disconnected 41 | 2. Connect channel A to 10 kOhm, leave channels B,C disconnected 42 | 3. Join channels A,B,C to the same 1 kOhm resistor 43 | 4. Join channels A,B,C to the same 10 kOhm resistor 44 | 45 | */ 46 | 47 | const int A0PIN=8, WRPIN=9, ICPIN=10; 48 | 49 | void setup() { 50 | // Set Pins 2-12 as an output 51 | DDRD=0xff; 52 | DDRB=0xff; 53 | // pinMode(A0PIN, OUTPUT); 54 | // pinMode(WRPIN, OUTPUT); 55 | // pinMode(ICPIN, OUTPUT); 56 | // PSG 57 | psg_setup(); 58 | // Serial.begin(9600); 59 | } 60 | 61 | void wrDout(int v) { 62 | PORTD=v&0xff; 63 | PORTB=PINB&0xfd; // WR low 64 | PORTB=PINB|0x02; // WR high 65 | } 66 | 67 | void wrReg( int r, int v) { 68 | PORTB=0xfe; // A0 low 69 | wrDout(r); 70 | PORTB=0xff; // A0 hihg 71 | wrDout(v); 72 | } 73 | 74 | void psg_setup() { 75 | // reset 76 | digitalWrite(ICPIN,0); 77 | delay(100); 78 | digitalWrite(ICPIN,1); 79 | delay(100); 80 | 81 | for(int k=0;k<6;k+=2) { // set minimum freq for all channels 82 | wrReg(0+k,0xff); 83 | wrReg(1+k,0x0); 84 | } 85 | wrReg(7, 7<<3 ); // tone enable 86 | wrReg(11, 0 ); // fast envelope 87 | wrReg(12, 0 ); 88 | wrReg(13, 13 ); // envelope held high 89 | } 90 | 91 | // void loop() { 92 | // for(int k=0;;k++) PORTD=k&0xff; 93 | // } 94 | 95 | void loop() { 96 | psg_setup(); 97 | int vol[3]={0,0,0}; 98 | char str[64]; 99 | for(int ch=0;ch<3;ch++) { 100 | for(int k=0;k<16;k++) { 101 | vol[ch]=k; 102 | wrReg( 8,vol[0]); 103 | wrReg( 9,vol[1]); 104 | wrReg(10,vol[2]); 105 | delay(50); 106 | int amp = analogRead(A0); 107 | sprintf(str,"%d,%d,%d,%04d",vol[0],vol[1],vol[2],amp); 108 | // Serial.println(str); 109 | } 110 | } 111 | } 112 | 113 | -------------------------------------------------------------------------------- /lab/ym2203/DS1Z_QuickPrint20.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jotego/jt49/7f6abfd08a2af9a92dbd5b32c71ea773248a77e2/lab/ym2203/DS1Z_QuickPrint20.png -------------------------------------------------------------------------------- /lab/ym2203/DS1Z_QuickPrint23.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jotego/jt49/7f6abfd08a2af9a92dbd5b32c71ea773248a77e2/lab/ym2203/DS1Z_QuickPrint23.png -------------------------------------------------------------------------------- /lab/ym2203/ym2203_setup.jpeg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/jotego/jt49/7f6abfd08a2af9a92dbd5b32c71ea773248a77e2/lab/ym2203/ym2203_setup.jpeg -------------------------------------------------------------------------------- /lut/go.mod: -------------------------------------------------------------------------------- 1 | module github.com/jotego/jt49 2 | 3 | go 1.21.3 4 | -------------------------------------------------------------------------------- /lut/main.go: -------------------------------------------------------------------------------- 1 | package main 2 | 3 | import( 4 | "fmt" 5 | ) 6 | 7 | const roff_small=3e6 8 | const ron_large =900 9 | const scale=1.55 10 | const vdd=5.0 11 | 12 | var goff, gon [16]float64 13 | 14 | func conductance(a int) (g float64) { 15 | g = 0 16 | a&=0xf 17 | for k:=0;k<16;k++ { 18 | if k==a { 19 | g += gon[k] 20 | } else { 21 | g += goff[k] 22 | } 23 | } 24 | return g 25 | } 26 | 27 | func fill_glut() { 28 | goff[0]=1.0/roff_small 29 | for k:=1; k<16;k++ { 30 | goff[k] = goff[k-1]*scale 31 | } 32 | gon[15]=1.0/ron_large 33 | for k:=14;k>=0;k-- { 34 | gon[k] = gon[k+1]/scale 35 | } 36 | // for k:=0;k<16;k++ { 37 | // fmt.Printf("%e,%e\n",goff[k],gon[k]) 38 | // } 39 | } 40 | 41 | func vout(rout, rload float64) float64 { 42 | return rload/(rload+rout)*vdd 43 | } 44 | 45 | func single_output(rload float64) { 46 | for k:=0; k<0x10; k++ { 47 | rt := 1.0/conductance(k) 48 | fmt.Printf("%02d,%.0f Ohm,%f V\n",k,rload,vout(rt, rload)) 49 | } 50 | } 51 | 52 | // func 53 | // for k:=0; k<0x400; k++ { 54 | // g1 := conductance(k) 55 | // g2 := conductance(k>>4) 56 | // g3 := conductance(k>>8) 57 | // gt = g1+g2+g3 58 | // } 59 | func main() { 60 | fill_glut() 61 | single_output(1000) 62 | single_output(10000) 63 | } -------------------------------------------------------------------------------- /syn/quartus/jt49.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../hdl/jt49.v ] 2 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../hdl/jt49_bus.v ] 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../hdl/jt49_div.v ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../hdl/jt49_cen.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../hdl/jt49_eg.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../hdl/jt49_exp.v ] 7 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ../../hdl/jt49_noise.v ] 8 | -------------------------------------------------------------------------------- /ver/clkdiv/go: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog test.v ../../hdl/jt49_div.v -o sim && ./sim -lxt 4 | -------------------------------------------------------------------------------- /ver/clkdiv/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module test; 4 | 5 | reg clk, cen=1'b1, rst_n; 6 | 7 | initial begin 8 | clk = 0; 9 | forever clk = #5 ~clk; 10 | end 11 | 12 | initial begin 13 | rst_n = 1'b0; 14 | #50 rst_n = 1'b1; 15 | end 16 | 17 | initial begin 18 | $dumpfile("test.lxt"); 19 | $dumpvars; 20 | $dumpon; 21 | #(10*15*4*16) $finish; 22 | end 23 | 24 | reg [3:0] period; 25 | 26 | initial begin 27 | period = 4'h0; 28 | forever #(10*15*4) period = period+4'h1; 29 | end 30 | 31 | // always @(negedge clk) 32 | // cen <= ~cen; 33 | 34 | wire div; 35 | 36 | jt49_div #(.W(4) ) uut ( 37 | .clk ( clk ), 38 | .cen ( cen ), 39 | .rst_n ( rst_n ), 40 | .period ( period ), 41 | .div ( div ) 42 | ); 43 | 44 | endmodule // jt49_cen_div 45 | -------------------------------------------------------------------------------- /ver/comp/cmd.hex: -------------------------------------------------------------------------------- 1 | 100 2 | 0 3 | 101 4 | 0 5 | 102 6 | 1 7 | 103 8 | 0 9 | 104 10 | FF 11 | 105 12 | F 13 | 106 14 | 0 15 | 108 16 | 1 17 | 109 18 | 2 19 | 10A 20 | 4 21 | 2FF 22 | 108 23 | 2 24 | 2FF 25 | 108 26 | 4 27 | 2FF 28 | 108 29 | 8 30 | 2FF 31 | 108 32 | A 33 | 2FF 34 | 108 35 | D 36 | 2FF 37 | 108 38 | F 39 | 2FF 40 | 108 41 | 10 42 | 10D 43 | 0 44 | 10B 45 | 80 46 | 10C 47 | 0 48 | 2FF 49 | 2FF 50 | 106 51 | 7 52 | 2FF 53 | 106 54 | 1 55 | 2FF 56 | 10D 57 | 0 58 | 2FF 59 | 2FF 60 | 2FF 61 | 2FF 62 | 10D 63 | 1 64 | 2FF 65 | 2FF 66 | 2FF 67 | 2FF 68 | 10D 69 | 2 70 | 2FF 71 | 2FF 72 | 2FF 73 | 2FF 74 | 10D 75 | 3 76 | 2FF 77 | 2FF 78 | 2FF 79 | 2FF 80 | 10D 81 | 4 82 | 2FF 83 | 2FF 84 | 2FF 85 | 2FF 86 | 10D 87 | 5 88 | 2FF 89 | 2FF 90 | 2FF 91 | 2FF 92 | 10D 93 | 6 94 | 2FF 95 | 2FF 96 | 2FF 97 | 2FF 98 | 10D 99 | 7 100 | 2FF 101 | 2FF 102 | 2FF 103 | 2FF 104 | 10D 105 | 8 106 | 2FF 107 | 2FF 108 | 2FF 109 | 2FF 110 | 10D 111 | 9 112 | 2FF 113 | 2FF 114 | 2FF 115 | 2FF 116 | 10D 117 | A 118 | 2FF 119 | 2FF 120 | 2FF 121 | 2FF 122 | 10D 123 | B 124 | 2FF 125 | 2FF 126 | 2FF 127 | 2FF 128 | 10D 129 | C 130 | 2FF 131 | 2FF 132 | 2FF 133 | 2FF 134 | 10D 135 | D 136 | 2FF 137 | 2FF 138 | 2FF 139 | 2FF 140 | 10D 141 | E 142 | 2FF 143 | 2FF 144 | 2FF 145 | 2FF 146 | 10D 147 | F 148 | 2FF 149 | 2FF 150 | 2FF 151 | 2FF 152 | 300 153 | -------------------------------------------------------------------------------- /ver/comp/gather.f: -------------------------------------------------------------------------------- 1 | test.v 2 | ../../hdl/jt49_noise.v 3 | ../../hdl/jt49.v 4 | ../../hdl/jt49_bus.v 5 | ../../hdl/jt49_cen.v 6 | ../../hdl/jt49_exp.v 7 | ../../hdl/jt49_eg.v 8 | ../../hdl/jt49_div.v 9 | ../../doc/sch/rtl/ay_model.v 10 | -------------------------------------------------------------------------------- /ver/comp/go.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | gawk -f parser.awk test_cmd > cmd.hex || exit $? 4 | 5 | ncverilog -f gather.f +access+r 6 | -------------------------------------------------------------------------------- /ver/comp/parser.awk: -------------------------------------------------------------------------------- 1 | BEGIN { 2 | for( i=0; i<4096; i++ ) 3 | mem[i]=0x300 4 | cnt=0 5 | } 6 | function add_cmd(val) { 7 | mem[cnt]=val 8 | cnt=cnt+1 9 | } 10 | function validate_ch(c) { 11 | if( ch!="a" && ch!="b" && ch!="c" && ch!="no" && ch!="env" ) { 12 | print "ERROR: bad channel at line " FNR ". Used '" ch "'" > "/dev/stderr" 13 | exit 1 14 | } 15 | } 16 | function validate_arg(val,min,max) { 17 | if( valmax ) { 18 | print "ERROR: value should be bettwen " min " and " max " at " FNR > "/dev/stderr" 19 | exit 1 20 | } 21 | } 22 | /vol / { 23 | allargs=substr($0,4) 24 | gsub( " ", "", allargs ) 25 | split( allargs, cmdargs, "," ) 26 | ch=cmdargs[1] 27 | val=strtonum(cmdargs[2]) 28 | validate_ch(ch) 29 | if( ch=="a" ) ch=8 30 | else if( ch=="b" ) ch=9 31 | else if( ch=="c" ) ch=10 32 | validate_arg( val, 0, 0x1f ) 33 | add_cmd( 0x100 + ch ) # address 34 | add_cmd( val ) 35 | next 36 | } 37 | /period / { 38 | allargs=substr($0,7) 39 | gsub( " ", "", allargs ) 40 | split( allargs, cmdargs, "," ) 41 | ch=cmdargs[1] 42 | val=strtonum(cmdargs[2]) 43 | validate_ch(ch) 44 | if( ch=="a" ) ch=0 45 | else if( ch=="b" ) ch=2 46 | else if( ch=="c" ) ch=4 47 | else if( ch=="no") ch=6 48 | else if( ch=="env") ch=013 49 | if( ch<6 || ch==013) { 50 | lsb=val%256 51 | msb=(val-lsb)/256 52 | if( ch==6 ) validate_arg( val, 0, 0xfff ) 53 | if( ch==013 ) validate_arg( val, 0, 0xffff ) 54 | add_cmd( 0x100 + ch ) # address 55 | add_cmd( lsb ) 56 | add_cmd( 0x100 + ch +1 ) # address 57 | add_cmd( msb ) 58 | } else if(ch==6) { # Noise 59 | lsb=val%32 60 | add_cmd( 0x100 + ch ) # address 61 | add_cmd( lsb ) 62 | } 63 | next 64 | } 65 | /shape/ { 66 | allargs=substr($0,6) 67 | gsub(" ", "", allargs) 68 | val=strtonum(allargs) 69 | validate_arg( val, 0, 0xf) 70 | add_cmd(0x100+015 ) # Octal! 71 | add_cmd(val) 72 | next 73 | } 74 | /^#/ { 75 | next 76 | } 77 | /wait / { 78 | split( $0, cmdargs, " " ) 79 | waitcnt=strtonum(cmdargs[2]) 80 | if(waitcnt>255 || waitcnt==0) { 81 | print "ERROR: wait cannot be longer than 255 or be zero. " waitcnt " was used." 82 | exit 1 83 | } 84 | add_cmd(0x200 + waitcnt) 85 | next 86 | } 87 | /finish/ { 88 | add_cmd(0x300) 89 | next 90 | } 91 | { 92 | print "ERROR: cannot parse line " $0 > "/dev/stderr" 93 | exit 1 94 | } 95 | END { 96 | for( i=0; i0 ) begin 49 | cntwait <= cntwait-1; 50 | bc1 <= 0; 51 | bdir <= 0; 52 | end else begin 53 | casez( nextcmd[9:8] ) 54 | 2'b0?: begin 55 | bdir <= 1; 56 | bc1 <= nextcmd[8]; 57 | din <= cmdmem[cntcmd][7:0]; 58 | cntwait <= 8; 59 | end 60 | 2'b10: begin 61 | bdir <= 0; 62 | bc1 <= 0; 63 | cntwait <= { nextcmd[7:0], 8'd0 }; 64 | end 65 | 2'b11: $finish; 66 | endcase 67 | cntcmd <= cntcmd+1; 68 | if( cntcmd==4095 ) $finish; 69 | end 70 | end 71 | 72 | jt49_bus uut( // note that input ports are not multiplexed 73 | .rst_n ( rstn ), 74 | .clk ( clk ), // signal on positive edge 75 | .clk_en ( cen ) /* synthesis direct_enable = 1 */, 76 | // bus control pins of original chip 77 | .bdir ( bdir ), 78 | .bc1 ( bc1 ), 79 | .din ( din ), 80 | 81 | .sel ( 1'b1 ), // if sel is low, the clock is divided by 2 82 | .dout ( ), 83 | .sound ( ), // combined channel output 84 | .A ( ), // linearised channel output 85 | .B ( ), 86 | .C ( ), 87 | 88 | .IOA_in ( 8'd0 ), 89 | .IOA_out ( ), 90 | 91 | .IOB_in ( 8'd0 ), 92 | .IOB_out ( ) 93 | ); 94 | 95 | ay_model u_model 96 | ( 97 | // clock & reset 98 | .clk ( clk ), // Simple clock, AY outputs sound at clk/8 rate. 99 | // For example: at 1.75 MHz clock, sound rate will be 218.75 kHz 100 | ._rst ( rstn ), // Negative asynchronous reset. When _rst=0, chip is under reset. 101 | // The reset will set all AY registers to zero, 102 | // initialize phases of tone and noise generators, 103 | // and initialize the phase of internal clk->clk/8 divider. 104 | // bus & control 105 | .da ( da ), // 8 bit I/O bus 106 | // 107 | .bdir ( bdir ), // Asynchronous bus control signals. The AY captures cmdmem for the internal registers from 'da' bus 108 | .bc2 ( 1'b1 ), // by driving enables on internal latches asynchronously by these signals. 109 | .bc1 ( bc1 ), // Short help on using those signals: 110 | // 111 | // {bdir, bc2, bc1} | bus operation 112 | // -----------------+--------------- 113 | // either of | Select register (number is da[3:0]) for subsequent read or write. 114 | // 0 0 1 | Selection only succeedes when da[7:4]==0, 115 | // 1 0 0 | a8=1 and _a9=0, otherwise AY gets 'unselected', 116 | // 1 1 1 | i.e. it won't react on subsequent reads or writes. 117 | // -----------------+--------------- 118 | // 1 1 0 | write the contents of the 'da' bus into the previously selected AY register 119 | // -----------------+--------------- 120 | // 0 1 1 | read contents of the previously selected AY register to the 'da' bus 121 | // -----------------+--------------- 122 | // any other values | ignore anything on the bus and do not change selected register (idle state) 123 | 124 | .a8 ( 1'b1 ), // additional selection signals, see above 125 | ._a9 ( 1'b0 ), // 126 | 127 | // gpio 128 | .ioa ( ioa ), // bidirectional GPIO pins. 129 | .iob ( iob ), // Unlike it is in real AY, there are no pullups on these pins. 130 | // If you need some, try using 'tri1' instead of 'wire' 131 | // for the signals that connect here. 132 | 133 | // test pins 134 | .test1 ( ), // outputs the frequency that drives envelope state machine, 135 | // its frequency is Fclk/(16*envelope_period). 136 | 137 | .test2 ( 1'b0 ), // put here 1'b0 for normal work. Otherwise 138 | // AY won't do any register reads or writes, while 139 | // the register selections will still work. 140 | 141 | // sound outputs (see comments above) 142 | .ch_a ( ), // Logical sound levels, from 0 to 15. 143 | .ch_b ( ), // You need an additional table lookup if you want real 144 | .ch_c ( ) // sound levels. 145 | // Because AY is an asynchronous design and because here we 146 | // emulate the delays of internal latches where it is necessary, 147 | // there are glitches on these pins. 148 | ); 149 | 150 | initial begin 151 | $shm_open("test.shm"); 152 | $shm_probe(test,"AS"); 153 | $dumpon; 154 | #(10*16*256*256*128) 155 | $display("WARNING: simulation too long"); 156 | $finish; 157 | end 158 | 159 | endmodule -------------------------------------------------------------------------------- /ver/comp/test_cmd: -------------------------------------------------------------------------------- 1 | period a,0 2 | period b,1 3 | period c,0xFFF 4 | period no,0 5 | vol a, 1 6 | vol b, 2 7 | vol c, 4 8 | # volume sweep 9 | wait 255 10 | vol a, 2 11 | wait 255 12 | vol a, 4 13 | wait 255 14 | vol a, 8 15 | wait 255 16 | vol a, 0xa 17 | wait 255 18 | vol a, 0xd 19 | wait 255 20 | vol a, 0xf 21 | wait 255 22 | # EG test 23 | vol a,0x10 24 | shape 0x0 25 | period env,0x80 26 | wait 255 27 | wait 255 28 | period no,7 29 | wait 255 30 | period no,1f 31 | wait 255 32 | shape 0x0 33 | wait 255 34 | wait 255 35 | wait 255 36 | wait 255 37 | shape 0x1 38 | wait 255 39 | wait 255 40 | wait 255 41 | wait 255 42 | shape 0x2 43 | wait 255 44 | wait 255 45 | wait 255 46 | wait 255 47 | shape 0x3 48 | wait 255 49 | wait 255 50 | wait 255 51 | wait 255 52 | shape 0x4 53 | wait 255 54 | wait 255 55 | wait 255 56 | wait 255 57 | shape 0x5 58 | wait 255 59 | wait 255 60 | wait 255 61 | wait 255 62 | shape 0x6 63 | wait 255 64 | wait 255 65 | wait 255 66 | wait 255 67 | shape 0x7 68 | wait 255 69 | wait 255 70 | wait 255 71 | wait 255 72 | shape 0x8 73 | wait 255 74 | wait 255 75 | wait 255 76 | wait 255 77 | shape 0x9 78 | wait 255 79 | wait 255 80 | wait 255 81 | wait 255 82 | shape 0xa 83 | wait 255 84 | wait 255 85 | wait 255 86 | wait 255 87 | shape 0xb 88 | wait 255 89 | wait 255 90 | wait 255 91 | wait 255 92 | shape 0xc 93 | wait 255 94 | wait 255 95 | wait 255 96 | wait 255 97 | shape 0xd 98 | wait 255 99 | wait 255 100 | wait 255 101 | wait 255 102 | shape 0xe 103 | wait 255 104 | wait 255 105 | wait 255 106 | wait 255 107 | shape 0xf 108 | wait 255 109 | wait 255 110 | wait 255 111 | wait 255 112 | finish -------------------------------------------------------------------------------- /ver/dcrm/go.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | 4 | if which ncverilog; then 5 | ncverilog test.v ../../hdl/filter/jt49_{dcrm,mave,dly}.v \ 6 | +define+NCVERILOG +access+r +define+SIMULATION 7 | else 8 | iverilog test.v ../../hdl/filter/jt49_dcrm2.v \ 9 | -DSIMULATION -o sim && ./sim -lxt 10 | fi 11 | -------------------------------------------------------------------------------- /ver/dcrm/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module test; 4 | 5 | reg clk, rst; 6 | 7 | initial begin 8 | clk = 1'b0; 9 | forever clk = #12500 ~clk; 10 | end 11 | 12 | integer simcnt; 13 | 14 | initial begin 15 | rst = 1'b1; 16 | #30000 rst=1'b0; 17 | $display("Reset over: simulation starts"); 18 | for( simcnt=0; simcnt<1000; simcnt=simcnt+1) 19 | #1000_000; 20 | $finish; 21 | end 22 | 23 | wire signed [7:0] dout; 24 | 25 | reg [15:0] cnt; 26 | wire [7:0] din; 27 | 28 | always @(posedge clk) 29 | if( rst ) begin 30 | cnt <= 0; 31 | end else begin 32 | cnt <= cnt + 1; 33 | end 34 | 35 | assign din = cnt[10:5] + cnt[3:0]; 36 | // assign din = cnt[7:0]; 37 | 38 | jt49_dcrm2 UUT( 39 | .clk ( clk ), 40 | .cen ( 1'b1 ), 41 | .rst ( rst ), 42 | .din ( din ), 43 | .dout ( dout ) 44 | ); 45 | 46 | `ifndef NCVERILOG 47 | initial begin 48 | $display("DUMP enabled"); 49 | $dumpfile("test.lxt"); 50 | $dumpvars; 51 | $dumpon; 52 | end 53 | `else 54 | initial begin 55 | $display("NC Verilog: will dump all signals"); 56 | $shm_open("test.shm"); 57 | $shm_probe(UUT,"AS"); 58 | end 59 | `endif 60 | 61 | endmodule -------------------------------------------------------------------------------- /ver/eg/go: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog test.v ../../hdl/jt49_eg.v -o sim && ./sim -lxt 4 | -------------------------------------------------------------------------------- /ver/eg/test.v: -------------------------------------------------------------------------------- 1 | module test; 2 | 3 | reg clk, cen=1'b1, rst_n, restart; 4 | wire [4:0] env; 5 | reg [3:0]ctrl; 6 | 7 | initial begin 8 | clk = 1'b0; 9 | forever clk = #5 ~clk; 10 | end // initial 11 | 12 | initial begin 13 | rst_n = 1'b0; 14 | #50 15 | rst_n = 1'b1; 16 | end // initial 17 | 18 | reg [7:0] aux; 19 | 20 | always @(posedge clk ) begin 21 | if(~rst_n) begin 22 | {ctrl,aux} <= 12'd0; 23 | restart <= 1'b0; 24 | end else begin 25 | {ctrl,aux} <= {ctrl,aux} + 12'd1; 26 | restart <= aux==8'd0; 27 | end 28 | end 29 | 30 | jt49_eg uut( 31 | .clk ( clk ), 32 | .cen ( cen ), 33 | .rst_n ( rst_n ), 34 | .restart ( restart ), 35 | .ctrl ( ctrl ), 36 | .env ( env ) 37 | ); 38 | 39 | initial begin 40 | $dumpfile("test.lxt"); 41 | $dumpvars; 42 | $dumpon; 43 | #(10*16*256) $finish; 44 | end 45 | 46 | endmodule // test -------------------------------------------------------------------------------- /ver/model/sim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog *.v ../../hdl/*.v ../../doc/ay_model.v -o sim && ./sim -lxt 4 | rm -f sim 5 | -------------------------------------------------------------------------------- /ver/model/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module test; 4 | 5 | reg clk, rst_n; 6 | wire wr_n, eof; 7 | wire [3:0] addr; 8 | wire [7:0] din; 9 | 10 | initial begin 11 | $dumpfile("test.lxt"); 12 | $dumpvars; 13 | $dumpon; 14 | #10000000000 $finish; 15 | end 16 | 17 | initial begin 18 | clk=0; 19 | rst_n=0; 20 | #300 rst_n=1; 21 | forever #(1270/4) clk = ~clk; 22 | end 23 | 24 | always @(posedge clk) begin 25 | if( eof ) $finish; 26 | end 27 | 28 | vcd_tnzso16 stim( 29 | .clk ( clk ), 30 | .addr ( addr ), 31 | .wr_n ( wr_n ), 32 | .din ( din ), 33 | .eof ( eof ) 34 | ); 35 | 36 | jt49 uut( 37 | .rst_n ( rst_n ), 38 | .clk ( clk ), 39 | .clk_en ( 1'b1 ), 40 | .addr ( addr ), 41 | .cs_n ( 1'b0 ), 42 | .wr_n ( wr_n ), 43 | .din ( din ), 44 | .sel ( 1'b0 ), 45 | .dout ( ), 46 | .sound ( ), 47 | .A ( ), 48 | .B ( ), 49 | .C ( ), 50 | .sample ( ), 51 | .IOA_in ( 8'd0 ), 52 | .IOA_out ( ), 53 | .IOA_oe ( ), 54 | .IOB_in ( 8'd0 ), 55 | .IOB_out ( ), 56 | .IOB_oe ( ) 57 | ); 58 | 59 | wire [7:0] dmux = wr_n ? {4'd0, addr } : din; 60 | 61 | // {bdir, bc2, bc1} | bus operation 62 | // -----------------+--------------- 63 | // either of | Select register (number is da[3:0]) for subsequent read or write. 64 | // 0 0 1 | Selection only succeedes when da[7:4]==0, 65 | // 1 0 0 | a8=1 and _a9=0, otherwise AY gets 'unselected', 66 | // 1 1 1 | i.e. it won't react on subsequent reads or writes. 67 | // -----------------+--------------- 68 | // 1 1 0 | write the contents of the 'da' bus into the previously selected AY register 69 | // -----------------+--------------- 70 | // 0 1 1 | read contents of the previously selected AY register to the 'da' bus 71 | // -----------------+--------------- 72 | // any other values | ignore anything on the bus and do not change selected register (idle state) 73 | ay_model model( 74 | .clk ( clk ), 75 | ._rst ( rst_n ), 76 | .da ( dmux ), 77 | .bdir ( ~wr_n ), 78 | .bc2 ( ~wr_n ), 79 | .bc1 ( wr_n ), 80 | .a8 ( 1'b1 ), 81 | ._a9 ( 1'b0 ), 82 | 83 | .ioa ( ), 84 | .iob ( ), 85 | .test1 ( ), 86 | .test2 ( ), 87 | .ch_a ( ), 88 | .ch_b ( ), 89 | .ch_c ( ) 90 | ); 91 | 92 | endmodule -------------------------------------------------------------------------------- /ver/model/tnzso16.v: -------------------------------------------------------------------------------- 1 | module vcd_tnzso16( 2 | input clk, 3 | output wr_n, 4 | output [7:0] din, 5 | output [3:0] addr, 6 | output reg eof=0 7 | ); 8 | reg [77-1:0] data[0:819-1]; 9 | wire [63:0] vcd_time; 10 | integer idx=0; 11 | 12 | initial $readmemb("tnzso16.bin",data); 13 | assign {vcd_time,wr_n,din,addr} = data[idx]; 14 | 15 | always @(posedge clk) begin 16 | if( !eof ) begin 17 | if( $time > vcd_time ) idx <= idx+1; 18 | if( idx==819-1 ) begin 19 | eof <= 1; 20 | $display("tnzso16 data completely parsed"); 21 | end 22 | end 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /ver/model/tnzso16.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Mon Jan 22 07:03:46 2024 3 | $end 4 | $version 5 | GTKWave Analyzer v3.3.103 (w)1999-2019 BSI 6 | $end 7 | $timescale 8 | 1ps 9 | $end 10 | $scope module TOP $end 11 | $scope module game_test $end 12 | $scope module u_game $end 13 | $scope module u_game $end 14 | $scope module u_sound $end 15 | $scope module u_2203 $end 16 | $scope module u_jt12 $end 17 | $scope module gen_ssg $end 18 | $scope module u_psg $end 19 | $var wire 4 " addr[3:0] $end 20 | $var wire 1 # wr_n $end 21 | $var wire 8 $ din[7:0] $end 22 | $upscope $end 23 | $upscope $end 24 | $upscope $end 25 | $upscope $end 26 | $upscope $end 27 | $upscope $end 28 | $upscope $end 29 | $upscope $end 30 | $upscope $end 31 | $enddefinitions $end 32 | #5052547564176 33 | $dumpvars 34 | 1# 35 | b0 $ 36 | b1111 " 37 | $end 38 | #5068563705744 39 | b1110 " 40 | #5068571705232 41 | b1111 " 42 | #5085464624016 43 | b1110 " 44 | #5085472623504 45 | b1111 " 46 | #5102353543056 47 | b1110 " 48 | #5102361542544 49 | b1111 " 50 | #5119247795088 51 | b1110 " 52 | #5119255794576 53 | b1111 " 54 | #5136146546832 55 | b1110 " 56 | #5136154546320 57 | b1111 " 58 | #5153039632272 59 | b1110 " 60 | #5153047798416 61 | b1111 " 62 | #5169938217360 63 | b1110 " 64 | #5169946279344 65 | b1111 " 66 | #5186830469520 67 | b1110 " 68 | #5186838469008 69 | b1111 " 70 | #5189527963536 71 | b0 " 72 | #5189537462928 73 | 0# 74 | b110110 $ 75 | #5189537942064 76 | 1# 77 | #5189541462672 78 | b1 " 79 | #5189550962064 80 | 0# 81 | b0 $ 82 | #5189552024496 83 | 1# 84 | #5189561961360 85 | b10 " 86 | #5189571627408 87 | 0# 88 | b110100 $ 89 | #5189571939888 90 | 1# 91 | #5189575627152 92 | b11 " 93 | #5189585126544 94 | 0# 95 | b0 $ 96 | #5189586084816 97 | 1# 98 | #5189596125840 99 | b100 " 100 | #5189605625232 101 | 0# 102 | b111000 $ 103 | #5189605937712 104 | 1# 105 | #5189609624976 106 | b101 " 107 | #5189619124368 108 | 0# 109 | b0 $ 110 | #5189620082640 111 | 1# 112 | #5189631456912 113 | b110 " 114 | #5189640956304 115 | 0# 116 | #5189641935408 117 | 1# 118 | #5189650789008 119 | b111 " 120 | #5189660288400 121 | 0# 122 | b111000 $ 123 | #5189661934128 124 | 1# 125 | #5189670121104 126 | b1000 " 127 | #5189679620496 128 | 0# 129 | b10000 $ 130 | #5189679932976 131 | 1# 132 | #5189689453200 133 | b1001 " 134 | #5189698952592 135 | 0# 136 | #5189699931696 137 | 1# 138 | #5189708785296 139 | b1010 " 140 | #5189718284688 141 | 0# 142 | #5189719930416 143 | 1# 144 | #5189742116496 145 | b1011 " 146 | #5189751615888 147 | 0# 148 | b0 $ 149 | #5189751928368 150 | 1# 151 | #5189755615632 152 | b1100 " 153 | #5189765115024 154 | 0# 155 | b11000 $ 156 | #5189766073296 157 | 1# 158 | #5189772947856 159 | b1101 " 160 | #5189782447248 161 | 0# 162 | b1001 $ 163 | #5189783926320 164 | 1# 165 | #5203726888080 166 | b1110 " 167 | #5203734887568 168 | b1111 " 169 | #5206435048080 170 | b10 " 171 | #5206444547472 172 | 0# 173 | b101010 $ 174 | #5206444859952 175 | 1# 176 | #5206448547216 177 | b11 " 178 | #5206458046608 179 | 0# 180 | b0 $ 181 | #5206459004880 182 | 1# 183 | #5206469045904 184 | b100 " 185 | #5206478545296 186 | 0# 187 | b101110 $ 188 | #5206478857776 189 | 1# 190 | #5206482545040 191 | b101 " 192 | #5206492044432 193 | 0# 194 | b0 $ 195 | #5206493002704 196 | 1# 197 | #5220625973136 198 | b1110 " 199 | #5220633972624 200 | b1111 " 201 | #5223334966416 202 | b10 " 203 | #5223344465808 204 | 0# 205 | b110100 $ 206 | #5223345778224 207 | 1# 208 | #5223348465552 209 | b11 " 210 | #5223357964944 211 | 0# 212 | b0 $ 213 | #5223359777328 214 | 1# 215 | #5223369130896 216 | b100 " 217 | #5223378630288 218 | 0# 219 | b111000 $ 220 | #5223379776048 221 | 1# 222 | #5223382630032 223 | b101 " 224 | #5223392129424 225 | 0# 226 | b0 $ 227 | #5223393775152 228 | 1# 229 | #5237518558608 230 | b1110 " 231 | #5237526558096 232 | b1111 " 233 | #5240211719568 234 | b0 " 235 | #5240221218960 236 | 0# 237 | b101100 $ 238 | #5240222698032 239 | 1# 240 | #5240225218704 241 | b1 " 242 | #5240234718096 243 | 0# 244 | b0 $ 245 | #5240236697136 246 | 1# 247 | #5240245717392 248 | b10 " 249 | #5240255216784 250 | 0# 251 | b101101 $ 252 | #5240256695856 253 | 1# 254 | #5240259216528 255 | b11 " 256 | #5240268715920 257 | 0# 258 | b0 $ 259 | #5240270694960 260 | 1# 261 | #5240279715216 262 | b100 " 263 | #5240289214608 264 | 0# 265 | b110001 $ 266 | #5240290693680 267 | 1# 268 | #5240293214352 269 | b101 " 270 | #5240302713744 271 | 0# 272 | b0 $ 273 | #5240304692784 274 | 1# 275 | #5254405977744 276 | b1110 " 277 | #5254413977232 278 | b1111 " 279 | #5257115470992 280 | b10 " 281 | #5257124970384 282 | 0# 283 | b110100 $ 284 | #5257125616176 285 | 1# 286 | #5257128970128 287 | b11 " 288 | #5257138469520 289 | 0# 290 | b0 $ 291 | #5257139615280 292 | 1# 293 | #5257149468816 294 | b100 " 295 | #5257158968208 296 | 0# 297 | b111000 $ 298 | #5257159614000 299 | 1# 300 | #5257162967952 301 | b101 " 302 | #5257172634000 303 | 0# 304 | b0 $ 305 | #5257173696432 306 | 1# 307 | #5271306562704 308 | b1110 " 309 | #5271314562192 310 | b1111 " 311 | #5274011389584 312 | b10 " 313 | #5274020888976 314 | 0# 315 | b101010 $ 316 | #5274022534704 317 | 1# 318 | #5274024888720 319 | b11 " 320 | #5274034388112 321 | 0# 322 | b0 $ 323 | #5274034533936 324 | 1# 325 | #5274045387408 326 | b100 " 327 | #5274054886800 328 | 0# 329 | b101110 $ 330 | #5274056532528 331 | 1# 332 | #5274058886544 333 | b101 " 334 | #5274068385936 335 | 0# 336 | b0 $ 337 | #5274068531760 338 | 1# 339 | #5288194481808 340 | b1110 " 341 | #5288202647952 342 | b1111 " 343 | #5290887476112 344 | b0 " 345 | #5290896975504 346 | 0# 347 | b110110 $ 348 | #5290897454640 349 | 1# 350 | #5290900975248 351 | b1 " 352 | #5290910474640 353 | 0# 354 | b0 $ 355 | #5290911537072 356 | 1# 357 | #5290921473936 358 | b10 " 359 | #5290930973328 360 | 0# 361 | b110100 $ 362 | #5290931452464 363 | 1# 364 | #5290934973072 365 | b11 " 366 | #5290944472464 367 | 0# 368 | b0 $ 369 | #5290945534896 370 | 1# 371 | #5290955471760 372 | b100 " 373 | #5290965137808 374 | 0# 375 | b111000 $ 376 | #5290965450288 377 | 1# 378 | #5290969137552 379 | b101 " 380 | #5290978636944 381 | 0# 382 | b0 $ 383 | #5290979595216 384 | 1# 385 | #5305088067216 386 | b1110 " 387 | #5305096066704 388 | b1111 " 389 | #5307798227088 390 | b10 " 391 | #5307807726480 392 | 0# 393 | b101101 $ 394 | #5307808372272 395 | 1# 396 | #5307811726224 397 | b11 " 398 | #5307821225616 399 | 0# 400 | b0 $ 401 | #5307822371376 402 | 1# 403 | #5307832224912 404 | b100 " 405 | #5307841724304 406 | 0# 407 | b110001 $ 408 | #5307842370096 409 | 1# 410 | #5307845724048 411 | b101 " 412 | #5307855390096 413 | 0# 414 | b0 $ 415 | #5307856452528 416 | 1# 417 | #5321993485200 418 | b1110 " 419 | #5322001484688 420 | b1111 " 421 | #5324698812048 422 | b10 " 423 | #5324708311440 424 | 0# 425 | b110100 $ 426 | #5324709373872 427 | 1# 428 | #5324712311184 429 | b11 " 430 | #5324721810576 431 | 0# 432 | b0 $ 433 | #5324723289648 434 | 1# 435 | #5324732809872 436 | b100 " 437 | #5324742309264 438 | 0# 439 | b111000 $ 440 | #5324743371696 441 | 1# 442 | #5324746309008 443 | b101 " 444 | #5324755808400 445 | 0# 446 | b0 $ 447 | #5324757287472 448 | 1# 449 | #5338888237200 450 | b1110 " 451 | #5338896236688 452 | b1111 " 453 | #5341585397904 454 | b0 " 455 | #5341594897296 456 | 0# 457 | b101111 $ 458 | #5341596209712 459 | 1# 460 | #5341598897040 461 | b1 " 462 | #5341608563088 463 | 0# 464 | b0 $ 465 | #5341610208816 466 | 1# 467 | #5341619562384 468 | b10 " 469 | #5341629061776 470 | 0# 471 | b101010 $ 472 | #5341630207536 473 | 1# 474 | #5341633061520 475 | b11 " 476 | #5341642560912 477 | 0# 478 | b0 $ 479 | #5341644206640 480 | 1# 481 | #5341653560208 482 | b100 " 483 | #5341663059600 484 | 0# 485 | b101110 $ 486 | #5341664205360 487 | 1# 488 | #5341667059344 489 | b101 " 490 | #5341676558736 491 | 0# 492 | b0 $ 493 | #5341678204464 494 | 1# 495 | #5355780489360 496 | b1110 " 497 | #5355788488848 498 | b1111 " 499 | #5358485316240 500 | b10 " 501 | #5358494815632 502 | 0# 503 | b110100 $ 504 | #5358495128112 505 | 1# 506 | #5358498815376 507 | b11 " 508 | #5358508314768 509 | 0# 510 | b0 $ 511 | #5358509273040 512 | 1# 513 | #5358519314064 514 | b100 " 515 | #5358528813456 516 | 0# 517 | b111000 $ 518 | #5358529125936 519 | 1# 520 | #5358532813200 521 | b101 " 522 | #5358542312592 523 | 0# 524 | b0 $ 525 | #5358543270864 526 | 1# 527 | #5372676741264 528 | b1110 " 529 | #5372684740752 530 | b1111 " 531 | #5375381234832 532 | b10 " 533 | #5375390734224 534 | 0# 535 | b101101 $ 536 | #5375392046640 537 | 1# 538 | #5375394733968 539 | b11 " 540 | #5375404233360 541 | 0# 542 | b0 $ 543 | #5375406045744 544 | 1# 545 | #5375415399312 546 | b100 " 547 | #5375424898704 548 | 0# 549 | b110001 $ 550 | #5375426044464 551 | 1# 552 | #5375428898448 553 | b101 " 554 | #5375438397840 555 | 0# 556 | b0 $ 557 | #5375440043568 558 | 1# 559 | #5389569160080 560 | b1110 " 561 | #5389577159568 562 | b1111 " 563 | #5392262654352 564 | b0 " 565 | #5392272153744 566 | 0# 567 | b110110 $ 568 | #5392273112016 569 | 1# 570 | #5392276153488 571 | b1 " 572 | #5392285652880 573 | 0# 574 | b0 $ 575 | #5392286965296 576 | 1# 577 | #5392296652176 578 | b10 " 579 | #5392306151568 580 | 0# 581 | b110100 $ 582 | #5392307109840 583 | 1# 584 | #5392310151312 585 | b11 " 586 | #5392319650704 587 | 0# 588 | b0 $ 589 | #5392320963120 590 | 1# 591 | #5392330650000 592 | b100 " 593 | #5392340149392 594 | 0# 595 | b111000 $ 596 | #5392341107664 597 | 1# 598 | #5392344149136 599 | b101 " 600 | #5392353648528 601 | 0# 602 | b0 $ 603 | #5392354960944 604 | 1# 605 | #5406458245776 606 | b1110 " 607 | #5406466245264 608 | b1111 " 609 | #5409164239248 610 | b10 " 611 | #5409173738640 612 | 0# 613 | b101010 $ 614 | #5409173884464 615 | 1# 616 | #5409177738384 617 | b11 " 618 | #5409187237776 619 | 0# 620 | b0 $ 621 | #5409187883568 622 | 1# 623 | #5409198237072 624 | b100 " 625 | #5409207736464 626 | 0# 627 | b101110 $ 628 | #5409207882288 629 | 1# 630 | #5409211736208 631 | b101 " 632 | #5409221235600 633 | 0# 634 | b0 $ 635 | #5409221881392 636 | 1# 637 | #5423360163984 638 | b1110 " 639 | #5423368163472 640 | b1111 " 641 | #5426067657360 642 | b10 " 643 | #5426077156752 644 | 0# 645 | b110100 $ 646 | #5426078802480 647 | 1# 648 | #5426081156496 649 | b11 " 650 | #5426090655888 651 | 0# 652 | b0 $ 653 | #5426090801712 654 | 1# 655 | #5426101655184 656 | b100 " 657 | #5426111154576 658 | 0# 659 | b111000 $ 660 | #5426112800304 661 | 1# 662 | #5426115154320 663 | b101 " 664 | #5426124653712 665 | 0# 666 | b0 $ 667 | #5426124799536 668 | 1# 669 | #5440254416016 670 | b1110 " 671 | #5440262415504 672 | b1111 " 673 | #5442950910096 674 | b0 " 675 | #5442960409488 676 | 0# 677 | b101100 $ 678 | #5442961721904 679 | 1# 680 | #5442964409232 681 | b1 " 682 | #5442974075280 683 | 0# 684 | b0 $ 685 | #5442975721008 686 | 1# 687 | #5442985074576 688 | b10 " 689 | #5442994573968 690 | 0# 691 | b101101 $ 692 | #5442995719728 693 | 1# 694 | #5442998573712 695 | b11 " 696 | #5443008073104 697 | 0# 698 | b0 $ 699 | #5443009718832 700 | 1# 701 | #5443019072400 702 | b100 " 703 | #5443028571792 704 | 0# 705 | b110001 $ 706 | #5443029717552 707 | 1# 708 | #5443032571536 709 | b101 " 710 | #5443042070928 711 | 0# 712 | b0 $ 713 | #5443043716656 714 | 1# 715 | #5457148001424 716 | b1110 " 717 | #5457156000912 718 | b1111 " 719 | #5459855161488 720 | b10 " 721 | #5459864660880 722 | 0# 723 | b110100 $ 724 | #5459866639920 725 | 1# 726 | #5459868660624 727 | b11 " 728 | #5459878160016 729 | 0# 730 | b0 $ 731 | #5459878639152 732 | 1# 733 | #5459889325968 734 | b100 " 735 | #5459898825360 736 | 0# 737 | b111000 $ 738 | #5459900637744 739 | 1# 740 | #5459902825104 741 | b101 " 742 | #5459912324496 743 | 0# 744 | b0 $ 745 | #5459912636976 746 | 1# 747 | #5474042920080 748 | b1110 " 749 | #5474050919568 750 | b1111 " 751 | #5476746413712 752 | b10 " 753 | #5476755913104 754 | 0# 755 | b101010 $ 756 | #5476757558832 757 | 1# 758 | #5476759912848 759 | b11 " 760 | #5476769412240 761 | 0# 762 | b0 $ 763 | #5476769558064 764 | 1# 765 | #5476780411536 766 | b100 " 767 | #5476789910928 768 | 0# 769 | b101110 $ 770 | #5476791556656 771 | 1# 772 | #5476793910672 773 | b101 " 774 | #5476803410064 775 | 0# 776 | b0 $ 777 | #5476803555888 778 | 1# 779 | #5490937838736 780 | b1110 " 781 | #5490945838224 782 | b1111 " 783 | #5493627499920 784 | b0 " 785 | #5493636999312 786 | 0# 787 | b110110 $ 788 | #5493638478384 789 | 1# 790 | #5493640999056 791 | b1 " 792 | #5493650498448 793 | 0# 794 | b0 $ 795 | #5493652477488 796 | 1# 797 | #5493661497744 798 | b10 " 799 | #5493670997136 800 | 0# 801 | b110100 $ 802 | #5493672476208 803 | 1# 804 | #5493674996880 805 | b11 " 806 | #5493684496272 807 | 0# 808 | b0 $ 809 | #5493686475312 810 | 1# 811 | #5493695495568 812 | b100 " 813 | #5493704994960 814 | 0# 815 | b111000 $ 816 | #5493706474032 817 | 1# 818 | #5493708994704 819 | b101 " 820 | #5493718494096 821 | 0# 822 | b0 $ 823 | #5493720473136 824 | 1# 825 | #5507832924048 826 | b1110 " 827 | #5507840923536 828 | b1111 " 829 | #5510537917584 830 | b10 " 831 | #5510547416976 832 | 0# 833 | b101101 $ 834 | #5510549396016 835 | 1# 836 | #5510551416720 837 | b11 " 838 | #5510560916112 839 | 0# 840 | b0 $ 841 | #5510561395248 842 | 1# 843 | #5510572082064 844 | b100 " 845 | #5510581581456 846 | 0# 847 | b110001 $ 848 | #5510583393840 849 | 1# 850 | #5510585581200 851 | b101 " 852 | #5510595080592 853 | 0# 854 | b0 $ 855 | #5510595393072 856 | 1# 857 | #5524726509456 858 | b1110 " 859 | #5524734508944 860 | b1111 " 861 | #5527435169424 862 | b10 " 863 | #5527444668816 864 | 0# 865 | b110100 $ 866 | #5527446314544 867 | 1# 868 | #5527448668560 869 | b11 " 870 | #5527458167952 871 | 0# 872 | b0 $ 873 | #5527458313776 874 | 1# 875 | #5527469167248 876 | b100 " 877 | #5527478666640 878 | 0# 879 | b111000 $ 880 | #5527480312368 881 | 1# 882 | #5527482666384 883 | b101 " 884 | #5527492165776 885 | 0# 886 | b0 $ 887 | #5527492311600 888 | 1# 889 | #5541618094992 890 | b1110 " 891 | #5541626094480 892 | b1111 " 893 | #5544315089040 894 | b0 " 895 | #5544324588432 896 | 0# 897 | b101111 $ 898 | #5544325234224 899 | 1# 900 | #5544328588176 901 | b1 " 902 | #5544338254224 903 | 0# 904 | b0 $ 905 | #5544339316656 906 | 1# 907 | #5544349253520 908 | b10 " 909 | #5544358752912 910 | 0# 911 | b101010 $ 912 | #5544359232048 913 | 1# 914 | #5544362752656 915 | b11 " 916 | #5544372252048 917 | 0# 918 | b0 $ 919 | #5544373314480 920 | 1# 921 | #5544383251344 922 | b100 " 923 | #5544392750736 924 | 0# 925 | b101110 $ 926 | #5544393229872 927 | 1# 928 | #5544396750480 929 | b101 " 930 | #5544406249872 931 | 0# 932 | b0 $ 933 | #5544407312304 934 | 1# 935 | #5558523908784 936 | b1110 " 937 | #5558531845776 938 | b1111 " 939 | #5561224673424 940 | b10 " 941 | #5561234172816 942 | 0# 943 | b110100 $ 944 | #5561236151856 945 | 1# 946 | #5561238172560 947 | b11 " 948 | #5561247671952 949 | 0# 950 | b0 $ 951 | #5561248151088 952 | 1# 953 | #5561258837904 954 | b100 " 955 | #5561268337296 956 | 0# 957 | b111000 $ 958 | #5561270149680 959 | 1# 960 | #5561272337040 961 | b101 " 962 | #5561281836432 963 | 0# 964 | b0 $ 965 | #5561282148912 966 | 1# 967 | #5575413598608 968 | b1110 " 969 | #5575421598096 970 | b1111 " 971 | #5578121591952 972 | b10 " 973 | #5578131091344 974 | 0# 975 | b101101 $ 976 | #5578133070384 977 | 1# 978 | #5578135091088 979 | b11 " 980 | #5578144590480 981 | 0# 982 | b0 $ 983 | #5578145069616 984 | 1# 985 | #5578155756432 986 | b100 " 987 | #5578165255824 988 | 0# 989 | b110001 $ 990 | #5578167068208 991 | 1# 992 | #5578169255568 993 | b101 " 994 | #5578178754960 995 | 0# 996 | b0 $ 997 | #5578179067440 998 | 1# 999 | #5592306184080 1000 | b1110 " 1001 | #5592314183568 1002 | b1111 " 1003 | #5594999678352 1004 | b0 " 1005 | #5595009177744 1006 | 0# 1007 | b110110 $ 1008 | #5595010136016 1009 | 1# 1010 | #5595013177488 1011 | b1 " 1012 | #5595022676880 1013 | 0# 1014 | b0 $ 1015 | #5595023989296 1016 | 1# 1017 | #5595033676176 1018 | b10 " 1019 | #5595043175568 1020 | 0# 1021 | b110100 $ 1022 | #5595044133840 1023 | 1# 1024 | #5595047175312 1025 | b11 " 1026 | #5595056674704 1027 | 0# 1028 | b0 $ 1029 | #5595057987120 1030 | 1# 1031 | #5595067674000 1032 | b100 " 1033 | #5595077173392 1034 | 0# 1035 | b111000 $ 1036 | #5595078131664 1037 | 1# 1038 | #5595081173136 1039 | b101 " 1040 | #5595090672528 1041 | 0# 1042 | b0 $ 1043 | #5595091984944 1044 | 1# 1045 | #5609205935760 1046 | b1110 " 1047 | #5609213935248 1048 | b1111 " 1049 | #5611913929104 1050 | b10 " 1051 | #5611923428496 1052 | 0# 1053 | b101010 $ 1054 | #5611924907568 1055 | 1# 1056 | #5611927428240 1057 | b11 " 1058 | #5611936927632 1059 | 0# 1060 | b0 $ 1061 | #5611938906672 1062 | 1# 1063 | #5611947926928 1064 | b100 " 1065 | #5611957426320 1066 | 0# 1067 | b101110 $ 1068 | #5611958905392 1069 | 1# 1070 | #5611961426064 1071 | b101 " 1072 | #5611970925456 1073 | 0# 1074 | b0 $ 1075 | #5611972904496 1076 | 1# 1077 | #5626097187984 1078 | b1110 " 1079 | #5626105187472 1080 | b1111 " 1081 | #5628805347984 1082 | b10 " 1083 | #5628814847376 1084 | 0# 1085 | b110100 $ 1086 | #5628815993136 1087 | 1# 1088 | #5628818847120 1089 | b11 " 1090 | #5628828346512 1091 | 0# 1092 | b0 $ 1093 | #5628829825584 1094 | 1# 1095 | #5628839345808 1096 | b100 " 1097 | #5628848845200 1098 | 0# 1099 | b111000 $ 1100 | #5628849907632 1101 | 1# 1102 | #5628852844944 1103 | b101 " 1104 | #5628862344336 1105 | 0# 1106 | b0 $ 1107 | #5628863823408 1108 | 1# 1109 | #5642992106640 1110 | b1110 " 1111 | #5643000106128 1112 | b1111 " 1113 | #5645687267472 1114 | b0 " 1115 | #5645696766864 1116 | 0# 1117 | b101100 $ 1118 | #5645698745904 1119 | 1# 1120 | #5645700766608 1121 | b1 " 1122 | #5645710432656 1123 | 0# 1124 | b0 $ 1125 | #5645710745136 1126 | 1# 1127 | #5645721431952 1128 | b10 " 1129 | #5645730931344 1130 | 0# 1131 | b101101 $ 1132 | #5645732743728 1133 | 1# 1134 | #5645734931088 1135 | b11 " 1136 | #5645744430480 1137 | 0# 1138 | b0 $ 1139 | #5645744742960 1140 | 1# 1141 | #5645755429776 1142 | b100 " 1143 | #5645764929168 1144 | 0# 1145 | b110001 $ 1146 | #5645766741552 1147 | 1# 1148 | #5645768928912 1149 | b101 " 1150 | #5645778428304 1151 | 0# 1152 | b0 $ 1153 | #5645778740784 1154 | 1# 1155 | #5659887691920 1156 | b1110 " 1157 | #5659895691408 1158 | b1111 " 1159 | #5662597518480 1160 | b10 " 1161 | #5662607017872 1162 | 0# 1163 | b110100 $ 1164 | #5662607663664 1165 | 1# 1166 | #5662611017616 1167 | b11 " 1168 | #5662620517008 1169 | 0# 1170 | b0 $ 1171 | #5662621662768 1172 | 1# 1173 | #5662631516304 1174 | b100 " 1175 | #5662641015696 1176 | 0# 1177 | b111000 $ 1178 | #5662641661488 1179 | 1# 1180 | #5662645015440 1181 | b101 " 1182 | #5662654681488 1183 | 0# 1184 | b0 $ 1185 | #5662655743920 1186 | 1# 1187 | #5676785777040 1188 | b1110 " 1189 | #5676793839024 1190 | b1111 " 1191 | #5679491770512 1192 | b10 " 1193 | #5679501269904 1194 | 0# 1195 | b101010 $ 1196 | #5679502582320 1197 | 1# 1198 | #5679505269648 1199 | b11 " 1200 | #5679514769040 1201 | 0# 1202 | b0 $ 1203 | #5679516581424 1204 | 1# 1205 | #5679525934992 1206 | b100 " 1207 | #5679535434384 1208 | 0# 1209 | b101110 $ 1210 | #5679536580144 1211 | 1# 1212 | #5679539434128 1213 | b101 " 1214 | #5679548933520 1215 | 0# 1216 | b0 $ 1217 | #5679550579248 1218 | 1# 1219 | #5693685695376 1220 | b1110 " 1221 | #5693693694864 1222 | b1111 " 1223 | #5696382522768 1224 | b0 " 1225 | #5696392022160 1226 | 0# 1227 | b110110 $ 1228 | #5696393501232 1229 | 1# 1230 | #5696396021904 1231 | b1 " 1232 | #5696405521296 1233 | 0# 1234 | b0 $ 1235 | #5696407500336 1236 | 1# 1237 | #5696416520592 1238 | b10 " 1239 | #5696426019984 1240 | 0# 1241 | b110100 $ 1242 | #5696427499056 1243 | 1# 1244 | #5696430019728 1245 | b11 " 1246 | #5696439519120 1247 | 0# 1248 | b0 $ 1249 | #5696441498160 1250 | 1# 1251 | #5696450518416 1252 | b100 " 1253 | #5696460017808 1254 | 0# 1255 | b111000 $ 1256 | #5696461496880 1257 | 1# 1258 | #5696464017552 1259 | b101 " 1260 | #5696473516944 1261 | 0# 1262 | b0 $ 1263 | #5696475495984 1264 | 1# 1265 | #5710568281488 1266 | b1110 " 1267 | #5710576280976 1268 | b1111 " 1269 | #5713273608336 1270 | b10 " 1271 | #5713283107728 1272 | 0# 1273 | b101101 $ 1274 | #5713284420144 1275 | 1# 1276 | #5713287107472 1277 | b11 " 1278 | #5713296606864 1279 | 0# 1280 | b0 $ 1281 | #5713298419248 1282 | 1# 1283 | #5713307772816 1284 | b100 " 1285 | #5713317272208 1286 | 0# 1287 | b110001 $ 1288 | #5713318417968 1289 | 1# 1290 | #5713321271952 1291 | b101 " 1292 | #5713330771344 1293 | 0# 1294 | b0 $ 1295 | #5713332417072 1296 | 1# 1297 | #5727466866576 1298 | b1110 " 1299 | #5727474866064 1300 | b1111 " 1301 | #5730171526800 1302 | b10 " 1303 | #5730181026192 1304 | 0# 1305 | b110100 $ 1306 | #5730181338672 1307 | 1# 1308 | #5730185025936 1309 | b11 " 1310 | #5730194525328 1311 | 0# 1312 | b0 $ 1313 | #5730195441936 1314 | 1# 1315 | #5730205524624 1316 | b100 " 1317 | #5730215024016 1318 | 0# 1319 | b111000 $ 1320 | #5730215336496 1321 | 1# 1322 | #5730219023760 1323 | b101 " 1324 | #5730228523152 1325 | 0# 1326 | b0 $ 1327 | #5730229481424 1328 | 1# 1329 | #5744361785232 1330 | b1110 " 1331 | #5744369784720 1332 | b1111 " 1333 | #5747052113040 1334 | b0 " 1335 | #5747061612432 1336 | 0# 1337 | b101111 $ 1338 | #5747062258224 1339 | 1# 1340 | #5747065612176 1341 | b1 " 1342 | #5747075278224 1343 | 0# 1344 | b0 $ 1345 | #5747076340656 1346 | 1# 1347 | #5747086277520 1348 | b10 " 1349 | #5747095776912 1350 | 0# 1351 | b101010 $ 1352 | #5747096256048 1353 | 1# 1354 | #5747099776656 1355 | b11 " 1356 | #5747109276048 1357 | 0# 1358 | b0 $ 1359 | #5747110338480 1360 | 1# 1361 | #5747120275344 1362 | b100 " 1363 | #5747129774736 1364 | 0# 1365 | b101110 $ 1366 | #5747130253872 1367 | 1# 1368 | #5747133774480 1369 | b101 " 1370 | #5747143273872 1371 | 0# 1372 | b0 $ 1373 | #5747144419632 1374 | 1# 1375 | #5761251870864 1376 | b1110 " 1377 | #5761259870352 1378 | b1111 " 1379 | #5763960864144 1380 | b10 " 1381 | #5763970363536 1382 | 0# 1383 | b110100 $ 1384 | #5763971321808 1385 | 1# 1386 | #5763974363280 1387 | b11 " 1388 | #5763983862672 1389 | 0# 1390 | b0 $ 1391 | #5763985175088 1392 | 1# 1393 | #5763994861968 1394 | b100 " 1395 | #5764004361360 1396 | 0# 1397 | b111000 $ 1398 | #5764005319632 1399 | 1# 1400 | #5764008361104 1401 | b101 " 1402 | #5764017860496 1403 | 0# 1404 | b0 $ 1405 | #5764019172912 1406 | 1# 1407 | #5778159955344 1408 | b1110 " 1409 | #5778167954832 1410 | b1111 " 1411 | #5780869115280 1412 | b10 " 1413 | #5780878614672 1414 | 0# 1415 | b101101 $ 1416 | #5780880093744 1417 | 1# 1418 | #5780882614416 1419 | b11 " 1420 | #5780892113808 1421 | 0# 1422 | b0 $ 1423 | #5780894092848 1424 | 1# 1425 | #5780903113104 1426 | b100 " 1427 | #5780912612496 1428 | 0# 1429 | b110001 $ 1430 | #5780914091568 1431 | 1# 1432 | #5780916612240 1433 | b101 " 1434 | #5780926111632 1435 | 0# 1436 | b0 $ 1437 | #5780928090672 1438 | 1# 1439 | #5795054540688 1440 | b1110 " 1441 | #5795062602672 1442 | b1111 " 1443 | #5797751368080 1444 | b0 " 1445 | #5797760867472 1446 | 0# 1447 | b110110 $ 1448 | #5797761013296 1449 | 1# 1450 | #5797764867216 1451 | b1 " 1452 | #5797774366608 1453 | 0# 1454 | b0 $ 1455 | #5797775012400 1456 | 1# 1457 | #5797785365904 1458 | b10 " 1459 | #5797794865296 1460 | 0# 1461 | b110100 $ 1462 | #5797795011120 1463 | 1# 1464 | #5797798865040 1465 | b11 " 1466 | #5797808364432 1467 | 0# 1468 | b0 $ 1469 | #5797809010224 1470 | 1# 1471 | #5797819363728 1472 | b100 " 1473 | #5797828863120 1474 | 0# 1475 | b111000 $ 1476 | #5797829008944 1477 | 1# 1478 | #5797832862864 1479 | b101 " 1480 | #5797842362256 1481 | 0# 1482 | b0 $ 1483 | #5797843008048 1484 | 1# 1485 | #5811936626832 1486 | b1110 " 1487 | #5811944626320 1488 | b1111 " 1489 | #5814642120336 1490 | b10 " 1491 | #5814651619728 1492 | 0# 1493 | b101010 $ 1494 | #5814651932208 1495 | 1# 1496 | #5814655619472 1497 | b11 " 1498 | #5814665118864 1499 | 0# 1500 | b0 $ 1501 | #5814666077136 1502 | 1# 1503 | #5814676118160 1504 | b100 " 1505 | #5814685617552 1506 | 0# 1507 | b101110 $ 1508 | #5814685930032 1509 | 1# 1510 | #5814689617296 1511 | b101 " 1512 | #5814699116688 1513 | 0# 1514 | b0 $ 1515 | #5814700074960 1516 | 1# 1517 | #5828839544976 1518 | b1110 " 1519 | #5828847544464 1520 | b1111 " 1521 | #5831547371664 1522 | b10 " 1523 | #5831556871056 1524 | 0# 1525 | b110100 $ 1526 | #5831558850096 1527 | 1# 1528 | #5831560870800 1529 | b11 " 1530 | #5831570370192 1531 | 0# 1532 | b0 $ 1533 | #5831570849328 1534 | 1# 1535 | #5831581369488 1536 | b100 " 1537 | #5831590868880 1538 | 0# 1539 | b111000 $ 1540 | #5831592847920 1541 | 1# 1542 | #5831594868624 1543 | b101 " 1544 | #5831604368016 1545 | 0# 1546 | b0 $ 1547 | #5831604847152 1548 | 1# 1549 | #5845729297296 1550 | b1110 " 1551 | #5845737296784 1552 | b1111 " 1553 | #5848422791568 1554 | b0 " 1555 | #5848432290960 1556 | 0# 1557 | b101100 $ 1558 | #5848433770032 1559 | 1# 1560 | #5848436290704 1561 | b1 " 1562 | #5848445790096 1563 | 0# 1564 | b0 $ 1565 | #5848447769136 1566 | 1# 1567 | #5848456789392 1568 | b10 " 1569 | #5848466288784 1570 | 0# 1571 | b101101 $ 1572 | #5848467767856 1573 | 1# 1574 | #5848470288528 1575 | b11 " 1576 | #5848479787920 1577 | 0# 1578 | b0 $ 1579 | #5848481766960 1580 | 1# 1581 | #5848490787216 1582 | b100 " 1583 | #5848500286608 1584 | 0# 1585 | b110001 $ 1586 | #5848501765680 1587 | 1# 1588 | #5848504286352 1589 | b101 " 1590 | #5848513785744 1591 | 0# 1592 | b0 $ 1593 | #5848515785616 1594 | 1# 1595 | #5862627882384 1596 | b1110 " 1597 | #5862635881872 1598 | b1111 " 1599 | #5865333209232 1600 | b10 " 1601 | #5865342708624 1602 | 0# 1603 | b110100 $ 1604 | #5865344687664 1605 | 1# 1606 | #5865346708368 1607 | b11 " 1608 | #5865356207760 1609 | 0# 1610 | b0 $ 1611 | #5865356686896 1612 | 1# 1613 | #5865367373712 1614 | b100 " 1615 | #5865376873104 1616 | 0# 1617 | b111000 $ 1618 | #5865378685488 1619 | 1# 1620 | #5865380872848 1621 | b101 " 1622 | #5865390372240 1623 | 0# 1624 | b0 $ 1625 | #5865390684720 1626 | 1# 1627 | #5879521801104 1628 | b1110 " 1629 | #5879529967248 1630 | b1111 " 1631 | #5882225461392 1632 | b10 " 1633 | #5882234960784 1634 | 0# 1635 | b101010 $ 1636 | #5882235606576 1637 | 1# 1638 | #5882238960528 1639 | b11 " 1640 | #5882248459920 1641 | 0# 1642 | b0 $ 1643 | #5882249605680 1644 | 1# 1645 | #5882259625872 1646 | b100 " 1647 | #5882269125264 1648 | 0# 1649 | b101110 $ 1650 | #5882269604400 1651 | 1# 1652 | #5882273125008 1653 | b101 " 1654 | #5882282624400 1655 | 0# 1656 | b0 $ 1657 | #5882283686832 1658 | 1# 1659 | #5896420886160 1660 | b1110 " 1661 | #5896428885648 1662 | b1111 " 1663 | #5899114213776 1664 | b0 " 1665 | #5899123713168 1666 | 0# 1667 | #5899124671440 1668 | 1# 1669 | #5899127712912 1670 | b1 " 1671 | #5899137212304 1672 | 0# 1673 | #5899138524720 1674 | 1# 1675 | #5899148211600 1676 | b10 " 1677 | #5899157710992 1678 | 0# 1679 | #5899158669264 1680 | 1# 1681 | #5899161710736 1682 | b11 " 1683 | #5899171210128 1684 | 0# 1685 | #5899172522544 1686 | 1# 1687 | #5899182209424 1688 | b100 " 1689 | #5899191708816 1690 | 0# 1691 | #5899192667088 1692 | 1# 1693 | #5899195708560 1694 | b101 " 1695 | #5899205207952 1696 | 0# 1697 | #5899206520368 1698 | 1# 1699 | #5899217540496 1700 | b110 " 1701 | #5899227039888 1702 | 0# 1703 | #5899228518960 1704 | 1# 1705 | #5899236872592 1706 | b111 " 1707 | #5899246371984 1708 | 0# 1709 | b111111 $ 1710 | #5899246517808 1711 | 1# 1712 | #5899256204688 1713 | b1000 " 1714 | #5899265704080 1715 | 0# 1716 | b0 $ 1717 | #5899266516528 1718 | 1# 1719 | #5899275536784 1720 | b1001 " 1721 | #5899285036176 1722 | 0# 1723 | #5899286515248 1724 | 1# 1725 | #5899294868880 1726 | b1010 " 1727 | #5899304368272 1728 | 0# 1729 | #5899304514096 1730 | 1# 1731 | #5899328366736 1732 | b1011 " 1733 | #5899337866128 1734 | 0# 1735 | #5899338511920 1736 | 1# 1737 | #5899341865872 1738 | b1100 " 1739 | #5899351365264 1740 | 0# 1741 | #5899352511024 1742 | 1# 1743 | #5899359364752 1744 | b1101 " 1745 | #5899368864144 1746 | 0# 1747 | #5899370509872 1748 | 1# 1749 | #5899411194768 1750 | b0 " 1751 | #5899420694160 1752 | 0# 1753 | #5899422506544 1754 | 1# 1755 | #5899424693904 1756 | b1 " 1757 | #5899434193296 1758 | 0# 1759 | #5899434505776 1760 | 1# 1761 | #5899445192592 1762 | b10 " 1763 | #5899454691984 1764 | 0# 1765 | #5899456504368 1766 | 1# 1767 | #5899458691728 1768 | b11 " 1769 | #5899468191120 1770 | 0# 1771 | #5899468503600 1772 | 1# 1773 | #5899479190416 1774 | b100 " 1775 | #5899488856464 1776 | 0# 1777 | #5899490502192 1778 | 1# 1779 | #5899492856208 1780 | b101 " 1781 | #5899502355600 1782 | 0# 1783 | #5899502501424 1784 | 1# 1785 | #5899514688144 1786 | b110 " 1787 | #5899524187536 1788 | 0# 1789 | #5899524500016 1790 | 1# 1791 | #5899534020240 1792 | b111 " 1793 | #5899543519632 1794 | 0# 1795 | b111111 $ 1796 | #5899544498736 1797 | 1# 1798 | #5899553352336 1799 | b1000 " 1800 | #5899562851728 1801 | 0# 1802 | b0 $ 1803 | #5899564497456 1804 | 1# 1805 | #5899572684432 1806 | b1001 " 1807 | #5899582183824 1808 | 0# 1809 | #5899582496304 1810 | 1# 1811 | #5899592245680 1812 | b1010 " 1813 | #5899601515920 1814 | 0# 1815 | #5899602495024 1816 | 1# 1817 | #5899625514384 1818 | b1011 " 1819 | #5899635013776 1820 | 0# 1821 | #5899636492848 1822 | 1# 1823 | #5899639013520 1824 | b1100 " 1825 | #5899648512912 1826 | 0# 1827 | #5899650491952 1828 | 1# 1829 | #5899656345744 1830 | b1101 " 1831 | #5899665845136 1832 | 0# 1833 | #5899666490928 1834 | 1# 1835 | #5913316304784 1836 | b1110 " 1837 | #5913324304272 1838 | b1111 " 1839 | #5930210223504 1840 | b1110 " 1841 | #5930218222992 1842 | b1111 " 1843 | #5947100142480 1844 | b1110 " 1845 | #5947108141968 1846 | b1111 " 1847 | #5963997560976 1848 | b1110 " 1849 | #5964005560464 1850 | b1111 " 1851 | #5980889979792 1852 | b1110 " 1853 | #5980897979280 1854 | b1111 " 1855 | #5997785398416 1856 | b1110 " 1857 | #5997793397904 1858 | b1111 " 1859 | #6014679150480 1860 | b1110 " 1861 | #6014687149968 1862 | b1111 " 1863 | #6031576568976 1864 | b1110 " 1865 | #6031584568464 1866 | b1111 " 1867 | #6048471487632 1868 | b1110 " 1869 | #6048479487120 1870 | b1111 " 1871 | #6065370572688 1872 | b1110 " 1873 | #6065378572176 1874 | b1111 " 1875 | #6082266387120 1876 | b1110 " 1877 | #6082274324112 1878 | b1111 " 1879 | #6083154028224 1880 | -------------------------------------------------------------------------------- /ver/top/gather.f: -------------------------------------------------------------------------------- 1 | test.v 2 | ../../hdl/jt49_noise.v 3 | ../../hdl/jt49.v 4 | ../../hdl/jt49_cen.v 5 | ../../hdl/jt49_exp.v 6 | ../../hdl/jt49_eg.v 7 | ../../hdl/jt49_div.v 8 | -------------------------------------------------------------------------------- /ver/top/go: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog -f gather.f -o sim -s test && ./sim -lxt 4 | -------------------------------------------------------------------------------- /ver/top/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module test; 4 | 5 | reg clk, cen=1'b0, rst_n, restart; 6 | wire [4:0] env; 7 | reg [3:0]ctrl; 8 | 9 | initial begin 10 | clk = 1'b0; 11 | forever clk = #50 ~clk; 12 | end // initial 13 | 14 | reg [1:0] cen_cnt=2'd0; 15 | always @(negedge clk) begin 16 | cen_cnt <= cen_cnt+2'd1; 17 | cen <= cen_cnt==2'd0; 18 | end 19 | 20 | initial begin 21 | rst_n = 1'b0; 22 | #500 23 | rst_n = 1'b1; 24 | end // initial 25 | 26 | reg [7:0] aux; 27 | 28 | always @(posedge clk ) begin 29 | if(~rst_n) begin 30 | {ctrl,aux} <= 12'd0; 31 | restart <= 1'b0; 32 | end else begin 33 | {ctrl,aux} <= {ctrl,aux} + 12'd1; 34 | restart <= aux==8'd0; 35 | end 36 | end 37 | 38 | wire [9:0] sound; 39 | reg [7:0] data_in; 40 | reg [3:0] addr; 41 | reg wr_n; 42 | 43 | reg [11:0] cmd_list [0:127]; 44 | integer cmd_cnt, cmd_wait, cmd_end=127; 45 | 46 | initial begin : cmd_set 47 | integer cnt; 48 | for(cnt=0;cnt